1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "compiler/disassembler.hpp" 29 #include "gc/shared/cardTableModRefBS.hpp" 30 #include "gc/shared/collectedHeap.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 #include "memory/resourceArea.hpp" 33 #include "memory/universe.hpp" 34 #include "oops/klass.inline.hpp" 35 #include "prims/methodHandles.hpp" 36 #include "runtime/biasedLocking.hpp" 37 #include "runtime/interfaceSupport.hpp" 38 #include "runtime/objectMonitor.hpp" 39 #include "runtime/os.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "runtime/stubRoutines.hpp" 42 #include "runtime/thread.hpp" 43 #include "utilities/macros.hpp" 44 #if INCLUDE_ALL_GCS 45 #include "gc/g1/g1CollectedHeap.inline.hpp" 46 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 47 #include "gc/g1/heapRegion.hpp" 48 #endif // INCLUDE_ALL_GCS 49 #include "crc32c.h" 50 #ifdef COMPILER2 51 #include "opto/intrinsicnode.hpp" 52 #endif 53 54 #ifdef PRODUCT 55 #define BLOCK_COMMENT(str) /* nothing */ 56 #define STOP(error) stop(error) 57 #else 58 #define BLOCK_COMMENT(str) block_comment(str) 59 #define STOP(error) block_comment(error); stop(error) 60 #endif 61 62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 63 64 #ifdef ASSERT 65 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 66 #endif 67 68 static Assembler::Condition reverse[] = { 69 Assembler::noOverflow /* overflow = 0x0 */ , 70 Assembler::overflow /* noOverflow = 0x1 */ , 71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 75 Assembler::above /* belowEqual = 0x6 */ , 76 Assembler::belowEqual /* above = 0x7 */ , 77 Assembler::positive /* negative = 0x8 */ , 78 Assembler::negative /* positive = 0x9 */ , 79 Assembler::noParity /* parity = 0xa */ , 80 Assembler::parity /* noParity = 0xb */ , 81 Assembler::greaterEqual /* less = 0xc */ , 82 Assembler::less /* greaterEqual = 0xd */ , 83 Assembler::greater /* lessEqual = 0xe */ , 84 Assembler::lessEqual /* greater = 0xf, */ 85 86 }; 87 88 89 // Implementation of MacroAssembler 90 91 // First all the versions that have distinct versions depending on 32/64 bit 92 // Unless the difference is trivial (1 line or so). 93 94 #ifndef _LP64 95 96 // 32bit versions 97 98 Address MacroAssembler::as_Address(AddressLiteral adr) { 99 return Address(adr.target(), adr.rspec()); 100 } 101 102 Address MacroAssembler::as_Address(ArrayAddress adr) { 103 return Address::make_array(adr); 104 } 105 106 void MacroAssembler::call_VM_leaf_base(address entry_point, 107 int number_of_arguments) { 108 call(RuntimeAddress(entry_point)); 109 increment(rsp, number_of_arguments * wordSize); 110 } 111 112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 114 } 115 116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 118 } 119 120 void MacroAssembler::cmpoop(Address src1, jobject obj) { 121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 122 } 123 124 void MacroAssembler::cmpoop(Register src1, jobject obj) { 125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 126 } 127 128 void MacroAssembler::extend_sign(Register hi, Register lo) { 129 // According to Intel Doc. AP-526, "Integer Divide", p.18. 130 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 131 cdql(); 132 } else { 133 movl(hi, lo); 134 sarl(hi, 31); 135 } 136 } 137 138 void MacroAssembler::jC2(Register tmp, Label& L) { 139 // set parity bit if FPU flag C2 is set (via rax) 140 save_rax(tmp); 141 fwait(); fnstsw_ax(); 142 sahf(); 143 restore_rax(tmp); 144 // branch 145 jcc(Assembler::parity, L); 146 } 147 148 void MacroAssembler::jnC2(Register tmp, Label& L) { 149 // set parity bit if FPU flag C2 is set (via rax) 150 save_rax(tmp); 151 fwait(); fnstsw_ax(); 152 sahf(); 153 restore_rax(tmp); 154 // branch 155 jcc(Assembler::noParity, L); 156 } 157 158 // 32bit can do a case table jump in one instruction but we no longer allow the base 159 // to be installed in the Address class 160 void MacroAssembler::jump(ArrayAddress entry) { 161 jmp(as_Address(entry)); 162 } 163 164 // Note: y_lo will be destroyed 165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 166 // Long compare for Java (semantics as described in JVM spec.) 167 Label high, low, done; 168 169 cmpl(x_hi, y_hi); 170 jcc(Assembler::less, low); 171 jcc(Assembler::greater, high); 172 // x_hi is the return register 173 xorl(x_hi, x_hi); 174 cmpl(x_lo, y_lo); 175 jcc(Assembler::below, low); 176 jcc(Assembler::equal, done); 177 178 bind(high); 179 xorl(x_hi, x_hi); 180 increment(x_hi); 181 jmp(done); 182 183 bind(low); 184 xorl(x_hi, x_hi); 185 decrementl(x_hi); 186 187 bind(done); 188 } 189 190 void MacroAssembler::lea(Register dst, AddressLiteral src) { 191 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 192 } 193 194 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 195 // leal(dst, as_Address(adr)); 196 // see note in movl as to why we must use a move 197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 198 } 199 200 void MacroAssembler::leave() { 201 mov(rsp, rbp); 202 pop(rbp); 203 } 204 205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 206 // Multiplication of two Java long values stored on the stack 207 // as illustrated below. Result is in rdx:rax. 208 // 209 // rsp ---> [ ?? ] \ \ 210 // .... | y_rsp_offset | 211 // [ y_lo ] / (in bytes) | x_rsp_offset 212 // [ y_hi ] | (in bytes) 213 // .... | 214 // [ x_lo ] / 215 // [ x_hi ] 216 // .... 217 // 218 // Basic idea: lo(result) = lo(x_lo * y_lo) 219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 222 Label quick; 223 // load x_hi, y_hi and check if quick 224 // multiplication is possible 225 movl(rbx, x_hi); 226 movl(rcx, y_hi); 227 movl(rax, rbx); 228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 230 // do full multiplication 231 // 1st step 232 mull(y_lo); // x_hi * y_lo 233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 234 // 2nd step 235 movl(rax, x_lo); 236 mull(rcx); // x_lo * y_hi 237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 238 // 3rd step 239 bind(quick); // note: rbx, = 0 if quick multiply! 240 movl(rax, x_lo); 241 mull(y_lo); // x_lo * y_lo 242 addl(rdx, rbx); // correct hi(x_lo * y_lo) 243 } 244 245 void MacroAssembler::lneg(Register hi, Register lo) { 246 negl(lo); 247 adcl(hi, 0); 248 negl(hi); 249 } 250 251 void MacroAssembler::lshl(Register hi, Register lo) { 252 // Java shift left long support (semantics as described in JVM spec., p.305) 253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 254 // shift value is in rcx ! 255 assert(hi != rcx, "must not use rcx"); 256 assert(lo != rcx, "must not use rcx"); 257 const Register s = rcx; // shift count 258 const int n = BitsPerWord; 259 Label L; 260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 261 cmpl(s, n); // if (s < n) 262 jcc(Assembler::less, L); // else (s >= n) 263 movl(hi, lo); // x := x << n 264 xorl(lo, lo); 265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 266 bind(L); // s (mod n) < n 267 shldl(hi, lo); // x := x << s 268 shll(lo); 269 } 270 271 272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 275 assert(hi != rcx, "must not use rcx"); 276 assert(lo != rcx, "must not use rcx"); 277 const Register s = rcx; // shift count 278 const int n = BitsPerWord; 279 Label L; 280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 281 cmpl(s, n); // if (s < n) 282 jcc(Assembler::less, L); // else (s >= n) 283 movl(lo, hi); // x := x >> n 284 if (sign_extension) sarl(hi, 31); 285 else xorl(hi, hi); 286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 287 bind(L); // s (mod n) < n 288 shrdl(lo, hi); // x := x >> s 289 if (sign_extension) sarl(hi); 290 else shrl(hi); 291 } 292 293 void MacroAssembler::movoop(Register dst, jobject obj) { 294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 295 } 296 297 void MacroAssembler::movoop(Address dst, jobject obj) { 298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 299 } 300 301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 303 } 304 305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 307 } 308 309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 310 // scratch register is not used, 311 // it is defined to match parameters of 64-bit version of this method. 312 if (src.is_lval()) { 313 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 314 } else { 315 movl(dst, as_Address(src)); 316 } 317 } 318 319 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 320 movl(as_Address(dst), src); 321 } 322 323 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 324 movl(dst, as_Address(src)); 325 } 326 327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 328 void MacroAssembler::movptr(Address dst, intptr_t src) { 329 movl(dst, src); 330 } 331 332 333 void MacroAssembler::pop_callee_saved_registers() { 334 pop(rcx); 335 pop(rdx); 336 pop(rdi); 337 pop(rsi); 338 } 339 340 void MacroAssembler::pop_fTOS() { 341 fld_d(Address(rsp, 0)); 342 addl(rsp, 2 * wordSize); 343 } 344 345 void MacroAssembler::push_callee_saved_registers() { 346 push(rsi); 347 push(rdi); 348 push(rdx); 349 push(rcx); 350 } 351 352 void MacroAssembler::push_fTOS() { 353 subl(rsp, 2 * wordSize); 354 fstp_d(Address(rsp, 0)); 355 } 356 357 358 void MacroAssembler::pushoop(jobject obj) { 359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 360 } 361 362 void MacroAssembler::pushklass(Metadata* obj) { 363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 364 } 365 366 void MacroAssembler::pushptr(AddressLiteral src) { 367 if (src.is_lval()) { 368 push_literal32((int32_t)src.target(), src.rspec()); 369 } else { 370 pushl(as_Address(src)); 371 } 372 } 373 374 void MacroAssembler::set_word_if_not_zero(Register dst) { 375 xorl(dst, dst); 376 set_byte_if_not_zero(dst); 377 } 378 379 static void pass_arg0(MacroAssembler* masm, Register arg) { 380 masm->push(arg); 381 } 382 383 static void pass_arg1(MacroAssembler* masm, Register arg) { 384 masm->push(arg); 385 } 386 387 static void pass_arg2(MacroAssembler* masm, Register arg) { 388 masm->push(arg); 389 } 390 391 static void pass_arg3(MacroAssembler* masm, Register arg) { 392 masm->push(arg); 393 } 394 395 #ifndef PRODUCT 396 extern "C" void findpc(intptr_t x); 397 #endif 398 399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 400 // In order to get locks to work, we need to fake a in_VM state 401 JavaThread* thread = JavaThread::current(); 402 JavaThreadState saved_state = thread->thread_state(); 403 thread->set_thread_state(_thread_in_vm); 404 if (ShowMessageBoxOnError) { 405 JavaThread* thread = JavaThread::current(); 406 JavaThreadState saved_state = thread->thread_state(); 407 thread->set_thread_state(_thread_in_vm); 408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 409 ttyLocker ttyl; 410 BytecodeCounter::print(); 411 } 412 // To see where a verify_oop failed, get $ebx+40/X for this frame. 413 // This is the value of eip which points to where verify_oop will return. 414 if (os::message_box(msg, "Execution stopped, print registers?")) { 415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 416 BREAKPOINT; 417 } 418 } else { 419 ttyLocker ttyl; 420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 421 } 422 // Don't assert holding the ttyLock 423 assert(false, "DEBUG MESSAGE: %s", msg); 424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 425 } 426 427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 428 ttyLocker ttyl; 429 FlagSetting fs(Debugging, true); 430 tty->print_cr("eip = 0x%08x", eip); 431 #ifndef PRODUCT 432 if ((WizardMode || Verbose) && PrintMiscellaneous) { 433 tty->cr(); 434 findpc(eip); 435 tty->cr(); 436 } 437 #endif 438 #define PRINT_REG(rax) \ 439 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 440 PRINT_REG(rax); 441 PRINT_REG(rbx); 442 PRINT_REG(rcx); 443 PRINT_REG(rdx); 444 PRINT_REG(rdi); 445 PRINT_REG(rsi); 446 PRINT_REG(rbp); 447 PRINT_REG(rsp); 448 #undef PRINT_REG 449 // Print some words near top of staack. 450 int* dump_sp = (int*) rsp; 451 for (int col1 = 0; col1 < 8; col1++) { 452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 453 os::print_location(tty, *dump_sp++); 454 } 455 for (int row = 0; row < 16; row++) { 456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 457 for (int col = 0; col < 8; col++) { 458 tty->print(" 0x%08x", *dump_sp++); 459 } 460 tty->cr(); 461 } 462 // Print some instructions around pc: 463 Disassembler::decode((address)eip-64, (address)eip); 464 tty->print_cr("--------"); 465 Disassembler::decode((address)eip, (address)eip+32); 466 } 467 468 void MacroAssembler::stop(const char* msg) { 469 ExternalAddress message((address)msg); 470 // push address of message 471 pushptr(message.addr()); 472 { Label L; call(L, relocInfo::none); bind(L); } // push eip 473 pusha(); // push registers 474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 475 hlt(); 476 } 477 478 void MacroAssembler::warn(const char* msg) { 479 push_CPU_state(); 480 481 ExternalAddress message((address) msg); 482 // push address of message 483 pushptr(message.addr()); 484 485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 486 addl(rsp, wordSize); // discard argument 487 pop_CPU_state(); 488 } 489 490 void MacroAssembler::print_state() { 491 { Label L; call(L, relocInfo::none); bind(L); } // push eip 492 pusha(); // push registers 493 494 push_CPU_state(); 495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 496 pop_CPU_state(); 497 498 popa(); 499 addl(rsp, wordSize); 500 } 501 502 #else // _LP64 503 504 // 64 bit versions 505 506 Address MacroAssembler::as_Address(AddressLiteral adr) { 507 // amd64 always does this as a pc-rel 508 // we can be absolute or disp based on the instruction type 509 // jmp/call are displacements others are absolute 510 assert(!adr.is_lval(), "must be rval"); 511 assert(reachable(adr), "must be"); 512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 513 514 } 515 516 Address MacroAssembler::as_Address(ArrayAddress adr) { 517 AddressLiteral base = adr.base(); 518 lea(rscratch1, base); 519 Address index = adr.index(); 520 assert(index._disp == 0, "must not have disp"); // maybe it can? 521 Address array(rscratch1, index._index, index._scale, index._disp); 522 return array; 523 } 524 525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 526 Label L, E; 527 528 #ifdef _WIN64 529 // Windows always allocates space for it's register args 530 assert(num_args <= 4, "only register arguments supported"); 531 subq(rsp, frame::arg_reg_save_area_bytes); 532 #endif 533 534 // Align stack if necessary 535 testl(rsp, 15); 536 jcc(Assembler::zero, L); 537 538 subq(rsp, 8); 539 { 540 call(RuntimeAddress(entry_point)); 541 } 542 addq(rsp, 8); 543 jmp(E); 544 545 bind(L); 546 { 547 call(RuntimeAddress(entry_point)); 548 } 549 550 bind(E); 551 552 #ifdef _WIN64 553 // restore stack pointer 554 addq(rsp, frame::arg_reg_save_area_bytes); 555 #endif 556 557 } 558 559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 560 assert(!src2.is_lval(), "should use cmpptr"); 561 562 if (reachable(src2)) { 563 cmpq(src1, as_Address(src2)); 564 } else { 565 lea(rscratch1, src2); 566 Assembler::cmpq(src1, Address(rscratch1, 0)); 567 } 568 } 569 570 int MacroAssembler::corrected_idivq(Register reg) { 571 // Full implementation of Java ldiv and lrem; checks for special 572 // case as described in JVM spec., p.243 & p.271. The function 573 // returns the (pc) offset of the idivl instruction - may be needed 574 // for implicit exceptions. 575 // 576 // normal case special case 577 // 578 // input : rax: dividend min_long 579 // reg: divisor (may not be eax/edx) -1 580 // 581 // output: rax: quotient (= rax idiv reg) min_long 582 // rdx: remainder (= rax irem reg) 0 583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 584 static const int64_t min_long = 0x8000000000000000; 585 Label normal_case, special_case; 586 587 // check for special case 588 cmp64(rax, ExternalAddress((address) &min_long)); 589 jcc(Assembler::notEqual, normal_case); 590 xorl(rdx, rdx); // prepare rdx for possible special case (where 591 // remainder = 0) 592 cmpq(reg, -1); 593 jcc(Assembler::equal, special_case); 594 595 // handle normal case 596 bind(normal_case); 597 cdqq(); 598 int idivq_offset = offset(); 599 idivq(reg); 600 601 // normal and special case exit 602 bind(special_case); 603 604 return idivq_offset; 605 } 606 607 void MacroAssembler::decrementq(Register reg, int value) { 608 if (value == min_jint) { subq(reg, value); return; } 609 if (value < 0) { incrementq(reg, -value); return; } 610 if (value == 0) { ; return; } 611 if (value == 1 && UseIncDec) { decq(reg) ; return; } 612 /* else */ { subq(reg, value) ; return; } 613 } 614 615 void MacroAssembler::decrementq(Address dst, int value) { 616 if (value == min_jint) { subq(dst, value); return; } 617 if (value < 0) { incrementq(dst, -value); return; } 618 if (value == 0) { ; return; } 619 if (value == 1 && UseIncDec) { decq(dst) ; return; } 620 /* else */ { subq(dst, value) ; return; } 621 } 622 623 void MacroAssembler::incrementq(AddressLiteral dst) { 624 if (reachable(dst)) { 625 incrementq(as_Address(dst)); 626 } else { 627 lea(rscratch1, dst); 628 incrementq(Address(rscratch1, 0)); 629 } 630 } 631 632 void MacroAssembler::incrementq(Register reg, int value) { 633 if (value == min_jint) { addq(reg, value); return; } 634 if (value < 0) { decrementq(reg, -value); return; } 635 if (value == 0) { ; return; } 636 if (value == 1 && UseIncDec) { incq(reg) ; return; } 637 /* else */ { addq(reg, value) ; return; } 638 } 639 640 void MacroAssembler::incrementq(Address dst, int value) { 641 if (value == min_jint) { addq(dst, value); return; } 642 if (value < 0) { decrementq(dst, -value); return; } 643 if (value == 0) { ; return; } 644 if (value == 1 && UseIncDec) { incq(dst) ; return; } 645 /* else */ { addq(dst, value) ; return; } 646 } 647 648 // 32bit can do a case table jump in one instruction but we no longer allow the base 649 // to be installed in the Address class 650 void MacroAssembler::jump(ArrayAddress entry) { 651 lea(rscratch1, entry.base()); 652 Address dispatch = entry.index(); 653 assert(dispatch._base == noreg, "must be"); 654 dispatch._base = rscratch1; 655 jmp(dispatch); 656 } 657 658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 659 ShouldNotReachHere(); // 64bit doesn't use two regs 660 cmpq(x_lo, y_lo); 661 } 662 663 void MacroAssembler::lea(Register dst, AddressLiteral src) { 664 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 665 } 666 667 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 669 movptr(dst, rscratch1); 670 } 671 672 void MacroAssembler::leave() { 673 // %%% is this really better? Why not on 32bit too? 674 emit_int8((unsigned char)0xC9); // LEAVE 675 } 676 677 void MacroAssembler::lneg(Register hi, Register lo) { 678 ShouldNotReachHere(); // 64bit doesn't use two regs 679 negq(lo); 680 } 681 682 void MacroAssembler::movoop(Register dst, jobject obj) { 683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 684 } 685 686 void MacroAssembler::movoop(Address dst, jobject obj) { 687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 688 movq(dst, rscratch1); 689 } 690 691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 693 } 694 695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 697 movq(dst, rscratch1); 698 } 699 700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 701 if (src.is_lval()) { 702 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 703 } else { 704 if (reachable(src)) { 705 movq(dst, as_Address(src)); 706 } else { 707 lea(scratch, src); 708 movq(dst, Address(scratch, 0)); 709 } 710 } 711 } 712 713 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 714 movq(as_Address(dst), src); 715 } 716 717 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 718 movq(dst, as_Address(src)); 719 } 720 721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 722 void MacroAssembler::movptr(Address dst, intptr_t src) { 723 mov64(rscratch1, src); 724 movq(dst, rscratch1); 725 } 726 727 // These are mostly for initializing NULL 728 void MacroAssembler::movptr(Address dst, int32_t src) { 729 movslq(dst, src); 730 } 731 732 void MacroAssembler::movptr(Register dst, int32_t src) { 733 mov64(dst, (intptr_t)src); 734 } 735 736 void MacroAssembler::pushoop(jobject obj) { 737 movoop(rscratch1, obj); 738 push(rscratch1); 739 } 740 741 void MacroAssembler::pushklass(Metadata* obj) { 742 mov_metadata(rscratch1, obj); 743 push(rscratch1); 744 } 745 746 void MacroAssembler::pushptr(AddressLiteral src) { 747 lea(rscratch1, src); 748 if (src.is_lval()) { 749 push(rscratch1); 750 } else { 751 pushq(Address(rscratch1, 0)); 752 } 753 } 754 755 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 756 // we must set sp to zero to clear frame 757 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 758 // must clear fp, so that compiled frames are not confused; it is 759 // possible that we need it only for debugging 760 if (clear_fp) { 761 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 762 } 763 764 // Always clear the pc because it could have been set by make_walkable() 765 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 766 } 767 768 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 769 Register last_java_fp, 770 address last_java_pc) { 771 // determine last_java_sp register 772 if (!last_java_sp->is_valid()) { 773 last_java_sp = rsp; 774 } 775 776 // last_java_fp is optional 777 if (last_java_fp->is_valid()) { 778 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 779 last_java_fp); 780 } 781 782 // last_java_pc is optional 783 if (last_java_pc != NULL) { 784 Address java_pc(r15_thread, 785 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 786 lea(rscratch1, InternalAddress(last_java_pc)); 787 movptr(java_pc, rscratch1); 788 } 789 790 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 791 } 792 793 static void pass_arg0(MacroAssembler* masm, Register arg) { 794 if (c_rarg0 != arg ) { 795 masm->mov(c_rarg0, arg); 796 } 797 } 798 799 static void pass_arg1(MacroAssembler* masm, Register arg) { 800 if (c_rarg1 != arg ) { 801 masm->mov(c_rarg1, arg); 802 } 803 } 804 805 static void pass_arg2(MacroAssembler* masm, Register arg) { 806 if (c_rarg2 != arg ) { 807 masm->mov(c_rarg2, arg); 808 } 809 } 810 811 static void pass_arg3(MacroAssembler* masm, Register arg) { 812 if (c_rarg3 != arg ) { 813 masm->mov(c_rarg3, arg); 814 } 815 } 816 817 void MacroAssembler::stop(const char* msg) { 818 address rip = pc(); 819 pusha(); // get regs on stack 820 lea(c_rarg0, ExternalAddress((address) msg)); 821 lea(c_rarg1, InternalAddress(rip)); 822 movq(c_rarg2, rsp); // pass pointer to regs array 823 andq(rsp, -16); // align stack as required by ABI 824 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 825 hlt(); 826 } 827 828 void MacroAssembler::warn(const char* msg) { 829 push(rbp); 830 movq(rbp, rsp); 831 andq(rsp, -16); // align stack as required by push_CPU_state and call 832 push_CPU_state(); // keeps alignment at 16 bytes 833 lea(c_rarg0, ExternalAddress((address) msg)); 834 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 835 pop_CPU_state(); 836 mov(rsp, rbp); 837 pop(rbp); 838 } 839 840 void MacroAssembler::print_state() { 841 address rip = pc(); 842 pusha(); // get regs on stack 843 push(rbp); 844 movq(rbp, rsp); 845 andq(rsp, -16); // align stack as required by push_CPU_state and call 846 push_CPU_state(); // keeps alignment at 16 bytes 847 848 lea(c_rarg0, InternalAddress(rip)); 849 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 850 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 851 852 pop_CPU_state(); 853 mov(rsp, rbp); 854 pop(rbp); 855 popa(); 856 } 857 858 #ifndef PRODUCT 859 extern "C" void findpc(intptr_t x); 860 #endif 861 862 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 863 // In order to get locks to work, we need to fake a in_VM state 864 if (ShowMessageBoxOnError) { 865 JavaThread* thread = JavaThread::current(); 866 JavaThreadState saved_state = thread->thread_state(); 867 thread->set_thread_state(_thread_in_vm); 868 #ifndef PRODUCT 869 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 870 ttyLocker ttyl; 871 BytecodeCounter::print(); 872 } 873 #endif 874 // To see where a verify_oop failed, get $ebx+40/X for this frame. 875 // XXX correct this offset for amd64 876 // This is the value of eip which points to where verify_oop will return. 877 if (os::message_box(msg, "Execution stopped, print registers?")) { 878 print_state64(pc, regs); 879 BREAKPOINT; 880 assert(false, "start up GDB"); 881 } 882 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 883 } else { 884 ttyLocker ttyl; 885 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 886 msg); 887 assert(false, "DEBUG MESSAGE: %s", msg); 888 } 889 } 890 891 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 892 ttyLocker ttyl; 893 FlagSetting fs(Debugging, true); 894 tty->print_cr("rip = 0x%016lx", pc); 895 #ifndef PRODUCT 896 tty->cr(); 897 findpc(pc); 898 tty->cr(); 899 #endif 900 #define PRINT_REG(rax, value) \ 901 { tty->print("%s = ", #rax); os::print_location(tty, value); } 902 PRINT_REG(rax, regs[15]); 903 PRINT_REG(rbx, regs[12]); 904 PRINT_REG(rcx, regs[14]); 905 PRINT_REG(rdx, regs[13]); 906 PRINT_REG(rdi, regs[8]); 907 PRINT_REG(rsi, regs[9]); 908 PRINT_REG(rbp, regs[10]); 909 PRINT_REG(rsp, regs[11]); 910 PRINT_REG(r8 , regs[7]); 911 PRINT_REG(r9 , regs[6]); 912 PRINT_REG(r10, regs[5]); 913 PRINT_REG(r11, regs[4]); 914 PRINT_REG(r12, regs[3]); 915 PRINT_REG(r13, regs[2]); 916 PRINT_REG(r14, regs[1]); 917 PRINT_REG(r15, regs[0]); 918 #undef PRINT_REG 919 // Print some words near top of staack. 920 int64_t* rsp = (int64_t*) regs[11]; 921 int64_t* dump_sp = rsp; 922 for (int col1 = 0; col1 < 8; col1++) { 923 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 924 os::print_location(tty, *dump_sp++); 925 } 926 for (int row = 0; row < 25; row++) { 927 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 928 for (int col = 0; col < 4; col++) { 929 tty->print(" 0x%016lx", *dump_sp++); 930 } 931 tty->cr(); 932 } 933 // Print some instructions around pc: 934 Disassembler::decode((address)pc-64, (address)pc); 935 tty->print_cr("--------"); 936 Disassembler::decode((address)pc, (address)pc+32); 937 } 938 939 #endif // _LP64 940 941 // Now versions that are common to 32/64 bit 942 943 void MacroAssembler::addptr(Register dst, int32_t imm32) { 944 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 945 } 946 947 void MacroAssembler::addptr(Register dst, Register src) { 948 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 949 } 950 951 void MacroAssembler::addptr(Address dst, Register src) { 952 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 953 } 954 955 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 956 if (reachable(src)) { 957 Assembler::addsd(dst, as_Address(src)); 958 } else { 959 lea(rscratch1, src); 960 Assembler::addsd(dst, Address(rscratch1, 0)); 961 } 962 } 963 964 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 965 if (reachable(src)) { 966 addss(dst, as_Address(src)); 967 } else { 968 lea(rscratch1, src); 969 addss(dst, Address(rscratch1, 0)); 970 } 971 } 972 973 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) { 974 if (reachable(src)) { 975 Assembler::addpd(dst, as_Address(src)); 976 } else { 977 lea(rscratch1, src); 978 Assembler::addpd(dst, Address(rscratch1, 0)); 979 } 980 } 981 982 void MacroAssembler::align(int modulus) { 983 align(modulus, offset()); 984 } 985 986 void MacroAssembler::align(int modulus, int target) { 987 if (target % modulus != 0) { 988 nop(modulus - (target % modulus)); 989 } 990 } 991 992 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 993 // Used in sign-masking with aligned address. 994 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 995 if (reachable(src)) { 996 Assembler::andpd(dst, as_Address(src)); 997 } else { 998 lea(rscratch1, src); 999 Assembler::andpd(dst, Address(rscratch1, 0)); 1000 } 1001 } 1002 1003 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 1004 // Used in sign-masking with aligned address. 1005 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1006 if (reachable(src)) { 1007 Assembler::andps(dst, as_Address(src)); 1008 } else { 1009 lea(rscratch1, src); 1010 Assembler::andps(dst, Address(rscratch1, 0)); 1011 } 1012 } 1013 1014 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1015 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1016 } 1017 1018 void MacroAssembler::atomic_incl(Address counter_addr) { 1019 if (os::is_MP()) 1020 lock(); 1021 incrementl(counter_addr); 1022 } 1023 1024 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1025 if (reachable(counter_addr)) { 1026 atomic_incl(as_Address(counter_addr)); 1027 } else { 1028 lea(scr, counter_addr); 1029 atomic_incl(Address(scr, 0)); 1030 } 1031 } 1032 1033 #ifdef _LP64 1034 void MacroAssembler::atomic_incq(Address counter_addr) { 1035 if (os::is_MP()) 1036 lock(); 1037 incrementq(counter_addr); 1038 } 1039 1040 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1041 if (reachable(counter_addr)) { 1042 atomic_incq(as_Address(counter_addr)); 1043 } else { 1044 lea(scr, counter_addr); 1045 atomic_incq(Address(scr, 0)); 1046 } 1047 } 1048 #endif 1049 1050 // Writes to stack successive pages until offset reached to check for 1051 // stack overflow + shadow pages. This clobbers tmp. 1052 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1053 movptr(tmp, rsp); 1054 // Bang stack for total size given plus shadow page size. 1055 // Bang one page at a time because large size can bang beyond yellow and 1056 // red zones. 1057 Label loop; 1058 bind(loop); 1059 movl(Address(tmp, (-os::vm_page_size())), size ); 1060 subptr(tmp, os::vm_page_size()); 1061 subl(size, os::vm_page_size()); 1062 jcc(Assembler::greater, loop); 1063 1064 // Bang down shadow pages too. 1065 // At this point, (tmp-0) is the last address touched, so don't 1066 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1067 // was post-decremented.) Skip this address by starting at i=1, and 1068 // touch a few more pages below. N.B. It is important to touch all 1069 // the way down including all pages in the shadow zone. 1070 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) { 1071 // this could be any sized move but this is can be a debugging crumb 1072 // so the bigger the better. 1073 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1074 } 1075 } 1076 1077 void MacroAssembler::reserved_stack_check() { 1078 // testing if reserved zone needs to be enabled 1079 Label no_reserved_zone_enabling; 1080 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1081 NOT_LP64(get_thread(rsi);) 1082 1083 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1084 jcc(Assembler::below, no_reserved_zone_enabling); 1085 1086 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1087 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1088 should_not_reach_here(); 1089 1090 bind(no_reserved_zone_enabling); 1091 } 1092 1093 int MacroAssembler::biased_locking_enter(Register lock_reg, 1094 Register obj_reg, 1095 Register swap_reg, 1096 Register tmp_reg, 1097 bool swap_reg_contains_mark, 1098 Label& done, 1099 Label* slow_case, 1100 BiasedLockingCounters* counters) { 1101 assert(UseBiasedLocking, "why call this otherwise?"); 1102 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1103 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1104 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1105 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1106 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1107 NOT_LP64( Address saved_mark_addr(lock_reg, 0); ) 1108 1109 if (PrintBiasedLockingStatistics && counters == NULL) { 1110 counters = BiasedLocking::counters(); 1111 } 1112 // Biased locking 1113 // See whether the lock is currently biased toward our thread and 1114 // whether the epoch is still valid 1115 // Note that the runtime guarantees sufficient alignment of JavaThread 1116 // pointers to allow age to be placed into low bits 1117 // First check to see whether biasing is even enabled for this object 1118 Label cas_label; 1119 int null_check_offset = -1; 1120 if (!swap_reg_contains_mark) { 1121 null_check_offset = offset(); 1122 movptr(swap_reg, mark_addr); 1123 } 1124 movptr(tmp_reg, swap_reg); 1125 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1126 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1127 jcc(Assembler::notEqual, cas_label); 1128 // The bias pattern is present in the object's header. Need to check 1129 // whether the bias owner and the epoch are both still current. 1130 #ifndef _LP64 1131 // Note that because there is no current thread register on x86_32 we 1132 // need to store off the mark word we read out of the object to 1133 // avoid reloading it and needing to recheck invariants below. This 1134 // store is unfortunate but it makes the overall code shorter and 1135 // simpler. 1136 movptr(saved_mark_addr, swap_reg); 1137 #endif 1138 if (swap_reg_contains_mark) { 1139 null_check_offset = offset(); 1140 } 1141 load_prototype_header(tmp_reg, obj_reg); 1142 #ifdef _LP64 1143 orptr(tmp_reg, r15_thread); 1144 xorptr(tmp_reg, swap_reg); 1145 Register header_reg = tmp_reg; 1146 #else 1147 xorptr(tmp_reg, swap_reg); 1148 get_thread(swap_reg); 1149 xorptr(swap_reg, tmp_reg); 1150 Register header_reg = swap_reg; 1151 #endif 1152 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1153 if (counters != NULL) { 1154 cond_inc32(Assembler::zero, 1155 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1156 } 1157 jcc(Assembler::equal, done); 1158 1159 Label try_revoke_bias; 1160 Label try_rebias; 1161 1162 // At this point we know that the header has the bias pattern and 1163 // that we are not the bias owner in the current epoch. We need to 1164 // figure out more details about the state of the header in order to 1165 // know what operations can be legally performed on the object's 1166 // header. 1167 1168 // If the low three bits in the xor result aren't clear, that means 1169 // the prototype header is no longer biased and we have to revoke 1170 // the bias on this object. 1171 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1172 jccb(Assembler::notZero, try_revoke_bias); 1173 1174 // Biasing is still enabled for this data type. See whether the 1175 // epoch of the current bias is still valid, meaning that the epoch 1176 // bits of the mark word are equal to the epoch bits of the 1177 // prototype header. (Note that the prototype header's epoch bits 1178 // only change at a safepoint.) If not, attempt to rebias the object 1179 // toward the current thread. Note that we must be absolutely sure 1180 // that the current epoch is invalid in order to do this because 1181 // otherwise the manipulations it performs on the mark word are 1182 // illegal. 1183 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1184 jccb(Assembler::notZero, try_rebias); 1185 1186 // The epoch of the current bias is still valid but we know nothing 1187 // about the owner; it might be set or it might be clear. Try to 1188 // acquire the bias of the object using an atomic operation. If this 1189 // fails we will go in to the runtime to revoke the object's bias. 1190 // Note that we first construct the presumed unbiased header so we 1191 // don't accidentally blow away another thread's valid bias. 1192 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1193 andptr(swap_reg, 1194 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1195 #ifdef _LP64 1196 movptr(tmp_reg, swap_reg); 1197 orptr(tmp_reg, r15_thread); 1198 #else 1199 get_thread(tmp_reg); 1200 orptr(tmp_reg, swap_reg); 1201 #endif 1202 if (os::is_MP()) { 1203 lock(); 1204 } 1205 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1206 // If the biasing toward our thread failed, this means that 1207 // another thread succeeded in biasing it toward itself and we 1208 // need to revoke that bias. The revocation will occur in the 1209 // interpreter runtime in the slow case. 1210 if (counters != NULL) { 1211 cond_inc32(Assembler::zero, 1212 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1213 } 1214 if (slow_case != NULL) { 1215 jcc(Assembler::notZero, *slow_case); 1216 } 1217 jmp(done); 1218 1219 bind(try_rebias); 1220 // At this point we know the epoch has expired, meaning that the 1221 // current "bias owner", if any, is actually invalid. Under these 1222 // circumstances _only_, we are allowed to use the current header's 1223 // value as the comparison value when doing the cas to acquire the 1224 // bias in the current epoch. In other words, we allow transfer of 1225 // the bias from one thread to another directly in this situation. 1226 // 1227 // FIXME: due to a lack of registers we currently blow away the age 1228 // bits in this situation. Should attempt to preserve them. 1229 load_prototype_header(tmp_reg, obj_reg); 1230 #ifdef _LP64 1231 orptr(tmp_reg, r15_thread); 1232 #else 1233 get_thread(swap_reg); 1234 orptr(tmp_reg, swap_reg); 1235 movptr(swap_reg, saved_mark_addr); 1236 #endif 1237 if (os::is_MP()) { 1238 lock(); 1239 } 1240 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1241 // If the biasing toward our thread failed, then another thread 1242 // succeeded in biasing it toward itself and we need to revoke that 1243 // bias. The revocation will occur in the runtime in the slow case. 1244 if (counters != NULL) { 1245 cond_inc32(Assembler::zero, 1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1247 } 1248 if (slow_case != NULL) { 1249 jcc(Assembler::notZero, *slow_case); 1250 } 1251 jmp(done); 1252 1253 bind(try_revoke_bias); 1254 // The prototype mark in the klass doesn't have the bias bit set any 1255 // more, indicating that objects of this data type are not supposed 1256 // to be biased any more. We are going to try to reset the mark of 1257 // this object to the prototype value and fall through to the 1258 // CAS-based locking scheme. Note that if our CAS fails, it means 1259 // that another thread raced us for the privilege of revoking the 1260 // bias of this particular object, so it's okay to continue in the 1261 // normal locking code. 1262 // 1263 // FIXME: due to a lack of registers we currently blow away the age 1264 // bits in this situation. Should attempt to preserve them. 1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1266 load_prototype_header(tmp_reg, obj_reg); 1267 if (os::is_MP()) { 1268 lock(); 1269 } 1270 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1271 // Fall through to the normal CAS-based lock, because no matter what 1272 // the result of the above CAS, some thread must have succeeded in 1273 // removing the bias bit from the object's header. 1274 if (counters != NULL) { 1275 cond_inc32(Assembler::zero, 1276 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1277 } 1278 1279 bind(cas_label); 1280 1281 return null_check_offset; 1282 } 1283 1284 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1285 assert(UseBiasedLocking, "why call this otherwise?"); 1286 1287 // Check for biased locking unlock case, which is a no-op 1288 // Note: we do not have to check the thread ID for two reasons. 1289 // First, the interpreter checks for IllegalMonitorStateException at 1290 // a higher level. Second, if the bias was revoked while we held the 1291 // lock, the object could not be rebiased toward another thread, so 1292 // the bias bit would be clear. 1293 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1294 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1295 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1296 jcc(Assembler::equal, done); 1297 } 1298 1299 #ifdef COMPILER2 1300 1301 #if INCLUDE_RTM_OPT 1302 1303 // Update rtm_counters based on abort status 1304 // input: abort_status 1305 // rtm_counters (RTMLockingCounters*) 1306 // flags are killed 1307 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1308 1309 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1310 if (PrintPreciseRTMLockingStatistics) { 1311 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1312 Label check_abort; 1313 testl(abort_status, (1<<i)); 1314 jccb(Assembler::equal, check_abort); 1315 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1316 bind(check_abort); 1317 } 1318 } 1319 } 1320 1321 // Branch if (random & (count-1) != 0), count is 2^n 1322 // tmp, scr and flags are killed 1323 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1324 assert(tmp == rax, ""); 1325 assert(scr == rdx, ""); 1326 rdtsc(); // modifies EDX:EAX 1327 andptr(tmp, count-1); 1328 jccb(Assembler::notZero, brLabel); 1329 } 1330 1331 // Perform abort ratio calculation, set no_rtm bit if high ratio 1332 // input: rtm_counters_Reg (RTMLockingCounters* address) 1333 // tmpReg, rtm_counters_Reg and flags are killed 1334 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1335 Register rtm_counters_Reg, 1336 RTMLockingCounters* rtm_counters, 1337 Metadata* method_data) { 1338 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1339 1340 if (RTMLockingCalculationDelay > 0) { 1341 // Delay calculation 1342 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1343 testptr(tmpReg, tmpReg); 1344 jccb(Assembler::equal, L_done); 1345 } 1346 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1347 // Aborted transactions = abort_count * 100 1348 // All transactions = total_count * RTMTotalCountIncrRate 1349 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1350 1351 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1352 cmpptr(tmpReg, RTMAbortThreshold); 1353 jccb(Assembler::below, L_check_always_rtm2); 1354 imulptr(tmpReg, tmpReg, 100); 1355 1356 Register scrReg = rtm_counters_Reg; 1357 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1358 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1359 imulptr(scrReg, scrReg, RTMAbortRatio); 1360 cmpptr(tmpReg, scrReg); 1361 jccb(Assembler::below, L_check_always_rtm1); 1362 if (method_data != NULL) { 1363 // set rtm_state to "no rtm" in MDO 1364 mov_metadata(tmpReg, method_data); 1365 if (os::is_MP()) { 1366 lock(); 1367 } 1368 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1369 } 1370 jmpb(L_done); 1371 bind(L_check_always_rtm1); 1372 // Reload RTMLockingCounters* address 1373 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1374 bind(L_check_always_rtm2); 1375 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1376 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1377 jccb(Assembler::below, L_done); 1378 if (method_data != NULL) { 1379 // set rtm_state to "always rtm" in MDO 1380 mov_metadata(tmpReg, method_data); 1381 if (os::is_MP()) { 1382 lock(); 1383 } 1384 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1385 } 1386 bind(L_done); 1387 } 1388 1389 // Update counters and perform abort ratio calculation 1390 // input: abort_status_Reg 1391 // rtm_counters_Reg, flags are killed 1392 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1393 Register rtm_counters_Reg, 1394 RTMLockingCounters* rtm_counters, 1395 Metadata* method_data, 1396 bool profile_rtm) { 1397 1398 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1399 // update rtm counters based on rax value at abort 1400 // reads abort_status_Reg, updates flags 1401 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1402 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1403 if (profile_rtm) { 1404 // Save abort status because abort_status_Reg is used by following code. 1405 if (RTMRetryCount > 0) { 1406 push(abort_status_Reg); 1407 } 1408 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1409 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1410 // restore abort status 1411 if (RTMRetryCount > 0) { 1412 pop(abort_status_Reg); 1413 } 1414 } 1415 } 1416 1417 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1418 // inputs: retry_count_Reg 1419 // : abort_status_Reg 1420 // output: retry_count_Reg decremented by 1 1421 // flags are killed 1422 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1423 Label doneRetry; 1424 assert(abort_status_Reg == rax, ""); 1425 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1426 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1427 // if reason is in 0x6 and retry count != 0 then retry 1428 andptr(abort_status_Reg, 0x6); 1429 jccb(Assembler::zero, doneRetry); 1430 testl(retry_count_Reg, retry_count_Reg); 1431 jccb(Assembler::zero, doneRetry); 1432 pause(); 1433 decrementl(retry_count_Reg); 1434 jmp(retryLabel); 1435 bind(doneRetry); 1436 } 1437 1438 // Spin and retry if lock is busy, 1439 // inputs: box_Reg (monitor address) 1440 // : retry_count_Reg 1441 // output: retry_count_Reg decremented by 1 1442 // : clear z flag if retry count exceeded 1443 // tmp_Reg, scr_Reg, flags are killed 1444 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1445 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1446 Label SpinLoop, SpinExit, doneRetry; 1447 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1448 1449 testl(retry_count_Reg, retry_count_Reg); 1450 jccb(Assembler::zero, doneRetry); 1451 decrementl(retry_count_Reg); 1452 movptr(scr_Reg, RTMSpinLoopCount); 1453 1454 bind(SpinLoop); 1455 pause(); 1456 decrementl(scr_Reg); 1457 jccb(Assembler::lessEqual, SpinExit); 1458 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1459 testptr(tmp_Reg, tmp_Reg); 1460 jccb(Assembler::notZero, SpinLoop); 1461 1462 bind(SpinExit); 1463 jmp(retryLabel); 1464 bind(doneRetry); 1465 incrementl(retry_count_Reg); // clear z flag 1466 } 1467 1468 // Use RTM for normal stack locks 1469 // Input: objReg (object to lock) 1470 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1471 Register retry_on_abort_count_Reg, 1472 RTMLockingCounters* stack_rtm_counters, 1473 Metadata* method_data, bool profile_rtm, 1474 Label& DONE_LABEL, Label& IsInflated) { 1475 assert(UseRTMForStackLocks, "why call this otherwise?"); 1476 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1477 assert(tmpReg == rax, ""); 1478 assert(scrReg == rdx, ""); 1479 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1480 1481 if (RTMRetryCount > 0) { 1482 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1483 bind(L_rtm_retry); 1484 } 1485 movptr(tmpReg, Address(objReg, 0)); 1486 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1487 jcc(Assembler::notZero, IsInflated); 1488 1489 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1490 Label L_noincrement; 1491 if (RTMTotalCountIncrRate > 1) { 1492 // tmpReg, scrReg and flags are killed 1493 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1494 } 1495 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1496 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1497 bind(L_noincrement); 1498 } 1499 xbegin(L_on_abort); 1500 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1501 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1502 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1503 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1504 1505 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1506 if (UseRTMXendForLockBusy) { 1507 xend(); 1508 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1509 jmp(L_decrement_retry); 1510 } 1511 else { 1512 xabort(0); 1513 } 1514 bind(L_on_abort); 1515 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1516 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1517 } 1518 bind(L_decrement_retry); 1519 if (RTMRetryCount > 0) { 1520 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1521 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1522 } 1523 } 1524 1525 // Use RTM for inflating locks 1526 // inputs: objReg (object to lock) 1527 // boxReg (on-stack box address (displaced header location) - KILLED) 1528 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1529 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1530 Register scrReg, Register retry_on_busy_count_Reg, 1531 Register retry_on_abort_count_Reg, 1532 RTMLockingCounters* rtm_counters, 1533 Metadata* method_data, bool profile_rtm, 1534 Label& DONE_LABEL) { 1535 assert(UseRTMLocking, "why call this otherwise?"); 1536 assert(tmpReg == rax, ""); 1537 assert(scrReg == rdx, ""); 1538 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1539 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1540 1541 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1542 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1543 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1544 1545 if (RTMRetryCount > 0) { 1546 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1547 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1548 bind(L_rtm_retry); 1549 } 1550 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1551 Label L_noincrement; 1552 if (RTMTotalCountIncrRate > 1) { 1553 // tmpReg, scrReg and flags are killed 1554 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1555 } 1556 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1557 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1558 bind(L_noincrement); 1559 } 1560 xbegin(L_on_abort); 1561 movptr(tmpReg, Address(objReg, 0)); 1562 movptr(tmpReg, Address(tmpReg, owner_offset)); 1563 testptr(tmpReg, tmpReg); 1564 jcc(Assembler::zero, DONE_LABEL); 1565 if (UseRTMXendForLockBusy) { 1566 xend(); 1567 jmp(L_decrement_retry); 1568 } 1569 else { 1570 xabort(0); 1571 } 1572 bind(L_on_abort); 1573 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1574 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1575 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1576 } 1577 if (RTMRetryCount > 0) { 1578 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1579 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1580 } 1581 1582 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1583 testptr(tmpReg, tmpReg) ; 1584 jccb(Assembler::notZero, L_decrement_retry) ; 1585 1586 // Appears unlocked - try to swing _owner from null to non-null. 1587 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1588 #ifdef _LP64 1589 Register threadReg = r15_thread; 1590 #else 1591 get_thread(scrReg); 1592 Register threadReg = scrReg; 1593 #endif 1594 if (os::is_MP()) { 1595 lock(); 1596 } 1597 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1598 1599 if (RTMRetryCount > 0) { 1600 // success done else retry 1601 jccb(Assembler::equal, DONE_LABEL) ; 1602 bind(L_decrement_retry); 1603 // Spin and retry if lock is busy. 1604 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1605 } 1606 else { 1607 bind(L_decrement_retry); 1608 } 1609 } 1610 1611 #endif // INCLUDE_RTM_OPT 1612 1613 // Fast_Lock and Fast_Unlock used by C2 1614 1615 // Because the transitions from emitted code to the runtime 1616 // monitorenter/exit helper stubs are so slow it's critical that 1617 // we inline both the stack-locking fast-path and the inflated fast path. 1618 // 1619 // See also: cmpFastLock and cmpFastUnlock. 1620 // 1621 // What follows is a specialized inline transliteration of the code 1622 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1623 // another option would be to emit TrySlowEnter and TrySlowExit methods 1624 // at startup-time. These methods would accept arguments as 1625 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1626 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1627 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1628 // In practice, however, the # of lock sites is bounded and is usually small. 1629 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1630 // if the processor uses simple bimodal branch predictors keyed by EIP 1631 // Since the helper routines would be called from multiple synchronization 1632 // sites. 1633 // 1634 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1635 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1636 // to those specialized methods. That'd give us a mostly platform-independent 1637 // implementation that the JITs could optimize and inline at their pleasure. 1638 // Done correctly, the only time we'd need to cross to native could would be 1639 // to park() or unpark() threads. We'd also need a few more unsafe operators 1640 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1641 // (b) explicit barriers or fence operations. 1642 // 1643 // TODO: 1644 // 1645 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1646 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1647 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1648 // the lock operators would typically be faster than reifying Self. 1649 // 1650 // * Ideally I'd define the primitives as: 1651 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1652 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1653 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1654 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1655 // Furthermore the register assignments are overconstrained, possibly resulting in 1656 // sub-optimal code near the synchronization site. 1657 // 1658 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1659 // Alternately, use a better sp-proximity test. 1660 // 1661 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1662 // Either one is sufficient to uniquely identify a thread. 1663 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1664 // 1665 // * Intrinsify notify() and notifyAll() for the common cases where the 1666 // object is locked by the calling thread but the waitlist is empty. 1667 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1668 // 1669 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1670 // But beware of excessive branch density on AMD Opterons. 1671 // 1672 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1673 // or failure of the fast-path. If the fast-path fails then we pass 1674 // control to the slow-path, typically in C. In Fast_Lock and 1675 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1676 // will emit a conditional branch immediately after the node. 1677 // So we have branches to branches and lots of ICC.ZF games. 1678 // Instead, it might be better to have C2 pass a "FailureLabel" 1679 // into Fast_Lock and Fast_Unlock. In the case of success, control 1680 // will drop through the node. ICC.ZF is undefined at exit. 1681 // In the case of failure, the node will branch directly to the 1682 // FailureLabel 1683 1684 1685 // obj: object to lock 1686 // box: on-stack box address (displaced header location) - KILLED 1687 // rax,: tmp -- KILLED 1688 // scr: tmp -- KILLED 1689 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1690 Register scrReg, Register cx1Reg, Register cx2Reg, 1691 BiasedLockingCounters* counters, 1692 RTMLockingCounters* rtm_counters, 1693 RTMLockingCounters* stack_rtm_counters, 1694 Metadata* method_data, 1695 bool use_rtm, bool profile_rtm) { 1696 // Ensure the register assignments are disjoint 1697 assert(tmpReg == rax, ""); 1698 1699 if (use_rtm) { 1700 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1701 } else { 1702 assert(cx1Reg == noreg, ""); 1703 assert(cx2Reg == noreg, ""); 1704 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1705 } 1706 1707 if (counters != NULL) { 1708 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1709 } 1710 if (EmitSync & 1) { 1711 // set box->dhw = markOopDesc::unused_mark() 1712 // Force all sync thru slow-path: slow_enter() and slow_exit() 1713 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1714 cmpptr (rsp, (int32_t)NULL_WORD); 1715 } else { 1716 // Possible cases that we'll encounter in fast_lock 1717 // ------------------------------------------------ 1718 // * Inflated 1719 // -- unlocked 1720 // -- Locked 1721 // = by self 1722 // = by other 1723 // * biased 1724 // -- by Self 1725 // -- by other 1726 // * neutral 1727 // * stack-locked 1728 // -- by self 1729 // = sp-proximity test hits 1730 // = sp-proximity test generates false-negative 1731 // -- by other 1732 // 1733 1734 Label IsInflated, DONE_LABEL; 1735 1736 // it's stack-locked, biased or neutral 1737 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1738 // order to reduce the number of conditional branches in the most common cases. 1739 // Beware -- there's a subtle invariant that fetch of the markword 1740 // at [FETCH], below, will never observe a biased encoding (*101b). 1741 // If this invariant is not held we risk exclusion (safety) failure. 1742 if (UseBiasedLocking && !UseOptoBiasInlining) { 1743 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1744 } 1745 1746 #if INCLUDE_RTM_OPT 1747 if (UseRTMForStackLocks && use_rtm) { 1748 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1749 stack_rtm_counters, method_data, profile_rtm, 1750 DONE_LABEL, IsInflated); 1751 } 1752 #endif // INCLUDE_RTM_OPT 1753 1754 movptr(tmpReg, Address(objReg, 0)); // [FETCH] 1755 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1756 jccb(Assembler::notZero, IsInflated); 1757 1758 // Attempt stack-locking ... 1759 orptr (tmpReg, markOopDesc::unlocked_value); 1760 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1761 if (os::is_MP()) { 1762 lock(); 1763 } 1764 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 1765 if (counters != NULL) { 1766 cond_inc32(Assembler::equal, 1767 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1768 } 1769 jcc(Assembler::equal, DONE_LABEL); // Success 1770 1771 // Recursive locking. 1772 // The object is stack-locked: markword contains stack pointer to BasicLock. 1773 // Locked by current thread if difference with current SP is less than one page. 1774 subptr(tmpReg, rsp); 1775 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1776 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1777 movptr(Address(boxReg, 0), tmpReg); 1778 if (counters != NULL) { 1779 cond_inc32(Assembler::equal, 1780 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1781 } 1782 jmp(DONE_LABEL); 1783 1784 bind(IsInflated); 1785 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1786 1787 #if INCLUDE_RTM_OPT 1788 // Use the same RTM locking code in 32- and 64-bit VM. 1789 if (use_rtm) { 1790 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1791 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1792 } else { 1793 #endif // INCLUDE_RTM_OPT 1794 1795 #ifndef _LP64 1796 // The object is inflated. 1797 1798 // boxReg refers to the on-stack BasicLock in the current frame. 1799 // We'd like to write: 1800 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1801 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1802 // additional latency as we have another ST in the store buffer that must drain. 1803 1804 if (EmitSync & 8192) { 1805 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1806 get_thread (scrReg); 1807 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1808 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1809 if (os::is_MP()) { 1810 lock(); 1811 } 1812 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1813 } else 1814 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1815 // register juggle because we need tmpReg for cmpxchgptr below 1816 movptr(scrReg, boxReg); 1817 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1818 1819 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1820 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1821 // prefetchw [eax + Offset(_owner)-2] 1822 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1823 } 1824 1825 if ((EmitSync & 64) == 0) { 1826 // Optimistic form: consider XORL tmpReg,tmpReg 1827 movptr(tmpReg, NULL_WORD); 1828 } else { 1829 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1830 // Test-And-CAS instead of CAS 1831 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1832 testptr(tmpReg, tmpReg); // Locked ? 1833 jccb (Assembler::notZero, DONE_LABEL); 1834 } 1835 1836 // Appears unlocked - try to swing _owner from null to non-null. 1837 // Ideally, I'd manifest "Self" with get_thread and then attempt 1838 // to CAS the register containing Self into m->Owner. 1839 // But we don't have enough registers, so instead we can either try to CAS 1840 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1841 // we later store "Self" into m->Owner. Transiently storing a stack address 1842 // (rsp or the address of the box) into m->owner is harmless. 1843 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1844 if (os::is_MP()) { 1845 lock(); 1846 } 1847 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1848 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1849 // If we weren't able to swing _owner from NULL to the BasicLock 1850 // then take the slow path. 1851 jccb (Assembler::notZero, DONE_LABEL); 1852 // update _owner from BasicLock to thread 1853 get_thread (scrReg); // beware: clobbers ICCs 1854 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1855 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1856 1857 // If the CAS fails we can either retry or pass control to the slow-path. 1858 // We use the latter tactic. 1859 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1860 // If the CAS was successful ... 1861 // Self has acquired the lock 1862 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1863 // Intentional fall-through into DONE_LABEL ... 1864 } else { 1865 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1866 movptr(boxReg, tmpReg); 1867 1868 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1869 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1870 // prefetchw [eax + Offset(_owner)-2] 1871 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1872 } 1873 1874 if ((EmitSync & 64) == 0) { 1875 // Optimistic form 1876 xorptr (tmpReg, tmpReg); 1877 } else { 1878 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1879 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1880 testptr(tmpReg, tmpReg); // Locked ? 1881 jccb (Assembler::notZero, DONE_LABEL); 1882 } 1883 1884 // Appears unlocked - try to swing _owner from null to non-null. 1885 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1886 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1887 get_thread (scrReg); 1888 if (os::is_MP()) { 1889 lock(); 1890 } 1891 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1892 1893 // If the CAS fails we can either retry or pass control to the slow-path. 1894 // We use the latter tactic. 1895 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1896 // If the CAS was successful ... 1897 // Self has acquired the lock 1898 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1899 // Intentional fall-through into DONE_LABEL ... 1900 } 1901 #else // _LP64 1902 // It's inflated 1903 movq(scrReg, tmpReg); 1904 xorq(tmpReg, tmpReg); 1905 1906 if (os::is_MP()) { 1907 lock(); 1908 } 1909 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1910 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1911 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1912 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1913 // Intentional fall-through into DONE_LABEL ... 1914 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1915 #endif // _LP64 1916 #if INCLUDE_RTM_OPT 1917 } // use_rtm() 1918 #endif 1919 // DONE_LABEL is a hot target - we'd really like to place it at the 1920 // start of cache line by padding with NOPs. 1921 // See the AMD and Intel software optimization manuals for the 1922 // most efficient "long" NOP encodings. 1923 // Unfortunately none of our alignment mechanisms suffice. 1924 bind(DONE_LABEL); 1925 1926 // At DONE_LABEL the icc ZFlag is set as follows ... 1927 // Fast_Unlock uses the same protocol. 1928 // ZFlag == 1 -> Success 1929 // ZFlag == 0 -> Failure - force control through the slow-path 1930 } 1931 } 1932 1933 // obj: object to unlock 1934 // box: box address (displaced header location), killed. Must be EAX. 1935 // tmp: killed, cannot be obj nor box. 1936 // 1937 // Some commentary on balanced locking: 1938 // 1939 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1940 // Methods that don't have provably balanced locking are forced to run in the 1941 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1942 // The interpreter provides two properties: 1943 // I1: At return-time the interpreter automatically and quietly unlocks any 1944 // objects acquired the current activation (frame). Recall that the 1945 // interpreter maintains an on-stack list of locks currently held by 1946 // a frame. 1947 // I2: If a method attempts to unlock an object that is not held by the 1948 // the frame the interpreter throws IMSX. 1949 // 1950 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1951 // B() doesn't have provably balanced locking so it runs in the interpreter. 1952 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1953 // is still locked by A(). 1954 // 1955 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1956 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1957 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1958 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1959 // Arguably given that the spec legislates the JNI case as undefined our implementation 1960 // could reasonably *avoid* checking owner in Fast_Unlock(). 1961 // In the interest of performance we elide m->Owner==Self check in unlock. 1962 // A perfectly viable alternative is to elide the owner check except when 1963 // Xcheck:jni is enabled. 1964 1965 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1966 assert(boxReg == rax, ""); 1967 assert_different_registers(objReg, boxReg, tmpReg); 1968 1969 if (EmitSync & 4) { 1970 // Disable - inhibit all inlining. Force control through the slow-path 1971 cmpptr (rsp, 0); 1972 } else { 1973 Label DONE_LABEL, Stacked, CheckSucc; 1974 1975 // Critically, the biased locking test must have precedence over 1976 // and appear before the (box->dhw == 0) recursive stack-lock test. 1977 if (UseBiasedLocking && !UseOptoBiasInlining) { 1978 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1979 } 1980 1981 #if INCLUDE_RTM_OPT 1982 if (UseRTMForStackLocks && use_rtm) { 1983 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1984 Label L_regular_unlock; 1985 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1986 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1987 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1988 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 1989 xend(); // otherwise end... 1990 jmp(DONE_LABEL); // ... and we're done 1991 bind(L_regular_unlock); 1992 } 1993 #endif 1994 1995 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 1996 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 1997 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword 1998 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 1999 jccb (Assembler::zero, Stacked); 2000 2001 // It's inflated. 2002 #if INCLUDE_RTM_OPT 2003 if (use_rtm) { 2004 Label L_regular_inflated_unlock; 2005 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 2006 movptr(boxReg, Address(tmpReg, owner_offset)); 2007 testptr(boxReg, boxReg); 2008 jccb(Assembler::notZero, L_regular_inflated_unlock); 2009 xend(); 2010 jmpb(DONE_LABEL); 2011 bind(L_regular_inflated_unlock); 2012 } 2013 #endif 2014 2015 // Despite our balanced locking property we still check that m->_owner == Self 2016 // as java routines or native JNI code called by this thread might 2017 // have released the lock. 2018 // Refer to the comments in synchronizer.cpp for how we might encode extra 2019 // state in _succ so we can avoid fetching EntryList|cxq. 2020 // 2021 // I'd like to add more cases in fast_lock() and fast_unlock() -- 2022 // such as recursive enter and exit -- but we have to be wary of 2023 // I$ bloat, T$ effects and BP$ effects. 2024 // 2025 // If there's no contention try a 1-0 exit. That is, exit without 2026 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 2027 // we detect and recover from the race that the 1-0 exit admits. 2028 // 2029 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2030 // before it STs null into _owner, releasing the lock. Updates 2031 // to data protected by the critical section must be visible before 2032 // we drop the lock (and thus before any other thread could acquire 2033 // the lock and observe the fields protected by the lock). 2034 // IA32's memory-model is SPO, so STs are ordered with respect to 2035 // each other and there's no need for an explicit barrier (fence). 2036 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2037 #ifndef _LP64 2038 get_thread (boxReg); 2039 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2040 // prefetchw [ebx + Offset(_owner)-2] 2041 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2042 } 2043 2044 // Note that we could employ various encoding schemes to reduce 2045 // the number of loads below (currently 4) to just 2 or 3. 2046 // Refer to the comments in synchronizer.cpp. 2047 // In practice the chain of fetches doesn't seem to impact performance, however. 2048 xorptr(boxReg, boxReg); 2049 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2050 // Attempt to reduce branch density - AMD's branch predictor. 2051 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2052 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2054 jccb (Assembler::notZero, DONE_LABEL); 2055 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2056 jmpb (DONE_LABEL); 2057 } else { 2058 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2059 jccb (Assembler::notZero, DONE_LABEL); 2060 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2061 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2062 jccb (Assembler::notZero, CheckSucc); 2063 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2064 jmpb (DONE_LABEL); 2065 } 2066 2067 // The Following code fragment (EmitSync & 65536) improves the performance of 2068 // contended applications and contended synchronization microbenchmarks. 2069 // Unfortunately the emission of the code - even though not executed - causes regressions 2070 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2071 // with an equal number of never-executed NOPs results in the same regression. 2072 // We leave it off by default. 2073 2074 if ((EmitSync & 65536) != 0) { 2075 Label LSuccess, LGoSlowPath ; 2076 2077 bind (CheckSucc); 2078 2079 // Optional pre-test ... it's safe to elide this 2080 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2081 jccb(Assembler::zero, LGoSlowPath); 2082 2083 // We have a classic Dekker-style idiom: 2084 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2085 // There are a number of ways to implement the barrier: 2086 // (1) lock:andl &m->_owner, 0 2087 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2088 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2089 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2090 // (2) If supported, an explicit MFENCE is appealing. 2091 // In older IA32 processors MFENCE is slower than lock:add or xchg 2092 // particularly if the write-buffer is full as might be the case if 2093 // if stores closely precede the fence or fence-equivalent instruction. 2094 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2095 // as the situation has changed with Nehalem and Shanghai. 2096 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2097 // The $lines underlying the top-of-stack should be in M-state. 2098 // The locked add instruction is serializing, of course. 2099 // (4) Use xchg, which is serializing 2100 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2101 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2102 // The integer condition codes will tell us if succ was 0. 2103 // Since _succ and _owner should reside in the same $line and 2104 // we just stored into _owner, it's likely that the $line 2105 // remains in M-state for the lock:orl. 2106 // 2107 // We currently use (3), although it's likely that switching to (2) 2108 // is correct for the future. 2109 2110 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2111 if (os::is_MP()) { 2112 lock(); addptr(Address(rsp, 0), 0); 2113 } 2114 // Ratify _succ remains non-null 2115 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2116 jccb (Assembler::notZero, LSuccess); 2117 2118 xorptr(boxReg, boxReg); // box is really EAX 2119 if (os::is_MP()) { lock(); } 2120 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2121 // There's no successor so we tried to regrab the lock with the 2122 // placeholder value. If that didn't work, then another thread 2123 // grabbed the lock so we're done (and exit was a success). 2124 jccb (Assembler::notEqual, LSuccess); 2125 // Since we're low on registers we installed rsp as a placeholding in _owner. 2126 // Now install Self over rsp. This is safe as we're transitioning from 2127 // non-null to non=null 2128 get_thread (boxReg); 2129 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2130 // Intentional fall-through into LGoSlowPath ... 2131 2132 bind (LGoSlowPath); 2133 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2134 jmpb (DONE_LABEL); 2135 2136 bind (LSuccess); 2137 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2138 jmpb (DONE_LABEL); 2139 } 2140 2141 bind (Stacked); 2142 // It's not inflated and it's not recursively stack-locked and it's not biased. 2143 // It must be stack-locked. 2144 // Try to reset the header to displaced header. 2145 // The "box" value on the stack is stable, so we can reload 2146 // and be assured we observe the same value as above. 2147 movptr(tmpReg, Address(boxReg, 0)); 2148 if (os::is_MP()) { 2149 lock(); 2150 } 2151 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2152 // Intention fall-thru into DONE_LABEL 2153 2154 // DONE_LABEL is a hot target - we'd really like to place it at the 2155 // start of cache line by padding with NOPs. 2156 // See the AMD and Intel software optimization manuals for the 2157 // most efficient "long" NOP encodings. 2158 // Unfortunately none of our alignment mechanisms suffice. 2159 if ((EmitSync & 65536) == 0) { 2160 bind (CheckSucc); 2161 } 2162 #else // _LP64 2163 // It's inflated 2164 if (EmitSync & 1024) { 2165 // Emit code to check that _owner == Self 2166 // We could fold the _owner test into subsequent code more efficiently 2167 // than using a stand-alone check, but since _owner checking is off by 2168 // default we don't bother. We also might consider predicating the 2169 // _owner==Self check on Xcheck:jni or running on a debug build. 2170 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2171 xorptr(boxReg, r15_thread); 2172 } else { 2173 xorptr(boxReg, boxReg); 2174 } 2175 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2176 jccb (Assembler::notZero, DONE_LABEL); 2177 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2178 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2179 jccb (Assembler::notZero, CheckSucc); 2180 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2181 jmpb (DONE_LABEL); 2182 2183 if ((EmitSync & 65536) == 0) { 2184 // Try to avoid passing control into the slow_path ... 2185 Label LSuccess, LGoSlowPath ; 2186 bind (CheckSucc); 2187 2188 // The following optional optimization can be elided if necessary 2189 // Effectively: if (succ == null) goto SlowPath 2190 // The code reduces the window for a race, however, 2191 // and thus benefits performance. 2192 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2193 jccb (Assembler::zero, LGoSlowPath); 2194 2195 xorptr(boxReg, boxReg); 2196 if ((EmitSync & 16) && os::is_MP()) { 2197 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2198 } else { 2199 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2200 if (os::is_MP()) { 2201 // Memory barrier/fence 2202 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2203 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2204 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2205 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2206 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2207 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2208 lock(); addl(Address(rsp, 0), 0); 2209 } 2210 } 2211 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2212 jccb (Assembler::notZero, LSuccess); 2213 2214 // Rare inopportune interleaving - race. 2215 // The successor vanished in the small window above. 2216 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2217 // We need to ensure progress and succession. 2218 // Try to reacquire the lock. 2219 // If that fails then the new owner is responsible for succession and this 2220 // thread needs to take no further action and can exit via the fast path (success). 2221 // If the re-acquire succeeds then pass control into the slow path. 2222 // As implemented, this latter mode is horrible because we generated more 2223 // coherence traffic on the lock *and* artifically extended the critical section 2224 // length while by virtue of passing control into the slow path. 2225 2226 // box is really RAX -- the following CMPXCHG depends on that binding 2227 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2228 if (os::is_MP()) { lock(); } 2229 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2230 // There's no successor so we tried to regrab the lock. 2231 // If that didn't work, then another thread grabbed the 2232 // lock so we're done (and exit was a success). 2233 jccb (Assembler::notEqual, LSuccess); 2234 // Intentional fall-through into slow-path 2235 2236 bind (LGoSlowPath); 2237 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2238 jmpb (DONE_LABEL); 2239 2240 bind (LSuccess); 2241 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2242 jmpb (DONE_LABEL); 2243 } 2244 2245 bind (Stacked); 2246 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2247 if (os::is_MP()) { lock(); } 2248 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2249 2250 if (EmitSync & 65536) { 2251 bind (CheckSucc); 2252 } 2253 #endif 2254 bind(DONE_LABEL); 2255 } 2256 } 2257 #endif // COMPILER2 2258 2259 void MacroAssembler::c2bool(Register x) { 2260 // implements x == 0 ? 0 : 1 2261 // note: must only look at least-significant byte of x 2262 // since C-style booleans are stored in one byte 2263 // only! (was bug) 2264 andl(x, 0xFF); 2265 setb(Assembler::notZero, x); 2266 } 2267 2268 // Wouldn't need if AddressLiteral version had new name 2269 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2270 Assembler::call(L, rtype); 2271 } 2272 2273 void MacroAssembler::call(Register entry) { 2274 Assembler::call(entry); 2275 } 2276 2277 void MacroAssembler::call(AddressLiteral entry) { 2278 if (reachable(entry)) { 2279 Assembler::call_literal(entry.target(), entry.rspec()); 2280 } else { 2281 lea(rscratch1, entry); 2282 Assembler::call(rscratch1); 2283 } 2284 } 2285 2286 void MacroAssembler::ic_call(address entry, jint method_index) { 2287 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 2288 movptr(rax, (intptr_t)Universe::non_oop_word()); 2289 call(AddressLiteral(entry, rh)); 2290 } 2291 2292 // Implementation of call_VM versions 2293 2294 void MacroAssembler::call_VM(Register oop_result, 2295 address entry_point, 2296 bool check_exceptions) { 2297 Label C, E; 2298 call(C, relocInfo::none); 2299 jmp(E); 2300 2301 bind(C); 2302 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2303 ret(0); 2304 2305 bind(E); 2306 } 2307 2308 void MacroAssembler::call_VM(Register oop_result, 2309 address entry_point, 2310 Register arg_1, 2311 bool check_exceptions) { 2312 Label C, E; 2313 call(C, relocInfo::none); 2314 jmp(E); 2315 2316 bind(C); 2317 pass_arg1(this, arg_1); 2318 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2319 ret(0); 2320 2321 bind(E); 2322 } 2323 2324 void MacroAssembler::call_VM(Register oop_result, 2325 address entry_point, 2326 Register arg_1, 2327 Register arg_2, 2328 bool check_exceptions) { 2329 Label C, E; 2330 call(C, relocInfo::none); 2331 jmp(E); 2332 2333 bind(C); 2334 2335 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2336 2337 pass_arg2(this, arg_2); 2338 pass_arg1(this, arg_1); 2339 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2340 ret(0); 2341 2342 bind(E); 2343 } 2344 2345 void MacroAssembler::call_VM(Register oop_result, 2346 address entry_point, 2347 Register arg_1, 2348 Register arg_2, 2349 Register arg_3, 2350 bool check_exceptions) { 2351 Label C, E; 2352 call(C, relocInfo::none); 2353 jmp(E); 2354 2355 bind(C); 2356 2357 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2358 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2359 pass_arg3(this, arg_3); 2360 2361 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2362 pass_arg2(this, arg_2); 2363 2364 pass_arg1(this, arg_1); 2365 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2366 ret(0); 2367 2368 bind(E); 2369 } 2370 2371 void MacroAssembler::call_VM(Register oop_result, 2372 Register last_java_sp, 2373 address entry_point, 2374 int number_of_arguments, 2375 bool check_exceptions) { 2376 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2377 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2378 } 2379 2380 void MacroAssembler::call_VM(Register oop_result, 2381 Register last_java_sp, 2382 address entry_point, 2383 Register arg_1, 2384 bool check_exceptions) { 2385 pass_arg1(this, arg_1); 2386 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2387 } 2388 2389 void MacroAssembler::call_VM(Register oop_result, 2390 Register last_java_sp, 2391 address entry_point, 2392 Register arg_1, 2393 Register arg_2, 2394 bool check_exceptions) { 2395 2396 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2397 pass_arg2(this, arg_2); 2398 pass_arg1(this, arg_1); 2399 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2400 } 2401 2402 void MacroAssembler::call_VM(Register oop_result, 2403 Register last_java_sp, 2404 address entry_point, 2405 Register arg_1, 2406 Register arg_2, 2407 Register arg_3, 2408 bool check_exceptions) { 2409 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2410 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2411 pass_arg3(this, arg_3); 2412 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2413 pass_arg2(this, arg_2); 2414 pass_arg1(this, arg_1); 2415 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2416 } 2417 2418 void MacroAssembler::super_call_VM(Register oop_result, 2419 Register last_java_sp, 2420 address entry_point, 2421 int number_of_arguments, 2422 bool check_exceptions) { 2423 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2424 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2425 } 2426 2427 void MacroAssembler::super_call_VM(Register oop_result, 2428 Register last_java_sp, 2429 address entry_point, 2430 Register arg_1, 2431 bool check_exceptions) { 2432 pass_arg1(this, arg_1); 2433 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2434 } 2435 2436 void MacroAssembler::super_call_VM(Register oop_result, 2437 Register last_java_sp, 2438 address entry_point, 2439 Register arg_1, 2440 Register arg_2, 2441 bool check_exceptions) { 2442 2443 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2444 pass_arg2(this, arg_2); 2445 pass_arg1(this, arg_1); 2446 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2447 } 2448 2449 void MacroAssembler::super_call_VM(Register oop_result, 2450 Register last_java_sp, 2451 address entry_point, 2452 Register arg_1, 2453 Register arg_2, 2454 Register arg_3, 2455 bool check_exceptions) { 2456 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2457 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2458 pass_arg3(this, arg_3); 2459 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2460 pass_arg2(this, arg_2); 2461 pass_arg1(this, arg_1); 2462 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2463 } 2464 2465 void MacroAssembler::call_VM_base(Register oop_result, 2466 Register java_thread, 2467 Register last_java_sp, 2468 address entry_point, 2469 int number_of_arguments, 2470 bool check_exceptions) { 2471 // determine java_thread register 2472 if (!java_thread->is_valid()) { 2473 #ifdef _LP64 2474 java_thread = r15_thread; 2475 #else 2476 java_thread = rdi; 2477 get_thread(java_thread); 2478 #endif // LP64 2479 } 2480 // determine last_java_sp register 2481 if (!last_java_sp->is_valid()) { 2482 last_java_sp = rsp; 2483 } 2484 // debugging support 2485 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2486 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2487 #ifdef ASSERT 2488 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2489 // r12 is the heapbase. 2490 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2491 #endif // ASSERT 2492 2493 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2494 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2495 2496 // push java thread (becomes first argument of C function) 2497 2498 NOT_LP64(push(java_thread); number_of_arguments++); 2499 LP64_ONLY(mov(c_rarg0, r15_thread)); 2500 2501 // set last Java frame before call 2502 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2503 2504 // Only interpreter should have to set fp 2505 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2506 2507 // do the call, remove parameters 2508 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2509 2510 // restore the thread (cannot use the pushed argument since arguments 2511 // may be overwritten by C code generated by an optimizing compiler); 2512 // however can use the register value directly if it is callee saved. 2513 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2514 // rdi & rsi (also r15) are callee saved -> nothing to do 2515 #ifdef ASSERT 2516 guarantee(java_thread != rax, "change this code"); 2517 push(rax); 2518 { Label L; 2519 get_thread(rax); 2520 cmpptr(java_thread, rax); 2521 jcc(Assembler::equal, L); 2522 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2523 bind(L); 2524 } 2525 pop(rax); 2526 #endif 2527 } else { 2528 get_thread(java_thread); 2529 } 2530 // reset last Java frame 2531 // Only interpreter should have to clear fp 2532 reset_last_Java_frame(java_thread, true); 2533 2534 // C++ interp handles this in the interpreter 2535 check_and_handle_popframe(java_thread); 2536 check_and_handle_earlyret(java_thread); 2537 2538 if (check_exceptions) { 2539 // check for pending exceptions (java_thread is set upon return) 2540 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2541 #ifndef _LP64 2542 jump_cc(Assembler::notEqual, 2543 RuntimeAddress(StubRoutines::forward_exception_entry())); 2544 #else 2545 // This used to conditionally jump to forward_exception however it is 2546 // possible if we relocate that the branch will not reach. So we must jump 2547 // around so we can always reach 2548 2549 Label ok; 2550 jcc(Assembler::equal, ok); 2551 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2552 bind(ok); 2553 #endif // LP64 2554 } 2555 2556 // get oop result if there is one and reset the value in the thread 2557 if (oop_result->is_valid()) { 2558 get_vm_result(oop_result, java_thread); 2559 } 2560 } 2561 2562 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2563 2564 // Calculate the value for last_Java_sp 2565 // somewhat subtle. call_VM does an intermediate call 2566 // which places a return address on the stack just under the 2567 // stack pointer as the user finsihed with it. This allows 2568 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2569 // On 32bit we then have to push additional args on the stack to accomplish 2570 // the actual requested call. On 64bit call_VM only can use register args 2571 // so the only extra space is the return address that call_VM created. 2572 // This hopefully explains the calculations here. 2573 2574 #ifdef _LP64 2575 // We've pushed one address, correct last_Java_sp 2576 lea(rax, Address(rsp, wordSize)); 2577 #else 2578 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2579 #endif // LP64 2580 2581 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2582 2583 } 2584 2585 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter. 2586 void MacroAssembler::call_VM_leaf0(address entry_point) { 2587 MacroAssembler::call_VM_leaf_base(entry_point, 0); 2588 } 2589 2590 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2591 call_VM_leaf_base(entry_point, number_of_arguments); 2592 } 2593 2594 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2595 pass_arg0(this, arg_0); 2596 call_VM_leaf(entry_point, 1); 2597 } 2598 2599 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2600 2601 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2602 pass_arg1(this, arg_1); 2603 pass_arg0(this, arg_0); 2604 call_VM_leaf(entry_point, 2); 2605 } 2606 2607 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2608 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2609 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2610 pass_arg2(this, arg_2); 2611 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2612 pass_arg1(this, arg_1); 2613 pass_arg0(this, arg_0); 2614 call_VM_leaf(entry_point, 3); 2615 } 2616 2617 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2618 pass_arg0(this, arg_0); 2619 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2620 } 2621 2622 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2623 2624 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2625 pass_arg1(this, arg_1); 2626 pass_arg0(this, arg_0); 2627 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2628 } 2629 2630 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2631 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2632 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2633 pass_arg2(this, arg_2); 2634 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2635 pass_arg1(this, arg_1); 2636 pass_arg0(this, arg_0); 2637 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2638 } 2639 2640 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2641 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2642 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2643 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2644 pass_arg3(this, arg_3); 2645 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2646 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2647 pass_arg2(this, arg_2); 2648 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2649 pass_arg1(this, arg_1); 2650 pass_arg0(this, arg_0); 2651 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2652 } 2653 2654 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2655 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2656 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2657 verify_oop(oop_result, "broken oop in call_VM_base"); 2658 } 2659 2660 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2661 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2662 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2663 } 2664 2665 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2666 } 2667 2668 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2669 } 2670 2671 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2672 if (reachable(src1)) { 2673 cmpl(as_Address(src1), imm); 2674 } else { 2675 lea(rscratch1, src1); 2676 cmpl(Address(rscratch1, 0), imm); 2677 } 2678 } 2679 2680 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2681 assert(!src2.is_lval(), "use cmpptr"); 2682 if (reachable(src2)) { 2683 cmpl(src1, as_Address(src2)); 2684 } else { 2685 lea(rscratch1, src2); 2686 cmpl(src1, Address(rscratch1, 0)); 2687 } 2688 } 2689 2690 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2691 Assembler::cmpl(src1, imm); 2692 } 2693 2694 void MacroAssembler::cmp32(Register src1, Address src2) { 2695 Assembler::cmpl(src1, src2); 2696 } 2697 2698 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2699 ucomisd(opr1, opr2); 2700 2701 Label L; 2702 if (unordered_is_less) { 2703 movl(dst, -1); 2704 jcc(Assembler::parity, L); 2705 jcc(Assembler::below , L); 2706 movl(dst, 0); 2707 jcc(Assembler::equal , L); 2708 increment(dst); 2709 } else { // unordered is greater 2710 movl(dst, 1); 2711 jcc(Assembler::parity, L); 2712 jcc(Assembler::above , L); 2713 movl(dst, 0); 2714 jcc(Assembler::equal , L); 2715 decrementl(dst); 2716 } 2717 bind(L); 2718 } 2719 2720 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2721 ucomiss(opr1, opr2); 2722 2723 Label L; 2724 if (unordered_is_less) { 2725 movl(dst, -1); 2726 jcc(Assembler::parity, L); 2727 jcc(Assembler::below , L); 2728 movl(dst, 0); 2729 jcc(Assembler::equal , L); 2730 increment(dst); 2731 } else { // unordered is greater 2732 movl(dst, 1); 2733 jcc(Assembler::parity, L); 2734 jcc(Assembler::above , L); 2735 movl(dst, 0); 2736 jcc(Assembler::equal , L); 2737 decrementl(dst); 2738 } 2739 bind(L); 2740 } 2741 2742 2743 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2744 if (reachable(src1)) { 2745 cmpb(as_Address(src1), imm); 2746 } else { 2747 lea(rscratch1, src1); 2748 cmpb(Address(rscratch1, 0), imm); 2749 } 2750 } 2751 2752 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2753 #ifdef _LP64 2754 if (src2.is_lval()) { 2755 movptr(rscratch1, src2); 2756 Assembler::cmpq(src1, rscratch1); 2757 } else if (reachable(src2)) { 2758 cmpq(src1, as_Address(src2)); 2759 } else { 2760 lea(rscratch1, src2); 2761 Assembler::cmpq(src1, Address(rscratch1, 0)); 2762 } 2763 #else 2764 if (src2.is_lval()) { 2765 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2766 } else { 2767 cmpl(src1, as_Address(src2)); 2768 } 2769 #endif // _LP64 2770 } 2771 2772 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2773 assert(src2.is_lval(), "not a mem-mem compare"); 2774 #ifdef _LP64 2775 // moves src2's literal address 2776 movptr(rscratch1, src2); 2777 Assembler::cmpq(src1, rscratch1); 2778 #else 2779 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2780 #endif // _LP64 2781 } 2782 2783 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2784 if (reachable(adr)) { 2785 if (os::is_MP()) 2786 lock(); 2787 cmpxchgptr(reg, as_Address(adr)); 2788 } else { 2789 lea(rscratch1, adr); 2790 if (os::is_MP()) 2791 lock(); 2792 cmpxchgptr(reg, Address(rscratch1, 0)); 2793 } 2794 } 2795 2796 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2797 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2798 } 2799 2800 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2801 if (reachable(src)) { 2802 Assembler::comisd(dst, as_Address(src)); 2803 } else { 2804 lea(rscratch1, src); 2805 Assembler::comisd(dst, Address(rscratch1, 0)); 2806 } 2807 } 2808 2809 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2810 if (reachable(src)) { 2811 Assembler::comiss(dst, as_Address(src)); 2812 } else { 2813 lea(rscratch1, src); 2814 Assembler::comiss(dst, Address(rscratch1, 0)); 2815 } 2816 } 2817 2818 2819 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2820 Condition negated_cond = negate_condition(cond); 2821 Label L; 2822 jcc(negated_cond, L); 2823 pushf(); // Preserve flags 2824 atomic_incl(counter_addr); 2825 popf(); 2826 bind(L); 2827 } 2828 2829 int MacroAssembler::corrected_idivl(Register reg) { 2830 // Full implementation of Java idiv and irem; checks for 2831 // special case as described in JVM spec., p.243 & p.271. 2832 // The function returns the (pc) offset of the idivl 2833 // instruction - may be needed for implicit exceptions. 2834 // 2835 // normal case special case 2836 // 2837 // input : rax,: dividend min_int 2838 // reg: divisor (may not be rax,/rdx) -1 2839 // 2840 // output: rax,: quotient (= rax, idiv reg) min_int 2841 // rdx: remainder (= rax, irem reg) 0 2842 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2843 const int min_int = 0x80000000; 2844 Label normal_case, special_case; 2845 2846 // check for special case 2847 cmpl(rax, min_int); 2848 jcc(Assembler::notEqual, normal_case); 2849 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2850 cmpl(reg, -1); 2851 jcc(Assembler::equal, special_case); 2852 2853 // handle normal case 2854 bind(normal_case); 2855 cdql(); 2856 int idivl_offset = offset(); 2857 idivl(reg); 2858 2859 // normal and special case exit 2860 bind(special_case); 2861 2862 return idivl_offset; 2863 } 2864 2865 2866 2867 void MacroAssembler::decrementl(Register reg, int value) { 2868 if (value == min_jint) {subl(reg, value) ; return; } 2869 if (value < 0) { incrementl(reg, -value); return; } 2870 if (value == 0) { ; return; } 2871 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2872 /* else */ { subl(reg, value) ; return; } 2873 } 2874 2875 void MacroAssembler::decrementl(Address dst, int value) { 2876 if (value == min_jint) {subl(dst, value) ; return; } 2877 if (value < 0) { incrementl(dst, -value); return; } 2878 if (value == 0) { ; return; } 2879 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2880 /* else */ { subl(dst, value) ; return; } 2881 } 2882 2883 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2884 assert (shift_value > 0, "illegal shift value"); 2885 Label _is_positive; 2886 testl (reg, reg); 2887 jcc (Assembler::positive, _is_positive); 2888 int offset = (1 << shift_value) - 1 ; 2889 2890 if (offset == 1) { 2891 incrementl(reg); 2892 } else { 2893 addl(reg, offset); 2894 } 2895 2896 bind (_is_positive); 2897 sarl(reg, shift_value); 2898 } 2899 2900 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2901 if (reachable(src)) { 2902 Assembler::divsd(dst, as_Address(src)); 2903 } else { 2904 lea(rscratch1, src); 2905 Assembler::divsd(dst, Address(rscratch1, 0)); 2906 } 2907 } 2908 2909 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2910 if (reachable(src)) { 2911 Assembler::divss(dst, as_Address(src)); 2912 } else { 2913 lea(rscratch1, src); 2914 Assembler::divss(dst, Address(rscratch1, 0)); 2915 } 2916 } 2917 2918 // !defined(COMPILER2) is because of stupid core builds 2919 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI 2920 void MacroAssembler::empty_FPU_stack() { 2921 if (VM_Version::supports_mmx()) { 2922 emms(); 2923 } else { 2924 for (int i = 8; i-- > 0; ) ffree(i); 2925 } 2926 } 2927 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI 2928 2929 2930 // Defines obj, preserves var_size_in_bytes 2931 void MacroAssembler::eden_allocate(Register obj, 2932 Register var_size_in_bytes, 2933 int con_size_in_bytes, 2934 Register t1, 2935 Label& slow_case) { 2936 assert(obj == rax, "obj must be in rax, for cmpxchg"); 2937 assert_different_registers(obj, var_size_in_bytes, t1); 2938 if (!Universe::heap()->supports_inline_contig_alloc()) { 2939 jmp(slow_case); 2940 } else { 2941 Register end = t1; 2942 Label retry; 2943 bind(retry); 2944 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 2945 movptr(obj, heap_top); 2946 if (var_size_in_bytes == noreg) { 2947 lea(end, Address(obj, con_size_in_bytes)); 2948 } else { 2949 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 2950 } 2951 // if end < obj then we wrapped around => object too long => slow case 2952 cmpptr(end, obj); 2953 jcc(Assembler::below, slow_case); 2954 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 2955 jcc(Assembler::above, slow_case); 2956 // Compare obj with the top addr, and if still equal, store the new top addr in 2957 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 2958 // it otherwise. Use lock prefix for atomicity on MPs. 2959 locked_cmpxchgptr(end, heap_top); 2960 jcc(Assembler::notEqual, retry); 2961 } 2962 } 2963 2964 void MacroAssembler::enter() { 2965 push(rbp); 2966 mov(rbp, rsp); 2967 } 2968 2969 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2970 void MacroAssembler::fat_nop() { 2971 if (UseAddressNop) { 2972 addr_nop_5(); 2973 } else { 2974 emit_int8(0x26); // es: 2975 emit_int8(0x2e); // cs: 2976 emit_int8(0x64); // fs: 2977 emit_int8(0x65); // gs: 2978 emit_int8((unsigned char)0x90); 2979 } 2980 } 2981 2982 void MacroAssembler::fcmp(Register tmp) { 2983 fcmp(tmp, 1, true, true); 2984 } 2985 2986 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2987 assert(!pop_right || pop_left, "usage error"); 2988 if (VM_Version::supports_cmov()) { 2989 assert(tmp == noreg, "unneeded temp"); 2990 if (pop_left) { 2991 fucomip(index); 2992 } else { 2993 fucomi(index); 2994 } 2995 if (pop_right) { 2996 fpop(); 2997 } 2998 } else { 2999 assert(tmp != noreg, "need temp"); 3000 if (pop_left) { 3001 if (pop_right) { 3002 fcompp(); 3003 } else { 3004 fcomp(index); 3005 } 3006 } else { 3007 fcom(index); 3008 } 3009 // convert FPU condition into eflags condition via rax, 3010 save_rax(tmp); 3011 fwait(); fnstsw_ax(); 3012 sahf(); 3013 restore_rax(tmp); 3014 } 3015 // condition codes set as follows: 3016 // 3017 // CF (corresponds to C0) if x < y 3018 // PF (corresponds to C2) if unordered 3019 // ZF (corresponds to C3) if x = y 3020 } 3021 3022 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 3023 fcmp2int(dst, unordered_is_less, 1, true, true); 3024 } 3025 3026 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 3027 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 3028 Label L; 3029 if (unordered_is_less) { 3030 movl(dst, -1); 3031 jcc(Assembler::parity, L); 3032 jcc(Assembler::below , L); 3033 movl(dst, 0); 3034 jcc(Assembler::equal , L); 3035 increment(dst); 3036 } else { // unordered is greater 3037 movl(dst, 1); 3038 jcc(Assembler::parity, L); 3039 jcc(Assembler::above , L); 3040 movl(dst, 0); 3041 jcc(Assembler::equal , L); 3042 decrementl(dst); 3043 } 3044 bind(L); 3045 } 3046 3047 void MacroAssembler::fld_d(AddressLiteral src) { 3048 fld_d(as_Address(src)); 3049 } 3050 3051 void MacroAssembler::fld_s(AddressLiteral src) { 3052 fld_s(as_Address(src)); 3053 } 3054 3055 void MacroAssembler::fld_x(AddressLiteral src) { 3056 Assembler::fld_x(as_Address(src)); 3057 } 3058 3059 void MacroAssembler::fldcw(AddressLiteral src) { 3060 Assembler::fldcw(as_Address(src)); 3061 } 3062 3063 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 3064 if (reachable(src)) { 3065 Assembler::mulpd(dst, as_Address(src)); 3066 } else { 3067 lea(rscratch1, src); 3068 Assembler::mulpd(dst, Address(rscratch1, 0)); 3069 } 3070 } 3071 3072 void MacroAssembler::increase_precision() { 3073 subptr(rsp, BytesPerWord); 3074 fnstcw(Address(rsp, 0)); 3075 movl(rax, Address(rsp, 0)); 3076 orl(rax, 0x300); 3077 push(rax); 3078 fldcw(Address(rsp, 0)); 3079 pop(rax); 3080 } 3081 3082 void MacroAssembler::restore_precision() { 3083 fldcw(Address(rsp, 0)); 3084 addptr(rsp, BytesPerWord); 3085 } 3086 3087 void MacroAssembler::fpop() { 3088 ffree(); 3089 fincstp(); 3090 } 3091 3092 void MacroAssembler::load_float(Address src) { 3093 if (UseSSE >= 1) { 3094 movflt(xmm0, src); 3095 } else { 3096 LP64_ONLY(ShouldNotReachHere()); 3097 NOT_LP64(fld_s(src)); 3098 } 3099 } 3100 3101 void MacroAssembler::store_float(Address dst) { 3102 if (UseSSE >= 1) { 3103 movflt(dst, xmm0); 3104 } else { 3105 LP64_ONLY(ShouldNotReachHere()); 3106 NOT_LP64(fstp_s(dst)); 3107 } 3108 } 3109 3110 void MacroAssembler::load_double(Address src) { 3111 if (UseSSE >= 2) { 3112 movdbl(xmm0, src); 3113 } else { 3114 LP64_ONLY(ShouldNotReachHere()); 3115 NOT_LP64(fld_d(src)); 3116 } 3117 } 3118 3119 void MacroAssembler::store_double(Address dst) { 3120 if (UseSSE >= 2) { 3121 movdbl(dst, xmm0); 3122 } else { 3123 LP64_ONLY(ShouldNotReachHere()); 3124 NOT_LP64(fstp_d(dst)); 3125 } 3126 } 3127 3128 void MacroAssembler::fremr(Register tmp) { 3129 save_rax(tmp); 3130 { Label L; 3131 bind(L); 3132 fprem(); 3133 fwait(); fnstsw_ax(); 3134 #ifdef _LP64 3135 testl(rax, 0x400); 3136 jcc(Assembler::notEqual, L); 3137 #else 3138 sahf(); 3139 jcc(Assembler::parity, L); 3140 #endif // _LP64 3141 } 3142 restore_rax(tmp); 3143 // Result is in ST0. 3144 // Note: fxch & fpop to get rid of ST1 3145 // (otherwise FPU stack could overflow eventually) 3146 fxch(1); 3147 fpop(); 3148 } 3149 3150 3151 void MacroAssembler::incrementl(AddressLiteral dst) { 3152 if (reachable(dst)) { 3153 incrementl(as_Address(dst)); 3154 } else { 3155 lea(rscratch1, dst); 3156 incrementl(Address(rscratch1, 0)); 3157 } 3158 } 3159 3160 void MacroAssembler::incrementl(ArrayAddress dst) { 3161 incrementl(as_Address(dst)); 3162 } 3163 3164 void MacroAssembler::incrementl(Register reg, int value) { 3165 if (value == min_jint) {addl(reg, value) ; return; } 3166 if (value < 0) { decrementl(reg, -value); return; } 3167 if (value == 0) { ; return; } 3168 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3169 /* else */ { addl(reg, value) ; return; } 3170 } 3171 3172 void MacroAssembler::incrementl(Address dst, int value) { 3173 if (value == min_jint) {addl(dst, value) ; return; } 3174 if (value < 0) { decrementl(dst, -value); return; } 3175 if (value == 0) { ; return; } 3176 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3177 /* else */ { addl(dst, value) ; return; } 3178 } 3179 3180 void MacroAssembler::jump(AddressLiteral dst) { 3181 if (reachable(dst)) { 3182 jmp_literal(dst.target(), dst.rspec()); 3183 } else { 3184 lea(rscratch1, dst); 3185 jmp(rscratch1); 3186 } 3187 } 3188 3189 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3190 if (reachable(dst)) { 3191 InstructionMark im(this); 3192 relocate(dst.reloc()); 3193 const int short_size = 2; 3194 const int long_size = 6; 3195 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3196 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3197 // 0111 tttn #8-bit disp 3198 emit_int8(0x70 | cc); 3199 emit_int8((offs - short_size) & 0xFF); 3200 } else { 3201 // 0000 1111 1000 tttn #32-bit disp 3202 emit_int8(0x0F); 3203 emit_int8((unsigned char)(0x80 | cc)); 3204 emit_int32(offs - long_size); 3205 } 3206 } else { 3207 #ifdef ASSERT 3208 warning("reversing conditional branch"); 3209 #endif /* ASSERT */ 3210 Label skip; 3211 jccb(reverse[cc], skip); 3212 lea(rscratch1, dst); 3213 Assembler::jmp(rscratch1); 3214 bind(skip); 3215 } 3216 } 3217 3218 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3219 if (reachable(src)) { 3220 Assembler::ldmxcsr(as_Address(src)); 3221 } else { 3222 lea(rscratch1, src); 3223 Assembler::ldmxcsr(Address(rscratch1, 0)); 3224 } 3225 } 3226 3227 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3228 int off; 3229 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3230 off = offset(); 3231 movsbl(dst, src); // movsxb 3232 } else { 3233 off = load_unsigned_byte(dst, src); 3234 shll(dst, 24); 3235 sarl(dst, 24); 3236 } 3237 return off; 3238 } 3239 3240 // Note: load_signed_short used to be called load_signed_word. 3241 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3242 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3243 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3244 int MacroAssembler::load_signed_short(Register dst, Address src) { 3245 int off; 3246 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3247 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3248 // version but this is what 64bit has always done. This seems to imply 3249 // that users are only using 32bits worth. 3250 off = offset(); 3251 movswl(dst, src); // movsxw 3252 } else { 3253 off = load_unsigned_short(dst, src); 3254 shll(dst, 16); 3255 sarl(dst, 16); 3256 } 3257 return off; 3258 } 3259 3260 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3261 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3262 // and "3.9 Partial Register Penalties", p. 22). 3263 int off; 3264 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3265 off = offset(); 3266 movzbl(dst, src); // movzxb 3267 } else { 3268 xorl(dst, dst); 3269 off = offset(); 3270 movb(dst, src); 3271 } 3272 return off; 3273 } 3274 3275 // Note: load_unsigned_short used to be called load_unsigned_word. 3276 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3277 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3278 // and "3.9 Partial Register Penalties", p. 22). 3279 int off; 3280 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3281 off = offset(); 3282 movzwl(dst, src); // movzxw 3283 } else { 3284 xorl(dst, dst); 3285 off = offset(); 3286 movw(dst, src); 3287 } 3288 return off; 3289 } 3290 3291 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3292 switch (size_in_bytes) { 3293 #ifndef _LP64 3294 case 8: 3295 assert(dst2 != noreg, "second dest register required"); 3296 movl(dst, src); 3297 movl(dst2, src.plus_disp(BytesPerInt)); 3298 break; 3299 #else 3300 case 8: movq(dst, src); break; 3301 #endif 3302 case 4: movl(dst, src); break; 3303 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3304 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3305 default: ShouldNotReachHere(); 3306 } 3307 } 3308 3309 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3310 switch (size_in_bytes) { 3311 #ifndef _LP64 3312 case 8: 3313 assert(src2 != noreg, "second source register required"); 3314 movl(dst, src); 3315 movl(dst.plus_disp(BytesPerInt), src2); 3316 break; 3317 #else 3318 case 8: movq(dst, src); break; 3319 #endif 3320 case 4: movl(dst, src); break; 3321 case 2: movw(dst, src); break; 3322 case 1: movb(dst, src); break; 3323 default: ShouldNotReachHere(); 3324 } 3325 } 3326 3327 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3328 if (reachable(dst)) { 3329 movl(as_Address(dst), src); 3330 } else { 3331 lea(rscratch1, dst); 3332 movl(Address(rscratch1, 0), src); 3333 } 3334 } 3335 3336 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3337 if (reachable(src)) { 3338 movl(dst, as_Address(src)); 3339 } else { 3340 lea(rscratch1, src); 3341 movl(dst, Address(rscratch1, 0)); 3342 } 3343 } 3344 3345 // C++ bool manipulation 3346 3347 void MacroAssembler::movbool(Register dst, Address src) { 3348 if(sizeof(bool) == 1) 3349 movb(dst, src); 3350 else if(sizeof(bool) == 2) 3351 movw(dst, src); 3352 else if(sizeof(bool) == 4) 3353 movl(dst, src); 3354 else 3355 // unsupported 3356 ShouldNotReachHere(); 3357 } 3358 3359 void MacroAssembler::movbool(Address dst, bool boolconst) { 3360 if(sizeof(bool) == 1) 3361 movb(dst, (int) boolconst); 3362 else if(sizeof(bool) == 2) 3363 movw(dst, (int) boolconst); 3364 else if(sizeof(bool) == 4) 3365 movl(dst, (int) boolconst); 3366 else 3367 // unsupported 3368 ShouldNotReachHere(); 3369 } 3370 3371 void MacroAssembler::movbool(Address dst, Register src) { 3372 if(sizeof(bool) == 1) 3373 movb(dst, src); 3374 else if(sizeof(bool) == 2) 3375 movw(dst, src); 3376 else if(sizeof(bool) == 4) 3377 movl(dst, src); 3378 else 3379 // unsupported 3380 ShouldNotReachHere(); 3381 } 3382 3383 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3384 movb(as_Address(dst), src); 3385 } 3386 3387 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3388 if (reachable(src)) { 3389 movdl(dst, as_Address(src)); 3390 } else { 3391 lea(rscratch1, src); 3392 movdl(dst, Address(rscratch1, 0)); 3393 } 3394 } 3395 3396 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3397 if (reachable(src)) { 3398 movq(dst, as_Address(src)); 3399 } else { 3400 lea(rscratch1, src); 3401 movq(dst, Address(rscratch1, 0)); 3402 } 3403 } 3404 3405 void MacroAssembler::setvectmask(Register dst, Register src) { 3406 Assembler::movl(dst, 1); 3407 Assembler::shlxl(dst, dst, src); 3408 Assembler::decl(dst); 3409 Assembler::kmovdl(k1, dst); 3410 Assembler::movl(dst, src); 3411 } 3412 3413 void MacroAssembler::restorevectmask() { 3414 Assembler::knotwl(k1, k0); 3415 } 3416 3417 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3418 if (reachable(src)) { 3419 if (UseXmmLoadAndClearUpper) { 3420 movsd (dst, as_Address(src)); 3421 } else { 3422 movlpd(dst, as_Address(src)); 3423 } 3424 } else { 3425 lea(rscratch1, src); 3426 if (UseXmmLoadAndClearUpper) { 3427 movsd (dst, Address(rscratch1, 0)); 3428 } else { 3429 movlpd(dst, Address(rscratch1, 0)); 3430 } 3431 } 3432 } 3433 3434 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3435 if (reachable(src)) { 3436 movss(dst, as_Address(src)); 3437 } else { 3438 lea(rscratch1, src); 3439 movss(dst, Address(rscratch1, 0)); 3440 } 3441 } 3442 3443 void MacroAssembler::movptr(Register dst, Register src) { 3444 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3445 } 3446 3447 void MacroAssembler::movptr(Register dst, Address src) { 3448 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3449 } 3450 3451 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3452 void MacroAssembler::movptr(Register dst, intptr_t src) { 3453 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3454 } 3455 3456 void MacroAssembler::movptr(Address dst, Register src) { 3457 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3458 } 3459 3460 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 3461 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3462 Assembler::vextractf32x4(dst, src, 0); 3463 } else { 3464 Assembler::movdqu(dst, src); 3465 } 3466 } 3467 3468 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 3469 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3470 Assembler::vinsertf32x4(dst, dst, src, 0); 3471 } else { 3472 Assembler::movdqu(dst, src); 3473 } 3474 } 3475 3476 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 3477 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3478 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3479 } else { 3480 Assembler::movdqu(dst, src); 3481 } 3482 } 3483 3484 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) { 3485 if (reachable(src)) { 3486 movdqu(dst, as_Address(src)); 3487 } else { 3488 lea(rscratch1, src); 3489 movdqu(dst, Address(rscratch1, 0)); 3490 } 3491 } 3492 3493 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 3494 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3495 vextractf64x4_low(dst, src); 3496 } else { 3497 Assembler::vmovdqu(dst, src); 3498 } 3499 } 3500 3501 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 3502 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3503 vinsertf64x4_low(dst, src); 3504 } else { 3505 Assembler::vmovdqu(dst, src); 3506 } 3507 } 3508 3509 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 3510 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3511 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3512 } 3513 else { 3514 Assembler::vmovdqu(dst, src); 3515 } 3516 } 3517 3518 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) { 3519 if (reachable(src)) { 3520 vmovdqu(dst, as_Address(src)); 3521 } 3522 else { 3523 lea(rscratch1, src); 3524 vmovdqu(dst, Address(rscratch1, 0)); 3525 } 3526 } 3527 3528 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3529 if (reachable(src)) { 3530 Assembler::movdqa(dst, as_Address(src)); 3531 } else { 3532 lea(rscratch1, src); 3533 Assembler::movdqa(dst, Address(rscratch1, 0)); 3534 } 3535 } 3536 3537 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3538 if (reachable(src)) { 3539 Assembler::movsd(dst, as_Address(src)); 3540 } else { 3541 lea(rscratch1, src); 3542 Assembler::movsd(dst, Address(rscratch1, 0)); 3543 } 3544 } 3545 3546 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3547 if (reachable(src)) { 3548 Assembler::movss(dst, as_Address(src)); 3549 } else { 3550 lea(rscratch1, src); 3551 Assembler::movss(dst, Address(rscratch1, 0)); 3552 } 3553 } 3554 3555 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3556 if (reachable(src)) { 3557 Assembler::mulsd(dst, as_Address(src)); 3558 } else { 3559 lea(rscratch1, src); 3560 Assembler::mulsd(dst, Address(rscratch1, 0)); 3561 } 3562 } 3563 3564 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3565 if (reachable(src)) { 3566 Assembler::mulss(dst, as_Address(src)); 3567 } else { 3568 lea(rscratch1, src); 3569 Assembler::mulss(dst, Address(rscratch1, 0)); 3570 } 3571 } 3572 3573 void MacroAssembler::null_check(Register reg, int offset) { 3574 if (needs_explicit_null_check(offset)) { 3575 // provoke OS NULL exception if reg = NULL by 3576 // accessing M[reg] w/o changing any (non-CC) registers 3577 // NOTE: cmpl is plenty here to provoke a segv 3578 3579 if (ShenandoahVerifyReadsToFromSpace) { 3580 oopDesc::bs()->interpreter_read_barrier(this, reg); 3581 } 3582 3583 cmpptr(rax, Address(reg, 0)); 3584 // Note: should probably use testl(rax, Address(reg, 0)); 3585 // may be shorter code (however, this version of 3586 // testl needs to be implemented first) 3587 } else { 3588 // nothing to do, (later) access of M[reg + offset] 3589 // will provoke OS NULL exception if reg = NULL 3590 } 3591 } 3592 3593 void MacroAssembler::os_breakpoint() { 3594 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3595 // (e.g., MSVC can't call ps() otherwise) 3596 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3597 } 3598 3599 #ifdef _LP64 3600 #define XSTATE_BV 0x200 3601 #endif 3602 3603 void MacroAssembler::pop_CPU_state() { 3604 pop_FPU_state(); 3605 pop_IU_state(); 3606 } 3607 3608 void MacroAssembler::pop_FPU_state() { 3609 #ifndef _LP64 3610 frstor(Address(rsp, 0)); 3611 #else 3612 fxrstor(Address(rsp, 0)); 3613 #endif 3614 addptr(rsp, FPUStateSizeInWords * wordSize); 3615 } 3616 3617 void MacroAssembler::pop_IU_state() { 3618 popa(); 3619 LP64_ONLY(addq(rsp, 8)); 3620 popf(); 3621 } 3622 3623 // Save Integer and Float state 3624 // Warning: Stack must be 16 byte aligned (64bit) 3625 void MacroAssembler::push_CPU_state() { 3626 push_IU_state(); 3627 push_FPU_state(); 3628 } 3629 3630 void MacroAssembler::push_FPU_state() { 3631 subptr(rsp, FPUStateSizeInWords * wordSize); 3632 #ifndef _LP64 3633 fnsave(Address(rsp, 0)); 3634 fwait(); 3635 #else 3636 fxsave(Address(rsp, 0)); 3637 #endif // LP64 3638 } 3639 3640 void MacroAssembler::push_IU_state() { 3641 // Push flags first because pusha kills them 3642 pushf(); 3643 // Make sure rsp stays 16-byte aligned 3644 LP64_ONLY(subq(rsp, 8)); 3645 pusha(); 3646 } 3647 3648 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register 3649 if (!java_thread->is_valid()) { 3650 java_thread = rdi; 3651 get_thread(java_thread); 3652 } 3653 // we must set sp to zero to clear frame 3654 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3655 if (clear_fp) { 3656 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3657 } 3658 3659 // Always clear the pc because it could have been set by make_walkable() 3660 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3661 3662 } 3663 3664 void MacroAssembler::restore_rax(Register tmp) { 3665 if (tmp == noreg) pop(rax); 3666 else if (tmp != rax) mov(rax, tmp); 3667 } 3668 3669 void MacroAssembler::round_to(Register reg, int modulus) { 3670 addptr(reg, modulus - 1); 3671 andptr(reg, -modulus); 3672 } 3673 3674 void MacroAssembler::save_rax(Register tmp) { 3675 if (tmp == noreg) push(rax); 3676 else if (tmp != rax) mov(tmp, rax); 3677 } 3678 3679 // Write serialization page so VM thread can do a pseudo remote membar. 3680 // We use the current thread pointer to calculate a thread specific 3681 // offset to write to within the page. This minimizes bus traffic 3682 // due to cache line collision. 3683 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3684 movl(tmp, thread); 3685 shrl(tmp, os::get_serialize_page_shift_count()); 3686 andl(tmp, (os::vm_page_size() - sizeof(int))); 3687 3688 Address index(noreg, tmp, Address::times_1); 3689 ExternalAddress page(os::get_memory_serialize_page()); 3690 3691 // Size of store must match masking code above 3692 movl(as_Address(ArrayAddress(page, index)), tmp); 3693 } 3694 3695 // Special Shenandoah CAS implementation that handles false negatives 3696 // due to concurrent evacuation. 3697 void MacroAssembler::cmpxchg_oop_shenandoah(Register res, Address addr, Register oldval, Register newval, 3698 bool exchange, 3699 Register tmp1, Register tmp2) { 3700 assert (UseShenandoahGC, "Should only be used with Shenandoah"); 3701 assert(oldval == rax, "must be in rax for implicit use in cmpxchg"); 3702 3703 Label retry, done; 3704 3705 // Remember oldval for retry logic below 3706 if (UseCompressedOops) { 3707 movl(tmp1, oldval); 3708 } else { 3709 movptr(tmp1, oldval); 3710 } 3711 3712 // Step 1. Try to CAS with given arguments. If successful, then we are done, 3713 // and can safely return. 3714 if (os::is_MP()) lock(); 3715 if (UseCompressedOops) { 3716 cmpxchgl(newval, addr); 3717 } else { 3718 cmpxchgptr(newval, addr); 3719 } 3720 jcc(Assembler::equal, done, true); 3721 3722 // Step 2. CAS had failed. This may be a false negative. 3723 // 3724 // The trouble comes when we compare the to-space pointer with the from-space 3725 // pointer to the same object. To resolve this, it will suffice to read both 3726 // oldval and the value from memory through the read barriers -- this will give 3727 // both to-space pointers. If they mismatch, then it was a legitimate failure. 3728 // 3729 if (UseCompressedOops) { 3730 decode_heap_oop(tmp1); 3731 } 3732 oopDesc::bs()->interpreter_read_barrier(this, tmp1); 3733 3734 if (UseCompressedOops) { 3735 movl(tmp2, oldval); 3736 decode_heap_oop(tmp2); 3737 } else { 3738 movptr(tmp2, oldval); 3739 } 3740 oopDesc::bs()->interpreter_read_barrier(this, tmp2); 3741 3742 cmpptr(tmp1, tmp2); 3743 jcc(Assembler::notEqual, done, true); 3744 3745 // Step 3. Try to CAS again with resolved to-space pointers. 3746 // 3747 // Corner case: it may happen that somebody stored the from-space pointer 3748 // to memory while we were preparing for retry. Therefore, we can fail again 3749 // on retry, and so need to do this in loop, always re-reading the failure 3750 // witness through the read barrier. 3751 bind(retry); 3752 if (os::is_MP()) lock(); 3753 if (UseCompressedOops) { 3754 cmpxchgl(newval, addr); 3755 } else { 3756 cmpxchgptr(newval, addr); 3757 } 3758 jcc(Assembler::equal, done, true); 3759 3760 if (UseCompressedOops) { 3761 movl(tmp2, oldval); 3762 decode_heap_oop(tmp2); 3763 } else { 3764 movptr(tmp2, oldval); 3765 } 3766 oopDesc::bs()->interpreter_read_barrier(this, tmp2); 3767 3768 cmpptr(tmp1, tmp2); 3769 jcc(Assembler::equal, retry, true); 3770 3771 // Step 4. If we need a boolean result out of CAS, check the flag again, 3772 // and promote the result. Note that we handle the flag from both the CAS 3773 // itself and from the retry loop. 3774 bind(done); 3775 if (!exchange) { 3776 setb(Assembler::equal, res); 3777 movzbl(res, res); 3778 } 3779 } 3780 3781 // Calls to C land 3782 // 3783 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3784 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3785 // has to be reset to 0. This is required to allow proper stack traversal. 3786 void MacroAssembler::set_last_Java_frame(Register java_thread, 3787 Register last_java_sp, 3788 Register last_java_fp, 3789 address last_java_pc) { 3790 // determine java_thread register 3791 if (!java_thread->is_valid()) { 3792 java_thread = rdi; 3793 get_thread(java_thread); 3794 } 3795 // determine last_java_sp register 3796 if (!last_java_sp->is_valid()) { 3797 last_java_sp = rsp; 3798 } 3799 3800 // last_java_fp is optional 3801 3802 if (last_java_fp->is_valid()) { 3803 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3804 } 3805 3806 // last_java_pc is optional 3807 3808 if (last_java_pc != NULL) { 3809 lea(Address(java_thread, 3810 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3811 InternalAddress(last_java_pc)); 3812 3813 } 3814 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3815 } 3816 3817 void MacroAssembler::shlptr(Register dst, int imm8) { 3818 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3819 } 3820 3821 void MacroAssembler::shrptr(Register dst, int imm8) { 3822 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3823 } 3824 3825 void MacroAssembler::sign_extend_byte(Register reg) { 3826 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3827 movsbl(reg, reg); // movsxb 3828 } else { 3829 shll(reg, 24); 3830 sarl(reg, 24); 3831 } 3832 } 3833 3834 void MacroAssembler::sign_extend_short(Register reg) { 3835 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3836 movswl(reg, reg); // movsxw 3837 } else { 3838 shll(reg, 16); 3839 sarl(reg, 16); 3840 } 3841 } 3842 3843 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3844 assert(reachable(src), "Address should be reachable"); 3845 testl(dst, as_Address(src)); 3846 } 3847 3848 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3849 int dst_enc = dst->encoding(); 3850 int src_enc = src->encoding(); 3851 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3852 Assembler::pcmpeqb(dst, src); 3853 } else if ((dst_enc < 16) && (src_enc < 16)) { 3854 Assembler::pcmpeqb(dst, src); 3855 } else if (src_enc < 16) { 3856 subptr(rsp, 64); 3857 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3858 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3859 Assembler::pcmpeqb(xmm0, src); 3860 movdqu(dst, xmm0); 3861 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3862 addptr(rsp, 64); 3863 } else if (dst_enc < 16) { 3864 subptr(rsp, 64); 3865 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3866 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3867 Assembler::pcmpeqb(dst, xmm0); 3868 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3869 addptr(rsp, 64); 3870 } else { 3871 subptr(rsp, 64); 3872 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3873 subptr(rsp, 64); 3874 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3875 movdqu(xmm0, src); 3876 movdqu(xmm1, dst); 3877 Assembler::pcmpeqb(xmm1, xmm0); 3878 movdqu(dst, xmm1); 3879 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3880 addptr(rsp, 64); 3881 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3882 addptr(rsp, 64); 3883 } 3884 } 3885 3886 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3887 int dst_enc = dst->encoding(); 3888 int src_enc = src->encoding(); 3889 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3890 Assembler::pcmpeqw(dst, src); 3891 } else if ((dst_enc < 16) && (src_enc < 16)) { 3892 Assembler::pcmpeqw(dst, src); 3893 } else if (src_enc < 16) { 3894 subptr(rsp, 64); 3895 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3896 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3897 Assembler::pcmpeqw(xmm0, src); 3898 movdqu(dst, xmm0); 3899 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3900 addptr(rsp, 64); 3901 } else if (dst_enc < 16) { 3902 subptr(rsp, 64); 3903 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3904 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3905 Assembler::pcmpeqw(dst, xmm0); 3906 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3907 addptr(rsp, 64); 3908 } else { 3909 subptr(rsp, 64); 3910 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3911 subptr(rsp, 64); 3912 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3913 movdqu(xmm0, src); 3914 movdqu(xmm1, dst); 3915 Assembler::pcmpeqw(xmm1, xmm0); 3916 movdqu(dst, xmm1); 3917 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3918 addptr(rsp, 64); 3919 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3920 addptr(rsp, 64); 3921 } 3922 } 3923 3924 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3925 int dst_enc = dst->encoding(); 3926 if (dst_enc < 16) { 3927 Assembler::pcmpestri(dst, src, imm8); 3928 } else { 3929 subptr(rsp, 64); 3930 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3931 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3932 Assembler::pcmpestri(xmm0, src, imm8); 3933 movdqu(dst, xmm0); 3934 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3935 addptr(rsp, 64); 3936 } 3937 } 3938 3939 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3940 int dst_enc = dst->encoding(); 3941 int src_enc = src->encoding(); 3942 if ((dst_enc < 16) && (src_enc < 16)) { 3943 Assembler::pcmpestri(dst, src, imm8); 3944 } else if (src_enc < 16) { 3945 subptr(rsp, 64); 3946 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3947 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3948 Assembler::pcmpestri(xmm0, src, imm8); 3949 movdqu(dst, xmm0); 3950 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3951 addptr(rsp, 64); 3952 } else if (dst_enc < 16) { 3953 subptr(rsp, 64); 3954 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3955 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3956 Assembler::pcmpestri(dst, xmm0, imm8); 3957 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3958 addptr(rsp, 64); 3959 } else { 3960 subptr(rsp, 64); 3961 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3962 subptr(rsp, 64); 3963 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3964 movdqu(xmm0, src); 3965 movdqu(xmm1, dst); 3966 Assembler::pcmpestri(xmm1, xmm0, imm8); 3967 movdqu(dst, xmm1); 3968 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3969 addptr(rsp, 64); 3970 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3971 addptr(rsp, 64); 3972 } 3973 } 3974 3975 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3976 int dst_enc = dst->encoding(); 3977 int src_enc = src->encoding(); 3978 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3979 Assembler::pmovzxbw(dst, src); 3980 } else if ((dst_enc < 16) && (src_enc < 16)) { 3981 Assembler::pmovzxbw(dst, src); 3982 } else if (src_enc < 16) { 3983 subptr(rsp, 64); 3984 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3985 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3986 Assembler::pmovzxbw(xmm0, src); 3987 movdqu(dst, xmm0); 3988 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3989 addptr(rsp, 64); 3990 } else if (dst_enc < 16) { 3991 subptr(rsp, 64); 3992 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3993 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3994 Assembler::pmovzxbw(dst, xmm0); 3995 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3996 addptr(rsp, 64); 3997 } else { 3998 subptr(rsp, 64); 3999 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4000 subptr(rsp, 64); 4001 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4002 movdqu(xmm0, src); 4003 movdqu(xmm1, dst); 4004 Assembler::pmovzxbw(xmm1, xmm0); 4005 movdqu(dst, xmm1); 4006 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4007 addptr(rsp, 64); 4008 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4009 addptr(rsp, 64); 4010 } 4011 } 4012 4013 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 4014 int dst_enc = dst->encoding(); 4015 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4016 Assembler::pmovzxbw(dst, src); 4017 } else if (dst_enc < 16) { 4018 Assembler::pmovzxbw(dst, src); 4019 } else { 4020 subptr(rsp, 64); 4021 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4022 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4023 Assembler::pmovzxbw(xmm0, src); 4024 movdqu(dst, xmm0); 4025 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4026 addptr(rsp, 64); 4027 } 4028 } 4029 4030 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 4031 int src_enc = src->encoding(); 4032 if (src_enc < 16) { 4033 Assembler::pmovmskb(dst, src); 4034 } else { 4035 subptr(rsp, 64); 4036 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4037 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4038 Assembler::pmovmskb(dst, xmm0); 4039 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4040 addptr(rsp, 64); 4041 } 4042 } 4043 4044 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 4045 int dst_enc = dst->encoding(); 4046 int src_enc = src->encoding(); 4047 if ((dst_enc < 16) && (src_enc < 16)) { 4048 Assembler::ptest(dst, src); 4049 } else if (src_enc < 16) { 4050 subptr(rsp, 64); 4051 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4052 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4053 Assembler::ptest(xmm0, src); 4054 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4055 addptr(rsp, 64); 4056 } else if (dst_enc < 16) { 4057 subptr(rsp, 64); 4058 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4059 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4060 Assembler::ptest(dst, xmm0); 4061 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4062 addptr(rsp, 64); 4063 } else { 4064 subptr(rsp, 64); 4065 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4066 subptr(rsp, 64); 4067 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4068 movdqu(xmm0, src); 4069 movdqu(xmm1, dst); 4070 Assembler::ptest(xmm1, xmm0); 4071 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4072 addptr(rsp, 64); 4073 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4074 addptr(rsp, 64); 4075 } 4076 } 4077 4078 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 4079 if (reachable(src)) { 4080 Assembler::sqrtsd(dst, as_Address(src)); 4081 } else { 4082 lea(rscratch1, src); 4083 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 4084 } 4085 } 4086 4087 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 4088 if (reachable(src)) { 4089 Assembler::sqrtss(dst, as_Address(src)); 4090 } else { 4091 lea(rscratch1, src); 4092 Assembler::sqrtss(dst, Address(rscratch1, 0)); 4093 } 4094 } 4095 4096 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 4097 if (reachable(src)) { 4098 Assembler::subsd(dst, as_Address(src)); 4099 } else { 4100 lea(rscratch1, src); 4101 Assembler::subsd(dst, Address(rscratch1, 0)); 4102 } 4103 } 4104 4105 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 4106 if (reachable(src)) { 4107 Assembler::subss(dst, as_Address(src)); 4108 } else { 4109 lea(rscratch1, src); 4110 Assembler::subss(dst, Address(rscratch1, 0)); 4111 } 4112 } 4113 4114 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 4115 if (reachable(src)) { 4116 Assembler::ucomisd(dst, as_Address(src)); 4117 } else { 4118 lea(rscratch1, src); 4119 Assembler::ucomisd(dst, Address(rscratch1, 0)); 4120 } 4121 } 4122 4123 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 4124 if (reachable(src)) { 4125 Assembler::ucomiss(dst, as_Address(src)); 4126 } else { 4127 lea(rscratch1, src); 4128 Assembler::ucomiss(dst, Address(rscratch1, 0)); 4129 } 4130 } 4131 4132 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 4133 // Used in sign-bit flipping with aligned address. 4134 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4135 if (reachable(src)) { 4136 Assembler::xorpd(dst, as_Address(src)); 4137 } else { 4138 lea(rscratch1, src); 4139 Assembler::xorpd(dst, Address(rscratch1, 0)); 4140 } 4141 } 4142 4143 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 4144 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4145 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4146 } 4147 else { 4148 Assembler::xorpd(dst, src); 4149 } 4150 } 4151 4152 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 4153 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4154 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4155 } else { 4156 Assembler::xorps(dst, src); 4157 } 4158 } 4159 4160 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 4161 // Used in sign-bit flipping with aligned address. 4162 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4163 if (reachable(src)) { 4164 Assembler::xorps(dst, as_Address(src)); 4165 } else { 4166 lea(rscratch1, src); 4167 Assembler::xorps(dst, Address(rscratch1, 0)); 4168 } 4169 } 4170 4171 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 4172 // Used in sign-bit flipping with aligned address. 4173 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 4174 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 4175 if (reachable(src)) { 4176 Assembler::pshufb(dst, as_Address(src)); 4177 } else { 4178 lea(rscratch1, src); 4179 Assembler::pshufb(dst, Address(rscratch1, 0)); 4180 } 4181 } 4182 4183 // AVX 3-operands instructions 4184 4185 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4186 if (reachable(src)) { 4187 vaddsd(dst, nds, as_Address(src)); 4188 } else { 4189 lea(rscratch1, src); 4190 vaddsd(dst, nds, Address(rscratch1, 0)); 4191 } 4192 } 4193 4194 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4195 if (reachable(src)) { 4196 vaddss(dst, nds, as_Address(src)); 4197 } else { 4198 lea(rscratch1, src); 4199 vaddss(dst, nds, Address(rscratch1, 0)); 4200 } 4201 } 4202 4203 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4204 int dst_enc = dst->encoding(); 4205 int nds_enc = nds->encoding(); 4206 int src_enc = src->encoding(); 4207 if ((dst_enc < 16) && (nds_enc < 16)) { 4208 vandps(dst, nds, negate_field, vector_len); 4209 } else if ((src_enc < 16) && (dst_enc < 16)) { 4210 movss(src, nds); 4211 vandps(dst, src, negate_field, vector_len); 4212 } else if (src_enc < 16) { 4213 movss(src, nds); 4214 vandps(src, src, negate_field, vector_len); 4215 movss(dst, src); 4216 } else if (dst_enc < 16) { 4217 movdqu(src, xmm0); 4218 movss(xmm0, nds); 4219 vandps(dst, xmm0, negate_field, vector_len); 4220 movdqu(xmm0, src); 4221 } else if (nds_enc < 16) { 4222 movdqu(src, xmm0); 4223 vandps(xmm0, nds, negate_field, vector_len); 4224 movss(dst, xmm0); 4225 movdqu(xmm0, src); 4226 } else { 4227 movdqu(src, xmm0); 4228 movss(xmm0, nds); 4229 vandps(xmm0, xmm0, negate_field, vector_len); 4230 movss(dst, xmm0); 4231 movdqu(xmm0, src); 4232 } 4233 } 4234 4235 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4236 int dst_enc = dst->encoding(); 4237 int nds_enc = nds->encoding(); 4238 int src_enc = src->encoding(); 4239 if ((dst_enc < 16) && (nds_enc < 16)) { 4240 vandpd(dst, nds, negate_field, vector_len); 4241 } else if ((src_enc < 16) && (dst_enc < 16)) { 4242 movsd(src, nds); 4243 vandpd(dst, src, negate_field, vector_len); 4244 } else if (src_enc < 16) { 4245 movsd(src, nds); 4246 vandpd(src, src, negate_field, vector_len); 4247 movsd(dst, src); 4248 } else if (dst_enc < 16) { 4249 movdqu(src, xmm0); 4250 movsd(xmm0, nds); 4251 vandpd(dst, xmm0, negate_field, vector_len); 4252 movdqu(xmm0, src); 4253 } else if (nds_enc < 16) { 4254 movdqu(src, xmm0); 4255 vandpd(xmm0, nds, negate_field, vector_len); 4256 movsd(dst, xmm0); 4257 movdqu(xmm0, src); 4258 } else { 4259 movdqu(src, xmm0); 4260 movsd(xmm0, nds); 4261 vandpd(xmm0, xmm0, negate_field, vector_len); 4262 movsd(dst, xmm0); 4263 movdqu(xmm0, src); 4264 } 4265 } 4266 4267 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4268 int dst_enc = dst->encoding(); 4269 int nds_enc = nds->encoding(); 4270 int src_enc = src->encoding(); 4271 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4272 Assembler::vpaddb(dst, nds, src, vector_len); 4273 } else if ((dst_enc < 16) && (src_enc < 16)) { 4274 Assembler::vpaddb(dst, dst, src, vector_len); 4275 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4276 // use nds as scratch for src 4277 evmovdqul(nds, src, Assembler::AVX_512bit); 4278 Assembler::vpaddb(dst, dst, nds, vector_len); 4279 } else if ((src_enc < 16) && (nds_enc < 16)) { 4280 // use nds as scratch for dst 4281 evmovdqul(nds, dst, Assembler::AVX_512bit); 4282 Assembler::vpaddb(nds, nds, src, vector_len); 4283 evmovdqul(dst, nds, Assembler::AVX_512bit); 4284 } else if (dst_enc < 16) { 4285 // use nds as scatch for xmm0 to hold src 4286 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4287 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4288 Assembler::vpaddb(dst, dst, xmm0, vector_len); 4289 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4290 } else { 4291 // worse case scenario, all regs are in the upper bank 4292 subptr(rsp, 64); 4293 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4294 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4295 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4296 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4297 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len); 4298 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4299 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4300 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4301 addptr(rsp, 64); 4302 } 4303 } 4304 4305 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4306 int dst_enc = dst->encoding(); 4307 int nds_enc = nds->encoding(); 4308 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4309 Assembler::vpaddb(dst, nds, src, vector_len); 4310 } else if (dst_enc < 16) { 4311 Assembler::vpaddb(dst, dst, src, vector_len); 4312 } else if (nds_enc < 16) { 4313 // implies dst_enc in upper bank with src as scratch 4314 evmovdqul(nds, dst, Assembler::AVX_512bit); 4315 Assembler::vpaddb(nds, nds, src, vector_len); 4316 evmovdqul(dst, nds, Assembler::AVX_512bit); 4317 } else { 4318 // worse case scenario, all regs in upper bank 4319 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4320 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4321 Assembler::vpaddb(xmm0, xmm0, src, vector_len); 4322 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4323 } 4324 } 4325 4326 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4327 int dst_enc = dst->encoding(); 4328 int nds_enc = nds->encoding(); 4329 int src_enc = src->encoding(); 4330 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4331 Assembler::vpaddw(dst, nds, src, vector_len); 4332 } else if ((dst_enc < 16) && (src_enc < 16)) { 4333 Assembler::vpaddw(dst, dst, src, vector_len); 4334 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4335 // use nds as scratch for src 4336 evmovdqul(nds, src, Assembler::AVX_512bit); 4337 Assembler::vpaddw(dst, dst, nds, vector_len); 4338 } else if ((src_enc < 16) && (nds_enc < 16)) { 4339 // use nds as scratch for dst 4340 evmovdqul(nds, dst, Assembler::AVX_512bit); 4341 Assembler::vpaddw(nds, nds, src, vector_len); 4342 evmovdqul(dst, nds, Assembler::AVX_512bit); 4343 } else if (dst_enc < 16) { 4344 // use nds as scatch for xmm0 to hold src 4345 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4346 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4347 Assembler::vpaddw(dst, dst, xmm0, vector_len); 4348 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4349 } else { 4350 // worse case scenario, all regs are in the upper bank 4351 subptr(rsp, 64); 4352 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4353 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4354 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4355 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4356 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len); 4357 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4358 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4359 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4360 addptr(rsp, 64); 4361 } 4362 } 4363 4364 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4365 int dst_enc = dst->encoding(); 4366 int nds_enc = nds->encoding(); 4367 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4368 Assembler::vpaddw(dst, nds, src, vector_len); 4369 } else if (dst_enc < 16) { 4370 Assembler::vpaddw(dst, dst, src, vector_len); 4371 } else if (nds_enc < 16) { 4372 // implies dst_enc in upper bank with src as scratch 4373 evmovdqul(nds, dst, Assembler::AVX_512bit); 4374 Assembler::vpaddw(nds, nds, src, vector_len); 4375 evmovdqul(dst, nds, Assembler::AVX_512bit); 4376 } else { 4377 // worse case scenario, all regs in upper bank 4378 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4379 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4380 Assembler::vpaddw(xmm0, xmm0, src, vector_len); 4381 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4382 } 4383 } 4384 4385 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 4386 int dst_enc = dst->encoding(); 4387 int src_enc = src->encoding(); 4388 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4389 Assembler::vpbroadcastw(dst, src); 4390 } else if ((dst_enc < 16) && (src_enc < 16)) { 4391 Assembler::vpbroadcastw(dst, src); 4392 } else if (src_enc < 16) { 4393 subptr(rsp, 64); 4394 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4395 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4396 Assembler::vpbroadcastw(xmm0, src); 4397 movdqu(dst, xmm0); 4398 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4399 addptr(rsp, 64); 4400 } else if (dst_enc < 16) { 4401 subptr(rsp, 64); 4402 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4403 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4404 Assembler::vpbroadcastw(dst, xmm0); 4405 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4406 addptr(rsp, 64); 4407 } else { 4408 subptr(rsp, 64); 4409 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4410 subptr(rsp, 64); 4411 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4412 movdqu(xmm0, src); 4413 movdqu(xmm1, dst); 4414 Assembler::vpbroadcastw(xmm1, xmm0); 4415 movdqu(dst, xmm1); 4416 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4417 addptr(rsp, 64); 4418 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4419 addptr(rsp, 64); 4420 } 4421 } 4422 4423 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4424 int dst_enc = dst->encoding(); 4425 int nds_enc = nds->encoding(); 4426 int src_enc = src->encoding(); 4427 assert(dst_enc == nds_enc, ""); 4428 if ((dst_enc < 16) && (src_enc < 16)) { 4429 Assembler::vpcmpeqb(dst, nds, src, vector_len); 4430 } else if (src_enc < 16) { 4431 subptr(rsp, 64); 4432 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4433 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4434 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len); 4435 movdqu(dst, xmm0); 4436 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4437 addptr(rsp, 64); 4438 } else if (dst_enc < 16) { 4439 subptr(rsp, 64); 4440 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4441 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4442 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len); 4443 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4444 addptr(rsp, 64); 4445 } else { 4446 subptr(rsp, 64); 4447 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4448 subptr(rsp, 64); 4449 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4450 movdqu(xmm0, src); 4451 movdqu(xmm1, dst); 4452 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len); 4453 movdqu(dst, xmm1); 4454 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4455 addptr(rsp, 64); 4456 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4457 addptr(rsp, 64); 4458 } 4459 } 4460 4461 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4462 int dst_enc = dst->encoding(); 4463 int nds_enc = nds->encoding(); 4464 int src_enc = src->encoding(); 4465 assert(dst_enc == nds_enc, ""); 4466 if ((dst_enc < 16) && (src_enc < 16)) { 4467 Assembler::vpcmpeqw(dst, nds, src, vector_len); 4468 } else if (src_enc < 16) { 4469 subptr(rsp, 64); 4470 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4471 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4472 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len); 4473 movdqu(dst, xmm0); 4474 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4475 addptr(rsp, 64); 4476 } else if (dst_enc < 16) { 4477 subptr(rsp, 64); 4478 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4479 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4480 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len); 4481 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4482 addptr(rsp, 64); 4483 } else { 4484 subptr(rsp, 64); 4485 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4486 subptr(rsp, 64); 4487 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4488 movdqu(xmm0, src); 4489 movdqu(xmm1, dst); 4490 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len); 4491 movdqu(dst, xmm1); 4492 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4493 addptr(rsp, 64); 4494 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4495 addptr(rsp, 64); 4496 } 4497 } 4498 4499 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 4500 int dst_enc = dst->encoding(); 4501 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4502 Assembler::vpmovzxbw(dst, src, vector_len); 4503 } else if (dst_enc < 16) { 4504 Assembler::vpmovzxbw(dst, src, vector_len); 4505 } else { 4506 subptr(rsp, 64); 4507 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4508 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4509 Assembler::vpmovzxbw(xmm0, src, vector_len); 4510 movdqu(dst, xmm0); 4511 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4512 addptr(rsp, 64); 4513 } 4514 } 4515 4516 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) { 4517 int src_enc = src->encoding(); 4518 if (src_enc < 16) { 4519 Assembler::vpmovmskb(dst, src); 4520 } else { 4521 subptr(rsp, 64); 4522 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4523 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4524 Assembler::vpmovmskb(dst, xmm0); 4525 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4526 addptr(rsp, 64); 4527 } 4528 } 4529 4530 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4531 int dst_enc = dst->encoding(); 4532 int nds_enc = nds->encoding(); 4533 int src_enc = src->encoding(); 4534 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4535 Assembler::vpmullw(dst, nds, src, vector_len); 4536 } else if ((dst_enc < 16) && (src_enc < 16)) { 4537 Assembler::vpmullw(dst, dst, src, vector_len); 4538 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4539 // use nds as scratch for src 4540 evmovdqul(nds, src, Assembler::AVX_512bit); 4541 Assembler::vpmullw(dst, dst, nds, vector_len); 4542 } else if ((src_enc < 16) && (nds_enc < 16)) { 4543 // use nds as scratch for dst 4544 evmovdqul(nds, dst, Assembler::AVX_512bit); 4545 Assembler::vpmullw(nds, nds, src, vector_len); 4546 evmovdqul(dst, nds, Assembler::AVX_512bit); 4547 } else if (dst_enc < 16) { 4548 // use nds as scatch for xmm0 to hold src 4549 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4550 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4551 Assembler::vpmullw(dst, dst, xmm0, vector_len); 4552 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4553 } else { 4554 // worse case scenario, all regs are in the upper bank 4555 subptr(rsp, 64); 4556 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4557 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4558 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4559 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4560 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len); 4561 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4562 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4563 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4564 addptr(rsp, 64); 4565 } 4566 } 4567 4568 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4569 int dst_enc = dst->encoding(); 4570 int nds_enc = nds->encoding(); 4571 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4572 Assembler::vpmullw(dst, nds, src, vector_len); 4573 } else if (dst_enc < 16) { 4574 Assembler::vpmullw(dst, dst, src, vector_len); 4575 } else if (nds_enc < 16) { 4576 // implies dst_enc in upper bank with src as scratch 4577 evmovdqul(nds, dst, Assembler::AVX_512bit); 4578 Assembler::vpmullw(nds, nds, src, vector_len); 4579 evmovdqul(dst, nds, Assembler::AVX_512bit); 4580 } else { 4581 // worse case scenario, all regs in upper bank 4582 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4583 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4584 Assembler::vpmullw(xmm0, xmm0, src, vector_len); 4585 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4586 } 4587 } 4588 4589 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4590 int dst_enc = dst->encoding(); 4591 int nds_enc = nds->encoding(); 4592 int src_enc = src->encoding(); 4593 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4594 Assembler::vpsubb(dst, nds, src, vector_len); 4595 } else if ((dst_enc < 16) && (src_enc < 16)) { 4596 Assembler::vpsubb(dst, dst, src, vector_len); 4597 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4598 // use nds as scratch for src 4599 evmovdqul(nds, src, Assembler::AVX_512bit); 4600 Assembler::vpsubb(dst, dst, nds, vector_len); 4601 } else if ((src_enc < 16) && (nds_enc < 16)) { 4602 // use nds as scratch for dst 4603 evmovdqul(nds, dst, Assembler::AVX_512bit); 4604 Assembler::vpsubb(nds, nds, src, vector_len); 4605 evmovdqul(dst, nds, Assembler::AVX_512bit); 4606 } else if (dst_enc < 16) { 4607 // use nds as scatch for xmm0 to hold src 4608 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4609 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4610 Assembler::vpsubb(dst, dst, xmm0, vector_len); 4611 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4612 } else { 4613 // worse case scenario, all regs are in the upper bank 4614 subptr(rsp, 64); 4615 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4616 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4617 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4618 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4619 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len); 4620 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4621 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4622 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4623 addptr(rsp, 64); 4624 } 4625 } 4626 4627 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4628 int dst_enc = dst->encoding(); 4629 int nds_enc = nds->encoding(); 4630 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4631 Assembler::vpsubb(dst, nds, src, vector_len); 4632 } else if (dst_enc < 16) { 4633 Assembler::vpsubb(dst, dst, src, vector_len); 4634 } else if (nds_enc < 16) { 4635 // implies dst_enc in upper bank with src as scratch 4636 evmovdqul(nds, dst, Assembler::AVX_512bit); 4637 Assembler::vpsubb(nds, nds, src, vector_len); 4638 evmovdqul(dst, nds, Assembler::AVX_512bit); 4639 } else { 4640 // worse case scenario, all regs in upper bank 4641 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4642 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4643 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4644 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4645 } 4646 } 4647 4648 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4649 int dst_enc = dst->encoding(); 4650 int nds_enc = nds->encoding(); 4651 int src_enc = src->encoding(); 4652 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4653 Assembler::vpsubw(dst, nds, src, vector_len); 4654 } else if ((dst_enc < 16) && (src_enc < 16)) { 4655 Assembler::vpsubw(dst, dst, src, vector_len); 4656 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4657 // use nds as scratch for src 4658 evmovdqul(nds, src, Assembler::AVX_512bit); 4659 Assembler::vpsubw(dst, dst, nds, vector_len); 4660 } else if ((src_enc < 16) && (nds_enc < 16)) { 4661 // use nds as scratch for dst 4662 evmovdqul(nds, dst, Assembler::AVX_512bit); 4663 Assembler::vpsubw(nds, nds, src, vector_len); 4664 evmovdqul(dst, nds, Assembler::AVX_512bit); 4665 } else if (dst_enc < 16) { 4666 // use nds as scatch for xmm0 to hold src 4667 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4668 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4669 Assembler::vpsubw(dst, dst, xmm0, vector_len); 4670 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4671 } else { 4672 // worse case scenario, all regs are in the upper bank 4673 subptr(rsp, 64); 4674 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4675 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4676 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4677 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4678 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len); 4679 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4680 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4681 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4682 addptr(rsp, 64); 4683 } 4684 } 4685 4686 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4687 int dst_enc = dst->encoding(); 4688 int nds_enc = nds->encoding(); 4689 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4690 Assembler::vpsubw(dst, nds, src, vector_len); 4691 } else if (dst_enc < 16) { 4692 Assembler::vpsubw(dst, dst, src, vector_len); 4693 } else if (nds_enc < 16) { 4694 // implies dst_enc in upper bank with src as scratch 4695 evmovdqul(nds, dst, Assembler::AVX_512bit); 4696 Assembler::vpsubw(nds, nds, src, vector_len); 4697 evmovdqul(dst, nds, Assembler::AVX_512bit); 4698 } else { 4699 // worse case scenario, all regs in upper bank 4700 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4701 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4702 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4703 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4704 } 4705 } 4706 4707 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4708 int dst_enc = dst->encoding(); 4709 int nds_enc = nds->encoding(); 4710 int shift_enc = shift->encoding(); 4711 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4712 Assembler::vpsraw(dst, nds, shift, vector_len); 4713 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4714 Assembler::vpsraw(dst, dst, shift, vector_len); 4715 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4716 // use nds_enc as scratch with shift 4717 evmovdqul(nds, shift, Assembler::AVX_512bit); 4718 Assembler::vpsraw(dst, dst, nds, vector_len); 4719 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4720 // use nds as scratch with dst 4721 evmovdqul(nds, dst, Assembler::AVX_512bit); 4722 Assembler::vpsraw(nds, nds, shift, vector_len); 4723 evmovdqul(dst, nds, Assembler::AVX_512bit); 4724 } else if (dst_enc < 16) { 4725 // use nds to save a copy of xmm0 and hold shift 4726 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4727 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4728 Assembler::vpsraw(dst, dst, xmm0, vector_len); 4729 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4730 } else if (nds_enc < 16) { 4731 // use nds as dest as temps 4732 evmovdqul(nds, dst, Assembler::AVX_512bit); 4733 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4734 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4735 Assembler::vpsraw(nds, nds, xmm0, vector_len); 4736 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4737 evmovdqul(dst, nds, Assembler::AVX_512bit); 4738 } else { 4739 // worse case scenario, all regs are in the upper bank 4740 subptr(rsp, 64); 4741 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4742 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4743 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4744 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4745 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4746 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4747 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4748 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4749 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4750 addptr(rsp, 64); 4751 } 4752 } 4753 4754 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4755 int dst_enc = dst->encoding(); 4756 int nds_enc = nds->encoding(); 4757 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4758 Assembler::vpsraw(dst, nds, shift, vector_len); 4759 } else if (dst_enc < 16) { 4760 Assembler::vpsraw(dst, dst, shift, vector_len); 4761 } else if (nds_enc < 16) { 4762 // use nds as scratch 4763 evmovdqul(nds, dst, Assembler::AVX_512bit); 4764 Assembler::vpsraw(nds, nds, shift, vector_len); 4765 evmovdqul(dst, nds, Assembler::AVX_512bit); 4766 } else { 4767 // use nds as scratch for xmm0 4768 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4769 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4770 Assembler::vpsraw(xmm0, xmm0, shift, vector_len); 4771 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4772 } 4773 } 4774 4775 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4776 int dst_enc = dst->encoding(); 4777 int nds_enc = nds->encoding(); 4778 int shift_enc = shift->encoding(); 4779 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4780 Assembler::vpsrlw(dst, nds, shift, vector_len); 4781 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4782 Assembler::vpsrlw(dst, dst, shift, vector_len); 4783 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4784 // use nds_enc as scratch with shift 4785 evmovdqul(nds, shift, Assembler::AVX_512bit); 4786 Assembler::vpsrlw(dst, dst, nds, vector_len); 4787 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4788 // use nds as scratch with dst 4789 evmovdqul(nds, dst, Assembler::AVX_512bit); 4790 Assembler::vpsrlw(nds, nds, shift, vector_len); 4791 evmovdqul(dst, nds, Assembler::AVX_512bit); 4792 } else if (dst_enc < 16) { 4793 // use nds to save a copy of xmm0 and hold shift 4794 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4795 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4796 Assembler::vpsrlw(dst, dst, xmm0, vector_len); 4797 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4798 } else if (nds_enc < 16) { 4799 // use nds as dest as temps 4800 evmovdqul(nds, dst, Assembler::AVX_512bit); 4801 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4802 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4803 Assembler::vpsrlw(nds, nds, xmm0, vector_len); 4804 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4805 evmovdqul(dst, nds, Assembler::AVX_512bit); 4806 } else { 4807 // worse case scenario, all regs are in the upper bank 4808 subptr(rsp, 64); 4809 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4810 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4811 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4812 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4813 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4814 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4815 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4816 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4817 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4818 addptr(rsp, 64); 4819 } 4820 } 4821 4822 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4823 int dst_enc = dst->encoding(); 4824 int nds_enc = nds->encoding(); 4825 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4826 Assembler::vpsrlw(dst, nds, shift, vector_len); 4827 } else if (dst_enc < 16) { 4828 Assembler::vpsrlw(dst, dst, shift, vector_len); 4829 } else if (nds_enc < 16) { 4830 // use nds as scratch 4831 evmovdqul(nds, dst, Assembler::AVX_512bit); 4832 Assembler::vpsrlw(nds, nds, shift, vector_len); 4833 evmovdqul(dst, nds, Assembler::AVX_512bit); 4834 } else { 4835 // use nds as scratch for xmm0 4836 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4837 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4838 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len); 4839 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4840 } 4841 } 4842 4843 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4844 int dst_enc = dst->encoding(); 4845 int nds_enc = nds->encoding(); 4846 int shift_enc = shift->encoding(); 4847 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4848 Assembler::vpsllw(dst, nds, shift, vector_len); 4849 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4850 Assembler::vpsllw(dst, dst, shift, vector_len); 4851 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4852 // use nds_enc as scratch with shift 4853 evmovdqul(nds, shift, Assembler::AVX_512bit); 4854 Assembler::vpsllw(dst, dst, nds, vector_len); 4855 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4856 // use nds as scratch with dst 4857 evmovdqul(nds, dst, Assembler::AVX_512bit); 4858 Assembler::vpsllw(nds, nds, shift, vector_len); 4859 evmovdqul(dst, nds, Assembler::AVX_512bit); 4860 } else if (dst_enc < 16) { 4861 // use nds to save a copy of xmm0 and hold shift 4862 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4863 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4864 Assembler::vpsllw(dst, dst, xmm0, vector_len); 4865 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4866 } else if (nds_enc < 16) { 4867 // use nds as dest as temps 4868 evmovdqul(nds, dst, Assembler::AVX_512bit); 4869 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4870 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4871 Assembler::vpsllw(nds, nds, xmm0, vector_len); 4872 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4873 evmovdqul(dst, nds, Assembler::AVX_512bit); 4874 } else { 4875 // worse case scenario, all regs are in the upper bank 4876 subptr(rsp, 64); 4877 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4878 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4879 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4880 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4881 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4882 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4883 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4884 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4885 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4886 addptr(rsp, 64); 4887 } 4888 } 4889 4890 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4891 int dst_enc = dst->encoding(); 4892 int nds_enc = nds->encoding(); 4893 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4894 Assembler::vpsllw(dst, nds, shift, vector_len); 4895 } else if (dst_enc < 16) { 4896 Assembler::vpsllw(dst, dst, shift, vector_len); 4897 } else if (nds_enc < 16) { 4898 // use nds as scratch 4899 evmovdqul(nds, dst, Assembler::AVX_512bit); 4900 Assembler::vpsllw(nds, nds, shift, vector_len); 4901 evmovdqul(dst, nds, Assembler::AVX_512bit); 4902 } else { 4903 // use nds as scratch for xmm0 4904 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4905 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4906 Assembler::vpsllw(xmm0, xmm0, shift, vector_len); 4907 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4908 } 4909 } 4910 4911 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 4912 int dst_enc = dst->encoding(); 4913 int src_enc = src->encoding(); 4914 if ((dst_enc < 16) && (src_enc < 16)) { 4915 Assembler::vptest(dst, src); 4916 } else if (src_enc < 16) { 4917 subptr(rsp, 64); 4918 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4919 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4920 Assembler::vptest(xmm0, src); 4921 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4922 addptr(rsp, 64); 4923 } else if (dst_enc < 16) { 4924 subptr(rsp, 64); 4925 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4926 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4927 Assembler::vptest(dst, xmm0); 4928 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4929 addptr(rsp, 64); 4930 } else { 4931 subptr(rsp, 64); 4932 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4933 subptr(rsp, 64); 4934 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4935 movdqu(xmm0, src); 4936 movdqu(xmm1, dst); 4937 Assembler::vptest(xmm1, xmm0); 4938 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4939 addptr(rsp, 64); 4940 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4941 addptr(rsp, 64); 4942 } 4943 } 4944 4945 // This instruction exists within macros, ergo we cannot control its input 4946 // when emitted through those patterns. 4947 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4948 if (VM_Version::supports_avx512nobw()) { 4949 int dst_enc = dst->encoding(); 4950 int src_enc = src->encoding(); 4951 if (dst_enc == src_enc) { 4952 if (dst_enc < 16) { 4953 Assembler::punpcklbw(dst, src); 4954 } else { 4955 subptr(rsp, 64); 4956 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4957 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4958 Assembler::punpcklbw(xmm0, xmm0); 4959 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4960 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4961 addptr(rsp, 64); 4962 } 4963 } else { 4964 if ((src_enc < 16) && (dst_enc < 16)) { 4965 Assembler::punpcklbw(dst, src); 4966 } else if (src_enc < 16) { 4967 subptr(rsp, 64); 4968 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4969 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4970 Assembler::punpcklbw(xmm0, src); 4971 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4972 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4973 addptr(rsp, 64); 4974 } else if (dst_enc < 16) { 4975 subptr(rsp, 64); 4976 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4977 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4978 Assembler::punpcklbw(dst, xmm0); 4979 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4980 addptr(rsp, 64); 4981 } else { 4982 subptr(rsp, 64); 4983 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4984 subptr(rsp, 64); 4985 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4986 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4987 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4988 Assembler::punpcklbw(xmm0, xmm1); 4989 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4990 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4991 addptr(rsp, 64); 4992 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4993 addptr(rsp, 64); 4994 } 4995 } 4996 } else { 4997 Assembler::punpcklbw(dst, src); 4998 } 4999 } 5000 5001 // This instruction exists within macros, ergo we cannot control its input 5002 // when emitted through those patterns. 5003 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 5004 if (VM_Version::supports_avx512nobw()) { 5005 int dst_enc = dst->encoding(); 5006 int src_enc = src->encoding(); 5007 if (dst_enc == src_enc) { 5008 if (dst_enc < 16) { 5009 Assembler::pshuflw(dst, src, mode); 5010 } else { 5011 subptr(rsp, 64); 5012 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5013 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 5014 Assembler::pshuflw(xmm0, xmm0, mode); 5015 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5016 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5017 addptr(rsp, 64); 5018 } 5019 } else { 5020 if ((src_enc < 16) && (dst_enc < 16)) { 5021 Assembler::pshuflw(dst, src, mode); 5022 } else if (src_enc < 16) { 5023 subptr(rsp, 64); 5024 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5025 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 5026 Assembler::pshuflw(xmm0, src, mode); 5027 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5028 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5029 addptr(rsp, 64); 5030 } else if (dst_enc < 16) { 5031 subptr(rsp, 64); 5032 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5033 evmovdqul(xmm0, src, Assembler::AVX_512bit); 5034 Assembler::pshuflw(dst, xmm0, mode); 5035 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5036 addptr(rsp, 64); 5037 } else { 5038 subptr(rsp, 64); 5039 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5040 subptr(rsp, 64); 5041 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 5042 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 5043 evmovdqul(xmm1, src, Assembler::AVX_512bit); 5044 Assembler::pshuflw(xmm0, xmm1, mode); 5045 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 5046 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 5047 addptr(rsp, 64); 5048 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5049 addptr(rsp, 64); 5050 } 5051 } 5052 } else { 5053 Assembler::pshuflw(dst, src, mode); 5054 } 5055 } 5056 5057 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5058 if (reachable(src)) { 5059 vandpd(dst, nds, as_Address(src), vector_len); 5060 } else { 5061 lea(rscratch1, src); 5062 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 5063 } 5064 } 5065 5066 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5067 if (reachable(src)) { 5068 vandps(dst, nds, as_Address(src), vector_len); 5069 } else { 5070 lea(rscratch1, src); 5071 vandps(dst, nds, Address(rscratch1, 0), vector_len); 5072 } 5073 } 5074 5075 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5076 if (reachable(src)) { 5077 vdivsd(dst, nds, as_Address(src)); 5078 } else { 5079 lea(rscratch1, src); 5080 vdivsd(dst, nds, Address(rscratch1, 0)); 5081 } 5082 } 5083 5084 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5085 if (reachable(src)) { 5086 vdivss(dst, nds, as_Address(src)); 5087 } else { 5088 lea(rscratch1, src); 5089 vdivss(dst, nds, Address(rscratch1, 0)); 5090 } 5091 } 5092 5093 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5094 if (reachable(src)) { 5095 vmulsd(dst, nds, as_Address(src)); 5096 } else { 5097 lea(rscratch1, src); 5098 vmulsd(dst, nds, Address(rscratch1, 0)); 5099 } 5100 } 5101 5102 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5103 if (reachable(src)) { 5104 vmulss(dst, nds, as_Address(src)); 5105 } else { 5106 lea(rscratch1, src); 5107 vmulss(dst, nds, Address(rscratch1, 0)); 5108 } 5109 } 5110 5111 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5112 if (reachable(src)) { 5113 vsubsd(dst, nds, as_Address(src)); 5114 } else { 5115 lea(rscratch1, src); 5116 vsubsd(dst, nds, Address(rscratch1, 0)); 5117 } 5118 } 5119 5120 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5121 if (reachable(src)) { 5122 vsubss(dst, nds, as_Address(src)); 5123 } else { 5124 lea(rscratch1, src); 5125 vsubss(dst, nds, Address(rscratch1, 0)); 5126 } 5127 } 5128 5129 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5130 int nds_enc = nds->encoding(); 5131 int dst_enc = dst->encoding(); 5132 bool dst_upper_bank = (dst_enc > 15); 5133 bool nds_upper_bank = (nds_enc > 15); 5134 if (VM_Version::supports_avx512novl() && 5135 (nds_upper_bank || dst_upper_bank)) { 5136 if (dst_upper_bank) { 5137 subptr(rsp, 64); 5138 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5139 movflt(xmm0, nds); 5140 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit); 5141 movflt(dst, xmm0); 5142 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5143 addptr(rsp, 64); 5144 } else { 5145 movflt(dst, nds); 5146 vxorps(dst, dst, src, Assembler::AVX_128bit); 5147 } 5148 } else { 5149 vxorps(dst, nds, src, Assembler::AVX_128bit); 5150 } 5151 } 5152 5153 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5154 int nds_enc = nds->encoding(); 5155 int dst_enc = dst->encoding(); 5156 bool dst_upper_bank = (dst_enc > 15); 5157 bool nds_upper_bank = (nds_enc > 15); 5158 if (VM_Version::supports_avx512novl() && 5159 (nds_upper_bank || dst_upper_bank)) { 5160 if (dst_upper_bank) { 5161 subptr(rsp, 64); 5162 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5163 movdbl(xmm0, nds); 5164 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit); 5165 movdbl(dst, xmm0); 5166 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5167 addptr(rsp, 64); 5168 } else { 5169 movdbl(dst, nds); 5170 vxorpd(dst, dst, src, Assembler::AVX_128bit); 5171 } 5172 } else { 5173 vxorpd(dst, nds, src, Assembler::AVX_128bit); 5174 } 5175 } 5176 5177 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5178 if (reachable(src)) { 5179 vxorpd(dst, nds, as_Address(src), vector_len); 5180 } else { 5181 lea(rscratch1, src); 5182 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 5183 } 5184 } 5185 5186 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5187 if (reachable(src)) { 5188 vxorps(dst, nds, as_Address(src), vector_len); 5189 } else { 5190 lea(rscratch1, src); 5191 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 5192 } 5193 } 5194 5195 5196 ////////////////////////////////////////////////////////////////////////////////// 5197 #if INCLUDE_ALL_GCS 5198 5199 void MacroAssembler::g1_write_barrier_pre(Register obj, 5200 Register pre_val, 5201 Register thread, 5202 Register tmp, 5203 bool tosca_live, 5204 bool expand_call) { 5205 5206 // If expand_call is true then we expand the call_VM_leaf macro 5207 // directly to skip generating the check by 5208 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 5209 5210 #ifdef _LP64 5211 assert(thread == r15_thread, "must be"); 5212 #endif // _LP64 5213 5214 Label done; 5215 Label runtime; 5216 5217 assert(pre_val != noreg, "check this code"); 5218 5219 if (obj != noreg) { 5220 assert_different_registers(obj, pre_val, tmp); 5221 assert(pre_val != rax, "check this code"); 5222 } 5223 5224 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5225 SATBMarkQueue::byte_offset_of_active())); 5226 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5227 SATBMarkQueue::byte_offset_of_index())); 5228 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5229 SATBMarkQueue::byte_offset_of_buf())); 5230 5231 5232 // Is marking active? 5233 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 5234 cmpl(in_progress, 0); 5235 } else { 5236 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 5237 cmpb(in_progress, 0); 5238 } 5239 jcc(Assembler::equal, done); 5240 5241 // Do we need to load the previous value? 5242 if (obj != noreg) { 5243 load_heap_oop(pre_val, Address(obj, 0)); 5244 } 5245 5246 // Is the previous value null? 5247 cmpptr(pre_val, (int32_t) NULL_WORD); 5248 jcc(Assembler::equal, done); 5249 5250 // Can we store original value in the thread's buffer? 5251 // Is index == 0? 5252 // (The index field is typed as size_t.) 5253 5254 movptr(tmp, index); // tmp := *index_adr 5255 cmpptr(tmp, 0); // tmp == 0? 5256 jcc(Assembler::equal, runtime); // If yes, goto runtime 5257 5258 subptr(tmp, wordSize); // tmp := tmp - wordSize 5259 movptr(index, tmp); // *index_adr := tmp 5260 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 5261 5262 // Record the previous value 5263 movptr(Address(tmp, 0), pre_val); 5264 jmp(done); 5265 5266 bind(runtime); 5267 // save the live input values 5268 if(tosca_live) push(rax); 5269 5270 if (obj != noreg && obj != rax) 5271 push(obj); 5272 5273 if (pre_val != rax) 5274 push(pre_val); 5275 5276 // Calling the runtime using the regular call_VM_leaf mechanism generates 5277 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 5278 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 5279 // 5280 // If we care generating the pre-barrier without a frame (e.g. in the 5281 // intrinsified Reference.get() routine) then ebp might be pointing to 5282 // the caller frame and so this check will most likely fail at runtime. 5283 // 5284 // Expanding the call directly bypasses the generation of the check. 5285 // So when we do not have have a full interpreter frame on the stack 5286 // expand_call should be passed true. 5287 5288 NOT_LP64( push(thread); ) 5289 5290 if (expand_call) { 5291 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 5292 pass_arg1(this, thread); 5293 pass_arg0(this, pre_val); 5294 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 5295 } else { 5296 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 5297 } 5298 5299 NOT_LP64( pop(thread); ) 5300 5301 // save the live input values 5302 if (pre_val != rax) 5303 pop(pre_val); 5304 5305 if (obj != noreg && obj != rax) 5306 pop(obj); 5307 5308 if(tosca_live) pop(rax); 5309 5310 bind(done); 5311 } 5312 5313 void MacroAssembler::g1_write_barrier_post(Register store_addr, 5314 Register new_val, 5315 Register thread, 5316 Register tmp, 5317 Register tmp2) { 5318 #ifdef _LP64 5319 assert(thread == r15_thread, "must be"); 5320 #endif // _LP64 5321 5322 if (UseShenandoahGC) { 5323 // No need for this in Shenandoah. 5324 return; 5325 } 5326 5327 assert(UseG1GC, "expect G1 GC"); 5328 5329 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5330 DirtyCardQueue::byte_offset_of_index())); 5331 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5332 DirtyCardQueue::byte_offset_of_buf())); 5333 5334 CardTableModRefBS* ct = 5335 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 5336 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5337 5338 Label done; 5339 Label runtime; 5340 5341 // Does store cross heap regions? 5342 5343 movptr(tmp, store_addr); 5344 xorptr(tmp, new_val); 5345 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 5346 jcc(Assembler::equal, done); 5347 5348 // crosses regions, storing NULL? 5349 5350 cmpptr(new_val, (int32_t) NULL_WORD); 5351 jcc(Assembler::equal, done); 5352 5353 // storing region crossing non-NULL, is card already dirty? 5354 5355 const Register card_addr = tmp; 5356 const Register cardtable = tmp2; 5357 5358 movptr(card_addr, store_addr); 5359 shrptr(card_addr, CardTableModRefBS::card_shift); 5360 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 5361 // a valid address and therefore is not properly handled by the relocation code. 5362 movptr(cardtable, (intptr_t)ct->byte_map_base); 5363 addptr(card_addr, cardtable); 5364 5365 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 5366 jcc(Assembler::equal, done); 5367 5368 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 5369 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5370 jcc(Assembler::equal, done); 5371 5372 5373 // storing a region crossing, non-NULL oop, card is clean. 5374 // dirty card and log. 5375 5376 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5377 5378 cmpl(queue_index, 0); 5379 jcc(Assembler::equal, runtime); 5380 subl(queue_index, wordSize); 5381 movptr(tmp2, buffer); 5382 #ifdef _LP64 5383 movslq(rscratch1, queue_index); 5384 addq(tmp2, rscratch1); 5385 movq(Address(tmp2, 0), card_addr); 5386 #else 5387 addl(tmp2, queue_index); 5388 movl(Address(tmp2, 0), card_addr); 5389 #endif 5390 jmp(done); 5391 5392 bind(runtime); 5393 // save the live input values 5394 push(store_addr); 5395 push(new_val); 5396 #ifdef _LP64 5397 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 5398 #else 5399 push(thread); 5400 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 5401 pop(thread); 5402 #endif 5403 pop(new_val); 5404 pop(store_addr); 5405 5406 bind(done); 5407 } 5408 5409 #endif // INCLUDE_ALL_GCS 5410 ////////////////////////////////////////////////////////////////////////////////// 5411 5412 5413 void MacroAssembler::store_check(Register obj, Address dst) { 5414 store_check(obj); 5415 } 5416 5417 void MacroAssembler::store_check(Register obj) { 5418 // Does a store check for the oop in register obj. The content of 5419 // register obj is destroyed afterwards. 5420 BarrierSet* bs = Universe::heap()->barrier_set(); 5421 assert(bs->kind() == BarrierSet::CardTableForRS || 5422 bs->kind() == BarrierSet::CardTableExtension, 5423 "Wrong barrier set kind"); 5424 5425 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 5426 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5427 5428 shrptr(obj, CardTableModRefBS::card_shift); 5429 5430 Address card_addr; 5431 5432 // The calculation for byte_map_base is as follows: 5433 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 5434 // So this essentially converts an address to a displacement and it will 5435 // never need to be relocated. On 64bit however the value may be too 5436 // large for a 32bit displacement. 5437 intptr_t disp = (intptr_t) ct->byte_map_base; 5438 if (is_simm32(disp)) { 5439 card_addr = Address(noreg, obj, Address::times_1, disp); 5440 } else { 5441 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative 5442 // displacement and done in a single instruction given favorable mapping and a 5443 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation 5444 // entry and that entry is not properly handled by the relocation code. 5445 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); 5446 Address index(noreg, obj, Address::times_1); 5447 card_addr = as_Address(ArrayAddress(cardtable, index)); 5448 } 5449 5450 int dirty = CardTableModRefBS::dirty_card_val(); 5451 if (UseCondCardMark) { 5452 Label L_already_dirty; 5453 if (UseConcMarkSweepGC) { 5454 membar(Assembler::StoreLoad); 5455 } 5456 cmpb(card_addr, dirty); 5457 jcc(Assembler::equal, L_already_dirty); 5458 movb(card_addr, dirty); 5459 bind(L_already_dirty); 5460 } else { 5461 movb(card_addr, dirty); 5462 } 5463 } 5464 5465 void MacroAssembler::subptr(Register dst, int32_t imm32) { 5466 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 5467 } 5468 5469 // Force generation of a 4 byte immediate value even if it fits into 8bit 5470 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 5471 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 5472 } 5473 5474 void MacroAssembler::subptr(Register dst, Register src) { 5475 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 5476 } 5477 5478 // C++ bool manipulation 5479 void MacroAssembler::testbool(Register dst) { 5480 if(sizeof(bool) == 1) 5481 testb(dst, 0xff); 5482 else if(sizeof(bool) == 2) { 5483 // testw implementation needed for two byte bools 5484 ShouldNotReachHere(); 5485 } else if(sizeof(bool) == 4) 5486 testl(dst, dst); 5487 else 5488 // unsupported 5489 ShouldNotReachHere(); 5490 } 5491 5492 void MacroAssembler::testptr(Register dst, Register src) { 5493 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 5494 } 5495 5496 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 5497 void MacroAssembler::tlab_allocate(Register obj, 5498 Register var_size_in_bytes, 5499 int con_size_in_bytes, 5500 Register t1, 5501 Register t2, 5502 Label& slow_case) { 5503 assert_different_registers(obj, t1, t2); 5504 assert_different_registers(obj, var_size_in_bytes, t1); 5505 Register end = t2; 5506 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 5507 5508 verify_tlab(); 5509 5510 NOT_LP64(get_thread(thread)); 5511 5512 uint oop_extra_words = Universe::heap()->oop_extra_words(); 5513 5514 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 5515 if (var_size_in_bytes == noreg) { 5516 lea(end, Address(obj, con_size_in_bytes + oop_extra_words * HeapWordSize)); 5517 } else { 5518 if (oop_extra_words > 0) { 5519 addq(var_size_in_bytes, oop_extra_words * HeapWordSize); 5520 } 5521 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 5522 } 5523 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 5524 jcc(Assembler::above, slow_case); 5525 5526 // update the tlab top pointer 5527 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 5528 5529 Universe::heap()->compile_prepare_oop(this, obj); 5530 5531 // recover var_size_in_bytes if necessary 5532 if (var_size_in_bytes == end) { 5533 subptr(var_size_in_bytes, obj); 5534 } 5535 verify_tlab(); 5536 } 5537 5538 // Preserves rbx, and rdx. 5539 Register MacroAssembler::tlab_refill(Label& retry, 5540 Label& try_eden, 5541 Label& slow_case) { 5542 Register top = rax; 5543 Register t1 = rcx; // object size 5544 Register t2 = rsi; 5545 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 5546 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 5547 Label do_refill, discard_tlab; 5548 5549 if (!Universe::heap()->supports_inline_contig_alloc()) { 5550 // No allocation in the shared eden. 5551 jmp(slow_case); 5552 } 5553 5554 NOT_LP64(get_thread(thread_reg)); 5555 5556 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5557 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5558 5559 // calculate amount of free space 5560 subptr(t1, top); 5561 shrptr(t1, LogHeapWordSize); 5562 5563 // Retain tlab and allocate object in shared space if 5564 // the amount free in the tlab is too large to discard. 5565 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 5566 jcc(Assembler::lessEqual, discard_tlab); 5567 5568 // Retain 5569 // %%% yuck as movptr... 5570 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 5571 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 5572 if (TLABStats) { 5573 // increment number of slow_allocations 5574 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 5575 } 5576 jmp(try_eden); 5577 5578 bind(discard_tlab); 5579 if (TLABStats) { 5580 // increment number of refills 5581 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 5582 // accumulate wastage -- t1 is amount free in tlab 5583 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 5584 } 5585 5586 // if tlab is currently allocated (top or end != null) then 5587 // fill [top, end + alignment_reserve) with array object 5588 testptr(top, top); 5589 jcc(Assembler::zero, do_refill); 5590 5591 // set up the mark word 5592 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 5593 // set the length to the remaining space 5594 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 5595 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 5596 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 5597 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 5598 // set klass to intArrayKlass 5599 // dubious reloc why not an oop reloc? 5600 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 5601 // store klass last. concurrent gcs assumes klass length is valid if 5602 // klass field is not null. 5603 store_klass(top, t1); 5604 5605 movptr(t1, top); 5606 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5607 incr_allocated_bytes(thread_reg, t1, 0); 5608 5609 // refill the tlab with an eden allocation 5610 bind(do_refill); 5611 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5612 shlptr(t1, LogHeapWordSize); 5613 // allocate new tlab, address returned in top 5614 eden_allocate(top, t1, 0, t2, slow_case); 5615 5616 // Check that t1 was preserved in eden_allocate. 5617 #ifdef ASSERT 5618 if (UseTLAB) { 5619 Label ok; 5620 Register tsize = rsi; 5621 assert_different_registers(tsize, thread_reg, t1); 5622 push(tsize); 5623 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5624 shlptr(tsize, LogHeapWordSize); 5625 cmpptr(t1, tsize); 5626 jcc(Assembler::equal, ok); 5627 STOP("assert(t1 != tlab size)"); 5628 should_not_reach_here(); 5629 5630 bind(ok); 5631 pop(tsize); 5632 } 5633 #endif 5634 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 5635 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 5636 addptr(top, t1); 5637 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 5638 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 5639 5640 if (ZeroTLAB) { 5641 // This is a fast TLAB refill, therefore the GC is not notified of it. 5642 // So compiled code must fill the new TLAB with zeroes. 5643 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5644 zero_memory(top, t1, 0, t2); 5645 } 5646 5647 verify_tlab(); 5648 jmp(retry); 5649 5650 return thread_reg; // for use by caller 5651 } 5652 5653 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 5654 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 5655 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 5656 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 5657 Label done; 5658 5659 testptr(length_in_bytes, length_in_bytes); 5660 jcc(Assembler::zero, done); 5661 5662 // initialize topmost word, divide index by 2, check if odd and test if zero 5663 // note: for the remaining code to work, index must be a multiple of BytesPerWord 5664 #ifdef ASSERT 5665 { 5666 Label L; 5667 testptr(length_in_bytes, BytesPerWord - 1); 5668 jcc(Assembler::zero, L); 5669 stop("length must be a multiple of BytesPerWord"); 5670 bind(L); 5671 } 5672 #endif 5673 Register index = length_in_bytes; 5674 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 5675 if (UseIncDec) { 5676 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 5677 } else { 5678 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 5679 shrptr(index, 1); 5680 } 5681 #ifndef _LP64 5682 // index could have not been a multiple of 8 (i.e., bit 2 was set) 5683 { 5684 Label even; 5685 // note: if index was a multiple of 8, then it cannot 5686 // be 0 now otherwise it must have been 0 before 5687 // => if it is even, we don't need to check for 0 again 5688 jcc(Assembler::carryClear, even); 5689 // clear topmost word (no jump would be needed if conditional assignment worked here) 5690 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 5691 // index could be 0 now, must check again 5692 jcc(Assembler::zero, done); 5693 bind(even); 5694 } 5695 #endif // !_LP64 5696 // initialize remaining object fields: index is a multiple of 2 now 5697 { 5698 Label loop; 5699 bind(loop); 5700 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 5701 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 5702 decrement(index); 5703 jcc(Assembler::notZero, loop); 5704 } 5705 5706 bind(done); 5707 } 5708 5709 void MacroAssembler::incr_allocated_bytes(Register thread, 5710 Register var_size_in_bytes, 5711 int con_size_in_bytes, 5712 Register t1) { 5713 if (!thread->is_valid()) { 5714 #ifdef _LP64 5715 thread = r15_thread; 5716 #else 5717 assert(t1->is_valid(), "need temp reg"); 5718 thread = t1; 5719 get_thread(thread); 5720 #endif 5721 } 5722 5723 #ifdef _LP64 5724 if (var_size_in_bytes->is_valid()) { 5725 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5726 } else { 5727 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5728 } 5729 #else 5730 if (var_size_in_bytes->is_valid()) { 5731 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5732 } else { 5733 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5734 } 5735 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 5736 #endif 5737 } 5738 5739 // Look up the method for a megamorphic invokeinterface call. 5740 // The target method is determined by <intf_klass, itable_index>. 5741 // The receiver klass is in recv_klass. 5742 // On success, the result will be in method_result, and execution falls through. 5743 // On failure, execution transfers to the given label. 5744 void MacroAssembler::lookup_interface_method(Register recv_klass, 5745 Register intf_klass, 5746 RegisterOrConstant itable_index, 5747 Register method_result, 5748 Register scan_temp, 5749 Label& L_no_such_interface) { 5750 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 5751 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 5752 "caller must use same register for non-constant itable index as for method"); 5753 5754 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 5755 int vtable_base = in_bytes(Klass::vtable_start_offset()); 5756 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 5757 int scan_step = itableOffsetEntry::size() * wordSize; 5758 int vte_size = vtableEntry::size_in_bytes(); 5759 Address::ScaleFactor times_vte_scale = Address::times_ptr; 5760 assert(vte_size == wordSize, "else adjust times_vte_scale"); 5761 5762 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 5763 5764 // %%% Could store the aligned, prescaled offset in the klassoop. 5765 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 5766 5767 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 5768 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 5769 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 5770 5771 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 5772 // if (scan->interface() == intf) { 5773 // result = (klass + scan->offset() + itable_index); 5774 // } 5775 // } 5776 Label search, found_method; 5777 5778 for (int peel = 1; peel >= 0; peel--) { 5779 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 5780 cmpptr(intf_klass, method_result); 5781 5782 if (peel) { 5783 jccb(Assembler::equal, found_method); 5784 } else { 5785 jccb(Assembler::notEqual, search); 5786 // (invert the test to fall through to found_method...) 5787 } 5788 5789 if (!peel) break; 5790 5791 bind(search); 5792 5793 // Check that the previous entry is non-null. A null entry means that 5794 // the receiver class doesn't implement the interface, and wasn't the 5795 // same as when the caller was compiled. 5796 testptr(method_result, method_result); 5797 jcc(Assembler::zero, L_no_such_interface); 5798 addptr(scan_temp, scan_step); 5799 } 5800 5801 bind(found_method); 5802 5803 // Got a hit. 5804 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 5805 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 5806 } 5807 5808 5809 // virtual method calling 5810 void MacroAssembler::lookup_virtual_method(Register recv_klass, 5811 RegisterOrConstant vtable_index, 5812 Register method_result) { 5813 const int base = in_bytes(Klass::vtable_start_offset()); 5814 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 5815 Address vtable_entry_addr(recv_klass, 5816 vtable_index, Address::times_ptr, 5817 base + vtableEntry::method_offset_in_bytes()); 5818 movptr(method_result, vtable_entry_addr); 5819 } 5820 5821 5822 void MacroAssembler::check_klass_subtype(Register sub_klass, 5823 Register super_klass, 5824 Register temp_reg, 5825 Label& L_success) { 5826 Label L_failure; 5827 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 5828 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 5829 bind(L_failure); 5830 } 5831 5832 5833 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 5834 Register super_klass, 5835 Register temp_reg, 5836 Label* L_success, 5837 Label* L_failure, 5838 Label* L_slow_path, 5839 RegisterOrConstant super_check_offset) { 5840 assert_different_registers(sub_klass, super_klass, temp_reg); 5841 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 5842 if (super_check_offset.is_register()) { 5843 assert_different_registers(sub_klass, super_klass, 5844 super_check_offset.as_register()); 5845 } else if (must_load_sco) { 5846 assert(temp_reg != noreg, "supply either a temp or a register offset"); 5847 } 5848 5849 Label L_fallthrough; 5850 int label_nulls = 0; 5851 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5852 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5853 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 5854 assert(label_nulls <= 1, "at most one NULL in the batch"); 5855 5856 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5857 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 5858 Address super_check_offset_addr(super_klass, sco_offset); 5859 5860 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 5861 // range of a jccb. If this routine grows larger, reconsider at 5862 // least some of these. 5863 #define local_jcc(assembler_cond, label) \ 5864 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 5865 else jcc( assembler_cond, label) /*omit semi*/ 5866 5867 // Hacked jmp, which may only be used just before L_fallthrough. 5868 #define final_jmp(label) \ 5869 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 5870 else jmp(label) /*omit semi*/ 5871 5872 // If the pointers are equal, we are done (e.g., String[] elements). 5873 // This self-check enables sharing of secondary supertype arrays among 5874 // non-primary types such as array-of-interface. Otherwise, each such 5875 // type would need its own customized SSA. 5876 // We move this check to the front of the fast path because many 5877 // type checks are in fact trivially successful in this manner, 5878 // so we get a nicely predicted branch right at the start of the check. 5879 cmpptr(sub_klass, super_klass); 5880 local_jcc(Assembler::equal, *L_success); 5881 5882 // Check the supertype display: 5883 if (must_load_sco) { 5884 // Positive movl does right thing on LP64. 5885 movl(temp_reg, super_check_offset_addr); 5886 super_check_offset = RegisterOrConstant(temp_reg); 5887 } 5888 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 5889 cmpptr(super_klass, super_check_addr); // load displayed supertype 5890 5891 // This check has worked decisively for primary supers. 5892 // Secondary supers are sought in the super_cache ('super_cache_addr'). 5893 // (Secondary supers are interfaces and very deeply nested subtypes.) 5894 // This works in the same check above because of a tricky aliasing 5895 // between the super_cache and the primary super display elements. 5896 // (The 'super_check_addr' can address either, as the case requires.) 5897 // Note that the cache is updated below if it does not help us find 5898 // what we need immediately. 5899 // So if it was a primary super, we can just fail immediately. 5900 // Otherwise, it's the slow path for us (no success at this point). 5901 5902 if (super_check_offset.is_register()) { 5903 local_jcc(Assembler::equal, *L_success); 5904 cmpl(super_check_offset.as_register(), sc_offset); 5905 if (L_failure == &L_fallthrough) { 5906 local_jcc(Assembler::equal, *L_slow_path); 5907 } else { 5908 local_jcc(Assembler::notEqual, *L_failure); 5909 final_jmp(*L_slow_path); 5910 } 5911 } else if (super_check_offset.as_constant() == sc_offset) { 5912 // Need a slow path; fast failure is impossible. 5913 if (L_slow_path == &L_fallthrough) { 5914 local_jcc(Assembler::equal, *L_success); 5915 } else { 5916 local_jcc(Assembler::notEqual, *L_slow_path); 5917 final_jmp(*L_success); 5918 } 5919 } else { 5920 // No slow path; it's a fast decision. 5921 if (L_failure == &L_fallthrough) { 5922 local_jcc(Assembler::equal, *L_success); 5923 } else { 5924 local_jcc(Assembler::notEqual, *L_failure); 5925 final_jmp(*L_success); 5926 } 5927 } 5928 5929 bind(L_fallthrough); 5930 5931 #undef local_jcc 5932 #undef final_jmp 5933 } 5934 5935 5936 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 5937 Register super_klass, 5938 Register temp_reg, 5939 Register temp2_reg, 5940 Label* L_success, 5941 Label* L_failure, 5942 bool set_cond_codes) { 5943 assert_different_registers(sub_klass, super_klass, temp_reg); 5944 if (temp2_reg != noreg) 5945 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 5946 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 5947 5948 Label L_fallthrough; 5949 int label_nulls = 0; 5950 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5951 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5952 assert(label_nulls <= 1, "at most one NULL in the batch"); 5953 5954 // a couple of useful fields in sub_klass: 5955 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 5956 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5957 Address secondary_supers_addr(sub_klass, ss_offset); 5958 Address super_cache_addr( sub_klass, sc_offset); 5959 5960 // Do a linear scan of the secondary super-klass chain. 5961 // This code is rarely used, so simplicity is a virtue here. 5962 // The repne_scan instruction uses fixed registers, which we must spill. 5963 // Don't worry too much about pre-existing connections with the input regs. 5964 5965 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 5966 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 5967 5968 // Get super_klass value into rax (even if it was in rdi or rcx). 5969 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 5970 if (super_klass != rax || UseCompressedOops) { 5971 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 5972 mov(rax, super_klass); 5973 } 5974 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 5975 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 5976 5977 #ifndef PRODUCT 5978 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 5979 ExternalAddress pst_counter_addr((address) pst_counter); 5980 NOT_LP64( incrementl(pst_counter_addr) ); 5981 LP64_ONLY( lea(rcx, pst_counter_addr) ); 5982 LP64_ONLY( incrementl(Address(rcx, 0)) ); 5983 #endif //PRODUCT 5984 5985 // We will consult the secondary-super array. 5986 movptr(rdi, secondary_supers_addr); 5987 // Load the array length. (Positive movl does right thing on LP64.) 5988 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 5989 // Skip to start of data. 5990 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 5991 5992 // Scan RCX words at [RDI] for an occurrence of RAX. 5993 // Set NZ/Z based on last compare. 5994 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 5995 // not change flags (only scas instruction which is repeated sets flags). 5996 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 5997 5998 testptr(rax,rax); // Set Z = 0 5999 repne_scan(); 6000 6001 // Unspill the temp. registers: 6002 if (pushed_rdi) pop(rdi); 6003 if (pushed_rcx) pop(rcx); 6004 if (pushed_rax) pop(rax); 6005 6006 if (set_cond_codes) { 6007 // Special hack for the AD files: rdi is guaranteed non-zero. 6008 assert(!pushed_rdi, "rdi must be left non-NULL"); 6009 // Also, the condition codes are properly set Z/NZ on succeed/failure. 6010 } 6011 6012 if (L_failure == &L_fallthrough) 6013 jccb(Assembler::notEqual, *L_failure); 6014 else jcc(Assembler::notEqual, *L_failure); 6015 6016 // Success. Cache the super we found and proceed in triumph. 6017 movptr(super_cache_addr, super_klass); 6018 6019 if (L_success != &L_fallthrough) { 6020 jmp(*L_success); 6021 } 6022 6023 #undef IS_A_TEMP 6024 6025 bind(L_fallthrough); 6026 } 6027 6028 6029 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 6030 if (VM_Version::supports_cmov()) { 6031 cmovl(cc, dst, src); 6032 } else { 6033 Label L; 6034 jccb(negate_condition(cc), L); 6035 movl(dst, src); 6036 bind(L); 6037 } 6038 } 6039 6040 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 6041 if (VM_Version::supports_cmov()) { 6042 cmovl(cc, dst, src); 6043 } else { 6044 Label L; 6045 jccb(negate_condition(cc), L); 6046 movl(dst, src); 6047 bind(L); 6048 } 6049 } 6050 6051 void MacroAssembler::verify_oop(Register reg, const char* s) { 6052 if (!VerifyOops) return; 6053 6054 // Pass register number to verify_oop_subroutine 6055 const char* b = NULL; 6056 { 6057 ResourceMark rm; 6058 stringStream ss; 6059 ss.print("verify_oop: %s: %s", reg->name(), s); 6060 b = code_string(ss.as_string()); 6061 } 6062 BLOCK_COMMENT("verify_oop {"); 6063 #ifdef _LP64 6064 push(rscratch1); // save r10, trashed by movptr() 6065 #endif 6066 push(rax); // save rax, 6067 push(reg); // pass register argument 6068 ExternalAddress buffer((address) b); 6069 // avoid using pushptr, as it modifies scratch registers 6070 // and our contract is not to modify anything 6071 movptr(rax, buffer.addr()); 6072 push(rax); 6073 // call indirectly to solve generation ordering problem 6074 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6075 call(rax); 6076 // Caller pops the arguments (oop, message) and restores rax, r10 6077 BLOCK_COMMENT("} verify_oop"); 6078 } 6079 6080 6081 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 6082 Register tmp, 6083 int offset) { 6084 intptr_t value = *delayed_value_addr; 6085 if (value != 0) 6086 return RegisterOrConstant(value + offset); 6087 6088 // load indirectly to solve generation ordering problem 6089 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 6090 6091 #ifdef ASSERT 6092 { Label L; 6093 testptr(tmp, tmp); 6094 if (WizardMode) { 6095 const char* buf = NULL; 6096 { 6097 ResourceMark rm; 6098 stringStream ss; 6099 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 6100 buf = code_string(ss.as_string()); 6101 } 6102 jcc(Assembler::notZero, L); 6103 STOP(buf); 6104 } else { 6105 jccb(Assembler::notZero, L); 6106 hlt(); 6107 } 6108 bind(L); 6109 } 6110 #endif 6111 6112 if (offset != 0) 6113 addptr(tmp, offset); 6114 6115 return RegisterOrConstant(tmp); 6116 } 6117 6118 6119 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 6120 int extra_slot_offset) { 6121 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 6122 int stackElementSize = Interpreter::stackElementSize; 6123 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 6124 #ifdef ASSERT 6125 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 6126 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 6127 #endif 6128 Register scale_reg = noreg; 6129 Address::ScaleFactor scale_factor = Address::no_scale; 6130 if (arg_slot.is_constant()) { 6131 offset += arg_slot.as_constant() * stackElementSize; 6132 } else { 6133 scale_reg = arg_slot.as_register(); 6134 scale_factor = Address::times(stackElementSize); 6135 } 6136 offset += wordSize; // return PC is on stack 6137 return Address(rsp, scale_reg, scale_factor, offset); 6138 } 6139 6140 6141 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 6142 if (!VerifyOops) return; 6143 6144 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 6145 // Pass register number to verify_oop_subroutine 6146 const char* b = NULL; 6147 { 6148 ResourceMark rm; 6149 stringStream ss; 6150 ss.print("verify_oop_addr: %s", s); 6151 b = code_string(ss.as_string()); 6152 } 6153 #ifdef _LP64 6154 push(rscratch1); // save r10, trashed by movptr() 6155 #endif 6156 push(rax); // save rax, 6157 // addr may contain rsp so we will have to adjust it based on the push 6158 // we just did (and on 64 bit we do two pushes) 6159 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 6160 // stores rax into addr which is backwards of what was intended. 6161 if (addr.uses(rsp)) { 6162 lea(rax, addr); 6163 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 6164 } else { 6165 pushptr(addr); 6166 } 6167 6168 ExternalAddress buffer((address) b); 6169 // pass msg argument 6170 // avoid using pushptr, as it modifies scratch registers 6171 // and our contract is not to modify anything 6172 movptr(rax, buffer.addr()); 6173 push(rax); 6174 6175 // call indirectly to solve generation ordering problem 6176 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6177 call(rax); 6178 // Caller pops the arguments (addr, message) and restores rax, r10. 6179 } 6180 6181 void MacroAssembler::verify_tlab() { 6182 #ifdef ASSERT 6183 if (UseTLAB && VerifyOops) { 6184 Label next, ok; 6185 Register t1 = rsi; 6186 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 6187 6188 push(t1); 6189 NOT_LP64(push(thread_reg)); 6190 NOT_LP64(get_thread(thread_reg)); 6191 6192 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6193 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 6194 jcc(Assembler::aboveEqual, next); 6195 STOP("assert(top >= start)"); 6196 should_not_reach_here(); 6197 6198 bind(next); 6199 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 6200 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6201 jcc(Assembler::aboveEqual, ok); 6202 STOP("assert(top <= end)"); 6203 should_not_reach_here(); 6204 6205 bind(ok); 6206 NOT_LP64(pop(thread_reg)); 6207 pop(t1); 6208 } 6209 #endif 6210 } 6211 6212 class ControlWord { 6213 public: 6214 int32_t _value; 6215 6216 int rounding_control() const { return (_value >> 10) & 3 ; } 6217 int precision_control() const { return (_value >> 8) & 3 ; } 6218 bool precision() const { return ((_value >> 5) & 1) != 0; } 6219 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6220 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6221 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6222 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6223 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6224 6225 void print() const { 6226 // rounding control 6227 const char* rc; 6228 switch (rounding_control()) { 6229 case 0: rc = "round near"; break; 6230 case 1: rc = "round down"; break; 6231 case 2: rc = "round up "; break; 6232 case 3: rc = "chop "; break; 6233 }; 6234 // precision control 6235 const char* pc; 6236 switch (precision_control()) { 6237 case 0: pc = "24 bits "; break; 6238 case 1: pc = "reserved"; break; 6239 case 2: pc = "53 bits "; break; 6240 case 3: pc = "64 bits "; break; 6241 }; 6242 // flags 6243 char f[9]; 6244 f[0] = ' '; 6245 f[1] = ' '; 6246 f[2] = (precision ()) ? 'P' : 'p'; 6247 f[3] = (underflow ()) ? 'U' : 'u'; 6248 f[4] = (overflow ()) ? 'O' : 'o'; 6249 f[5] = (zero_divide ()) ? 'Z' : 'z'; 6250 f[6] = (denormalized()) ? 'D' : 'd'; 6251 f[7] = (invalid ()) ? 'I' : 'i'; 6252 f[8] = '\x0'; 6253 // output 6254 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 6255 } 6256 6257 }; 6258 6259 class StatusWord { 6260 public: 6261 int32_t _value; 6262 6263 bool busy() const { return ((_value >> 15) & 1) != 0; } 6264 bool C3() const { return ((_value >> 14) & 1) != 0; } 6265 bool C2() const { return ((_value >> 10) & 1) != 0; } 6266 bool C1() const { return ((_value >> 9) & 1) != 0; } 6267 bool C0() const { return ((_value >> 8) & 1) != 0; } 6268 int top() const { return (_value >> 11) & 7 ; } 6269 bool error_status() const { return ((_value >> 7) & 1) != 0; } 6270 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 6271 bool precision() const { return ((_value >> 5) & 1) != 0; } 6272 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6273 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6274 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6275 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6276 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6277 6278 void print() const { 6279 // condition codes 6280 char c[5]; 6281 c[0] = (C3()) ? '3' : '-'; 6282 c[1] = (C2()) ? '2' : '-'; 6283 c[2] = (C1()) ? '1' : '-'; 6284 c[3] = (C0()) ? '0' : '-'; 6285 c[4] = '\x0'; 6286 // flags 6287 char f[9]; 6288 f[0] = (error_status()) ? 'E' : '-'; 6289 f[1] = (stack_fault ()) ? 'S' : '-'; 6290 f[2] = (precision ()) ? 'P' : '-'; 6291 f[3] = (underflow ()) ? 'U' : '-'; 6292 f[4] = (overflow ()) ? 'O' : '-'; 6293 f[5] = (zero_divide ()) ? 'Z' : '-'; 6294 f[6] = (denormalized()) ? 'D' : '-'; 6295 f[7] = (invalid ()) ? 'I' : '-'; 6296 f[8] = '\x0'; 6297 // output 6298 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 6299 } 6300 6301 }; 6302 6303 class TagWord { 6304 public: 6305 int32_t _value; 6306 6307 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 6308 6309 void print() const { 6310 printf("%04x", _value & 0xFFFF); 6311 } 6312 6313 }; 6314 6315 class FPU_Register { 6316 public: 6317 int32_t _m0; 6318 int32_t _m1; 6319 int16_t _ex; 6320 6321 bool is_indefinite() const { 6322 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 6323 } 6324 6325 void print() const { 6326 char sign = (_ex < 0) ? '-' : '+'; 6327 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 6328 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 6329 }; 6330 6331 }; 6332 6333 class FPU_State { 6334 public: 6335 enum { 6336 register_size = 10, 6337 number_of_registers = 8, 6338 register_mask = 7 6339 }; 6340 6341 ControlWord _control_word; 6342 StatusWord _status_word; 6343 TagWord _tag_word; 6344 int32_t _error_offset; 6345 int32_t _error_selector; 6346 int32_t _data_offset; 6347 int32_t _data_selector; 6348 int8_t _register[register_size * number_of_registers]; 6349 6350 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 6351 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 6352 6353 const char* tag_as_string(int tag) const { 6354 switch (tag) { 6355 case 0: return "valid"; 6356 case 1: return "zero"; 6357 case 2: return "special"; 6358 case 3: return "empty"; 6359 } 6360 ShouldNotReachHere(); 6361 return NULL; 6362 } 6363 6364 void print() const { 6365 // print computation registers 6366 { int t = _status_word.top(); 6367 for (int i = 0; i < number_of_registers; i++) { 6368 int j = (i - t) & register_mask; 6369 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 6370 st(j)->print(); 6371 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 6372 } 6373 } 6374 printf("\n"); 6375 // print control registers 6376 printf("ctrl = "); _control_word.print(); printf("\n"); 6377 printf("stat = "); _status_word .print(); printf("\n"); 6378 printf("tags = "); _tag_word .print(); printf("\n"); 6379 } 6380 6381 }; 6382 6383 class Flag_Register { 6384 public: 6385 int32_t _value; 6386 6387 bool overflow() const { return ((_value >> 11) & 1) != 0; } 6388 bool direction() const { return ((_value >> 10) & 1) != 0; } 6389 bool sign() const { return ((_value >> 7) & 1) != 0; } 6390 bool zero() const { return ((_value >> 6) & 1) != 0; } 6391 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 6392 bool parity() const { return ((_value >> 2) & 1) != 0; } 6393 bool carry() const { return ((_value >> 0) & 1) != 0; } 6394 6395 void print() const { 6396 // flags 6397 char f[8]; 6398 f[0] = (overflow ()) ? 'O' : '-'; 6399 f[1] = (direction ()) ? 'D' : '-'; 6400 f[2] = (sign ()) ? 'S' : '-'; 6401 f[3] = (zero ()) ? 'Z' : '-'; 6402 f[4] = (auxiliary_carry()) ? 'A' : '-'; 6403 f[5] = (parity ()) ? 'P' : '-'; 6404 f[6] = (carry ()) ? 'C' : '-'; 6405 f[7] = '\x0'; 6406 // output 6407 printf("%08x flags = %s", _value, f); 6408 } 6409 6410 }; 6411 6412 class IU_Register { 6413 public: 6414 int32_t _value; 6415 6416 void print() const { 6417 printf("%08x %11d", _value, _value); 6418 } 6419 6420 }; 6421 6422 class IU_State { 6423 public: 6424 Flag_Register _eflags; 6425 IU_Register _rdi; 6426 IU_Register _rsi; 6427 IU_Register _rbp; 6428 IU_Register _rsp; 6429 IU_Register _rbx; 6430 IU_Register _rdx; 6431 IU_Register _rcx; 6432 IU_Register _rax; 6433 6434 void print() const { 6435 // computation registers 6436 printf("rax, = "); _rax.print(); printf("\n"); 6437 printf("rbx, = "); _rbx.print(); printf("\n"); 6438 printf("rcx = "); _rcx.print(); printf("\n"); 6439 printf("rdx = "); _rdx.print(); printf("\n"); 6440 printf("rdi = "); _rdi.print(); printf("\n"); 6441 printf("rsi = "); _rsi.print(); printf("\n"); 6442 printf("rbp, = "); _rbp.print(); printf("\n"); 6443 printf("rsp = "); _rsp.print(); printf("\n"); 6444 printf("\n"); 6445 // control registers 6446 printf("flgs = "); _eflags.print(); printf("\n"); 6447 } 6448 }; 6449 6450 6451 class CPU_State { 6452 public: 6453 FPU_State _fpu_state; 6454 IU_State _iu_state; 6455 6456 void print() const { 6457 printf("--------------------------------------------------\n"); 6458 _iu_state .print(); 6459 printf("\n"); 6460 _fpu_state.print(); 6461 printf("--------------------------------------------------\n"); 6462 } 6463 6464 }; 6465 6466 6467 static void _print_CPU_state(CPU_State* state) { 6468 state->print(); 6469 }; 6470 6471 6472 void MacroAssembler::print_CPU_state() { 6473 push_CPU_state(); 6474 push(rsp); // pass CPU state 6475 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 6476 addptr(rsp, wordSize); // discard argument 6477 pop_CPU_state(); 6478 } 6479 6480 6481 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 6482 static int counter = 0; 6483 FPU_State* fs = &state->_fpu_state; 6484 counter++; 6485 // For leaf calls, only verify that the top few elements remain empty. 6486 // We only need 1 empty at the top for C2 code. 6487 if( stack_depth < 0 ) { 6488 if( fs->tag_for_st(7) != 3 ) { 6489 printf("FPR7 not empty\n"); 6490 state->print(); 6491 assert(false, "error"); 6492 return false; 6493 } 6494 return true; // All other stack states do not matter 6495 } 6496 6497 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 6498 "bad FPU control word"); 6499 6500 // compute stack depth 6501 int i = 0; 6502 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 6503 int d = i; 6504 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 6505 // verify findings 6506 if (i != FPU_State::number_of_registers) { 6507 // stack not contiguous 6508 printf("%s: stack not contiguous at ST%d\n", s, i); 6509 state->print(); 6510 assert(false, "error"); 6511 return false; 6512 } 6513 // check if computed stack depth corresponds to expected stack depth 6514 if (stack_depth < 0) { 6515 // expected stack depth is -stack_depth or less 6516 if (d > -stack_depth) { 6517 // too many elements on the stack 6518 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 6519 state->print(); 6520 assert(false, "error"); 6521 return false; 6522 } 6523 } else { 6524 // expected stack depth is stack_depth 6525 if (d != stack_depth) { 6526 // wrong stack depth 6527 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 6528 state->print(); 6529 assert(false, "error"); 6530 return false; 6531 } 6532 } 6533 // everything is cool 6534 return true; 6535 } 6536 6537 6538 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 6539 if (!VerifyFPU) return; 6540 push_CPU_state(); 6541 push(rsp); // pass CPU state 6542 ExternalAddress msg((address) s); 6543 // pass message string s 6544 pushptr(msg.addr()); 6545 push(stack_depth); // pass stack depth 6546 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 6547 addptr(rsp, 3 * wordSize); // discard arguments 6548 // check for error 6549 { Label L; 6550 testl(rax, rax); 6551 jcc(Assembler::notZero, L); 6552 int3(); // break if error condition 6553 bind(L); 6554 } 6555 pop_CPU_state(); 6556 } 6557 6558 void MacroAssembler::restore_cpu_control_state_after_jni() { 6559 // Either restore the MXCSR register after returning from the JNI Call 6560 // or verify that it wasn't changed (with -Xcheck:jni flag). 6561 if (VM_Version::supports_sse()) { 6562 if (RestoreMXCSROnJNICalls) { 6563 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 6564 } else if (CheckJNICalls) { 6565 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 6566 } 6567 } 6568 if (VM_Version::supports_avx()) { 6569 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 6570 vzeroupper(); 6571 } 6572 6573 #ifndef _LP64 6574 // Either restore the x87 floating pointer control word after returning 6575 // from the JNI call or verify that it wasn't changed. 6576 if (CheckJNICalls) { 6577 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 6578 } 6579 #endif // _LP64 6580 } 6581 6582 void MacroAssembler::load_mirror(Register mirror, Register method) { 6583 // get mirror 6584 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 6585 movptr(mirror, Address(method, Method::const_offset())); 6586 movptr(mirror, Address(mirror, ConstMethod::constants_offset())); 6587 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes())); 6588 movptr(mirror, Address(mirror, mirror_offset)); 6589 } 6590 6591 void MacroAssembler::load_klass(Register dst, Register src) { 6592 if (ShenandoahVerifyReadsToFromSpace) { 6593 oopDesc::bs()->interpreter_read_barrier(this, src); 6594 } 6595 #ifdef _LP64 6596 if (UseCompressedClassPointers) { 6597 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6598 decode_klass_not_null(dst); 6599 } else 6600 #endif 6601 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6602 } 6603 6604 void MacroAssembler::load_prototype_header(Register dst, Register src) { 6605 load_klass(dst, src); 6606 movptr(dst, Address(dst, Klass::prototype_header_offset())); 6607 } 6608 6609 void MacroAssembler::store_klass(Register dst, Register src) { 6610 #ifdef _LP64 6611 if (UseCompressedClassPointers) { 6612 encode_klass_not_null(src); 6613 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6614 } else 6615 #endif 6616 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6617 } 6618 6619 void MacroAssembler::load_heap_oop(Register dst, Address src) { 6620 #ifdef _LP64 6621 // FIXME: Must change all places where we try to load the klass. 6622 if (UseCompressedOops) { 6623 movl(dst, src); 6624 decode_heap_oop(dst); 6625 } else 6626 #endif 6627 movptr(dst, src); 6628 } 6629 6630 // Doesn't do verfication, generates fixed size code 6631 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 6632 #ifdef _LP64 6633 if (UseCompressedOops) { 6634 movl(dst, src); 6635 decode_heap_oop_not_null(dst); 6636 } else 6637 #endif 6638 movptr(dst, src); 6639 } 6640 6641 void MacroAssembler::store_heap_oop(Address dst, Register src) { 6642 #ifdef _LP64 6643 if (UseCompressedOops) { 6644 assert(!dst.uses(src), "not enough registers"); 6645 encode_heap_oop(src); 6646 movl(dst, src); 6647 } else 6648 #endif 6649 movptr(dst, src); 6650 } 6651 6652 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { 6653 assert_different_registers(src1, tmp); 6654 #ifdef _LP64 6655 if (UseCompressedOops) { 6656 bool did_push = false; 6657 if (tmp == noreg) { 6658 tmp = rax; 6659 push(tmp); 6660 did_push = true; 6661 assert(!src2.uses(rsp), "can't push"); 6662 } 6663 load_heap_oop(tmp, src2); 6664 cmpptr(src1, tmp); 6665 if (did_push) pop(tmp); 6666 } else 6667 #endif 6668 cmpptr(src1, src2); 6669 } 6670 6671 // Used for storing NULLs. 6672 void MacroAssembler::store_heap_oop_null(Address dst) { 6673 #ifdef _LP64 6674 if (UseCompressedOops) { 6675 movl(dst, (int32_t)NULL_WORD); 6676 } else { 6677 movslq(dst, (int32_t)NULL_WORD); 6678 } 6679 #else 6680 movl(dst, (int32_t)NULL_WORD); 6681 #endif 6682 } 6683 6684 #ifdef _LP64 6685 void MacroAssembler::store_klass_gap(Register dst, Register src) { 6686 if (UseCompressedClassPointers) { 6687 // Store to klass gap in destination 6688 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 6689 } 6690 } 6691 6692 #ifdef ASSERT 6693 void MacroAssembler::verify_heapbase(const char* msg) { 6694 assert (UseCompressedOops, "should be compressed"); 6695 assert (Universe::heap() != NULL, "java heap should be initialized"); 6696 if (CheckCompressedOops) { 6697 Label ok; 6698 push(rscratch1); // cmpptr trashes rscratch1 6699 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6700 jcc(Assembler::equal, ok); 6701 STOP(msg); 6702 bind(ok); 6703 pop(rscratch1); 6704 } 6705 } 6706 #endif 6707 6708 // Algorithm must match oop.inline.hpp encode_heap_oop. 6709 void MacroAssembler::encode_heap_oop(Register r) { 6710 #ifdef ASSERT 6711 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 6712 #endif 6713 verify_oop(r, "broken oop in encode_heap_oop"); 6714 if (Universe::narrow_oop_base() == NULL) { 6715 if (Universe::narrow_oop_shift() != 0) { 6716 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6717 shrq(r, LogMinObjAlignmentInBytes); 6718 } 6719 return; 6720 } 6721 testq(r, r); 6722 cmovq(Assembler::equal, r, r12_heapbase); 6723 subq(r, r12_heapbase); 6724 shrq(r, LogMinObjAlignmentInBytes); 6725 } 6726 6727 void MacroAssembler::encode_heap_oop_not_null(Register r) { 6728 #ifdef ASSERT 6729 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 6730 if (CheckCompressedOops) { 6731 Label ok; 6732 testq(r, r); 6733 jcc(Assembler::notEqual, ok); 6734 STOP("null oop passed to encode_heap_oop_not_null"); 6735 bind(ok); 6736 } 6737 #endif 6738 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 6739 if (Universe::narrow_oop_base() != NULL) { 6740 subq(r, r12_heapbase); 6741 } 6742 if (Universe::narrow_oop_shift() != 0) { 6743 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6744 shrq(r, LogMinObjAlignmentInBytes); 6745 } 6746 } 6747 6748 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 6749 #ifdef ASSERT 6750 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 6751 if (CheckCompressedOops) { 6752 Label ok; 6753 testq(src, src); 6754 jcc(Assembler::notEqual, ok); 6755 STOP("null oop passed to encode_heap_oop_not_null2"); 6756 bind(ok); 6757 } 6758 #endif 6759 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 6760 if (dst != src) { 6761 movq(dst, src); 6762 } 6763 if (Universe::narrow_oop_base() != NULL) { 6764 subq(dst, r12_heapbase); 6765 } 6766 if (Universe::narrow_oop_shift() != 0) { 6767 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6768 shrq(dst, LogMinObjAlignmentInBytes); 6769 } 6770 } 6771 6772 void MacroAssembler::decode_heap_oop(Register r) { 6773 #ifdef ASSERT 6774 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 6775 #endif 6776 if (Universe::narrow_oop_base() == NULL) { 6777 if (Universe::narrow_oop_shift() != 0) { 6778 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6779 shlq(r, LogMinObjAlignmentInBytes); 6780 } 6781 } else { 6782 Label done; 6783 shlq(r, LogMinObjAlignmentInBytes); 6784 jccb(Assembler::equal, done); 6785 addq(r, r12_heapbase); 6786 bind(done); 6787 } 6788 verify_oop(r, "broken oop in decode_heap_oop"); 6789 } 6790 6791 void MacroAssembler::decode_heap_oop_not_null(Register r) { 6792 // Note: it will change flags 6793 assert (UseCompressedOops, "should only be used for compressed headers"); 6794 assert (Universe::heap() != NULL, "java heap should be initialized"); 6795 // Cannot assert, unverified entry point counts instructions (see .ad file) 6796 // vtableStubs also counts instructions in pd_code_size_limit. 6797 // Also do not verify_oop as this is called by verify_oop. 6798 if (Universe::narrow_oop_shift() != 0) { 6799 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6800 shlq(r, LogMinObjAlignmentInBytes); 6801 if (Universe::narrow_oop_base() != NULL) { 6802 addq(r, r12_heapbase); 6803 } 6804 } else { 6805 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6806 } 6807 } 6808 6809 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 6810 // Note: it will change flags 6811 assert (UseCompressedOops, "should only be used for compressed headers"); 6812 assert (Universe::heap() != NULL, "java heap should be initialized"); 6813 // Cannot assert, unverified entry point counts instructions (see .ad file) 6814 // vtableStubs also counts instructions in pd_code_size_limit. 6815 // Also do not verify_oop as this is called by verify_oop. 6816 if (Universe::narrow_oop_shift() != 0) { 6817 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6818 if (LogMinObjAlignmentInBytes == Address::times_8) { 6819 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 6820 } else { 6821 if (dst != src) { 6822 movq(dst, src); 6823 } 6824 shlq(dst, LogMinObjAlignmentInBytes); 6825 if (Universe::narrow_oop_base() != NULL) { 6826 addq(dst, r12_heapbase); 6827 } 6828 } 6829 } else { 6830 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6831 if (dst != src) { 6832 movq(dst, src); 6833 } 6834 } 6835 } 6836 6837 void MacroAssembler::encode_klass_not_null(Register r) { 6838 if (Universe::narrow_klass_base() != NULL) { 6839 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6840 assert(r != r12_heapbase, "Encoding a klass in r12"); 6841 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6842 subq(r, r12_heapbase); 6843 } 6844 if (Universe::narrow_klass_shift() != 0) { 6845 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6846 shrq(r, LogKlassAlignmentInBytes); 6847 } 6848 if (Universe::narrow_klass_base() != NULL) { 6849 reinit_heapbase(); 6850 } 6851 } 6852 6853 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 6854 if (dst == src) { 6855 encode_klass_not_null(src); 6856 } else { 6857 if (Universe::narrow_klass_base() != NULL) { 6858 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6859 negq(dst); 6860 addq(dst, src); 6861 } else { 6862 movptr(dst, src); 6863 } 6864 if (Universe::narrow_klass_shift() != 0) { 6865 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6866 shrq(dst, LogKlassAlignmentInBytes); 6867 } 6868 } 6869 } 6870 6871 // Function instr_size_for_decode_klass_not_null() counts the instructions 6872 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 6873 // when (Universe::heap() != NULL). Hence, if the instructions they 6874 // generate change, then this method needs to be updated. 6875 int MacroAssembler::instr_size_for_decode_klass_not_null() { 6876 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 6877 if (Universe::narrow_klass_base() != NULL) { 6878 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 6879 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 6880 } else { 6881 // longest load decode klass function, mov64, leaq 6882 return 16; 6883 } 6884 } 6885 6886 // !!! If the instructions that get generated here change then function 6887 // instr_size_for_decode_klass_not_null() needs to get updated. 6888 void MacroAssembler::decode_klass_not_null(Register r) { 6889 // Note: it will change flags 6890 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6891 assert(r != r12_heapbase, "Decoding a klass in r12"); 6892 // Cannot assert, unverified entry point counts instructions (see .ad file) 6893 // vtableStubs also counts instructions in pd_code_size_limit. 6894 // Also do not verify_oop as this is called by verify_oop. 6895 if (Universe::narrow_klass_shift() != 0) { 6896 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6897 shlq(r, LogKlassAlignmentInBytes); 6898 } 6899 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6900 if (Universe::narrow_klass_base() != NULL) { 6901 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6902 addq(r, r12_heapbase); 6903 reinit_heapbase(); 6904 } 6905 } 6906 6907 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 6908 // Note: it will change flags 6909 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6910 if (dst == src) { 6911 decode_klass_not_null(dst); 6912 } else { 6913 // Cannot assert, unverified entry point counts instructions (see .ad file) 6914 // vtableStubs also counts instructions in pd_code_size_limit. 6915 // Also do not verify_oop as this is called by verify_oop. 6916 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6917 if (Universe::narrow_klass_shift() != 0) { 6918 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6919 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 6920 leaq(dst, Address(dst, src, Address::times_8, 0)); 6921 } else { 6922 addq(dst, src); 6923 } 6924 } 6925 } 6926 6927 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 6928 assert (UseCompressedOops, "should only be used for compressed headers"); 6929 assert (Universe::heap() != NULL, "java heap should be initialized"); 6930 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6931 int oop_index = oop_recorder()->find_index(obj); 6932 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6933 mov_narrow_oop(dst, oop_index, rspec); 6934 } 6935 6936 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 6937 assert (UseCompressedOops, "should only be used for compressed headers"); 6938 assert (Universe::heap() != NULL, "java heap should be initialized"); 6939 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6940 int oop_index = oop_recorder()->find_index(obj); 6941 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6942 mov_narrow_oop(dst, oop_index, rspec); 6943 } 6944 6945 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 6946 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6947 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6948 int klass_index = oop_recorder()->find_index(k); 6949 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6950 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6951 } 6952 6953 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 6954 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6955 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6956 int klass_index = oop_recorder()->find_index(k); 6957 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6958 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 6959 } 6960 6961 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 6962 assert (UseCompressedOops, "should only be used for compressed headers"); 6963 assert (Universe::heap() != NULL, "java heap should be initialized"); 6964 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6965 int oop_index = oop_recorder()->find_index(obj); 6966 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6967 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6968 } 6969 6970 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 6971 assert (UseCompressedOops, "should only be used for compressed headers"); 6972 assert (Universe::heap() != NULL, "java heap should be initialized"); 6973 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6974 int oop_index = oop_recorder()->find_index(obj); 6975 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6976 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 6977 } 6978 6979 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 6980 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6981 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6982 int klass_index = oop_recorder()->find_index(k); 6983 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6984 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6985 } 6986 6987 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 6988 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6989 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6990 int klass_index = oop_recorder()->find_index(k); 6991 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6992 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 6993 } 6994 6995 void MacroAssembler::reinit_heapbase() { 6996 if (UseCompressedOops || UseCompressedClassPointers) { 6997 if (Universe::heap() != NULL) { 6998 if (Universe::narrow_oop_base() == NULL) { 6999 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 7000 } else { 7001 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 7002 } 7003 } else { 7004 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 7005 } 7006 } 7007 } 7008 7009 #endif // _LP64 7010 7011 7012 // C2 compiled method's prolog code. 7013 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 7014 7015 // WARNING: Initial instruction MUST be 5 bytes or longer so that 7016 // NativeJump::patch_verified_entry will be able to patch out the entry 7017 // code safely. The push to verify stack depth is ok at 5 bytes, 7018 // the frame allocation can be either 3 or 6 bytes. So if we don't do 7019 // stack bang then we must use the 6 byte frame allocation even if 7020 // we have no frame. :-( 7021 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 7022 7023 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 7024 // Remove word for return addr 7025 framesize -= wordSize; 7026 stack_bang_size -= wordSize; 7027 7028 // Calls to C2R adapters often do not accept exceptional returns. 7029 // We require that their callers must bang for them. But be careful, because 7030 // some VM calls (such as call site linkage) can use several kilobytes of 7031 // stack. But the stack safety zone should account for that. 7032 // See bugs 4446381, 4468289, 4497237. 7033 if (stack_bang_size > 0) { 7034 generate_stack_overflow_check(stack_bang_size); 7035 7036 // We always push rbp, so that on return to interpreter rbp, will be 7037 // restored correctly and we can correct the stack. 7038 push(rbp); 7039 // Save caller's stack pointer into RBP if the frame pointer is preserved. 7040 if (PreserveFramePointer) { 7041 mov(rbp, rsp); 7042 } 7043 // Remove word for ebp 7044 framesize -= wordSize; 7045 7046 // Create frame 7047 if (framesize) { 7048 subptr(rsp, framesize); 7049 } 7050 } else { 7051 // Create frame (force generation of a 4 byte immediate value) 7052 subptr_imm32(rsp, framesize); 7053 7054 // Save RBP register now. 7055 framesize -= wordSize; 7056 movptr(Address(rsp, framesize), rbp); 7057 // Save caller's stack pointer into RBP if the frame pointer is preserved. 7058 if (PreserveFramePointer) { 7059 movptr(rbp, rsp); 7060 if (framesize > 0) { 7061 addptr(rbp, framesize); 7062 } 7063 } 7064 } 7065 7066 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 7067 framesize -= wordSize; 7068 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 7069 } 7070 7071 #ifndef _LP64 7072 // If method sets FPU control word do it now 7073 if (fp_mode_24b) { 7074 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 7075 } 7076 if (UseSSE >= 2 && VerifyFPU) { 7077 verify_FPU(0, "FPU stack must be clean on entry"); 7078 } 7079 #endif 7080 7081 #ifdef ASSERT 7082 if (VerifyStackAtCalls) { 7083 Label L; 7084 push(rax); 7085 mov(rax, rsp); 7086 andptr(rax, StackAlignmentInBytes-1); 7087 cmpptr(rax, StackAlignmentInBytes-wordSize); 7088 pop(rax); 7089 jcc(Assembler::equal, L); 7090 STOP("Stack is not properly aligned!"); 7091 bind(L); 7092 } 7093 #endif 7094 7095 } 7096 7097 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) { 7098 // cnt - number of qwords (8-byte words). 7099 // base - start address, qword aligned. 7100 // is_large - if optimizers know cnt is larger than InitArrayShortSize 7101 assert(base==rdi, "base register must be edi for rep stos"); 7102 assert(tmp==rax, "tmp register must be eax for rep stos"); 7103 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 7104 assert(InitArrayShortSize % BytesPerLong == 0, 7105 "InitArrayShortSize should be the multiple of BytesPerLong"); 7106 7107 Label DONE; 7108 7109 xorptr(tmp, tmp); 7110 7111 if (!is_large) { 7112 Label LOOP, LONG; 7113 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 7114 jccb(Assembler::greater, LONG); 7115 7116 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7117 7118 decrement(cnt); 7119 jccb(Assembler::negative, DONE); // Zero length 7120 7121 // Use individual pointer-sized stores for small counts: 7122 BIND(LOOP); 7123 movptr(Address(base, cnt, Address::times_ptr), tmp); 7124 decrement(cnt); 7125 jccb(Assembler::greaterEqual, LOOP); 7126 jmpb(DONE); 7127 7128 BIND(LONG); 7129 } 7130 7131 // Use longer rep-prefixed ops for non-small counts: 7132 if (UseFastStosb) { 7133 shlptr(cnt, 3); // convert to number of bytes 7134 rep_stosb(); 7135 } else { 7136 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7137 rep_stos(); 7138 } 7139 7140 BIND(DONE); 7141 } 7142 7143 #ifdef COMPILER2 7144 7145 // IndexOf for constant substrings with size >= 8 chars 7146 // which don't need to be loaded through stack. 7147 void MacroAssembler::string_indexofC8(Register str1, Register str2, 7148 Register cnt1, Register cnt2, 7149 int int_cnt2, Register result, 7150 XMMRegister vec, Register tmp, 7151 int ae) { 7152 ShortBranchVerifier sbv(this); 7153 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7154 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7155 7156 // This method uses the pcmpestri instruction with bound registers 7157 // inputs: 7158 // xmm - substring 7159 // rax - substring length (elements count) 7160 // mem - scanned string 7161 // rdx - string length (elements count) 7162 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7163 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7164 // outputs: 7165 // rcx - matched index in string 7166 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7167 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7168 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7169 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7170 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7171 7172 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 7173 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 7174 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 7175 7176 // Note, inline_string_indexOf() generates checks: 7177 // if (substr.count > string.count) return -1; 7178 // if (substr.count == 0) return 0; 7179 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars"); 7180 7181 // Load substring. 7182 if (ae == StrIntrinsicNode::UL) { 7183 pmovzxbw(vec, Address(str2, 0)); 7184 } else { 7185 movdqu(vec, Address(str2, 0)); 7186 } 7187 movl(cnt2, int_cnt2); 7188 movptr(result, str1); // string addr 7189 7190 if (int_cnt2 > stride) { 7191 jmpb(SCAN_TO_SUBSTR); 7192 7193 // Reload substr for rescan, this code 7194 // is executed only for large substrings (> 8 chars) 7195 bind(RELOAD_SUBSTR); 7196 if (ae == StrIntrinsicNode::UL) { 7197 pmovzxbw(vec, Address(str2, 0)); 7198 } else { 7199 movdqu(vec, Address(str2, 0)); 7200 } 7201 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 7202 7203 bind(RELOAD_STR); 7204 // We came here after the beginning of the substring was 7205 // matched but the rest of it was not so we need to search 7206 // again. Start from the next element after the previous match. 7207 7208 // cnt2 is number of substring reminding elements and 7209 // cnt1 is number of string reminding elements when cmp failed. 7210 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 7211 subl(cnt1, cnt2); 7212 addl(cnt1, int_cnt2); 7213 movl(cnt2, int_cnt2); // Now restore cnt2 7214 7215 decrementl(cnt1); // Shift to next element 7216 cmpl(cnt1, cnt2); 7217 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7218 7219 addptr(result, (1<<scale1)); 7220 7221 } // (int_cnt2 > 8) 7222 7223 // Scan string for start of substr in 16-byte vectors 7224 bind(SCAN_TO_SUBSTR); 7225 pcmpestri(vec, Address(result, 0), mode); 7226 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7227 subl(cnt1, stride); 7228 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7229 cmpl(cnt1, cnt2); 7230 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7231 addptr(result, 16); 7232 jmpb(SCAN_TO_SUBSTR); 7233 7234 // Found a potential substr 7235 bind(FOUND_CANDIDATE); 7236 // Matched whole vector if first element matched (tmp(rcx) == 0). 7237 if (int_cnt2 == stride) { 7238 jccb(Assembler::overflow, RET_FOUND); // OF == 1 7239 } else { // int_cnt2 > 8 7240 jccb(Assembler::overflow, FOUND_SUBSTR); 7241 } 7242 // After pcmpestri tmp(rcx) contains matched element index 7243 // Compute start addr of substr 7244 lea(result, Address(result, tmp, scale1)); 7245 7246 // Make sure string is still long enough 7247 subl(cnt1, tmp); 7248 cmpl(cnt1, cnt2); 7249 if (int_cnt2 == stride) { 7250 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7251 } else { // int_cnt2 > 8 7252 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 7253 } 7254 // Left less then substring. 7255 7256 bind(RET_NOT_FOUND); 7257 movl(result, -1); 7258 jmp(EXIT); 7259 7260 if (int_cnt2 > stride) { 7261 // This code is optimized for the case when whole substring 7262 // is matched if its head is matched. 7263 bind(MATCH_SUBSTR_HEAD); 7264 pcmpestri(vec, Address(result, 0), mode); 7265 // Reload only string if does not match 7266 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0 7267 7268 Label CONT_SCAN_SUBSTR; 7269 // Compare the rest of substring (> 8 chars). 7270 bind(FOUND_SUBSTR); 7271 // First 8 chars are already matched. 7272 negptr(cnt2); 7273 addptr(cnt2, stride); 7274 7275 bind(SCAN_SUBSTR); 7276 subl(cnt1, stride); 7277 cmpl(cnt2, -stride); // Do not read beyond substring 7278 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 7279 // Back-up strings to avoid reading beyond substring: 7280 // cnt1 = cnt1 - cnt2 + 8 7281 addl(cnt1, cnt2); // cnt2 is negative 7282 addl(cnt1, stride); 7283 movl(cnt2, stride); negptr(cnt2); 7284 bind(CONT_SCAN_SUBSTR); 7285 if (int_cnt2 < (int)G) { 7286 int tail_off1 = int_cnt2<<scale1; 7287 int tail_off2 = int_cnt2<<scale2; 7288 if (ae == StrIntrinsicNode::UL) { 7289 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2)); 7290 } else { 7291 movdqu(vec, Address(str2, cnt2, scale2, tail_off2)); 7292 } 7293 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode); 7294 } else { 7295 // calculate index in register to avoid integer overflow (int_cnt2*2) 7296 movl(tmp, int_cnt2); 7297 addptr(tmp, cnt2); 7298 if (ae == StrIntrinsicNode::UL) { 7299 pmovzxbw(vec, Address(str2, tmp, scale2, 0)); 7300 } else { 7301 movdqu(vec, Address(str2, tmp, scale2, 0)); 7302 } 7303 pcmpestri(vec, Address(result, tmp, scale1, 0), mode); 7304 } 7305 // Need to reload strings pointers if not matched whole vector 7306 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7307 addptr(cnt2, stride); 7308 jcc(Assembler::negative, SCAN_SUBSTR); 7309 // Fall through if found full substring 7310 7311 } // (int_cnt2 > 8) 7312 7313 bind(RET_FOUND); 7314 // Found result if we matched full small substring. 7315 // Compute substr offset 7316 subptr(result, str1); 7317 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7318 shrl(result, 1); // index 7319 } 7320 bind(EXIT); 7321 7322 } // string_indexofC8 7323 7324 // Small strings are loaded through stack if they cross page boundary. 7325 void MacroAssembler::string_indexof(Register str1, Register str2, 7326 Register cnt1, Register cnt2, 7327 int int_cnt2, Register result, 7328 XMMRegister vec, Register tmp, 7329 int ae) { 7330 ShortBranchVerifier sbv(this); 7331 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7332 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7333 7334 // 7335 // int_cnt2 is length of small (< 8 chars) constant substring 7336 // or (-1) for non constant substring in which case its length 7337 // is in cnt2 register. 7338 // 7339 // Note, inline_string_indexOf() generates checks: 7340 // if (substr.count > string.count) return -1; 7341 // if (substr.count == 0) return 0; 7342 // 7343 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7344 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0"); 7345 // This method uses the pcmpestri instruction with bound registers 7346 // inputs: 7347 // xmm - substring 7348 // rax - substring length (elements count) 7349 // mem - scanned string 7350 // rdx - string length (elements count) 7351 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7352 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7353 // outputs: 7354 // rcx - matched index in string 7355 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7356 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7357 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7358 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7359 7360 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 7361 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 7362 FOUND_CANDIDATE; 7363 7364 { //======================================================== 7365 // We don't know where these strings are located 7366 // and we can't read beyond them. Load them through stack. 7367 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 7368 7369 movptr(tmp, rsp); // save old SP 7370 7371 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 7372 if (int_cnt2 == (1>>scale2)) { // One byte 7373 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding"); 7374 load_unsigned_byte(result, Address(str2, 0)); 7375 movdl(vec, result); // move 32 bits 7376 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes 7377 // Not enough header space in 32-bit VM: 12+3 = 15. 7378 movl(result, Address(str2, -1)); 7379 shrl(result, 8); 7380 movdl(vec, result); // move 32 bits 7381 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char 7382 load_unsigned_short(result, Address(str2, 0)); 7383 movdl(vec, result); // move 32 bits 7384 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars 7385 movdl(vec, Address(str2, 0)); // move 32 bits 7386 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars 7387 movq(vec, Address(str2, 0)); // move 64 bits 7388 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7}) 7389 // Array header size is 12 bytes in 32-bit VM 7390 // + 6 bytes for 3 chars == 18 bytes, 7391 // enough space to load vec and shift. 7392 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 7393 if (ae == StrIntrinsicNode::UL) { 7394 int tail_off = int_cnt2-8; 7395 pmovzxbw(vec, Address(str2, tail_off)); 7396 psrldq(vec, -2*tail_off); 7397 } 7398 else { 7399 int tail_off = int_cnt2*(1<<scale2); 7400 movdqu(vec, Address(str2, tail_off-16)); 7401 psrldq(vec, 16-tail_off); 7402 } 7403 } 7404 } else { // not constant substring 7405 cmpl(cnt2, stride); 7406 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 7407 7408 // We can read beyond string if srt+16 does not cross page boundary 7409 // since heaps are aligned and mapped by pages. 7410 assert(os::vm_page_size() < (int)G, "default page should be small"); 7411 movl(result, str2); // We need only low 32 bits 7412 andl(result, (os::vm_page_size()-1)); 7413 cmpl(result, (os::vm_page_size()-16)); 7414 jccb(Assembler::belowEqual, CHECK_STR); 7415 7416 // Move small strings to stack to allow load 16 bytes into vec. 7417 subptr(rsp, 16); 7418 int stk_offset = wordSize-(1<<scale2); 7419 push(cnt2); 7420 7421 bind(COPY_SUBSTR); 7422 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) { 7423 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1)); 7424 movb(Address(rsp, cnt2, scale2, stk_offset), result); 7425 } else if (ae == StrIntrinsicNode::UU) { 7426 load_unsigned_short(result, Address(str2, cnt2, scale2, -2)); 7427 movw(Address(rsp, cnt2, scale2, stk_offset), result); 7428 } 7429 decrement(cnt2); 7430 jccb(Assembler::notZero, COPY_SUBSTR); 7431 7432 pop(cnt2); 7433 movptr(str2, rsp); // New substring address 7434 } // non constant 7435 7436 bind(CHECK_STR); 7437 cmpl(cnt1, stride); 7438 jccb(Assembler::aboveEqual, BIG_STRINGS); 7439 7440 // Check cross page boundary. 7441 movl(result, str1); // We need only low 32 bits 7442 andl(result, (os::vm_page_size()-1)); 7443 cmpl(result, (os::vm_page_size()-16)); 7444 jccb(Assembler::belowEqual, BIG_STRINGS); 7445 7446 subptr(rsp, 16); 7447 int stk_offset = -(1<<scale1); 7448 if (int_cnt2 < 0) { // not constant 7449 push(cnt2); 7450 stk_offset += wordSize; 7451 } 7452 movl(cnt2, cnt1); 7453 7454 bind(COPY_STR); 7455 if (ae == StrIntrinsicNode::LL) { 7456 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1)); 7457 movb(Address(rsp, cnt2, scale1, stk_offset), result); 7458 } else { 7459 load_unsigned_short(result, Address(str1, cnt2, scale1, -2)); 7460 movw(Address(rsp, cnt2, scale1, stk_offset), result); 7461 } 7462 decrement(cnt2); 7463 jccb(Assembler::notZero, COPY_STR); 7464 7465 if (int_cnt2 < 0) { // not constant 7466 pop(cnt2); 7467 } 7468 movptr(str1, rsp); // New string address 7469 7470 bind(BIG_STRINGS); 7471 // Load substring. 7472 if (int_cnt2 < 0) { // -1 7473 if (ae == StrIntrinsicNode::UL) { 7474 pmovzxbw(vec, Address(str2, 0)); 7475 } else { 7476 movdqu(vec, Address(str2, 0)); 7477 } 7478 push(cnt2); // substr count 7479 push(str2); // substr addr 7480 push(str1); // string addr 7481 } else { 7482 // Small (< 8 chars) constant substrings are loaded already. 7483 movl(cnt2, int_cnt2); 7484 } 7485 push(tmp); // original SP 7486 7487 } // Finished loading 7488 7489 //======================================================== 7490 // Start search 7491 // 7492 7493 movptr(result, str1); // string addr 7494 7495 if (int_cnt2 < 0) { // Only for non constant substring 7496 jmpb(SCAN_TO_SUBSTR); 7497 7498 // SP saved at sp+0 7499 // String saved at sp+1*wordSize 7500 // Substr saved at sp+2*wordSize 7501 // Substr count saved at sp+3*wordSize 7502 7503 // Reload substr for rescan, this code 7504 // is executed only for large substrings (> 8 chars) 7505 bind(RELOAD_SUBSTR); 7506 movptr(str2, Address(rsp, 2*wordSize)); 7507 movl(cnt2, Address(rsp, 3*wordSize)); 7508 if (ae == StrIntrinsicNode::UL) { 7509 pmovzxbw(vec, Address(str2, 0)); 7510 } else { 7511 movdqu(vec, Address(str2, 0)); 7512 } 7513 // We came here after the beginning of the substring was 7514 // matched but the rest of it was not so we need to search 7515 // again. Start from the next element after the previous match. 7516 subptr(str1, result); // Restore counter 7517 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7518 shrl(str1, 1); 7519 } 7520 addl(cnt1, str1); 7521 decrementl(cnt1); // Shift to next element 7522 cmpl(cnt1, cnt2); 7523 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7524 7525 addptr(result, (1<<scale1)); 7526 } // non constant 7527 7528 // Scan string for start of substr in 16-byte vectors 7529 bind(SCAN_TO_SUBSTR); 7530 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7531 pcmpestri(vec, Address(result, 0), mode); 7532 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7533 subl(cnt1, stride); 7534 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7535 cmpl(cnt1, cnt2); 7536 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7537 addptr(result, 16); 7538 7539 bind(ADJUST_STR); 7540 cmpl(cnt1, stride); // Do not read beyond string 7541 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7542 // Back-up string to avoid reading beyond string. 7543 lea(result, Address(result, cnt1, scale1, -16)); 7544 movl(cnt1, stride); 7545 jmpb(SCAN_TO_SUBSTR); 7546 7547 // Found a potential substr 7548 bind(FOUND_CANDIDATE); 7549 // After pcmpestri tmp(rcx) contains matched element index 7550 7551 // Make sure string is still long enough 7552 subl(cnt1, tmp); 7553 cmpl(cnt1, cnt2); 7554 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 7555 // Left less then substring. 7556 7557 bind(RET_NOT_FOUND); 7558 movl(result, -1); 7559 jmpb(CLEANUP); 7560 7561 bind(FOUND_SUBSTR); 7562 // Compute start addr of substr 7563 lea(result, Address(result, tmp, scale1)); 7564 if (int_cnt2 > 0) { // Constant substring 7565 // Repeat search for small substring (< 8 chars) 7566 // from new point without reloading substring. 7567 // Have to check that we don't read beyond string. 7568 cmpl(tmp, stride-int_cnt2); 7569 jccb(Assembler::greater, ADJUST_STR); 7570 // Fall through if matched whole substring. 7571 } else { // non constant 7572 assert(int_cnt2 == -1, "should be != 0"); 7573 7574 addl(tmp, cnt2); 7575 // Found result if we matched whole substring. 7576 cmpl(tmp, stride); 7577 jccb(Assembler::lessEqual, RET_FOUND); 7578 7579 // Repeat search for small substring (<= 8 chars) 7580 // from new point 'str1' without reloading substring. 7581 cmpl(cnt2, stride); 7582 // Have to check that we don't read beyond string. 7583 jccb(Assembler::lessEqual, ADJUST_STR); 7584 7585 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 7586 // Compare the rest of substring (> 8 chars). 7587 movptr(str1, result); 7588 7589 cmpl(tmp, cnt2); 7590 // First 8 chars are already matched. 7591 jccb(Assembler::equal, CHECK_NEXT); 7592 7593 bind(SCAN_SUBSTR); 7594 pcmpestri(vec, Address(str1, 0), mode); 7595 // Need to reload strings pointers if not matched whole vector 7596 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7597 7598 bind(CHECK_NEXT); 7599 subl(cnt2, stride); 7600 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 7601 addptr(str1, 16); 7602 if (ae == StrIntrinsicNode::UL) { 7603 addptr(str2, 8); 7604 } else { 7605 addptr(str2, 16); 7606 } 7607 subl(cnt1, stride); 7608 cmpl(cnt2, stride); // Do not read beyond substring 7609 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 7610 // Back-up strings to avoid reading beyond substring. 7611 7612 if (ae == StrIntrinsicNode::UL) { 7613 lea(str2, Address(str2, cnt2, scale2, -8)); 7614 lea(str1, Address(str1, cnt2, scale1, -16)); 7615 } else { 7616 lea(str2, Address(str2, cnt2, scale2, -16)); 7617 lea(str1, Address(str1, cnt2, scale1, -16)); 7618 } 7619 subl(cnt1, cnt2); 7620 movl(cnt2, stride); 7621 addl(cnt1, stride); 7622 bind(CONT_SCAN_SUBSTR); 7623 if (ae == StrIntrinsicNode::UL) { 7624 pmovzxbw(vec, Address(str2, 0)); 7625 } else { 7626 movdqu(vec, Address(str2, 0)); 7627 } 7628 jmp(SCAN_SUBSTR); 7629 7630 bind(RET_FOUND_LONG); 7631 movptr(str1, Address(rsp, wordSize)); 7632 } // non constant 7633 7634 bind(RET_FOUND); 7635 // Compute substr offset 7636 subptr(result, str1); 7637 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7638 shrl(result, 1); // index 7639 } 7640 bind(CLEANUP); 7641 pop(rsp); // restore SP 7642 7643 } // string_indexof 7644 7645 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result, 7646 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) { 7647 ShortBranchVerifier sbv(this); 7648 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7649 7650 int stride = 8; 7651 7652 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP, 7653 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP, 7654 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT, 7655 FOUND_SEQ_CHAR, DONE_LABEL; 7656 7657 movptr(result, str1); 7658 if (UseAVX >= 2) { 7659 cmpl(cnt1, stride); 7660 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7661 cmpl(cnt1, 2*stride); 7662 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT); 7663 movdl(vec1, ch); 7664 vpbroadcastw(vec1, vec1); 7665 vpxor(vec2, vec2); 7666 movl(tmp, cnt1); 7667 andl(tmp, 0xFFFFFFF0); //vector count (in chars) 7668 andl(cnt1,0x0000000F); //tail count (in chars) 7669 7670 bind(SCAN_TO_16_CHAR_LOOP); 7671 vmovdqu(vec3, Address(result, 0)); 7672 vpcmpeqw(vec3, vec3, vec1, 1); 7673 vptest(vec2, vec3); 7674 jcc(Assembler::carryClear, FOUND_CHAR); 7675 addptr(result, 32); 7676 subl(tmp, 2*stride); 7677 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP); 7678 jmp(SCAN_TO_8_CHAR); 7679 bind(SCAN_TO_8_CHAR_INIT); 7680 movdl(vec1, ch); 7681 pshuflw(vec1, vec1, 0x00); 7682 pshufd(vec1, vec1, 0); 7683 pxor(vec2, vec2); 7684 } 7685 bind(SCAN_TO_8_CHAR); 7686 cmpl(cnt1, stride); 7687 if (UseAVX >= 2) { 7688 jcc(Assembler::less, SCAN_TO_CHAR); 7689 } else { 7690 jcc(Assembler::less, SCAN_TO_CHAR_LOOP); 7691 movdl(vec1, ch); 7692 pshuflw(vec1, vec1, 0x00); 7693 pshufd(vec1, vec1, 0); 7694 pxor(vec2, vec2); 7695 } 7696 movl(tmp, cnt1); 7697 andl(tmp, 0xFFFFFFF8); //vector count (in chars) 7698 andl(cnt1,0x00000007); //tail count (in chars) 7699 7700 bind(SCAN_TO_8_CHAR_LOOP); 7701 movdqu(vec3, Address(result, 0)); 7702 pcmpeqw(vec3, vec1); 7703 ptest(vec2, vec3); 7704 jcc(Assembler::carryClear, FOUND_CHAR); 7705 addptr(result, 16); 7706 subl(tmp, stride); 7707 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP); 7708 bind(SCAN_TO_CHAR); 7709 testl(cnt1, cnt1); 7710 jcc(Assembler::zero, RET_NOT_FOUND); 7711 bind(SCAN_TO_CHAR_LOOP); 7712 load_unsigned_short(tmp, Address(result, 0)); 7713 cmpl(ch, tmp); 7714 jccb(Assembler::equal, FOUND_SEQ_CHAR); 7715 addptr(result, 2); 7716 subl(cnt1, 1); 7717 jccb(Assembler::zero, RET_NOT_FOUND); 7718 jmp(SCAN_TO_CHAR_LOOP); 7719 7720 bind(RET_NOT_FOUND); 7721 movl(result, -1); 7722 jmpb(DONE_LABEL); 7723 7724 bind(FOUND_CHAR); 7725 if (UseAVX >= 2) { 7726 vpmovmskb(tmp, vec3); 7727 } else { 7728 pmovmskb(tmp, vec3); 7729 } 7730 bsfl(ch, tmp); 7731 addl(result, ch); 7732 7733 bind(FOUND_SEQ_CHAR); 7734 subptr(result, str1); 7735 shrl(result, 1); 7736 7737 bind(DONE_LABEL); 7738 } // string_indexof_char 7739 7740 // helper function for string_compare 7741 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2, 7742 Address::ScaleFactor scale, Address::ScaleFactor scale1, 7743 Address::ScaleFactor scale2, Register index, int ae) { 7744 if (ae == StrIntrinsicNode::LL) { 7745 load_unsigned_byte(elem1, Address(str1, index, scale, 0)); 7746 load_unsigned_byte(elem2, Address(str2, index, scale, 0)); 7747 } else if (ae == StrIntrinsicNode::UU) { 7748 load_unsigned_short(elem1, Address(str1, index, scale, 0)); 7749 load_unsigned_short(elem2, Address(str2, index, scale, 0)); 7750 } else { 7751 load_unsigned_byte(elem1, Address(str1, index, scale1, 0)); 7752 load_unsigned_short(elem2, Address(str2, index, scale2, 0)); 7753 } 7754 } 7755 7756 // Compare strings, used for char[] and byte[]. 7757 void MacroAssembler::string_compare(Register str1, Register str2, 7758 Register cnt1, Register cnt2, Register result, 7759 XMMRegister vec1, int ae) { 7760 ShortBranchVerifier sbv(this); 7761 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 7762 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3 7763 int stride, stride2, adr_stride, adr_stride1, adr_stride2; 7764 int stride2x2 = 0x40; 7765 Address::ScaleFactor scale = Address::no_scale; 7766 Address::ScaleFactor scale1 = Address::no_scale; 7767 Address::ScaleFactor scale2 = Address::no_scale; 7768 7769 if (ae != StrIntrinsicNode::LL) { 7770 stride2x2 = 0x20; 7771 } 7772 7773 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 7774 shrl(cnt2, 1); 7775 } 7776 // Compute the minimum of the string lengths and the 7777 // difference of the string lengths (stack). 7778 // Do the conditional move stuff 7779 movl(result, cnt1); 7780 subl(cnt1, cnt2); 7781 push(cnt1); 7782 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2) 7783 7784 // Is the minimum length zero? 7785 testl(cnt2, cnt2); 7786 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7787 if (ae == StrIntrinsicNode::LL) { 7788 // Load first bytes 7789 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0] 7790 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0] 7791 } else if (ae == StrIntrinsicNode::UU) { 7792 // Load first characters 7793 load_unsigned_short(result, Address(str1, 0)); 7794 load_unsigned_short(cnt1, Address(str2, 0)); 7795 } else { 7796 load_unsigned_byte(result, Address(str1, 0)); 7797 load_unsigned_short(cnt1, Address(str2, 0)); 7798 } 7799 subl(result, cnt1); 7800 jcc(Assembler::notZero, POP_LABEL); 7801 7802 if (ae == StrIntrinsicNode::UU) { 7803 // Divide length by 2 to get number of chars 7804 shrl(cnt2, 1); 7805 } 7806 cmpl(cnt2, 1); 7807 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7808 7809 // Check if the strings start at the same location and setup scale and stride 7810 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7811 cmpptr(str1, str2); 7812 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7813 if (ae == StrIntrinsicNode::LL) { 7814 scale = Address::times_1; 7815 stride = 16; 7816 } else { 7817 scale = Address::times_2; 7818 stride = 8; 7819 } 7820 } else { 7821 scale1 = Address::times_1; 7822 scale2 = Address::times_2; 7823 // scale not used 7824 stride = 8; 7825 } 7826 7827 if (UseAVX >= 2 && UseSSE42Intrinsics) { 7828 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 7829 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 7830 Label COMPARE_WIDE_VECTORS_LOOP_AVX2; 7831 Label COMPARE_TAIL_LONG; 7832 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3 7833 7834 int pcmpmask = 0x19; 7835 if (ae == StrIntrinsicNode::LL) { 7836 pcmpmask &= ~0x01; 7837 } 7838 7839 // Setup to compare 16-chars (32-bytes) vectors, 7840 // start from first character again because it has aligned address. 7841 if (ae == StrIntrinsicNode::LL) { 7842 stride2 = 32; 7843 } else { 7844 stride2 = 16; 7845 } 7846 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7847 adr_stride = stride << scale; 7848 } else { 7849 adr_stride1 = 8; //stride << scale1; 7850 adr_stride2 = 16; //stride << scale2; 7851 } 7852 7853 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7854 // rax and rdx are used by pcmpestri as elements counters 7855 movl(result, cnt2); 7856 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 7857 jcc(Assembler::zero, COMPARE_TAIL_LONG); 7858 7859 // fast path : compare first 2 8-char vectors. 7860 bind(COMPARE_16_CHARS); 7861 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7862 movdqu(vec1, Address(str1, 0)); 7863 } else { 7864 pmovzxbw(vec1, Address(str1, 0)); 7865 } 7866 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7867 jccb(Assembler::below, COMPARE_INDEX_CHAR); 7868 7869 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7870 movdqu(vec1, Address(str1, adr_stride)); 7871 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 7872 } else { 7873 pmovzxbw(vec1, Address(str1, adr_stride1)); 7874 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask); 7875 } 7876 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 7877 addl(cnt1, stride); 7878 7879 // Compare the characters at index in cnt1 7880 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character 7881 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 7882 subl(result, cnt2); 7883 jmp(POP_LABEL); 7884 7885 // Setup the registers to start vector comparison loop 7886 bind(COMPARE_WIDE_VECTORS); 7887 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7888 lea(str1, Address(str1, result, scale)); 7889 lea(str2, Address(str2, result, scale)); 7890 } else { 7891 lea(str1, Address(str1, result, scale1)); 7892 lea(str2, Address(str2, result, scale2)); 7893 } 7894 subl(result, stride2); 7895 subl(cnt2, stride2); 7896 jcc(Assembler::zero, COMPARE_WIDE_TAIL); 7897 negptr(result); 7898 7899 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 7900 bind(COMPARE_WIDE_VECTORS_LOOP); 7901 7902 #ifdef _LP64 7903 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 7904 cmpl(cnt2, stride2x2); 7905 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2); 7906 testl(cnt2, stride2x2-1); // cnt2 holds the vector count 7907 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40 7908 7909 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 7910 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7911 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit); 7912 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7913 } else { 7914 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit); 7915 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 7916 } 7917 kortestql(k7, k7); 7918 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare 7919 addptr(result, stride2x2); // update since we already compared at this addr 7920 subl(cnt2, stride2x2); // and sub the size too 7921 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3); 7922 7923 vpxor(vec1, vec1); 7924 jmpb(COMPARE_WIDE_TAIL); 7925 }//if (VM_Version::supports_avx512vlbw()) 7926 #endif // _LP64 7927 7928 7929 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7930 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7931 vmovdqu(vec1, Address(str1, result, scale)); 7932 vpxor(vec1, Address(str2, result, scale)); 7933 } else { 7934 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit); 7935 vpxor(vec1, Address(str2, result, scale2)); 7936 } 7937 vptest(vec1, vec1); 7938 jcc(Assembler::notZero, VECTOR_NOT_EQUAL); 7939 addptr(result, stride2); 7940 subl(cnt2, stride2); 7941 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 7942 // clean upper bits of YMM registers 7943 vpxor(vec1, vec1); 7944 7945 // compare wide vectors tail 7946 bind(COMPARE_WIDE_TAIL); 7947 testptr(result, result); 7948 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7949 7950 movl(result, stride2); 7951 movl(cnt2, result); 7952 negptr(result); 7953 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2); 7954 7955 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 7956 bind(VECTOR_NOT_EQUAL); 7957 // clean upper bits of YMM registers 7958 vpxor(vec1, vec1); 7959 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7960 lea(str1, Address(str1, result, scale)); 7961 lea(str2, Address(str2, result, scale)); 7962 } else { 7963 lea(str1, Address(str1, result, scale1)); 7964 lea(str2, Address(str2, result, scale2)); 7965 } 7966 jmp(COMPARE_16_CHARS); 7967 7968 // Compare tail chars, length between 1 to 15 chars 7969 bind(COMPARE_TAIL_LONG); 7970 movl(cnt2, result); 7971 cmpl(cnt2, stride); 7972 jcc(Assembler::less, COMPARE_SMALL_STR); 7973 7974 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7975 movdqu(vec1, Address(str1, 0)); 7976 } else { 7977 pmovzxbw(vec1, Address(str1, 0)); 7978 } 7979 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7980 jcc(Assembler::below, COMPARE_INDEX_CHAR); 7981 subptr(cnt2, stride); 7982 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7983 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7984 lea(str1, Address(str1, result, scale)); 7985 lea(str2, Address(str2, result, scale)); 7986 } else { 7987 lea(str1, Address(str1, result, scale1)); 7988 lea(str2, Address(str2, result, scale2)); 7989 } 7990 negptr(cnt2); 7991 jmpb(WHILE_HEAD_LABEL); 7992 7993 bind(COMPARE_SMALL_STR); 7994 } else if (UseSSE42Intrinsics) { 7995 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 7996 int pcmpmask = 0x19; 7997 // Setup to compare 8-char (16-byte) vectors, 7998 // start from first character again because it has aligned address. 7999 movl(result, cnt2); 8000 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 8001 if (ae == StrIntrinsicNode::LL) { 8002 pcmpmask &= ~0x01; 8003 } 8004 jcc(Assembler::zero, COMPARE_TAIL); 8005 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8006 lea(str1, Address(str1, result, scale)); 8007 lea(str2, Address(str2, result, scale)); 8008 } else { 8009 lea(str1, Address(str1, result, scale1)); 8010 lea(str2, Address(str2, result, scale2)); 8011 } 8012 negptr(result); 8013 8014 // pcmpestri 8015 // inputs: 8016 // vec1- substring 8017 // rax - negative string length (elements count) 8018 // mem - scanned string 8019 // rdx - string length (elements count) 8020 // pcmpmask - cmp mode: 11000 (string compare with negated result) 8021 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 8022 // outputs: 8023 // rcx - first mismatched element index 8024 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 8025 8026 bind(COMPARE_WIDE_VECTORS); 8027 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8028 movdqu(vec1, Address(str1, result, scale)); 8029 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 8030 } else { 8031 pmovzxbw(vec1, Address(str1, result, scale1)); 8032 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 8033 } 8034 // After pcmpestri cnt1(rcx) contains mismatched element index 8035 8036 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 8037 addptr(result, stride); 8038 subptr(cnt2, stride); 8039 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 8040 8041 // compare wide vectors tail 8042 testptr(result, result); 8043 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 8044 8045 movl(cnt2, stride); 8046 movl(result, stride); 8047 negptr(result); 8048 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8049 movdqu(vec1, Address(str1, result, scale)); 8050 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 8051 } else { 8052 pmovzxbw(vec1, Address(str1, result, scale1)); 8053 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 8054 } 8055 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 8056 8057 // Mismatched characters in the vectors 8058 bind(VECTOR_NOT_EQUAL); 8059 addptr(cnt1, result); 8060 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 8061 subl(result, cnt2); 8062 jmpb(POP_LABEL); 8063 8064 bind(COMPARE_TAIL); // limit is zero 8065 movl(cnt2, result); 8066 // Fallthru to tail compare 8067 } 8068 // Shift str2 and str1 to the end of the arrays, negate min 8069 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8070 lea(str1, Address(str1, cnt2, scale)); 8071 lea(str2, Address(str2, cnt2, scale)); 8072 } else { 8073 lea(str1, Address(str1, cnt2, scale1)); 8074 lea(str2, Address(str2, cnt2, scale2)); 8075 } 8076 decrementl(cnt2); // first character was compared already 8077 negptr(cnt2); 8078 8079 // Compare the rest of the elements 8080 bind(WHILE_HEAD_LABEL); 8081 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae); 8082 subl(result, cnt1); 8083 jccb(Assembler::notZero, POP_LABEL); 8084 increment(cnt2); 8085 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 8086 8087 // Strings are equal up to min length. Return the length difference. 8088 bind(LENGTH_DIFF_LABEL); 8089 pop(result); 8090 if (ae == StrIntrinsicNode::UU) { 8091 // Divide diff by 2 to get number of chars 8092 sarl(result, 1); 8093 } 8094 jmpb(DONE_LABEL); 8095 8096 #ifdef _LP64 8097 if (VM_Version::supports_avx512vlbw()) { 8098 8099 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED); 8100 8101 kmovql(cnt1, k7); 8102 notq(cnt1); 8103 bsfq(cnt2, cnt1); 8104 if (ae != StrIntrinsicNode::LL) { 8105 // Divide diff by 2 to get number of chars 8106 sarl(cnt2, 1); 8107 } 8108 addq(result, cnt2); 8109 if (ae == StrIntrinsicNode::LL) { 8110 load_unsigned_byte(cnt1, Address(str2, result)); 8111 load_unsigned_byte(result, Address(str1, result)); 8112 } else if (ae == StrIntrinsicNode::UU) { 8113 load_unsigned_short(cnt1, Address(str2, result, scale)); 8114 load_unsigned_short(result, Address(str1, result, scale)); 8115 } else { 8116 load_unsigned_short(cnt1, Address(str2, result, scale2)); 8117 load_unsigned_byte(result, Address(str1, result, scale1)); 8118 } 8119 subl(result, cnt1); 8120 jmpb(POP_LABEL); 8121 }//if (VM_Version::supports_avx512vlbw()) 8122 #endif // _LP64 8123 8124 // Discard the stored length difference 8125 bind(POP_LABEL); 8126 pop(cnt1); 8127 8128 // That's it 8129 bind(DONE_LABEL); 8130 if(ae == StrIntrinsicNode::UL) { 8131 negl(result); 8132 } 8133 8134 } 8135 8136 // Search for Non-ASCII character (Negative byte value) in a byte array, 8137 // return true if it has any and false otherwise. 8138 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java 8139 // @HotSpotIntrinsicCandidate 8140 // private static boolean hasNegatives(byte[] ba, int off, int len) { 8141 // for (int i = off; i < off + len; i++) { 8142 // if (ba[i] < 0) { 8143 // return true; 8144 // } 8145 // } 8146 // return false; 8147 // } 8148 void MacroAssembler::has_negatives(Register ary1, Register len, 8149 Register result, Register tmp1, 8150 XMMRegister vec1, XMMRegister vec2) { 8151 // rsi: byte array 8152 // rcx: len 8153 // rax: result 8154 ShortBranchVerifier sbv(this); 8155 assert_different_registers(ary1, len, result, tmp1); 8156 assert_different_registers(vec1, vec2); 8157 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE; 8158 8159 // len == 0 8160 testl(len, len); 8161 jcc(Assembler::zero, FALSE_LABEL); 8162 8163 if ((UseAVX > 2) && // AVX512 8164 VM_Version::supports_avx512vlbw() && 8165 VM_Version::supports_bmi2()) { 8166 8167 set_vector_masking(); // opening of the stub context for programming mask registers 8168 8169 Label test_64_loop, test_tail; 8170 Register tmp3_aliased = len; 8171 8172 movl(tmp1, len); 8173 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit); 8174 8175 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F 8176 andl(len, ~(64 - 1)); // vector count (in chars) 8177 jccb(Assembler::zero, test_tail); 8178 8179 lea(ary1, Address(ary1, len, Address::times_1)); 8180 negptr(len); 8181 8182 bind(test_64_loop); 8183 // Check whether our 64 elements of size byte contain negatives 8184 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit); 8185 kortestql(k2, k2); 8186 jcc(Assembler::notZero, TRUE_LABEL); 8187 8188 addptr(len, 64); 8189 jccb(Assembler::notZero, test_64_loop); 8190 8191 8192 bind(test_tail); 8193 // bail out when there is nothing to be done 8194 testl(tmp1, -1); 8195 jcc(Assembler::zero, FALSE_LABEL); 8196 8197 // Save k1 8198 kmovql(k3, k1); 8199 8200 // ~(~0 << len) applied up to two times (for 32-bit scenario) 8201 #ifdef _LP64 8202 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF); 8203 shlxq(tmp3_aliased, tmp3_aliased, tmp1); 8204 notq(tmp3_aliased); 8205 kmovql(k1, tmp3_aliased); 8206 #else 8207 Label k_init; 8208 jmp(k_init); 8209 8210 // We could not read 64-bits from a general purpose register thus we move 8211 // data required to compose 64 1's to the instruction stream 8212 // We emit 64 byte wide series of elements from 0..63 which later on would 8213 // be used as a compare targets with tail count contained in tmp1 register. 8214 // Result would be a k1 register having tmp1 consecutive number or 1 8215 // counting from least significant bit. 8216 address tmp = pc(); 8217 emit_int64(0x0706050403020100); 8218 emit_int64(0x0F0E0D0C0B0A0908); 8219 emit_int64(0x1716151413121110); 8220 emit_int64(0x1F1E1D1C1B1A1918); 8221 emit_int64(0x2726252423222120); 8222 emit_int64(0x2F2E2D2C2B2A2928); 8223 emit_int64(0x3736353433323130); 8224 emit_int64(0x3F3E3D3C3B3A3938); 8225 8226 bind(k_init); 8227 lea(len, InternalAddress(tmp)); 8228 // create mask to test for negative byte inside a vector 8229 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit); 8230 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit); 8231 8232 #endif 8233 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit); 8234 ktestq(k2, k1); 8235 // Restore k1 8236 kmovql(k1, k3); 8237 jcc(Assembler::notZero, TRUE_LABEL); 8238 8239 jmp(FALSE_LABEL); 8240 8241 clear_vector_masking(); // closing of the stub context for programming mask registers 8242 } 8243 else { 8244 movl(result, len); // copy 8245 8246 if (UseAVX == 2 && UseSSE >= 2) { 8247 // With AVX2, use 32-byte vector compare 8248 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8249 8250 // Compare 32-byte vectors 8251 andl(result, 0x0000001f); // tail count (in bytes) 8252 andl(len, 0xffffffe0); // vector count (in bytes) 8253 jccb(Assembler::zero, COMPARE_TAIL); 8254 8255 lea(ary1, Address(ary1, len, Address::times_1)); 8256 negptr(len); 8257 8258 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector 8259 movdl(vec2, tmp1); 8260 vpbroadcastd(vec2, vec2); 8261 8262 bind(COMPARE_WIDE_VECTORS); 8263 vmovdqu(vec1, Address(ary1, len, Address::times_1)); 8264 vptest(vec1, vec2); 8265 jccb(Assembler::notZero, TRUE_LABEL); 8266 addptr(len, 32); 8267 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8268 8269 testl(result, result); 8270 jccb(Assembler::zero, FALSE_LABEL); 8271 8272 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8273 vptest(vec1, vec2); 8274 jccb(Assembler::notZero, TRUE_LABEL); 8275 jmpb(FALSE_LABEL); 8276 8277 bind(COMPARE_TAIL); // len is zero 8278 movl(len, result); 8279 // Fallthru to tail compare 8280 } 8281 else if (UseSSE42Intrinsics) { 8282 // With SSE4.2, use double quad vector compare 8283 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8284 8285 // Compare 16-byte vectors 8286 andl(result, 0x0000000f); // tail count (in bytes) 8287 andl(len, 0xfffffff0); // vector count (in bytes) 8288 jccb(Assembler::zero, COMPARE_TAIL); 8289 8290 lea(ary1, Address(ary1, len, Address::times_1)); 8291 negptr(len); 8292 8293 movl(tmp1, 0x80808080); 8294 movdl(vec2, tmp1); 8295 pshufd(vec2, vec2, 0); 8296 8297 bind(COMPARE_WIDE_VECTORS); 8298 movdqu(vec1, Address(ary1, len, Address::times_1)); 8299 ptest(vec1, vec2); 8300 jccb(Assembler::notZero, TRUE_LABEL); 8301 addptr(len, 16); 8302 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8303 8304 testl(result, result); 8305 jccb(Assembler::zero, FALSE_LABEL); 8306 8307 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8308 ptest(vec1, vec2); 8309 jccb(Assembler::notZero, TRUE_LABEL); 8310 jmpb(FALSE_LABEL); 8311 8312 bind(COMPARE_TAIL); // len is zero 8313 movl(len, result); 8314 // Fallthru to tail compare 8315 } 8316 } 8317 // Compare 4-byte vectors 8318 andl(len, 0xfffffffc); // vector count (in bytes) 8319 jccb(Assembler::zero, COMPARE_CHAR); 8320 8321 lea(ary1, Address(ary1, len, Address::times_1)); 8322 negptr(len); 8323 8324 bind(COMPARE_VECTORS); 8325 movl(tmp1, Address(ary1, len, Address::times_1)); 8326 andl(tmp1, 0x80808080); 8327 jccb(Assembler::notZero, TRUE_LABEL); 8328 addptr(len, 4); 8329 jcc(Assembler::notZero, COMPARE_VECTORS); 8330 8331 // Compare trailing char (final 2 bytes), if any 8332 bind(COMPARE_CHAR); 8333 testl(result, 0x2); // tail char 8334 jccb(Assembler::zero, COMPARE_BYTE); 8335 load_unsigned_short(tmp1, Address(ary1, 0)); 8336 andl(tmp1, 0x00008080); 8337 jccb(Assembler::notZero, TRUE_LABEL); 8338 subptr(result, 2); 8339 lea(ary1, Address(ary1, 2)); 8340 8341 bind(COMPARE_BYTE); 8342 testl(result, 0x1); // tail byte 8343 jccb(Assembler::zero, FALSE_LABEL); 8344 load_unsigned_byte(tmp1, Address(ary1, 0)); 8345 andl(tmp1, 0x00000080); 8346 jccb(Assembler::notEqual, TRUE_LABEL); 8347 jmpb(FALSE_LABEL); 8348 8349 bind(TRUE_LABEL); 8350 movl(result, 1); // return true 8351 jmpb(DONE); 8352 8353 bind(FALSE_LABEL); 8354 xorl(result, result); // return false 8355 8356 // That's it 8357 bind(DONE); 8358 if (UseAVX >= 2 && UseSSE >= 2) { 8359 // clean upper bits of YMM registers 8360 vpxor(vec1, vec1); 8361 vpxor(vec2, vec2); 8362 } 8363 } 8364 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings. 8365 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2, 8366 Register limit, Register result, Register chr, 8367 XMMRegister vec1, XMMRegister vec2, bool is_char) { 8368 ShortBranchVerifier sbv(this); 8369 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE; 8370 8371 int length_offset = arrayOopDesc::length_offset_in_bytes(); 8372 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE); 8373 8374 if (is_array_equ) { 8375 // Check the input args 8376 cmpptr(ary1, ary2); 8377 jcc(Assembler::equal, TRUE_LABEL); 8378 8379 // Need additional checks for arrays_equals. 8380 testptr(ary1, ary1); 8381 jcc(Assembler::zero, FALSE_LABEL); 8382 testptr(ary2, ary2); 8383 jcc(Assembler::zero, FALSE_LABEL); 8384 8385 // Check the lengths 8386 movl(limit, Address(ary1, length_offset)); 8387 cmpl(limit, Address(ary2, length_offset)); 8388 jcc(Assembler::notEqual, FALSE_LABEL); 8389 } 8390 8391 // count == 0 8392 testl(limit, limit); 8393 jcc(Assembler::zero, TRUE_LABEL); 8394 8395 if (is_array_equ) { 8396 // Load array address 8397 lea(ary1, Address(ary1, base_offset)); 8398 lea(ary2, Address(ary2, base_offset)); 8399 } 8400 8401 if (is_array_equ && is_char) { 8402 // arrays_equals when used for char[]. 8403 shll(limit, 1); // byte count != 0 8404 } 8405 movl(result, limit); // copy 8406 8407 if (UseAVX >= 2) { 8408 // With AVX2, use 32-byte vector compare 8409 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8410 8411 // Compare 32-byte vectors 8412 andl(result, 0x0000001f); // tail count (in bytes) 8413 andl(limit, 0xffffffe0); // vector count (in bytes) 8414 jcc(Assembler::zero, COMPARE_TAIL); 8415 8416 lea(ary1, Address(ary1, limit, Address::times_1)); 8417 lea(ary2, Address(ary2, limit, Address::times_1)); 8418 negptr(limit); 8419 8420 bind(COMPARE_WIDE_VECTORS); 8421 8422 #ifdef _LP64 8423 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 8424 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3; 8425 8426 cmpl(limit, -64); 8427 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2); 8428 8429 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 8430 8431 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit); 8432 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit); 8433 kortestql(k7, k7); 8434 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8435 addptr(limit, 64); // update since we already compared at this addr 8436 cmpl(limit, -64); 8437 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3); 8438 8439 // At this point we may still need to compare -limit+result bytes. 8440 // We could execute the next two instruction and just continue via non-wide path: 8441 // cmpl(limit, 0); 8442 // jcc(Assembler::equal, COMPARE_TAIL); // true 8443 // But since we stopped at the points ary{1,2}+limit which are 8444 // not farther than 64 bytes from the ends of arrays ary{1,2}+result 8445 // (|limit| <= 32 and result < 32), 8446 // we may just compare the last 64 bytes. 8447 // 8448 addptr(result, -64); // it is safe, bc we just came from this area 8449 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit); 8450 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit); 8451 kortestql(k7, k7); 8452 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8453 8454 jmp(TRUE_LABEL); 8455 8456 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8457 8458 }//if (VM_Version::supports_avx512vlbw()) 8459 #endif //_LP64 8460 8461 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 8462 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 8463 vpxor(vec1, vec2); 8464 8465 vptest(vec1, vec1); 8466 jcc(Assembler::notZero, FALSE_LABEL); 8467 addptr(limit, 32); 8468 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8469 8470 testl(result, result); 8471 jcc(Assembler::zero, TRUE_LABEL); 8472 8473 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8474 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 8475 vpxor(vec1, vec2); 8476 8477 vptest(vec1, vec1); 8478 jccb(Assembler::notZero, FALSE_LABEL); 8479 jmpb(TRUE_LABEL); 8480 8481 bind(COMPARE_TAIL); // limit is zero 8482 movl(limit, result); 8483 // Fallthru to tail compare 8484 } else if (UseSSE42Intrinsics) { 8485 // With SSE4.2, use double quad vector compare 8486 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8487 8488 // Compare 16-byte vectors 8489 andl(result, 0x0000000f); // tail count (in bytes) 8490 andl(limit, 0xfffffff0); // vector count (in bytes) 8491 jcc(Assembler::zero, COMPARE_TAIL); 8492 8493 lea(ary1, Address(ary1, limit, Address::times_1)); 8494 lea(ary2, Address(ary2, limit, Address::times_1)); 8495 negptr(limit); 8496 8497 bind(COMPARE_WIDE_VECTORS); 8498 movdqu(vec1, Address(ary1, limit, Address::times_1)); 8499 movdqu(vec2, Address(ary2, limit, Address::times_1)); 8500 pxor(vec1, vec2); 8501 8502 ptest(vec1, vec1); 8503 jcc(Assembler::notZero, FALSE_LABEL); 8504 addptr(limit, 16); 8505 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8506 8507 testl(result, result); 8508 jcc(Assembler::zero, TRUE_LABEL); 8509 8510 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8511 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 8512 pxor(vec1, vec2); 8513 8514 ptest(vec1, vec1); 8515 jccb(Assembler::notZero, FALSE_LABEL); 8516 jmpb(TRUE_LABEL); 8517 8518 bind(COMPARE_TAIL); // limit is zero 8519 movl(limit, result); 8520 // Fallthru to tail compare 8521 } 8522 8523 // Compare 4-byte vectors 8524 andl(limit, 0xfffffffc); // vector count (in bytes) 8525 jccb(Assembler::zero, COMPARE_CHAR); 8526 8527 lea(ary1, Address(ary1, limit, Address::times_1)); 8528 lea(ary2, Address(ary2, limit, Address::times_1)); 8529 negptr(limit); 8530 8531 bind(COMPARE_VECTORS); 8532 movl(chr, Address(ary1, limit, Address::times_1)); 8533 cmpl(chr, Address(ary2, limit, Address::times_1)); 8534 jccb(Assembler::notEqual, FALSE_LABEL); 8535 addptr(limit, 4); 8536 jcc(Assembler::notZero, COMPARE_VECTORS); 8537 8538 // Compare trailing char (final 2 bytes), if any 8539 bind(COMPARE_CHAR); 8540 testl(result, 0x2); // tail char 8541 jccb(Assembler::zero, COMPARE_BYTE); 8542 load_unsigned_short(chr, Address(ary1, 0)); 8543 load_unsigned_short(limit, Address(ary2, 0)); 8544 cmpl(chr, limit); 8545 jccb(Assembler::notEqual, FALSE_LABEL); 8546 8547 if (is_array_equ && is_char) { 8548 bind(COMPARE_BYTE); 8549 } else { 8550 lea(ary1, Address(ary1, 2)); 8551 lea(ary2, Address(ary2, 2)); 8552 8553 bind(COMPARE_BYTE); 8554 testl(result, 0x1); // tail byte 8555 jccb(Assembler::zero, TRUE_LABEL); 8556 load_unsigned_byte(chr, Address(ary1, 0)); 8557 load_unsigned_byte(limit, Address(ary2, 0)); 8558 cmpl(chr, limit); 8559 jccb(Assembler::notEqual, FALSE_LABEL); 8560 } 8561 bind(TRUE_LABEL); 8562 movl(result, 1); // return true 8563 jmpb(DONE); 8564 8565 bind(FALSE_LABEL); 8566 xorl(result, result); // return false 8567 8568 // That's it 8569 bind(DONE); 8570 if (UseAVX >= 2) { 8571 // clean upper bits of YMM registers 8572 vpxor(vec1, vec1); 8573 vpxor(vec2, vec2); 8574 } 8575 } 8576 8577 #endif 8578 8579 void MacroAssembler::generate_fill(BasicType t, bool aligned, 8580 Register to, Register value, Register count, 8581 Register rtmp, XMMRegister xtmp) { 8582 ShortBranchVerifier sbv(this); 8583 assert_different_registers(to, value, count, rtmp); 8584 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 8585 Label L_fill_2_bytes, L_fill_4_bytes; 8586 8587 int shift = -1; 8588 switch (t) { 8589 case T_BYTE: 8590 shift = 2; 8591 break; 8592 case T_SHORT: 8593 shift = 1; 8594 break; 8595 case T_INT: 8596 shift = 0; 8597 break; 8598 default: ShouldNotReachHere(); 8599 } 8600 8601 if (t == T_BYTE) { 8602 andl(value, 0xff); 8603 movl(rtmp, value); 8604 shll(rtmp, 8); 8605 orl(value, rtmp); 8606 } 8607 if (t == T_SHORT) { 8608 andl(value, 0xffff); 8609 } 8610 if (t == T_BYTE || t == T_SHORT) { 8611 movl(rtmp, value); 8612 shll(rtmp, 16); 8613 orl(value, rtmp); 8614 } 8615 8616 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 8617 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 8618 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 8619 // align source address at 4 bytes address boundary 8620 if (t == T_BYTE) { 8621 // One byte misalignment happens only for byte arrays 8622 testptr(to, 1); 8623 jccb(Assembler::zero, L_skip_align1); 8624 movb(Address(to, 0), value); 8625 increment(to); 8626 decrement(count); 8627 BIND(L_skip_align1); 8628 } 8629 // Two bytes misalignment happens only for byte and short (char) arrays 8630 testptr(to, 2); 8631 jccb(Assembler::zero, L_skip_align2); 8632 movw(Address(to, 0), value); 8633 addptr(to, 2); 8634 subl(count, 1<<(shift-1)); 8635 BIND(L_skip_align2); 8636 } 8637 if (UseSSE < 2) { 8638 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8639 // Fill 32-byte chunks 8640 subl(count, 8 << shift); 8641 jcc(Assembler::less, L_check_fill_8_bytes); 8642 align(16); 8643 8644 BIND(L_fill_32_bytes_loop); 8645 8646 for (int i = 0; i < 32; i += 4) { 8647 movl(Address(to, i), value); 8648 } 8649 8650 addptr(to, 32); 8651 subl(count, 8 << shift); 8652 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8653 BIND(L_check_fill_8_bytes); 8654 addl(count, 8 << shift); 8655 jccb(Assembler::zero, L_exit); 8656 jmpb(L_fill_8_bytes); 8657 8658 // 8659 // length is too short, just fill qwords 8660 // 8661 BIND(L_fill_8_bytes_loop); 8662 movl(Address(to, 0), value); 8663 movl(Address(to, 4), value); 8664 addptr(to, 8); 8665 BIND(L_fill_8_bytes); 8666 subl(count, 1 << (shift + 1)); 8667 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8668 // fall through to fill 4 bytes 8669 } else { 8670 Label L_fill_32_bytes; 8671 if (!UseUnalignedLoadStores) { 8672 // align to 8 bytes, we know we are 4 byte aligned to start 8673 testptr(to, 4); 8674 jccb(Assembler::zero, L_fill_32_bytes); 8675 movl(Address(to, 0), value); 8676 addptr(to, 4); 8677 subl(count, 1<<shift); 8678 } 8679 BIND(L_fill_32_bytes); 8680 { 8681 assert( UseSSE >= 2, "supported cpu only" ); 8682 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8683 if (UseAVX > 2) { 8684 movl(rtmp, 0xffff); 8685 kmovwl(k1, rtmp); 8686 } 8687 movdl(xtmp, value); 8688 if (UseAVX > 2 && UseUnalignedLoadStores) { 8689 // Fill 64-byte chunks 8690 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8691 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 8692 8693 subl(count, 16 << shift); 8694 jcc(Assembler::less, L_check_fill_32_bytes); 8695 align(16); 8696 8697 BIND(L_fill_64_bytes_loop); 8698 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 8699 addptr(to, 64); 8700 subl(count, 16 << shift); 8701 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8702 8703 BIND(L_check_fill_32_bytes); 8704 addl(count, 8 << shift); 8705 jccb(Assembler::less, L_check_fill_8_bytes); 8706 vmovdqu(Address(to, 0), xtmp); 8707 addptr(to, 32); 8708 subl(count, 8 << shift); 8709 8710 BIND(L_check_fill_8_bytes); 8711 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 8712 // Fill 64-byte chunks 8713 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8714 vpbroadcastd(xtmp, xtmp); 8715 8716 subl(count, 16 << shift); 8717 jcc(Assembler::less, L_check_fill_32_bytes); 8718 align(16); 8719 8720 BIND(L_fill_64_bytes_loop); 8721 vmovdqu(Address(to, 0), xtmp); 8722 vmovdqu(Address(to, 32), xtmp); 8723 addptr(to, 64); 8724 subl(count, 16 << shift); 8725 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8726 8727 BIND(L_check_fill_32_bytes); 8728 addl(count, 8 << shift); 8729 jccb(Assembler::less, L_check_fill_8_bytes); 8730 vmovdqu(Address(to, 0), xtmp); 8731 addptr(to, 32); 8732 subl(count, 8 << shift); 8733 8734 BIND(L_check_fill_8_bytes); 8735 // clean upper bits of YMM registers 8736 movdl(xtmp, value); 8737 pshufd(xtmp, xtmp, 0); 8738 } else { 8739 // Fill 32-byte chunks 8740 pshufd(xtmp, xtmp, 0); 8741 8742 subl(count, 8 << shift); 8743 jcc(Assembler::less, L_check_fill_8_bytes); 8744 align(16); 8745 8746 BIND(L_fill_32_bytes_loop); 8747 8748 if (UseUnalignedLoadStores) { 8749 movdqu(Address(to, 0), xtmp); 8750 movdqu(Address(to, 16), xtmp); 8751 } else { 8752 movq(Address(to, 0), xtmp); 8753 movq(Address(to, 8), xtmp); 8754 movq(Address(to, 16), xtmp); 8755 movq(Address(to, 24), xtmp); 8756 } 8757 8758 addptr(to, 32); 8759 subl(count, 8 << shift); 8760 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8761 8762 BIND(L_check_fill_8_bytes); 8763 } 8764 addl(count, 8 << shift); 8765 jccb(Assembler::zero, L_exit); 8766 jmpb(L_fill_8_bytes); 8767 8768 // 8769 // length is too short, just fill qwords 8770 // 8771 BIND(L_fill_8_bytes_loop); 8772 movq(Address(to, 0), xtmp); 8773 addptr(to, 8); 8774 BIND(L_fill_8_bytes); 8775 subl(count, 1 << (shift + 1)); 8776 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8777 } 8778 } 8779 // fill trailing 4 bytes 8780 BIND(L_fill_4_bytes); 8781 testl(count, 1<<shift); 8782 jccb(Assembler::zero, L_fill_2_bytes); 8783 movl(Address(to, 0), value); 8784 if (t == T_BYTE || t == T_SHORT) { 8785 addptr(to, 4); 8786 BIND(L_fill_2_bytes); 8787 // fill trailing 2 bytes 8788 testl(count, 1<<(shift-1)); 8789 jccb(Assembler::zero, L_fill_byte); 8790 movw(Address(to, 0), value); 8791 if (t == T_BYTE) { 8792 addptr(to, 2); 8793 BIND(L_fill_byte); 8794 // fill trailing byte 8795 testl(count, 1); 8796 jccb(Assembler::zero, L_exit); 8797 movb(Address(to, 0), value); 8798 } else { 8799 BIND(L_fill_byte); 8800 } 8801 } else { 8802 BIND(L_fill_2_bytes); 8803 } 8804 BIND(L_exit); 8805 } 8806 8807 // encode char[] to byte[] in ISO_8859_1 8808 //@HotSpotIntrinsicCandidate 8809 //private static int implEncodeISOArray(byte[] sa, int sp, 8810 //byte[] da, int dp, int len) { 8811 // int i = 0; 8812 // for (; i < len; i++) { 8813 // char c = StringUTF16.getChar(sa, sp++); 8814 // if (c > '\u00FF') 8815 // break; 8816 // da[dp++] = (byte)c; 8817 // } 8818 // return i; 8819 //} 8820 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 8821 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 8822 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 8823 Register tmp5, Register result) { 8824 8825 // rsi: src 8826 // rdi: dst 8827 // rdx: len 8828 // rcx: tmp5 8829 // rax: result 8830 ShortBranchVerifier sbv(this); 8831 assert_different_registers(src, dst, len, tmp5, result); 8832 Label L_done, L_copy_1_char, L_copy_1_char_exit; 8833 8834 // set result 8835 xorl(result, result); 8836 // check for zero length 8837 testl(len, len); 8838 jcc(Assembler::zero, L_done); 8839 8840 movl(result, len); 8841 8842 // Setup pointers 8843 lea(src, Address(src, len, Address::times_2)); // char[] 8844 lea(dst, Address(dst, len, Address::times_1)); // byte[] 8845 negptr(len); 8846 8847 if (UseSSE42Intrinsics || UseAVX >= 2) { 8848 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 8849 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 8850 8851 if (UseAVX >= 2) { 8852 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 8853 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8854 movdl(tmp1Reg, tmp5); 8855 vpbroadcastd(tmp1Reg, tmp1Reg); 8856 jmp(L_chars_32_check); 8857 8858 bind(L_copy_32_chars); 8859 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 8860 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 8861 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8862 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8863 jccb(Assembler::notZero, L_copy_32_chars_exit); 8864 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8865 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 8866 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 8867 8868 bind(L_chars_32_check); 8869 addptr(len, 32); 8870 jcc(Assembler::lessEqual, L_copy_32_chars); 8871 8872 bind(L_copy_32_chars_exit); 8873 subptr(len, 16); 8874 jccb(Assembler::greater, L_copy_16_chars_exit); 8875 8876 } else if (UseSSE42Intrinsics) { 8877 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8878 movdl(tmp1Reg, tmp5); 8879 pshufd(tmp1Reg, tmp1Reg, 0); 8880 jmpb(L_chars_16_check); 8881 } 8882 8883 bind(L_copy_16_chars); 8884 if (UseAVX >= 2) { 8885 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 8886 vptest(tmp2Reg, tmp1Reg); 8887 jcc(Assembler::notZero, L_copy_16_chars_exit); 8888 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 8889 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 8890 } else { 8891 if (UseAVX > 0) { 8892 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8893 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8894 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 8895 } else { 8896 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8897 por(tmp2Reg, tmp3Reg); 8898 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8899 por(tmp2Reg, tmp4Reg); 8900 } 8901 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8902 jccb(Assembler::notZero, L_copy_16_chars_exit); 8903 packuswb(tmp3Reg, tmp4Reg); 8904 } 8905 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 8906 8907 bind(L_chars_16_check); 8908 addptr(len, 16); 8909 jcc(Assembler::lessEqual, L_copy_16_chars); 8910 8911 bind(L_copy_16_chars_exit); 8912 if (UseAVX >= 2) { 8913 // clean upper bits of YMM registers 8914 vpxor(tmp2Reg, tmp2Reg); 8915 vpxor(tmp3Reg, tmp3Reg); 8916 vpxor(tmp4Reg, tmp4Reg); 8917 movdl(tmp1Reg, tmp5); 8918 pshufd(tmp1Reg, tmp1Reg, 0); 8919 } 8920 subptr(len, 8); 8921 jccb(Assembler::greater, L_copy_8_chars_exit); 8922 8923 bind(L_copy_8_chars); 8924 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 8925 ptest(tmp3Reg, tmp1Reg); 8926 jccb(Assembler::notZero, L_copy_8_chars_exit); 8927 packuswb(tmp3Reg, tmp1Reg); 8928 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 8929 addptr(len, 8); 8930 jccb(Assembler::lessEqual, L_copy_8_chars); 8931 8932 bind(L_copy_8_chars_exit); 8933 subptr(len, 8); 8934 jccb(Assembler::zero, L_done); 8935 } 8936 8937 bind(L_copy_1_char); 8938 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 8939 testl(tmp5, 0xff00); // check if Unicode char 8940 jccb(Assembler::notZero, L_copy_1_char_exit); 8941 movb(Address(dst, len, Address::times_1, 0), tmp5); 8942 addptr(len, 1); 8943 jccb(Assembler::less, L_copy_1_char); 8944 8945 bind(L_copy_1_char_exit); 8946 addptr(result, len); // len is negative count of not processed elements 8947 8948 bind(L_done); 8949 } 8950 8951 #ifdef _LP64 8952 /** 8953 * Helper for multiply_to_len(). 8954 */ 8955 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 8956 addq(dest_lo, src1); 8957 adcq(dest_hi, 0); 8958 addq(dest_lo, src2); 8959 adcq(dest_hi, 0); 8960 } 8961 8962 /** 8963 * Multiply 64 bit by 64 bit first loop. 8964 */ 8965 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 8966 Register y, Register y_idx, Register z, 8967 Register carry, Register product, 8968 Register idx, Register kdx) { 8969 // 8970 // jlong carry, x[], y[], z[]; 8971 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 8972 // huge_128 product = y[idx] * x[xstart] + carry; 8973 // z[kdx] = (jlong)product; 8974 // carry = (jlong)(product >>> 64); 8975 // } 8976 // z[xstart] = carry; 8977 // 8978 8979 Label L_first_loop, L_first_loop_exit; 8980 Label L_one_x, L_one_y, L_multiply; 8981 8982 decrementl(xstart); 8983 jcc(Assembler::negative, L_one_x); 8984 8985 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 8986 rorq(x_xstart, 32); // convert big-endian to little-endian 8987 8988 bind(L_first_loop); 8989 decrementl(idx); 8990 jcc(Assembler::negative, L_first_loop_exit); 8991 decrementl(idx); 8992 jcc(Assembler::negative, L_one_y); 8993 movq(y_idx, Address(y, idx, Address::times_4, 0)); 8994 rorq(y_idx, 32); // convert big-endian to little-endian 8995 bind(L_multiply); 8996 movq(product, x_xstart); 8997 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 8998 addq(product, carry); 8999 adcq(rdx, 0); 9000 subl(kdx, 2); 9001 movl(Address(z, kdx, Address::times_4, 4), product); 9002 shrq(product, 32); 9003 movl(Address(z, kdx, Address::times_4, 0), product); 9004 movq(carry, rdx); 9005 jmp(L_first_loop); 9006 9007 bind(L_one_y); 9008 movl(y_idx, Address(y, 0)); 9009 jmp(L_multiply); 9010 9011 bind(L_one_x); 9012 movl(x_xstart, Address(x, 0)); 9013 jmp(L_first_loop); 9014 9015 bind(L_first_loop_exit); 9016 } 9017 9018 /** 9019 * Multiply 64 bit by 64 bit and add 128 bit. 9020 */ 9021 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 9022 Register yz_idx, Register idx, 9023 Register carry, Register product, int offset) { 9024 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 9025 // z[kdx] = (jlong)product; 9026 9027 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 9028 rorq(yz_idx, 32); // convert big-endian to little-endian 9029 movq(product, x_xstart); 9030 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9031 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 9032 rorq(yz_idx, 32); // convert big-endian to little-endian 9033 9034 add2_with_carry(rdx, product, carry, yz_idx); 9035 9036 movl(Address(z, idx, Address::times_4, offset+4), product); 9037 shrq(product, 32); 9038 movl(Address(z, idx, Address::times_4, offset), product); 9039 9040 } 9041 9042 /** 9043 * Multiply 128 bit by 128 bit. Unrolled inner loop. 9044 */ 9045 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 9046 Register yz_idx, Register idx, Register jdx, 9047 Register carry, Register product, 9048 Register carry2) { 9049 // jlong carry, x[], y[], z[]; 9050 // int kdx = ystart+1; 9051 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9052 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 9053 // z[kdx+idx+1] = (jlong)product; 9054 // jlong carry2 = (jlong)(product >>> 64); 9055 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 9056 // z[kdx+idx] = (jlong)product; 9057 // carry = (jlong)(product >>> 64); 9058 // } 9059 // idx += 2; 9060 // if (idx > 0) { 9061 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 9062 // z[kdx+idx] = (jlong)product; 9063 // carry = (jlong)(product >>> 64); 9064 // } 9065 // 9066 9067 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9068 9069 movl(jdx, idx); 9070 andl(jdx, 0xFFFFFFFC); 9071 shrl(jdx, 2); 9072 9073 bind(L_third_loop); 9074 subl(jdx, 1); 9075 jcc(Assembler::negative, L_third_loop_exit); 9076 subl(idx, 4); 9077 9078 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 9079 movq(carry2, rdx); 9080 9081 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 9082 movq(carry, rdx); 9083 jmp(L_third_loop); 9084 9085 bind (L_third_loop_exit); 9086 9087 andl (idx, 0x3); 9088 jcc(Assembler::zero, L_post_third_loop_done); 9089 9090 Label L_check_1; 9091 subl(idx, 2); 9092 jcc(Assembler::negative, L_check_1); 9093 9094 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 9095 movq(carry, rdx); 9096 9097 bind (L_check_1); 9098 addl (idx, 0x2); 9099 andl (idx, 0x1); 9100 subl(idx, 1); 9101 jcc(Assembler::negative, L_post_third_loop_done); 9102 9103 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 9104 movq(product, x_xstart); 9105 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9106 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 9107 9108 add2_with_carry(rdx, product, yz_idx, carry); 9109 9110 movl(Address(z, idx, Address::times_4, 0), product); 9111 shrq(product, 32); 9112 9113 shlq(rdx, 32); 9114 orq(product, rdx); 9115 movq(carry, product); 9116 9117 bind(L_post_third_loop_done); 9118 } 9119 9120 /** 9121 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 9122 * 9123 */ 9124 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 9125 Register carry, Register carry2, 9126 Register idx, Register jdx, 9127 Register yz_idx1, Register yz_idx2, 9128 Register tmp, Register tmp3, Register tmp4) { 9129 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 9130 9131 // jlong carry, x[], y[], z[]; 9132 // int kdx = ystart+1; 9133 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9134 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 9135 // jlong carry2 = (jlong)(tmp3 >>> 64); 9136 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 9137 // carry = (jlong)(tmp4 >>> 64); 9138 // z[kdx+idx+1] = (jlong)tmp3; 9139 // z[kdx+idx] = (jlong)tmp4; 9140 // } 9141 // idx += 2; 9142 // if (idx > 0) { 9143 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 9144 // z[kdx+idx] = (jlong)yz_idx1; 9145 // carry = (jlong)(yz_idx1 >>> 64); 9146 // } 9147 // 9148 9149 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9150 9151 movl(jdx, idx); 9152 andl(jdx, 0xFFFFFFFC); 9153 shrl(jdx, 2); 9154 9155 bind(L_third_loop); 9156 subl(jdx, 1); 9157 jcc(Assembler::negative, L_third_loop_exit); 9158 subl(idx, 4); 9159 9160 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 9161 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 9162 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 9163 rorxq(yz_idx2, yz_idx2, 32); 9164 9165 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9166 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 9167 9168 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 9169 rorxq(yz_idx1, yz_idx1, 32); 9170 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9171 rorxq(yz_idx2, yz_idx2, 32); 9172 9173 if (VM_Version::supports_adx()) { 9174 adcxq(tmp3, carry); 9175 adoxq(tmp3, yz_idx1); 9176 9177 adcxq(tmp4, tmp); 9178 adoxq(tmp4, yz_idx2); 9179 9180 movl(carry, 0); // does not affect flags 9181 adcxq(carry2, carry); 9182 adoxq(carry2, carry); 9183 } else { 9184 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 9185 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 9186 } 9187 movq(carry, carry2); 9188 9189 movl(Address(z, idx, Address::times_4, 12), tmp3); 9190 shrq(tmp3, 32); 9191 movl(Address(z, idx, Address::times_4, 8), tmp3); 9192 9193 movl(Address(z, idx, Address::times_4, 4), tmp4); 9194 shrq(tmp4, 32); 9195 movl(Address(z, idx, Address::times_4, 0), tmp4); 9196 9197 jmp(L_third_loop); 9198 9199 bind (L_third_loop_exit); 9200 9201 andl (idx, 0x3); 9202 jcc(Assembler::zero, L_post_third_loop_done); 9203 9204 Label L_check_1; 9205 subl(idx, 2); 9206 jcc(Assembler::negative, L_check_1); 9207 9208 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 9209 rorxq(yz_idx1, yz_idx1, 32); 9210 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9211 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9212 rorxq(yz_idx2, yz_idx2, 32); 9213 9214 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 9215 9216 movl(Address(z, idx, Address::times_4, 4), tmp3); 9217 shrq(tmp3, 32); 9218 movl(Address(z, idx, Address::times_4, 0), tmp3); 9219 movq(carry, tmp4); 9220 9221 bind (L_check_1); 9222 addl (idx, 0x2); 9223 andl (idx, 0x1); 9224 subl(idx, 1); 9225 jcc(Assembler::negative, L_post_third_loop_done); 9226 movl(tmp4, Address(y, idx, Address::times_4, 0)); 9227 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 9228 movl(tmp4, Address(z, idx, Address::times_4, 0)); 9229 9230 add2_with_carry(carry2, tmp3, tmp4, carry); 9231 9232 movl(Address(z, idx, Address::times_4, 0), tmp3); 9233 shrq(tmp3, 32); 9234 9235 shlq(carry2, 32); 9236 orq(tmp3, carry2); 9237 movq(carry, tmp3); 9238 9239 bind(L_post_third_loop_done); 9240 } 9241 9242 /** 9243 * Code for BigInteger::multiplyToLen() instrinsic. 9244 * 9245 * rdi: x 9246 * rax: xlen 9247 * rsi: y 9248 * rcx: ylen 9249 * r8: z 9250 * r11: zlen 9251 * r12: tmp1 9252 * r13: tmp2 9253 * r14: tmp3 9254 * r15: tmp4 9255 * rbx: tmp5 9256 * 9257 */ 9258 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 9259 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 9260 ShortBranchVerifier sbv(this); 9261 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 9262 9263 push(tmp1); 9264 push(tmp2); 9265 push(tmp3); 9266 push(tmp4); 9267 push(tmp5); 9268 9269 push(xlen); 9270 push(zlen); 9271 9272 const Register idx = tmp1; 9273 const Register kdx = tmp2; 9274 const Register xstart = tmp3; 9275 9276 const Register y_idx = tmp4; 9277 const Register carry = tmp5; 9278 const Register product = xlen; 9279 const Register x_xstart = zlen; // reuse register 9280 9281 // First Loop. 9282 // 9283 // final static long LONG_MASK = 0xffffffffL; 9284 // int xstart = xlen - 1; 9285 // int ystart = ylen - 1; 9286 // long carry = 0; 9287 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 9288 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 9289 // z[kdx] = (int)product; 9290 // carry = product >>> 32; 9291 // } 9292 // z[xstart] = (int)carry; 9293 // 9294 9295 movl(idx, ylen); // idx = ylen; 9296 movl(kdx, zlen); // kdx = xlen+ylen; 9297 xorq(carry, carry); // carry = 0; 9298 9299 Label L_done; 9300 9301 movl(xstart, xlen); 9302 decrementl(xstart); 9303 jcc(Assembler::negative, L_done); 9304 9305 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 9306 9307 Label L_second_loop; 9308 testl(kdx, kdx); 9309 jcc(Assembler::zero, L_second_loop); 9310 9311 Label L_carry; 9312 subl(kdx, 1); 9313 jcc(Assembler::zero, L_carry); 9314 9315 movl(Address(z, kdx, Address::times_4, 0), carry); 9316 shrq(carry, 32); 9317 subl(kdx, 1); 9318 9319 bind(L_carry); 9320 movl(Address(z, kdx, Address::times_4, 0), carry); 9321 9322 // Second and third (nested) loops. 9323 // 9324 // for (int i = xstart-1; i >= 0; i--) { // Second loop 9325 // carry = 0; 9326 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 9327 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 9328 // (z[k] & LONG_MASK) + carry; 9329 // z[k] = (int)product; 9330 // carry = product >>> 32; 9331 // } 9332 // z[i] = (int)carry; 9333 // } 9334 // 9335 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 9336 9337 const Register jdx = tmp1; 9338 9339 bind(L_second_loop); 9340 xorl(carry, carry); // carry = 0; 9341 movl(jdx, ylen); // j = ystart+1 9342 9343 subl(xstart, 1); // i = xstart-1; 9344 jcc(Assembler::negative, L_done); 9345 9346 push (z); 9347 9348 Label L_last_x; 9349 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 9350 subl(xstart, 1); // i = xstart-1; 9351 jcc(Assembler::negative, L_last_x); 9352 9353 if (UseBMI2Instructions) { 9354 movq(rdx, Address(x, xstart, Address::times_4, 0)); 9355 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 9356 } else { 9357 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 9358 rorq(x_xstart, 32); // convert big-endian to little-endian 9359 } 9360 9361 Label L_third_loop_prologue; 9362 bind(L_third_loop_prologue); 9363 9364 push (x); 9365 push (xstart); 9366 push (ylen); 9367 9368 9369 if (UseBMI2Instructions) { 9370 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 9371 } else { // !UseBMI2Instructions 9372 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 9373 } 9374 9375 pop(ylen); 9376 pop(xlen); 9377 pop(x); 9378 pop(z); 9379 9380 movl(tmp3, xlen); 9381 addl(tmp3, 1); 9382 movl(Address(z, tmp3, Address::times_4, 0), carry); 9383 subl(tmp3, 1); 9384 jccb(Assembler::negative, L_done); 9385 9386 shrq(carry, 32); 9387 movl(Address(z, tmp3, Address::times_4, 0), carry); 9388 jmp(L_second_loop); 9389 9390 // Next infrequent code is moved outside loops. 9391 bind(L_last_x); 9392 if (UseBMI2Instructions) { 9393 movl(rdx, Address(x, 0)); 9394 } else { 9395 movl(x_xstart, Address(x, 0)); 9396 } 9397 jmp(L_third_loop_prologue); 9398 9399 bind(L_done); 9400 9401 pop(zlen); 9402 pop(xlen); 9403 9404 pop(tmp5); 9405 pop(tmp4); 9406 pop(tmp3); 9407 pop(tmp2); 9408 pop(tmp1); 9409 } 9410 9411 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 9412 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 9413 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 9414 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL; 9415 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 9416 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL; 9417 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 9418 Label SAME_TILL_END, DONE; 9419 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 9420 9421 //scale is in rcx in both Win64 and Unix 9422 ShortBranchVerifier sbv(this); 9423 9424 shlq(length); 9425 xorq(result, result); 9426 9427 if ((UseAVX > 2) && 9428 VM_Version::supports_avx512vlbw()) { 9429 set_vector_masking(); // opening of the stub context for programming mask registers 9430 cmpq(length, 64); 9431 jcc(Assembler::less, VECTOR32_TAIL); 9432 movq(tmp1, length); 9433 andq(tmp1, 0x3F); // tail count 9434 andq(length, ~(0x3F)); //vector count 9435 9436 bind(VECTOR64_LOOP); 9437 // AVX512 code to compare 64 byte vectors. 9438 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit); 9439 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit); 9440 kortestql(k7, k7); 9441 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch 9442 addq(result, 64); 9443 subq(length, 64); 9444 jccb(Assembler::notZero, VECTOR64_LOOP); 9445 9446 //bind(VECTOR64_TAIL); 9447 testq(tmp1, tmp1); 9448 jcc(Assembler::zero, SAME_TILL_END); 9449 9450 bind(VECTOR64_TAIL); 9451 // AVX512 code to compare upto 63 byte vectors. 9452 // Save k1 9453 kmovql(k3, k1); 9454 mov64(tmp2, 0xFFFFFFFFFFFFFFFF); 9455 shlxq(tmp2, tmp2, tmp1); 9456 notq(tmp2); 9457 kmovql(k1, tmp2); 9458 9459 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit); 9460 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit); 9461 9462 ktestql(k7, k1); 9463 // Restore k1 9464 kmovql(k1, k3); 9465 jcc(Assembler::below, SAME_TILL_END); // not mismatch 9466 9467 bind(VECTOR64_NOT_EQUAL); 9468 kmovql(tmp1, k7); 9469 notq(tmp1); 9470 tzcntq(tmp1, tmp1); 9471 addq(result, tmp1); 9472 shrq(result); 9473 jmp(DONE); 9474 bind(VECTOR32_TAIL); 9475 clear_vector_masking(); // closing of the stub context for programming mask registers 9476 } 9477 9478 cmpq(length, 8); 9479 jcc(Assembler::equal, VECTOR8_LOOP); 9480 jcc(Assembler::less, VECTOR4_TAIL); 9481 9482 if (UseAVX >= 2) { 9483 9484 cmpq(length, 16); 9485 jcc(Assembler::equal, VECTOR16_LOOP); 9486 jcc(Assembler::less, VECTOR8_LOOP); 9487 9488 cmpq(length, 32); 9489 jccb(Assembler::less, VECTOR16_TAIL); 9490 9491 subq(length, 32); 9492 bind(VECTOR32_LOOP); 9493 vmovdqu(rymm0, Address(obja, result)); 9494 vmovdqu(rymm1, Address(objb, result)); 9495 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 9496 vptest(rymm2, rymm2); 9497 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 9498 addq(result, 32); 9499 subq(length, 32); 9500 jccb(Assembler::greaterEqual, VECTOR32_LOOP); 9501 addq(length, 32); 9502 jcc(Assembler::equal, SAME_TILL_END); 9503 //falling through if less than 32 bytes left //close the branch here. 9504 9505 bind(VECTOR16_TAIL); 9506 cmpq(length, 16); 9507 jccb(Assembler::less, VECTOR8_TAIL); 9508 bind(VECTOR16_LOOP); 9509 movdqu(rymm0, Address(obja, result)); 9510 movdqu(rymm1, Address(objb, result)); 9511 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 9512 ptest(rymm2, rymm2); 9513 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9514 addq(result, 16); 9515 subq(length, 16); 9516 jcc(Assembler::equal, SAME_TILL_END); 9517 //falling through if less than 16 bytes left 9518 } else {//regular intrinsics 9519 9520 cmpq(length, 16); 9521 jccb(Assembler::less, VECTOR8_TAIL); 9522 9523 subq(length, 16); 9524 bind(VECTOR16_LOOP); 9525 movdqu(rymm0, Address(obja, result)); 9526 movdqu(rymm1, Address(objb, result)); 9527 pxor(rymm0, rymm1); 9528 ptest(rymm0, rymm0); 9529 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9530 addq(result, 16); 9531 subq(length, 16); 9532 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 9533 addq(length, 16); 9534 jcc(Assembler::equal, SAME_TILL_END); 9535 //falling through if less than 16 bytes left 9536 } 9537 9538 bind(VECTOR8_TAIL); 9539 cmpq(length, 8); 9540 jccb(Assembler::less, VECTOR4_TAIL); 9541 bind(VECTOR8_LOOP); 9542 movq(tmp1, Address(obja, result)); 9543 movq(tmp2, Address(objb, result)); 9544 xorq(tmp1, tmp2); 9545 testq(tmp1, tmp1); 9546 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 9547 addq(result, 8); 9548 subq(length, 8); 9549 jcc(Assembler::equal, SAME_TILL_END); 9550 //falling through if less than 8 bytes left 9551 9552 bind(VECTOR4_TAIL); 9553 cmpq(length, 4); 9554 jccb(Assembler::less, BYTES_TAIL); 9555 bind(VECTOR4_LOOP); 9556 movl(tmp1, Address(obja, result)); 9557 xorl(tmp1, Address(objb, result)); 9558 testl(tmp1, tmp1); 9559 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 9560 addq(result, 4); 9561 subq(length, 4); 9562 jcc(Assembler::equal, SAME_TILL_END); 9563 //falling through if less than 4 bytes left 9564 9565 bind(BYTES_TAIL); 9566 bind(BYTES_LOOP); 9567 load_unsigned_byte(tmp1, Address(obja, result)); 9568 load_unsigned_byte(tmp2, Address(objb, result)); 9569 xorl(tmp1, tmp2); 9570 testl(tmp1, tmp1); 9571 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9572 decq(length); 9573 jccb(Assembler::zero, SAME_TILL_END); 9574 incq(result); 9575 load_unsigned_byte(tmp1, Address(obja, result)); 9576 load_unsigned_byte(tmp2, Address(objb, result)); 9577 xorl(tmp1, tmp2); 9578 testl(tmp1, tmp1); 9579 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9580 decq(length); 9581 jccb(Assembler::zero, SAME_TILL_END); 9582 incq(result); 9583 load_unsigned_byte(tmp1, Address(obja, result)); 9584 load_unsigned_byte(tmp2, Address(objb, result)); 9585 xorl(tmp1, tmp2); 9586 testl(tmp1, tmp1); 9587 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9588 jmpb(SAME_TILL_END); 9589 9590 if (UseAVX >= 2) { 9591 bind(VECTOR32_NOT_EQUAL); 9592 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 9593 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 9594 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 9595 vpmovmskb(tmp1, rymm0); 9596 bsfq(tmp1, tmp1); 9597 addq(result, tmp1); 9598 shrq(result); 9599 jmpb(DONE); 9600 } 9601 9602 bind(VECTOR16_NOT_EQUAL); 9603 if (UseAVX >= 2) { 9604 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 9605 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 9606 pxor(rymm0, rymm2); 9607 } else { 9608 pcmpeqb(rymm2, rymm2); 9609 pxor(rymm0, rymm1); 9610 pcmpeqb(rymm0, rymm1); 9611 pxor(rymm0, rymm2); 9612 } 9613 pmovmskb(tmp1, rymm0); 9614 bsfq(tmp1, tmp1); 9615 addq(result, tmp1); 9616 shrq(result); 9617 jmpb(DONE); 9618 9619 bind(VECTOR8_NOT_EQUAL); 9620 bind(VECTOR4_NOT_EQUAL); 9621 bsfq(tmp1, tmp1); 9622 shrq(tmp1, 3); 9623 addq(result, tmp1); 9624 bind(BYTES_NOT_EQUAL); 9625 shrq(result); 9626 jmpb(DONE); 9627 9628 bind(SAME_TILL_END); 9629 mov64(result, -1); 9630 9631 bind(DONE); 9632 } 9633 9634 //Helper functions for square_to_len() 9635 9636 /** 9637 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 9638 * Preserves x and z and modifies rest of the registers. 9639 */ 9640 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9641 // Perform square and right shift by 1 9642 // Handle odd xlen case first, then for even xlen do the following 9643 // jlong carry = 0; 9644 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 9645 // huge_128 product = x[j:j+1] * x[j:j+1]; 9646 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 9647 // z[i+2:i+3] = (jlong)(product >>> 1); 9648 // carry = (jlong)product; 9649 // } 9650 9651 xorq(tmp5, tmp5); // carry 9652 xorq(rdxReg, rdxReg); 9653 xorl(tmp1, tmp1); // index for x 9654 xorl(tmp4, tmp4); // index for z 9655 9656 Label L_first_loop, L_first_loop_exit; 9657 9658 testl(xlen, 1); 9659 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 9660 9661 // Square and right shift by 1 the odd element using 32 bit multiply 9662 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 9663 imulq(raxReg, raxReg); 9664 shrq(raxReg, 1); 9665 adcq(tmp5, 0); 9666 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 9667 incrementl(tmp1); 9668 addl(tmp4, 2); 9669 9670 // Square and right shift by 1 the rest using 64 bit multiply 9671 bind(L_first_loop); 9672 cmpptr(tmp1, xlen); 9673 jccb(Assembler::equal, L_first_loop_exit); 9674 9675 // Square 9676 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 9677 rorq(raxReg, 32); // convert big-endian to little-endian 9678 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 9679 9680 // Right shift by 1 and save carry 9681 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 9682 rcrq(rdxReg, 1); 9683 rcrq(raxReg, 1); 9684 adcq(tmp5, 0); 9685 9686 // Store result in z 9687 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 9688 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 9689 9690 // Update indices for x and z 9691 addl(tmp1, 2); 9692 addl(tmp4, 4); 9693 jmp(L_first_loop); 9694 9695 bind(L_first_loop_exit); 9696 } 9697 9698 9699 /** 9700 * Perform the following multiply add operation using BMI2 instructions 9701 * carry:sum = sum + op1*op2 + carry 9702 * op2 should be in rdx 9703 * op2 is preserved, all other registers are modified 9704 */ 9705 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 9706 // assert op2 is rdx 9707 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 9708 addq(sum, carry); 9709 adcq(tmp2, 0); 9710 addq(sum, op1); 9711 adcq(tmp2, 0); 9712 movq(carry, tmp2); 9713 } 9714 9715 /** 9716 * Perform the following multiply add operation: 9717 * carry:sum = sum + op1*op2 + carry 9718 * Preserves op1, op2 and modifies rest of registers 9719 */ 9720 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 9721 // rdx:rax = op1 * op2 9722 movq(raxReg, op2); 9723 mulq(op1); 9724 9725 // rdx:rax = sum + carry + rdx:rax 9726 addq(sum, carry); 9727 adcq(rdxReg, 0); 9728 addq(sum, raxReg); 9729 adcq(rdxReg, 0); 9730 9731 // carry:sum = rdx:sum 9732 movq(carry, rdxReg); 9733 } 9734 9735 /** 9736 * Add 64 bit long carry into z[] with carry propogation. 9737 * Preserves z and carry register values and modifies rest of registers. 9738 * 9739 */ 9740 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 9741 Label L_fourth_loop, L_fourth_loop_exit; 9742 9743 movl(tmp1, 1); 9744 subl(zlen, 2); 9745 addq(Address(z, zlen, Address::times_4, 0), carry); 9746 9747 bind(L_fourth_loop); 9748 jccb(Assembler::carryClear, L_fourth_loop_exit); 9749 subl(zlen, 2); 9750 jccb(Assembler::negative, L_fourth_loop_exit); 9751 addq(Address(z, zlen, Address::times_4, 0), tmp1); 9752 jmp(L_fourth_loop); 9753 bind(L_fourth_loop_exit); 9754 } 9755 9756 /** 9757 * Shift z[] left by 1 bit. 9758 * Preserves x, len, z and zlen registers and modifies rest of the registers. 9759 * 9760 */ 9761 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 9762 9763 Label L_fifth_loop, L_fifth_loop_exit; 9764 9765 // Fifth loop 9766 // Perform primitiveLeftShift(z, zlen, 1) 9767 9768 const Register prev_carry = tmp1; 9769 const Register new_carry = tmp4; 9770 const Register value = tmp2; 9771 const Register zidx = tmp3; 9772 9773 // int zidx, carry; 9774 // long value; 9775 // carry = 0; 9776 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 9777 // (carry:value) = (z[i] << 1) | carry ; 9778 // z[i] = value; 9779 // } 9780 9781 movl(zidx, zlen); 9782 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 9783 9784 bind(L_fifth_loop); 9785 decl(zidx); // Use decl to preserve carry flag 9786 decl(zidx); 9787 jccb(Assembler::negative, L_fifth_loop_exit); 9788 9789 if (UseBMI2Instructions) { 9790 movq(value, Address(z, zidx, Address::times_4, 0)); 9791 rclq(value, 1); 9792 rorxq(value, value, 32); 9793 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9794 } 9795 else { 9796 // clear new_carry 9797 xorl(new_carry, new_carry); 9798 9799 // Shift z[i] by 1, or in previous carry and save new carry 9800 movq(value, Address(z, zidx, Address::times_4, 0)); 9801 shlq(value, 1); 9802 adcl(new_carry, 0); 9803 9804 orq(value, prev_carry); 9805 rorq(value, 0x20); 9806 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9807 9808 // Set previous carry = new carry 9809 movl(prev_carry, new_carry); 9810 } 9811 jmp(L_fifth_loop); 9812 9813 bind(L_fifth_loop_exit); 9814 } 9815 9816 9817 /** 9818 * Code for BigInteger::squareToLen() intrinsic 9819 * 9820 * rdi: x 9821 * rsi: len 9822 * r8: z 9823 * rcx: zlen 9824 * r12: tmp1 9825 * r13: tmp2 9826 * r14: tmp3 9827 * r15: tmp4 9828 * rbx: tmp5 9829 * 9830 */ 9831 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9832 9833 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 9834 push(tmp1); 9835 push(tmp2); 9836 push(tmp3); 9837 push(tmp4); 9838 push(tmp5); 9839 9840 // First loop 9841 // Store the squares, right shifted one bit (i.e., divided by 2). 9842 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 9843 9844 // Add in off-diagonal sums. 9845 // 9846 // Second, third (nested) and fourth loops. 9847 // zlen +=2; 9848 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 9849 // carry = 0; 9850 // long op2 = x[xidx:xidx+1]; 9851 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 9852 // k -= 2; 9853 // long op1 = x[j:j+1]; 9854 // long sum = z[k:k+1]; 9855 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 9856 // z[k:k+1] = sum; 9857 // } 9858 // add_one_64(z, k, carry, tmp_regs); 9859 // } 9860 9861 const Register carry = tmp5; 9862 const Register sum = tmp3; 9863 const Register op1 = tmp4; 9864 Register op2 = tmp2; 9865 9866 push(zlen); 9867 push(len); 9868 addl(zlen,2); 9869 bind(L_second_loop); 9870 xorq(carry, carry); 9871 subl(zlen, 4); 9872 subl(len, 2); 9873 push(zlen); 9874 push(len); 9875 cmpl(len, 0); 9876 jccb(Assembler::lessEqual, L_second_loop_exit); 9877 9878 // Multiply an array by one 64 bit long. 9879 if (UseBMI2Instructions) { 9880 op2 = rdxReg; 9881 movq(op2, Address(x, len, Address::times_4, 0)); 9882 rorxq(op2, op2, 32); 9883 } 9884 else { 9885 movq(op2, Address(x, len, Address::times_4, 0)); 9886 rorq(op2, 32); 9887 } 9888 9889 bind(L_third_loop); 9890 decrementl(len); 9891 jccb(Assembler::negative, L_third_loop_exit); 9892 decrementl(len); 9893 jccb(Assembler::negative, L_last_x); 9894 9895 movq(op1, Address(x, len, Address::times_4, 0)); 9896 rorq(op1, 32); 9897 9898 bind(L_multiply); 9899 subl(zlen, 2); 9900 movq(sum, Address(z, zlen, Address::times_4, 0)); 9901 9902 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 9903 if (UseBMI2Instructions) { 9904 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 9905 } 9906 else { 9907 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9908 } 9909 9910 movq(Address(z, zlen, Address::times_4, 0), sum); 9911 9912 jmp(L_third_loop); 9913 bind(L_third_loop_exit); 9914 9915 // Fourth loop 9916 // Add 64 bit long carry into z with carry propogation. 9917 // Uses offsetted zlen. 9918 add_one_64(z, zlen, carry, tmp1); 9919 9920 pop(len); 9921 pop(zlen); 9922 jmp(L_second_loop); 9923 9924 // Next infrequent code is moved outside loops. 9925 bind(L_last_x); 9926 movl(op1, Address(x, 0)); 9927 jmp(L_multiply); 9928 9929 bind(L_second_loop_exit); 9930 pop(len); 9931 pop(zlen); 9932 pop(len); 9933 pop(zlen); 9934 9935 // Fifth loop 9936 // Shift z left 1 bit. 9937 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 9938 9939 // z[zlen-1] |= x[len-1] & 1; 9940 movl(tmp3, Address(x, len, Address::times_4, -4)); 9941 andl(tmp3, 1); 9942 orl(Address(z, zlen, Address::times_4, -4), tmp3); 9943 9944 pop(tmp5); 9945 pop(tmp4); 9946 pop(tmp3); 9947 pop(tmp2); 9948 pop(tmp1); 9949 } 9950 9951 /** 9952 * Helper function for mul_add() 9953 * Multiply the in[] by int k and add to out[] starting at offset offs using 9954 * 128 bit by 32 bit multiply and return the carry in tmp5. 9955 * Only quad int aligned length of in[] is operated on in this function. 9956 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 9957 * This function preserves out, in and k registers. 9958 * len and offset point to the appropriate index in "in" & "out" correspondingly 9959 * tmp5 has the carry. 9960 * other registers are temporary and are modified. 9961 * 9962 */ 9963 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 9964 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 9965 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9966 9967 Label L_first_loop, L_first_loop_exit; 9968 9969 movl(tmp1, len); 9970 shrl(tmp1, 2); 9971 9972 bind(L_first_loop); 9973 subl(tmp1, 1); 9974 jccb(Assembler::negative, L_first_loop_exit); 9975 9976 subl(len, 4); 9977 subl(offset, 4); 9978 9979 Register op2 = tmp2; 9980 const Register sum = tmp3; 9981 const Register op1 = tmp4; 9982 const Register carry = tmp5; 9983 9984 if (UseBMI2Instructions) { 9985 op2 = rdxReg; 9986 } 9987 9988 movq(op1, Address(in, len, Address::times_4, 8)); 9989 rorq(op1, 32); 9990 movq(sum, Address(out, offset, Address::times_4, 8)); 9991 rorq(sum, 32); 9992 if (UseBMI2Instructions) { 9993 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9994 } 9995 else { 9996 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9997 } 9998 // Store back in big endian from little endian 9999 rorq(sum, 0x20); 10000 movq(Address(out, offset, Address::times_4, 8), sum); 10001 10002 movq(op1, Address(in, len, Address::times_4, 0)); 10003 rorq(op1, 32); 10004 movq(sum, Address(out, offset, Address::times_4, 0)); 10005 rorq(sum, 32); 10006 if (UseBMI2Instructions) { 10007 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10008 } 10009 else { 10010 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10011 } 10012 // Store back in big endian from little endian 10013 rorq(sum, 0x20); 10014 movq(Address(out, offset, Address::times_4, 0), sum); 10015 10016 jmp(L_first_loop); 10017 bind(L_first_loop_exit); 10018 } 10019 10020 /** 10021 * Code for BigInteger::mulAdd() intrinsic 10022 * 10023 * rdi: out 10024 * rsi: in 10025 * r11: offs (out.length - offset) 10026 * rcx: len 10027 * r8: k 10028 * r12: tmp1 10029 * r13: tmp2 10030 * r14: tmp3 10031 * r15: tmp4 10032 * rbx: tmp5 10033 * Multiply the in[] by word k and add to out[], return the carry in rax 10034 */ 10035 void MacroAssembler::mul_add(Register out, Register in, Register offs, 10036 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 10037 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 10038 10039 Label L_carry, L_last_in, L_done; 10040 10041 // carry = 0; 10042 // for (int j=len-1; j >= 0; j--) { 10043 // long product = (in[j] & LONG_MASK) * kLong + 10044 // (out[offs] & LONG_MASK) + carry; 10045 // out[offs--] = (int)product; 10046 // carry = product >>> 32; 10047 // } 10048 // 10049 push(tmp1); 10050 push(tmp2); 10051 push(tmp3); 10052 push(tmp4); 10053 push(tmp5); 10054 10055 Register op2 = tmp2; 10056 const Register sum = tmp3; 10057 const Register op1 = tmp4; 10058 const Register carry = tmp5; 10059 10060 if (UseBMI2Instructions) { 10061 op2 = rdxReg; 10062 movl(op2, k); 10063 } 10064 else { 10065 movl(op2, k); 10066 } 10067 10068 xorq(carry, carry); 10069 10070 //First loop 10071 10072 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 10073 //The carry is in tmp5 10074 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 10075 10076 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 10077 decrementl(len); 10078 jccb(Assembler::negative, L_carry); 10079 decrementl(len); 10080 jccb(Assembler::negative, L_last_in); 10081 10082 movq(op1, Address(in, len, Address::times_4, 0)); 10083 rorq(op1, 32); 10084 10085 subl(offs, 2); 10086 movq(sum, Address(out, offs, Address::times_4, 0)); 10087 rorq(sum, 32); 10088 10089 if (UseBMI2Instructions) { 10090 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10091 } 10092 else { 10093 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10094 } 10095 10096 // Store back in big endian from little endian 10097 rorq(sum, 0x20); 10098 movq(Address(out, offs, Address::times_4, 0), sum); 10099 10100 testl(len, len); 10101 jccb(Assembler::zero, L_carry); 10102 10103 //Multiply the last in[] entry, if any 10104 bind(L_last_in); 10105 movl(op1, Address(in, 0)); 10106 movl(sum, Address(out, offs, Address::times_4, -4)); 10107 10108 movl(raxReg, k); 10109 mull(op1); //tmp4 * eax -> edx:eax 10110 addl(sum, carry); 10111 adcl(rdxReg, 0); 10112 addl(sum, raxReg); 10113 adcl(rdxReg, 0); 10114 movl(carry, rdxReg); 10115 10116 movl(Address(out, offs, Address::times_4, -4), sum); 10117 10118 bind(L_carry); 10119 //return tmp5/carry as carry in rax 10120 movl(rax, carry); 10121 10122 bind(L_done); 10123 pop(tmp5); 10124 pop(tmp4); 10125 pop(tmp3); 10126 pop(tmp2); 10127 pop(tmp1); 10128 } 10129 #endif 10130 10131 /** 10132 * Emits code to update CRC-32 with a byte value according to constants in table 10133 * 10134 * @param [in,out]crc Register containing the crc. 10135 * @param [in]val Register containing the byte to fold into the CRC. 10136 * @param [in]table Register containing the table of crc constants. 10137 * 10138 * uint32_t crc; 10139 * val = crc_table[(val ^ crc) & 0xFF]; 10140 * crc = val ^ (crc >> 8); 10141 * 10142 */ 10143 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 10144 xorl(val, crc); 10145 andl(val, 0xFF); 10146 shrl(crc, 8); // unsigned shift 10147 xorl(crc, Address(table, val, Address::times_4, 0)); 10148 } 10149 10150 /** 10151 * Fold 128-bit data chunk 10152 */ 10153 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 10154 if (UseAVX > 0) { 10155 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 10156 vpclmulldq(xcrc, xK, xcrc); // [63:0] 10157 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 10158 pxor(xcrc, xtmp); 10159 } else { 10160 movdqa(xtmp, xcrc); 10161 pclmulhdq(xtmp, xK); // [123:64] 10162 pclmulldq(xcrc, xK); // [63:0] 10163 pxor(xcrc, xtmp); 10164 movdqu(xtmp, Address(buf, offset)); 10165 pxor(xcrc, xtmp); 10166 } 10167 } 10168 10169 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 10170 if (UseAVX > 0) { 10171 vpclmulhdq(xtmp, xK, xcrc); 10172 vpclmulldq(xcrc, xK, xcrc); 10173 pxor(xcrc, xbuf); 10174 pxor(xcrc, xtmp); 10175 } else { 10176 movdqa(xtmp, xcrc); 10177 pclmulhdq(xtmp, xK); 10178 pclmulldq(xcrc, xK); 10179 pxor(xcrc, xbuf); 10180 pxor(xcrc, xtmp); 10181 } 10182 } 10183 10184 /** 10185 * 8-bit folds to compute 32-bit CRC 10186 * 10187 * uint64_t xcrc; 10188 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 10189 */ 10190 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 10191 movdl(tmp, xcrc); 10192 andl(tmp, 0xFF); 10193 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 10194 psrldq(xcrc, 1); // unsigned shift one byte 10195 pxor(xcrc, xtmp); 10196 } 10197 10198 /** 10199 * uint32_t crc; 10200 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 10201 */ 10202 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 10203 movl(tmp, crc); 10204 andl(tmp, 0xFF); 10205 shrl(crc, 8); 10206 xorl(crc, Address(table, tmp, Address::times_4, 0)); 10207 } 10208 10209 /** 10210 * @param crc register containing existing CRC (32-bit) 10211 * @param buf register pointing to input byte buffer (byte*) 10212 * @param len register containing number of bytes 10213 * @param table register that will contain address of CRC table 10214 * @param tmp scratch register 10215 */ 10216 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 10217 assert_different_registers(crc, buf, len, table, tmp, rax); 10218 10219 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 10220 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 10221 10222 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 10223 // context for the registers used, where all instructions below are using 128-bit mode 10224 // On EVEX without VL and BW, these instructions will all be AVX. 10225 if (VM_Version::supports_avx512vlbw()) { 10226 movl(tmp, 0xffff); 10227 kmovwl(k1, tmp); 10228 } 10229 10230 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 10231 notl(crc); // ~crc 10232 cmpl(len, 16); 10233 jcc(Assembler::less, L_tail); 10234 10235 // Align buffer to 16 bytes 10236 movl(tmp, buf); 10237 andl(tmp, 0xF); 10238 jccb(Assembler::zero, L_aligned); 10239 subl(tmp, 16); 10240 addl(len, tmp); 10241 10242 align(4); 10243 BIND(L_align_loop); 10244 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10245 update_byte_crc32(crc, rax, table); 10246 increment(buf); 10247 incrementl(tmp); 10248 jccb(Assembler::less, L_align_loop); 10249 10250 BIND(L_aligned); 10251 movl(tmp, len); // save 10252 shrl(len, 4); 10253 jcc(Assembler::zero, L_tail_restore); 10254 10255 // Fold crc into first bytes of vector 10256 movdqa(xmm1, Address(buf, 0)); 10257 movdl(rax, xmm1); 10258 xorl(crc, rax); 10259 if (VM_Version::supports_sse4_1()) { 10260 pinsrd(xmm1, crc, 0); 10261 } else { 10262 pinsrw(xmm1, crc, 0); 10263 shrl(crc, 16); 10264 pinsrw(xmm1, crc, 1); 10265 } 10266 addptr(buf, 16); 10267 subl(len, 4); // len > 0 10268 jcc(Assembler::less, L_fold_tail); 10269 10270 movdqa(xmm2, Address(buf, 0)); 10271 movdqa(xmm3, Address(buf, 16)); 10272 movdqa(xmm4, Address(buf, 32)); 10273 addptr(buf, 48); 10274 subl(len, 3); 10275 jcc(Assembler::lessEqual, L_fold_512b); 10276 10277 // Fold total 512 bits of polynomial on each iteration, 10278 // 128 bits per each of 4 parallel streams. 10279 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 10280 10281 align(32); 10282 BIND(L_fold_512b_loop); 10283 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10284 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 10285 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 10286 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 10287 addptr(buf, 64); 10288 subl(len, 4); 10289 jcc(Assembler::greater, L_fold_512b_loop); 10290 10291 // Fold 512 bits to 128 bits. 10292 BIND(L_fold_512b); 10293 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10294 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 10295 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 10296 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 10297 10298 // Fold the rest of 128 bits data chunks 10299 BIND(L_fold_tail); 10300 addl(len, 3); 10301 jccb(Assembler::lessEqual, L_fold_128b); 10302 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10303 10304 BIND(L_fold_tail_loop); 10305 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10306 addptr(buf, 16); 10307 decrementl(len); 10308 jccb(Assembler::greater, L_fold_tail_loop); 10309 10310 // Fold 128 bits in xmm1 down into 32 bits in crc register. 10311 BIND(L_fold_128b); 10312 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 10313 if (UseAVX > 0) { 10314 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 10315 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 10316 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 10317 } else { 10318 movdqa(xmm2, xmm0); 10319 pclmulqdq(xmm2, xmm1, 0x1); 10320 movdqa(xmm3, xmm0); 10321 pand(xmm3, xmm2); 10322 pclmulqdq(xmm0, xmm3, 0x1); 10323 } 10324 psrldq(xmm1, 8); 10325 psrldq(xmm2, 4); 10326 pxor(xmm0, xmm1); 10327 pxor(xmm0, xmm2); 10328 10329 // 8 8-bit folds to compute 32-bit CRC. 10330 for (int j = 0; j < 4; j++) { 10331 fold_8bit_crc32(xmm0, table, xmm1, rax); 10332 } 10333 movdl(crc, xmm0); // mov 32 bits to general register 10334 for (int j = 0; j < 4; j++) { 10335 fold_8bit_crc32(crc, table, rax); 10336 } 10337 10338 BIND(L_tail_restore); 10339 movl(len, tmp); // restore 10340 BIND(L_tail); 10341 andl(len, 0xf); 10342 jccb(Assembler::zero, L_exit); 10343 10344 // Fold the rest of bytes 10345 align(4); 10346 BIND(L_tail_loop); 10347 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10348 update_byte_crc32(crc, rax, table); 10349 increment(buf); 10350 decrementl(len); 10351 jccb(Assembler::greater, L_tail_loop); 10352 10353 BIND(L_exit); 10354 notl(crc); // ~c 10355 } 10356 10357 #ifdef _LP64 10358 // S. Gueron / Information Processing Letters 112 (2012) 184 10359 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 10360 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 10361 // Output: the 64-bit carry-less product of B * CONST 10362 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 10363 Register tmp1, Register tmp2, Register tmp3) { 10364 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10365 if (n > 0) { 10366 addq(tmp3, n * 256 * 8); 10367 } 10368 // Q1 = TABLEExt[n][B & 0xFF]; 10369 movl(tmp1, in); 10370 andl(tmp1, 0x000000FF); 10371 shll(tmp1, 3); 10372 addq(tmp1, tmp3); 10373 movq(tmp1, Address(tmp1, 0)); 10374 10375 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10376 movl(tmp2, in); 10377 shrl(tmp2, 8); 10378 andl(tmp2, 0x000000FF); 10379 shll(tmp2, 3); 10380 addq(tmp2, tmp3); 10381 movq(tmp2, Address(tmp2, 0)); 10382 10383 shlq(tmp2, 8); 10384 xorq(tmp1, tmp2); 10385 10386 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10387 movl(tmp2, in); 10388 shrl(tmp2, 16); 10389 andl(tmp2, 0x000000FF); 10390 shll(tmp2, 3); 10391 addq(tmp2, tmp3); 10392 movq(tmp2, Address(tmp2, 0)); 10393 10394 shlq(tmp2, 16); 10395 xorq(tmp1, tmp2); 10396 10397 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10398 shrl(in, 24); 10399 andl(in, 0x000000FF); 10400 shll(in, 3); 10401 addq(in, tmp3); 10402 movq(in, Address(in, 0)); 10403 10404 shlq(in, 24); 10405 xorq(in, tmp1); 10406 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10407 } 10408 10409 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10410 Register in_out, 10411 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10412 XMMRegister w_xtmp2, 10413 Register tmp1, 10414 Register n_tmp2, Register n_tmp3) { 10415 if (is_pclmulqdq_supported) { 10416 movdl(w_xtmp1, in_out); // modified blindly 10417 10418 movl(tmp1, const_or_pre_comp_const_index); 10419 movdl(w_xtmp2, tmp1); 10420 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10421 10422 movdq(in_out, w_xtmp1); 10423 } else { 10424 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 10425 } 10426 } 10427 10428 // Recombination Alternative 2: No bit-reflections 10429 // T1 = (CRC_A * U1) << 1 10430 // T2 = (CRC_B * U2) << 1 10431 // C1 = T1 >> 32 10432 // C2 = T2 >> 32 10433 // T1 = T1 & 0xFFFFFFFF 10434 // T2 = T2 & 0xFFFFFFFF 10435 // T1 = CRC32(0, T1) 10436 // T2 = CRC32(0, T2) 10437 // C1 = C1 ^ T1 10438 // C2 = C2 ^ T2 10439 // CRC = C1 ^ C2 ^ CRC_C 10440 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10441 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10442 Register tmp1, Register tmp2, 10443 Register n_tmp3) { 10444 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10445 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10446 shlq(in_out, 1); 10447 movl(tmp1, in_out); 10448 shrq(in_out, 32); 10449 xorl(tmp2, tmp2); 10450 crc32(tmp2, tmp1, 4); 10451 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 10452 shlq(in1, 1); 10453 movl(tmp1, in1); 10454 shrq(in1, 32); 10455 xorl(tmp2, tmp2); 10456 crc32(tmp2, tmp1, 4); 10457 xorl(in1, tmp2); 10458 xorl(in_out, in1); 10459 xorl(in_out, in2); 10460 } 10461 10462 // Set N to predefined value 10463 // Subtract from a lenght of a buffer 10464 // execute in a loop: 10465 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 10466 // for i = 1 to N do 10467 // CRC_A = CRC32(CRC_A, A[i]) 10468 // CRC_B = CRC32(CRC_B, B[i]) 10469 // CRC_C = CRC32(CRC_C, C[i]) 10470 // end for 10471 // Recombine 10472 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10473 Register in_out1, Register in_out2, Register in_out3, 10474 Register tmp1, Register tmp2, Register tmp3, 10475 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10476 Register tmp4, Register tmp5, 10477 Register n_tmp6) { 10478 Label L_processPartitions; 10479 Label L_processPartition; 10480 Label L_exit; 10481 10482 bind(L_processPartitions); 10483 cmpl(in_out1, 3 * size); 10484 jcc(Assembler::less, L_exit); 10485 xorl(tmp1, tmp1); 10486 xorl(tmp2, tmp2); 10487 movq(tmp3, in_out2); 10488 addq(tmp3, size); 10489 10490 bind(L_processPartition); 10491 crc32(in_out3, Address(in_out2, 0), 8); 10492 crc32(tmp1, Address(in_out2, size), 8); 10493 crc32(tmp2, Address(in_out2, size * 2), 8); 10494 addq(in_out2, 8); 10495 cmpq(in_out2, tmp3); 10496 jcc(Assembler::less, L_processPartition); 10497 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10498 w_xtmp1, w_xtmp2, w_xtmp3, 10499 tmp4, tmp5, 10500 n_tmp6); 10501 addq(in_out2, 2 * size); 10502 subl(in_out1, 3 * size); 10503 jmp(L_processPartitions); 10504 10505 bind(L_exit); 10506 } 10507 #else 10508 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 10509 Register tmp1, Register tmp2, Register tmp3, 10510 XMMRegister xtmp1, XMMRegister xtmp2) { 10511 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10512 if (n > 0) { 10513 addl(tmp3, n * 256 * 8); 10514 } 10515 // Q1 = TABLEExt[n][B & 0xFF]; 10516 movl(tmp1, in_out); 10517 andl(tmp1, 0x000000FF); 10518 shll(tmp1, 3); 10519 addl(tmp1, tmp3); 10520 movq(xtmp1, Address(tmp1, 0)); 10521 10522 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10523 movl(tmp2, in_out); 10524 shrl(tmp2, 8); 10525 andl(tmp2, 0x000000FF); 10526 shll(tmp2, 3); 10527 addl(tmp2, tmp3); 10528 movq(xtmp2, Address(tmp2, 0)); 10529 10530 psllq(xtmp2, 8); 10531 pxor(xtmp1, xtmp2); 10532 10533 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10534 movl(tmp2, in_out); 10535 shrl(tmp2, 16); 10536 andl(tmp2, 0x000000FF); 10537 shll(tmp2, 3); 10538 addl(tmp2, tmp3); 10539 movq(xtmp2, Address(tmp2, 0)); 10540 10541 psllq(xtmp2, 16); 10542 pxor(xtmp1, xtmp2); 10543 10544 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10545 shrl(in_out, 24); 10546 andl(in_out, 0x000000FF); 10547 shll(in_out, 3); 10548 addl(in_out, tmp3); 10549 movq(xtmp2, Address(in_out, 0)); 10550 10551 psllq(xtmp2, 24); 10552 pxor(xtmp1, xtmp2); // Result in CXMM 10553 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10554 } 10555 10556 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10557 Register in_out, 10558 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10559 XMMRegister w_xtmp2, 10560 Register tmp1, 10561 Register n_tmp2, Register n_tmp3) { 10562 if (is_pclmulqdq_supported) { 10563 movdl(w_xtmp1, in_out); 10564 10565 movl(tmp1, const_or_pre_comp_const_index); 10566 movdl(w_xtmp2, tmp1); 10567 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10568 // Keep result in XMM since GPR is 32 bit in length 10569 } else { 10570 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 10571 } 10572 } 10573 10574 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10575 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10576 Register tmp1, Register tmp2, 10577 Register n_tmp3) { 10578 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10579 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10580 10581 psllq(w_xtmp1, 1); 10582 movdl(tmp1, w_xtmp1); 10583 psrlq(w_xtmp1, 32); 10584 movdl(in_out, w_xtmp1); 10585 10586 xorl(tmp2, tmp2); 10587 crc32(tmp2, tmp1, 4); 10588 xorl(in_out, tmp2); 10589 10590 psllq(w_xtmp2, 1); 10591 movdl(tmp1, w_xtmp2); 10592 psrlq(w_xtmp2, 32); 10593 movdl(in1, w_xtmp2); 10594 10595 xorl(tmp2, tmp2); 10596 crc32(tmp2, tmp1, 4); 10597 xorl(in1, tmp2); 10598 xorl(in_out, in1); 10599 xorl(in_out, in2); 10600 } 10601 10602 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10603 Register in_out1, Register in_out2, Register in_out3, 10604 Register tmp1, Register tmp2, Register tmp3, 10605 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10606 Register tmp4, Register tmp5, 10607 Register n_tmp6) { 10608 Label L_processPartitions; 10609 Label L_processPartition; 10610 Label L_exit; 10611 10612 bind(L_processPartitions); 10613 cmpl(in_out1, 3 * size); 10614 jcc(Assembler::less, L_exit); 10615 xorl(tmp1, tmp1); 10616 xorl(tmp2, tmp2); 10617 movl(tmp3, in_out2); 10618 addl(tmp3, size); 10619 10620 bind(L_processPartition); 10621 crc32(in_out3, Address(in_out2, 0), 4); 10622 crc32(tmp1, Address(in_out2, size), 4); 10623 crc32(tmp2, Address(in_out2, size*2), 4); 10624 crc32(in_out3, Address(in_out2, 0+4), 4); 10625 crc32(tmp1, Address(in_out2, size+4), 4); 10626 crc32(tmp2, Address(in_out2, size*2+4), 4); 10627 addl(in_out2, 8); 10628 cmpl(in_out2, tmp3); 10629 jcc(Assembler::less, L_processPartition); 10630 10631 push(tmp3); 10632 push(in_out1); 10633 push(in_out2); 10634 tmp4 = tmp3; 10635 tmp5 = in_out1; 10636 n_tmp6 = in_out2; 10637 10638 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10639 w_xtmp1, w_xtmp2, w_xtmp3, 10640 tmp4, tmp5, 10641 n_tmp6); 10642 10643 pop(in_out2); 10644 pop(in_out1); 10645 pop(tmp3); 10646 10647 addl(in_out2, 2 * size); 10648 subl(in_out1, 3 * size); 10649 jmp(L_processPartitions); 10650 10651 bind(L_exit); 10652 } 10653 #endif //LP64 10654 10655 #ifdef _LP64 10656 // Algorithm 2: Pipelined usage of the CRC32 instruction. 10657 // Input: A buffer I of L bytes. 10658 // Output: the CRC32C value of the buffer. 10659 // Notations: 10660 // Write L = 24N + r, with N = floor (L/24). 10661 // r = L mod 24 (0 <= r < 24). 10662 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 10663 // N quadwords, and R consists of r bytes. 10664 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 10665 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 10666 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 10667 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 10668 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10669 Register tmp1, Register tmp2, Register tmp3, 10670 Register tmp4, Register tmp5, Register tmp6, 10671 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10672 bool is_pclmulqdq_supported) { 10673 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10674 Label L_wordByWord; 10675 Label L_byteByByteProlog; 10676 Label L_byteByByte; 10677 Label L_exit; 10678 10679 if (is_pclmulqdq_supported ) { 10680 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10681 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 10682 10683 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10684 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10685 10686 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10687 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10688 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 10689 } else { 10690 const_or_pre_comp_const_index[0] = 1; 10691 const_or_pre_comp_const_index[1] = 0; 10692 10693 const_or_pre_comp_const_index[2] = 3; 10694 const_or_pre_comp_const_index[3] = 2; 10695 10696 const_or_pre_comp_const_index[4] = 5; 10697 const_or_pre_comp_const_index[5] = 4; 10698 } 10699 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10700 in2, in1, in_out, 10701 tmp1, tmp2, tmp3, 10702 w_xtmp1, w_xtmp2, w_xtmp3, 10703 tmp4, tmp5, 10704 tmp6); 10705 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10706 in2, in1, in_out, 10707 tmp1, tmp2, tmp3, 10708 w_xtmp1, w_xtmp2, w_xtmp3, 10709 tmp4, tmp5, 10710 tmp6); 10711 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10712 in2, in1, in_out, 10713 tmp1, tmp2, tmp3, 10714 w_xtmp1, w_xtmp2, w_xtmp3, 10715 tmp4, tmp5, 10716 tmp6); 10717 movl(tmp1, in2); 10718 andl(tmp1, 0x00000007); 10719 negl(tmp1); 10720 addl(tmp1, in2); 10721 addq(tmp1, in1); 10722 10723 BIND(L_wordByWord); 10724 cmpq(in1, tmp1); 10725 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10726 crc32(in_out, Address(in1, 0), 4); 10727 addq(in1, 4); 10728 jmp(L_wordByWord); 10729 10730 BIND(L_byteByByteProlog); 10731 andl(in2, 0x00000007); 10732 movl(tmp2, 1); 10733 10734 BIND(L_byteByByte); 10735 cmpl(tmp2, in2); 10736 jccb(Assembler::greater, L_exit); 10737 crc32(in_out, Address(in1, 0), 1); 10738 incq(in1); 10739 incl(tmp2); 10740 jmp(L_byteByByte); 10741 10742 BIND(L_exit); 10743 } 10744 #else 10745 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10746 Register tmp1, Register tmp2, Register tmp3, 10747 Register tmp4, Register tmp5, Register tmp6, 10748 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10749 bool is_pclmulqdq_supported) { 10750 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10751 Label L_wordByWord; 10752 Label L_byteByByteProlog; 10753 Label L_byteByByte; 10754 Label L_exit; 10755 10756 if (is_pclmulqdq_supported) { 10757 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10758 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 10759 10760 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10761 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10762 10763 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10764 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10765 } else { 10766 const_or_pre_comp_const_index[0] = 1; 10767 const_or_pre_comp_const_index[1] = 0; 10768 10769 const_or_pre_comp_const_index[2] = 3; 10770 const_or_pre_comp_const_index[3] = 2; 10771 10772 const_or_pre_comp_const_index[4] = 5; 10773 const_or_pre_comp_const_index[5] = 4; 10774 } 10775 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10776 in2, in1, in_out, 10777 tmp1, tmp2, tmp3, 10778 w_xtmp1, w_xtmp2, w_xtmp3, 10779 tmp4, tmp5, 10780 tmp6); 10781 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10782 in2, in1, in_out, 10783 tmp1, tmp2, tmp3, 10784 w_xtmp1, w_xtmp2, w_xtmp3, 10785 tmp4, tmp5, 10786 tmp6); 10787 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10788 in2, in1, in_out, 10789 tmp1, tmp2, tmp3, 10790 w_xtmp1, w_xtmp2, w_xtmp3, 10791 tmp4, tmp5, 10792 tmp6); 10793 movl(tmp1, in2); 10794 andl(tmp1, 0x00000007); 10795 negl(tmp1); 10796 addl(tmp1, in2); 10797 addl(tmp1, in1); 10798 10799 BIND(L_wordByWord); 10800 cmpl(in1, tmp1); 10801 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10802 crc32(in_out, Address(in1,0), 4); 10803 addl(in1, 4); 10804 jmp(L_wordByWord); 10805 10806 BIND(L_byteByByteProlog); 10807 andl(in2, 0x00000007); 10808 movl(tmp2, 1); 10809 10810 BIND(L_byteByByte); 10811 cmpl(tmp2, in2); 10812 jccb(Assembler::greater, L_exit); 10813 movb(tmp1, Address(in1, 0)); 10814 crc32(in_out, tmp1, 1); 10815 incl(in1); 10816 incl(tmp2); 10817 jmp(L_byteByByte); 10818 10819 BIND(L_exit); 10820 } 10821 #endif // LP64 10822 #undef BIND 10823 #undef BLOCK_COMMENT 10824 10825 // Compress char[] array to byte[]. 10826 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java 10827 // @HotSpotIntrinsicCandidate 10828 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) { 10829 // for (int i = 0; i < len; i++) { 10830 // int c = src[srcOff++]; 10831 // if (c >>> 8 != 0) { 10832 // return 0; 10833 // } 10834 // dst[dstOff++] = (byte)c; 10835 // } 10836 // return len; 10837 // } 10838 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 10839 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 10840 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 10841 Register tmp5, Register result) { 10842 Label copy_chars_loop, return_length, return_zero, done, below_threshold; 10843 10844 // rsi: src 10845 // rdi: dst 10846 // rdx: len 10847 // rcx: tmp5 10848 // rax: result 10849 10850 // rsi holds start addr of source char[] to be compressed 10851 // rdi holds start addr of destination byte[] 10852 // rdx holds length 10853 10854 assert(len != result, ""); 10855 10856 // save length for return 10857 push(len); 10858 10859 if ((UseAVX > 2) && // AVX512 10860 VM_Version::supports_avx512vlbw() && 10861 VM_Version::supports_bmi2()) { 10862 10863 set_vector_masking(); // opening of the stub context for programming mask registers 10864 10865 Label copy_32_loop, copy_loop_tail, copy_just_portion_of_candidates; 10866 10867 // alignement 10868 Label post_alignement; 10869 10870 // if length of the string is less than 16, handle it in an old fashioned 10871 // way 10872 testl(len, -32); 10873 jcc(Assembler::zero, below_threshold); 10874 10875 // First check whether a character is compressable ( <= 0xFF). 10876 // Create mask to test for Unicode chars inside zmm vector 10877 movl(result, 0x00FF); 10878 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit); 10879 10880 testl(len, -64); 10881 jcc(Assembler::zero, post_alignement); 10882 10883 // Save k1 10884 kmovql(k3, k1); 10885 10886 movl(tmp5, dst); 10887 andl(tmp5, (64 - 1)); 10888 negl(tmp5); 10889 andl(tmp5, (64 - 1)); 10890 10891 // bail out when there is nothing to be done 10892 testl(tmp5, 0xFFFFFFFF); 10893 jcc(Assembler::zero, post_alignement); 10894 10895 // ~(~0 << len), where len is the # of remaining elements to process 10896 movl(result, 0xFFFFFFFF); 10897 shlxl(result, result, tmp5); 10898 notl(result); 10899 10900 kmovdl(k1, result); 10901 10902 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10903 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10904 ktestd(k2, k1); 10905 jcc(Assembler::carryClear, copy_just_portion_of_candidates); 10906 10907 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10908 10909 addptr(src, tmp5); 10910 addptr(src, tmp5); 10911 addptr(dst, tmp5); 10912 subl(len, tmp5); 10913 10914 bind(post_alignement); 10915 // end of alignement 10916 10917 movl(tmp5, len); 10918 andl(tmp5, (32 - 1)); // tail count (in chars) 10919 andl(len, ~(32 - 1)); // vector count (in chars) 10920 jcc(Assembler::zero, copy_loop_tail); 10921 10922 lea(src, Address(src, len, Address::times_2)); 10923 lea(dst, Address(dst, len, Address::times_1)); 10924 negptr(len); 10925 10926 bind(copy_32_loop); 10927 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit); 10928 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10929 kortestdl(k2, k2); 10930 jcc(Assembler::carryClear, copy_just_portion_of_candidates); 10931 10932 // All elements in current processed chunk are valid candidates for 10933 // compression. Write a truncated byte elements to the memory. 10934 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit); 10935 addptr(len, 32); 10936 jcc(Assembler::notZero, copy_32_loop); 10937 10938 bind(copy_loop_tail); 10939 // bail out when there is nothing to be done 10940 testl(tmp5, 0xFFFFFFFF); 10941 jcc(Assembler::zero, return_length); 10942 10943 // Save k1 10944 kmovql(k3, k1); 10945 10946 movl(len, tmp5); 10947 10948 // ~(~0 << len), where len is the # of remaining elements to process 10949 movl(result, 0xFFFFFFFF); 10950 shlxl(result, result, len); 10951 notl(result); 10952 10953 kmovdl(k1, result); 10954 10955 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit); 10956 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 10957 ktestd(k2, k1); 10958 jcc(Assembler::carryClear, copy_just_portion_of_candidates); 10959 10960 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10961 // Restore k1 10962 kmovql(k1, k3); 10963 10964 jmp(return_length); 10965 10966 bind(copy_just_portion_of_candidates); 10967 kmovdl(tmp5, k2); 10968 tzcntl(tmp5, tmp5); 10969 10970 // ~(~0 << tmp5), where tmp5 is a number of elements in an array from the 10971 // result to the first element larger than 0xFF 10972 movl(result, 0xFFFFFFFF); 10973 shlxl(result, result, tmp5); 10974 notl(result); 10975 10976 kmovdl(k1, result); 10977 10978 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit); 10979 // Restore k1 10980 kmovql(k1, k3); 10981 10982 jmp(return_zero); 10983 10984 clear_vector_masking(); // closing of the stub context for programming mask registers 10985 } 10986 if (UseSSE42Intrinsics) { 10987 Label copy_32_loop, copy_16, copy_tail; 10988 10989 bind(below_threshold); 10990 10991 movl(result, len); 10992 10993 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 10994 10995 // vectored compression 10996 andl(len, 0xfffffff0); // vector count (in chars) 10997 andl(result, 0x0000000f); // tail count (in chars) 10998 testl(len, len); 10999 jccb(Assembler::zero, copy_16); 11000 11001 // compress 16 chars per iter 11002 movdl(tmp1Reg, tmp5); 11003 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 11004 pxor(tmp4Reg, tmp4Reg); 11005 11006 lea(src, Address(src, len, Address::times_2)); 11007 lea(dst, Address(dst, len, Address::times_1)); 11008 negptr(len); 11009 11010 bind(copy_32_loop); 11011 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 11012 por(tmp4Reg, tmp2Reg); 11013 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 11014 por(tmp4Reg, tmp3Reg); 11015 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 11016 jcc(Assembler::notZero, return_zero); 11017 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 11018 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 11019 addptr(len, 16); 11020 jcc(Assembler::notZero, copy_32_loop); 11021 11022 // compress next vector of 8 chars (if any) 11023 bind(copy_16); 11024 movl(len, result); 11025 andl(len, 0xfffffff8); // vector count (in chars) 11026 andl(result, 0x00000007); // tail count (in chars) 11027 testl(len, len); 11028 jccb(Assembler::zero, copy_tail); 11029 11030 movdl(tmp1Reg, tmp5); 11031 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 11032 pxor(tmp3Reg, tmp3Reg); 11033 11034 movdqu(tmp2Reg, Address(src, 0)); 11035 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 11036 jccb(Assembler::notZero, return_zero); 11037 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 11038 movq(Address(dst, 0), tmp2Reg); 11039 addptr(src, 16); 11040 addptr(dst, 8); 11041 11042 bind(copy_tail); 11043 movl(len, result); 11044 } 11045 // compress 1 char per iter 11046 testl(len, len); 11047 jccb(Assembler::zero, return_length); 11048 lea(src, Address(src, len, Address::times_2)); 11049 lea(dst, Address(dst, len, Address::times_1)); 11050 negptr(len); 11051 11052 bind(copy_chars_loop); 11053 load_unsigned_short(result, Address(src, len, Address::times_2)); 11054 testl(result, 0xff00); // check if Unicode char 11055 jccb(Assembler::notZero, return_zero); 11056 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 11057 increment(len); 11058 jcc(Assembler::notZero, copy_chars_loop); 11059 11060 // if compression succeeded, return length 11061 bind(return_length); 11062 pop(result); 11063 jmpb(done); 11064 11065 // if compression failed, return 0 11066 bind(return_zero); 11067 xorl(result, result); 11068 addptr(rsp, wordSize); 11069 11070 bind(done); 11071 } 11072 11073 // Inflate byte[] array to char[]. 11074 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java 11075 // @HotSpotIntrinsicCandidate 11076 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) { 11077 // for (int i = 0; i < len; i++) { 11078 // dst[dstOff++] = (char)(src[srcOff++] & 0xff); 11079 // } 11080 // } 11081 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 11082 XMMRegister tmp1, Register tmp2) { 11083 Label copy_chars_loop, done, below_threshold; 11084 // rsi: src 11085 // rdi: dst 11086 // rdx: len 11087 // rcx: tmp2 11088 11089 // rsi holds start addr of source byte[] to be inflated 11090 // rdi holds start addr of destination char[] 11091 // rdx holds length 11092 assert_different_registers(src, dst, len, tmp2); 11093 11094 if ((UseAVX > 2) && // AVX512 11095 VM_Version::supports_avx512vlbw() && 11096 VM_Version::supports_bmi2()) { 11097 11098 set_vector_masking(); // opening of the stub context for programming mask registers 11099 11100 Label copy_32_loop, copy_tail; 11101 Register tmp3_aliased = len; 11102 11103 // if length of the string is less than 16, handle it in an old fashioned 11104 // way 11105 testl(len, -16); 11106 jcc(Assembler::zero, below_threshold); 11107 11108 // In order to use only one arithmetic operation for the main loop we use 11109 // this pre-calculation 11110 movl(tmp2, len); 11111 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop 11112 andl(len, -32); // vector count 11113 jccb(Assembler::zero, copy_tail); 11114 11115 lea(src, Address(src, len, Address::times_1)); 11116 lea(dst, Address(dst, len, Address::times_2)); 11117 negptr(len); 11118 11119 11120 // inflate 32 chars per iter 11121 bind(copy_32_loop); 11122 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit); 11123 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit); 11124 addptr(len, 32); 11125 jcc(Assembler::notZero, copy_32_loop); 11126 11127 bind(copy_tail); 11128 // bail out when there is nothing to be done 11129 testl(tmp2, -1); // we don't destroy the contents of tmp2 here 11130 jcc(Assembler::zero, done); 11131 11132 // Save k1 11133 kmovql(k2, k1); 11134 11135 // ~(~0 << length), where length is the # of remaining elements to process 11136 movl(tmp3_aliased, -1); 11137 shlxl(tmp3_aliased, tmp3_aliased, tmp2); 11138 notl(tmp3_aliased); 11139 kmovdl(k1, tmp3_aliased); 11140 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit); 11141 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit); 11142 11143 // Restore k1 11144 kmovql(k1, k2); 11145 jmp(done); 11146 11147 clear_vector_masking(); // closing of the stub context for programming mask registers 11148 } 11149 if (UseSSE42Intrinsics) { 11150 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; 11151 11152 movl(tmp2, len); 11153 11154 if (UseAVX > 1) { 11155 andl(tmp2, (16 - 1)); 11156 andl(len, -16); 11157 jccb(Assembler::zero, copy_new_tail); 11158 } else { 11159 andl(tmp2, 0x00000007); // tail count (in chars) 11160 andl(len, 0xfffffff8); // vector count (in chars) 11161 jccb(Assembler::zero, copy_tail); 11162 } 11163 11164 // vectored inflation 11165 lea(src, Address(src, len, Address::times_1)); 11166 lea(dst, Address(dst, len, Address::times_2)); 11167 negptr(len); 11168 11169 if (UseAVX > 1) { 11170 bind(copy_16_loop); 11171 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit); 11172 vmovdqu(Address(dst, len, Address::times_2), tmp1); 11173 addptr(len, 16); 11174 jcc(Assembler::notZero, copy_16_loop); 11175 11176 bind(below_threshold); 11177 bind(copy_new_tail); 11178 if (UseAVX > 2) { 11179 movl(tmp2, len); 11180 } 11181 else { 11182 movl(len, tmp2); 11183 } 11184 andl(tmp2, 0x00000007); 11185 andl(len, 0xFFFFFFF8); 11186 jccb(Assembler::zero, copy_tail); 11187 11188 pmovzxbw(tmp1, Address(src, 0)); 11189 movdqu(Address(dst, 0), tmp1); 11190 addptr(src, 8); 11191 addptr(dst, 2 * 8); 11192 11193 jmp(copy_tail, true); 11194 } 11195 11196 // inflate 8 chars per iter 11197 bind(copy_8_loop); 11198 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 11199 movdqu(Address(dst, len, Address::times_2), tmp1); 11200 addptr(len, 8); 11201 jcc(Assembler::notZero, copy_8_loop); 11202 11203 bind(copy_tail); 11204 movl(len, tmp2); 11205 11206 cmpl(len, 4); 11207 jccb(Assembler::less, copy_bytes); 11208 11209 movdl(tmp1, Address(src, 0)); // load 4 byte chars 11210 pmovzxbw(tmp1, tmp1); 11211 movq(Address(dst, 0), tmp1); 11212 subptr(len, 4); 11213 addptr(src, 4); 11214 addptr(dst, 8); 11215 11216 bind(copy_bytes); 11217 } 11218 testl(len, len); 11219 jccb(Assembler::zero, done); 11220 lea(src, Address(src, len, Address::times_1)); 11221 lea(dst, Address(dst, len, Address::times_2)); 11222 negptr(len); 11223 11224 // inflate 1 char per iter 11225 bind(copy_chars_loop); 11226 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 11227 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 11228 increment(len); 11229 jcc(Assembler::notZero, copy_chars_loop); 11230 11231 bind(done); 11232 } 11233 11234 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 11235 switch (cond) { 11236 // Note some conditions are synonyms for others 11237 case Assembler::zero: return Assembler::notZero; 11238 case Assembler::notZero: return Assembler::zero; 11239 case Assembler::less: return Assembler::greaterEqual; 11240 case Assembler::lessEqual: return Assembler::greater; 11241 case Assembler::greater: return Assembler::lessEqual; 11242 case Assembler::greaterEqual: return Assembler::less; 11243 case Assembler::below: return Assembler::aboveEqual; 11244 case Assembler::belowEqual: return Assembler::above; 11245 case Assembler::above: return Assembler::belowEqual; 11246 case Assembler::aboveEqual: return Assembler::below; 11247 case Assembler::overflow: return Assembler::noOverflow; 11248 case Assembler::noOverflow: return Assembler::overflow; 11249 case Assembler::negative: return Assembler::positive; 11250 case Assembler::positive: return Assembler::negative; 11251 case Assembler::parity: return Assembler::noParity; 11252 case Assembler::noParity: return Assembler::parity; 11253 } 11254 ShouldNotReachHere(); return Assembler::overflow; 11255 } 11256 11257 SkipIfEqual::SkipIfEqual( 11258 MacroAssembler* masm, const bool* flag_addr, bool value) { 11259 _masm = masm; 11260 _masm->cmp8(ExternalAddress((address)flag_addr), value); 11261 _masm->jcc(Assembler::equal, _label); 11262 } 11263 11264 SkipIfEqual::~SkipIfEqual() { 11265 _masm->bind(_label); 11266 } 11267 11268 // 32-bit Windows has its own fast-path implementation 11269 // of get_thread 11270 #if !defined(WIN32) || defined(_LP64) 11271 11272 // This is simply a call to Thread::current() 11273 void MacroAssembler::get_thread(Register thread) { 11274 if (thread != rax) { 11275 push(rax); 11276 } 11277 LP64_ONLY(push(rdi);) 11278 LP64_ONLY(push(rsi);) 11279 push(rdx); 11280 push(rcx); 11281 #ifdef _LP64 11282 push(r8); 11283 push(r9); 11284 push(r10); 11285 push(r11); 11286 #endif 11287 11288 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 11289 11290 #ifdef _LP64 11291 pop(r11); 11292 pop(r10); 11293 pop(r9); 11294 pop(r8); 11295 #endif 11296 pop(rcx); 11297 pop(rdx); 11298 LP64_ONLY(pop(rsi);) 11299 LP64_ONLY(pop(rdi);) 11300 if (thread != rax) { 11301 mov(thread, rax); 11302 pop(rax); 11303 } 11304 } 11305 11306 #endif 11307 11308 void MacroAssembler::save_vector_registers() { 11309 int num_xmm_regs = LP64_ONLY(16) NOT_LP64(8); 11310 if (UseAVX > 2) { 11311 num_xmm_regs = LP64_ONLY(32) NOT_LP64(8); 11312 } 11313 11314 if (UseSSE == 1) { 11315 subptr(rsp, sizeof(jdouble)*8); 11316 for (int n = 0; n < 8; n++) { 11317 movflt(Address(rsp, n*sizeof(jdouble)), as_XMMRegister(n)); 11318 } 11319 } else if (UseSSE >= 2) { 11320 if (UseAVX > 2) { 11321 push(rbx); 11322 movl(rbx, 0xffff); 11323 kmovwl(k1, rbx); 11324 pop(rbx); 11325 } 11326 #ifdef COMPILER2 11327 if (MaxVectorSize > 16) { 11328 if(UseAVX > 2) { 11329 // Save upper half of ZMM registers 11330 subptr(rsp, 32*num_xmm_regs); 11331 for (int n = 0; n < num_xmm_regs; n++) { 11332 vextractf64x4_high(Address(rsp, n*32), as_XMMRegister(n)); 11333 } 11334 } 11335 assert(UseAVX > 0, "256 bit vectors are supported only with AVX"); 11336 // Save upper half of YMM registers 11337 subptr(rsp, 16*num_xmm_regs); 11338 for (int n = 0; n < num_xmm_regs; n++) { 11339 vextractf128_high(Address(rsp, n*16), as_XMMRegister(n)); 11340 } 11341 } 11342 #endif 11343 // Save whole 128bit (16 bytes) XMM registers 11344 subptr(rsp, 16*num_xmm_regs); 11345 #ifdef _LP64 11346 if (VM_Version::supports_evex()) { 11347 for (int n = 0; n < num_xmm_regs; n++) { 11348 vextractf32x4(Address(rsp, n*16), as_XMMRegister(n), 0); 11349 } 11350 } else { 11351 for (int n = 0; n < num_xmm_regs; n++) { 11352 movdqu(Address(rsp, n*16), as_XMMRegister(n)); 11353 } 11354 } 11355 #else 11356 for (int n = 0; n < num_xmm_regs; n++) { 11357 movdqu(Address(rsp, n*16), as_XMMRegister(n)); 11358 } 11359 #endif 11360 } 11361 } 11362 11363 void MacroAssembler::restore_vector_registers() { 11364 int num_xmm_regs = LP64_ONLY(16) NOT_LP64(8); 11365 if (UseAVX > 2) { 11366 num_xmm_regs = LP64_ONLY(32) NOT_LP64(8); 11367 } 11368 if (UseSSE == 1) { 11369 for (int n = 0; n < 8; n++) { 11370 movflt(as_XMMRegister(n), Address(rsp, n*sizeof(jdouble))); 11371 } 11372 addptr(rsp, sizeof(jdouble)*8); 11373 } else if (UseSSE >= 2) { 11374 // Restore whole 128bit (16 bytes) XMM registers 11375 #ifdef _LP64 11376 if (VM_Version::supports_evex()) { 11377 for (int n = 0; n < num_xmm_regs; n++) { 11378 vinsertf32x4(as_XMMRegister(n), as_XMMRegister(n), Address(rsp, n*16), 0); 11379 } 11380 } else { 11381 for (int n = 0; n < num_xmm_regs; n++) { 11382 movdqu(as_XMMRegister(n), Address(rsp, n*16)); 11383 } 11384 } 11385 #else 11386 for (int n = 0; n < num_xmm_regs; n++) { 11387 movdqu(as_XMMRegister(n), Address(rsp, n*16)); 11388 } 11389 #endif 11390 addptr(rsp, 16*num_xmm_regs); 11391 11392 #ifdef COMPILER2 11393 if (MaxVectorSize > 16) { 11394 // Restore upper half of YMM registers. 11395 for (int n = 0; n < num_xmm_regs; n++) { 11396 vinsertf128_high(as_XMMRegister(n), Address(rsp, n*16)); 11397 } 11398 addptr(rsp, 16*num_xmm_regs); 11399 if(UseAVX > 2) { 11400 for (int n = 0; n < num_xmm_regs; n++) { 11401 vinsertf64x4_high(as_XMMRegister(n), Address(rsp, n*32)); 11402 } 11403 addptr(rsp, 32*num_xmm_regs); 11404 } 11405 } 11406 #endif 11407 } 11408 }