1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
75 // The implementation is only non-empty for the InterpreterMacroAssembler,
76 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
77 virtual void check_and_handle_popframe(Register java_thread);
78 virtual void check_and_handle_earlyret(Register java_thread);
79
80 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
81
82 // helpers for FPU flag access
83 // tmp is a temporary register, if none is available use noreg
84 void save_rax (Register tmp);
85 void restore_rax(Register tmp);
86
87 public:
88 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // special instructions for EVEX
160 void setvectmask(Register dst, Register src);
161 void restorevectmask();
162
163 // Support optimal SSE move instructions.
164 void movflt(XMMRegister dst, XMMRegister src) {
165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
166 else { movss (dst, src); return; }
167 }
168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
169 void movflt(XMMRegister dst, AddressLiteral src);
170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
171
172 void movdbl(XMMRegister dst, XMMRegister src) {
173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
174 else { movsd (dst, src); return; }
175 }
176
177 void movdbl(XMMRegister dst, AddressLiteral src);
178
179 void movdbl(XMMRegister dst, Address src) {
180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
181 else { movlpd(dst, src); return; }
182 }
183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
184
185 void incrementl(AddressLiteral dst);
186 void incrementl(ArrayAddress dst);
187
188 void incrementq(AddressLiteral dst);
189
190 // Alignment
191 void align(int modulus);
192 void align(int modulus, int target);
193
194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
195 void fat_nop();
196
197 // Stack frame creation/removal
198 void enter();
199 void leave();
200
201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
202 // The pointer will be loaded into the thread register.
203 void get_thread(Register thread);
204
205
206 // Support for VM calls
207 //
208 // It is imperative that all calls into the VM are handled via the call_VM macros.
209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
211
212
213 void call_VM(Register oop_result,
214 address entry_point,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2, Register arg_3,
227 bool check_exceptions = true);
228
229 // Overloadings with last_Java_sp
230 void call_VM(Register oop_result,
231 Register last_java_sp,
232 address entry_point,
233 int number_of_arguments = 0,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 Register arg_1, bool
239 check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2, Register arg_3,
249 bool check_exceptions = true);
250
251 void get_vm_result (Register oop_result, Register thread);
252 void get_vm_result_2(Register metadata_result, Register thread);
253
254 // These always tightly bind to MacroAssembler::call_VM_base
255 // bypassing the virtual implementation
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
261
262 void call_VM_leaf0(address entry_point);
263 void call_VM_leaf(address entry_point,
264 int number_of_arguments = 0);
265 void call_VM_leaf(address entry_point,
266 Register arg_1);
267 void call_VM_leaf(address entry_point,
268 Register arg_1, Register arg_2);
269 void call_VM_leaf(address entry_point,
270 Register arg_1, Register arg_2, Register arg_3);
271
272 // These always tightly bind to MacroAssembler::call_VM_leaf_base
273 // bypassing the virtual implementation
274 void super_call_VM_leaf(address entry_point);
275 void super_call_VM_leaf(address entry_point, Register arg_1);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
279
280 // last Java Frame (fills frame anchor)
281 void set_last_Java_frame(Register thread,
282 Register last_java_sp,
283 Register last_java_fp,
284 address last_java_pc);
285
286 // thread in the default location (r15_thread on 64bit)
287 void set_last_Java_frame(Register last_java_sp,
288 Register last_java_fp,
289 address last_java_pc);
290
291 void reset_last_Java_frame(Register thread, bool clear_fp);
292
293 // thread in the default location (r15_thread on 64bit)
294 void reset_last_Java_frame(bool clear_fp);
295
296 // Stores
297 void store_check(Register obj); // store check for obj - register is destroyed afterwards
298 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
299
300 #if INCLUDE_ALL_GCS
301
302 void g1_write_barrier_pre(Register obj,
303 Register pre_val,
304 Register thread,
305 Register tmp,
306 bool tosca_live,
307 bool expand_call);
308
309 void g1_write_barrier_post(Register store_addr,
310 Register new_val,
311 Register thread,
312 Register tmp,
313 Register tmp2);
314
315 #endif // INCLUDE_ALL_GCS
316
317 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
318 void c2bool(Register x);
319
320 // C++ bool manipulation
321
322 void movbool(Register dst, Address src);
323 void movbool(Address dst, bool boolconst);
324 void movbool(Address dst, Register src);
325 void testbool(Register dst);
326
327 void load_mirror(Register mirror, Register method);
328
329 // oop manipulations
330 void load_klass(Register dst, Register src);
331 void store_klass(Register dst, Register src);
332
333 void load_heap_oop(Register dst, Address src);
334 void load_heap_oop_not_null(Register dst, Address src);
335 void store_heap_oop(Address dst, Register src);
336 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
337
338 // Used for storing NULL. All other oop constants should be
339 // stored using routines that take a jobject.
340 void store_heap_oop_null(Address dst);
341
342 void load_prototype_header(Register dst, Register src);
343
344 #ifdef _LP64
345 void store_klass_gap(Register dst, Register src);
346
347 // This dummy is to prevent a call to store_heap_oop from
348 // converting a zero (like NULL) into a Register by giving
349 // the compiler two choices it can't resolve
350
351 void store_heap_oop(Address dst, void* dummy);
352
353 void encode_heap_oop(Register r);
354 void decode_heap_oop(Register r);
355 void encode_heap_oop_not_null(Register r);
356 void decode_heap_oop_not_null(Register r);
357 void encode_heap_oop_not_null(Register dst, Register src);
358 void decode_heap_oop_not_null(Register dst, Register src);
359
360 void set_narrow_oop(Register dst, jobject obj);
361 void set_narrow_oop(Address dst, jobject obj);
362 void cmp_narrow_oop(Register dst, jobject obj);
363 void cmp_narrow_oop(Address dst, jobject obj);
364
365 void encode_klass_not_null(Register r);
366 void decode_klass_not_null(Register r);
367 void encode_klass_not_null(Register dst, Register src);
368 void decode_klass_not_null(Register dst, Register src);
369 void set_narrow_klass(Register dst, Klass* k);
370 void set_narrow_klass(Address dst, Klass* k);
371 void cmp_narrow_klass(Register dst, Klass* k);
372 void cmp_narrow_klass(Address dst, Klass* k);
373
374 // Returns the byte size of the instructions generated by decode_klass_not_null()
375 // when compressed klass pointers are being used.
376 static int instr_size_for_decode_klass_not_null();
377
378 // if heap base register is used - reinit it with the correct value
379 void reinit_heapbase();
380
381 DEBUG_ONLY(void verify_heapbase(const char* msg);)
382
383 #endif // _LP64
384
385 // Int division/remainder for Java
386 // (as idivl, but checks for special case as described in JVM spec.)
387 // returns idivl instruction offset for implicit exception handling
388 int corrected_idivl(Register reg);
389
390 // Long division/remainder for Java
391 // (as idivq, but checks for special case as described in JVM spec.)
392 // returns idivq instruction offset for implicit exception handling
393 int corrected_idivq(Register reg);
394
395 void int3();
396
397 // Long operation macros for a 32bit cpu
398 // Long negation for Java
399 void lneg(Register hi, Register lo);
400
401 // Long multiplication for Java
402 // (destroys contents of eax, ebx, ecx and edx)
403 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
404
405 // Long shifts for Java
406 // (semantics as described in JVM spec.)
407 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
408 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
409
410 // Long compare for Java
411 // (semantics as described in JVM spec.)
412 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
413
414
415 // misc
416
417 // Sign extension
418 void sign_extend_short(Register reg);
419 void sign_extend_byte(Register reg);
420
421 // Division by power of 2, rounding towards 0
422 void division_with_shift(Register reg, int shift_value);
423
424 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
425 //
426 // CF (corresponds to C0) if x < y
427 // PF (corresponds to C2) if unordered
428 // ZF (corresponds to C3) if x = y
429 //
430 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
431 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
432 void fcmp(Register tmp);
433 // Variant of the above which allows y to be further down the stack
434 // and which only pops x and y if specified. If pop_right is
435 // specified then pop_left must also be specified.
436 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
437
438 // Floating-point comparison for Java
439 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
440 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
441 // (semantics as described in JVM spec.)
442 void fcmp2int(Register dst, bool unordered_is_less);
443 // Variant of the above which allows y to be further down the stack
444 // and which only pops x and y if specified. If pop_right is
445 // specified then pop_left must also be specified.
446 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
447
448 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
449 // tmp is a temporary register, if none is available use noreg
450 void fremr(Register tmp);
451
452
453 // same as fcmp2int, but using SSE2
454 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
455 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
456
457 // branch to L if FPU flag C2 is set/not set
458 // tmp is a temporary register, if none is available use noreg
459 void jC2 (Register tmp, Label& L);
460 void jnC2(Register tmp, Label& L);
461
462 // Pop ST (ffree & fincstp combined)
463 void fpop();
464
465 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
466 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
467 void load_float(Address src);
468
469 // Store float value to 'address'. If UseSSE >= 1, the value is stored
470 // from register xmm0. Otherwise, the value is stored from the FPU stack.
471 void store_float(Address dst);
472
473 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
474 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
475 void load_double(Address src);
476
477 // Store double value to 'address'. If UseSSE >= 2, the value is stored
478 // from register xmm0. Otherwise, the value is stored from the FPU stack.
479 void store_double(Address dst);
480
481 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
482 void push_fTOS();
483
484 // pops double TOS element from CPU stack and pushes on FPU stack
485 void pop_fTOS();
486
487 void empty_FPU_stack();
488
489 void push_IU_state();
490 void pop_IU_state();
491
492 void push_FPU_state();
493 void pop_FPU_state();
494
495 void push_CPU_state();
496 void pop_CPU_state();
497
498 // Round up to a power of two
499 void round_to(Register reg, int modulus);
500
501 // Callee saved registers handling
502 void push_callee_saved_registers();
503 void pop_callee_saved_registers();
504
505 // allocation
506 void eden_allocate(
507 Register obj, // result: pointer to object after successful allocation
508 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
509 int con_size_in_bytes, // object size in bytes if known at compile time
510 Register t1, // temp register
511 Label& slow_case // continuation point if fast allocation fails
512 );
513 void tlab_allocate(
514 Register obj, // result: pointer to object after successful allocation
515 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
516 int con_size_in_bytes, // object size in bytes if known at compile time
517 Register t1, // temp register
518 Register t2, // temp register
519 Label& slow_case // continuation point if fast allocation fails
520 );
521 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
522 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
523
524 void incr_allocated_bytes(Register thread,
525 Register var_size_in_bytes, int con_size_in_bytes,
526 Register t1 = noreg);
527
528 // interface method calling
529 void lookup_interface_method(Register recv_klass,
530 Register intf_klass,
531 RegisterOrConstant itable_index,
532 Register method_result,
533 Register scan_temp,
534 Label& no_such_interface);
535
536 // virtual method calling
537 void lookup_virtual_method(Register recv_klass,
538 RegisterOrConstant vtable_index,
539 Register method_result);
540
541 // Test sub_klass against super_klass, with fast and slow paths.
542
543 // The fast path produces a tri-state answer: yes / no / maybe-slow.
544 // One of the three labels can be NULL, meaning take the fall-through.
545 // If super_check_offset is -1, the value is loaded up from super_klass.
546 // No registers are killed, except temp_reg.
547 void check_klass_subtype_fast_path(Register sub_klass,
548 Register super_klass,
549 Register temp_reg,
550 Label* L_success,
551 Label* L_failure,
552 Label* L_slow_path,
553 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
554
555 // The rest of the type check; must be wired to a corresponding fast path.
556 // It does not repeat the fast path logic, so don't use it standalone.
557 // The temp_reg and temp2_reg can be noreg, if no temps are available.
558 // Updates the sub's secondary super cache as necessary.
559 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
560 void check_klass_subtype_slow_path(Register sub_klass,
561 Register super_klass,
562 Register temp_reg,
563 Register temp2_reg,
564 Label* L_success,
565 Label* L_failure,
566 bool set_cond_codes = false);
567
568 // Simplified, combined version, good for typical uses.
569 // Falls through on failure.
570 void check_klass_subtype(Register sub_klass,
571 Register super_klass,
572 Register temp_reg,
573 Label& L_success);
574
575 // method handles (JSR 292)
576 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
577
578 //----
579 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
580
581 // Debugging
582
583 // only if +VerifyOops
584 // TODO: Make these macros with file and line like sparc version!
585 void verify_oop(Register reg, const char* s = "broken oop");
586 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
587
588 // TODO: verify method and klass metadata (compare against vptr?)
589 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
590 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
591
592 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
593 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
594
595 // only if +VerifyFPU
596 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
597
598 // Verify or restore cpu control state after JNI call
599 void restore_cpu_control_state_after_jni();
600
601 // prints msg, dumps registers and stops execution
602 void stop(const char* msg);
603
604 // prints msg and continues
605 void warn(const char* msg);
606
607 // dumps registers and other state
608 void print_state();
609
610 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
611 static void debug64(char* msg, int64_t pc, int64_t regs[]);
612 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
613 static void print_state64(int64_t pc, int64_t regs[]);
614
615 void os_breakpoint();
616
617 void untested() { stop("untested"); }
618
619 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
620
621 void should_not_reach_here() { stop("should not reach here"); }
622
623 void print_CPU_state();
624
625 // Stack overflow checking
626 void bang_stack_with_offset(int offset) {
627 // stack grows down, caller passes positive offset
628 assert(offset > 0, "must bang with negative offset");
629 movl(Address(rsp, (-offset)), rax);
630 }
631
632 // Writes to stack successive pages until offset reached to check for
633 // stack overflow + shadow pages. Also, clobbers tmp
634 void bang_stack_size(Register size, Register tmp);
635
636 // Check for reserved stack access in method being exited (for JIT)
637 void reserved_stack_check();
638
639 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
640 Register tmp,
641 int offset);
642
643 // Support for serializing memory accesses between threads
644 void serialize_memory(Register thread, Register tmp);
645
646 void verify_tlab();
647
648 // Biased locking support
649 // lock_reg and obj_reg must be loaded up with the appropriate values.
650 // swap_reg must be rax, and is killed.
651 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
652 // be killed; if not supplied, push/pop will be used internally to
653 // allocate a temporary (inefficient, avoid if possible).
654 // Optional slow case is for implementations (interpreter and C1) which branch to
655 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
656 // Returns offset of first potentially-faulting instruction for null
657 // check info (currently consumed only by C1). If
658 // swap_reg_contains_mark is true then returns -1 as it is assumed
659 // the calling code has already passed any potential faults.
660 int biased_locking_enter(Register lock_reg, Register obj_reg,
661 Register swap_reg, Register tmp_reg,
662 bool swap_reg_contains_mark,
663 Label& done, Label* slow_case = NULL,
664 BiasedLockingCounters* counters = NULL);
665 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
666 #ifdef COMPILER2
667 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
668 // See full desription in macroAssembler_x86.cpp.
669 void fast_lock(Register obj, Register box, Register tmp,
670 Register scr, Register cx1, Register cx2,
671 BiasedLockingCounters* counters,
672 RTMLockingCounters* rtm_counters,
673 RTMLockingCounters* stack_rtm_counters,
674 Metadata* method_data,
675 bool use_rtm, bool profile_rtm);
676 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
677 #if INCLUDE_RTM_OPT
678 void rtm_counters_update(Register abort_status, Register rtm_counters);
679 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
680 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
681 RTMLockingCounters* rtm_counters,
682 Metadata* method_data);
683 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
684 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
685 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
686 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
687 void rtm_stack_locking(Register obj, Register tmp, Register scr,
688 Register retry_on_abort_count,
689 RTMLockingCounters* stack_rtm_counters,
690 Metadata* method_data, bool profile_rtm,
691 Label& DONE_LABEL, Label& IsInflated);
692 void rtm_inflated_locking(Register obj, Register box, Register tmp,
693 Register scr, Register retry_on_busy_count,
694 Register retry_on_abort_count,
695 RTMLockingCounters* rtm_counters,
696 Metadata* method_data, bool profile_rtm,
697 Label& DONE_LABEL);
698 #endif
699 #endif
700
701 Condition negate_condition(Condition cond);
702
703 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
704 // operands. In general the names are modified to avoid hiding the instruction in Assembler
705 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
706 // here in MacroAssembler. The major exception to this rule is call
707
708 // Arithmetics
709
710
711 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
712 void addptr(Address dst, Register src);
713
714 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
715 void addptr(Register dst, int32_t src);
716 void addptr(Register dst, Register src);
717 void addptr(Register dst, RegisterOrConstant src) {
718 if (src.is_constant()) addptr(dst, (int) src.as_constant());
719 else addptr(dst, src.as_register());
720 }
721
722 void andptr(Register dst, int32_t src);
723 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
724
725 void cmp8(AddressLiteral src1, int imm);
726
727 // renamed to drag out the casting of address to int32_t/intptr_t
728 void cmp32(Register src1, int32_t imm);
729
730 void cmp32(AddressLiteral src1, int32_t imm);
731 // compare reg - mem, or reg - &mem
732 void cmp32(Register src1, AddressLiteral src2);
733
734 void cmp32(Register src1, Address src2);
735
736 #ifndef _LP64
737 void cmpklass(Address dst, Metadata* obj);
738 void cmpklass(Register dst, Metadata* obj);
739 void cmpoop(Address dst, jobject obj);
740 void cmpoop(Register dst, jobject obj);
741 #endif // _LP64
742
743 // NOTE src2 must be the lval. This is NOT an mem-mem compare
744 void cmpptr(Address src1, AddressLiteral src2);
745
746 void cmpptr(Register src1, AddressLiteral src2);
747
748 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
749 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
750 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
751
752 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
753 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
754
755 // cmp64 to avoild hiding cmpq
756 void cmp64(Register src1, AddressLiteral src);
757
758 void cmpxchgptr(Register reg, Address adr);
759
760 // Special Shenandoah CAS implementation that handles false negatives
761 // due to concurrent evacuation.
762 void cmpxchg_oop_shenandoah(Register res, Address addr, Register oldval, Register newval,
763 bool exchange,
764 Register tmp1, Register tmp2);
765
766 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
767
768
769 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
770 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
771
772
773 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
774
775 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
776
777 void shlptr(Register dst, int32_t shift);
778 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
779
780 void shrptr(Register dst, int32_t shift);
781 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
782
783 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
784 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
785
786 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
787
788 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
789 void subptr(Register dst, int32_t src);
790 // Force generation of a 4 byte immediate value even if it fits into 8bit
791 void subptr_imm32(Register dst, int32_t src);
792 void subptr(Register dst, Register src);
793 void subptr(Register dst, RegisterOrConstant src) {
794 if (src.is_constant()) subptr(dst, (int) src.as_constant());
795 else subptr(dst, src.as_register());
796 }
797
798 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
799 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
800
801 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
802 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
803
804 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
805
806
807
808 // Helper functions for statistics gathering.
809 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
810 void cond_inc32(Condition cond, AddressLiteral counter_addr);
811 // Unconditional atomic increment.
812 void atomic_incl(Address counter_addr);
813 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
814 #ifdef _LP64
815 void atomic_incq(Address counter_addr);
816 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
817 #endif
818 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
819 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
820
821 void lea(Register dst, AddressLiteral adr);
822 void lea(Address dst, AddressLiteral adr);
823 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
824
825 void leal32(Register dst, Address src) { leal(dst, src); }
826
827 // Import other testl() methods from the parent class or else
828 // they will be hidden by the following overriding declaration.
829 using Assembler::testl;
830 void testl(Register dst, AddressLiteral src);
831
832 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
833 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
834 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
835 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
836
837 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
838 void testptr(Register src1, Register src2);
839
840 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
841 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
842
843 // Calls
844
845 void call(Label& L, relocInfo::relocType rtype);
846 void call(Register entry);
847
848 // NOTE: this call transfers to the effective address of entry NOT
849 // the address contained by entry. This is because this is more natural
850 // for jumps/calls.
851 void call(AddressLiteral entry);
852
853 // Emit the CompiledIC call idiom
854 void ic_call(address entry, jint method_index = 0);
855
856 // Jumps
857
858 // NOTE: these jumps tranfer to the effective address of dst NOT
859 // the address contained by dst. This is because this is more natural
860 // for jumps/calls.
861 void jump(AddressLiteral dst);
862 void jump_cc(Condition cc, AddressLiteral dst);
863
864 // 32bit can do a case table jump in one instruction but we no longer allow the base
865 // to be installed in the Address class. This jump will tranfers to the address
866 // contained in the location described by entry (not the address of entry)
867 void jump(ArrayAddress entry);
868
869 // Floating
870
871 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
872 void andpd(XMMRegister dst, AddressLiteral src);
873 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
874
875 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
876 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
877 void andps(XMMRegister dst, AddressLiteral src);
878
879 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
880 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
881 void comiss(XMMRegister dst, AddressLiteral src);
882
883 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
884 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
885 void comisd(XMMRegister dst, AddressLiteral src);
886
887 void fadd_s(Address src) { Assembler::fadd_s(src); }
888 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
889
890 void fldcw(Address src) { Assembler::fldcw(src); }
891 void fldcw(AddressLiteral src);
892
893 void fld_s(int index) { Assembler::fld_s(index); }
894 void fld_s(Address src) { Assembler::fld_s(src); }
895 void fld_s(AddressLiteral src);
896
897 void fld_d(Address src) { Assembler::fld_d(src); }
898 void fld_d(AddressLiteral src);
899
900 void fld_x(Address src) { Assembler::fld_x(src); }
901 void fld_x(AddressLiteral src);
902
903 void fmul_s(Address src) { Assembler::fmul_s(src); }
904 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
905
906 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
907 void ldmxcsr(AddressLiteral src);
908
909 #ifdef _LP64
910 private:
911 void sha256_AVX2_one_round_compute(
912 Register reg_old_h,
913 Register reg_a,
914 Register reg_b,
915 Register reg_c,
916 Register reg_d,
917 Register reg_e,
918 Register reg_f,
919 Register reg_g,
920 Register reg_h,
921 int iter);
922 void sha256_AVX2_four_rounds_compute_first(int start);
923 void sha256_AVX2_four_rounds_compute_last(int start);
924 void sha256_AVX2_one_round_and_sched(
925 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
926 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
927 XMMRegister xmm_2, /* ymm6 */
928 XMMRegister xmm_3, /* ymm7 */
929 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
930 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
931 Register reg_c, /* edi */
932 Register reg_d, /* esi */
933 Register reg_e, /* r8d */
934 Register reg_f, /* r9d */
935 Register reg_g, /* r10d */
936 Register reg_h, /* r11d */
937 int iter);
938
939 void addm(int disp, Register r1, Register r2);
940
941 public:
942 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
943 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
944 Register buf, Register state, Register ofs, Register limit, Register rsp,
945 bool multi_block, XMMRegister shuf_mask);
946 #endif
947
948 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
949 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
950 Register buf, Register state, Register ofs, Register limit, Register rsp,
951 bool multi_block);
952
953 #ifdef _LP64
954 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
955 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
956 Register buf, Register state, Register ofs, Register limit, Register rsp,
957 bool multi_block, XMMRegister shuf_mask);
958 #else
959 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
960 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
961 Register buf, Register state, Register ofs, Register limit, Register rsp,
962 bool multi_block);
963 #endif
964
965 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
966 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
967 Register rax, Register rcx, Register rdx, Register tmp);
968
969 #ifdef _LP64
970 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
971 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
972 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
973
974 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
975 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
976 Register rax, Register rcx, Register rdx, Register r11);
977
978 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
979 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
980 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
981
982 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
983 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
984 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
985 Register tmp3, Register tmp4);
986
987 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
988 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
989 Register rax, Register rcx, Register rdx, Register tmp1,
990 Register tmp2, Register tmp3, Register tmp4);
991 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
992 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
993 Register rax, Register rcx, Register rdx, Register tmp1,
994 Register tmp2, Register tmp3, Register tmp4);
995 #else
996 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
997 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
998 Register rax, Register rcx, Register rdx, Register tmp1);
999
1000 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1001 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1002 Register rax, Register rcx, Register rdx, Register tmp);
1003
1004 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1005 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1006 Register rdx, Register tmp);
1007
1008 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1009 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1010 Register rax, Register rbx, Register rdx);
1011
1012 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1013 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1014 Register rax, Register rcx, Register rdx, Register tmp);
1015
1016 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1017 Register edx, Register ebx, Register esi, Register edi,
1018 Register ebp, Register esp);
1019
1020 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1021 Register esi, Register edi, Register ebp, Register esp);
1022
1023 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1024 Register edx, Register ebx, Register esi, Register edi,
1025 Register ebp, Register esp);
1026
1027 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1028 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1029 Register rax, Register rcx, Register rdx, Register tmp);
1030 #endif
1031
1032 void increase_precision();
1033 void restore_precision();
1034
1035 private:
1036
1037 // these are private because users should be doing movflt/movdbl
1038
1039 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1040 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1041 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1042 void movss(XMMRegister dst, AddressLiteral src);
1043
1044 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1045 void movlpd(XMMRegister dst, AddressLiteral src);
1046
1047 public:
1048
1049 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1050 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1051 void addsd(XMMRegister dst, AddressLiteral src);
1052
1053 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1054 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1055 void addss(XMMRegister dst, AddressLiteral src);
1056
1057 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1058 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1059 void addpd(XMMRegister dst, AddressLiteral src);
1060
1061 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1062 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1063 void divsd(XMMRegister dst, AddressLiteral src);
1064
1065 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1066 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1067 void divss(XMMRegister dst, AddressLiteral src);
1068
1069 // Move Unaligned Double Quadword
1070 void movdqu(Address dst, XMMRegister src);
1071 void movdqu(XMMRegister dst, Address src);
1072 void movdqu(XMMRegister dst, XMMRegister src);
1073 void movdqu(XMMRegister dst, AddressLiteral src);
1074 // AVX Unaligned forms
1075 void vmovdqu(Address dst, XMMRegister src);
1076 void vmovdqu(XMMRegister dst, Address src);
1077 void vmovdqu(XMMRegister dst, XMMRegister src);
1078 void vmovdqu(XMMRegister dst, AddressLiteral src);
1079
1080 // Move Aligned Double Quadword
1081 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1082 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1083 void movdqa(XMMRegister dst, AddressLiteral src);
1084
1085 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1086 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1087 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1088 void movsd(XMMRegister dst, AddressLiteral src);
1089
1090 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1091 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1092 void mulpd(XMMRegister dst, AddressLiteral src);
1093
1094 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1095 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1096 void mulsd(XMMRegister dst, AddressLiteral src);
1097
1098 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1099 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1100 void mulss(XMMRegister dst, AddressLiteral src);
1101
1102 // Carry-Less Multiplication Quadword
1103 void pclmulldq(XMMRegister dst, XMMRegister src) {
1104 // 0x00 - multiply lower 64 bits [0:63]
1105 Assembler::pclmulqdq(dst, src, 0x00);
1106 }
1107 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1108 // 0x11 - multiply upper 64 bits [64:127]
1109 Assembler::pclmulqdq(dst, src, 0x11);
1110 }
1111
1112 void pcmpeqb(XMMRegister dst, XMMRegister src);
1113 void pcmpeqw(XMMRegister dst, XMMRegister src);
1114
1115 void pcmpestri(XMMRegister dst, Address src, int imm8);
1116 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1117
1118 void pmovzxbw(XMMRegister dst, XMMRegister src);
1119 void pmovzxbw(XMMRegister dst, Address src);
1120
1121 void pmovmskb(Register dst, XMMRegister src);
1122
1123 void ptest(XMMRegister dst, XMMRegister src);
1124
1125 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1126 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1127 void sqrtsd(XMMRegister dst, AddressLiteral src);
1128
1129 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1130 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1131 void sqrtss(XMMRegister dst, AddressLiteral src);
1132
1133 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1134 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1135 void subsd(XMMRegister dst, AddressLiteral src);
1136
1137 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1138 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1139 void subss(XMMRegister dst, AddressLiteral src);
1140
1141 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1142 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1143 void ucomiss(XMMRegister dst, AddressLiteral src);
1144
1145 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1146 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1147 void ucomisd(XMMRegister dst, AddressLiteral src);
1148
1149 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1150 void xorpd(XMMRegister dst, XMMRegister src);
1151 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1152 void xorpd(XMMRegister dst, AddressLiteral src);
1153
1154 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1155 void xorps(XMMRegister dst, XMMRegister src);
1156 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1157 void xorps(XMMRegister dst, AddressLiteral src);
1158
1159 // Shuffle Bytes
1160 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1161 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1162 void pshufb(XMMRegister dst, AddressLiteral src);
1163 // AVX 3-operands instructions
1164
1165 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1166 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1167 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1168
1169 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1170 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1171 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1172
1173 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1174 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1175
1176 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1177 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1178
1179 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1180 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1181
1182 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1183
1184 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1185 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1186
1187 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1188 void vpmovmskb(Register dst, XMMRegister src);
1189
1190 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1191 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1192
1193 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1194 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1195
1196 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1197 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1198
1199 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1200 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1201
1202 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1203 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1204
1205 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1206 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1207
1208 void vptest(XMMRegister dst, XMMRegister src);
1209
1210 void punpcklbw(XMMRegister dst, XMMRegister src);
1211 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1212
1213 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1214 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1215
1216 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1217 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1218 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1219
1220 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1221 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1222 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1223
1224 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1225 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1226 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1227
1228 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1229 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1230 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1231
1232 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1233 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1234 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1235
1236 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1237 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1238 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1239
1240 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1241 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1242 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1243
1244 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1245 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1246 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1247
1248 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1249 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1250
1251 // AVX Vector instructions
1252
1253 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1254 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1255 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1256
1257 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1258 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1259 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1260
1261 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1262 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1263 Assembler::vpxor(dst, nds, src, vector_len);
1264 else
1265 Assembler::vxorpd(dst, nds, src, vector_len);
1266 }
1267 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1268 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1269 Assembler::vpxor(dst, nds, src, vector_len);
1270 else
1271 Assembler::vxorpd(dst, nds, src, vector_len);
1272 }
1273
1274 // Simple version for AVX2 256bit vectors
1275 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1276 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1277
1278 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1279 if (UseAVX > 2) {
1280 Assembler::vinserti32x4(dst, dst, src, imm8);
1281 } else if (UseAVX > 1) {
1282 // vinserti128 is available only in AVX2
1283 Assembler::vinserti128(dst, nds, src, imm8);
1284 } else {
1285 Assembler::vinsertf128(dst, nds, src, imm8);
1286 }
1287 }
1288
1289 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1290 if (UseAVX > 2) {
1291 Assembler::vinserti32x4(dst, dst, src, imm8);
1292 } else if (UseAVX > 1) {
1293 // vinserti128 is available only in AVX2
1294 Assembler::vinserti128(dst, nds, src, imm8);
1295 } else {
1296 Assembler::vinsertf128(dst, nds, src, imm8);
1297 }
1298 }
1299
1300 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1301 if (UseAVX > 2) {
1302 Assembler::vextracti32x4(dst, src, imm8);
1303 } else if (UseAVX > 1) {
1304 // vextracti128 is available only in AVX2
1305 Assembler::vextracti128(dst, src, imm8);
1306 } else {
1307 Assembler::vextractf128(dst, src, imm8);
1308 }
1309 }
1310
1311 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1312 if (UseAVX > 2) {
1313 Assembler::vextracti32x4(dst, src, imm8);
1314 } else if (UseAVX > 1) {
1315 // vextracti128 is available only in AVX2
1316 Assembler::vextracti128(dst, src, imm8);
1317 } else {
1318 Assembler::vextractf128(dst, src, imm8);
1319 }
1320 }
1321
1322 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1323 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1324 vinserti128(dst, dst, src, 1);
1325 }
1326 void vinserti128_high(XMMRegister dst, Address src) {
1327 vinserti128(dst, dst, src, 1);
1328 }
1329 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1330 vextracti128(dst, src, 1);
1331 }
1332 void vextracti128_high(Address dst, XMMRegister src) {
1333 vextracti128(dst, src, 1);
1334 }
1335
1336 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1337 if (UseAVX > 2) {
1338 Assembler::vinsertf32x4(dst, dst, src, 1);
1339 } else {
1340 Assembler::vinsertf128(dst, dst, src, 1);
1341 }
1342 }
1343
1344 void vinsertf128_high(XMMRegister dst, Address src) {
1345 if (UseAVX > 2) {
1346 Assembler::vinsertf32x4(dst, dst, src, 1);
1347 } else {
1348 Assembler::vinsertf128(dst, dst, src, 1);
1349 }
1350 }
1351
1352 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1353 if (UseAVX > 2) {
1354 Assembler::vextractf32x4(dst, src, 1);
1355 } else {
1356 Assembler::vextractf128(dst, src, 1);
1357 }
1358 }
1359
1360 void vextractf128_high(Address dst, XMMRegister src) {
1361 if (UseAVX > 2) {
1362 Assembler::vextractf32x4(dst, src, 1);
1363 } else {
1364 Assembler::vextractf128(dst, src, 1);
1365 }
1366 }
1367
1368 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1369 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1370 Assembler::vinserti64x4(dst, dst, src, 1);
1371 }
1372 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1373 Assembler::vinsertf64x4(dst, dst, src, 1);
1374 }
1375 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1376 Assembler::vextracti64x4(dst, src, 1);
1377 }
1378 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1379 Assembler::vextractf64x4(dst, src, 1);
1380 }
1381 void vextractf64x4_high(Address dst, XMMRegister src) {
1382 Assembler::vextractf64x4(dst, src, 1);
1383 }
1384 void vinsertf64x4_high(XMMRegister dst, Address src) {
1385 Assembler::vinsertf64x4(dst, dst, src, 1);
1386 }
1387
1388 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1389 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1390 vinserti128(dst, dst, src, 0);
1391 }
1392 void vinserti128_low(XMMRegister dst, Address src) {
1393 vinserti128(dst, dst, src, 0);
1394 }
1395 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1396 vextracti128(dst, src, 0);
1397 }
1398 void vextracti128_low(Address dst, XMMRegister src) {
1399 vextracti128(dst, src, 0);
1400 }
1401
1402 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1403 if (UseAVX > 2) {
1404 Assembler::vinsertf32x4(dst, dst, src, 0);
1405 } else {
1406 Assembler::vinsertf128(dst, dst, src, 0);
1407 }
1408 }
1409
1410 void vinsertf128_low(XMMRegister dst, Address src) {
1411 if (UseAVX > 2) {
1412 Assembler::vinsertf32x4(dst, dst, src, 0);
1413 } else {
1414 Assembler::vinsertf128(dst, dst, src, 0);
1415 }
1416 }
1417
1418 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1419 if (UseAVX > 2) {
1420 Assembler::vextractf32x4(dst, src, 0);
1421 } else {
1422 Assembler::vextractf128(dst, src, 0);
1423 }
1424 }
1425
1426 void vextractf128_low(Address dst, XMMRegister src) {
1427 if (UseAVX > 2) {
1428 Assembler::vextractf32x4(dst, src, 0);
1429 } else {
1430 Assembler::vextractf128(dst, src, 0);
1431 }
1432 }
1433
1434 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1435 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1436 Assembler::vinserti64x4(dst, dst, src, 0);
1437 }
1438 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1439 Assembler::vinsertf64x4(dst, dst, src, 0);
1440 }
1441 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1442 Assembler::vextracti64x4(dst, src, 0);
1443 }
1444 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1445 Assembler::vextractf64x4(dst, src, 0);
1446 }
1447 void vextractf64x4_low(Address dst, XMMRegister src) {
1448 Assembler::vextractf64x4(dst, src, 0);
1449 }
1450 void vinsertf64x4_low(XMMRegister dst, Address src) {
1451 Assembler::vinsertf64x4(dst, dst, src, 0);
1452 }
1453
1454 // Carry-Less Multiplication Quadword
1455 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1456 // 0x00 - multiply lower 64 bits [0:63]
1457 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1458 }
1459 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1460 // 0x11 - multiply upper 64 bits [64:127]
1461 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1462 }
1463
1464 // Data
1465
1466 void cmov32( Condition cc, Register dst, Address src);
1467 void cmov32( Condition cc, Register dst, Register src);
1468
1469 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1470
1471 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1472 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1473
1474 void movoop(Register dst, jobject obj);
1475 void movoop(Address dst, jobject obj);
1476
1477 void mov_metadata(Register dst, Metadata* obj);
1478 void mov_metadata(Address dst, Metadata* obj);
1479
1480 void movptr(ArrayAddress dst, Register src);
1481 // can this do an lea?
1482 void movptr(Register dst, ArrayAddress src);
1483
1484 void movptr(Register dst, Address src);
1485
1486 #ifdef _LP64
1487 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1488 #else
1489 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1490 #endif
1491
1492 void movptr(Register dst, intptr_t src);
1493 void movptr(Register dst, Register src);
1494 void movptr(Address dst, intptr_t src);
1495
1496 void movptr(Address dst, Register src);
1497
1498 void movptr(Register dst, RegisterOrConstant src) {
1499 if (src.is_constant()) movptr(dst, src.as_constant());
1500 else movptr(dst, src.as_register());
1501 }
1502
1503 #ifdef _LP64
1504 // Generally the next two are only used for moving NULL
1505 // Although there are situations in initializing the mark word where
1506 // they could be used. They are dangerous.
1507
1508 // They only exist on LP64 so that int32_t and intptr_t are not the same
1509 // and we have ambiguous declarations.
1510
1511 void movptr(Address dst, int32_t imm32);
1512 void movptr(Register dst, int32_t imm32);
1513 #endif // _LP64
1514
1515 // to avoid hiding movl
1516 void mov32(AddressLiteral dst, Register src);
1517 void mov32(Register dst, AddressLiteral src);
1518
1519 // to avoid hiding movb
1520 void movbyte(ArrayAddress dst, int src);
1521
1522 // Import other mov() methods from the parent class or else
1523 // they will be hidden by the following overriding declaration.
1524 using Assembler::movdl;
1525 using Assembler::movq;
1526 void movdl(XMMRegister dst, AddressLiteral src);
1527 void movq(XMMRegister dst, AddressLiteral src);
1528
1529 // Can push value or effective address
1530 void pushptr(AddressLiteral src);
1531
1532 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1533 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1534
1535 void pushoop(jobject obj);
1536 void pushklass(Metadata* obj);
1537
1538 // sign extend as need a l to ptr sized element
1539 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1540 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1541
1542 // C2 compiled method's prolog code.
1543 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1544
1545 // clear memory of size 'cnt' qwords, starting at 'base';
1546 // if 'is_large' is set, do not try to produce short loop
1547 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1548
1549 #ifdef COMPILER2
1550 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1551 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1552
1553 // IndexOf strings.
1554 // Small strings are loaded through stack if they cross page boundary.
1555 void string_indexof(Register str1, Register str2,
1556 Register cnt1, Register cnt2,
1557 int int_cnt2, Register result,
1558 XMMRegister vec, Register tmp,
1559 int ae);
1560
1561 // IndexOf for constant substrings with size >= 8 elements
1562 // which don't need to be loaded through stack.
1563 void string_indexofC8(Register str1, Register str2,
1564 Register cnt1, Register cnt2,
1565 int int_cnt2, Register result,
1566 XMMRegister vec, Register tmp,
1567 int ae);
1568
1569 // Smallest code: we don't need to load through stack,
1570 // check string tail.
1571
1572 // helper function for string_compare
1573 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1574 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1575 Address::ScaleFactor scale2, Register index, int ae);
1576 // Compare strings.
1577 void string_compare(Register str1, Register str2,
1578 Register cnt1, Register cnt2, Register result,
1579 XMMRegister vec1, int ae);
1580
1581 // Search for Non-ASCII character (Negative byte value) in a byte array,
1582 // return true if it has any and false otherwise.
1583 void has_negatives(Register ary1, Register len,
1584 Register result, Register tmp1,
1585 XMMRegister vec1, XMMRegister vec2);
1586
1587 // Compare char[] or byte[] arrays.
1588 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1589 Register limit, Register result, Register chr,
1590 XMMRegister vec1, XMMRegister vec2, bool is_char);
1591
1592 #endif
1593
1594 // Fill primitive arrays
1595 void generate_fill(BasicType t, bool aligned,
1596 Register to, Register value, Register count,
1597 Register rtmp, XMMRegister xtmp);
1598
1599 void encode_iso_array(Register src, Register dst, Register len,
1600 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1601 XMMRegister tmp4, Register tmp5, Register result);
1602
1603 #ifdef _LP64
1604 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1605 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1606 Register y, Register y_idx, Register z,
1607 Register carry, Register product,
1608 Register idx, Register kdx);
1609 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1610 Register yz_idx, Register idx,
1611 Register carry, Register product, int offset);
1612 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1613 Register carry, Register carry2,
1614 Register idx, Register jdx,
1615 Register yz_idx1, Register yz_idx2,
1616 Register tmp, Register tmp3, Register tmp4);
1617 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1618 Register yz_idx, Register idx, Register jdx,
1619 Register carry, Register product,
1620 Register carry2);
1621 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1622 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1623 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1624 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1625 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1626 Register tmp2);
1627 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1628 Register rdxReg, Register raxReg);
1629 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1630 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1631 Register tmp3, Register tmp4);
1632 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1633 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1634
1635 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1636 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1637 Register raxReg);
1638 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1639 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1640 Register raxReg);
1641 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1642 Register result, Register tmp1, Register tmp2,
1643 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1644 #endif
1645
1646 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1647 void update_byte_crc32(Register crc, Register val, Register table);
1648 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1649 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1650 // Note on a naming convention:
1651 // Prefix w = register only used on a Westmere+ architecture
1652 // Prefix n = register only used on a Nehalem architecture
1653 #ifdef _LP64
1654 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1655 Register tmp1, Register tmp2, Register tmp3);
1656 #else
1657 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1658 Register tmp1, Register tmp2, Register tmp3,
1659 XMMRegister xtmp1, XMMRegister xtmp2);
1660 #endif
1661 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1662 Register in_out,
1663 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1664 XMMRegister w_xtmp2,
1665 Register tmp1,
1666 Register n_tmp2, Register n_tmp3);
1667 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1668 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1669 Register tmp1, Register tmp2,
1670 Register n_tmp3);
1671 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1672 Register in_out1, Register in_out2, Register in_out3,
1673 Register tmp1, Register tmp2, Register tmp3,
1674 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1675 Register tmp4, Register tmp5,
1676 Register n_tmp6);
1677 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1678 Register tmp1, Register tmp2, Register tmp3,
1679 Register tmp4, Register tmp5, Register tmp6,
1680 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1681 bool is_pclmulqdq_supported);
1682 // Fold 128-bit data chunk
1683 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1684 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1685 // Fold 8-bit data
1686 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1687 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1688
1689 // Compress char[] array to byte[].
1690 void char_array_compress(Register src, Register dst, Register len,
1691 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1692 XMMRegister tmp4, Register tmp5, Register result);
1693
1694 // Inflate byte[] array to char[].
1695 void byte_array_inflate(Register src, Register dst, Register len,
1696 XMMRegister tmp1, Register tmp2);
1697
1698
1699 void save_vector_registers();
1700 void restore_vector_registers();
1701 };
1702
1703 /**
1704 * class SkipIfEqual:
1705 *
1706 * Instantiating this class will result in assembly code being output that will
1707 * jump around any code emitted between the creation of the instance and it's
1708 * automatic destruction at the end of a scope block, depending on the value of
1709 * the flag passed to the constructor, which will be checked at run-time.
1710 */
1711 class SkipIfEqual {
1712 private:
1713 MacroAssembler* _masm;
1714 Label _label;
1715
1716 public:
1717 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1718 ~SkipIfEqual();
1719 };
1720
1721 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP