461 int shift = t12->get_con();
462 shift &= BitsPerJavaInteger - 1; // semantics of Java shifts
463 int mask = max_juint >> shift;
464 if ((mask & con) == mask) // If AND is useless, skip it
465 return in1;
466 }
467 }
468 }
469 return MulNode::Identity(phase);
470 }
471
472 //------------------------------Ideal------------------------------------------
473 Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
474 // Special case constant AND mask
475 const TypeInt *t2 = phase->type( in(2) )->isa_int();
476 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
477 const int mask = t2->get_con();
478 Node *load = in(1);
479 uint lop = load->Opcode();
480
481 #if INCLUDE_SHENANDOAHGC
482 if (UseShenandoahGC && ShenandoahWriteBarrierNode::is_gc_state_load(load)) {
483 // Do not touch the load+mask, we would match the whole sequence exactly.
484 // Converting the load to LoadUB/LoadUS would mismatch and waste a register
485 // on the barrier fastpath.
486 return NULL;
487 }
488 #endif
489
490 // Masking bits off of a Character? Hi bits are already zero.
491 if( lop == Op_LoadUS &&
492 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
493 return new AndINode(load,phase->intcon(mask&0xFFFF));
494
495 // Masking bits off of a Short? Loading a Character does some masking
496 if (can_reshape &&
497 load->outcnt() == 1 && load->unique_out() == this) {
498 if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) {
499 Node* ldus = load->as_Load()->convert_to_unsigned_load(*phase);
500 ldus = phase->transform(ldus);
501 return new AndINode(ldus, phase->intcon(mask & 0xFFFF));
502 }
503
504 // Masking sign bits off of a Byte? Do an unsigned byte load plus
505 // an and.
506 if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) {
507 Node* ldub = load->as_Load()->convert_to_unsigned_load(*phase);
508 ldub = phase->transform(ldub);
509 return new AndINode(ldub, phase->intcon(mask));
510 }
511 }
512
513 // Masking off sign bits? Dont make them!
514 if( lop == Op_RShiftI ) {
515 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
516 if( t12 && t12->is_con() ) { // Shift is by a constant
517 int shift = t12->get_con();
518 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
519 const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
520 // If the AND'ing of the 2 masks has no bits, then only original shifted
521 // bits survive. NO sign-extension bits survive the maskings.
522 if( (sign_bits_mask & mask) == 0 ) {
523 // Use zero-fill shift instead
524 Node *zshift = phase->transform(new URShiftINode(load->in(1),load->in(2)));
525 return new AndINode( zshift, in(2) );
526 }
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461 int shift = t12->get_con();
462 shift &= BitsPerJavaInteger - 1; // semantics of Java shifts
463 int mask = max_juint >> shift;
464 if ((mask & con) == mask) // If AND is useless, skip it
465 return in1;
466 }
467 }
468 }
469 return MulNode::Identity(phase);
470 }
471
472 //------------------------------Ideal------------------------------------------
473 Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
474 // Special case constant AND mask
475 const TypeInt *t2 = phase->type( in(2) )->isa_int();
476 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
477 const int mask = t2->get_con();
478 Node *load = in(1);
479 uint lop = load->Opcode();
480
481 // Masking bits off of a Character? Hi bits are already zero.
482 if( lop == Op_LoadUS &&
483 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
484 return new AndINode(load,phase->intcon(mask&0xFFFF));
485
486 // Masking bits off of a Short? Loading a Character does some masking
487 if (can_reshape &&
488 load->outcnt() == 1 && load->unique_out() == this) {
489 if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) {
490 Node* ldus = load->as_Load()->convert_to_unsigned_load(*phase);
491 ldus = phase->transform(ldus);
492 return new AndINode(ldus, phase->intcon(mask & 0xFFFF));
493 }
494
495 // Masking sign bits off of a Byte? Do an unsigned byte load plus
496 // an and.
497 // Prevent transform if it feeds to CmpI. We have special matcher
498 // for LoadB+AndI+CmpI that generates a single instruction.
499 bool feeds_to_cmpi = outcnt() == 1 && unique_out()->Opcode() == Op_CmpI;
500 if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0 && !feeds_to_cmpi) {
501 Node* ldub = load->as_Load()->convert_to_unsigned_load(*phase);
502 ldub = phase->transform(ldub);
503 return new AndINode(ldub, phase->intcon(mask));
504 }
505 }
506
507 // Masking off sign bits? Dont make them!
508 if( lop == Op_RShiftI ) {
509 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
510 if( t12 && t12->is_con() ) { // Shift is by a constant
511 int shift = t12->get_con();
512 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
513 const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
514 // If the AND'ing of the 2 masks has no bits, then only original shifted
515 // bits survive. NO sign-extension bits survive the maskings.
516 if( (sign_bits_mask & mask) == 0 ) {
517 // Use zero-fill shift instead
518 Node *zshift = phase->transform(new URShiftINode(load->in(1),load->in(2)));
519 return new AndINode( zshift, in(2) );
520 }
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