src/hotspot/cpu/x86/x86.ad

rev 47825 : Support vectorization of sqrt for float

*** 1250,1259 ****
--- 1250,1260 ----
      case Op_MulReductionVD:
        if (UseSSE < 1) // requires at least SSE
          ret_value = false;
        break;
      case Op_SqrtVD:
+     case Op_SqrtVF:
        if (UseAVX < 1) // enabled for AVX only
          ret_value = false;
        break;
      case Op_CompareAndSwapL:
  #ifdef _LP64
*** 2578,2588 ****
    ins_pipe(pipe_slow);
  %}
  
  instruct sqrtF_reg(regF dst, regF src) %{
    predicate(UseSSE>=1);
!   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
  
    format %{ "sqrtss  $dst, $src" %}
    ins_cost(150);
    ins_encode %{
      __ sqrtss($dst$$XMMRegister, $src$$XMMRegister);
--- 2579,2589 ----
    ins_pipe(pipe_slow);
  %}
  
  instruct sqrtF_reg(regF dst, regF src) %{
    predicate(UseSSE>=1);
!   match(Set dst (SqrtF src));
  
    format %{ "sqrtss  $dst, $src" %}
    ins_cost(150);
    ins_encode %{
      __ sqrtss($dst$$XMMRegister, $src$$XMMRegister);
*** 2590,2600 ****
    ins_pipe(pipe_slow);
  %}
  
  instruct sqrtF_mem(regF dst, memory src) %{
    predicate(UseSSE>=1);
!   match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
  
    format %{ "sqrtss  $dst, $src" %}
    ins_cost(150);
    ins_encode %{
      __ sqrtss($dst$$XMMRegister, $src$$Address);
--- 2591,2601 ----
    ins_pipe(pipe_slow);
  %}
  
  instruct sqrtF_mem(regF dst, memory src) %{
    predicate(UseSSE>=1);
!   match(Set dst (SqrtF (LoadF src)));
  
    format %{ "sqrtss  $dst, $src" %}
    ins_cost(150);
    ins_encode %{
      __ sqrtss($dst$$XMMRegister, $src$$Address);
*** 2602,2612 ****
    ins_pipe(pipe_slow);
  %}
  
  instruct sqrtF_imm(regF dst, immF con) %{
    predicate(UseSSE>=1);
!   match(Set dst (ConvD2F (SqrtD (ConvF2D con))));
    format %{ "sqrtss  $dst, [$constantaddress]\t# load from constant table: float=$con" %}
    ins_cost(150);
    ins_encode %{
      __ sqrtss($dst$$XMMRegister, $constantaddress($con));
    %}
--- 2603,2614 ----
    ins_pipe(pipe_slow);
  %}
  
  instruct sqrtF_imm(regF dst, immF con) %{
    predicate(UseSSE>=1);
!   match(Set dst (SqrtF con));
! 
    format %{ "sqrtss  $dst, [$constantaddress]\t# load from constant table: float=$con" %}
    ins_cost(150);
    ins_encode %{
      __ sqrtss($dst$$XMMRegister, $constantaddress($con));
    %}
*** 8386,8396 ****
    ins_pipe( pipe_slow );
  %}
  
  // --------------------------------- Sqrt --------------------------------------
  
! // Floating point vector sqrt - double precision only
  instruct vsqrt2D_reg(vecX dst, vecX src) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
    match(Set dst (SqrtVD src));
    format %{ "vsqrtpd  $dst,$src\t! sqrt packed2D" %}
    ins_encode %{
--- 8388,8398 ----
    ins_pipe( pipe_slow );
  %}
  
  // --------------------------------- Sqrt --------------------------------------
  
! // Floating point vector sqrt
  instruct vsqrt2D_reg(vecX dst, vecX src) %{
    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
    match(Set dst (SqrtVD src));
    format %{ "vsqrtpd  $dst,$src\t! sqrt packed2D" %}
    ins_encode %{
*** 8453,8462 ****
--- 8455,8552 ----
      __ vsqrtpd($dst$$XMMRegister, $mem$$Address, vector_len);
    %}
    ins_pipe( pipe_slow );
  %}
  
+ instruct vsqrt2F_reg(vecD dst, vecD src) %{
+   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+   match(Set dst (SqrtVF src));
+   format %{ "vsqrtps  $dst,$src\t! sqrt packed2F" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vsqrtps($dst$$XMMRegister, $src$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsqrt2F_mem(vecD dst, memory mem) %{
+   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
+   match(Set dst (SqrtVF (LoadVector mem)));
+   format %{ "vsqrtps  $dst,$mem\t! sqrt packed2F" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vsqrtps($dst$$XMMRegister, $mem$$Address, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsqrt4F_reg(vecX dst, vecX src) %{
+   predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+   match(Set dst (SqrtVF src));
+   format %{ "vsqrtps  $dst,$src\t! sqrt packed4F" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vsqrtps($dst$$XMMRegister, $src$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsqrt4F_mem(vecX dst, memory mem) %{
+   predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
+   match(Set dst (SqrtVF (LoadVector mem)));
+   format %{ "vsqrtps  $dst,$mem\t! sqrt packed4F" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vsqrtps($dst$$XMMRegister, $mem$$Address, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsqrt8F_reg(vecY dst, vecY src) %{
+   predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
+   match(Set dst (SqrtVF src));
+   format %{ "vsqrtps  $dst,$src\t! sqrt packed8F" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vsqrtps($dst$$XMMRegister, $src$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsqrt8F_mem(vecY dst, memory mem) %{
+   predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
+   match(Set dst (SqrtVF (LoadVector mem)));
+   format %{ "vsqrtps  $dst,$mem\t! sqrt packed8F" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vsqrtps($dst$$XMMRegister, $mem$$Address, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsqrt16F_reg(vecZ dst, vecZ src) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 16);
+   match(Set dst (SqrtVF src));
+   format %{ "vsqrtps  $dst,$src\t! sqrt packed16F" %}
+   ins_encode %{
+     int vector_len = 2;
+     __ vsqrtps($dst$$XMMRegister, $src$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsqrt16F_mem(vecZ dst, memory mem) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 16);
+   match(Set dst (SqrtVF (LoadVector mem)));
+   format %{ "vsqrtps  $dst,$mem\t! sqrt packed16F" %}
+   ins_encode %{
+     int vector_len = 2;
+     __ vsqrtps($dst$$XMMRegister, $mem$$Address, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
  // ------------------------------ LeftShift -----------------------------------
  
  // Shorts/Chars vector left shift
  instruct vsll2S(vecS dst, vecS shift) %{
    predicate(UseAVX == 0 && n->as_Vector()->length() == 2);