1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "logging/log.hpp"
30 #include "logging/logStream.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "vm_version_x86.hpp"
36
37
38 int VM_Version::_cpu;
39 int VM_Version::_model;
40 int VM_Version::_stepping;
41 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
42
43 // Address of instruction which causes SEGV
44 address VM_Version::_cpuinfo_segv_addr = 0;
45 // Address of instruction after the one which causes SEGV
46 address VM_Version::_cpuinfo_cont_addr = 0;
47
48 static BufferBlob* stub_blob;
49 static const int stub_size = 1100;
50
51 extern "C" {
52 typedef void (*get_cpu_info_stub_t)(void*);
53 }
54 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
55
56
57 class VM_Version_StubGenerator: public StubCodeGenerator {
58 public:
59
60 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
61
62 address generate_get_cpu_info() {
63 // Flags to test CPU type.
64 const uint32_t HS_EFL_AC = 0x40000;
65 const uint32_t HS_EFL_ID = 0x200000;
66 // Values for when we don't have a CPUID instruction.
67 const int CPU_FAMILY_SHIFT = 8;
68 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
69 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
70 bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
71
72 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
73 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup;
74 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
75
76 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
77 # define __ _masm->
78
79 address start = __ pc();
80
81 //
82 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
83 //
84 // LP64: rcx and rdx are first and second argument registers on windows
85
86 __ push(rbp);
87 #ifdef _LP64
88 __ mov(rbp, c_rarg0); // cpuid_info address
89 #else
90 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
91 #endif
92 __ push(rbx);
93 __ push(rsi);
94 __ pushf(); // preserve rbx, and flags
95 __ pop(rax);
96 __ push(rax);
97 __ mov(rcx, rax);
98 //
99 // if we are unable to change the AC flag, we have a 386
100 //
101 __ xorl(rax, HS_EFL_AC);
102 __ push(rax);
103 __ popf();
104 __ pushf();
105 __ pop(rax);
106 __ cmpptr(rax, rcx);
107 __ jccb(Assembler::notEqual, detect_486);
108
109 __ movl(rax, CPU_FAMILY_386);
110 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
111 __ jmp(done);
112
113 //
114 // If we are unable to change the ID flag, we have a 486 which does
115 // not support the "cpuid" instruction.
116 //
117 __ bind(detect_486);
118 __ mov(rax, rcx);
119 __ xorl(rax, HS_EFL_ID);
120 __ push(rax);
121 __ popf();
122 __ pushf();
123 __ pop(rax);
124 __ cmpptr(rcx, rax);
125 __ jccb(Assembler::notEqual, detect_586);
126
127 __ bind(cpu486);
128 __ movl(rax, CPU_FAMILY_486);
129 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
130 __ jmp(done);
131
132 //
133 // At this point, we have a chip which supports the "cpuid" instruction
134 //
135 __ bind(detect_586);
136 __ xorl(rax, rax);
137 __ cpuid();
138 __ orl(rax, rax);
139 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
140 // value of at least 1, we give up and
141 // assume a 486
142 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
143 __ movl(Address(rsi, 0), rax);
144 __ movl(Address(rsi, 4), rbx);
145 __ movl(Address(rsi, 8), rcx);
146 __ movl(Address(rsi,12), rdx);
147
148 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
149 __ jccb(Assembler::belowEqual, std_cpuid4);
150
151 //
152 // cpuid(0xB) Processor Topology
153 //
154 __ movl(rax, 0xb);
155 __ xorl(rcx, rcx); // Threads level
156 __ cpuid();
157
158 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
159 __ movl(Address(rsi, 0), rax);
160 __ movl(Address(rsi, 4), rbx);
161 __ movl(Address(rsi, 8), rcx);
162 __ movl(Address(rsi,12), rdx);
163
164 __ movl(rax, 0xb);
165 __ movl(rcx, 1); // Cores level
166 __ cpuid();
167 __ push(rax);
168 __ andl(rax, 0x1f); // Determine if valid topology level
169 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
170 __ andl(rax, 0xffff);
171 __ pop(rax);
172 __ jccb(Assembler::equal, std_cpuid4);
173
174 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
175 __ movl(Address(rsi, 0), rax);
176 __ movl(Address(rsi, 4), rbx);
177 __ movl(Address(rsi, 8), rcx);
178 __ movl(Address(rsi,12), rdx);
179
180 __ movl(rax, 0xb);
181 __ movl(rcx, 2); // Packages level
182 __ cpuid();
183 __ push(rax);
184 __ andl(rax, 0x1f); // Determine if valid topology level
185 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
186 __ andl(rax, 0xffff);
187 __ pop(rax);
188 __ jccb(Assembler::equal, std_cpuid4);
189
190 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
191 __ movl(Address(rsi, 0), rax);
192 __ movl(Address(rsi, 4), rbx);
193 __ movl(Address(rsi, 8), rcx);
194 __ movl(Address(rsi,12), rdx);
195
196 //
197 // cpuid(0x4) Deterministic cache params
198 //
199 __ bind(std_cpuid4);
200 __ movl(rax, 4);
201 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
202 __ jccb(Assembler::greater, std_cpuid1);
203
204 __ xorl(rcx, rcx); // L1 cache
205 __ cpuid();
206 __ push(rax);
207 __ andl(rax, 0x1f); // Determine if valid cache parameters used
208 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
209 __ pop(rax);
210 __ jccb(Assembler::equal, std_cpuid1);
211
212 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
213 __ movl(Address(rsi, 0), rax);
214 __ movl(Address(rsi, 4), rbx);
215 __ movl(Address(rsi, 8), rcx);
216 __ movl(Address(rsi,12), rdx);
217
218 //
219 // Standard cpuid(0x1)
220 //
221 __ bind(std_cpuid1);
222 __ movl(rax, 1);
223 __ cpuid();
224 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
225 __ movl(Address(rsi, 0), rax);
226 __ movl(Address(rsi, 4), rbx);
227 __ movl(Address(rsi, 8), rcx);
228 __ movl(Address(rsi,12), rdx);
229
230 //
231 // Check if OS has enabled XGETBV instruction to access XCR0
232 // (OSXSAVE feature flag) and CPU supports AVX
233 //
234 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
235 __ cmpl(rcx, 0x18000000);
236 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
237
238 //
239 // XCR0, XFEATURE_ENABLED_MASK register
240 //
241 __ xorl(rcx, rcx); // zero for XCR0 register
242 __ xgetbv();
243 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
244 __ movl(Address(rsi, 0), rax);
245 __ movl(Address(rsi, 4), rdx);
246
247 //
248 // cpuid(0x7) Structured Extended Features
249 //
250 __ bind(sef_cpuid);
251 __ movl(rax, 7);
252 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
253 __ jccb(Assembler::greater, ext_cpuid);
254
255 __ xorl(rcx, rcx);
256 __ cpuid();
257 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
258 __ movl(Address(rsi, 0), rax);
259 __ movl(Address(rsi, 4), rbx);
260
261 //
262 // Extended cpuid(0x80000000)
263 //
264 __ bind(ext_cpuid);
265 __ movl(rax, 0x80000000);
266 __ cpuid();
267 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
268 __ jcc(Assembler::belowEqual, done);
269 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
270 __ jcc(Assembler::belowEqual, ext_cpuid1);
271 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
272 __ jccb(Assembler::belowEqual, ext_cpuid5);
273 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
274 __ jccb(Assembler::belowEqual, ext_cpuid7);
275 __ cmpl(rax, 0x80000008); // Is cpuid(0x80000009 and above) supported?
276 __ jccb(Assembler::belowEqual, ext_cpuid8);
277 __ cmpl(rax, 0x8000001E); // Is cpuid(0x8000001E) supported?
278 __ jccb(Assembler::below, ext_cpuid8);
279 //
280 // Extended cpuid(0x8000001E)
281 //
282 __ movl(rax, 0x8000001E);
283 __ cpuid();
284 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
285 __ movl(Address(rsi, 0), rax);
286 __ movl(Address(rsi, 4), rbx);
287 __ movl(Address(rsi, 8), rcx);
288 __ movl(Address(rsi,12), rdx);
289
290 //
291 // Extended cpuid(0x80000008)
292 //
293 __ bind(ext_cpuid8);
294 __ movl(rax, 0x80000008);
295 __ cpuid();
296 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
297 __ movl(Address(rsi, 0), rax);
298 __ movl(Address(rsi, 4), rbx);
299 __ movl(Address(rsi, 8), rcx);
300 __ movl(Address(rsi,12), rdx);
301
302 //
303 // Extended cpuid(0x80000007)
304 //
305 __ bind(ext_cpuid7);
306 __ movl(rax, 0x80000007);
307 __ cpuid();
308 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
309 __ movl(Address(rsi, 0), rax);
310 __ movl(Address(rsi, 4), rbx);
311 __ movl(Address(rsi, 8), rcx);
312 __ movl(Address(rsi,12), rdx);
313
314 //
315 // Extended cpuid(0x80000005)
316 //
317 __ bind(ext_cpuid5);
318 __ movl(rax, 0x80000005);
319 __ cpuid();
320 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
321 __ movl(Address(rsi, 0), rax);
322 __ movl(Address(rsi, 4), rbx);
323 __ movl(Address(rsi, 8), rcx);
324 __ movl(Address(rsi,12), rdx);
325
326 //
327 // Extended cpuid(0x80000001)
328 //
329 __ bind(ext_cpuid1);
330 __ movl(rax, 0x80000001);
331 __ cpuid();
332 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
333 __ movl(Address(rsi, 0), rax);
334 __ movl(Address(rsi, 4), rbx);
335 __ movl(Address(rsi, 8), rcx);
336 __ movl(Address(rsi,12), rdx);
337
338 //
339 // Check if OS has enabled XGETBV instruction to access XCR0
340 // (OSXSAVE feature flag) and CPU supports AVX
341 //
342 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
343 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
344 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
345 __ cmpl(rcx, 0x18000000);
346 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
347
348 __ movl(rax, 0x6);
349 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
350 __ cmpl(rax, 0x6);
351 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
352
353 // we need to bridge farther than imm8, so we use this island as a thunk
354 __ bind(done);
355 __ jmp(wrapup);
356
357 __ bind(start_simd_check);
358 //
359 // Some OSs have a bug when upper 128/256bits of YMM/ZMM
360 // registers are not restored after a signal processing.
361 // Generate SEGV here (reference through NULL)
362 // and check upper YMM/ZMM bits after it.
363 //
364 intx saved_useavx = UseAVX;
365 intx saved_usesse = UseSSE;
366 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
367 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
368 __ movl(rax, 0x10000);
369 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
370 __ cmpl(rax, 0x10000);
371 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
372 // check _cpuid_info.xem_xcr0_eax.bits.opmask
373 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
374 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
375 __ movl(rax, 0xE0);
376 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
377 __ cmpl(rax, 0xE0);
378 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
379
380 // If UseAVX is unitialized or is set by the user to include EVEX
381 if (use_evex) {
382 // EVEX setup: run in lowest evex mode
383 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
384 UseAVX = 3;
385 UseSSE = 2;
386 #ifdef _WINDOWS
387 // xmm5-xmm15 are not preserved by caller on windows
388 // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
389 __ subptr(rsp, 64);
390 __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
391 #ifdef _LP64
392 __ subptr(rsp, 64);
393 __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
394 __ subptr(rsp, 64);
395 __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
396 #endif // _LP64
397 #endif // _WINDOWS
398
399 // load value into all 64 bytes of zmm7 register
400 __ movl(rcx, VM_Version::ymm_test_value());
401 __ movdl(xmm0, rcx);
402 __ movl(rcx, 0xffff);
403 __ kmovwl(k1, rcx);
404 __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
405 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
406 #ifdef _LP64
407 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
408 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
409 #endif
410 VM_Version::clean_cpuFeatures();
411 __ jmp(save_restore_except);
412 }
413
414 __ bind(legacy_setup);
415 // AVX setup
416 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
417 UseAVX = 1;
418 UseSSE = 2;
419 #ifdef _WINDOWS
420 __ subptr(rsp, 32);
421 __ vmovdqu(Address(rsp, 0), xmm7);
422 #ifdef _LP64
423 __ subptr(rsp, 32);
424 __ vmovdqu(Address(rsp, 0), xmm8);
425 __ subptr(rsp, 32);
426 __ vmovdqu(Address(rsp, 0), xmm15);
427 #endif // _LP64
428 #endif // _WINDOWS
429
430 // load value into all 32 bytes of ymm7 register
431 __ movl(rcx, VM_Version::ymm_test_value());
432
433 __ movdl(xmm0, rcx);
434 __ pshufd(xmm0, xmm0, 0x00);
435 __ vinsertf128_high(xmm0, xmm0);
436 __ vmovdqu(xmm7, xmm0);
437 #ifdef _LP64
438 __ vmovdqu(xmm8, xmm0);
439 __ vmovdqu(xmm15, xmm0);
440 #endif
441 VM_Version::clean_cpuFeatures();
442
443 __ bind(save_restore_except);
444 __ xorl(rsi, rsi);
445 VM_Version::set_cpuinfo_segv_addr(__ pc());
446 // Generate SEGV
447 __ movl(rax, Address(rsi, 0));
448
449 VM_Version::set_cpuinfo_cont_addr(__ pc());
450 // Returns here after signal. Save xmm0 to check it later.
451
452 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
453 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
454 __ movl(rax, 0x10000);
455 __ andl(rax, Address(rsi, 4));
456 __ cmpl(rax, 0x10000);
457 __ jcc(Assembler::notEqual, legacy_save_restore);
458 // check _cpuid_info.xem_xcr0_eax.bits.opmask
459 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
460 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
461 __ movl(rax, 0xE0);
462 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
463 __ cmpl(rax, 0xE0);
464 __ jcc(Assembler::notEqual, legacy_save_restore);
465
466 // If UseAVX is unitialized or is set by the user to include EVEX
467 if (use_evex) {
468 // EVEX check: run in lowest evex mode
469 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
470 UseAVX = 3;
471 UseSSE = 2;
472 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
473 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
474 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
475 #ifdef _LP64
476 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
477 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
478 #endif
479
480 #ifdef _WINDOWS
481 #ifdef _LP64
482 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
483 __ addptr(rsp, 64);
484 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
485 __ addptr(rsp, 64);
486 #endif // _LP64
487 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
488 __ addptr(rsp, 64);
489 #endif // _WINDOWS
490 generate_vzeroupper(wrapup);
491 VM_Version::clean_cpuFeatures();
492 UseAVX = saved_useavx;
493 UseSSE = saved_usesse;
494 __ jmp(wrapup);
495 }
496
497 __ bind(legacy_save_restore);
498 // AVX check
499 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
500 UseAVX = 1;
501 UseSSE = 2;
502 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
503 __ vmovdqu(Address(rsi, 0), xmm0);
504 __ vmovdqu(Address(rsi, 32), xmm7);
505 #ifdef _LP64
506 __ vmovdqu(Address(rsi, 64), xmm8);
507 __ vmovdqu(Address(rsi, 96), xmm15);
508 #endif
509
510 #ifdef _WINDOWS
511 #ifdef _LP64
512 __ vmovdqu(xmm15, Address(rsp, 0));
513 __ addptr(rsp, 32);
514 __ vmovdqu(xmm8, Address(rsp, 0));
515 __ addptr(rsp, 32);
516 #endif // _LP64
517 __ vmovdqu(xmm7, Address(rsp, 0));
518 __ addptr(rsp, 32);
519 #endif // _WINDOWS
520 generate_vzeroupper(wrapup);
521 VM_Version::clean_cpuFeatures();
522 UseAVX = saved_useavx;
523 UseSSE = saved_usesse;
524
525 __ bind(wrapup);
526 __ popf();
527 __ pop(rsi);
528 __ pop(rbx);
529 __ pop(rbp);
530 __ ret(0);
531
532 # undef __
533
534 return start;
535 };
536 void generate_vzeroupper(Label& L_wrapup) {
537 # define __ _masm->
538 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
539 __ cmpl(Address(rsi, 4), 0x756e6547); // 'uneG'
540 __ jcc(Assembler::notEqual, L_wrapup);
541 __ movl(rcx, 0x0FFF0FF0);
542 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
543 __ andl(rcx, Address(rsi, 0));
544 __ cmpl(rcx, 0x00050670); // If it is Xeon Phi 3200/5200/7200
545 __ jcc(Assembler::equal, L_wrapup);
546 __ cmpl(rcx, 0x00080650); // If it is Future Xeon Phi
547 __ jcc(Assembler::equal, L_wrapup);
548 __ vzeroupper();
549 # undef __
550 }
551 };
552
553 void VM_Version::get_processor_features() {
554
555 _cpu = 4; // 486 by default
556 _model = 0;
557 _stepping = 0;
558 _features = 0;
559 _logical_processors_per_package = 1;
560 // i486 internal cache is both I&D and has a 16-byte line size
561 _L1_data_cache_line_size = 16;
562
563 // Get raw processor info
564
565 get_cpu_info_stub(&_cpuid_info);
566
567 assert_is_initialized();
568 _cpu = extended_cpu_family();
569 _model = extended_cpu_model();
570 _stepping = cpu_stepping();
571
572 if (cpu_family() > 4) { // it supports CPUID
573 _features = feature_flags();
574 // Logical processors are only available on P4s and above,
575 // and only if hyperthreading is available.
576 _logical_processors_per_package = logical_processor_count();
577 _L1_data_cache_line_size = L1_line_size();
578 }
579
580 _supports_cx8 = supports_cmpxchg8();
581 // xchg and xadd instructions
582 _supports_atomic_getset4 = true;
583 _supports_atomic_getadd4 = true;
584 LP64_ONLY(_supports_atomic_getset8 = true);
585 LP64_ONLY(_supports_atomic_getadd8 = true);
586
587 #ifdef _LP64
588 // OS should support SSE for x64 and hardware should support at least SSE2.
589 if (!VM_Version::supports_sse2()) {
590 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
591 }
592 // in 64 bit the use of SSE2 is the minimum
593 if (UseSSE < 2) UseSSE = 2;
594 #endif
595
596 #ifdef AMD64
597 // flush_icache_stub have to be generated first.
598 // That is why Icache line size is hard coded in ICache class,
599 // see icache_x86.hpp. It is also the reason why we can't use
600 // clflush instruction in 32-bit VM since it could be running
601 // on CPU which does not support it.
602 //
603 // The only thing we can do is to verify that flushed
604 // ICache::line_size has correct value.
605 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
606 // clflush_size is size in quadwords (8 bytes).
607 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
608 #endif
609
610 // If the OS doesn't support SSE, we can't use this feature even if the HW does
611 if (!os::supports_sse())
612 _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
613
614 if (UseSSE < 4) {
615 _features &= ~CPU_SSE4_1;
616 _features &= ~CPU_SSE4_2;
617 }
618
619 if (UseSSE < 3) {
620 _features &= ~CPU_SSE3;
621 _features &= ~CPU_SSSE3;
622 _features &= ~CPU_SSE4A;
623 }
624
625 if (UseSSE < 2)
626 _features &= ~CPU_SSE2;
627
628 if (UseSSE < 1)
629 _features &= ~CPU_SSE;
630
631 //since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0.
632 if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
633 UseAVX = 0;
634 }
635
636 // first try initial setting and detect what we can support
637 int use_avx_limit = 0;
638 if (UseAVX > 0) {
639 if (UseAVX > 2 && supports_evex()) {
640 use_avx_limit = 3;
641 } else if (UseAVX > 1 && supports_avx2()) {
642 use_avx_limit = 2;
643 } else if (UseAVX > 0 && supports_avx()) {
644 use_avx_limit = 1;
645 } else {
646 use_avx_limit = 0;
647 }
648 }
649 if (FLAG_IS_DEFAULT(UseAVX)) {
650 FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
651 } else if (UseAVX > use_avx_limit) {
652 warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit);
653 FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
654 } else if (UseAVX < 0) {
655 warning("UseAVX=%d is not valid, setting it to UseAVX=0", (int) UseAVX);
656 FLAG_SET_DEFAULT(UseAVX, 0);
657 }
658
659 if (UseAVX < 3) {
660 _features &= ~CPU_AVX512F;
661 _features &= ~CPU_AVX512DQ;
662 _features &= ~CPU_AVX512CD;
663 _features &= ~CPU_AVX512BW;
664 _features &= ~CPU_AVX512VL;
665 }
666
667 if (UseAVX < 2)
668 _features &= ~CPU_AVX2;
669
670 if (UseAVX < 1) {
671 _features &= ~CPU_AVX;
672 _features &= ~CPU_VZEROUPPER;
673 }
674
675 if (logical_processors_per_package() == 1) {
676 // HT processor could be installed on a system which doesn't support HT.
677 _features &= ~CPU_HT;
678 }
679
680 if( is_intel() ) { // Intel cpus specific settings
681 if (is_knights_family()) {
682 _features &= ~CPU_VZEROUPPER;
683 }
684 }
685
686 char buf[256];
687 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
688 cores_per_cpu(), threads_per_core(),
689 cpu_family(), _model, _stepping,
690 (supports_cmov() ? ", cmov" : ""),
691 (supports_cmpxchg8() ? ", cx8" : ""),
692 (supports_fxsr() ? ", fxsr" : ""),
693 (supports_mmx() ? ", mmx" : ""),
694 (supports_sse() ? ", sse" : ""),
695 (supports_sse2() ? ", sse2" : ""),
696 (supports_sse3() ? ", sse3" : ""),
697 (supports_ssse3()? ", ssse3": ""),
698 (supports_sse4_1() ? ", sse4.1" : ""),
699 (supports_sse4_2() ? ", sse4.2" : ""),
700 (supports_popcnt() ? ", popcnt" : ""),
701 (supports_avx() ? ", avx" : ""),
702 (supports_avx2() ? ", avx2" : ""),
703 (supports_aes() ? ", aes" : ""),
704 (supports_clmul() ? ", clmul" : ""),
705 (supports_erms() ? ", erms" : ""),
706 (supports_rtm() ? ", rtm" : ""),
707 (supports_mmx_ext() ? ", mmxext" : ""),
708 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
709 (supports_lzcnt() ? ", lzcnt": ""),
710 (supports_sse4a() ? ", sse4a": ""),
711 (supports_ht() ? ", ht": ""),
712 (supports_tsc() ? ", tsc": ""),
713 (supports_tscinv_bit() ? ", tscinvbit": ""),
714 (supports_tscinv() ? ", tscinv": ""),
715 (supports_bmi1() ? ", bmi1" : ""),
716 (supports_bmi2() ? ", bmi2" : ""),
717 (supports_adx() ? ", adx" : ""),
718 (supports_evex() ? ", evex" : ""),
719 (supports_sha() ? ", sha" : ""),
720 (supports_fma() ? ", fma" : ""));
721 _features_string = os::strdup(buf);
722
723 // UseSSE is set to the smaller of what hardware supports and what
724 // the command line requires. I.e., you cannot set UseSSE to 2 on
725 // older Pentiums which do not support it.
726 int use_sse_limit = 0;
727 if (UseSSE > 0) {
728 if (UseSSE > 3 && supports_sse4_1()) {
729 use_sse_limit = 4;
730 } else if (UseSSE > 2 && supports_sse3()) {
731 use_sse_limit = 3;
732 } else if (UseSSE > 1 && supports_sse2()) {
733 use_sse_limit = 2;
734 } else if (UseSSE > 0 && supports_sse()) {
735 use_sse_limit = 1;
736 } else {
737 use_sse_limit = 0;
738 }
739 }
740 if (FLAG_IS_DEFAULT(UseSSE)) {
741 FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
742 } else if (UseSSE > use_sse_limit) {
743 warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", (int) UseSSE, use_sse_limit);
744 FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
745 } else if (UseSSE < 0) {
746 warning("UseSSE=%d is not valid, setting it to UseSSE=0", (int) UseSSE);
747 FLAG_SET_DEFAULT(UseSSE, 0);
748 }
749
750 // Use AES instructions if available.
751 if (supports_aes()) {
752 if (FLAG_IS_DEFAULT(UseAES)) {
753 FLAG_SET_DEFAULT(UseAES, true);
754 }
755 if (!UseAES) {
756 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
757 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
758 }
759 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
760 } else {
761 if (UseSSE > 2) {
762 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
763 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
764 }
765 } else {
766 // The AES intrinsic stubs require AES instruction support (of course)
767 // but also require sse3 mode or higher for instructions it use.
768 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
769 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
770 }
771 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
772 }
773
774 // --AES-CTR begins--
775 if (!UseAESIntrinsics) {
776 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
777 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
778 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
779 }
780 } else {
781 if(supports_sse4_1()) {
782 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
783 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
784 }
785 } else {
786 // The AES-CTR intrinsic stubs require AES instruction support (of course)
787 // but also require sse4.1 mode or higher for instructions it use.
788 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
789 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
790 }
791 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
792 }
793 }
794 // --AES-CTR ends--
795 }
796 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
797 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
798 warning("AES instructions are not available on this CPU");
799 FLAG_SET_DEFAULT(UseAES, false);
800 }
801 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
802 warning("AES intrinsics are not available on this CPU");
803 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
804 }
805 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
806 warning("AES-CTR intrinsics are not available on this CPU");
807 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
808 }
809 }
810
811 // Use CLMUL instructions if available.
812 if (supports_clmul()) {
813 if (FLAG_IS_DEFAULT(UseCLMUL)) {
814 UseCLMUL = true;
815 }
816 } else if (UseCLMUL) {
817 if (!FLAG_IS_DEFAULT(UseCLMUL))
818 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
819 FLAG_SET_DEFAULT(UseCLMUL, false);
820 }
821
822 if (UseCLMUL && (UseSSE > 2)) {
823 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
824 UseCRC32Intrinsics = true;
825 }
826 } else if (UseCRC32Intrinsics) {
827 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
828 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
829 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
830 }
831
832 if (supports_sse4_2() && supports_clmul()) {
833 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
834 UseCRC32CIntrinsics = true;
835 }
836 } else if (UseCRC32CIntrinsics) {
837 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
838 warning("CRC32C intrinsics are not available on this CPU");
839 }
840 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
841 }
842
843 // GHASH/GCM intrinsics
844 if (UseCLMUL && (UseSSE > 2)) {
845 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
846 UseGHASHIntrinsics = true;
847 }
848 } else if (UseGHASHIntrinsics) {
849 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
850 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
851 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
852 }
853
854 if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
855 if (FLAG_IS_DEFAULT(UseFMA)) {
856 UseFMA = true;
857 }
858 } else if (UseFMA) {
859 warning("FMA instructions are not available on this CPU");
860 FLAG_SET_DEFAULT(UseFMA, false);
861 }
862
863 if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
864 if (FLAG_IS_DEFAULT(UseSHA)) {
865 UseSHA = true;
866 }
867 } else if (UseSHA) {
868 warning("SHA instructions are not available on this CPU");
869 FLAG_SET_DEFAULT(UseSHA, false);
870 }
871
872 if (supports_sha() && UseSHA) {
873 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
874 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
875 }
876 } else if (UseSHA1Intrinsics) {
877 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
878 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
879 }
880
881 if (UseSHA) {
882 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
883 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
884 }
885 } else if (UseSHA256Intrinsics) {
886 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
887 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
888 }
889
890 if (UseSHA && supports_avx2() && supports_bmi2()) {
891 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
892 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
893 }
894 } else if (UseSHA512Intrinsics) {
895 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
896 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
897 }
898
899 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
900 FLAG_SET_DEFAULT(UseSHA, false);
901 }
902
903 if (UseAdler32Intrinsics) {
904 warning("Adler32Intrinsics not available on this CPU.");
905 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
906 }
907
908 if (!supports_rtm() && UseRTMLocking) {
909 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
910 // setting during arguments processing. See use_biased_locking().
911 // VM_Version_init() is executed after UseBiasedLocking is used
912 // in Thread::allocate().
913 vm_exit_during_initialization("RTM instructions are not available on this CPU");
914 }
915
916 #if INCLUDE_RTM_OPT
917 if (UseRTMLocking) {
918 if (is_client_compilation_mode_vm()) {
919 // Only C2 does RTM locking optimization.
920 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
921 // setting during arguments processing. See use_biased_locking().
922 vm_exit_during_initialization("RTM locking optimization is not supported in emulated client VM");
923 }
924 if (is_intel_family_core()) {
925 if ((_model == CPU_MODEL_HASWELL_E3) ||
926 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
927 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
928 // currently a collision between SKL and HSW_E3
929 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
930 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this "
931 "platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
932 } else {
933 warning("UseRTMLocking is only available as experimental option on this platform.");
934 }
935 }
936 }
937 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
938 // RTM locking should be used only for applications with
939 // high lock contention. For now we do not use it by default.
940 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
941 }
942 } else { // !UseRTMLocking
943 if (UseRTMForStackLocks) {
944 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
945 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
946 }
947 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
948 }
949 if (UseRTMDeopt) {
950 FLAG_SET_DEFAULT(UseRTMDeopt, false);
951 }
952 if (PrintPreciseRTMLockingStatistics) {
953 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
954 }
955 }
956 #else
957 if (UseRTMLocking) {
958 // Only C2 does RTM locking optimization.
959 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
960 // setting during arguments processing. See use_biased_locking().
961 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
962 }
963 #endif
964
965 #ifdef COMPILER2
966 if (UseFPUForSpilling) {
967 if (UseSSE < 2) {
968 // Only supported with SSE2+
969 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
970 }
971 }
972 #endif
973 #if COMPILER2_OR_JVMCI
974 if (MaxVectorSize > 0) {
975 if (!is_power_of_2(MaxVectorSize)) {
976 warning("MaxVectorSize must be a power of 2");
977 FLAG_SET_DEFAULT(MaxVectorSize, 64);
978 }
979 if (UseSSE < 2) {
980 // Vectors (in XMM) are only supported with SSE2+
981 if (MaxVectorSize > 0) {
982 if (!FLAG_IS_DEFAULT(MaxVectorSize))
983 warning("MaxVectorSize must be 0");
984 FLAG_SET_DEFAULT(MaxVectorSize, 0);
985 }
986 }
987 else if (UseAVX == 0 || !os_supports_avx_vectors()) {
988 // 32 bytes vectors (in YMM) are only supported with AVX+
989 if (MaxVectorSize > 16) {
990 if (!FLAG_IS_DEFAULT(MaxVectorSize))
991 warning("MaxVectorSize must be <= 16");
992 FLAG_SET_DEFAULT(MaxVectorSize, 16);
993 }
994 }
995 else if (UseAVX == 1 || UseAVX == 2) {
996 // 64 bytes vectors (in ZMM) are only supported with AVX 3
997 if (MaxVectorSize > 32) {
998 if (!FLAG_IS_DEFAULT(MaxVectorSize))
999 warning("MaxVectorSize must be <= 32");
1000 FLAG_SET_DEFAULT(MaxVectorSize, 32);
1001 }
1002 }
1003 else if (UseAVX > 2 ) {
1004 if (MaxVectorSize > 64) {
1005 if (!FLAG_IS_DEFAULT(MaxVectorSize))
1006 warning("MaxVectorSize must be <= 64");
1007 FLAG_SET_DEFAULT(MaxVectorSize, 64);
1008 }
1009 }
1010 #if defined(COMPILER2) && defined(ASSERT)
1011 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1012 tty->print_cr("State of YMM registers after signal handle:");
1013 int nreg = 2 LP64_ONLY(+2);
1014 const char* ymm_name[4] = {"0", "7", "8", "15"};
1015 for (int i = 0; i < nreg; i++) {
1016 tty->print("YMM%s:", ymm_name[i]);
1017 for (int j = 7; j >=0; j--) {
1018 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1019 }
1020 tty->cr();
1021 }
1022 }
1023 #endif // COMPILER2 && ASSERT
1024 }
1025 #endif // COMPILER2_OR_JVMCI
1026
1027 #ifdef COMPILER2
1028 #ifdef _LP64
1029 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1030 UseMultiplyToLenIntrinsic = true;
1031 }
1032 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1033 UseSquareToLenIntrinsic = true;
1034 }
1035 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1036 UseMulAddIntrinsic = true;
1037 }
1038 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1039 UseMontgomeryMultiplyIntrinsic = true;
1040 }
1041 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1042 UseMontgomerySquareIntrinsic = true;
1043 }
1044 #else
1045 if (UseMultiplyToLenIntrinsic) {
1046 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1047 warning("multiplyToLen intrinsic is not available in 32-bit VM");
1048 }
1049 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1050 }
1051 if (UseMontgomeryMultiplyIntrinsic) {
1052 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1053 warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1054 }
1055 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1056 }
1057 if (UseMontgomerySquareIntrinsic) {
1058 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1059 warning("montgomerySquare intrinsic is not available in 32-bit VM");
1060 }
1061 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1062 }
1063 if (UseSquareToLenIntrinsic) {
1064 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1065 warning("squareToLen intrinsic is not available in 32-bit VM");
1066 }
1067 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1068 }
1069 if (UseMulAddIntrinsic) {
1070 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1071 warning("mulAdd intrinsic is not available in 32-bit VM");
1072 }
1073 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1074 }
1075 #endif
1076 #endif // COMPILER2
1077
1078 // On new cpus instructions which update whole XMM register should be used
1079 // to prevent partial register stall due to dependencies on high half.
1080 //
1081 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1082 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1083 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1084 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1085
1086
1087 if (is_zx()) { // ZX cpus specific settings
1088 if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1089 UseStoreImmI16 = false; // don't use it on ZX cpus
1090 }
1091 if ((cpu_family() == 6) || (cpu_family() == 7)) {
1092 if (FLAG_IS_DEFAULT(UseAddressNop)) {
1093 // Use it on all ZX cpus
1094 UseAddressNop = true;
1095 }
1096 }
1097 if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1098 UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus
1099 }
1100 if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1101 if (supports_sse3()) {
1102 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus
1103 } else {
1104 UseXmmRegToRegMoveAll = false;
1105 }
1106 }
1107 if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus
1108 #ifdef COMPILER2
1109 if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1110 // For new ZX cpus do the next optimization:
1111 // don't align the beginning of a loop if there are enough instructions
1112 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1113 // in current fetch line (OptoLoopAlignment) or the padding
1114 // is big (> MaxLoopPad).
1115 // Set MaxLoopPad to 11 for new ZX cpus to reduce number of
1116 // generated NOP instructions. 11 is the largest size of one
1117 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1118 MaxLoopPad = 11;
1119 }
1120 #endif // COMPILER2
1121 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1122 UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus
1123 }
1124 if (supports_sse4_2()) { // new ZX cpus
1125 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1126 UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
1127 }
1128 }
1129 if (supports_sse4_2()) {
1130 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1131 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1132 }
1133 } else {
1134 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1135 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1136 }
1137 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1138 }
1139 }
1140
1141 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1142 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1143 }
1144 }
1145
1146 if( is_amd() ) { // AMD cpus specific settings
1147 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1148 // Use it on new AMD cpus starting from Opteron.
1149 UseAddressNop = true;
1150 }
1151 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1152 // Use it on new AMD cpus starting from Opteron.
1153 UseNewLongLShift = true;
1154 }
1155 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1156 if (supports_sse4a()) {
1157 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1158 } else {
1159 UseXmmLoadAndClearUpper = false;
1160 }
1161 }
1162 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1163 if( supports_sse4a() ) {
1164 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1165 } else {
1166 UseXmmRegToRegMoveAll = false;
1167 }
1168 }
1169 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1170 if( supports_sse4a() ) {
1171 UseXmmI2F = true;
1172 } else {
1173 UseXmmI2F = false;
1174 }
1175 }
1176 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1177 if( supports_sse4a() ) {
1178 UseXmmI2D = true;
1179 } else {
1180 UseXmmI2D = false;
1181 }
1182 }
1183 if (supports_sse4_2()) {
1184 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1185 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1186 }
1187 } else {
1188 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1189 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1190 }
1191 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1192 }
1193
1194 // some defaults for AMD family 15h
1195 if ( cpu_family() == 0x15 ) {
1196 // On family 15h processors default is no sw prefetch
1197 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1198 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1199 }
1200 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1201 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1202 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1203 }
1204 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1205 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1206 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1207 }
1208 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1209 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1210 }
1211 }
1212
1213 #ifdef COMPILER2
1214 if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1215 // Limit vectors size to 16 bytes on AMD cpus < 17h.
1216 FLAG_SET_DEFAULT(MaxVectorSize, 16);
1217 }
1218 #endif // COMPILER2
1219
1220 // Some defaults for AMD family 17h
1221 if ( cpu_family() == 0x17 ) {
1222 // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1223 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1224 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1225 }
1226 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1227 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1228 }
1229 #ifdef COMPILER2
1230 if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1231 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1232 }
1233 #endif
1234 }
1235 }
1236
1237 if( is_intel() ) { // Intel cpus specific settings
1238 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1239 UseStoreImmI16 = false; // don't use it on Intel cpus
1240 }
1241 if( cpu_family() == 6 || cpu_family() == 15 ) {
1242 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1243 // Use it on all Intel cpus starting from PentiumPro
1244 UseAddressNop = true;
1245 }
1246 }
1247 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1248 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1249 }
1250 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1251 if( supports_sse3() ) {
1252 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1253 } else {
1254 UseXmmRegToRegMoveAll = false;
1255 }
1256 }
1257 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1258 #ifdef COMPILER2
1259 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1260 // For new Intel cpus do the next optimization:
1261 // don't align the beginning of a loop if there are enough instructions
1262 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1263 // in current fetch line (OptoLoopAlignment) or the padding
1264 // is big (> MaxLoopPad).
1265 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1266 // generated NOP instructions. 11 is the largest size of one
1267 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1268 MaxLoopPad = 11;
1269 }
1270 #endif // COMPILER2
1271 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1272 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1273 }
1274 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1275 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1276 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1277 }
1278 }
1279 if (supports_sse4_2()) {
1280 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1281 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1282 }
1283 } else {
1284 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1285 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1286 }
1287 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1288 }
1289 }
1290 if (is_atom_family() || is_knights_family()) {
1291 #ifdef COMPILER2
1292 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1293 OptoScheduling = true;
1294 }
1295 #endif
1296 if (supports_sse4_2()) { // Silvermont
1297 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1298 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1299 }
1300 }
1301 if (FLAG_IS_DEFAULT(UseIncDec)) {
1302 FLAG_SET_DEFAULT(UseIncDec, false);
1303 }
1304 }
1305 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1306 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1307 }
1308 }
1309
1310 #ifdef _LP64
1311 if (UseSSE42Intrinsics) {
1312 if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1313 UseVectorizedMismatchIntrinsic = true;
1314 }
1315 } else if (UseVectorizedMismatchIntrinsic) {
1316 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1317 warning("vectorizedMismatch intrinsics are not available on this CPU");
1318 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1319 }
1320 #else
1321 if (UseVectorizedMismatchIntrinsic) {
1322 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1323 warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1324 }
1325 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1326 }
1327 #endif // _LP64
1328
1329 // Use count leading zeros count instruction if available.
1330 if (supports_lzcnt()) {
1331 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1332 UseCountLeadingZerosInstruction = true;
1333 }
1334 } else if (UseCountLeadingZerosInstruction) {
1335 warning("lzcnt instruction is not available on this CPU");
1336 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1337 }
1338
1339 // Use count trailing zeros instruction if available
1340 if (supports_bmi1()) {
1341 // tzcnt does not require VEX prefix
1342 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1343 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1344 // Don't use tzcnt if BMI1 is switched off on command line.
1345 UseCountTrailingZerosInstruction = false;
1346 } else {
1347 UseCountTrailingZerosInstruction = true;
1348 }
1349 }
1350 } else if (UseCountTrailingZerosInstruction) {
1351 warning("tzcnt instruction is not available on this CPU");
1352 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1353 }
1354
1355 // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1356 // VEX prefix is generated only when AVX > 0.
1357 if (supports_bmi1() && supports_avx()) {
1358 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1359 UseBMI1Instructions = true;
1360 }
1361 } else if (UseBMI1Instructions) {
1362 warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1363 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1364 }
1365
1366 if (supports_bmi2() && supports_avx()) {
1367 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1368 UseBMI2Instructions = true;
1369 }
1370 } else if (UseBMI2Instructions) {
1371 warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1372 FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1373 }
1374
1375 // Use population count instruction if available.
1376 if (supports_popcnt()) {
1377 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1378 UsePopCountInstruction = true;
1379 }
1380 } else if (UsePopCountInstruction) {
1381 warning("POPCNT instruction is not available on this CPU");
1382 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1383 }
1384
1385 // Use fast-string operations if available.
1386 if (supports_erms()) {
1387 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1388 UseFastStosb = true;
1389 }
1390 } else if (UseFastStosb) {
1391 warning("fast-string operations are not available on this CPU");
1392 FLAG_SET_DEFAULT(UseFastStosb, false);
1393 }
1394
1395 #ifdef COMPILER2
1396 if (FLAG_IS_DEFAULT(AlignVector)) {
1397 // Modern processors allow misaligned memory operations for vectors.
1398 AlignVector = !UseUnalignedLoadStores;
1399 }
1400 #endif // COMPILER2
1401
1402 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1403 if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1404 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1405 } else if (!supports_sse() && supports_3dnow_prefetch()) {
1406 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1407 }
1408 }
1409
1410 // Allocation prefetch settings
1411 intx cache_line_size = prefetch_data_size();
1412 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1413 (cache_line_size > AllocatePrefetchStepSize)) {
1414 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1415 }
1416
1417 if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1418 assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1419 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1420 warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1421 }
1422 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1423 }
1424
1425 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1426 bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1427 FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1428 }
1429
1430 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1431 if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1432 supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1433 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1434 }
1435 #ifdef COMPILER2
1436 if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1437 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1438 }
1439 #endif
1440 }
1441
1442 if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) {
1443 #ifdef COMPILER2
1444 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1445 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1446 }
1447 #endif
1448 }
1449
1450 #ifdef _LP64
1451 // Prefetch settings
1452
1453 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
1454 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
1455 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
1456 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
1457
1458 // gc copy/scan is disabled if prefetchw isn't supported, because
1459 // Prefetch::write emits an inlined prefetchw on Linux.
1460 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
1461 // The used prefetcht0 instruction works for both amd64 and em64t.
1462
1463 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1464 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1465 }
1466 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1467 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1468 }
1469 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1470 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1471 }
1472 #endif
1473
1474 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1475 (cache_line_size > ContendedPaddingWidth))
1476 ContendedPaddingWidth = cache_line_size;
1477
1478 // This machine allows unaligned memory accesses
1479 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1480 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1481 }
1482
1483 #ifndef PRODUCT
1484 if (log_is_enabled(Info, os, cpu)) {
1485 LogStream ls(Log(os, cpu)::info());
1486 outputStream* log = &ls;
1487 log->print_cr("Logical CPUs per core: %u",
1488 logical_processors_per_package());
1489 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1490 log->print("UseSSE=%d", (int) UseSSE);
1491 if (UseAVX > 0) {
1492 log->print(" UseAVX=%d", (int) UseAVX);
1493 }
1494 if (UseAES) {
1495 log->print(" UseAES=1");
1496 }
1497 #ifdef COMPILER2
1498 if (MaxVectorSize > 0) {
1499 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1500 }
1501 #endif
1502 log->cr();
1503 log->print("Allocation");
1504 if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1505 log->print_cr(": no prefetching");
1506 } else {
1507 log->print(" prefetching: ");
1508 if (UseSSE == 0 && supports_3dnow_prefetch()) {
1509 log->print("PREFETCHW");
1510 } else if (UseSSE >= 1) {
1511 if (AllocatePrefetchInstr == 0) {
1512 log->print("PREFETCHNTA");
1513 } else if (AllocatePrefetchInstr == 1) {
1514 log->print("PREFETCHT0");
1515 } else if (AllocatePrefetchInstr == 2) {
1516 log->print("PREFETCHT2");
1517 } else if (AllocatePrefetchInstr == 3) {
1518 log->print("PREFETCHW");
1519 }
1520 }
1521 if (AllocatePrefetchLines > 1) {
1522 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1523 } else {
1524 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1525 }
1526 }
1527
1528 if (PrefetchCopyIntervalInBytes > 0) {
1529 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1530 }
1531 if (PrefetchScanIntervalInBytes > 0) {
1532 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1533 }
1534 if (PrefetchFieldsAhead > 0) {
1535 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1536 }
1537 if (ContendedPaddingWidth > 0) {
1538 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1539 }
1540 }
1541 #endif // !PRODUCT
1542 }
1543
1544 bool VM_Version::use_biased_locking() {
1545 #if INCLUDE_RTM_OPT
1546 // RTM locking is most useful when there is high lock contention and
1547 // low data contention. With high lock contention the lock is usually
1548 // inflated and biased locking is not suitable for that case.
1549 // RTM locking code requires that biased locking is off.
1550 // Note: we can't switch off UseBiasedLocking in get_processor_features()
1551 // because it is used by Thread::allocate() which is called before
1552 // VM_Version::initialize().
1553 if (UseRTMLocking && UseBiasedLocking) {
1554 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1555 FLAG_SET_DEFAULT(UseBiasedLocking, false);
1556 } else {
1557 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1558 UseBiasedLocking = false;
1559 }
1560 }
1561 #endif
1562 return UseBiasedLocking;
1563 }
1564
1565 void VM_Version::initialize() {
1566 ResourceMark rm;
1567 // Making this stub must be FIRST use of assembler
1568
1569 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1570 if (stub_blob == NULL) {
1571 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1572 }
1573 CodeBuffer c(stub_blob);
1574 VM_Version_StubGenerator g(&c);
1575 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1576 g.generate_get_cpu_info());
1577
1578 get_processor_features();
1579 }