src/hotspot/cpu/x86/assembler_x86.cpp

rev 50140 : Vector cast support

*** 1760,1777 ****
--- 1760,1793 ----
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
    emit_int8((unsigned char)0xE6);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
+ void Assembler::vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
+   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
+   emit_int8((unsigned char)0xE6);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
  void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
    emit_int8(0x5B);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
+ void Assembler::vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
+   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
+   emit_int8(0x5B);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
  void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
    attributes.set_rex_vex_w_reverted();
    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
*** 1882,1892 ****
    assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
    InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
    int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
    emit_int8((unsigned char)0x5A);
    emit_int8((unsigned char)(0xC0 | encode));
- 
  }
  
  void Assembler::evcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len) {
    assert(UseAVX > 2, "");
    InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
--- 1898,1907 ----
*** 1910,1919 ****
--- 1925,2023 ----
    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x1D);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
+ void Assembler::vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
+   emit_int8((unsigned char)0x5A);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::evcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(UseAVX > 2, "");
+   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
+   emit_int8((unsigned char)0x5A);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
+   emit_int8((unsigned char)0x5B);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
+   emit_int8((unsigned char)0xE6);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::evpmovwb(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(UseAVX > 2, "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
+   emit_int8((unsigned char)0x30);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::evpmovdw(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(UseAVX > 2, "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
+   emit_int8((unsigned char)0x33);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::evpmovdb(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(UseAVX > 2, "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
+   emit_int8((unsigned char)0x31);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::evpmovqd(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(UseAVX > 2, "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
+   emit_int8((unsigned char)0x35);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::evpmovqb(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(UseAVX > 2, "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
+   emit_int8((unsigned char)0x32);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::evpmovqw(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(UseAVX > 2, "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
+   emit_int8((unsigned char)0x34);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
  void Assembler::pabsd(XMMRegister dst, XMMRegister src) {
    assert(VM_Version::supports_ssse3(), "");
    InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x1E);
*** 3635,3644 ****
--- 3739,3765 ----
    emit_int8(0x06);
    emit_int8(0xC0 | encode);
    emit_int8(imm8);
  }
  
+ void Assembler::vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
+   assert(VM_Version::supports_avx(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
+   emit_int8(0x04);
+   emit_int8(0xC0 | encode);
+   emit_int8(imm8);
+ }
+ 
+ void Assembler::vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
+   assert(VM_Version::supports_avx2(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
+   emit_int8(0x01);
+   emit_int8(0xC0 | encode);
+   emit_int8(imm8);
+ }
  
  void Assembler::pause() {
    emit_int8((unsigned char)0xF3);
    emit_int8((unsigned char)0x90);
  }
*** 4179,4211 ****
    emit_int8(0x32);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
  void Assembler::vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len) {
!   assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
!   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x21);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
  void Assembler::vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len) {
!   assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
!   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x22);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
  void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
!   assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
!   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x20);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
  void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
    assert(VM_Version::supports_avx512vlbw(), "");
    assert(src != xnoreg, "sanity");
    InstructionMark im(this);
    InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
--- 4300,4368 ----
    emit_int8(0x32);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
  void Assembler::vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len) {
!   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
!          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
!              VM_Version::supports_evex(), "");
!   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x21);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
  void Assembler::vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len) {
!   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
!          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
!              VM_Version::supports_evex(), "");
!   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x22);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
  void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
!   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
!          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
!              VM_Version::supports_evex(), "");
!   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
    int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
    emit_int8(0x20);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
+ void Assembler::vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
+          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
+              VM_Version::supports_evex(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
+   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8(0x23);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
+          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
+              VM_Version::supports_evex(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
+   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8(0x24);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
+ void Assembler::vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
+          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
+              VM_Version::supports_evex(), "");
+   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
+   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8(0x25);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
  void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
    assert(VM_Version::supports_avx512vlbw(), "");
    assert(src != xnoreg, "sanity");
    InstructionMark im(this);
    InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);