1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
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  24 
  25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "vm_version_x86.hpp"
  30 
  31 class BiasedLockingCounters;
  32 
  33 // Contains all the definitions needed for x86 assembly code generation.
  34 
  35 // Calling convention
  36 class Argument {
  37  public:
  38   enum {
  39 #ifdef _LP64
  40 #ifdef _WIN64
  41     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  42     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  43 #else
  44     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  45     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  46 #endif // _WIN64
  47     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  48     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  49 #else
  50     n_register_parameters = 0   // 0 registers used to pass arguments
  51 #endif // _LP64
  52   };
  53 };
  54 
  55 
  56 #ifdef _LP64
  57 // Symbolically name the register arguments used by the c calling convention.
  58 // Windows is different from linux/solaris. So much for standards...
  59 
  60 #ifdef _WIN64
  61 
  62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  64 REGISTER_DECLARATION(Register, c_rarg2, r8);
  65 REGISTER_DECLARATION(Register, c_rarg3, r9);
  66 
  67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  71 
  72 #else
  73 
  74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  78 REGISTER_DECLARATION(Register, c_rarg4, r8);
  79 REGISTER_DECLARATION(Register, c_rarg5, r9);
  80 
  81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  89 
  90 #endif // _WIN64
  91 
  92 // Symbolically name the register arguments used by the Java calling convention.
  93 // We have control over the convention for java so we can do what we please.
  94 // What pleases us is to offset the java calling convention so that when
  95 // we call a suitable jni method the arguments are lined up and we don't
  96 // have to do little shuffling. A suitable jni method is non-static and a
  97 // small number of arguments (two fewer args on windows)
  98 //
  99 //        |-------------------------------------------------------|
 100 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
 101 //        |-------------------------------------------------------|
 102 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 103 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 104 //        |-------------------------------------------------------|
 105 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 106 //        |-------------------------------------------------------|
 107 
 108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 111 // Windows runs out of register args here
 112 #ifdef _WIN64
 113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 115 #else
 116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 118 #endif /* _WIN64 */
 119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 120 
 121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 129 
 130 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 131 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 132 
 133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 135 
 136 #else
 137 // rscratch1 will apear in 32bit code that is dead but of course must compile
 138 // Using noreg ensures if the dead code is incorrectly live and executed it
 139 // will cause an assertion failure
 140 #define rscratch1 noreg
 141 #define rscratch2 noreg
 142 
 143 #endif // _LP64
 144 
 145 // JSR 292
 146 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 147 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 148 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
 149 
 150 // Address is an abstraction used to represent a memory location
 151 // using any of the amd64 addressing modes with one object.
 152 //
 153 // Note: A register location is represented via a Register, not
 154 //       via an address for efficiency & simplicity reasons.
 155 
 156 class ArrayAddress;
 157 
 158 class Address {
 159  public:
 160   enum ScaleFactor {
 161     no_scale = -1,
 162     times_1  =  0,
 163     times_2  =  1,
 164     times_4  =  2,
 165     times_8  =  3,
 166     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 167   };
 168   static ScaleFactor times(int size) {
 169     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 170     if (size == 8)  return times_8;
 171     if (size == 4)  return times_4;
 172     if (size == 2)  return times_2;
 173     return times_1;
 174   }
 175   static int scale_size(ScaleFactor scale) {
 176     assert(scale != no_scale, "");
 177     assert(((1 << (int)times_1) == 1 &&
 178             (1 << (int)times_2) == 2 &&
 179             (1 << (int)times_4) == 4 &&
 180             (1 << (int)times_8) == 8), "");
 181     return (1 << (int)scale);
 182   }
 183 
 184  private:
 185   Register         _base;
 186   Register         _index;
 187   ScaleFactor      _scale;
 188   int              _disp;
 189   RelocationHolder _rspec;
 190 
 191   // Easily misused constructors make them private
 192   // %%% can we make these go away?
 193   NOT_LP64(Address(address loc, RelocationHolder spec);)
 194   Address(int disp, address loc, relocInfo::relocType rtype);
 195   Address(int disp, address loc, RelocationHolder spec);
 196 
 197  public:
 198 
 199  int disp() { return _disp; }
 200   // creation
 201   Address()
 202     : _base(noreg),
 203       _index(noreg),
 204       _scale(no_scale),
 205       _disp(0) {
 206   }
 207 
 208   // No default displacement otherwise Register can be implicitly
 209   // converted to 0(Register) which is quite a different animal.
 210 
 211   Address(Register base, int disp)
 212     : _base(base),
 213       _index(noreg),
 214       _scale(no_scale),
 215       _disp(disp) {
 216   }
 217 
 218   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 219     : _base (base),
 220       _index(index),
 221       _scale(scale),
 222       _disp (disp) {
 223     assert(!index->is_valid() == (scale == Address::no_scale),
 224            "inconsistent address");
 225   }
 226 
 227   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 228     : _base (base),
 229       _index(index.register_or_noreg()),
 230       _scale(scale),
 231       _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
 232     if (!index.is_register())  scale = Address::no_scale;
 233     assert(!_index->is_valid() == (scale == Address::no_scale),
 234            "inconsistent address");
 235   }
 236 
 237   Address plus_disp(int disp) const {
 238     Address a = (*this);
 239     a._disp += disp;
 240     return a;
 241   }
 242   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 243     Address a = (*this);
 244     a._disp += disp.constant_or_zero() * scale_size(scale);
 245     if (disp.is_register()) {
 246       assert(!a.index()->is_valid(), "competing indexes");
 247       a._index = disp.as_register();
 248       a._scale = scale;
 249     }
 250     return a;
 251   }
 252   bool is_same_address(Address a) const {
 253     // disregard _rspec
 254     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 255   }
 256 
 257   // The following two overloads are used in connection with the
 258   // ByteSize type (see sizes.hpp).  They simplify the use of
 259   // ByteSize'd arguments in assembly code. Note that their equivalent
 260   // for the optimized build are the member functions with int disp
 261   // argument since ByteSize is mapped to an int type in that case.
 262   //
 263   // Note: DO NOT introduce similar overloaded functions for WordSize
 264   // arguments as in the optimized mode, both ByteSize and WordSize
 265   // are mapped to the same type and thus the compiler cannot make a
 266   // distinction anymore (=> compiler errors).
 267 
 268 #ifdef ASSERT
 269   Address(Register base, ByteSize disp)
 270     : _base(base),
 271       _index(noreg),
 272       _scale(no_scale),
 273       _disp(in_bytes(disp)) {
 274   }
 275 
 276   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 277     : _base(base),
 278       _index(index),
 279       _scale(scale),
 280       _disp(in_bytes(disp)) {
 281     assert(!index->is_valid() == (scale == Address::no_scale),
 282            "inconsistent address");
 283   }
 284 
 285   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 286     : _base (base),
 287       _index(index.register_or_noreg()),
 288       _scale(scale),
 289       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
 290     if (!index.is_register())  scale = Address::no_scale;
 291     assert(!_index->is_valid() == (scale == Address::no_scale),
 292            "inconsistent address");
 293   }
 294 
 295 #endif // ASSERT
 296 
 297   // accessors
 298   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 299   Register    base()             const { return _base;  }
 300   Register    index()            const { return _index; }
 301   ScaleFactor scale()            const { return _scale; }
 302   int         disp()             const { return _disp;  }
 303 
 304   // Convert the raw encoding form into the form expected by the constructor for
 305   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 306   // that to noreg for the Address constructor.
 307   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 308 
 309   static Address make_array(ArrayAddress);
 310 
 311  private:
 312   bool base_needs_rex() const {
 313     return _base != noreg && _base->encoding() >= 8;
 314   }
 315 
 316   bool index_needs_rex() const {
 317     return _index != noreg &&_index->encoding() >= 8;
 318   }
 319 
 320   relocInfo::relocType reloc() const { return _rspec.type(); }
 321 
 322   friend class Assembler;
 323   friend class MacroAssembler;
 324   friend class LIR_Assembler; // base/index/scale/disp
 325 };
 326 
 327 //
 328 // AddressLiteral has been split out from Address because operands of this type
 329 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 330 // the few instructions that need to deal with address literals are unique and the
 331 // MacroAssembler does not have to implement every instruction in the Assembler
 332 // in order to search for address literals that may need special handling depending
 333 // on the instruction and the platform. As small step on the way to merging i486/amd64
 334 // directories.
 335 //
 336 class AddressLiteral {
 337   friend class ArrayAddress;
 338   RelocationHolder _rspec;
 339   // Typically we use AddressLiterals we want to use their rval
 340   // However in some situations we want the lval (effect address) of the item.
 341   // We provide a special factory for making those lvals.
 342   bool _is_lval;
 343 
 344   // If the target is far we'll need to load the ea of this to
 345   // a register to reach it. Otherwise if near we can do rip
 346   // relative addressing.
 347 
 348   address          _target;
 349 
 350  protected:
 351   // creation
 352   AddressLiteral()
 353     : _is_lval(false),
 354       _target(NULL)
 355   {}
 356 
 357   public:
 358 
 359 
 360   AddressLiteral(address target, relocInfo::relocType rtype);
 361 
 362   AddressLiteral(address target, RelocationHolder const& rspec)
 363     : _rspec(rspec),
 364       _is_lval(false),
 365       _target(target)
 366   {}
 367 
 368   AddressLiteral addr() {
 369     AddressLiteral ret = *this;
 370     ret._is_lval = true;
 371     return ret;
 372   }
 373 
 374 
 375  private:
 376 
 377   address target() { return _target; }
 378   bool is_lval() { return _is_lval; }
 379 
 380   relocInfo::relocType reloc() const { return _rspec.type(); }
 381   const RelocationHolder& rspec() const { return _rspec; }
 382 
 383   friend class Assembler;
 384   friend class MacroAssembler;
 385   friend class Address;
 386   friend class LIR_Assembler;
 387 };
 388 
 389 // Convience classes
 390 class RuntimeAddress: public AddressLiteral {
 391 
 392   public:
 393 
 394   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 395 
 396 };
 397 
 398 class ExternalAddress: public AddressLiteral {
 399  private:
 400   static relocInfo::relocType reloc_for_target(address target) {
 401     // Sometimes ExternalAddress is used for values which aren't
 402     // exactly addresses, like the card table base.
 403     // external_word_type can't be used for values in the first page
 404     // so just skip the reloc in that case.
 405     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 406   }
 407 
 408  public:
 409 
 410   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 411 
 412 };
 413 
 414 class InternalAddress: public AddressLiteral {
 415 
 416   public:
 417 
 418   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 419 
 420 };
 421 
 422 // x86 can do array addressing as a single operation since disp can be an absolute
 423 // address amd64 can't. We create a class that expresses the concept but does extra
 424 // magic on amd64 to get the final result
 425 
 426 class ArrayAddress {
 427   private:
 428 
 429   AddressLiteral _base;
 430   Address        _index;
 431 
 432   public:
 433 
 434   ArrayAddress() {};
 435   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 436   AddressLiteral base() { return _base; }
 437   Address index() { return _index; }
 438 
 439 };
 440 
 441 class InstructionAttr;
 442 
 443 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
 444 // See fxsave and xsave(EVEX enabled) documentation for layout
 445 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
 446 
 447 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 448 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 449 // is what you get. The Assembler is generating code into a CodeBuffer.
 450 
 451 class Assembler : public AbstractAssembler  {
 452   friend class AbstractAssembler; // for the non-virtual hack
 453   friend class LIR_Assembler; // as_Address()
 454   friend class StubGenerator;
 455 
 456  public:
 457   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 458     zero          = 0x4,
 459     notZero       = 0x5,
 460     equal         = 0x4,
 461     notEqual      = 0x5,
 462     less          = 0xc,
 463     lessEqual     = 0xe,
 464     greater       = 0xf,
 465     greaterEqual  = 0xd,
 466     below         = 0x2,
 467     belowEqual    = 0x6,
 468     above         = 0x7,
 469     aboveEqual    = 0x3,
 470     overflow      = 0x0,
 471     noOverflow    = 0x1,
 472     carrySet      = 0x2,
 473     carryClear    = 0x3,
 474     negative      = 0x8,
 475     positive      = 0x9,
 476     parity        = 0xa,
 477     noParity      = 0xb
 478   };
 479 
 480   enum Prefix {
 481     // segment overrides
 482     CS_segment = 0x2e,
 483     SS_segment = 0x36,
 484     DS_segment = 0x3e,
 485     ES_segment = 0x26,
 486     FS_segment = 0x64,
 487     GS_segment = 0x65,
 488 
 489     REX        = 0x40,
 490 
 491     REX_B      = 0x41,
 492     REX_X      = 0x42,
 493     REX_XB     = 0x43,
 494     REX_R      = 0x44,
 495     REX_RB     = 0x45,
 496     REX_RX     = 0x46,
 497     REX_RXB    = 0x47,
 498 
 499     REX_W      = 0x48,
 500 
 501     REX_WB     = 0x49,
 502     REX_WX     = 0x4A,
 503     REX_WXB    = 0x4B,
 504     REX_WR     = 0x4C,
 505     REX_WRB    = 0x4D,
 506     REX_WRX    = 0x4E,
 507     REX_WRXB   = 0x4F,
 508 
 509     VEX_3bytes = 0xC4,
 510     VEX_2bytes = 0xC5,
 511     EVEX_4bytes = 0x62,
 512     Prefix_EMPTY = 0x0
 513   };
 514 
 515   enum VexPrefix {
 516     VEX_B = 0x20,
 517     VEX_X = 0x40,
 518     VEX_R = 0x80,
 519     VEX_W = 0x80
 520   };
 521 
 522   enum ExexPrefix {
 523     EVEX_F  = 0x04,
 524     EVEX_V  = 0x08,
 525     EVEX_Rb = 0x10,
 526     EVEX_X  = 0x40,
 527     EVEX_Z  = 0x80
 528   };
 529 
 530   enum VexSimdPrefix {
 531     VEX_SIMD_NONE = 0x0,
 532     VEX_SIMD_66   = 0x1,
 533     VEX_SIMD_F3   = 0x2,
 534     VEX_SIMD_F2   = 0x3
 535   };
 536 
 537   enum VexOpcode {
 538     VEX_OPCODE_NONE  = 0x0,
 539     VEX_OPCODE_0F    = 0x1,
 540     VEX_OPCODE_0F_38 = 0x2,
 541     VEX_OPCODE_0F_3A = 0x3,
 542     VEX_OPCODE_MASK  = 0x1F
 543   };
 544 
 545   enum AvxVectorLen {
 546     AVX_128bit = 0x0,
 547     AVX_256bit = 0x1,
 548     AVX_512bit = 0x2,
 549     AVX_NoVec  = 0x4
 550   };
 551 
 552   enum EvexTupleType {
 553     EVEX_FV   = 0,
 554     EVEX_HV   = 4,
 555     EVEX_FVM  = 6,
 556     EVEX_T1S  = 7,
 557     EVEX_T1F  = 11,
 558     EVEX_T2   = 13,
 559     EVEX_T4   = 15,
 560     EVEX_T8   = 17,
 561     EVEX_HVM  = 18,
 562     EVEX_QVM  = 19,
 563     EVEX_OVM  = 20,
 564     EVEX_M128 = 21,
 565     EVEX_DUP  = 22,
 566     EVEX_ETUP = 23
 567   };
 568 
 569   enum EvexInputSizeInBits {
 570     EVEX_8bit  = 0,
 571     EVEX_16bit = 1,
 572     EVEX_32bit = 2,
 573     EVEX_64bit = 3,
 574     EVEX_NObit = 4
 575   };
 576 
 577   enum WhichOperand {
 578     // input to locate_operand, and format code for relocations
 579     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 580     disp32_operand = 1,          // embedded 32-bit displacement or address
 581     call32_operand = 2,          // embedded 32-bit self-relative displacement
 582 #ifndef _LP64
 583     _WhichOperand_limit = 3
 584 #else
 585      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 586     _WhichOperand_limit = 4
 587 #endif
 588   };
 589 
 590   // Comparison predicates for integral types & FP types when using SSE
 591   enum ComparisonPredicate {
 592     eq = 0,
 593     lt = 1,
 594     le = 2,
 595     _false = 3,
 596     neq = 4,
 597     nlt = 5,
 598     nle = 6,
 599     _true = 7
 600   };
 601 
 602   // Comparison predicates for FP types when using AVX
 603   // O means ordered. U is unordered. When using ordered, any NaN comparison is false. Otherwise, it is true.
 604   // S means signaling. Q means non-signaling. When signaling is true, instruction signals #IA on NaN.
 605   enum ComparisonPredicateFP {
 606     EQ_OQ = 0,
 607     LT_OS = 1,
 608     LE_OS = 2,
 609     UNORD_Q = 3,
 610     NEQ_UQ = 4,
 611     NLT_US = 5,
 612     NLE_US = 6,
 613     ORD_Q = 7,
 614     EQ_UQ = 8,
 615     NGE_US = 9,
 616     NGT_US = 0xA,
 617     FALSE_OQ = 0XB,
 618     NEQ_OQ = 0xC,
 619     GE_OS = 0xD,
 620     GT_OS = 0xE,
 621     TRUE_UQ = 0xF,
 622     EQ_OS = 0x10,
 623     LT_OQ = 0x11,
 624     LE_OQ = 0x12,
 625     UNORD_S = 0x13,
 626     NEQ_US = 0x14,
 627     NLT_UQ = 0x15,
 628     NLE_UQ = 0x16,
 629     ORD_S = 0x17,
 630     EQ_US = 0x18,
 631     NGE_UQ = 0x19,
 632     NGT_UQ = 0x1A,
 633     FALSE_OS = 0x1B,
 634     NEQ_OS = 0x1C,
 635     GE_OQ = 0x1D,
 636     GT_OQ = 0x1E,
 637     TRUE_US =0x1F
 638   };
 639 
 640 
 641   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 642   // of instructions are freely declared without the need for wrapping them an ifdef.
 643   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 644   // In the .cpp file the implementations are wrapped so that they are dropped out
 645   // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
 646   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 647   //
 648   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 649   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 650 
 651 private:
 652 
 653   bool _legacy_mode_bw;
 654   bool _legacy_mode_dq;
 655   bool _legacy_mode_vl;
 656   bool _legacy_mode_vlbw;
 657   bool _is_managed;
 658   bool _vector_masking;    // For stub code use only
 659 
 660   class InstructionAttr *_attributes;
 661 
 662   // 64bit prefixes
 663   int prefix_and_encode(int reg_enc, bool byteinst = false);
 664   int prefixq_and_encode(int reg_enc);
 665 
 666   int prefix_and_encode(int dst_enc, int src_enc) {
 667     return prefix_and_encode(dst_enc, false, src_enc, false);
 668   }
 669   int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
 670   int prefixq_and_encode(int dst_enc, int src_enc);
 671 
 672   void prefix(Register reg);
 673   void prefix(Register dst, Register src, Prefix p);
 674   void prefix(Register dst, Address adr, Prefix p);
 675   void prefix(Address adr);
 676   void prefixq(Address adr);
 677 
 678   void prefix(Address adr, Register reg,  bool byteinst = false);
 679   void prefix(Address adr, XMMRegister reg);
 680   void prefixq(Address adr, Register reg);
 681   void prefixq(Address adr, XMMRegister reg);
 682 
 683   void prefetch_prefix(Address src);
 684 
 685   void rex_prefix(Address adr, XMMRegister xreg,
 686                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 687   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 688                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 689 
 690   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 691 
 692   void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
 693                    int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 694 
 695   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 696                   VexSimdPrefix pre, VexOpcode opc,
 697                   InstructionAttr *attributes);
 698 
 699   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 700                              VexSimdPrefix pre, VexOpcode opc,
 701                              InstructionAttr *attributes);
 702 
 703   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
 704                    VexOpcode opc, InstructionAttr *attributes);
 705 
 706   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
 707                              VexOpcode opc, InstructionAttr *attributes);
 708 
 709   // Helper functions for groups of instructions
 710   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 711 
 712   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 713   // Force generation of a 4 byte immediate value even if it fits into 8bit
 714   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 715   void emit_arith(int op1, int op2, Register dst, Register src);
 716 
 717   bool emit_compressed_disp_byte(int &disp);
 718 
 719   void emit_operand(Register reg,
 720                     Register base, Register index, Address::ScaleFactor scale,
 721                     int disp,
 722                     RelocationHolder const& rspec,
 723                     int rip_relative_correction = 0);
 724 
 725   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 726 
 727   // operands that only take the original 32bit registers
 728   void emit_operand32(Register reg, Address adr);
 729 
 730   void emit_operand(XMMRegister reg,
 731                     Register base, Register index, Address::ScaleFactor scale,
 732                     int disp,
 733                     RelocationHolder const& rspec);
 734 
 735   void emit_operand(XMMRegister reg, Address adr);
 736 
 737   void emit_operand(MMXRegister reg, Address adr);
 738 
 739   // workaround gcc (3.2.1-7) bug
 740   void emit_operand(Address adr, MMXRegister reg);
 741 
 742 
 743   // Immediate-to-memory forms
 744   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 745 
 746   void emit_farith(int b1, int b2, int i);
 747 
 748 
 749  protected:
 750   #ifdef ASSERT
 751   void check_relocation(RelocationHolder const& rspec, int format);
 752   #endif
 753 
 754   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 755   void emit_data(jint data, RelocationHolder const& rspec, int format);
 756   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 757   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 758 
 759   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 760 
 761   // These are all easily abused and hence protected
 762 
 763   // 32BIT ONLY SECTION
 764 #ifndef _LP64
 765   // Make these disappear in 64bit mode since they would never be correct
 766   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 767   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 768 
 769   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 770   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 771 
 772   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 773 #else
 774   // 64BIT ONLY SECTION
 775   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 776 
 777   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 778   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 779 
 780   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 781   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 782 #endif // _LP64
 783 
 784   // These are unique in that we are ensured by the caller that the 32bit
 785   // relative in these instructions will always be able to reach the potentially
 786   // 64bit address described by entry. Since they can take a 64bit address they
 787   // don't have the 32 suffix like the other instructions in this class.
 788 
 789   void call_literal(address entry, RelocationHolder const& rspec);
 790   void jmp_literal(address entry, RelocationHolder const& rspec);
 791 
 792   // Avoid using directly section
 793   // Instructions in this section are actually usable by anyone without danger
 794   // of failure but have performance issues that are addressed my enhanced
 795   // instructions which will do the proper thing base on the particular cpu.
 796   // We protect them because we don't trust you...
 797 
 798   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 799   // could cause a partial flag stall since they don't set CF flag.
 800   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 801   // which call inc() & dec() or add() & sub() in accordance with
 802   // the product flag UseIncDec value.
 803 
 804   void decl(Register dst);
 805   void decl(Address dst);
 806   void decq(Register dst);
 807   void decq(Address dst);
 808 
 809   void incl(Register dst);
 810   void incl(Address dst);
 811   void incq(Register dst);
 812   void incq(Address dst);
 813 
 814   // New cpus require use of movsd and movss to avoid partial register stall
 815   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 816   // The selection is done in MacroAssembler::movdbl() and movflt().
 817 
 818   // Move Scalar Single-Precision Floating-Point Values
 819   void movss(XMMRegister dst, Address src);
 820   void movss(XMMRegister dst, XMMRegister src);
 821   void movss(Address dst, XMMRegister src);
 822 
 823   // Move Scalar Double-Precision Floating-Point Values
 824   void movsd(XMMRegister dst, Address src);
 825   void movsd(XMMRegister dst, XMMRegister src);
 826   void movsd(Address dst, XMMRegister src);
 827   void movlpd(XMMRegister dst, Address src);
 828 
 829   // New cpus require use of movaps and movapd to avoid partial register stall
 830   // when moving between registers.
 831   void movaps(XMMRegister dst, XMMRegister src);
 832   void movapd(XMMRegister dst, XMMRegister src);
 833 
 834   // End avoid using directly
 835 
 836 
 837   // Instruction prefixes
 838   void prefix(Prefix p);
 839 
 840   public:
 841 
 842   // Creation
 843   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
 844     init_attributes();
 845   }
 846 
 847   // Decoding
 848   static address locate_operand(address inst, WhichOperand which);
 849   static address locate_next_instruction(address inst);
 850 
 851   // Utilities
 852   static bool is_polling_page_far() NOT_LP64({ return false;});
 853   static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
 854                                          int cur_tuple_type, int in_size_in_bits, int cur_encoding);
 855 
 856   // Generic instructions
 857   // Does 32bit or 64bit as needed for the platform. In some sense these
 858   // belong in macro assembler but there is no need for both varieties to exist
 859 
 860   void init_attributes(void) {
 861     _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
 862     _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
 863     _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
 864     _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
 865     _is_managed = false;
 866     _vector_masking = false;
 867     _attributes = NULL;
 868   }
 869 
 870   void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
 871   void clear_attributes(void) { _attributes = NULL; }
 872 
 873   void set_managed(void) { _is_managed = true; }
 874   void clear_managed(void) { _is_managed = false; }
 875   bool is_managed(void) { return _is_managed; }
 876 
 877   // Following functions are for stub code use only
 878   void set_vector_masking(void) { _vector_masking = true; }
 879   void clear_vector_masking(void) { _vector_masking = false; }
 880   bool is_vector_masking(void) { return _vector_masking; }
 881 
 882   void lea(Register dst, Address src);
 883 
 884   void mov(Register dst, Register src);
 885 
 886   void pusha();
 887   void popa();
 888 
 889   void pushf();
 890   void popf();
 891 
 892   void push(int32_t imm32);
 893 
 894   void push(Register src);
 895 
 896   void pop(Register dst);
 897 
 898   // These are dummies to prevent surprise implicit conversions to Register
 899   void push(void* v);
 900   void pop(void* v);
 901 
 902   // These do register sized moves/scans
 903   void rep_mov();
 904   void rep_stos();
 905   void rep_stosb();
 906   void repne_scan();
 907 #ifdef _LP64
 908   void repne_scanl();
 909 #endif
 910 
 911   // Vanilla instructions in lexical order
 912 
 913   void adcl(Address dst, int32_t imm32);
 914   void adcl(Address dst, Register src);
 915   void adcl(Register dst, int32_t imm32);
 916   void adcl(Register dst, Address src);
 917   void adcl(Register dst, Register src);
 918 
 919   void adcq(Register dst, int32_t imm32);
 920   void adcq(Register dst, Address src);
 921   void adcq(Register dst, Register src);
 922 
 923   void addb(Register dst, Register src);
 924   void addb(Address dst, int imm8);
 925   void addw(Register dst, Register src);
 926   void addw(Address dst, int imm16);
 927 
 928   void addl(Address dst, int32_t imm32);
 929   void addl(Address dst, Register src);
 930   void addl(Register dst, int32_t imm32);
 931   void addl(Register dst, Address src);
 932   void addl(Register dst, Register src);
 933 
 934   void addq(Address dst, int32_t imm32);
 935   void addq(Address dst, Register src);
 936   void addq(Register dst, int32_t imm32);
 937   void addq(Register dst, Address src);
 938   void addq(Register dst, Register src);
 939 
 940 #ifdef _LP64
 941  //Add Unsigned Integers with Carry Flag
 942   void adcxq(Register dst, Register src);
 943 
 944  //Add Unsigned Integers with Overflow Flag
 945   void adoxq(Register dst, Register src);
 946 #endif
 947 
 948   void addr_nop_4();
 949   void addr_nop_5();
 950   void addr_nop_7();
 951   void addr_nop_8();
 952 
 953   // Add Scalar Double-Precision Floating-Point Values
 954   void addsd(XMMRegister dst, Address src);
 955   void addsd(XMMRegister dst, XMMRegister src);
 956 
 957   // Add Scalar Single-Precision Floating-Point Values
 958   void addss(XMMRegister dst, Address src);
 959   void addss(XMMRegister dst, XMMRegister src);
 960 
 961   // AES instructions
 962   void aesdec(XMMRegister dst, Address src);
 963   void aesdec(XMMRegister dst, XMMRegister src);
 964   void aesdeclast(XMMRegister dst, Address src);
 965   void aesdeclast(XMMRegister dst, XMMRegister src);
 966   void aesenc(XMMRegister dst, Address src);
 967   void aesenc(XMMRegister dst, XMMRegister src);
 968   void aesenclast(XMMRegister dst, Address src);
 969   void aesenclast(XMMRegister dst, XMMRegister src);
 970 
 971   void andb(Register dst, Register src);
 972   void andw(Register dst, Register src);
 973 
 974   void andl(Address  dst, int32_t imm32);
 975   void andl(Register dst, int32_t imm32);
 976   void andl(Register dst, Address src);
 977   void andl(Register dst, Register src);
 978 
 979   void andq(Address  dst, int32_t imm32);
 980   void andq(Register dst, int32_t imm32);
 981   void andq(Register dst, Address src);
 982   void andq(Register dst, Register src);
 983 
 984   // BMI instructions
 985   void andnl(Register dst, Register src1, Register src2);
 986   void andnl(Register dst, Register src1, Address src2);
 987   void andnq(Register dst, Register src1, Register src2);
 988   void andnq(Register dst, Register src1, Address src2);
 989 
 990   void blsil(Register dst, Register src);
 991   void blsil(Register dst, Address src);
 992   void blsiq(Register dst, Register src);
 993   void blsiq(Register dst, Address src);
 994 
 995   void blsmskl(Register dst, Register src);
 996   void blsmskl(Register dst, Address src);
 997   void blsmskq(Register dst, Register src);
 998   void blsmskq(Register dst, Address src);
 999 
1000   void blsrl(Register dst, Register src);
1001   void blsrl(Register dst, Address src);
1002   void blsrq(Register dst, Register src);
1003   void blsrq(Register dst, Address src);
1004 
1005   void bsfl(Register dst, Register src);
1006   void bsrl(Register dst, Register src);
1007 
1008 #ifdef _LP64
1009   void bsfq(Register dst, Register src);
1010   void bsrq(Register dst, Register src);
1011 #endif
1012 
1013   void bswapl(Register reg);
1014 
1015   void bswapq(Register reg);
1016 
1017   void call(Label& L, relocInfo::relocType rtype);
1018   void call(Register reg);  // push pc; pc <- reg
1019   void call(Address adr);   // push pc; pc <- adr
1020 
1021   void cdql();
1022 
1023   void cdqq();
1024 
1025   void cld();
1026 
1027   void clflush(Address adr);
1028 
1029   void cmovl(Condition cc, Register dst, Register src);
1030   void cmovl(Condition cc, Register dst, Address src);
1031 
1032   void cmovq(Condition cc, Register dst, Register src);
1033   void cmovq(Condition cc, Register dst, Address src);
1034 
1035 
1036   void cmpb(Address dst, int imm8);
1037 
1038   void cmpl(Address dst, int32_t imm32);
1039 
1040   void cmpl(Register dst, int32_t imm32);
1041   void cmpl(Register dst, Register src);
1042   void cmpl(Register dst, Address src);
1043 
1044   void cmpq(Address dst, int32_t imm32);
1045   void cmpq(Address dst, Register src);
1046 
1047   void cmpq(Register dst, int32_t imm32);
1048   void cmpq(Register dst, Register src);
1049   void cmpq(Register dst, Address src);
1050 
1051   // these are dummies used to catch attempting to convert NULL to Register
1052   void cmpl(Register dst, void* junk); // dummy
1053   void cmpq(Register dst, void* junk); // dummy
1054 
1055   void cmpw(Address dst, int imm16);
1056 
1057   void cmpxchg8 (Address adr);
1058 
1059   void cmpxchgb(Register reg, Address adr);
1060   void cmpxchgl(Register reg, Address adr);
1061 
1062   void cmpxchgq(Register reg, Address adr);
1063 
1064   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1065   void comisd(XMMRegister dst, Address src);
1066   void comisd(XMMRegister dst, XMMRegister src);
1067 
1068   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1069   void comiss(XMMRegister dst, Address src);
1070   void comiss(XMMRegister dst, XMMRegister src);
1071 
1072   // Identify processor type and features
1073   void cpuid();
1074 
1075   // CRC32C
1076   void crc32(Register crc, Register v, int8_t sizeInBytes);
1077   void crc32(Register crc, Address adr, int8_t sizeInBytes);
1078 
1079   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1080   void cvtsd2ss(XMMRegister dst, XMMRegister src);
1081   void cvtsd2ss(XMMRegister dst, Address src);
1082 
1083   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1084   void cvtsi2sdl(XMMRegister dst, Register src);
1085   void cvtsi2sdl(XMMRegister dst, Address src);
1086   void cvtsi2sdq(XMMRegister dst, Register src);
1087   void cvtsi2sdq(XMMRegister dst, Address src);
1088 
1089   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1090   void cvtsi2ssl(XMMRegister dst, Register src);
1091   void cvtsi2ssl(XMMRegister dst, Address src);
1092   void cvtsi2ssq(XMMRegister dst, Register src);
1093   void cvtsi2ssq(XMMRegister dst, Address src);
1094 
1095   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1096   void cvtdq2pd(XMMRegister dst, XMMRegister src);
1097   void vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len);
1098 
1099   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1100   void cvtdq2ps(XMMRegister dst, XMMRegister src);
1101   void vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len);
1102 
1103   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1104   void cvtss2sd(XMMRegister dst, XMMRegister src);
1105   void cvtss2sd(XMMRegister dst, Address src);
1106 
1107   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1108   void cvttsd2sil(Register dst, Address src);
1109   void cvttsd2sil(Register dst, XMMRegister src);
1110   void cvttsd2siq(Register dst, XMMRegister src);
1111 
1112   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1113   void cvttss2sil(Register dst, XMMRegister src);
1114   void cvttss2siq(Register dst, XMMRegister src);
1115 
1116   // Convert vector double to int
1117   void cvttpd2dq(XMMRegister dst, XMMRegister src);
1118 
1119   // Convert vector float and double
1120   void vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len);
1121   void evcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len);
1122   void vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len);
1123   void evcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len);
1124 
1125   // Convert vector long to vector FP
1126   void evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len);
1127   void evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len);
1128 
1129   // Evex casts with truncation
1130   void evpmovwb(XMMRegister dst, XMMRegister src, int vector_len);
1131   void evpmovdw(XMMRegister dst, XMMRegister src, int vector_len);
1132   void evpmovdb(XMMRegister dst, XMMRegister src, int vector_len);
1133   void evpmovqd(XMMRegister dst, XMMRegister src, int vector_len);
1134   void evpmovqb(XMMRegister dst, XMMRegister src, int vector_len);
1135   void evpmovqw(XMMRegister dst, XMMRegister src, int vector_len);
1136 
1137   //Abs of packed Integer values
1138   void pabsb(XMMRegister dst, XMMRegister src);
1139   void pabsw(XMMRegister dst, XMMRegister src);
1140   void pabsd(XMMRegister dst, XMMRegister src);
1141   void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1142   void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1143   void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1144   void evpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1145   void evpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1146   void evpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1147   void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);
1148 
1149   // Divide Scalar Double-Precision Floating-Point Values
1150   void divsd(XMMRegister dst, Address src);
1151   void divsd(XMMRegister dst, XMMRegister src);
1152 
1153   // Divide Scalar Single-Precision Floating-Point Values
1154   void divss(XMMRegister dst, Address src);
1155   void divss(XMMRegister dst, XMMRegister src);
1156 
1157   void emms();
1158 
1159   void fabs();
1160 
1161   void fadd(int i);
1162 
1163   void fadd_d(Address src);
1164   void fadd_s(Address src);
1165 
1166   // "Alternate" versions of x87 instructions place result down in FPU
1167   // stack instead of on TOS
1168 
1169   void fadda(int i); // "alternate" fadd
1170   void faddp(int i = 1);
1171 
1172   void fchs();
1173 
1174   void fcom(int i);
1175 
1176   void fcomp(int i = 1);
1177   void fcomp_d(Address src);
1178   void fcomp_s(Address src);
1179 
1180   void fcompp();
1181 
1182   void fcos();
1183 
1184   void fdecstp();
1185 
1186   void fdiv(int i);
1187   void fdiv_d(Address src);
1188   void fdivr_s(Address src);
1189   void fdiva(int i);  // "alternate" fdiv
1190   void fdivp(int i = 1);
1191 
1192   void fdivr(int i);
1193   void fdivr_d(Address src);
1194   void fdiv_s(Address src);
1195 
1196   void fdivra(int i); // "alternate" reversed fdiv
1197 
1198   void fdivrp(int i = 1);
1199 
1200   void ffree(int i = 0);
1201 
1202   void fild_d(Address adr);
1203   void fild_s(Address adr);
1204 
1205   void fincstp();
1206 
1207   void finit();
1208 
1209   void fist_s (Address adr);
1210   void fistp_d(Address adr);
1211   void fistp_s(Address adr);
1212 
1213   void fld1();
1214 
1215   void fld_d(Address adr);
1216   void fld_s(Address adr);
1217   void fld_s(int index);
1218   void fld_x(Address adr);  // extended-precision (80-bit) format
1219 
1220   void fldcw(Address src);
1221 
1222   void fldenv(Address src);
1223 
1224   void fldlg2();
1225 
1226   void fldln2();
1227 
1228   void fldz();
1229 
1230   void flog();
1231   void flog10();
1232 
1233   void fmul(int i);
1234 
1235   void fmul_d(Address src);
1236   void fmul_s(Address src);
1237 
1238   void fmula(int i);  // "alternate" fmul
1239 
1240   void fmulp(int i = 1);
1241 
1242   void fnsave(Address dst);
1243 
1244   void fnstcw(Address src);
1245 
1246   void fnstsw_ax();
1247 
1248   void fprem();
1249   void fprem1();
1250 
1251   void frstor(Address src);
1252 
1253   void fsin();
1254 
1255   void fsqrt();
1256 
1257   void fst_d(Address adr);
1258   void fst_s(Address adr);
1259 
1260   void fstp_d(Address adr);
1261   void fstp_d(int index);
1262   void fstp_s(Address adr);
1263   void fstp_x(Address adr); // extended-precision (80-bit) format
1264 
1265   void fsub(int i);
1266   void fsub_d(Address src);
1267   void fsub_s(Address src);
1268 
1269   void fsuba(int i);  // "alternate" fsub
1270 
1271   void fsubp(int i = 1);
1272 
1273   void fsubr(int i);
1274   void fsubr_d(Address src);
1275   void fsubr_s(Address src);
1276 
1277   void fsubra(int i); // "alternate" reversed fsub
1278 
1279   void fsubrp(int i = 1);
1280 
1281   void ftan();
1282 
1283   void ftst();
1284 
1285   void fucomi(int i = 1);
1286   void fucomip(int i = 1);
1287 
1288   void fwait();
1289 
1290   void fxch(int i = 1);
1291 
1292   void fxrstor(Address src);
1293   void xrstor(Address src);
1294 
1295   void fxsave(Address dst);
1296   void xsave(Address dst);
1297 
1298   void fyl2x();
1299   void frndint();
1300   void f2xm1();
1301   void fldl2e();
1302 
1303   void hlt();
1304 
1305   void idivl(Register src);
1306   void divl(Register src); // Unsigned division
1307 
1308 #ifdef _LP64
1309   void idivq(Register src);
1310 #endif
1311 
1312   void imull(Register src);
1313   void imull(Register dst, Register src);
1314   void imull(Register dst, Register src, int value);
1315   void imull(Register dst, Address src);
1316 
1317 #ifdef _LP64
1318   void imulq(Register dst, Register src);
1319   void imulq(Register dst, Register src, int value);
1320   void imulq(Register dst, Address src);
1321 #endif
1322 
1323   // jcc is the generic conditional branch generator to run-
1324   // time routines, jcc is used for branches to labels. jcc
1325   // takes a branch opcode (cc) and a label (L) and generates
1326   // either a backward branch or a forward branch and links it
1327   // to the label fixup chain. Usage:
1328   //
1329   // Label L;      // unbound label
1330   // jcc(cc, L);   // forward branch to unbound label
1331   // bind(L);      // bind label to the current pc
1332   // jcc(cc, L);   // backward branch to bound label
1333   // bind(L);      // illegal: a label may be bound only once
1334   //
1335   // Note: The same Label can be used for forward and backward branches
1336   // but it may be bound only once.
1337 
1338   void jcc(Condition cc, Label& L, bool maybe_short = true);
1339 
1340   // Conditional jump to a 8-bit offset to L.
1341   // WARNING: be very careful using this for forward jumps.  If the label is
1342   // not bound within an 8-bit offset of this instruction, a run-time error
1343   // will occur.
1344   void jccb(Condition cc, Label& L);
1345 
1346   void jmp(Address entry);    // pc <- entry
1347 
1348   // Label operations & relative jumps (PPUM Appendix D)
1349   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1350 
1351   void jmp(Register entry); // pc <- entry
1352 
1353   // Unconditional 8-bit offset jump to L.
1354   // WARNING: be very careful using this for forward jumps.  If the label is
1355   // not bound within an 8-bit offset of this instruction, a run-time error
1356   // will occur.
1357   void jmpb(Label& L);
1358 
1359   void ldmxcsr( Address src );
1360 
1361   void leal(Register dst, Address src);
1362 
1363   void leaq(Register dst, Address src);
1364 
1365   void lfence();
1366 
1367   void lock();
1368 
1369   void lzcntl(Register dst, Register src);
1370 
1371 #ifdef _LP64
1372   void lzcntq(Register dst, Register src);
1373 #endif
1374 
1375   enum Membar_mask_bits {
1376     StoreStore = 1 << 3,
1377     LoadStore  = 1 << 2,
1378     StoreLoad  = 1 << 1,
1379     LoadLoad   = 1 << 0
1380   };
1381 
1382   // Serializes memory and blows flags
1383   void membar(Membar_mask_bits order_constraint) {
1384     if (os::is_MP()) {
1385       // We only have to handle StoreLoad
1386       if (order_constraint & StoreLoad) {
1387         // All usable chips support "locked" instructions which suffice
1388         // as barriers, and are much faster than the alternative of
1389         // using cpuid instruction. We use here a locked add [esp-C],0.
1390         // This is conveniently otherwise a no-op except for blowing
1391         // flags, and introducing a false dependency on target memory
1392         // location. We can't do anything with flags, but we can avoid
1393         // memory dependencies in the current method by locked-adding
1394         // somewhere else on the stack. Doing [esp+C] will collide with
1395         // something on stack in current method, hence we go for [esp-C].
1396         // It is convenient since it is almost always in data cache, for
1397         // any small C.  We need to step back from SP to avoid data
1398         // dependencies with other things on below SP (callee-saves, for
1399         // example). Without a clear way to figure out the minimal safe
1400         // distance from SP, it makes sense to step back the complete
1401         // cache line, as this will also avoid possible second-order effects
1402         // with locked ops against the cache line. Our choice of offset
1403         // is bounded by x86 operand encoding, which should stay within
1404         // [-128; +127] to have the 8-byte displacement encoding.
1405         //
1406         // Any change to this code may need to revisit other places in
1407         // the code where this idiom is used, in particular the
1408         // orderAccess code.
1409 
1410         int offset = -VM_Version::L1_line_size();
1411         if (offset < -128) {
1412           offset = -128;
1413         }
1414 
1415         lock();
1416         addl(Address(rsp, offset), 0);// Assert the lock# signal here
1417       }
1418     }
1419   }
1420 
1421   void mfence();
1422 
1423   // Moves
1424 
1425   void mov64(Register dst, int64_t imm64);
1426 
1427   void movb(Address dst, Register src);
1428   void movb(Address dst, int imm8);
1429   void movb(Register dst, Address src);
1430 
1431   void movddup(XMMRegister dst, XMMRegister src);
1432 
1433   void kmovbl(KRegister dst, Register src);
1434   void kmovbl(Register dst, KRegister src);
1435   void kmovwl(KRegister dst, Register src);
1436   void kmovwl(KRegister dst, Address src);
1437   void kmovwl(Register dst, KRegister src);
1438   void kmovdl(KRegister dst, Register src);
1439   void kmovdl(Register dst, KRegister src);
1440   void kmovql(KRegister dst, KRegister src);
1441   void kmovql(Address dst, KRegister src);
1442   void kmovql(KRegister dst, Address src);
1443   void kmovql(KRegister dst, Register src);
1444   void kmovql(Register dst, KRegister src);
1445 
1446   void knotwl(KRegister dst, KRegister src);
1447 
1448   void kortestbl(KRegister dst, KRegister src);
1449   void kortestwl(KRegister dst, KRegister src);
1450   void kortestdl(KRegister dst, KRegister src);
1451   void kortestql(KRegister dst, KRegister src);
1452 
1453   void ktestq(KRegister src1, KRegister src2);
1454   void ktestd(KRegister src1, KRegister src2);
1455 
1456   void ktestql(KRegister dst, KRegister src);
1457 
1458   void movdl(XMMRegister dst, Register src);
1459   void movdl(Register dst, XMMRegister src);
1460   void movdl(XMMRegister dst, Address src);
1461   void movdl(Address dst, XMMRegister src);
1462 
1463   // Move Double Quadword
1464   void movdq(XMMRegister dst, Register src);
1465   void movdq(Register dst, XMMRegister src);
1466 
1467   // Move Aligned Double Quadword
1468   void movdqa(XMMRegister dst, XMMRegister src);
1469   void movdqa(XMMRegister dst, Address src);
1470 
1471   // Move Unaligned Double Quadword
1472   void movdqu(Address     dst, XMMRegister src);
1473   void movdqu(XMMRegister dst, Address src);
1474   void movdqu(XMMRegister dst, XMMRegister src);
1475 
1476   // Move Unaligned 256bit Vector
1477   void vmovdqu(Address dst, XMMRegister src);
1478   void vmovdqu(XMMRegister dst, Address src);
1479   void vmovdqu(XMMRegister dst, XMMRegister src);
1480 
1481    // Move Unaligned 512bit Vector
1482   void evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len);
1483   void evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len);
1484   void evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len);
1485   void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1486   void evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len);
1487   void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1488   void evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len);
1489   void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1490   void evmovdqul(Address dst, XMMRegister src, int vector_len);
1491   void evmovdqul(XMMRegister dst, Address src, int vector_len);
1492   void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1493   void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1494   void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1495   void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1496   void evmovdquq(Address dst, XMMRegister src, int vector_len);
1497   void evmovdquq(XMMRegister dst, Address src, int vector_len);
1498   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1499   void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1500   void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1501   void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1502 
1503   // Move lower 64bit to high 64bit in 128bit register
1504   void movlhps(XMMRegister dst, XMMRegister src);
1505 
1506   void movl(Register dst, int32_t imm32);
1507   void movl(Address dst, int32_t imm32);
1508   void movl(Register dst, Register src);
1509   void movl(Register dst, Address src);
1510   void movl(Address dst, Register src);
1511 
1512   // These dummies prevent using movl from converting a zero (like NULL) into Register
1513   // by giving the compiler two choices it can't resolve
1514 
1515   void movl(Address  dst, void* junk);
1516   void movl(Register dst, void* junk);
1517 
1518 #ifdef _LP64
1519   void movq(Register dst, Register src);
1520   void movq(Register dst, Address src);
1521   void movq(Address  dst, Register src);
1522 #endif
1523 
1524   void movq(Address     dst, MMXRegister src );
1525   void movq(MMXRegister dst, Address src );
1526 
1527 #ifdef _LP64
1528   // These dummies prevent using movq from converting a zero (like NULL) into Register
1529   // by giving the compiler two choices it can't resolve
1530 
1531   void movq(Address  dst, void* dummy);
1532   void movq(Register dst, void* dummy);
1533 #endif
1534 
1535   // Move Quadword
1536   void movq(Address     dst, XMMRegister src);
1537   void movq(XMMRegister dst, Address src);
1538   void movq(Register dst, XMMRegister src);
1539   void movq(XMMRegister dst, Register src);
1540 
1541   void movsbl(Register dst, Address src);
1542   void movsbl(Register dst, Register src);
1543 
1544 #ifdef _LP64
1545   void movsbq(Register dst, Address src);
1546   void movsbq(Register dst, Register src);
1547 
1548   // Move signed 32bit immediate to 64bit extending sign
1549   void movslq(Address  dst, int32_t imm64);
1550   void movslq(Register dst, int32_t imm64);
1551 
1552   void movslq(Register dst, Address src);
1553   void movslq(Register dst, Register src);
1554   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1555 #endif
1556 
1557   void movswl(Register dst, Address src);
1558   void movswl(Register dst, Register src);
1559 
1560 #ifdef _LP64
1561   void movswq(Register dst, Address src);
1562   void movswq(Register dst, Register src);
1563 #endif
1564 
1565   void movw(Address dst, int imm16);
1566   void movw(Register dst, Address src);
1567   void movw(Address dst, Register src);
1568 
1569   void movzbl(Register dst, Address src);
1570   void movzbl(Register dst, Register src);
1571 
1572 #ifdef _LP64
1573   void movzbq(Register dst, Address src);
1574   void movzbq(Register dst, Register src);
1575 #endif
1576 
1577   void movzwl(Register dst, Address src);
1578   void movzwl(Register dst, Register src);
1579 
1580 #ifdef _LP64
1581   void movzwq(Register dst, Address src);
1582   void movzwq(Register dst, Register src);
1583 #endif
1584 
1585   // Unsigned multiply with RAX destination register
1586   void mull(Address src);
1587   void mull(Register src);
1588 
1589 #ifdef _LP64
1590   void mulq(Address src);
1591   void mulq(Register src);
1592   void mulxq(Register dst1, Register dst2, Register src);
1593 #endif
1594 
1595   // Multiply Scalar Double-Precision Floating-Point Values
1596   void mulsd(XMMRegister dst, Address src);
1597   void mulsd(XMMRegister dst, XMMRegister src);
1598 
1599   // Multiply Scalar Single-Precision Floating-Point Values
1600   void mulss(XMMRegister dst, Address src);
1601   void mulss(XMMRegister dst, XMMRegister src);
1602 
1603   void negl(Register dst);
1604 
1605 #ifdef _LP64
1606   void negq(Register dst);
1607 #endif
1608 
1609   void nop(int i = 1);
1610 
1611   void notl(Register dst);
1612 
1613 #ifdef _LP64
1614   void notq(Register dst);
1615 #endif
1616 
1617   void orl(Address dst, int32_t imm32);
1618   void orl(Register dst, int32_t imm32);
1619   void orl(Register dst, Address src);
1620   void orl(Register dst, Register src);
1621   void orl(Address dst, Register src);
1622 
1623   void orq(Address dst, int32_t imm32);
1624   void orq(Register dst, int32_t imm32);
1625   void orq(Register dst, Address src);
1626   void orq(Register dst, Register src);
1627 
1628   // Pack with unsigned saturation
1629   void packuswb(XMMRegister dst, XMMRegister src);
1630   void packuswb(XMMRegister dst, Address src);
1631   void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1632   void vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1633 
1634   // Permutations
1635   void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1636   void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1637   void vpermd(XMMRegister dst,  XMMRegister nds, XMMRegister src);
1638   void vpermd(XMMRegister dst,  XMMRegister nds, Address src);
1639   void vperm2i128(XMMRegister dst,  XMMRegister nds, XMMRegister src, int imm8);
1640   void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1641   void vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1642   void vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1643 
1644   void pause();
1645 
1646   // Undefined Instruction
1647   void ud2();
1648 
1649   // SSE4.2 string instructions
1650   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1651   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1652 
1653   void pcmpeqb(XMMRegister dst, XMMRegister src);
1654   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1655   void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1656   void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1657   void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1658 
1659   void vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1660   void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1661   void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1662 
1663   void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1664   void evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate of, int vector_len);
1665   void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);
1666 
1667   void pcmpeqw(XMMRegister dst, XMMRegister src);
1668   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1669   void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1670   void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1671 
1672   void vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1673 
1674   void pcmpeqd(XMMRegister dst, XMMRegister src);
1675   void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1676   void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len);
1677   void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1678 
1679   void pcmpeqq(XMMRegister dst, XMMRegister src);
1680   void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1681   void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1682   void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1683 
1684   void pcmpgtq(XMMRegister dst, XMMRegister src);
1685   void vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1686 
1687   void pmovmskb(Register dst, XMMRegister src);
1688   void vpmovmskb(Register dst, XMMRegister src);
1689 
1690   // SSE 4.1 extract
1691   void pextrd(Register dst, XMMRegister src, int imm8);
1692   void pextrq(Register dst, XMMRegister src, int imm8);
1693   void pextrd(Address dst, XMMRegister src, int imm8);
1694   void pextrq(Address dst, XMMRegister src, int imm8);
1695   void pextrb(Register dst, XMMRegister src, int imm8);
1696   void pextrb(Address dst, XMMRegister src, int imm8);
1697   // SSE 2 extract
1698   void pextrw(Register dst, XMMRegister src, int imm8);
1699   void pextrw(Address dst, XMMRegister src, int imm8);
1700 
1701   // SSE 4.1 insert
1702   void pinsrd(XMMRegister dst, Register src, int imm8);
1703   void pinsrq(XMMRegister dst, Register src, int imm8);
1704   void pinsrd(XMMRegister dst, Address src, int imm8);
1705   void pinsrq(XMMRegister dst, Address src, int imm8);
1706   void pinsrb(XMMRegister dst, Address src, int imm8);
1707   // SSE 2 insert
1708   void pinsrw(XMMRegister dst, Register src, int imm8);
1709   void pinsrw(XMMRegister dst, Address src, int imm8);
1710 
1711   // Zero extend moves
1712   void pmovzxbw(XMMRegister dst, XMMRegister src);
1713   void pmovzxbw(XMMRegister dst, Address src);
1714   void vpmovzxbw( XMMRegister dst, Address src, int vector_len);
1715   void pmovzxdq(XMMRegister dst, XMMRegister src);
1716   void vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len);
1717   void vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len);
1718   void vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len);
1719   void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1720 
1721   // Sign extend moves
1722   void pmovsxbw(XMMRegister dst, XMMRegister src);
1723   void pmovsxbd(XMMRegister dst, XMMRegister src);
1724   void pmovsxbq(XMMRegister dst, XMMRegister src);
1725   void vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len);
1726   void vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len);
1727   void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
1728   void vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len);
1729   void vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len);
1730   void vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len);
1731 
1732   void evpmovwb(Address dst, XMMRegister src, int vector_len);
1733   void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
1734 
1735 #ifndef _LP64 // no 32bit push/pop on amd64
1736   void popl(Address dst);
1737 #endif
1738 
1739 #ifdef _LP64
1740   void popq(Address dst);
1741 #endif
1742 
1743   void popcntl(Register dst, Address src);
1744   void popcntl(Register dst, Register src);
1745 
1746   void vpopcntd(XMMRegister dst, XMMRegister src, int vector_len);
1747 
1748 #ifdef _LP64
1749   void popcntq(Register dst, Address src);
1750   void popcntq(Register dst, Register src);
1751 #endif
1752 
1753   // Prefetches (SSE, SSE2, 3DNOW only)
1754 
1755   void prefetchnta(Address src);
1756   void prefetchr(Address src);
1757   void prefetcht0(Address src);
1758   void prefetcht1(Address src);
1759   void prefetcht2(Address src);
1760   void prefetchw(Address src);
1761 
1762   // Shuffle Bytes
1763   void pshufb(XMMRegister dst, XMMRegister src);
1764   void pshufb(XMMRegister dst, Address src);
1765   void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1766 
1767   // Shuffle Packed Doublewords
1768   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1769   void pshufd(XMMRegister dst, Address src,     int mode);
1770   void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1771 
1772   // Shuffle Packed Low Words
1773   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1774   void pshuflw(XMMRegister dst, Address src,     int mode);
1775 
1776   // Shift Right by bytes Logical DoubleQuadword Immediate
1777   void psrldq(XMMRegister dst, int shift);
1778   // Shift Left by bytes Logical DoubleQuadword Immediate
1779   void pslldq(XMMRegister dst, int shift);
1780 
1781   // Logical Compare 128bit
1782   void ptest(XMMRegister dst, XMMRegister src);
1783   void ptest(XMMRegister dst, Address src);
1784   // Logical Compare 256bit
1785   void vptest(XMMRegister dst, XMMRegister src);
1786   void vptest(XMMRegister dst, Address src);
1787 
1788   // Vector compare
1789   void vptest(XMMRegister dst, XMMRegister src, int vector_len);
1790 
1791   // Interleave Low Bytes
1792   void punpcklbw(XMMRegister dst, XMMRegister src);
1793   void punpcklbw(XMMRegister dst, Address src);
1794 
1795   // Interleave Low Doublewords
1796   void punpckldq(XMMRegister dst, XMMRegister src);
1797   void punpckldq(XMMRegister dst, Address src);
1798 
1799   // Interleave Low Quadwords
1800   void punpcklqdq(XMMRegister dst, XMMRegister src);
1801 
1802 #ifndef _LP64 // no 32bit push/pop on amd64
1803   void pushl(Address src);
1804 #endif
1805 
1806   void pushq(Address src);
1807 
1808   void rcll(Register dst, int imm8);
1809 
1810   void rclq(Register dst, int imm8);
1811 
1812   void rcrq(Register dst, int imm8);
1813 
1814   void rcpps(XMMRegister dst, XMMRegister src);
1815 
1816   void rcpss(XMMRegister dst, XMMRegister src);
1817 
1818   void rdtsc();
1819 
1820   void ret(int imm16);
1821 
1822 #ifdef _LP64
1823   void rorq(Register dst, int imm8);
1824   void rorxq(Register dst, Register src, int imm8);
1825   void rorxd(Register dst, Register src, int imm8);
1826 #endif
1827 
1828   void sahf();
1829 
1830   void sarl(Register dst, int imm8);
1831   void sarl(Register dst);
1832 
1833   void sarq(Register dst, int imm8);
1834   void sarq(Register dst);
1835 
1836   void sbbl(Address dst, int32_t imm32);
1837   void sbbl(Register dst, int32_t imm32);
1838   void sbbl(Register dst, Address src);
1839   void sbbl(Register dst, Register src);
1840 
1841   void sbbq(Address dst, int32_t imm32);
1842   void sbbq(Register dst, int32_t imm32);
1843   void sbbq(Register dst, Address src);
1844   void sbbq(Register dst, Register src);
1845 
1846   void setb(Condition cc, Register dst);
1847 
1848   void palignr(XMMRegister dst, XMMRegister src, int imm8);
1849   void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
1850 
1851   void pblendw(XMMRegister dst, XMMRegister src, int imm8);
1852 
1853   void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
1854   void sha1nexte(XMMRegister dst, XMMRegister src);
1855   void sha1msg1(XMMRegister dst, XMMRegister src);
1856   void sha1msg2(XMMRegister dst, XMMRegister src);
1857   // xmm0 is implicit additional source to the following instruction.
1858   void sha256rnds2(XMMRegister dst, XMMRegister src);
1859   void sha256msg1(XMMRegister dst, XMMRegister src);
1860   void sha256msg2(XMMRegister dst, XMMRegister src);
1861 
1862   void shldl(Register dst, Register src);
1863   void shldl(Register dst, Register src, int8_t imm8);
1864 
1865   void shll(Register dst, int imm8);
1866   void shll(Register dst);
1867 
1868   void shlq(Register dst, int imm8);
1869   void shlq(Register dst);
1870 
1871   void shrdl(Register dst, Register src);
1872 
1873   void shrl(Register dst, int imm8);
1874   void shrl(Register dst);
1875 
1876   void shrq(Register dst, int imm8);
1877   void shrq(Register dst);
1878 
1879   void smovl(); // QQQ generic?
1880 
1881   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1882   void sqrtsd(XMMRegister dst, Address src);
1883   void sqrtsd(XMMRegister dst, XMMRegister src);
1884 
1885   // Compute Square Root of Scalar Single-Precision Floating-Point Value
1886   void sqrtss(XMMRegister dst, Address src);
1887   void sqrtss(XMMRegister dst, XMMRegister src);
1888 
1889   void std();
1890 
1891   void stmxcsr( Address dst );
1892 
1893   void subl(Address dst, int32_t imm32);
1894   void subl(Address dst, Register src);
1895   void subl(Register dst, int32_t imm32);
1896   void subl(Register dst, Address src);
1897   void subl(Register dst, Register src);
1898 
1899   void subq(Address dst, int32_t imm32);
1900   void subq(Address dst, Register src);
1901   void subq(Register dst, int32_t imm32);
1902   void subq(Register dst, Address src);
1903   void subq(Register dst, Register src);
1904 
1905   // Force generation of a 4 byte immediate value even if it fits into 8bit
1906   void subl_imm32(Register dst, int32_t imm32);
1907   void subq_imm32(Register dst, int32_t imm32);
1908 
1909   // Subtract Scalar Double-Precision Floating-Point Values
1910   void subsd(XMMRegister dst, Address src);
1911   void subsd(XMMRegister dst, XMMRegister src);
1912 
1913   // Subtract Scalar Single-Precision Floating-Point Values
1914   void subss(XMMRegister dst, Address src);
1915   void subss(XMMRegister dst, XMMRegister src);
1916 
1917   void testb(Register dst, int imm8);
1918   void testb(Address dst, int imm8);
1919 
1920   void testl(Register dst, int32_t imm32);
1921   void testl(Register dst, Register src);
1922   void testl(Register dst, Address src);
1923 
1924   void testq(Register dst, int32_t imm32);
1925   void testq(Register dst, Register src);
1926 
1927   // BMI - count trailing zeros
1928   void tzcntl(Register dst, Register src);
1929   void tzcntq(Register dst, Register src);
1930 
1931   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1932   void ucomisd(XMMRegister dst, Address src);
1933   void ucomisd(XMMRegister dst, XMMRegister src);
1934 
1935   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1936   void ucomiss(XMMRegister dst, Address src);
1937   void ucomiss(XMMRegister dst, XMMRegister src);
1938 
1939   void xabort(int8_t imm8);
1940 
1941   void xaddb(Address dst, Register src);
1942   void xaddw(Address dst, Register src);
1943   void xaddl(Address dst, Register src);
1944   void xaddq(Address dst, Register src);
1945 
1946   void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1947 
1948   void xchgb(Register reg, Address adr);
1949   void xchgw(Register reg, Address adr);
1950   void xchgl(Register reg, Address adr);
1951   void xchgl(Register dst, Register src);
1952 
1953   void xchgq(Register reg, Address adr);
1954   void xchgq(Register dst, Register src);
1955 
1956   void xend();
1957 
1958   // Get Value of Extended Control Register
1959   void xgetbv();
1960 
1961   void xorl(Register dst, int32_t imm32);
1962   void xorl(Register dst, Address src);
1963   void xorl(Register dst, Register src);
1964 
1965   void xorb(Register dst, Address src);
1966 
1967   void xorq(Register dst, Address src);
1968   void xorq(Register dst, Register src);
1969 
1970   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1971 
1972   // AVX 3-operands scalar instructions (encoded with VEX prefix)
1973 
1974   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1975   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1976   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1977   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1978   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1979   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1980   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1981   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1982   void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1983   void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1984   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1985   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1986   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1987   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1988   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1989   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1990   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1991   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1992 
1993   void shlxl(Register dst, Register src1, Register src2);
1994   void shlxq(Register dst, Register src1, Register src2);
1995 
1996   //====================VECTOR ARITHMETIC=====================================
1997 
1998   // Add Packed Floating-Point Values
1999   void addpd(XMMRegister dst, XMMRegister src);
2000   void addpd(XMMRegister dst, Address src);
2001   void addps(XMMRegister dst, XMMRegister src);
2002   void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2003   void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2004   void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2005   void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2006 
2007   // Subtract Packed Floating-Point Values
2008   void subpd(XMMRegister dst, XMMRegister src);
2009   void subps(XMMRegister dst, XMMRegister src);
2010   void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2011   void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2012   void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2013   void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2014 
2015   // Multiply Packed Floating-Point Values
2016   void mulpd(XMMRegister dst, XMMRegister src);
2017   void mulpd(XMMRegister dst, Address src);
2018   void mulps(XMMRegister dst, XMMRegister src);
2019   void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2020   void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2021   void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2022   void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2023 
2024   void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2025   void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2026   void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2027   void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2028 
2029   // Divide Packed Floating-Point Values
2030   void divpd(XMMRegister dst, XMMRegister src);
2031   void divps(XMMRegister dst, XMMRegister src);
2032   void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2033   void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2034   void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2035   void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2036 
2037   // Sqrt Packed Floating-Point Values
2038   void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
2039   void vsqrtpd(XMMRegister dst, Address src, int vector_len);
2040   void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
2041   void vsqrtps(XMMRegister dst, Address src, int vector_len);
2042 
2043   // Bitwise Logical AND of Packed Floating-Point Values
2044   void andpd(XMMRegister dst, XMMRegister src);
2045   void andps(XMMRegister dst, XMMRegister src);
2046   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2047   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2048   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2049   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2050 
2051   void unpckhpd(XMMRegister dst, XMMRegister src);
2052   void unpcklpd(XMMRegister dst, XMMRegister src);
2053 
2054   // Bitwise Logical XOR of Packed Floating-Point Values
2055   void xorpd(XMMRegister dst, XMMRegister src);
2056   void xorps(XMMRegister dst, XMMRegister src);
2057   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2058   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2059   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2060   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2061 
2062   // Add horizontal packed integers
2063   void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2064   void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2065   void phaddw(XMMRegister dst, XMMRegister src);
2066   void phaddd(XMMRegister dst, XMMRegister src);
2067 
2068   // Add packed integers
2069   void paddb(XMMRegister dst, XMMRegister src);
2070   void paddw(XMMRegister dst, XMMRegister src);
2071   void paddd(XMMRegister dst, XMMRegister src);
2072   void paddd(XMMRegister dst, Address src);
2073   void paddq(XMMRegister dst, XMMRegister src);
2074   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2075   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2076   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2077   void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2078   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2079   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2080   void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2081   void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2082 
2083   // Sub packed integers
2084   void psubb(XMMRegister dst, XMMRegister src);
2085   void psubw(XMMRegister dst, XMMRegister src);
2086   void psubd(XMMRegister dst, XMMRegister src);
2087   void psubq(XMMRegister dst, XMMRegister src);
2088   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2089   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2090   void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2091   void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2092   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2093   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2094   void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2095   void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2096 
2097   // Multiply packed integers (only shorts and ints)
2098   void pmullw(XMMRegister dst, XMMRegister src);
2099   void pmulld(XMMRegister dst, XMMRegister src);
2100   void pmuludq(XMMRegister dst, XMMRegister src);
2101   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2102   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2103   void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2104   void vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2105   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2106   void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2107   void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2108 
2109   // Minimum of packed integers
2110   void pminsb(XMMRegister dst, XMMRegister src);
2111   void vpminsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2112   void pminsw(XMMRegister dst, XMMRegister src);
2113   void vpminsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2114   void pminsd(XMMRegister dst, XMMRegister src);
2115   void vpminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2116   void vpminsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2117   void minps(XMMRegister dst, XMMRegister src);
2118   void vminps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2119   void minpd(XMMRegister dst, XMMRegister src);
2120   void vminpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2121 
2122   // Maximum of packed integers
2123   void pmaxsb(XMMRegister dst, XMMRegister src);
2124   void vpmaxsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2125   void pmaxsw(XMMRegister dst, XMMRegister src);
2126   void vpmaxsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2127   void pmaxsd(XMMRegister dst, XMMRegister src);
2128   void vpmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2129   void vpmaxsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2130   void maxps(XMMRegister dst, XMMRegister src);
2131   void vmaxps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2132   void maxpd(XMMRegister dst, XMMRegister src);
2133   void vmaxpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2134 
2135   // Shift left packed integers
2136   void psllw(XMMRegister dst, int shift);
2137   void pslld(XMMRegister dst, int shift);
2138   void psllq(XMMRegister dst, int shift);
2139   void psllw(XMMRegister dst, XMMRegister shift);
2140   void pslld(XMMRegister dst, XMMRegister shift);
2141   void psllq(XMMRegister dst, XMMRegister shift);
2142   void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2143   void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2144   void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2145   void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2146   void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2147   void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2148 
2149   // Logical shift right packed integers
2150   void psrlw(XMMRegister dst, int shift);
2151   void psrld(XMMRegister dst, int shift);
2152   void psrlq(XMMRegister dst, int shift);
2153   void psrlw(XMMRegister dst, XMMRegister shift);
2154   void psrld(XMMRegister dst, XMMRegister shift);
2155   void psrlq(XMMRegister dst, XMMRegister shift);
2156   void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2157   void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2158   void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2159   void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2160   void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2161   void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2162 
2163   // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2164   void psraw(XMMRegister dst, int shift);
2165   void psrad(XMMRegister dst, int shift);
2166   void psraw(XMMRegister dst, XMMRegister shift);
2167   void psrad(XMMRegister dst, XMMRegister shift);
2168   void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2169   void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2170   void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2171   void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2172 
2173   // Variable shift left packed integers
2174   void vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2175   void vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2176 
2177   // Variable shift right packed integers
2178   void vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2179   void vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2180 
2181   // Variable shift right arithmetic packed integers
2182   void vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2183   void vpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2184 
2185   // And packed integers
2186   void pand(XMMRegister dst, XMMRegister src);
2187   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2188   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2189   void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2190   void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2191 
2192   // Andn packed integers
2193   void pandn(XMMRegister dst, XMMRegister src);
2194 
2195   // Or packed integers
2196   void por(XMMRegister dst, XMMRegister src);
2197   void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2198   void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2199   void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2200 
2201   void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2202   void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2203 
2204   // Xor packed integers
2205   void pxor(XMMRegister dst, XMMRegister src);
2206   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2207   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2208   void vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2209   void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2210 
2211   // vinserti forms
2212   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2213   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2214   void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2215   void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2216   void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2217 
2218   // vinsertf forms
2219   void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2220   void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2221   void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2222   void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2223   void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2224   void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2225 
2226   // vextracti forms
2227   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2228   void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2229   void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2230   void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2231   void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2232   void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2233 
2234   // vextractf forms
2235   void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2236   void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2237   void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2238   void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2239   void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2240   void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2241   void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2242 
2243   // legacy xmm sourced word/dword replicate
2244   void vpbroadcastw(XMMRegister dst, XMMRegister src);
2245   void vpbroadcastd(XMMRegister dst, XMMRegister src);
2246 
2247   // xmm/mem sourced byte/word/dword/qword replicate
2248   void evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2249   void evpbroadcastb(XMMRegister dst, Address src, int vector_len);
2250   void evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2251   void evpbroadcastw(XMMRegister dst, Address src, int vector_len);
2252   void evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2253   void evpbroadcastd(XMMRegister dst, Address src, int vector_len);
2254   void evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2255   void evpbroadcastq(XMMRegister dst, Address src, int vector_len);
2256 
2257   // scalar single/double precision replicate
2258   void evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2259   void evpbroadcastss(XMMRegister dst, Address src, int vector_len);
2260   void evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2261   void evpbroadcastsd(XMMRegister dst, Address src, int vector_len);
2262 
2263   // gpr sourced byte/word/dword/qword replicate
2264   void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2265   void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2266   void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2267   void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2268 
2269   // Carry-Less Multiplication Quadword
2270   void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2271   void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2272 
2273   // AVX instruction which is used to clear upper 128 bits of YMM registers and
2274   // to avoid transaction penalty between AVX and SSE states. There is no
2275   // penalty if legacy SSE instructions are encoded using VEX prefix because
2276   // they always clear upper 128 bits. It should be used before calling
2277   // runtime code and native libraries.
2278   void vzeroupper();
2279 
2280   // Vector double compares
2281   void vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2282   void evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2283                ComparisonPredicateFP comparison, int vector_len);
2284 
2285   // Vector float compares
2286   void vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len);
2287   void evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2288                ComparisonPredicateFP comparison, int vector_len);
2289 
2290   // Vector integer compares
2291   void vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2292   void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2293                int comparison, int vector_len);
2294   void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2295                int comparison, int vector_len);
2296 
2297   // Vector long compares
2298   void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2299                int comparison, int vector_len);
2300   void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2301                int comparison, int vector_len);
2302 
2303   // Vector byte compares
2304   void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2305                int comparison, int vector_len);
2306   void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2307                int comparison, int vector_len);
2308 
2309   // Vector short compares
2310   void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2311                int comparison, int vector_len);
2312   void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2313                int comparison, int vector_len);
2314 
2315   // Vector blends
2316   void blendvps(XMMRegister dst, XMMRegister src);
2317   void blendvpd(XMMRegister dst, XMMRegister src);
2318   void pblendvb(XMMRegister dst, XMMRegister src);
2319   void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
2320   void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2321   void vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
2322   void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
2323   void evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2324   void evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2325   void evpblendmb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2326   void evpblendmw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2327   void evpblendmd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2328   void evpblendmq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2329  protected:
2330   // Next instructions require address alignment 16 bytes SSE mode.
2331   // They should be called only from corresponding MacroAssembler instructions.
2332   void andpd(XMMRegister dst, Address src);
2333   void andps(XMMRegister dst, Address src);
2334   void xorpd(XMMRegister dst, Address src);
2335   void xorps(XMMRegister dst, Address src);
2336 
2337 };
2338 
2339 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2340 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2341 // are applied.
2342 class InstructionAttr {
2343 public:
2344   InstructionAttr(
2345     int vector_len,     // The length of vector to be applied in encoding - for both AVX and EVEX
2346     bool rex_vex_w,     // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2347     bool legacy_mode,   // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2348     bool no_reg_mask,   // when true, k0 is used when EVEX encoding is chosen, else k1 is used under the same condition
2349     bool uses_vl)       // This instruction may have legacy constraints based on vector length for EVEX
2350     :
2351       _avx_vector_len(vector_len),
2352       _rex_vex_w(rex_vex_w),
2353       _rex_vex_w_reverted(false),
2354       _legacy_mode(legacy_mode),
2355       _no_reg_mask(no_reg_mask),
2356       _uses_vl(uses_vl),
2357       _tuple_type(Assembler::EVEX_ETUP),
2358       _input_size_in_bits(Assembler::EVEX_NObit),
2359       _is_evex_instruction(false),
2360       _evex_encoding(0),
2361       _is_clear_context(true),
2362       _is_extended_context(false),
2363       _current_assembler(NULL),
2364       _embedded_opmask_register_specifier(1) { // hard code k1, it will be initialized for now
2365     if (UseAVX < 3) _legacy_mode = true;
2366   }
2367 
2368   ~InstructionAttr() {
2369     if (_current_assembler != NULL) {
2370       _current_assembler->clear_attributes();
2371     }
2372     _current_assembler = NULL;
2373   }
2374 
2375 private:
2376   int  _avx_vector_len;
2377   bool _rex_vex_w;
2378   bool _rex_vex_w_reverted;
2379   bool _legacy_mode;
2380   bool _no_reg_mask;
2381   bool _uses_vl;
2382   int  _tuple_type;
2383   int  _input_size_in_bits;
2384   bool _is_evex_instruction;
2385   int  _evex_encoding;
2386   bool _is_clear_context;
2387   bool _is_extended_context;
2388   int _embedded_opmask_register_specifier;
2389 
2390   Assembler *_current_assembler;
2391 
2392 public:
2393   // query functions for field accessors
2394   int  get_vector_len(void) const { return _avx_vector_len; }
2395   bool is_rex_vex_w(void) const { return _rex_vex_w; }
2396   bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2397   bool is_legacy_mode(void) const { return _legacy_mode; }
2398   bool is_no_reg_mask(void) const { return _no_reg_mask; }
2399   bool uses_vl(void) const { return _uses_vl; }
2400   int  get_tuple_type(void) const { return _tuple_type; }
2401   int  get_input_size(void) const { return _input_size_in_bits; }
2402   int  is_evex_instruction(void) const { return _is_evex_instruction; }
2403   int  get_evex_encoding(void) const { return _evex_encoding; }
2404   bool is_clear_context(void) const { return _is_clear_context; }
2405   bool is_extended_context(void) const { return _is_extended_context; }
2406   int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }
2407 
2408   // Set the vector len manually
2409   void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2410 
2411   // Set revert rex_vex_w for avx encoding
2412   void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2413 
2414   // Set rex_vex_w based on state
2415   void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2416 
2417   // Set the instruction to be encoded in AVX mode
2418   void set_is_legacy_mode(void) { _legacy_mode = true; }
2419 
2420   // Set the current instuction to be encoded as an EVEX instuction
2421   void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2422 
2423   // Internal encoding data used in compressed immediate offset programming
2424   void set_evex_encoding(int value) { _evex_encoding = value; }
2425 
2426   // When the Evex.Z field is set (true), it is used to clear all non directed XMM/YMM/ZMM components.
2427   // This method unsets it so that merge semantics are used instead.
2428   void reset_is_clear_context(void) { _is_clear_context = false; }
2429 
2430   // Map back to current asembler so that we can manage object level assocation
2431   void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2432 
2433   // Address modifiers used for compressed displacement calculation
2434   void set_address_attributes(int tuple_type, int input_size_in_bits) {
2435     if (VM_Version::supports_evex()) {
2436       _tuple_type = tuple_type;
2437       _input_size_in_bits = input_size_in_bits;
2438     }
2439   }
2440 
2441   // Set embedded opmask register specifier.
2442   void set_embedded_opmask_register_specifier(KRegister mask) {
2443     _embedded_opmask_register_specifier = (*mask).encoding() & 0x7;
2444   }
2445 
2446 };
2447 
2448 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP