1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
75
76 // helpers for FPU flag access
77 // tmp is a temporary register, if none is available use noreg
78 void save_rax (Register tmp);
79 void restore_rax(Register tmp);
80
81 public:
82 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
83
84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
85 // The implementation is only non-empty for the InterpreterMacroAssembler,
86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
87 virtual void check_and_handle_popframe(Register java_thread);
88 virtual void check_and_handle_earlyret(Register java_thread);
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // special instructions for EVEX
160 void setvectmask(Register dst, Register src);
161 void restorevectmask();
162
163 // Support optimal SSE move instructions.
164 void movflt(XMMRegister dst, XMMRegister src) {
165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
166 else { movss (dst, src); return; }
167 }
168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
169 void movflt(XMMRegister dst, AddressLiteral src);
170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
171
172 void movdbl(XMMRegister dst, XMMRegister src) {
173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
174 else { movsd (dst, src); return; }
175 }
176
177 void movdbl(XMMRegister dst, AddressLiteral src);
178
179 void movdbl(XMMRegister dst, Address src) {
180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
181 else { movlpd(dst, src); return; }
182 }
183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
184
185 void incrementl(AddressLiteral dst);
186 void incrementl(ArrayAddress dst);
187
188 void incrementq(AddressLiteral dst);
189
190 // Alignment
191 void align(int modulus);
192 void align(int modulus, int target);
193
194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
195 void fat_nop();
196
197 // Stack frame creation/removal
198 void enter();
199 void leave();
200
201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
202 // The pointer will be loaded into the thread register.
203 void get_thread(Register thread);
204
205
206 // Support for VM calls
207 //
208 // It is imperative that all calls into the VM are handled via the call_VM macros.
209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
211
212
213 void call_VM(Register oop_result,
214 address entry_point,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2, Register arg_3,
227 bool check_exceptions = true);
228
229 // Overloadings with last_Java_sp
230 void call_VM(Register oop_result,
231 Register last_java_sp,
232 address entry_point,
233 int number_of_arguments = 0,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 Register arg_1, bool
239 check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2, Register arg_3,
249 bool check_exceptions = true);
250
251 void get_vm_result (Register oop_result, Register thread);
252 void get_vm_result_2(Register metadata_result, Register thread);
253
254 // These always tightly bind to MacroAssembler::call_VM_base
255 // bypassing the virtual implementation
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
261
262 void call_VM_leaf0(address entry_point);
263 void call_VM_leaf(address entry_point,
264 int number_of_arguments = 0);
265 void call_VM_leaf(address entry_point,
266 Register arg_1);
267 void call_VM_leaf(address entry_point,
268 Register arg_1, Register arg_2);
269 void call_VM_leaf(address entry_point,
270 Register arg_1, Register arg_2, Register arg_3);
271
272 // These always tightly bind to MacroAssembler::call_VM_leaf_base
273 // bypassing the virtual implementation
274 void super_call_VM_leaf(address entry_point);
275 void super_call_VM_leaf(address entry_point, Register arg_1);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
279
280 // last Java Frame (fills frame anchor)
281 void set_last_Java_frame(Register thread,
282 Register last_java_sp,
283 Register last_java_fp,
284 address last_java_pc);
285
286 // thread in the default location (r15_thread on 64bit)
287 void set_last_Java_frame(Register last_java_sp,
288 Register last_java_fp,
289 address last_java_pc);
290
291 void reset_last_Java_frame(Register thread, bool clear_fp);
292
293 // thread in the default location (r15_thread on 64bit)
294 void reset_last_Java_frame(bool clear_fp);
295
296 // Stores
297 void store_check(Register obj); // store check for obj - register is destroyed afterwards
298 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
299
300 void resolve_jobject(Register value, Register thread, Register tmp);
301 void clear_jweak_tag(Register possibly_jweak);
302
303 #if INCLUDE_ALL_GCS
304
305 void g1_write_barrier_pre(Register obj,
306 Register pre_val,
307 Register thread,
308 Register tmp,
309 bool tosca_live,
310 bool expand_call);
311
312 void g1_write_barrier_post(Register store_addr,
313 Register new_val,
314 Register thread,
315 Register tmp,
316 Register tmp2);
317
318 #endif // INCLUDE_ALL_GCS
319
320 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
321 void c2bool(Register x);
322
323 // C++ bool manipulation
324
325 void movbool(Register dst, Address src);
326 void movbool(Address dst, bool boolconst);
327 void movbool(Address dst, Register src);
328 void testbool(Register dst);
329
330 void resolve_oop_handle(Register result);
331 void load_mirror(Register mirror, Register method);
332
333 // oop manipulations
334 void load_klass(Register dst, Register src);
335 void store_klass(Register dst, Register src);
336
337 void load_heap_oop(Register dst, Address src);
338 void load_heap_oop_not_null(Register dst, Address src);
339 void store_heap_oop(Address dst, Register src);
340 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
341
342 // Used for storing NULL. All other oop constants should be
343 // stored using routines that take a jobject.
344 void store_heap_oop_null(Address dst);
345
346 void load_prototype_header(Register dst, Register src);
347
348 #ifdef _LP64
349 void store_klass_gap(Register dst, Register src);
350
351 // This dummy is to prevent a call to store_heap_oop from
352 // converting a zero (like NULL) into a Register by giving
353 // the compiler two choices it can't resolve
354
355 void store_heap_oop(Address dst, void* dummy);
356
357 void encode_heap_oop(Register r);
358 void decode_heap_oop(Register r);
359 void encode_heap_oop_not_null(Register r);
360 void decode_heap_oop_not_null(Register r);
361 void encode_heap_oop_not_null(Register dst, Register src);
362 void decode_heap_oop_not_null(Register dst, Register src);
363
364 void set_narrow_oop(Register dst, jobject obj);
365 void set_narrow_oop(Address dst, jobject obj);
366 void cmp_narrow_oop(Register dst, jobject obj);
367 void cmp_narrow_oop(Address dst, jobject obj);
368
369 void encode_klass_not_null(Register r);
370 void decode_klass_not_null(Register r);
371 void encode_klass_not_null(Register dst, Register src);
372 void decode_klass_not_null(Register dst, Register src);
373 void set_narrow_klass(Register dst, Klass* k);
374 void set_narrow_klass(Address dst, Klass* k);
375 void cmp_narrow_klass(Register dst, Klass* k);
376 void cmp_narrow_klass(Address dst, Klass* k);
377
378 // Returns the byte size of the instructions generated by decode_klass_not_null()
379 // when compressed klass pointers are being used.
380 static int instr_size_for_decode_klass_not_null();
381
382 // if heap base register is used - reinit it with the correct value
383 void reinit_heapbase();
384
385 DEBUG_ONLY(void verify_heapbase(const char* msg);)
386
387 #endif // _LP64
388
389 // Int division/remainder for Java
390 // (as idivl, but checks for special case as described in JVM spec.)
391 // returns idivl instruction offset for implicit exception handling
392 int corrected_idivl(Register reg);
393
394 // Long division/remainder for Java
395 // (as idivq, but checks for special case as described in JVM spec.)
396 // returns idivq instruction offset for implicit exception handling
397 int corrected_idivq(Register reg);
398
399 void int3();
400
401 // Long operation macros for a 32bit cpu
402 // Long negation for Java
403 void lneg(Register hi, Register lo);
404
405 // Long multiplication for Java
406 // (destroys contents of eax, ebx, ecx and edx)
407 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
408
409 // Long shifts for Java
410 // (semantics as described in JVM spec.)
411 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
412 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
413
414 // Long compare for Java
415 // (semantics as described in JVM spec.)
416 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
417
418
419 // misc
420
421 // Sign extension
422 void sign_extend_short(Register reg);
423 void sign_extend_byte(Register reg);
424
425 // Division by power of 2, rounding towards 0
426 void division_with_shift(Register reg, int shift_value);
427
428 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
429 //
430 // CF (corresponds to C0) if x < y
431 // PF (corresponds to C2) if unordered
432 // ZF (corresponds to C3) if x = y
433 //
434 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
435 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
436 void fcmp(Register tmp);
437 // Variant of the above which allows y to be further down the stack
438 // and which only pops x and y if specified. If pop_right is
439 // specified then pop_left must also be specified.
440 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
441
442 // Floating-point comparison for Java
443 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
444 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
445 // (semantics as described in JVM spec.)
446 void fcmp2int(Register dst, bool unordered_is_less);
447 // Variant of the above which allows y to be further down the stack
448 // and which only pops x and y if specified. If pop_right is
449 // specified then pop_left must also be specified.
450 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
451
452 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
453 // tmp is a temporary register, if none is available use noreg
454 void fremr(Register tmp);
455
456 // dst = c = a * b + c
457 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
458 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
459
460 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
461 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
462 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
463 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
464
465
466 // same as fcmp2int, but using SSE2
467 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
468 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
469
470 // branch to L if FPU flag C2 is set/not set
471 // tmp is a temporary register, if none is available use noreg
472 void jC2 (Register tmp, Label& L);
473 void jnC2(Register tmp, Label& L);
474
475 // Pop ST (ffree & fincstp combined)
476 void fpop();
477
478 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
479 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
480 void load_float(Address src);
481
482 // Store float value to 'address'. If UseSSE >= 1, the value is stored
483 // from register xmm0. Otherwise, the value is stored from the FPU stack.
484 void store_float(Address dst);
485
486 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
487 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
488 void load_double(Address src);
489
490 // Store double value to 'address'. If UseSSE >= 2, the value is stored
491 // from register xmm0. Otherwise, the value is stored from the FPU stack.
492 void store_double(Address dst);
493
494 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
495 void push_fTOS();
496
497 // pops double TOS element from CPU stack and pushes on FPU stack
498 void pop_fTOS();
499
500 void empty_FPU_stack();
501
502 void push_IU_state();
503 void pop_IU_state();
504
505 void push_FPU_state();
506 void pop_FPU_state();
507
508 void push_CPU_state();
509 void pop_CPU_state();
510
511 // Round up to a power of two
512 void round_to(Register reg, int modulus);
513
514 // Callee saved registers handling
515 void push_callee_saved_registers();
516 void pop_callee_saved_registers();
517
518 // allocation
519 void eden_allocate(
520 Register obj, // result: pointer to object after successful allocation
521 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
522 int con_size_in_bytes, // object size in bytes if known at compile time
523 Register t1, // temp register
524 Label& slow_case // continuation point if fast allocation fails
525 );
526 void tlab_allocate(
527 Register obj, // result: pointer to object after successful allocation
528 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
529 int con_size_in_bytes, // object size in bytes if known at compile time
530 Register t1, // temp register
531 Register t2, // temp register
532 Label& slow_case // continuation point if fast allocation fails
533 );
534 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
535
536 void incr_allocated_bytes(Register thread,
537 Register var_size_in_bytes, int con_size_in_bytes,
538 Register t1 = noreg);
539
540 // interface method calling
541 void lookup_interface_method(Register recv_klass,
542 Register intf_klass,
543 RegisterOrConstant itable_index,
544 Register method_result,
545 Register scan_temp,
546 Label& no_such_interface,
547 bool return_method = true);
548
549 // virtual method calling
550 void lookup_virtual_method(Register recv_klass,
551 RegisterOrConstant vtable_index,
552 Register method_result);
553
554 // Test sub_klass against super_klass, with fast and slow paths.
555
556 // The fast path produces a tri-state answer: yes / no / maybe-slow.
557 // One of the three labels can be NULL, meaning take the fall-through.
558 // If super_check_offset is -1, the value is loaded up from super_klass.
559 // No registers are killed, except temp_reg.
560 void check_klass_subtype_fast_path(Register sub_klass,
561 Register super_klass,
562 Register temp_reg,
563 Label* L_success,
564 Label* L_failure,
565 Label* L_slow_path,
566 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
567
568 // The rest of the type check; must be wired to a corresponding fast path.
569 // It does not repeat the fast path logic, so don't use it standalone.
570 // The temp_reg and temp2_reg can be noreg, if no temps are available.
571 // Updates the sub's secondary super cache as necessary.
572 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
573 void check_klass_subtype_slow_path(Register sub_klass,
574 Register super_klass,
575 Register temp_reg,
576 Register temp2_reg,
577 Label* L_success,
578 Label* L_failure,
579 bool set_cond_codes = false);
580
581 // Simplified, combined version, good for typical uses.
582 // Falls through on failure.
583 void check_klass_subtype(Register sub_klass,
584 Register super_klass,
585 Register temp_reg,
586 Label& L_success);
587
588 // method handles (JSR 292)
589 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
590
591 //----
592 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
593
594 // Debugging
595
596 // only if +VerifyOops
597 // TODO: Make these macros with file and line like sparc version!
598 void verify_oop(Register reg, const char* s = "broken oop");
599 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
600
601 // TODO: verify method and klass metadata (compare against vptr?)
602 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
603 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
604
605 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
606 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
607
608 // only if +VerifyFPU
609 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
610
611 // Verify or restore cpu control state after JNI call
612 void restore_cpu_control_state_after_jni();
613
614 // prints msg, dumps registers and stops execution
615 void stop(const char* msg);
616
617 // prints msg and continues
618 void warn(const char* msg);
619
620 // dumps registers and other state
621 void print_state();
622
623 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
624 static void debug64(char* msg, int64_t pc, int64_t regs[]);
625 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
626 static void print_state64(int64_t pc, int64_t regs[]);
627
628 void os_breakpoint();
629
630 void untested() { stop("untested"); }
631
632 void unimplemented(const char* what = "");
633
634 void should_not_reach_here() { stop("should not reach here"); }
635
636 void print_CPU_state();
637
638 // Stack overflow checking
639 void bang_stack_with_offset(int offset) {
640 // stack grows down, caller passes positive offset
641 assert(offset > 0, "must bang with negative offset");
642 movl(Address(rsp, (-offset)), rax);
643 }
644
645 // Writes to stack successive pages until offset reached to check for
646 // stack overflow + shadow pages. Also, clobbers tmp
647 void bang_stack_size(Register size, Register tmp);
648
649 // Check for reserved stack access in method being exited (for JIT)
650 void reserved_stack_check();
651
652 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
653 Register tmp,
654 int offset);
655
656 // Support for serializing memory accesses between threads
657 void serialize_memory(Register thread, Register tmp);
658
659 // If thread_reg is != noreg the code assumes the register passed contains
660 // the thread (required on 64 bit).
661 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
662
663 void verify_tlab();
664
665 // Biased locking support
666 // lock_reg and obj_reg must be loaded up with the appropriate values.
667 // swap_reg must be rax, and is killed.
668 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
669 // be killed; if not supplied, push/pop will be used internally to
670 // allocate a temporary (inefficient, avoid if possible).
671 // Optional slow case is for implementations (interpreter and C1) which branch to
672 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
673 // Returns offset of first potentially-faulting instruction for null
674 // check info (currently consumed only by C1). If
675 // swap_reg_contains_mark is true then returns -1 as it is assumed
676 // the calling code has already passed any potential faults.
677 int biased_locking_enter(Register lock_reg, Register obj_reg,
678 Register swap_reg, Register tmp_reg,
679 bool swap_reg_contains_mark,
680 Label& done, Label* slow_case = NULL,
681 BiasedLockingCounters* counters = NULL);
682 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
683 #ifdef COMPILER2
684 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
685 // See full desription in macroAssembler_x86.cpp.
686 void fast_lock(Register obj, Register box, Register tmp,
687 Register scr, Register cx1, Register cx2,
688 BiasedLockingCounters* counters,
689 RTMLockingCounters* rtm_counters,
690 RTMLockingCounters* stack_rtm_counters,
691 Metadata* method_data,
692 bool use_rtm, bool profile_rtm);
693 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
694 #if INCLUDE_RTM_OPT
695 void rtm_counters_update(Register abort_status, Register rtm_counters);
696 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
697 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
698 RTMLockingCounters* rtm_counters,
699 Metadata* method_data);
700 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
701 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
702 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
703 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
704 void rtm_stack_locking(Register obj, Register tmp, Register scr,
705 Register retry_on_abort_count,
706 RTMLockingCounters* stack_rtm_counters,
707 Metadata* method_data, bool profile_rtm,
708 Label& DONE_LABEL, Label& IsInflated);
709 void rtm_inflated_locking(Register obj, Register box, Register tmp,
710 Register scr, Register retry_on_busy_count,
711 Register retry_on_abort_count,
712 RTMLockingCounters* rtm_counters,
713 Metadata* method_data, bool profile_rtm,
714 Label& DONE_LABEL);
715 #endif
716 #endif
717
718 Condition negate_condition(Condition cond);
719
720 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
721 // operands. In general the names are modified to avoid hiding the instruction in Assembler
722 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
723 // here in MacroAssembler. The major exception to this rule is call
724
725 // Arithmetics
726
727
728 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
729 void addptr(Address dst, Register src);
730
731 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
732 void addptr(Register dst, int32_t src);
733 void addptr(Register dst, Register src);
734 void addptr(Register dst, RegisterOrConstant src) {
735 if (src.is_constant()) addptr(dst, (int) src.as_constant());
736 else addptr(dst, src.as_register());
737 }
738
739 void andptr(Register dst, int32_t src);
740 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
741
742 void cmp8(AddressLiteral src1, int imm);
743
744 // renamed to drag out the casting of address to int32_t/intptr_t
745 void cmp32(Register src1, int32_t imm);
746
747 void cmp32(AddressLiteral src1, int32_t imm);
748 // compare reg - mem, or reg - &mem
749 void cmp32(Register src1, AddressLiteral src2);
750
751 void cmp32(Register src1, Address src2);
752
753 #ifndef _LP64
754 void cmpklass(Address dst, Metadata* obj);
755 void cmpklass(Register dst, Metadata* obj);
756 void cmpoop(Address dst, jobject obj);
757 #endif // _LP64
758
759 void cmpoop(Register src1, Register src2);
760 void cmpoop(Register src1, Address src2);
761 void cmpoop(Register dst, jobject obj);
762
763 // NOTE src2 must be the lval. This is NOT an mem-mem compare
764 void cmpptr(Address src1, AddressLiteral src2);
765
766 void cmpptr(Register src1, AddressLiteral src2);
767
768 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
769 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
770 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
771
772 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
773 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
774
775 // cmp64 to avoild hiding cmpq
776 void cmp64(Register src1, AddressLiteral src);
777
778 void cmpxchgptr(Register reg, Address adr);
779
780 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
781
782
783 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
784 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
785
786
787 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
788
789 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
790
791 void shlptr(Register dst, int32_t shift);
792 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
793
794 void shrptr(Register dst, int32_t shift);
795 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
796
797 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
798 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
799
800 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
801
802 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
803 void subptr(Register dst, int32_t src);
804 // Force generation of a 4 byte immediate value even if it fits into 8bit
805 void subptr_imm32(Register dst, int32_t src);
806 void subptr(Register dst, Register src);
807 void subptr(Register dst, RegisterOrConstant src) {
808 if (src.is_constant()) subptr(dst, (int) src.as_constant());
809 else subptr(dst, src.as_register());
810 }
811
812 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
813 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
814
815 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
816 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
817
818 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
819
820
821
822 // Helper functions for statistics gathering.
823 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
824 void cond_inc32(Condition cond, AddressLiteral counter_addr);
825 // Unconditional atomic increment.
826 void atomic_incl(Address counter_addr);
827 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
828 #ifdef _LP64
829 void atomic_incq(Address counter_addr);
830 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
831 #endif
832 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
833 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
834
835 void lea(Register dst, AddressLiteral adr);
836 void lea(Address dst, AddressLiteral adr);
837 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
838
839 void leal32(Register dst, Address src) { leal(dst, src); }
840
841 // Import other testl() methods from the parent class or else
842 // they will be hidden by the following overriding declaration.
843 using Assembler::testl;
844 void testl(Register dst, AddressLiteral src);
845
846 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
847 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
848 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
849 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
850
851 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
852 void testptr(Register src1, Register src2);
853
854 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
855 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
856
857 // Calls
858
859 void call(Label& L, relocInfo::relocType rtype);
860 void call(Register entry);
861
862 // NOTE: this call transfers to the effective address of entry NOT
863 // the address contained by entry. This is because this is more natural
864 // for jumps/calls.
865 void call(AddressLiteral entry);
866
867 // Emit the CompiledIC call idiom
868 void ic_call(address entry, jint method_index = 0);
869
870 // Jumps
871
872 // NOTE: these jumps tranfer to the effective address of dst NOT
873 // the address contained by dst. This is because this is more natural
874 // for jumps/calls.
875 void jump(AddressLiteral dst);
876 void jump_cc(Condition cc, AddressLiteral dst);
877
878 // 32bit can do a case table jump in one instruction but we no longer allow the base
879 // to be installed in the Address class. This jump will tranfers to the address
880 // contained in the location described by entry (not the address of entry)
881 void jump(ArrayAddress entry);
882
883 // Floating
884
885 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
886 void andpd(XMMRegister dst, AddressLiteral src);
887 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
888
889 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
890 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
891 void andps(XMMRegister dst, AddressLiteral src);
892
893 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
894 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
895 void comiss(XMMRegister dst, AddressLiteral src);
896
897 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
898 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
899 void comisd(XMMRegister dst, AddressLiteral src);
900
901 void fadd_s(Address src) { Assembler::fadd_s(src); }
902 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
903
904 void fldcw(Address src) { Assembler::fldcw(src); }
905 void fldcw(AddressLiteral src);
906
907 void fld_s(int index) { Assembler::fld_s(index); }
908 void fld_s(Address src) { Assembler::fld_s(src); }
909 void fld_s(AddressLiteral src);
910
911 void fld_d(Address src) { Assembler::fld_d(src); }
912 void fld_d(AddressLiteral src);
913
914 void fld_x(Address src) { Assembler::fld_x(src); }
915 void fld_x(AddressLiteral src);
916
917 void fmul_s(Address src) { Assembler::fmul_s(src); }
918 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
919
920 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
921 void ldmxcsr(AddressLiteral src);
922
923 #ifdef _LP64
924 private:
925 void sha256_AVX2_one_round_compute(
926 Register reg_old_h,
927 Register reg_a,
928 Register reg_b,
929 Register reg_c,
930 Register reg_d,
931 Register reg_e,
932 Register reg_f,
933 Register reg_g,
934 Register reg_h,
935 int iter);
936 void sha256_AVX2_four_rounds_compute_first(int start);
937 void sha256_AVX2_four_rounds_compute_last(int start);
938 void sha256_AVX2_one_round_and_sched(
939 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
940 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
941 XMMRegister xmm_2, /* ymm6 */
942 XMMRegister xmm_3, /* ymm7 */
943 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
944 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
945 Register reg_c, /* edi */
946 Register reg_d, /* esi */
947 Register reg_e, /* r8d */
948 Register reg_f, /* r9d */
949 Register reg_g, /* r10d */
950 Register reg_h, /* r11d */
951 int iter);
952
953 void addm(int disp, Register r1, Register r2);
954
955 public:
956 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
957 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
958 Register buf, Register state, Register ofs, Register limit, Register rsp,
959 bool multi_block, XMMRegister shuf_mask);
960 #endif
961
962 #ifdef _LP64
963 private:
964 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
965 Register e, Register f, Register g, Register h, int iteration);
966
967 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
968 Register a, Register b, Register c, Register d, Register e, Register f,
969 Register g, Register h, int iteration);
970
971 void addmq(int disp, Register r1, Register r2);
972 public:
973 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
974 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
975 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
976 XMMRegister shuf_mask);
977 #endif
978
979 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
980 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
981 Register buf, Register state, Register ofs, Register limit, Register rsp,
982 bool multi_block);
983
984 #ifdef _LP64
985 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
986 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
987 Register buf, Register state, Register ofs, Register limit, Register rsp,
988 bool multi_block, XMMRegister shuf_mask);
989 #else
990 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
991 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
992 Register buf, Register state, Register ofs, Register limit, Register rsp,
993 bool multi_block);
994 #endif
995
996 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
997 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
998 Register rax, Register rcx, Register rdx, Register tmp);
999
1000 #ifdef _LP64
1001 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1002 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1003 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1004
1005 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1006 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1007 Register rax, Register rcx, Register rdx, Register r11);
1008
1009 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1010 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1011 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1012
1013 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1014 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1015 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1016 Register tmp3, Register tmp4);
1017
1018 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1019 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1020 Register rax, Register rcx, Register rdx, Register tmp1,
1021 Register tmp2, Register tmp3, Register tmp4);
1022 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1023 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1024 Register rax, Register rcx, Register rdx, Register tmp1,
1025 Register tmp2, Register tmp3, Register tmp4);
1026 #else
1027 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1028 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1029 Register rax, Register rcx, Register rdx, Register tmp1);
1030
1031 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1032 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1033 Register rax, Register rcx, Register rdx, Register tmp);
1034
1035 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1036 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1037 Register rdx, Register tmp);
1038
1039 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1040 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1041 Register rax, Register rbx, Register rdx);
1042
1043 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1044 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1045 Register rax, Register rcx, Register rdx, Register tmp);
1046
1047 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1048 Register edx, Register ebx, Register esi, Register edi,
1049 Register ebp, Register esp);
1050
1051 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1052 Register esi, Register edi, Register ebp, Register esp);
1053
1054 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1055 Register edx, Register ebx, Register esi, Register edi,
1056 Register ebp, Register esp);
1057
1058 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1059 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1060 Register rax, Register rcx, Register rdx, Register tmp);
1061 #endif
1062
1063 void increase_precision();
1064 void restore_precision();
1065
1066 private:
1067
1068 // these are private because users should be doing movflt/movdbl
1069
1070 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1071 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1072 void movss(XMMRegister dst, AddressLiteral src);
1073
1074 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1075 void movlpd(XMMRegister dst, AddressLiteral src);
1076
1077 public:
1078
1079 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1080 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1081 void addsd(XMMRegister dst, AddressLiteral src);
1082
1083 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1084 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1085 void addss(XMMRegister dst, AddressLiteral src);
1086
1087 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1088 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1089 void addpd(XMMRegister dst, AddressLiteral src);
1090
1091 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1092 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1093 void divsd(XMMRegister dst, AddressLiteral src);
1094
1095 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1096 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1097 void divss(XMMRegister dst, AddressLiteral src);
1098
1099 // Move Unaligned Double Quadword
1100 void movdqu(Address dst, XMMRegister src);
1101 void movdqu(XMMRegister dst, Address src);
1102 void movdqu(XMMRegister dst, XMMRegister src);
1103 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1104 // AVX Unaligned forms
1105 void vmovdqu(Address dst, XMMRegister src);
1106 void vmovdqu(XMMRegister dst, Address src);
1107 void vmovdqu(XMMRegister dst, XMMRegister src);
1108 void vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1109 // AVX512 Unaligned
1110 void evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1111 void evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1112 void evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1113 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1114 void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1115
1116 void evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, src, merge, vector_len); }
1117 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1118 void evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, src, merge, vector_len); }
1119 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1120 void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1121
1122 void evmovdqul(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1123 void evmovdqul(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1124 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1125 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1126 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1127 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1128 void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1129
1130 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1131 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1132 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1133 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1134 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1135 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1136 void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1137
1138 // Move Aligned Double Quadword
1139 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1140 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1141 void movdqa(XMMRegister dst, AddressLiteral src);
1142
1143 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1144 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1145 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1146 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1147 void movsd(XMMRegister dst, AddressLiteral src);
1148
1149 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1150 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1151 void mulpd(XMMRegister dst, AddressLiteral src);
1152
1153 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1154 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1155 void mulsd(XMMRegister dst, AddressLiteral src);
1156
1157 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1158 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1159 void mulss(XMMRegister dst, AddressLiteral src);
1160
1161 // Carry-Less Multiplication Quadword
1162 void pclmulldq(XMMRegister dst, XMMRegister src) {
1163 // 0x00 - multiply lower 64 bits [0:63]
1164 Assembler::pclmulqdq(dst, src, 0x00);
1165 }
1166 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1167 // 0x11 - multiply upper 64 bits [64:127]
1168 Assembler::pclmulqdq(dst, src, 0x11);
1169 }
1170
1171 void pcmpeqb(XMMRegister dst, XMMRegister src);
1172 void pcmpeqw(XMMRegister dst, XMMRegister src);
1173
1174 void pcmpestri(XMMRegister dst, Address src, int imm8);
1175 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1176
1177 void pmovzxbw(XMMRegister dst, XMMRegister src);
1178 void pmovzxbw(XMMRegister dst, Address src);
1179
1180 void pmovmskb(Register dst, XMMRegister src);
1181
1182 void ptest(XMMRegister dst, XMMRegister src);
1183
1184 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1185 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1186 void sqrtsd(XMMRegister dst, AddressLiteral src);
1187
1188 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1189 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1190 void sqrtss(XMMRegister dst, AddressLiteral src);
1191
1192 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1193 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1194 void subsd(XMMRegister dst, AddressLiteral src);
1195
1196 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1197 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1198 void subss(XMMRegister dst, AddressLiteral src);
1199
1200 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1201 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1202 void ucomiss(XMMRegister dst, AddressLiteral src);
1203
1204 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1205 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1206 void ucomisd(XMMRegister dst, AddressLiteral src);
1207
1208 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1209 void xorpd(XMMRegister dst, XMMRegister src);
1210 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1211 void xorpd(XMMRegister dst, AddressLiteral src);
1212
1213 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1214 void xorps(XMMRegister dst, XMMRegister src);
1215 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1216 void xorps(XMMRegister dst, AddressLiteral src);
1217
1218 // Shuffle Bytes
1219 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1220 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1221 void pshufb(XMMRegister dst, AddressLiteral src);
1222 // AVX 3-operands instructions
1223
1224 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1225 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1226 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1227
1228 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1229 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1230 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1231
1232 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1233 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1234
1235 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1236 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1237
1238 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1239 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1240
1241 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1242 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1243 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1244
1245 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1246
1247 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1248 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1249 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1250
1251 // Vector compares
1252 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1253 int comparison, int vector_len) { Assembler::evpcmpd(kdst, mask, nds, src, comparison, vector_len); }
1254 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1255 int comparison, int vector_len, Register scratch_reg);
1256 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1257 int comparison, int vector_len) { Assembler::evpcmpq(kdst, mask, nds, src, comparison, vector_len); }
1258 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1259 int comparison, int vector_len, Register scratch_reg);
1260 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1261 int comparison, int vector_len) { Assembler::evpcmpb(kdst, mask, nds, src, comparison, vector_len); }
1262 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1263 int comparison, int vector_len, Register scratch_reg);
1264 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1265 int comparison, int vector_len) { Assembler::evpcmpw(kdst, mask, nds, src, comparison, vector_len); }
1266 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1267 int comparison, int vector_len, Register scratch_reg);
1268
1269 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1270 void vpmovmskb(Register dst, XMMRegister src);
1271
1272 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1273 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1274
1275 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1276 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1277
1278 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1279 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1280
1281 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1282 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1283
1284 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1285 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1286
1287 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1288 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1289
1290 void vptest(XMMRegister dst, XMMRegister src);
1291 void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1292
1293 void punpcklbw(XMMRegister dst, XMMRegister src);
1294 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1295
1296 void pshufd(XMMRegister dst, Address src, int mode);
1297 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1298
1299 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1300 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1301
1302 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1303 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1304 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1305
1306 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1307 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1308 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1309
1310 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1311
1312 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1313 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1314 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1315
1316 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1317 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1318 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1319
1320 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1321 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1322 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1323
1324 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1325 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1326 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1327
1328 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1329 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1330 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1331
1332 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1333 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1334 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1335
1336 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1337 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1338
1339 // AVX Vector instructions
1340
1341 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1342 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1343 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1344
1345 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1346 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1347 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1348
1349 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1350 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1351 Assembler::vpxor(dst, nds, src, vector_len);
1352 else
1353 Assembler::vxorpd(dst, nds, src, vector_len);
1354 }
1355 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1356 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1357 Assembler::vpxor(dst, nds, src, vector_len);
1358 else
1359 Assembler::vxorpd(dst, nds, src, vector_len);
1360 }
1361 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1362
1363 // Simple version for AVX2 256bit vectors
1364 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1365 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1366
1367 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vpermd(dst, nds, src); }
1368 void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register scratch_reg);
1369
1370 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1371 if (UseAVX > 2) {
1372 Assembler::vinserti32x4(dst, dst, src, imm8);
1373 } else if (UseAVX > 1) {
1374 // vinserti128 is available only in AVX2
1375 Assembler::vinserti128(dst, nds, src, imm8);
1376 } else {
1377 Assembler::vinsertf128(dst, nds, src, imm8);
1378 }
1379 }
1380
1381 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1382 if (UseAVX > 2) {
1383 Assembler::vinserti32x4(dst, dst, src, imm8);
1384 } else if (UseAVX > 1) {
1385 // vinserti128 is available only in AVX2
1386 Assembler::vinserti128(dst, nds, src, imm8);
1387 } else {
1388 Assembler::vinsertf128(dst, nds, src, imm8);
1389 }
1390 }
1391
1392 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1393 if (UseAVX > 2) {
1394 Assembler::vextracti32x4(dst, src, imm8);
1395 } else if (UseAVX > 1) {
1396 // vextracti128 is available only in AVX2
1397 Assembler::vextracti128(dst, src, imm8);
1398 } else {
1399 Assembler::vextractf128(dst, src, imm8);
1400 }
1401 }
1402
1403 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1404 if (UseAVX > 2) {
1405 Assembler::vextracti32x4(dst, src, imm8);
1406 } else if (UseAVX > 1) {
1407 // vextracti128 is available only in AVX2
1408 Assembler::vextracti128(dst, src, imm8);
1409 } else {
1410 Assembler::vextractf128(dst, src, imm8);
1411 }
1412 }
1413
1414 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1415 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1416 vinserti128(dst, dst, src, 1);
1417 }
1418 void vinserti128_high(XMMRegister dst, Address src) {
1419 vinserti128(dst, dst, src, 1);
1420 }
1421 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1422 vextracti128(dst, src, 1);
1423 }
1424 void vextracti128_high(Address dst, XMMRegister src) {
1425 vextracti128(dst, src, 1);
1426 }
1427
1428 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1429 if (UseAVX > 2) {
1430 Assembler::vinsertf32x4(dst, dst, src, 1);
1431 } else {
1432 Assembler::vinsertf128(dst, dst, src, 1);
1433 }
1434 }
1435
1436 void vinsertf128_high(XMMRegister dst, Address src) {
1437 if (UseAVX > 2) {
1438 Assembler::vinsertf32x4(dst, dst, src, 1);
1439 } else {
1440 Assembler::vinsertf128(dst, dst, src, 1);
1441 }
1442 }
1443
1444 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1445 if (UseAVX > 2) {
1446 Assembler::vextractf32x4(dst, src, 1);
1447 } else {
1448 Assembler::vextractf128(dst, src, 1);
1449 }
1450 }
1451
1452 void vextractf128_high(Address dst, XMMRegister src) {
1453 if (UseAVX > 2) {
1454 Assembler::vextractf32x4(dst, src, 1);
1455 } else {
1456 Assembler::vextractf128(dst, src, 1);
1457 }
1458 }
1459
1460 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1461 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1462 Assembler::vinserti64x4(dst, dst, src, 1);
1463 }
1464 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1465 Assembler::vinsertf64x4(dst, dst, src, 1);
1466 }
1467 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1468 Assembler::vextracti64x4(dst, src, 1);
1469 }
1470 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1471 Assembler::vextractf64x4(dst, src, 1);
1472 }
1473 void vextractf64x4_high(Address dst, XMMRegister src) {
1474 Assembler::vextractf64x4(dst, src, 1);
1475 }
1476 void vinsertf64x4_high(XMMRegister dst, Address src) {
1477 Assembler::vinsertf64x4(dst, dst, src, 1);
1478 }
1479
1480 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1481 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1482 vinserti128(dst, dst, src, 0);
1483 }
1484 void vinserti128_low(XMMRegister dst, Address src) {
1485 vinserti128(dst, dst, src, 0);
1486 }
1487 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1488 vextracti128(dst, src, 0);
1489 }
1490 void vextracti128_low(Address dst, XMMRegister src) {
1491 vextracti128(dst, src, 0);
1492 }
1493
1494 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1495 if (UseAVX > 2) {
1496 Assembler::vinsertf32x4(dst, dst, src, 0);
1497 } else {
1498 Assembler::vinsertf128(dst, dst, src, 0);
1499 }
1500 }
1501
1502 void vinsertf128_low(XMMRegister dst, Address src) {
1503 if (UseAVX > 2) {
1504 Assembler::vinsertf32x4(dst, dst, src, 0);
1505 } else {
1506 Assembler::vinsertf128(dst, dst, src, 0);
1507 }
1508 }
1509
1510 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1511 if (UseAVX > 2) {
1512 Assembler::vextractf32x4(dst, src, 0);
1513 } else {
1514 Assembler::vextractf128(dst, src, 0);
1515 }
1516 }
1517
1518 void vextractf128_low(Address dst, XMMRegister src) {
1519 if (UseAVX > 2) {
1520 Assembler::vextractf32x4(dst, src, 0);
1521 } else {
1522 Assembler::vextractf128(dst, src, 0);
1523 }
1524 }
1525
1526 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1527 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1528 Assembler::vinserti64x4(dst, dst, src, 0);
1529 }
1530 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1531 Assembler::vinsertf64x4(dst, dst, src, 0);
1532 }
1533 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1534 Assembler::vextracti64x4(dst, src, 0);
1535 }
1536 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1537 Assembler::vextractf64x4(dst, src, 0);
1538 }
1539 void vextractf64x4_low(Address dst, XMMRegister src) {
1540 Assembler::vextractf64x4(dst, src, 0);
1541 }
1542 void vinsertf64x4_low(XMMRegister dst, Address src) {
1543 Assembler::vinsertf64x4(dst, dst, src, 0);
1544 }
1545
1546 // Carry-Less Multiplication Quadword
1547 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1548 // 0x00 - multiply lower 64 bits [0:63]
1549 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1550 }
1551 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1552 // 0x11 - multiply upper 64 bits [64:127]
1553 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1554 }
1555
1556 // Data
1557
1558 void cmov32( Condition cc, Register dst, Address src);
1559 void cmov32( Condition cc, Register dst, Register src);
1560
1561 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1562
1563 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1564 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1565
1566 void movoop(Register dst, jobject obj);
1567 void movoop(Address dst, jobject obj);
1568
1569 void mov_metadata(Register dst, Metadata* obj);
1570 void mov_metadata(Address dst, Metadata* obj);
1571
1572 void movptr(ArrayAddress dst, Register src);
1573 // can this do an lea?
1574 void movptr(Register dst, ArrayAddress src);
1575
1576 void movptr(Register dst, Address src);
1577
1578 #ifdef _LP64
1579 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1580 #else
1581 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1582 #endif
1583
1584 void movptr(Register dst, intptr_t src);
1585 void movptr(Register dst, Register src);
1586 void movptr(Address dst, intptr_t src);
1587
1588 void movptr(Address dst, Register src);
1589
1590 void movptr(Register dst, RegisterOrConstant src) {
1591 if (src.is_constant()) movptr(dst, src.as_constant());
1592 else movptr(dst, src.as_register());
1593 }
1594
1595 #ifdef _LP64
1596 // Generally the next two are only used for moving NULL
1597 // Although there are situations in initializing the mark word where
1598 // they could be used. They are dangerous.
1599
1600 // They only exist on LP64 so that int32_t and intptr_t are not the same
1601 // and we have ambiguous declarations.
1602
1603 void movptr(Address dst, int32_t imm32);
1604 void movptr(Register dst, int32_t imm32);
1605 #endif // _LP64
1606
1607 // to avoid hiding movl
1608 void mov32(AddressLiteral dst, Register src);
1609 void mov32(Register dst, AddressLiteral src);
1610
1611 // to avoid hiding movb
1612 void movbyte(ArrayAddress dst, int src);
1613
1614 // Import other mov() methods from the parent class or else
1615 // they will be hidden by the following overriding declaration.
1616 using Assembler::movdl;
1617 using Assembler::movq;
1618 void movdl(XMMRegister dst, AddressLiteral src);
1619 void movq(XMMRegister dst, AddressLiteral src);
1620
1621 // Can push value or effective address
1622 void pushptr(AddressLiteral src);
1623
1624 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1625 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1626
1627 void pushoop(jobject obj);
1628 void pushklass(Metadata* obj);
1629
1630 // sign extend as need a l to ptr sized element
1631 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1632 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1633
1634 // C2 compiled method's prolog code.
1635 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1636
1637 // clear memory of size 'cnt' qwords, starting at 'base';
1638 // if 'is_large' is set, do not try to produce short loop
1639 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1640
1641 #ifdef COMPILER2
1642 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1643 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1644
1645 // IndexOf strings.
1646 // Small strings are loaded through stack if they cross page boundary.
1647 void string_indexof(Register str1, Register str2,
1648 Register cnt1, Register cnt2,
1649 int int_cnt2, Register result,
1650 XMMRegister vec, Register tmp,
1651 int ae);
1652
1653 // IndexOf for constant substrings with size >= 8 elements
1654 // which don't need to be loaded through stack.
1655 void string_indexofC8(Register str1, Register str2,
1656 Register cnt1, Register cnt2,
1657 int int_cnt2, Register result,
1658 XMMRegister vec, Register tmp,
1659 int ae);
1660
1661 // Smallest code: we don't need to load through stack,
1662 // check string tail.
1663
1664 // helper function for string_compare
1665 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1666 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1667 Address::ScaleFactor scale2, Register index, int ae);
1668 // Compare strings.
1669 void string_compare(Register str1, Register str2,
1670 Register cnt1, Register cnt2, Register result,
1671 XMMRegister vec1, int ae);
1672
1673 // Search for Non-ASCII character (Negative byte value) in a byte array,
1674 // return true if it has any and false otherwise.
1675 void has_negatives(Register ary1, Register len,
1676 Register result, Register tmp1,
1677 XMMRegister vec1, XMMRegister vec2);
1678
1679 // Compare char[] or byte[] arrays.
1680 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1681 Register limit, Register result, Register chr,
1682 XMMRegister vec1, XMMRegister vec2, bool is_char);
1683
1684 #endif
1685
1686 // Fill primitive arrays
1687 void generate_fill(BasicType t, bool aligned,
1688 Register to, Register value, Register count,
1689 Register rtmp, XMMRegister xtmp);
1690
1691 void encode_iso_array(Register src, Register dst, Register len,
1692 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1693 XMMRegister tmp4, Register tmp5, Register result);
1694
1695 #ifdef _LP64
1696 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1697 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1698 Register y, Register y_idx, Register z,
1699 Register carry, Register product,
1700 Register idx, Register kdx);
1701 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1702 Register yz_idx, Register idx,
1703 Register carry, Register product, int offset);
1704 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1705 Register carry, Register carry2,
1706 Register idx, Register jdx,
1707 Register yz_idx1, Register yz_idx2,
1708 Register tmp, Register tmp3, Register tmp4);
1709 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1710 Register yz_idx, Register idx, Register jdx,
1711 Register carry, Register product,
1712 Register carry2);
1713 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1714 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1715 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1716 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1717 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1718 Register tmp2);
1719 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1720 Register rdxReg, Register raxReg);
1721 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1722 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1723 Register tmp3, Register tmp4);
1724 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1725 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1726
1727 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1728 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1729 Register raxReg);
1730 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1731 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1732 Register raxReg);
1733 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1734 Register result, Register tmp1, Register tmp2,
1735 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1736 #endif
1737
1738 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1739 void update_byte_crc32(Register crc, Register val, Register table);
1740 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1741 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1742 // Note on a naming convention:
1743 // Prefix w = register only used on a Westmere+ architecture
1744 // Prefix n = register only used on a Nehalem architecture
1745 #ifdef _LP64
1746 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1747 Register tmp1, Register tmp2, Register tmp3);
1748 #else
1749 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1750 Register tmp1, Register tmp2, Register tmp3,
1751 XMMRegister xtmp1, XMMRegister xtmp2);
1752 #endif
1753 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1754 Register in_out,
1755 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1756 XMMRegister w_xtmp2,
1757 Register tmp1,
1758 Register n_tmp2, Register n_tmp3);
1759 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1760 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1761 Register tmp1, Register tmp2,
1762 Register n_tmp3);
1763 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1764 Register in_out1, Register in_out2, Register in_out3,
1765 Register tmp1, Register tmp2, Register tmp3,
1766 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1767 Register tmp4, Register tmp5,
1768 Register n_tmp6);
1769 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1770 Register tmp1, Register tmp2, Register tmp3,
1771 Register tmp4, Register tmp5, Register tmp6,
1772 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1773 bool is_pclmulqdq_supported);
1774 // Fold 128-bit data chunk
1775 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1776 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1777 // Fold 8-bit data
1778 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1779 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1780
1781 // Compress char[] array to byte[].
1782 void char_array_compress(Register src, Register dst, Register len,
1783 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1784 XMMRegister tmp4, Register tmp5, Register result);
1785
1786 // Inflate byte[] array to char[].
1787 void byte_array_inflate(Register src, Register dst, Register len,
1788 XMMRegister tmp1, Register tmp2);
1789
1790 };
1791
1792 /**
1793 * class SkipIfEqual:
1794 *
1795 * Instantiating this class will result in assembly code being output that will
1796 * jump around any code emitted between the creation of the instance and it's
1797 * automatic destruction at the end of a scope block, depending on the value of
1798 * the flag passed to the constructor, which will be checked at run-time.
1799 */
1800 class SkipIfEqual {
1801 private:
1802 MacroAssembler* _masm;
1803 Label _label;
1804
1805 public:
1806 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1807 ~SkipIfEqual();
1808 };
1809
1810 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP