1267 } else {
1268 assert(to_reg->is_double_cpu(), "Must be a long register.");
1269 #ifdef _LP64
1270 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1271 #else
1272 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1273 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1274 #endif
1275 }
1276
1277 }
1278 break;
1279
1280 default:
1281 ShouldNotReachHere();
1282 }
1283 }
1284
1285 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1286 Register reg = addr->base()->as_register();
1287 return Address(reg, addr->disp());
1288 }
1289
1290
1291 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1292 switch (type) {
1293 case T_INT:
1294 case T_FLOAT: {
1295 Register tmp = O7;
1296 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1297 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1298 __ lduw(from.base(), from.disp(), tmp);
1299 __ stw(tmp, to.base(), to.disp());
1300 break;
1301 }
1302 case T_OBJECT: {
1303 Register tmp = O7;
1304 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1305 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1306 __ ld_ptr(from.base(), from.disp(), tmp);
1307 __ st_ptr(tmp, to.base(), to.disp());
3386 arguments[a] = callop->arguments()[a];
3387 }
3388 if (op->code() == lir_virtual_call) {
3389 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3390 callop->vtable_offset(), arguments, callop->info());
3391 } else {
3392 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3393 callop->addr(), arguments, callop->info());
3394 }
3395 inst->at_put(i - 1, call);
3396 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
3397 T_LONG, lir_patch_none, NULL));
3398 }
3399 #endif
3400 break;
3401 }
3402 }
3403 }
3404 }
3405
3406
3407
3408
3409 #undef __
|
1267 } else {
1268 assert(to_reg->is_double_cpu(), "Must be a long register.");
1269 #ifdef _LP64
1270 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1271 #else
1272 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1273 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1274 #endif
1275 }
1276
1277 }
1278 break;
1279
1280 default:
1281 ShouldNotReachHere();
1282 }
1283 }
1284
1285 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1286 Register reg = addr->base()->as_register();
1287 LIR_Opr index = addr->index();
1288 if (index->is_illegal()) {
1289 return Address(reg, addr->disp());
1290 } else {
1291 assert (addr->disp() == 0, "unsupported address mode");
1292 return Address(reg, index->as_pointer_register());
1293 }
1294 }
1295
1296
1297 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1298 switch (type) {
1299 case T_INT:
1300 case T_FLOAT: {
1301 Register tmp = O7;
1302 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1303 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1304 __ lduw(from.base(), from.disp(), tmp);
1305 __ stw(tmp, to.base(), to.disp());
1306 break;
1307 }
1308 case T_OBJECT: {
1309 Register tmp = O7;
1310 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1311 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1312 __ ld_ptr(from.base(), from.disp(), tmp);
1313 __ st_ptr(tmp, to.base(), to.disp());
3392 arguments[a] = callop->arguments()[a];
3393 }
3394 if (op->code() == lir_virtual_call) {
3395 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3396 callop->vtable_offset(), arguments, callop->info());
3397 } else {
3398 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr,
3399 callop->addr(), arguments, callop->info());
3400 }
3401 inst->at_put(i - 1, call);
3402 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(),
3403 T_LONG, lir_patch_none, NULL));
3404 }
3405 #endif
3406 break;
3407 }
3408 }
3409 }
3410 }
3411
3412 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3413 LIR_Address* addr = src->as_address_ptr();
3414
3415 assert(data == dest, "swap uses only 2 operands");
3416 assert (code == lir_xchg, "no xadd on sparc");
3417
3418 if (data->type() == T_INT) {
3419 __ swap(as_Address(addr), data->as_register());
3420 } else if (data->is_oop()) {
3421 Register obj = data->as_register();
3422 Register narrow = tmp->as_register();
3423 #ifdef _LP64
3424 assert(UseCompressedOops, "swap is 32bit only");
3425 __ encode_heap_oop(obj, narrow);
3426 __ swap(as_Address(addr), narrow);
3427 __ decode_heap_oop(narrow, obj);
3428 #else
3429 __ swap(as_Address(addr), obj);
3430 #endif
3431 } else {
3432 ShouldNotReachHere();
3433 }
3434 }
3435
3436 #undef __
|