346 _cpuFeatures = 0;
347 _logical_processors_per_package = 1;
348
349 if (!Use486InstrsOnly) {
350 // Get raw processor info
351 getPsrInfo_stub(&_cpuid_info);
352 assert_is_initialized();
353 _cpu = extended_cpu_family();
354 _model = extended_cpu_model();
355 _stepping = cpu_stepping();
356
357 if (cpu_family() > 4) { // it supports CPUID
358 _cpuFeatures = feature_flags();
359 // Logical processors are only available on P4s and above,
360 // and only if hyperthreading is available.
361 _logical_processors_per_package = logical_processor_count();
362 }
363 }
364
365 _supports_cx8 = supports_cmpxchg8();
366
367 #ifdef _LP64
368 // OS should support SSE for x64 and hardware should support at least SSE2.
369 if (!VM_Version::supports_sse2()) {
370 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
371 }
372 // in 64 bit the use of SSE2 is the minimum
373 if (UseSSE < 2) UseSSE = 2;
374 #endif
375
376 #ifdef AMD64
377 // flush_icache_stub have to be generated first.
378 // That is why Icache line size is hard coded in ICache class,
379 // see icache_x86.hpp. It is also the reason why we can't use
380 // clflush instruction in 32-bit VM since it could be running
381 // on CPU which does not support it.
382 //
383 // The only thing we can do is to verify that flushed
384 // ICache::line_size has correct value.
385 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
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346 _cpuFeatures = 0;
347 _logical_processors_per_package = 1;
348
349 if (!Use486InstrsOnly) {
350 // Get raw processor info
351 getPsrInfo_stub(&_cpuid_info);
352 assert_is_initialized();
353 _cpu = extended_cpu_family();
354 _model = extended_cpu_model();
355 _stepping = cpu_stepping();
356
357 if (cpu_family() > 4) { // it supports CPUID
358 _cpuFeatures = feature_flags();
359 // Logical processors are only available on P4s and above,
360 // and only if hyperthreading is available.
361 _logical_processors_per_package = logical_processor_count();
362 }
363 }
364
365 _supports_cx8 = supports_cmpxchg8();
366 // xchg and xadd instructions
367 _supports_atomic_getset4 = true;
368 _supports_atomic_getadd4 = true;
369 LP64_ONLY(_supports_atomic_getset8 = true);
370 LP64_ONLY(_supports_atomic_getadd8 = true);
371
372 #ifdef _LP64
373 // OS should support SSE for x64 and hardware should support at least SSE2.
374 if (!VM_Version::supports_sse2()) {
375 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
376 }
377 // in 64 bit the use of SSE2 is the minimum
378 if (UseSSE < 2) UseSSE = 2;
379 #endif
380
381 #ifdef AMD64
382 // flush_icache_stub have to be generated first.
383 // That is why Icache line size is hard coded in ICache class,
384 // see icache_x86.hpp. It is also the reason why we can't use
385 // clflush instruction in 32-bit VM since it could be running
386 // on CPU which does not support it.
387 //
388 // The only thing we can do is to verify that flushed
389 // ICache::line_size has correct value.
390 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
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