1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_FPU_size() {
232 if (Compile::current()->in_24_bit_fp_mode())
233 return 6; // fldcw
234 return 0;
235 }
236
237 static int preserve_SP_size() {
238 return 2; // op, rm(reg/reg)
239 }
240
241 // !!!!! Special hack to get all type of calls to specify the byte offset
242 // from the start of the call to the point where the return address
243 // will point.
244 int MachCallStaticJavaNode::ret_addr_offset() {
245 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
246 if (_method_handle_invoke)
247 offset += preserve_SP_size();
248 return offset;
249 }
250
251 int MachCallDynamicJavaNode::ret_addr_offset() {
252 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
253 }
254
255 static int sizeof_FFree_Float_Stack_All = -1;
256
257 int MachCallRuntimeNode::ret_addr_offset() {
258 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
259 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
260 }
261
262 // Indicate if the safepoint node needs the polling page as an input.
263 // Since x86 does have absolute addressing, it doesn't.
264 bool SafePointNode::needs_polling_address_input() {
265 return false;
266 }
267
268 //
269 // Compute padding required for nodes which need alignment
270 //
271
272 // The address of the call instruction needs to be 4-byte aligned to
273 // ensure that it does not span a cache line so that it can be patched.
274 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
275 current_offset += pre_call_FPU_size(); // skip fldcw, if any
276 current_offset += 1; // skip call opcode byte
277 return round_to(current_offset, alignment_required()) - current_offset;
278 }
279
280 // The address of the call instruction needs to be 4-byte aligned to
281 // ensure that it does not span a cache line so that it can be patched.
282 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
283 current_offset += pre_call_FPU_size(); // skip fldcw, if any
284 current_offset += preserve_SP_size(); // skip mov rbp, rsp
285 current_offset += 1; // skip call opcode byte
286 return round_to(current_offset, alignment_required()) - current_offset;
287 }
288
289 // The address of the call instruction needs to be 4-byte aligned to
290 // ensure that it does not span a cache line so that it can be patched.
291 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
292 current_offset += pre_call_FPU_size(); // skip fldcw, if any
293 current_offset += 5; // skip MOV instruction
294 current_offset += 1; // skip call opcode byte
295 return round_to(current_offset, alignment_required()) - current_offset;
296 }
297
298 // EMIT_RM()
299 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
300 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
301 cbuf.insts()->emit_int8(c);
302 }
303
304 // EMIT_CC()
305 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
306 unsigned char c = (unsigned char)( f1 | f2 );
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_OPCODE()
311 void emit_opcode(CodeBuffer &cbuf, int code) {
312 cbuf.insts()->emit_int8((unsigned char) code);
313 }
314
315 // EMIT_OPCODE() w/ relocation information
316 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
317 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
318 emit_opcode(cbuf, code);
319 }
320
321 // EMIT_D8()
322 void emit_d8(CodeBuffer &cbuf, int d8) {
323 cbuf.insts()->emit_int8((unsigned char) d8);
324 }
325
326 // EMIT_D16()
327 void emit_d16(CodeBuffer &cbuf, int d16) {
328 cbuf.insts()->emit_int16(d16);
329 }
330
331 // EMIT_D32()
332 void emit_d32(CodeBuffer &cbuf, int d32) {
333 cbuf.insts()->emit_int32(d32);
334 }
335
336 // emit 32 bit value and construct relocation entry from relocInfo::relocType
337 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
338 int format) {
339 cbuf.relocate(cbuf.insts_mark(), reloc, format);
340 cbuf.insts()->emit_int32(d32);
341 }
342
343 // emit 32 bit value and construct relocation entry from RelocationHolder
344 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
345 int format) {
346 #ifdef ASSERT
347 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
348 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
349 }
350 #endif
351 cbuf.relocate(cbuf.insts_mark(), rspec, format);
352 cbuf.insts()->emit_int32(d32);
353 }
354
355 // Access stack slot for load or store
356 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
357 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
358 if( -128 <= disp && disp <= 127 ) {
359 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
360 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
361 emit_d8 (cbuf, disp); // Displacement // R/M byte
362 } else {
363 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
365 emit_d32(cbuf, disp); // Displacement // R/M byte
366 }
367 }
368
369 // rRegI ereg, memory mem) %{ // emit_reg_mem
370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
371 // There is no index & no scale, use form without SIB byte
372 if ((index == 0x4) &&
373 (scale == 0) && (base != ESP_enc)) {
374 // If no displacement, mode is 0x0; unless base is [EBP]
375 if ( (displace == 0) && (base != EBP_enc) ) {
376 emit_rm(cbuf, 0x0, reg_encoding, base);
377 }
378 else { // If 8-bit displacement, mode 0x1
379 if ((displace >= -128) && (displace <= 127)
380 && !(displace_is_oop) ) {
381 emit_rm(cbuf, 0x1, reg_encoding, base);
382 emit_d8(cbuf, displace);
383 }
384 else { // If 32-bit displacement
385 if (base == -1) { // Special flag for absolute address
386 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
387 // (manual lies; no SIB needed here)
388 if ( displace_is_oop ) {
389 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
390 } else {
391 emit_d32 (cbuf, displace);
392 }
393 }
394 else { // Normal base + offset
395 emit_rm(cbuf, 0x2, reg_encoding, base);
396 if ( displace_is_oop ) {
397 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
398 } else {
399 emit_d32 (cbuf, displace);
400 }
401 }
402 }
403 }
404 }
405 else { // Else, encode with the SIB byte
406 // If no displacement, mode is 0x0; unless base is [EBP]
407 if (displace == 0 && (base != EBP_enc)) { // If no displacement
408 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
409 emit_rm(cbuf, scale, index, base);
410 }
411 else { // If 8-bit displacement, mode 0x1
412 if ((displace >= -128) && (displace <= 127)
413 && !(displace_is_oop) ) {
414 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 emit_d8(cbuf, displace);
417 }
418 else { // If 32-bit displacement
419 if (base == 0x04 ) {
420 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, 0x04);
422 } else {
423 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
424 emit_rm(cbuf, scale, index, base);
425 }
426 if ( displace_is_oop ) {
427 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
428 } else {
429 emit_d32 (cbuf, displace);
430 }
431 }
432 }
433 }
434 }
435
436
437 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
438 if( dst_encoding == src_encoding ) {
439 // reg-reg copy, use an empty encoding
440 } else {
441 emit_opcode( cbuf, 0x8B );
442 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
443 }
444 }
445
446 void emit_cmpfp_fixup(MacroAssembler& _masm) {
447 Label exit;
448 __ jccb(Assembler::noParity, exit);
449 __ pushf();
450 //
451 // comiss/ucomiss instructions set ZF,PF,CF flags and
452 // zero OF,AF,SF for NaN values.
453 // Fixup flags by zeroing ZF,PF so that compare of NaN
454 // values returns 'less than' result (CF is set).
455 // Leave the rest of flags unchanged.
456 //
457 // 7 6 5 4 3 2 1 0
458 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
459 // 0 0 1 0 1 0 1 1 (0x2B)
460 //
461 __ andl(Address(rsp, 0), 0xffffff2b);
462 __ popf();
463 __ bind(exit);
464 }
465
466 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
467 Label done;
468 __ movl(dst, -1);
469 __ jcc(Assembler::parity, done);
470 __ jcc(Assembler::below, done);
471 __ setb(Assembler::notEqual, dst);
472 __ movzbl(dst, dst);
473 __ bind(done);
474 }
475
476
477 //=============================================================================
478 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
479
480 int Compile::ConstantTable::calculate_table_base_offset() const {
481 return 0; // absolute addressing, no offset
482 }
483
484 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
485 // Empty encoding
486 }
487
488 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
489 return 0;
490 }
491
492 #ifndef PRODUCT
493 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
494 st->print("# MachConstantBaseNode (empty encoding)");
495 }
496 #endif
497
498
499 //=============================================================================
500 #ifndef PRODUCT
501 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
502 Compile* C = ra_->C;
503
504 int framesize = C->frame_slots() << LogBytesPerInt;
505 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
506 // Remove wordSize for return addr which is already pushed.
507 framesize -= wordSize;
508
509 if (C->need_stack_bang(framesize)) {
510 framesize -= wordSize;
511 st->print("# stack bang");
512 st->print("\n\t");
513 st->print("PUSH EBP\t# Save EBP");
514 if (framesize) {
515 st->print("\n\t");
516 st->print("SUB ESP, #%d\t# Create frame",framesize);
517 }
518 } else {
519 st->print("SUB ESP, #%d\t# Create frame",framesize);
520 st->print("\n\t");
521 framesize -= wordSize;
522 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
523 }
524
525 if (VerifyStackAtCalls) {
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
529 }
530
531 if( C->in_24_bit_fp_mode() ) {
532 st->print("\n\t");
533 st->print("FLDCW \t# load 24 bit fpu control word");
534 }
535 if (UseSSE >= 2 && VerifyFPU) {
536 st->print("\n\t");
537 st->print("# verify FPU stack (must be clean on entry)");
538 }
539
540 #ifdef ASSERT
541 if (VerifyStackAtCalls) {
542 st->print("\n\t");
543 st->print("# stack alignment check");
544 }
545 #endif
546 st->cr();
547 }
548 #endif
549
550
551 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
552 Compile* C = ra_->C;
553 MacroAssembler _masm(&cbuf);
554
555 int framesize = C->frame_slots() << LogBytesPerInt;
556
557 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
558
559 C->set_frame_complete(cbuf.insts_size());
560
561 if (C->has_mach_constant_base_node()) {
562 // NOTE: We set the table base offset here because users might be
563 // emitted before MachConstantBaseNode.
564 Compile::ConstantTable& constant_table = C->constant_table();
565 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
566 }
567 }
568
569 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
570 return MachNode::size(ra_); // too many variables; just compute it the hard way
571 }
572
573 int MachPrologNode::reloc() const {
574 return 0; // a large enough number
575 }
576
577 //=============================================================================
578 #ifndef PRODUCT
579 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
580 Compile *C = ra_->C;
581 int framesize = C->frame_slots() << LogBytesPerInt;
582 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
583 // Remove two words for return addr and rbp,
584 framesize -= 2*wordSize;
585
586 if( C->in_24_bit_fp_mode() ) {
587 st->print("FLDCW standard control word");
588 st->cr(); st->print("\t");
589 }
590 if( framesize ) {
591 st->print("ADD ESP,%d\t# Destroy frame",framesize);
592 st->cr(); st->print("\t");
593 }
594 st->print_cr("POPL EBP"); st->print("\t");
595 if( do_polling() && C->is_method_compilation() ) {
596 st->print("TEST PollPage,EAX\t! Poll Safepoint");
597 st->cr(); st->print("\t");
598 }
599 }
600 #endif
601
602 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
603 Compile *C = ra_->C;
604
605 // If method set FPU control word, restore to standard control word
606 if( C->in_24_bit_fp_mode() ) {
607 MacroAssembler masm(&cbuf);
608 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
609 }
610
611 int framesize = C->frame_slots() << LogBytesPerInt;
612 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
613 // Remove two words for return addr and rbp,
614 framesize -= 2*wordSize;
615
616 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
617
618 if( framesize >= 128 ) {
619 emit_opcode(cbuf, 0x81); // add SP, #framesize
620 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
621 emit_d32(cbuf, framesize);
622 }
623 else if( framesize ) {
624 emit_opcode(cbuf, 0x83); // add SP, #framesize
625 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
626 emit_d8(cbuf, framesize);
627 }
628
629 emit_opcode(cbuf, 0x58 | EBP_enc);
630
631 if( do_polling() && C->is_method_compilation() ) {
632 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
633 emit_opcode(cbuf,0x85);
634 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
635 emit_d32(cbuf, (intptr_t)os::get_polling_page());
636 }
637 }
638
639 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
640 Compile *C = ra_->C;
641 // If method set FPU control word, restore to standard control word
642 int size = C->in_24_bit_fp_mode() ? 6 : 0;
643 if( do_polling() && C->is_method_compilation() ) size += 6;
644
645 int framesize = C->frame_slots() << LogBytesPerInt;
646 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
647 // Remove two words for return addr and rbp,
648 framesize -= 2*wordSize;
649
650 size++; // popl rbp,
651
652 if( framesize >= 128 ) {
653 size += 6;
654 } else {
655 size += framesize ? 3 : 0;
656 }
657 return size;
658 }
659
660 int MachEpilogNode::reloc() const {
661 return 0; // a large enough number
662 }
663
664 const Pipeline * MachEpilogNode::pipeline() const {
665 return MachNode::pipeline_class();
666 }
667
668 int MachEpilogNode::safepoint_offset() const { return 0; }
669
670 //=============================================================================
671
672 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
673 static enum RC rc_class( OptoReg::Name reg ) {
674
675 if( !OptoReg::is_valid(reg) ) return rc_bad;
676 if (OptoReg::is_stack(reg)) return rc_stack;
677
678 VMReg r = OptoReg::as_VMReg(reg);
679 if (r->is_Register()) return rc_int;
680 if (r->is_FloatRegister()) {
681 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
682 return rc_float;
683 }
684 assert(r->is_XMMRegister(), "must be");
685 return rc_xmm;
686 }
687
688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
689 int opcode, const char *op_str, int size, outputStream* st ) {
690 if( cbuf ) {
691 emit_opcode (*cbuf, opcode );
692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
693 #ifndef PRODUCT
694 } else if( !do_size ) {
695 if( size != 0 ) st->print("\n\t");
696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
698 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
699 } else { // FLD, FST, PUSH, POP
700 st->print("%s [ESP + #%d]",op_str,offset);
701 }
702 #endif
703 }
704 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
705 return size+3+offset_size;
706 }
707
708 // Helper for XMM registers. Extra opcode bits, limited syntax.
709 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
710 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
711 if (cbuf) {
712 MacroAssembler _masm(cbuf);
713 if (reg_lo+1 == reg_hi) { // double move?
714 if (is_load) {
715 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
716 } else {
717 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
718 }
719 } else {
720 if (is_load) {
721 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
722 } else {
723 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
724 }
725 }
726 #ifndef PRODUCT
727 } else if (!do_size) {
728 if (size != 0) st->print("\n\t");
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) st->print("%s %s,[ESP + #%d]",
731 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
732 Matcher::regName[reg_lo], offset);
733 else st->print("MOVSD [ESP + #%d],%s",
734 offset, Matcher::regName[reg_lo]);
735 } else {
736 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
737 Matcher::regName[reg_lo], offset);
738 else st->print("MOVSS [ESP + #%d],%s",
739 offset, Matcher::regName[reg_lo]);
740 }
741 #endif
742 }
743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
745 return size+5+offset_size;
746 }
747
748
749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
750 int src_hi, int dst_hi, int size, outputStream* st ) {
751 if (cbuf) {
752 MacroAssembler _masm(cbuf);
753 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
754 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
755 as_XMMRegister(Matcher::_regEncode[src_lo]));
756 } else {
757 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
758 as_XMMRegister(Matcher::_regEncode[src_lo]));
759 }
760 #ifndef PRODUCT
761 } else if (!do_size) {
762 if (size != 0) st->print("\n\t");
763 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
764 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
765 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
766 } else {
767 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
768 }
769 } else {
770 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
771 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
772 } else {
773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
774 }
775 }
776 #endif
777 }
778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
779 // Only MOVAPS SSE prefix uses 1 byte.
780 int sz = 4;
781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
783 return size + sz;
784 }
785
786 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
787 int src_hi, int dst_hi, int size, outputStream* st ) {
788 // 32-bit
789 if (cbuf) {
790 MacroAssembler _masm(cbuf);
791 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
792 as_Register(Matcher::_regEncode[src_lo]));
793 #ifndef PRODUCT
794 } else if (!do_size) {
795 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
796 #endif
797 }
798 return 4;
799 }
800
801
802 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
808 as_XMMRegister(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
816
817 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
818 if( cbuf ) {
819 emit_opcode(*cbuf, 0x8B );
820 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
821 #ifndef PRODUCT
822 } else if( !do_size ) {
823 if( size != 0 ) st->print("\n\t");
824 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
825 #endif
826 }
827 return size+2;
828 }
829
830 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
831 int offset, int size, outputStream* st ) {
832 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
833 if( cbuf ) {
834 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
835 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
836 #ifndef PRODUCT
837 } else if( !do_size ) {
838 if( size != 0 ) st->print("\n\t");
839 st->print("FLD %s",Matcher::regName[src_lo]);
840 #endif
841 }
842 size += 2;
843 }
844
845 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
846 const char *op_str;
847 int op;
848 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
849 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
850 op = 0xDD;
851 } else { // 32-bit store
852 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
853 op = 0xD9;
854 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
855 }
856
857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
858 }
859
860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
862 int src_hi, int dst_hi, uint ireg, outputStream* st);
863
864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
865 int stack_offset, int reg, uint ireg, outputStream* st);
866
867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
868 int dst_offset, uint ireg, outputStream* st) {
869 int calc_size = 0;
870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
872 switch (ireg) {
873 case Op_VecS:
874 calc_size = 3+src_offset_size + 3+dst_offset_size;
875 break;
876 case Op_VecD:
877 calc_size = 3+src_offset_size + 3+dst_offset_size;
878 src_offset += 4;
879 dst_offset += 4;
880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
882 calc_size += 3+src_offset_size + 3+dst_offset_size;
883 break;
884 case Op_VecX:
885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
886 break;
887 case Op_VecY:
888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
889 break;
890 default:
891 ShouldNotReachHere();
892 }
893 if (cbuf) {
894 MacroAssembler _masm(cbuf);
895 int offset = __ offset();
896 switch (ireg) {
897 case Op_VecS:
898 __ pushl(Address(rsp, src_offset));
899 __ popl (Address(rsp, dst_offset));
900 break;
901 case Op_VecD:
902 __ pushl(Address(rsp, src_offset));
903 __ popl (Address(rsp, dst_offset));
904 __ pushl(Address(rsp, src_offset+4));
905 __ popl (Address(rsp, dst_offset+4));
906 break;
907 case Op_VecX:
908 __ movdqu(Address(rsp, -16), xmm0);
909 __ movdqu(xmm0, Address(rsp, src_offset));
910 __ movdqu(Address(rsp, dst_offset), xmm0);
911 __ movdqu(xmm0, Address(rsp, -16));
912 break;
913 case Op_VecY:
914 __ vmovdqu(Address(rsp, -32), xmm0);
915 __ vmovdqu(xmm0, Address(rsp, src_offset));
916 __ vmovdqu(Address(rsp, dst_offset), xmm0);
917 __ vmovdqu(xmm0, Address(rsp, -32));
918 break;
919 default:
920 ShouldNotReachHere();
921 }
922 int size = __ offset() - offset;
923 assert(size == calc_size, "incorrect size calculattion");
924 return size;
925 #ifndef PRODUCT
926 } else if (!do_size) {
927 switch (ireg) {
928 case Op_VecS:
929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
930 "popl [rsp + #%d]",
931 src_offset, dst_offset);
932 break;
933 case Op_VecD:
934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
935 "popq [rsp + #%d]\n\t"
936 "pushl [rsp + #%d]\n\t"
937 "popq [rsp + #%d]",
938 src_offset, dst_offset, src_offset+4, dst_offset+4);
939 break;
940 case Op_VecX:
941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
942 "movdqu xmm0, [rsp + #%d]\n\t"
943 "movdqu [rsp + #%d], xmm0\n\t"
944 "movdqu xmm0, [rsp - #16]",
945 src_offset, dst_offset);
946 break;
947 case Op_VecY:
948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
949 "vmovdqu xmm0, [rsp + #%d]\n\t"
950 "vmovdqu [rsp + #%d], xmm0\n\t"
951 "vmovdqu xmm0, [rsp - #32]",
952 src_offset, dst_offset);
953 break;
954 default:
955 ShouldNotReachHere();
956 }
957 #endif
958 }
959 return calc_size;
960 }
961
962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
963 // Get registers to move
964 OptoReg::Name src_second = ra_->get_reg_second(in(1));
965 OptoReg::Name src_first = ra_->get_reg_first(in(1));
966 OptoReg::Name dst_second = ra_->get_reg_second(this );
967 OptoReg::Name dst_first = ra_->get_reg_first(this );
968
969 enum RC src_second_rc = rc_class(src_second);
970 enum RC src_first_rc = rc_class(src_first);
971 enum RC dst_second_rc = rc_class(dst_second);
972 enum RC dst_first_rc = rc_class(dst_first);
973
974 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
975
976 // Generate spill code!
977 int size = 0;
978
979 if( src_first == dst_first && src_second == dst_second )
980 return size; // Self copy, no move
981
982 if (bottom_type()->isa_vect() != NULL) {
983 uint ireg = ideal_reg();
984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
988 // mem -> mem
989 int src_offset = ra_->reg2offset(src_first);
990 int dst_offset = ra_->reg2offset(dst_first);
991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 int stack_offset = ra_->reg2offset(dst_first);
996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
998 int stack_offset = ra_->reg2offset(src_first);
999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1000 } else {
1001 ShouldNotReachHere();
1002 }
1003 }
1004
1005 // --------------------------------------
1006 // Check for mem-mem move. push/pop to move.
1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1008 if( src_second == dst_first ) { // overlapping stack copy ranges
1009 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1010 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1011 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1012 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1013 }
1014 // move low bits
1015 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1016 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1017 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1018 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1019 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1020 }
1021 return size;
1022 }
1023
1024 // --------------------------------------
1025 // Check for integer reg-reg copy
1026 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1027 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1028
1029 // Check for integer store
1030 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1031 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1032
1033 // Check for integer load
1034 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1035 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1036
1037 // Check for integer reg-xmm reg copy
1038 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1039 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1040 "no 64 bit integer-float reg moves" );
1041 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1042 }
1043 // --------------------------------------
1044 // Check for float reg-reg copy
1045 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1046 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1047 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1048 if( cbuf ) {
1049
1050 // Note the mucking with the register encode to compensate for the 0/1
1051 // indexing issue mentioned in a comment in the reg_def sections
1052 // for FPR registers many lines above here.
1053
1054 if( src_first != FPR1L_num ) {
1055 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1056 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1057 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1058 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1059 } else {
1060 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1061 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1062 }
1063 #ifndef PRODUCT
1064 } else if( !do_size ) {
1065 if( size != 0 ) st->print("\n\t");
1066 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1067 else st->print( "FST %s", Matcher::regName[dst_first]);
1068 #endif
1069 }
1070 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1071 }
1072
1073 // Check for float store
1074 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1075 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1076 }
1077
1078 // Check for float load
1079 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1080 int offset = ra_->reg2offset(src_first);
1081 const char *op_str;
1082 int op;
1083 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1084 op_str = "FLD_D";
1085 op = 0xDD;
1086 } else { // 32-bit load
1087 op_str = "FLD_S";
1088 op = 0xD9;
1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1090 }
1091 if( cbuf ) {
1092 emit_opcode (*cbuf, op );
1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1096 #ifndef PRODUCT
1097 } else if( !do_size ) {
1098 if( size != 0 ) st->print("\n\t");
1099 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1100 #endif
1101 }
1102 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1103 return size + 3+offset_size+2;
1104 }
1105
1106 // Check for xmm reg-reg copy
1107 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1108 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1109 (src_first+1 == src_second && dst_first+1 == dst_second),
1110 "no non-adjacent float-moves" );
1111 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1112 }
1113
1114 // Check for xmm reg-integer reg copy
1115 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1116 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1117 "no 64 bit float-integer reg moves" );
1118 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1119 }
1120
1121 // Check for xmm store
1122 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1123 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1124 }
1125
1126 // Check for float xmm load
1127 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1128 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1129 }
1130
1131 // Copy from float reg to xmm reg
1132 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1133 // copy to the top of stack from floating point reg
1134 // and use LEA to preserve flags
1135 if( cbuf ) {
1136 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1137 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1138 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1139 emit_d8(*cbuf,0xF8);
1140 #ifndef PRODUCT
1141 } else if( !do_size ) {
1142 if( size != 0 ) st->print("\n\t");
1143 st->print("LEA ESP,[ESP-8]");
1144 #endif
1145 }
1146 size += 4;
1147
1148 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1149
1150 // Copy from the temp memory to the xmm reg.
1151 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1152
1153 if( cbuf ) {
1154 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1155 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1156 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1157 emit_d8(*cbuf,0x08);
1158 #ifndef PRODUCT
1159 } else if( !do_size ) {
1160 if( size != 0 ) st->print("\n\t");
1161 st->print("LEA ESP,[ESP+8]");
1162 #endif
1163 }
1164 size += 4;
1165 return size;
1166 }
1167
1168 assert( size > 0, "missed a case" );
1169
1170 // --------------------------------------------------------------------
1171 // Check for second bits still needing moving.
1172 if( src_second == dst_second )
1173 return size; // Self copy; no move
1174 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1175
1176 // Check for second word int-int move
1177 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1178 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1179
1180 // Check for second word integer store
1181 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1182 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1183
1184 // Check for second word integer load
1185 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1186 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1187
1188
1189 Unimplemented();
1190 }
1191
1192 #ifndef PRODUCT
1193 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1194 implementation( NULL, ra_, false, st );
1195 }
1196 #endif
1197
1198 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1199 implementation( &cbuf, ra_, false, NULL );
1200 }
1201
1202 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1203 return implementation( NULL, ra_, true, NULL );
1204 }
1205
1206
1207 //=============================================================================
1208 #ifndef PRODUCT
1209 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1210 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1211 int reg = ra_->get_reg_first(this);
1212 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1213 }
1214 #endif
1215
1216 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1217 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1218 int reg = ra_->get_encode(this);
1219 if( offset >= 128 ) {
1220 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1221 emit_rm(cbuf, 0x2, reg, 0x04);
1222 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1223 emit_d32(cbuf, offset);
1224 }
1225 else {
1226 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1227 emit_rm(cbuf, 0x1, reg, 0x04);
1228 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1229 emit_d8(cbuf, offset);
1230 }
1231 }
1232
1233 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1235 if( offset >= 128 ) {
1236 return 7;
1237 }
1238 else {
1239 return 4;
1240 }
1241 }
1242
1243 //=============================================================================
1244
1245 // emit call stub, compiled java to interpreter
1246 void emit_java_to_interp(CodeBuffer &cbuf ) {
1247 // Stub is fixed up when the corresponding call is converted from calling
1248 // compiled code to calling interpreted code.
1249 // mov rbx,0
1250 // jmp -1
1251
1252 address mark = cbuf.insts_mark(); // get mark within main instrs section
1253
1254 // Note that the code buffer's insts_mark is always relative to insts.
1255 // That's why we must use the macroassembler to generate a stub.
1256 MacroAssembler _masm(&cbuf);
1257
1258 address base =
1259 __ start_a_stub(Compile::MAX_stubs_size);
1260 if (base == NULL) return; // CodeBuffer::expand failed
1261 // static stub relocation stores the instruction address of the call
1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1263 // static stub relocation also tags the methodOop in the code-stream.
1264 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1265 // This is recognized as unresolved by relocs/nativeInst/ic code
1266 __ jump(RuntimeAddress(__ pc()));
1267
1268 __ end_a_stub();
1269 // Update current stubs pointer and restore insts_end.
1270 }
1271 // size of call stub, compiled java to interpretor
1272 uint size_java_to_interp() {
1273 return 10; // movl; jmp
1274 }
1275 // relocation entries for call stub, compiled java to interpretor
1276 uint reloc_java_to_interp() {
1277 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1278 }
1279
1280 //=============================================================================
1281 #ifndef PRODUCT
1282 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1283 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1284 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1285 st->print_cr("\tNOP");
1286 st->print_cr("\tNOP");
1287 if( !OptoBreakpoint )
1288 st->print_cr("\tNOP");
1289 }
1290 #endif
1291
1292 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1293 MacroAssembler masm(&cbuf);
1294 #ifdef ASSERT
1295 uint insts_size = cbuf.insts_size();
1296 #endif
1297 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1298 masm.jump_cc(Assembler::notEqual,
1299 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1300 /* WARNING these NOPs are critical so that verified entry point is properly
1301 aligned for patching by NativeJump::patch_verified_entry() */
1302 int nops_cnt = 2;
1303 if( !OptoBreakpoint ) // Leave space for int3
1304 nops_cnt += 1;
1305 masm.nop(nops_cnt);
1306
1307 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1308 }
1309
1310 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1311 return OptoBreakpoint ? 11 : 12;
1312 }
1313
1314
1315 //=============================================================================
1316 uint size_exception_handler() {
1317 // NativeCall instruction size is the same as NativeJump.
1318 // exception handler starts out as jump and can be patched to
1319 // a call be deoptimization. (4932387)
1320 // Note that this value is also credited (in output.cpp) to
1321 // the size of the code section.
1322 return NativeJump::instruction_size;
1323 }
1324
1325 // Emit exception handler code. Stuff framesize into a register
1326 // and call a VM stub routine.
1327 int emit_exception_handler(CodeBuffer& cbuf) {
1328
1329 // Note that the code buffer's insts_mark is always relative to insts.
1330 // That's why we must use the macroassembler to generate a handler.
1331 MacroAssembler _masm(&cbuf);
1332 address base =
1333 __ start_a_stub(size_exception_handler());
1334 if (base == NULL) return 0; // CodeBuffer::expand failed
1335 int offset = __ offset();
1336 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1337 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1338 __ end_a_stub();
1339 return offset;
1340 }
1341
1342 uint size_deopt_handler() {
1343 // NativeCall instruction size is the same as NativeJump.
1344 // exception handler starts out as jump and can be patched to
1345 // a call be deoptimization. (4932387)
1346 // Note that this value is also credited (in output.cpp) to
1347 // the size of the code section.
1348 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1349 }
1350
1351 // Emit deopt handler code.
1352 int emit_deopt_handler(CodeBuffer& cbuf) {
1353
1354 // Note that the code buffer's insts_mark is always relative to insts.
1355 // That's why we must use the macroassembler to generate a handler.
1356 MacroAssembler _masm(&cbuf);
1357 address base =
1358 __ start_a_stub(size_exception_handler());
1359 if (base == NULL) return 0; // CodeBuffer::expand failed
1360 int offset = __ offset();
1361 InternalAddress here(__ pc());
1362 __ pushptr(here.addr());
1363
1364 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1365 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1366 __ end_a_stub();
1367 return offset;
1368 }
1369
1370
1371 const bool Matcher::match_rule_supported(int opcode) {
1372 if (!has_match_rule(opcode))
1373 return false;
1374
1375 switch (opcode) {
1376 case Op_PopCountI:
1377 case Op_PopCountL:
1378 if (!UsePopCountInstruction)
1379 return false;
1380 case Op_CompareAndSwapL:
1381 if (!VM_Version::supports_cx8())
1382 return false;
1383 break;
1384 }
1385
1386 return true; // Per default match rules are supported.
1387 }
1388
1389 int Matcher::regnum_to_fpu_offset(int regnum) {
1390 return regnum - 32; // The FP registers are in the second chunk
1391 }
1392
1393 // This is UltraSparc specific, true just means we have fast l2f conversion
1394 const bool Matcher::convL2FSupported(void) {
1395 return true;
1396 }
1397
1398 // Is this branch offset short enough that a short branch can be used?
1399 //
1400 // NOTE: If the platform does not provide any short branch variants, then
1401 // this method should return false for offset 0.
1402 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1403 // The passed offset is relative to address of the branch.
1404 // On 86 a branch displacement is calculated relative to address
1405 // of a next instruction.
1406 offset -= br_size;
1407
1408 // the short version of jmpConUCF2 contains multiple branches,
1409 // making the reach slightly less
1410 if (rule == jmpConUCF2_rule)
1411 return (-126 <= offset && offset <= 125);
1412 return (-128 <= offset && offset <= 127);
1413 }
1414
1415 const bool Matcher::isSimpleConstant64(jlong value) {
1416 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1417 return false;
1418 }
1419
1420 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1421 const bool Matcher::init_array_count_is_in_bytes = false;
1422
1423 // Threshold size for cleararray.
1424 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1425
1426 // Needs 2 CMOV's for longs.
1427 const int Matcher::long_cmove_cost() { return 1; }
1428
1429 // No CMOVF/CMOVD with SSE/SSE2
1430 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1431
1432 // Should the Matcher clone shifts on addressing modes, expecting them to
1433 // be subsumed into complex addressing expressions or compute them into
1434 // registers? True for Intel but false for most RISCs
1435 const bool Matcher::clone_shift_expressions = true;
1436
1437 // Do we need to mask the count passed to shift instructions or does
1438 // the cpu only look at the lower 5/6 bits anyway?
1439 const bool Matcher::need_masked_shift_count = false;
1440
1441 bool Matcher::narrow_oop_use_complex_address() {
1442 ShouldNotCallThis();
1443 return true;
1444 }
1445
1446
1447 // Is it better to copy float constants, or load them directly from memory?
1448 // Intel can load a float constant from a direct address, requiring no
1449 // extra registers. Most RISCs will have to materialize an address into a
1450 // register first, so they would do better to copy the constant from stack.
1451 const bool Matcher::rematerialize_float_constants = true;
1452
1453 // If CPU can load and store mis-aligned doubles directly then no fixup is
1454 // needed. Else we split the double into 2 integer pieces and move it
1455 // piece-by-piece. Only happens when passing doubles into C code as the
1456 // Java calling convention forces doubles to be aligned.
1457 const bool Matcher::misaligned_doubles_ok = true;
1458
1459
1460 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1461 // Get the memory operand from the node
1462 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1463 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1464 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1465 uint opcnt = 1; // First operand
1466 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1467 while( idx >= skipped+num_edges ) {
1468 skipped += num_edges;
1469 opcnt++; // Bump operand count
1470 assert( opcnt < numopnds, "Accessing non-existent operand" );
1471 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1472 }
1473
1474 MachOper *memory = node->_opnds[opcnt];
1475 MachOper *new_memory = NULL;
1476 switch (memory->opcode()) {
1477 case DIRECT:
1478 case INDOFFSET32X:
1479 // No transformation necessary.
1480 return;
1481 case INDIRECT:
1482 new_memory = new (C) indirect_win95_safeOper( );
1483 break;
1484 case INDOFFSET8:
1485 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1486 break;
1487 case INDOFFSET32:
1488 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1489 break;
1490 case INDINDEXOFFSET:
1491 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1492 break;
1493 case INDINDEXSCALE:
1494 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1495 break;
1496 case INDINDEXSCALEOFFSET:
1497 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1498 break;
1499 case LOAD_LONG_INDIRECT:
1500 case LOAD_LONG_INDOFFSET32:
1501 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1502 return;
1503 default:
1504 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1505 return;
1506 }
1507 node->_opnds[opcnt] = new_memory;
1508 }
1509
1510 // Advertise here if the CPU requires explicit rounding operations
1511 // to implement the UseStrictFP mode.
1512 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1513
1514 // Are floats conerted to double when stored to stack during deoptimization?
1515 // On x32 it is stored with convertion only when FPU is used for floats.
1516 bool Matcher::float_in_double() { return (UseSSE == 0); }
1517
1518 // Do ints take an entire long register or just half?
1519 const bool Matcher::int_in_long = false;
1520
1521 // Return whether or not this register is ever used as an argument. This
1522 // function is used on startup to build the trampoline stubs in generateOptoStub.
1523 // Registers not mentioned will be killed by the VM call in the trampoline, and
1524 // arguments in those registers not be available to the callee.
1525 bool Matcher::can_be_java_arg( int reg ) {
1526 if( reg == ECX_num || reg == EDX_num ) return true;
1527 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1528 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1529 return false;
1530 }
1531
1532 bool Matcher::is_spillable_arg( int reg ) {
1533 return can_be_java_arg(reg);
1534 }
1535
1536 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1537 // Use hardware integer DIV instruction when
1538 // it is faster than a code which use multiply.
1539 // Only when constant divisor fits into 32 bit
1540 // (min_jint is excluded to get only correct
1541 // positive 32 bit values from negative).
1542 return VM_Version::has_fast_idiv() &&
1543 (divisor == (int)divisor && divisor != min_jint);
1544 }
1545
1546 // Register for DIVI projection of divmodI
1547 RegMask Matcher::divI_proj_mask() {
1548 return EAX_REG_mask();
1549 }
1550
1551 // Register for MODI projection of divmodI
1552 RegMask Matcher::modI_proj_mask() {
1553 return EDX_REG_mask();
1554 }
1555
1556 // Register for DIVL projection of divmodL
1557 RegMask Matcher::divL_proj_mask() {
1558 ShouldNotReachHere();
1559 return RegMask();
1560 }
1561
1562 // Register for MODL projection of divmodL
1563 RegMask Matcher::modL_proj_mask() {
1564 ShouldNotReachHere();
1565 return RegMask();
1566 }
1567
1568 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1569 return EBP_REG_mask();
1570 }
1571
1572 // Returns true if the high 32 bits of the value is known to be zero.
1573 bool is_operand_hi32_zero(Node* n) {
1574 int opc = n->Opcode();
1575 if (opc == Op_LoadUI2L) {
1576 return true;
1577 }
1578 if (opc == Op_AndL) {
1579 Node* o2 = n->in(2);
1580 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1581 return true;
1582 }
1583 }
1584 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1585 return true;
1586 }
1587 return false;
1588 }
1589
1590 %}
1591
1592 //----------ENCODING BLOCK-----------------------------------------------------
1593 // This block specifies the encoding classes used by the compiler to output
1594 // byte streams. Encoding classes generate functions which are called by
1595 // Machine Instruction Nodes in order to generate the bit encoding of the
1596 // instruction. Operands specify their base encoding interface with the
1597 // interface keyword. There are currently supported four interfaces,
1598 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1599 // operand to generate a function which returns its register number when
1600 // queried. CONST_INTER causes an operand to generate a function which
1601 // returns the value of the constant when queried. MEMORY_INTER causes an
1602 // operand to generate four functions which return the Base Register, the
1603 // Index Register, the Scale Value, and the Offset Value of the operand when
1604 // queried. COND_INTER causes an operand to generate six functions which
1605 // return the encoding code (ie - encoding bits for the instruction)
1606 // associated with each basic boolean condition for a conditional instruction.
1607 // Instructions specify two basic values for encoding. They use the
1608 // ins_encode keyword to specify their encoding class (which must be one of
1609 // the class names specified in the encoding block), and they use the
1610 // opcode keyword to specify, in order, their primary, secondary, and
1611 // tertiary opcode. Only the opcode sections which a particular instruction
1612 // needs for encoding need to be specified.
1613 encode %{
1614 // Build emit functions for each basic byte or larger field in the intel
1615 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1616 // code in the enc_class source block. Emit functions will live in the
1617 // main source block for now. In future, we can generalize this by
1618 // adding a syntax that specifies the sizes of fields in an order,
1619 // so that the adlc can build the emit functions automagically
1620
1621 // Emit primary opcode
1622 enc_class OpcP %{
1623 emit_opcode(cbuf, $primary);
1624 %}
1625
1626 // Emit secondary opcode
1627 enc_class OpcS %{
1628 emit_opcode(cbuf, $secondary);
1629 %}
1630
1631 // Emit opcode directly
1632 enc_class Opcode(immI d8) %{
1633 emit_opcode(cbuf, $d8$$constant);
1634 %}
1635
1636 enc_class SizePrefix %{
1637 emit_opcode(cbuf,0x66);
1638 %}
1639
1640 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1641 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1642 %}
1643
1644 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1645 emit_opcode(cbuf,$opcode$$constant);
1646 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1647 %}
1648
1649 enc_class mov_r32_imm0( rRegI dst ) %{
1650 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1651 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1652 %}
1653
1654 enc_class cdq_enc %{
1655 // Full implementation of Java idiv and irem; checks for
1656 // special case as described in JVM spec., p.243 & p.271.
1657 //
1658 // normal case special case
1659 //
1660 // input : rax,: dividend min_int
1661 // reg: divisor -1
1662 //
1663 // output: rax,: quotient (= rax, idiv reg) min_int
1664 // rdx: remainder (= rax, irem reg) 0
1665 //
1666 // Code sequnce:
1667 //
1668 // 81 F8 00 00 00 80 cmp rax,80000000h
1669 // 0F 85 0B 00 00 00 jne normal_case
1670 // 33 D2 xor rdx,edx
1671 // 83 F9 FF cmp rcx,0FFh
1672 // 0F 84 03 00 00 00 je done
1673 // normal_case:
1674 // 99 cdq
1675 // F7 F9 idiv rax,ecx
1676 // done:
1677 //
1678 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1679 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1680 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1681 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1682 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1683 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1684 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1685 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1686 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1687 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1688 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1689 // normal_case:
1690 emit_opcode(cbuf,0x99); // cdq
1691 // idiv (note: must be emitted by the user of this rule)
1692 // normal:
1693 %}
1694
1695 // Dense encoding for older common ops
1696 enc_class Opc_plus(immI opcode, rRegI reg) %{
1697 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1698 %}
1699
1700
1701 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1702 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1703 // Check for 8-bit immediate, and set sign extend bit in opcode
1704 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1705 emit_opcode(cbuf, $primary | 0x02);
1706 }
1707 else { // If 32-bit immediate
1708 emit_opcode(cbuf, $primary);
1709 }
1710 %}
1711
1712 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1713 // Emit primary opcode and set sign-extend bit
1714 // Check for 8-bit immediate, and set sign extend bit in opcode
1715 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1716 emit_opcode(cbuf, $primary | 0x02); }
1717 else { // If 32-bit immediate
1718 emit_opcode(cbuf, $primary);
1719 }
1720 // Emit r/m byte with secondary opcode, after primary opcode.
1721 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1722 %}
1723
1724 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1725 // Check for 8-bit immediate, and set sign extend bit in opcode
1726 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1727 $$$emit8$imm$$constant;
1728 }
1729 else { // If 32-bit immediate
1730 // Output immediate
1731 $$$emit32$imm$$constant;
1732 }
1733 %}
1734
1735 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1736 // Emit primary opcode and set sign-extend bit
1737 // Check for 8-bit immediate, and set sign extend bit in opcode
1738 int con = (int)$imm$$constant; // Throw away top bits
1739 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1740 // Emit r/m byte with secondary opcode, after primary opcode.
1741 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1742 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1743 else emit_d32(cbuf,con);
1744 %}
1745
1746 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1747 // Emit primary opcode and set sign-extend bit
1748 // Check for 8-bit immediate, and set sign extend bit in opcode
1749 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1750 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1751 // Emit r/m byte with tertiary opcode, after primary opcode.
1752 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1753 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1754 else emit_d32(cbuf,con);
1755 %}
1756
1757 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1758 emit_cc(cbuf, $secondary, $dst$$reg );
1759 %}
1760
1761 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1762 int destlo = $dst$$reg;
1763 int desthi = HIGH_FROM_LOW(destlo);
1764 // bswap lo
1765 emit_opcode(cbuf, 0x0F);
1766 emit_cc(cbuf, 0xC8, destlo);
1767 // bswap hi
1768 emit_opcode(cbuf, 0x0F);
1769 emit_cc(cbuf, 0xC8, desthi);
1770 // xchg lo and hi
1771 emit_opcode(cbuf, 0x87);
1772 emit_rm(cbuf, 0x3, destlo, desthi);
1773 %}
1774
1775 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1776 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1777 %}
1778
1779 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1780 $$$emit8$primary;
1781 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1782 %}
1783
1784 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1785 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1786 emit_d8(cbuf, op >> 8 );
1787 emit_d8(cbuf, op & 255);
1788 %}
1789
1790 // emulate a CMOV with a conditional branch around a MOV
1791 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1792 // Invert sense of branch from sense of CMOV
1793 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1794 emit_d8( cbuf, $brOffs$$constant );
1795 %}
1796
1797 enc_class enc_PartialSubtypeCheck( ) %{
1798 Register Redi = as_Register(EDI_enc); // result register
1799 Register Reax = as_Register(EAX_enc); // super class
1800 Register Recx = as_Register(ECX_enc); // killed
1801 Register Resi = as_Register(ESI_enc); // sub class
1802 Label miss;
1803
1804 MacroAssembler _masm(&cbuf);
1805 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1806 NULL, &miss,
1807 /*set_cond_codes:*/ true);
1808 if ($primary) {
1809 __ xorptr(Redi, Redi);
1810 }
1811 __ bind(miss);
1812 %}
1813
1814 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1815 MacroAssembler masm(&cbuf);
1816 int start = masm.offset();
1817 if (UseSSE >= 2) {
1818 if (VerifyFPU) {
1819 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1820 }
1821 } else {
1822 // External c_calling_convention expects the FPU stack to be 'clean'.
1823 // Compiled code leaves it dirty. Do cleanup now.
1824 masm.empty_FPU_stack();
1825 }
1826 if (sizeof_FFree_Float_Stack_All == -1) {
1827 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1828 } else {
1829 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1830 }
1831 %}
1832
1833 enc_class Verify_FPU_For_Leaf %{
1834 if( VerifyFPU ) {
1835 MacroAssembler masm(&cbuf);
1836 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1837 }
1838 %}
1839
1840 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1841 // This is the instruction starting address for relocation info.
1842 cbuf.set_insts_mark();
1843 $$$emit8$primary;
1844 // CALL directly to the runtime
1845 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1846 runtime_call_Relocation::spec(), RELOC_IMM32 );
1847
1848 if (UseSSE >= 2) {
1849 MacroAssembler _masm(&cbuf);
1850 BasicType rt = tf()->return_type();
1851
1852 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1853 // A C runtime call where the return value is unused. In SSE2+
1854 // mode the result needs to be removed from the FPU stack. It's
1855 // likely that this function call could be removed by the
1856 // optimizer if the C function is a pure function.
1857 __ ffree(0);
1858 } else if (rt == T_FLOAT) {
1859 __ lea(rsp, Address(rsp, -4));
1860 __ fstp_s(Address(rsp, 0));
1861 __ movflt(xmm0, Address(rsp, 0));
1862 __ lea(rsp, Address(rsp, 4));
1863 } else if (rt == T_DOUBLE) {
1864 __ lea(rsp, Address(rsp, -8));
1865 __ fstp_d(Address(rsp, 0));
1866 __ movdbl(xmm0, Address(rsp, 0));
1867 __ lea(rsp, Address(rsp, 8));
1868 }
1869 }
1870 %}
1871
1872
1873 enc_class pre_call_FPU %{
1874 // If method sets FPU control word restore it here
1875 debug_only(int off0 = cbuf.insts_size());
1876 if( Compile::current()->in_24_bit_fp_mode() ) {
1877 MacroAssembler masm(&cbuf);
1878 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1879 }
1880 debug_only(int off1 = cbuf.insts_size());
1881 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1882 %}
1883
1884 enc_class post_call_FPU %{
1885 // If method sets FPU control word do it here also
1886 if( Compile::current()->in_24_bit_fp_mode() ) {
1887 MacroAssembler masm(&cbuf);
1888 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1889 }
1890 %}
1891
1892 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1893 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1894 // who we intended to call.
1895 cbuf.set_insts_mark();
1896 $$$emit8$primary;
1897 if ( !_method ) {
1898 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1899 runtime_call_Relocation::spec(), RELOC_IMM32 );
1900 } else if(_optimized_virtual) {
1901 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1902 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1903 } else {
1904 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1905 static_call_Relocation::spec(), RELOC_IMM32 );
1906 }
1907 if( _method ) { // Emit stub for static call
1908 emit_java_to_interp(cbuf);
1909 }
1910 %}
1911
1912 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1913 // !!!!!
1914 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1915 // emit_call_dynamic_prologue( cbuf );
1916 cbuf.set_insts_mark();
1917 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1918 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1919 address virtual_call_oop_addr = cbuf.insts_mark();
1920 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1921 // who we intended to call.
1922 cbuf.set_insts_mark();
1923 $$$emit8$primary;
1924 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1925 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1926 %}
1927
1928 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1929 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1930 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1931
1932 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1933 cbuf.set_insts_mark();
1934 $$$emit8$primary;
1935 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1936 emit_d8(cbuf, disp); // Displacement
1937
1938 %}
1939
1940 // Following encoding is no longer used, but may be restored if calling
1941 // convention changes significantly.
1942 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1943 //
1944 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1945 // // int ic_reg = Matcher::inline_cache_reg();
1946 // // int ic_encode = Matcher::_regEncode[ic_reg];
1947 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1948 // // int imo_encode = Matcher::_regEncode[imo_reg];
1949 //
1950 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1951 // // // so we load it immediately before the call
1952 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1953 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1954 //
1955 // // xor rbp,ebp
1956 // emit_opcode(cbuf, 0x33);
1957 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1958 //
1959 // // CALL to interpreter.
1960 // cbuf.set_insts_mark();
1961 // $$$emit8$primary;
1962 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1963 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1964 // %}
1965
1966 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1967 $$$emit8$primary;
1968 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1969 $$$emit8$shift$$constant;
1970 %}
1971
1972 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1973 // Load immediate does not have a zero or sign extended version
1974 // for 8-bit immediates
1975 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1976 $$$emit32$src$$constant;
1977 %}
1978
1979 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1980 // Load immediate does not have a zero or sign extended version
1981 // for 8-bit immediates
1982 emit_opcode(cbuf, $primary + $dst$$reg);
1983 $$$emit32$src$$constant;
1984 %}
1985
1986 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1987 // Load immediate does not have a zero or sign extended version
1988 // for 8-bit immediates
1989 int dst_enc = $dst$$reg;
1990 int src_con = $src$$constant & 0x0FFFFFFFFL;
1991 if (src_con == 0) {
1992 // xor dst, dst
1993 emit_opcode(cbuf, 0x33);
1994 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1995 } else {
1996 emit_opcode(cbuf, $primary + dst_enc);
1997 emit_d32(cbuf, src_con);
1998 }
1999 %}
2000
2001 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
2002 // Load immediate does not have a zero or sign extended version
2003 // for 8-bit immediates
2004 int dst_enc = $dst$$reg + 2;
2005 int src_con = ((julong)($src$$constant)) >> 32;
2006 if (src_con == 0) {
2007 // xor dst, dst
2008 emit_opcode(cbuf, 0x33);
2009 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
2010 } else {
2011 emit_opcode(cbuf, $primary + dst_enc);
2012 emit_d32(cbuf, src_con);
2013 }
2014 %}
2015
2016
2017 // Encode a reg-reg copy. If it is useless, then empty encoding.
2018 enc_class enc_Copy( rRegI dst, rRegI src ) %{
2019 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2020 %}
2021
2022 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
2023 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2024 %}
2025
2026 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
2027 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2028 %}
2029
2030 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2031 $$$emit8$primary;
2032 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2033 %}
2034
2035 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2036 $$$emit8$secondary;
2037 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2038 %}
2039
2040 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2041 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2042 %}
2043
2044 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2045 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2046 %}
2047
2048 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2049 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2050 %}
2051
2052 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2053 // Output immediate
2054 $$$emit32$src$$constant;
2055 %}
2056
2057 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2058 // Output Float immediate bits
2059 jfloat jf = $src$$constant;
2060 int jf_as_bits = jint_cast( jf );
2061 emit_d32(cbuf, jf_as_bits);
2062 %}
2063
2064 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2065 // Output Float immediate bits
2066 jfloat jf = $src$$constant;
2067 int jf_as_bits = jint_cast( jf );
2068 emit_d32(cbuf, jf_as_bits);
2069 %}
2070
2071 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2072 // Output immediate
2073 $$$emit16$src$$constant;
2074 %}
2075
2076 enc_class Con_d32(immI src) %{
2077 emit_d32(cbuf,$src$$constant);
2078 %}
2079
2080 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2081 // Output immediate memory reference
2082 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2083 emit_d32(cbuf, 0x00);
2084 %}
2085
2086 enc_class lock_prefix( ) %{
2087 if( os::is_MP() )
2088 emit_opcode(cbuf,0xF0); // [Lock]
2089 %}
2090
2091 // Cmp-xchg long value.
2092 // Note: we need to swap rbx, and rcx before and after the
2093 // cmpxchg8 instruction because the instruction uses
2094 // rcx as the high order word of the new value to store but
2095 // our register encoding uses rbx,.
2096 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2097
2098 // XCHG rbx,ecx
2099 emit_opcode(cbuf,0x87);
2100 emit_opcode(cbuf,0xD9);
2101 // [Lock]
2102 if( os::is_MP() )
2103 emit_opcode(cbuf,0xF0);
2104 // CMPXCHG8 [Eptr]
2105 emit_opcode(cbuf,0x0F);
2106 emit_opcode(cbuf,0xC7);
2107 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2108 // XCHG rbx,ecx
2109 emit_opcode(cbuf,0x87);
2110 emit_opcode(cbuf,0xD9);
2111 %}
2112
2113 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2114 // [Lock]
2115 if( os::is_MP() )
2116 emit_opcode(cbuf,0xF0);
2117
2118 // CMPXCHG [Eptr]
2119 emit_opcode(cbuf,0x0F);
2120 emit_opcode(cbuf,0xB1);
2121 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2122 %}
2123
2124 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2125 int res_encoding = $res$$reg;
2126
2127 // MOV res,0
2128 emit_opcode( cbuf, 0xB8 + res_encoding);
2129 emit_d32( cbuf, 0 );
2130 // JNE,s fail
2131 emit_opcode(cbuf,0x75);
2132 emit_d8(cbuf, 5 );
2133 // MOV res,1
2134 emit_opcode( cbuf, 0xB8 + res_encoding);
2135 emit_d32( cbuf, 1 );
2136 // fail:
2137 %}
2138
2139 enc_class set_instruction_start( ) %{
2140 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2141 %}
2142
2143 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2144 int reg_encoding = $ereg$$reg;
2145 int base = $mem$$base;
2146 int index = $mem$$index;
2147 int scale = $mem$$scale;
2148 int displace = $mem$$disp;
2149 bool disp_is_oop = $mem->disp_is_oop();
2150 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2151 %}
2152
2153 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2154 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2155 int base = $mem$$base;
2156 int index = $mem$$index;
2157 int scale = $mem$$scale;
2158 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2159 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2160 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2161 %}
2162
2163 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2164 int r1, r2;
2165 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2166 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2167 emit_opcode(cbuf,0x0F);
2168 emit_opcode(cbuf,$tertiary);
2169 emit_rm(cbuf, 0x3, r1, r2);
2170 emit_d8(cbuf,$cnt$$constant);
2171 emit_d8(cbuf,$primary);
2172 emit_rm(cbuf, 0x3, $secondary, r1);
2173 emit_d8(cbuf,$cnt$$constant);
2174 %}
2175
2176 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2177 emit_opcode( cbuf, 0x8B ); // Move
2178 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2179 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2180 emit_d8(cbuf,$primary);
2181 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2182 emit_d8(cbuf,$cnt$$constant-32);
2183 }
2184 emit_d8(cbuf,$primary);
2185 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2186 emit_d8(cbuf,31);
2187 %}
2188
2189 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2190 int r1, r2;
2191 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2192 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2193
2194 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2195 emit_rm(cbuf, 0x3, r1, r2);
2196 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2197 emit_opcode(cbuf,$primary);
2198 emit_rm(cbuf, 0x3, $secondary, r1);
2199 emit_d8(cbuf,$cnt$$constant-32);
2200 }
2201 emit_opcode(cbuf,0x33); // XOR r2,r2
2202 emit_rm(cbuf, 0x3, r2, r2);
2203 %}
2204
2205 // Clone of RegMem but accepts an extra parameter to access each
2206 // half of a double in memory; it never needs relocation info.
2207 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2208 emit_opcode(cbuf,$opcode$$constant);
2209 int reg_encoding = $rm_reg$$reg;
2210 int base = $mem$$base;
2211 int index = $mem$$index;
2212 int scale = $mem$$scale;
2213 int displace = $mem$$disp + $disp_for_half$$constant;
2214 bool disp_is_oop = false;
2215 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2216 %}
2217
2218 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2219 //
2220 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2221 // and it never needs relocation information.
2222 // Frequently used to move data between FPU's Stack Top and memory.
2223 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2224 int rm_byte_opcode = $rm_opcode$$constant;
2225 int base = $mem$$base;
2226 int index = $mem$$index;
2227 int scale = $mem$$scale;
2228 int displace = $mem$$disp;
2229 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2230 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2231 %}
2232
2233 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2234 int rm_byte_opcode = $rm_opcode$$constant;
2235 int base = $mem$$base;
2236 int index = $mem$$index;
2237 int scale = $mem$$scale;
2238 int displace = $mem$$disp;
2239 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2240 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2241 %}
2242
2243 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2244 int reg_encoding = $dst$$reg;
2245 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2246 int index = 0x04; // 0x04 indicates no index
2247 int scale = 0x00; // 0x00 indicates no scale
2248 int displace = $src1$$constant; // 0x00 indicates no displacement
2249 bool disp_is_oop = false;
2250 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2251 %}
2252
2253 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2254 // Compare dst,src
2255 emit_opcode(cbuf,0x3B);
2256 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2257 // jmp dst < src around move
2258 emit_opcode(cbuf,0x7C);
2259 emit_d8(cbuf,2);
2260 // move dst,src
2261 emit_opcode(cbuf,0x8B);
2262 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2263 %}
2264
2265 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2266 // Compare dst,src
2267 emit_opcode(cbuf,0x3B);
2268 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2269 // jmp dst > src around move
2270 emit_opcode(cbuf,0x7F);
2271 emit_d8(cbuf,2);
2272 // move dst,src
2273 emit_opcode(cbuf,0x8B);
2274 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2275 %}
2276
2277 enc_class enc_FPR_store(memory mem, regDPR src) %{
2278 // If src is FPR1, we can just FST to store it.
2279 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2280 int reg_encoding = 0x2; // Just store
2281 int base = $mem$$base;
2282 int index = $mem$$index;
2283 int scale = $mem$$scale;
2284 int displace = $mem$$disp;
2285 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2286 if( $src$$reg != FPR1L_enc ) {
2287 reg_encoding = 0x3; // Store & pop
2288 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2289 emit_d8( cbuf, 0xC0-1+$src$$reg );
2290 }
2291 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2292 emit_opcode(cbuf,$primary);
2293 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2294 %}
2295
2296 enc_class neg_reg(rRegI dst) %{
2297 // NEG $dst
2298 emit_opcode(cbuf,0xF7);
2299 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2300 %}
2301
2302 enc_class setLT_reg(eCXRegI dst) %{
2303 // SETLT $dst
2304 emit_opcode(cbuf,0x0F);
2305 emit_opcode(cbuf,0x9C);
2306 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2307 %}
2308
2309 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2310 int tmpReg = $tmp$$reg;
2311
2312 // SUB $p,$q
2313 emit_opcode(cbuf,0x2B);
2314 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2315 // SBB $tmp,$tmp
2316 emit_opcode(cbuf,0x1B);
2317 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2318 // AND $tmp,$y
2319 emit_opcode(cbuf,0x23);
2320 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2321 // ADD $p,$tmp
2322 emit_opcode(cbuf,0x03);
2323 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2324 %}
2325
2326 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2327 int tmpReg = $tmp$$reg;
2328
2329 // SUB $p,$q
2330 emit_opcode(cbuf,0x2B);
2331 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2332 // SBB $tmp,$tmp
2333 emit_opcode(cbuf,0x1B);
2334 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2335 // AND $tmp,$y
2336 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2337 emit_opcode(cbuf,0x23);
2338 int reg_encoding = tmpReg;
2339 int base = $mem$$base;
2340 int index = $mem$$index;
2341 int scale = $mem$$scale;
2342 int displace = $mem$$disp;
2343 bool disp_is_oop = $mem->disp_is_oop();
2344 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2345 // ADD $p,$tmp
2346 emit_opcode(cbuf,0x03);
2347 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2348 %}
2349
2350 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2351 // TEST shift,32
2352 emit_opcode(cbuf,0xF7);
2353 emit_rm(cbuf, 0x3, 0, ECX_enc);
2354 emit_d32(cbuf,0x20);
2355 // JEQ,s small
2356 emit_opcode(cbuf, 0x74);
2357 emit_d8(cbuf, 0x04);
2358 // MOV $dst.hi,$dst.lo
2359 emit_opcode( cbuf, 0x8B );
2360 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2361 // CLR $dst.lo
2362 emit_opcode(cbuf, 0x33);
2363 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2364 // small:
2365 // SHLD $dst.hi,$dst.lo,$shift
2366 emit_opcode(cbuf,0x0F);
2367 emit_opcode(cbuf,0xA5);
2368 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2369 // SHL $dst.lo,$shift"
2370 emit_opcode(cbuf,0xD3);
2371 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2372 %}
2373
2374 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2375 // TEST shift,32
2376 emit_opcode(cbuf,0xF7);
2377 emit_rm(cbuf, 0x3, 0, ECX_enc);
2378 emit_d32(cbuf,0x20);
2379 // JEQ,s small
2380 emit_opcode(cbuf, 0x74);
2381 emit_d8(cbuf, 0x04);
2382 // MOV $dst.lo,$dst.hi
2383 emit_opcode( cbuf, 0x8B );
2384 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2385 // CLR $dst.hi
2386 emit_opcode(cbuf, 0x33);
2387 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2388 // small:
2389 // SHRD $dst.lo,$dst.hi,$shift
2390 emit_opcode(cbuf,0x0F);
2391 emit_opcode(cbuf,0xAD);
2392 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2393 // SHR $dst.hi,$shift"
2394 emit_opcode(cbuf,0xD3);
2395 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2396 %}
2397
2398 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2399 // TEST shift,32
2400 emit_opcode(cbuf,0xF7);
2401 emit_rm(cbuf, 0x3, 0, ECX_enc);
2402 emit_d32(cbuf,0x20);
2403 // JEQ,s small
2404 emit_opcode(cbuf, 0x74);
2405 emit_d8(cbuf, 0x05);
2406 // MOV $dst.lo,$dst.hi
2407 emit_opcode( cbuf, 0x8B );
2408 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2409 // SAR $dst.hi,31
2410 emit_opcode(cbuf, 0xC1);
2411 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2412 emit_d8(cbuf, 0x1F );
2413 // small:
2414 // SHRD $dst.lo,$dst.hi,$shift
2415 emit_opcode(cbuf,0x0F);
2416 emit_opcode(cbuf,0xAD);
2417 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2418 // SAR $dst.hi,$shift"
2419 emit_opcode(cbuf,0xD3);
2420 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2421 %}
2422
2423
2424 // ----------------- Encodings for floating point unit -----------------
2425 // May leave result in FPU-TOS or FPU reg depending on opcodes
2426 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2427 $$$emit8$primary;
2428 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2429 %}
2430
2431 // Pop argument in FPR0 with FSTP ST(0)
2432 enc_class PopFPU() %{
2433 emit_opcode( cbuf, 0xDD );
2434 emit_d8( cbuf, 0xD8 );
2435 %}
2436
2437 // !!!!! equivalent to Pop_Reg_F
2438 enc_class Pop_Reg_DPR( regDPR dst ) %{
2439 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2440 emit_d8( cbuf, 0xD8+$dst$$reg );
2441 %}
2442
2443 enc_class Push_Reg_DPR( regDPR dst ) %{
2444 emit_opcode( cbuf, 0xD9 );
2445 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2446 %}
2447
2448 enc_class strictfp_bias1( regDPR dst ) %{
2449 emit_opcode( cbuf, 0xDB ); // FLD m80real
2450 emit_opcode( cbuf, 0x2D );
2451 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2452 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2453 emit_opcode( cbuf, 0xC8+$dst$$reg );
2454 %}
2455
2456 enc_class strictfp_bias2( regDPR dst ) %{
2457 emit_opcode( cbuf, 0xDB ); // FLD m80real
2458 emit_opcode( cbuf, 0x2D );
2459 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2460 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2461 emit_opcode( cbuf, 0xC8+$dst$$reg );
2462 %}
2463
2464 // Special case for moving an integer register to a stack slot.
2465 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2466 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2467 %}
2468
2469 // Special case for moving a register to a stack slot.
2470 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2471 // Opcode already emitted
2472 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2473 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2474 emit_d32(cbuf, $dst$$disp); // Displacement
2475 %}
2476
2477 // Push the integer in stackSlot 'src' onto FP-stack
2478 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2479 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2480 %}
2481
2482 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2483 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2484 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2485 %}
2486
2487 // Same as Pop_Mem_F except for opcode
2488 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2489 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2490 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2491 %}
2492
2493 enc_class Pop_Reg_FPR( regFPR dst ) %{
2494 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2495 emit_d8( cbuf, 0xD8+$dst$$reg );
2496 %}
2497
2498 enc_class Push_Reg_FPR( regFPR dst ) %{
2499 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2500 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2501 %}
2502
2503 // Push FPU's float to a stack-slot, and pop FPU-stack
2504 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2505 int pop = 0x02;
2506 if ($src$$reg != FPR1L_enc) {
2507 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2508 emit_d8( cbuf, 0xC0-1+$src$$reg );
2509 pop = 0x03;
2510 }
2511 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2512 %}
2513
2514 // Push FPU's double to a stack-slot, and pop FPU-stack
2515 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2516 int pop = 0x02;
2517 if ($src$$reg != FPR1L_enc) {
2518 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2519 emit_d8( cbuf, 0xC0-1+$src$$reg );
2520 pop = 0x03;
2521 }
2522 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2523 %}
2524
2525 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2526 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2527 int pop = 0xD0 - 1; // -1 since we skip FLD
2528 if ($src$$reg != FPR1L_enc) {
2529 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2530 emit_d8( cbuf, 0xC0-1+$src$$reg );
2531 pop = 0xD8;
2532 }
2533 emit_opcode( cbuf, 0xDD );
2534 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2535 %}
2536
2537
2538 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2539 // load dst in FPR0
2540 emit_opcode( cbuf, 0xD9 );
2541 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2542 if ($src$$reg != FPR1L_enc) {
2543 // fincstp
2544 emit_opcode (cbuf, 0xD9);
2545 emit_opcode (cbuf, 0xF7);
2546 // swap src with FPR1:
2547 // FXCH FPR1 with src
2548 emit_opcode(cbuf, 0xD9);
2549 emit_d8(cbuf, 0xC8-1+$src$$reg );
2550 // fdecstp
2551 emit_opcode (cbuf, 0xD9);
2552 emit_opcode (cbuf, 0xF6);
2553 }
2554 %}
2555
2556 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2557 MacroAssembler _masm(&cbuf);
2558 __ subptr(rsp, 8);
2559 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2560 __ fld_d(Address(rsp, 0));
2561 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2562 __ fld_d(Address(rsp, 0));
2563 %}
2564
2565 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2566 MacroAssembler _masm(&cbuf);
2567 __ subptr(rsp, 4);
2568 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2569 __ fld_s(Address(rsp, 0));
2570 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2571 __ fld_s(Address(rsp, 0));
2572 %}
2573
2574 enc_class Push_ResultD(regD dst) %{
2575 MacroAssembler _masm(&cbuf);
2576 __ fstp_d(Address(rsp, 0));
2577 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2578 __ addptr(rsp, 8);
2579 %}
2580
2581 enc_class Push_ResultF(regF dst, immI d8) %{
2582 MacroAssembler _masm(&cbuf);
2583 __ fstp_s(Address(rsp, 0));
2584 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2585 __ addptr(rsp, $d8$$constant);
2586 %}
2587
2588 enc_class Push_SrcD(regD src) %{
2589 MacroAssembler _masm(&cbuf);
2590 __ subptr(rsp, 8);
2591 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2592 __ fld_d(Address(rsp, 0));
2593 %}
2594
2595 enc_class push_stack_temp_qword() %{
2596 MacroAssembler _masm(&cbuf);
2597 __ subptr(rsp, 8);
2598 %}
2599
2600 enc_class pop_stack_temp_qword() %{
2601 MacroAssembler _masm(&cbuf);
2602 __ addptr(rsp, 8);
2603 %}
2604
2605 enc_class push_xmm_to_fpr1(regD src) %{
2606 MacroAssembler _masm(&cbuf);
2607 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2608 __ fld_d(Address(rsp, 0));
2609 %}
2610
2611 enc_class Push_Result_Mod_DPR( regDPR src) %{
2612 if ($src$$reg != FPR1L_enc) {
2613 // fincstp
2614 emit_opcode (cbuf, 0xD9);
2615 emit_opcode (cbuf, 0xF7);
2616 // FXCH FPR1 with src
2617 emit_opcode(cbuf, 0xD9);
2618 emit_d8(cbuf, 0xC8-1+$src$$reg );
2619 // fdecstp
2620 emit_opcode (cbuf, 0xD9);
2621 emit_opcode (cbuf, 0xF6);
2622 }
2623 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2624 // // FSTP FPR$dst$$reg
2625 // emit_opcode( cbuf, 0xDD );
2626 // emit_d8( cbuf, 0xD8+$dst$$reg );
2627 %}
2628
2629 enc_class fnstsw_sahf_skip_parity() %{
2630 // fnstsw ax
2631 emit_opcode( cbuf, 0xDF );
2632 emit_opcode( cbuf, 0xE0 );
2633 // sahf
2634 emit_opcode( cbuf, 0x9E );
2635 // jnp ::skip
2636 emit_opcode( cbuf, 0x7B );
2637 emit_opcode( cbuf, 0x05 );
2638 %}
2639
2640 enc_class emitModDPR() %{
2641 // fprem must be iterative
2642 // :: loop
2643 // fprem
2644 emit_opcode( cbuf, 0xD9 );
2645 emit_opcode( cbuf, 0xF8 );
2646 // wait
2647 emit_opcode( cbuf, 0x9b );
2648 // fnstsw ax
2649 emit_opcode( cbuf, 0xDF );
2650 emit_opcode( cbuf, 0xE0 );
2651 // sahf
2652 emit_opcode( cbuf, 0x9E );
2653 // jp ::loop
2654 emit_opcode( cbuf, 0x0F );
2655 emit_opcode( cbuf, 0x8A );
2656 emit_opcode( cbuf, 0xF4 );
2657 emit_opcode( cbuf, 0xFF );
2658 emit_opcode( cbuf, 0xFF );
2659 emit_opcode( cbuf, 0xFF );
2660 %}
2661
2662 enc_class fpu_flags() %{
2663 // fnstsw_ax
2664 emit_opcode( cbuf, 0xDF);
2665 emit_opcode( cbuf, 0xE0);
2666 // test ax,0x0400
2667 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2668 emit_opcode( cbuf, 0xA9 );
2669 emit_d16 ( cbuf, 0x0400 );
2670 // // // This sequence works, but stalls for 12-16 cycles on PPro
2671 // // test rax,0x0400
2672 // emit_opcode( cbuf, 0xA9 );
2673 // emit_d32 ( cbuf, 0x00000400 );
2674 //
2675 // jz exit (no unordered comparison)
2676 emit_opcode( cbuf, 0x74 );
2677 emit_d8 ( cbuf, 0x02 );
2678 // mov ah,1 - treat as LT case (set carry flag)
2679 emit_opcode( cbuf, 0xB4 );
2680 emit_d8 ( cbuf, 0x01 );
2681 // sahf
2682 emit_opcode( cbuf, 0x9E);
2683 %}
2684
2685 enc_class cmpF_P6_fixup() %{
2686 // Fixup the integer flags in case comparison involved a NaN
2687 //
2688 // JNP exit (no unordered comparison, P-flag is set by NaN)
2689 emit_opcode( cbuf, 0x7B );
2690 emit_d8 ( cbuf, 0x03 );
2691 // MOV AH,1 - treat as LT case (set carry flag)
2692 emit_opcode( cbuf, 0xB4 );
2693 emit_d8 ( cbuf, 0x01 );
2694 // SAHF
2695 emit_opcode( cbuf, 0x9E);
2696 // NOP // target for branch to avoid branch to branch
2697 emit_opcode( cbuf, 0x90);
2698 %}
2699
2700 // fnstsw_ax();
2701 // sahf();
2702 // movl(dst, nan_result);
2703 // jcc(Assembler::parity, exit);
2704 // movl(dst, less_result);
2705 // jcc(Assembler::below, exit);
2706 // movl(dst, equal_result);
2707 // jcc(Assembler::equal, exit);
2708 // movl(dst, greater_result);
2709
2710 // less_result = 1;
2711 // greater_result = -1;
2712 // equal_result = 0;
2713 // nan_result = -1;
2714
2715 enc_class CmpF_Result(rRegI dst) %{
2716 // fnstsw_ax();
2717 emit_opcode( cbuf, 0xDF);
2718 emit_opcode( cbuf, 0xE0);
2719 // sahf
2720 emit_opcode( cbuf, 0x9E);
2721 // movl(dst, nan_result);
2722 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2723 emit_d32( cbuf, -1 );
2724 // jcc(Assembler::parity, exit);
2725 emit_opcode( cbuf, 0x7A );
2726 emit_d8 ( cbuf, 0x13 );
2727 // movl(dst, less_result);
2728 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2729 emit_d32( cbuf, -1 );
2730 // jcc(Assembler::below, exit);
2731 emit_opcode( cbuf, 0x72 );
2732 emit_d8 ( cbuf, 0x0C );
2733 // movl(dst, equal_result);
2734 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2735 emit_d32( cbuf, 0 );
2736 // jcc(Assembler::equal, exit);
2737 emit_opcode( cbuf, 0x74 );
2738 emit_d8 ( cbuf, 0x05 );
2739 // movl(dst, greater_result);
2740 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2741 emit_d32( cbuf, 1 );
2742 %}
2743
2744
2745 // Compare the longs and set flags
2746 // BROKEN! Do Not use as-is
2747 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2748 // CMP $src1.hi,$src2.hi
2749 emit_opcode( cbuf, 0x3B );
2750 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2751 // JNE,s done
2752 emit_opcode(cbuf,0x75);
2753 emit_d8(cbuf, 2 );
2754 // CMP $src1.lo,$src2.lo
2755 emit_opcode( cbuf, 0x3B );
2756 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2757 // done:
2758 %}
2759
2760 enc_class convert_int_long( regL dst, rRegI src ) %{
2761 // mov $dst.lo,$src
2762 int dst_encoding = $dst$$reg;
2763 int src_encoding = $src$$reg;
2764 encode_Copy( cbuf, dst_encoding , src_encoding );
2765 // mov $dst.hi,$src
2766 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2767 // sar $dst.hi,31
2768 emit_opcode( cbuf, 0xC1 );
2769 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2770 emit_d8(cbuf, 0x1F );
2771 %}
2772
2773 enc_class convert_long_double( eRegL src ) %{
2774 // push $src.hi
2775 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2776 // push $src.lo
2777 emit_opcode(cbuf, 0x50+$src$$reg );
2778 // fild 64-bits at [SP]
2779 emit_opcode(cbuf,0xdf);
2780 emit_d8(cbuf, 0x6C);
2781 emit_d8(cbuf, 0x24);
2782 emit_d8(cbuf, 0x00);
2783 // pop stack
2784 emit_opcode(cbuf, 0x83); // add SP, #8
2785 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2786 emit_d8(cbuf, 0x8);
2787 %}
2788
2789 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2790 // IMUL EDX:EAX,$src1
2791 emit_opcode( cbuf, 0xF7 );
2792 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2793 // SAR EDX,$cnt-32
2794 int shift_count = ((int)$cnt$$constant) - 32;
2795 if (shift_count > 0) {
2796 emit_opcode(cbuf, 0xC1);
2797 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2798 emit_d8(cbuf, shift_count);
2799 }
2800 %}
2801
2802 // this version doesn't have add sp, 8
2803 enc_class convert_long_double2( eRegL src ) %{
2804 // push $src.hi
2805 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2806 // push $src.lo
2807 emit_opcode(cbuf, 0x50+$src$$reg );
2808 // fild 64-bits at [SP]
2809 emit_opcode(cbuf,0xdf);
2810 emit_d8(cbuf, 0x6C);
2811 emit_d8(cbuf, 0x24);
2812 emit_d8(cbuf, 0x00);
2813 %}
2814
2815 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2816 // Basic idea: long = (long)int * (long)int
2817 // IMUL EDX:EAX, src
2818 emit_opcode( cbuf, 0xF7 );
2819 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2820 %}
2821
2822 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2823 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2824 // MUL EDX:EAX, src
2825 emit_opcode( cbuf, 0xF7 );
2826 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2827 %}
2828
2829 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2830 // Basic idea: lo(result) = lo(x_lo * y_lo)
2831 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2832 // MOV $tmp,$src.lo
2833 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2834 // IMUL $tmp,EDX
2835 emit_opcode( cbuf, 0x0F );
2836 emit_opcode( cbuf, 0xAF );
2837 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2838 // MOV EDX,$src.hi
2839 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2840 // IMUL EDX,EAX
2841 emit_opcode( cbuf, 0x0F );
2842 emit_opcode( cbuf, 0xAF );
2843 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2844 // ADD $tmp,EDX
2845 emit_opcode( cbuf, 0x03 );
2846 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2847 // MUL EDX:EAX,$src.lo
2848 emit_opcode( cbuf, 0xF7 );
2849 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2850 // ADD EDX,ESI
2851 emit_opcode( cbuf, 0x03 );
2852 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2853 %}
2854
2855 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2856 // Basic idea: lo(result) = lo(src * y_lo)
2857 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2858 // IMUL $tmp,EDX,$src
2859 emit_opcode( cbuf, 0x6B );
2860 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2861 emit_d8( cbuf, (int)$src$$constant );
2862 // MOV EDX,$src
2863 emit_opcode(cbuf, 0xB8 + EDX_enc);
2864 emit_d32( cbuf, (int)$src$$constant );
2865 // MUL EDX:EAX,EDX
2866 emit_opcode( cbuf, 0xF7 );
2867 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2868 // ADD EDX,ESI
2869 emit_opcode( cbuf, 0x03 );
2870 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2871 %}
2872
2873 enc_class long_div( eRegL src1, eRegL src2 ) %{
2874 // PUSH src1.hi
2875 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2876 // PUSH src1.lo
2877 emit_opcode(cbuf, 0x50+$src1$$reg );
2878 // PUSH src2.hi
2879 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2880 // PUSH src2.lo
2881 emit_opcode(cbuf, 0x50+$src2$$reg );
2882 // CALL directly to the runtime
2883 cbuf.set_insts_mark();
2884 emit_opcode(cbuf,0xE8); // Call into runtime
2885 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2886 // Restore stack
2887 emit_opcode(cbuf, 0x83); // add SP, #framesize
2888 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2889 emit_d8(cbuf, 4*4);
2890 %}
2891
2892 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2893 // PUSH src1.hi
2894 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2895 // PUSH src1.lo
2896 emit_opcode(cbuf, 0x50+$src1$$reg );
2897 // PUSH src2.hi
2898 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2899 // PUSH src2.lo
2900 emit_opcode(cbuf, 0x50+$src2$$reg );
2901 // CALL directly to the runtime
2902 cbuf.set_insts_mark();
2903 emit_opcode(cbuf,0xE8); // Call into runtime
2904 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2905 // Restore stack
2906 emit_opcode(cbuf, 0x83); // add SP, #framesize
2907 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2908 emit_d8(cbuf, 4*4);
2909 %}
2910
2911 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2912 // MOV $tmp,$src.lo
2913 emit_opcode(cbuf, 0x8B);
2914 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2915 // OR $tmp,$src.hi
2916 emit_opcode(cbuf, 0x0B);
2917 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2918 %}
2919
2920 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2921 // CMP $src1.lo,$src2.lo
2922 emit_opcode( cbuf, 0x3B );
2923 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2924 // JNE,s skip
2925 emit_cc(cbuf, 0x70, 0x5);
2926 emit_d8(cbuf,2);
2927 // CMP $src1.hi,$src2.hi
2928 emit_opcode( cbuf, 0x3B );
2929 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2930 %}
2931
2932 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2933 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2934 emit_opcode( cbuf, 0x3B );
2935 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2936 // MOV $tmp,$src1.hi
2937 emit_opcode( cbuf, 0x8B );
2938 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2939 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2940 emit_opcode( cbuf, 0x1B );
2941 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2942 %}
2943
2944 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2945 // XOR $tmp,$tmp
2946 emit_opcode(cbuf,0x33); // XOR
2947 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2948 // CMP $tmp,$src.lo
2949 emit_opcode( cbuf, 0x3B );
2950 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2951 // SBB $tmp,$src.hi
2952 emit_opcode( cbuf, 0x1B );
2953 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2954 %}
2955
2956 // Sniff, sniff... smells like Gnu Superoptimizer
2957 enc_class neg_long( eRegL dst ) %{
2958 emit_opcode(cbuf,0xF7); // NEG hi
2959 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2960 emit_opcode(cbuf,0xF7); // NEG lo
2961 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2962 emit_opcode(cbuf,0x83); // SBB hi,0
2963 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2964 emit_d8 (cbuf,0 );
2965 %}
2966
2967
2968 // Because the transitions from emitted code to the runtime
2969 // monitorenter/exit helper stubs are so slow it's critical that
2970 // we inline both the stack-locking fast-path and the inflated fast path.
2971 //
2972 // See also: cmpFastLock and cmpFastUnlock.
2973 //
2974 // What follows is a specialized inline transliteration of the code
2975 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2976 // another option would be to emit TrySlowEnter and TrySlowExit methods
2977 // at startup-time. These methods would accept arguments as
2978 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2979 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2980 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2981 // In practice, however, the # of lock sites is bounded and is usually small.
2982 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2983 // if the processor uses simple bimodal branch predictors keyed by EIP
2984 // Since the helper routines would be called from multiple synchronization
2985 // sites.
2986 //
2987 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2988 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2989 // to those specialized methods. That'd give us a mostly platform-independent
2990 // implementation that the JITs could optimize and inline at their pleasure.
2991 // Done correctly, the only time we'd need to cross to native could would be
2992 // to park() or unpark() threads. We'd also need a few more unsafe operators
2993 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2994 // (b) explicit barriers or fence operations.
2995 //
2996 // TODO:
2997 //
2998 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2999 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3000 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3001 // the lock operators would typically be faster than reifying Self.
3002 //
3003 // * Ideally I'd define the primitives as:
3004 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3005 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3006 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3007 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3008 // Furthermore the register assignments are overconstrained, possibly resulting in
3009 // sub-optimal code near the synchronization site.
3010 //
3011 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3012 // Alternately, use a better sp-proximity test.
3013 //
3014 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3015 // Either one is sufficient to uniquely identify a thread.
3016 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3017 //
3018 // * Intrinsify notify() and notifyAll() for the common cases where the
3019 // object is locked by the calling thread but the waitlist is empty.
3020 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3021 //
3022 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3023 // But beware of excessive branch density on AMD Opterons.
3024 //
3025 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3026 // or failure of the fast-path. If the fast-path fails then we pass
3027 // control to the slow-path, typically in C. In Fast_Lock and
3028 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3029 // will emit a conditional branch immediately after the node.
3030 // So we have branches to branches and lots of ICC.ZF games.
3031 // Instead, it might be better to have C2 pass a "FailureLabel"
3032 // into Fast_Lock and Fast_Unlock. In the case of success, control
3033 // will drop through the node. ICC.ZF is undefined at exit.
3034 // In the case of failure, the node will branch directly to the
3035 // FailureLabel
3036
3037
3038 // obj: object to lock
3039 // box: on-stack box address (displaced header location) - KILLED
3040 // rax,: tmp -- KILLED
3041 // scr: tmp -- KILLED
3042 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3043
3044 Register objReg = as_Register($obj$$reg);
3045 Register boxReg = as_Register($box$$reg);
3046 Register tmpReg = as_Register($tmp$$reg);
3047 Register scrReg = as_Register($scr$$reg);
3048
3049 // Ensure the register assignents are disjoint
3050 guarantee (objReg != boxReg, "") ;
3051 guarantee (objReg != tmpReg, "") ;
3052 guarantee (objReg != scrReg, "") ;
3053 guarantee (boxReg != tmpReg, "") ;
3054 guarantee (boxReg != scrReg, "") ;
3055 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3056
3057 MacroAssembler masm(&cbuf);
3058
3059 if (_counters != NULL) {
3060 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3061 }
3062 if (EmitSync & 1) {
3063 // set box->dhw = unused_mark (3)
3064 // Force all sync thru slow-path: slow_enter() and slow_exit()
3065 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3066 masm.cmpptr (rsp, (int32_t)0) ;
3067 } else
3068 if (EmitSync & 2) {
3069 Label DONE_LABEL ;
3070 if (UseBiasedLocking) {
3071 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3072 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3073 }
3074
3075 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3076 masm.orptr (tmpReg, 0x1);
3077 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3078 if (os::is_MP()) { masm.lock(); }
3079 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3080 masm.jcc(Assembler::equal, DONE_LABEL);
3081 // Recursive locking
3082 masm.subptr(tmpReg, rsp);
3083 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3084 masm.movptr(Address(boxReg, 0), tmpReg);
3085 masm.bind(DONE_LABEL) ;
3086 } else {
3087 // Possible cases that we'll encounter in fast_lock
3088 // ------------------------------------------------
3089 // * Inflated
3090 // -- unlocked
3091 // -- Locked
3092 // = by self
3093 // = by other
3094 // * biased
3095 // -- by Self
3096 // -- by other
3097 // * neutral
3098 // * stack-locked
3099 // -- by self
3100 // = sp-proximity test hits
3101 // = sp-proximity test generates false-negative
3102 // -- by other
3103 //
3104
3105 Label IsInflated, DONE_LABEL, PopDone ;
3106
3107 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3108 // order to reduce the number of conditional branches in the most common cases.
3109 // Beware -- there's a subtle invariant that fetch of the markword
3110 // at [FETCH], below, will never observe a biased encoding (*101b).
3111 // If this invariant is not held we risk exclusion (safety) failure.
3112 if (UseBiasedLocking && !UseOptoBiasInlining) {
3113 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3114 }
3115
3116 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3117 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3118 masm.jccb (Assembler::notZero, IsInflated) ;
3119
3120 // Attempt stack-locking ...
3121 masm.orptr (tmpReg, 0x1);
3122 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3123 if (os::is_MP()) { masm.lock(); }
3124 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3125 if (_counters != NULL) {
3126 masm.cond_inc32(Assembler::equal,
3127 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3128 }
3129 masm.jccb (Assembler::equal, DONE_LABEL);
3130
3131 // Recursive locking
3132 masm.subptr(tmpReg, rsp);
3133 masm.andptr(tmpReg, 0xFFFFF003 );
3134 masm.movptr(Address(boxReg, 0), tmpReg);
3135 if (_counters != NULL) {
3136 masm.cond_inc32(Assembler::equal,
3137 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3138 }
3139 masm.jmp (DONE_LABEL) ;
3140
3141 masm.bind (IsInflated) ;
3142
3143 // The object is inflated.
3144 //
3145 // TODO-FIXME: eliminate the ugly use of manifest constants:
3146 // Use markOopDesc::monitor_value instead of "2".
3147 // use markOop::unused_mark() instead of "3".
3148 // The tmpReg value is an objectMonitor reference ORed with
3149 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3150 // objectmonitor pointer by masking off the "2" bit or we can just
3151 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3152 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3153 //
3154 // I use the latter as it avoids AGI stalls.
3155 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3156 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3157 //
3158 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3159
3160 // boxReg refers to the on-stack BasicLock in the current frame.
3161 // We'd like to write:
3162 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3163 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3164 // additional latency as we have another ST in the store buffer that must drain.
3165
3166 if (EmitSync & 8192) {
3167 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3168 masm.get_thread (scrReg) ;
3169 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3170 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3171 if (os::is_MP()) { masm.lock(); }
3172 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3173 } else
3174 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3175 masm.movptr(scrReg, boxReg) ;
3176 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3177
3178 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3179 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3180 // prefetchw [eax + Offset(_owner)-2]
3181 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3182 }
3183
3184 if ((EmitSync & 64) == 0) {
3185 // Optimistic form: consider XORL tmpReg,tmpReg
3186 masm.movptr(tmpReg, NULL_WORD) ;
3187 } else {
3188 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3189 // Test-And-CAS instead of CAS
3190 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3191 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3192 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3193 }
3194
3195 // Appears unlocked - try to swing _owner from null to non-null.
3196 // Ideally, I'd manifest "Self" with get_thread and then attempt
3197 // to CAS the register containing Self into m->Owner.
3198 // But we don't have enough registers, so instead we can either try to CAS
3199 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3200 // we later store "Self" into m->Owner. Transiently storing a stack address
3201 // (rsp or the address of the box) into m->owner is harmless.
3202 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3203 if (os::is_MP()) { masm.lock(); }
3204 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3205 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3206 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3207 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3208 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3209 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3210
3211 // If the CAS fails we can either retry or pass control to the slow-path.
3212 // We use the latter tactic.
3213 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3214 // If the CAS was successful ...
3215 // Self has acquired the lock
3216 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3217 // Intentional fall-through into DONE_LABEL ...
3218 } else {
3219 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3220 masm.movptr(boxReg, tmpReg) ;
3221
3222 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3223 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3224 // prefetchw [eax + Offset(_owner)-2]
3225 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3226 }
3227
3228 if ((EmitSync & 64) == 0) {
3229 // Optimistic form
3230 masm.xorptr (tmpReg, tmpReg) ;
3231 } else {
3232 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3233 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3234 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3235 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3236 }
3237
3238 // Appears unlocked - try to swing _owner from null to non-null.
3239 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3240 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3241 masm.get_thread (scrReg) ;
3242 if (os::is_MP()) { masm.lock(); }
3243 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3244
3245 // If the CAS fails we can either retry or pass control to the slow-path.
3246 // We use the latter tactic.
3247 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3248 // If the CAS was successful ...
3249 // Self has acquired the lock
3250 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3251 // Intentional fall-through into DONE_LABEL ...
3252 }
3253
3254 // DONE_LABEL is a hot target - we'd really like to place it at the
3255 // start of cache line by padding with NOPs.
3256 // See the AMD and Intel software optimization manuals for the
3257 // most efficient "long" NOP encodings.
3258 // Unfortunately none of our alignment mechanisms suffice.
3259 masm.bind(DONE_LABEL);
3260
3261 // Avoid branch-to-branch on AMD processors
3262 // This appears to be superstition.
3263 if (EmitSync & 32) masm.nop() ;
3264
3265
3266 // At DONE_LABEL the icc ZFlag is set as follows ...
3267 // Fast_Unlock uses the same protocol.
3268 // ZFlag == 1 -> Success
3269 // ZFlag == 0 -> Failure - force control through the slow-path
3270 }
3271 %}
3272
3273 // obj: object to unlock
3274 // box: box address (displaced header location), killed. Must be EAX.
3275 // rbx,: killed tmp; cannot be obj nor box.
3276 //
3277 // Some commentary on balanced locking:
3278 //
3279 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3280 // Methods that don't have provably balanced locking are forced to run in the
3281 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3282 // The interpreter provides two properties:
3283 // I1: At return-time the interpreter automatically and quietly unlocks any
3284 // objects acquired the current activation (frame). Recall that the
3285 // interpreter maintains an on-stack list of locks currently held by
3286 // a frame.
3287 // I2: If a method attempts to unlock an object that is not held by the
3288 // the frame the interpreter throws IMSX.
3289 //
3290 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3291 // B() doesn't have provably balanced locking so it runs in the interpreter.
3292 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3293 // is still locked by A().
3294 //
3295 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3296 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3297 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3298 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3299
3300 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3301
3302 Register objReg = as_Register($obj$$reg);
3303 Register boxReg = as_Register($box$$reg);
3304 Register tmpReg = as_Register($tmp$$reg);
3305
3306 guarantee (objReg != boxReg, "") ;
3307 guarantee (objReg != tmpReg, "") ;
3308 guarantee (boxReg != tmpReg, "") ;
3309 guarantee (boxReg == as_Register(EAX_enc), "") ;
3310 MacroAssembler masm(&cbuf);
3311
3312 if (EmitSync & 4) {
3313 // Disable - inhibit all inlining. Force control through the slow-path
3314 masm.cmpptr (rsp, 0) ;
3315 } else
3316 if (EmitSync & 8) {
3317 Label DONE_LABEL ;
3318 if (UseBiasedLocking) {
3319 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3320 }
3321 // classic stack-locking code ...
3322 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3323 masm.testptr(tmpReg, tmpReg) ;
3324 masm.jcc (Assembler::zero, DONE_LABEL) ;
3325 if (os::is_MP()) { masm.lock(); }
3326 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3327 masm.bind(DONE_LABEL);
3328 } else {
3329 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3330
3331 // Critically, the biased locking test must have precedence over
3332 // and appear before the (box->dhw == 0) recursive stack-lock test.
3333 if (UseBiasedLocking && !UseOptoBiasInlining) {
3334 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3335 }
3336
3337 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3338 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3339 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3340
3341 masm.testptr(tmpReg, 0x02) ; // Inflated?
3342 masm.jccb (Assembler::zero, Stacked) ;
3343
3344 masm.bind (Inflated) ;
3345 // It's inflated.
3346 // Despite our balanced locking property we still check that m->_owner == Self
3347 // as java routines or native JNI code called by this thread might
3348 // have released the lock.
3349 // Refer to the comments in synchronizer.cpp for how we might encode extra
3350 // state in _succ so we can avoid fetching EntryList|cxq.
3351 //
3352 // I'd like to add more cases in fast_lock() and fast_unlock() --
3353 // such as recursive enter and exit -- but we have to be wary of
3354 // I$ bloat, T$ effects and BP$ effects.
3355 //
3356 // If there's no contention try a 1-0 exit. That is, exit without
3357 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3358 // we detect and recover from the race that the 1-0 exit admits.
3359 //
3360 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3361 // before it STs null into _owner, releasing the lock. Updates
3362 // to data protected by the critical section must be visible before
3363 // we drop the lock (and thus before any other thread could acquire
3364 // the lock and observe the fields protected by the lock).
3365 // IA32's memory-model is SPO, so STs are ordered with respect to
3366 // each other and there's no need for an explicit barrier (fence).
3367 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3368
3369 masm.get_thread (boxReg) ;
3370 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3371 // prefetchw [ebx + Offset(_owner)-2]
3372 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3373 }
3374
3375 // Note that we could employ various encoding schemes to reduce
3376 // the number of loads below (currently 4) to just 2 or 3.
3377 // Refer to the comments in synchronizer.cpp.
3378 // In practice the chain of fetches doesn't seem to impact performance, however.
3379 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3380 // Attempt to reduce branch density - AMD's branch predictor.
3381 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3382 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3383 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3384 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3385 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3386 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3387 masm.jmpb (DONE_LABEL) ;
3388 } else {
3389 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3390 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3391 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3392 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3393 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3394 masm.jccb (Assembler::notZero, CheckSucc) ;
3395 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3396 masm.jmpb (DONE_LABEL) ;
3397 }
3398
3399 // The Following code fragment (EmitSync & 65536) improves the performance of
3400 // contended applications and contended synchronization microbenchmarks.
3401 // Unfortunately the emission of the code - even though not executed - causes regressions
3402 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3403 // with an equal number of never-executed NOPs results in the same regression.
3404 // We leave it off by default.
3405
3406 if ((EmitSync & 65536) != 0) {
3407 Label LSuccess, LGoSlowPath ;
3408
3409 masm.bind (CheckSucc) ;
3410
3411 // Optional pre-test ... it's safe to elide this
3412 if ((EmitSync & 16) == 0) {
3413 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3414 masm.jccb (Assembler::zero, LGoSlowPath) ;
3415 }
3416
3417 // We have a classic Dekker-style idiom:
3418 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3419 // There are a number of ways to implement the barrier:
3420 // (1) lock:andl &m->_owner, 0
3421 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3422 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3423 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3424 // (2) If supported, an explicit MFENCE is appealing.
3425 // In older IA32 processors MFENCE is slower than lock:add or xchg
3426 // particularly if the write-buffer is full as might be the case if
3427 // if stores closely precede the fence or fence-equivalent instruction.
3428 // In more modern implementations MFENCE appears faster, however.
3429 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3430 // The $lines underlying the top-of-stack should be in M-state.
3431 // The locked add instruction is serializing, of course.
3432 // (4) Use xchg, which is serializing
3433 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3434 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3435 // The integer condition codes will tell us if succ was 0.
3436 // Since _succ and _owner should reside in the same $line and
3437 // we just stored into _owner, it's likely that the $line
3438 // remains in M-state for the lock:orl.
3439 //
3440 // We currently use (3), although it's likely that switching to (2)
3441 // is correct for the future.
3442
3443 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3444 if (os::is_MP()) {
3445 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3446 masm.mfence();
3447 } else {
3448 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3449 }
3450 }
3451 // Ratify _succ remains non-null
3452 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3453 masm.jccb (Assembler::notZero, LSuccess) ;
3454
3455 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3456 if (os::is_MP()) { masm.lock(); }
3457 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3458 masm.jccb (Assembler::notEqual, LSuccess) ;
3459 // Since we're low on registers we installed rsp as a placeholding in _owner.
3460 // Now install Self over rsp. This is safe as we're transitioning from
3461 // non-null to non=null
3462 masm.get_thread (boxReg) ;
3463 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3464 // Intentional fall-through into LGoSlowPath ...
3465
3466 masm.bind (LGoSlowPath) ;
3467 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3468 masm.jmpb (DONE_LABEL) ;
3469
3470 masm.bind (LSuccess) ;
3471 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3472 masm.jmpb (DONE_LABEL) ;
3473 }
3474
3475 masm.bind (Stacked) ;
3476 // It's not inflated and it's not recursively stack-locked and it's not biased.
3477 // It must be stack-locked.
3478 // Try to reset the header to displaced header.
3479 // The "box" value on the stack is stable, so we can reload
3480 // and be assured we observe the same value as above.
3481 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3482 if (os::is_MP()) { masm.lock(); }
3483 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3484 // Intention fall-thru into DONE_LABEL
3485
3486
3487 // DONE_LABEL is a hot target - we'd really like to place it at the
3488 // start of cache line by padding with NOPs.
3489 // See the AMD and Intel software optimization manuals for the
3490 // most efficient "long" NOP encodings.
3491 // Unfortunately none of our alignment mechanisms suffice.
3492 if ((EmitSync & 65536) == 0) {
3493 masm.bind (CheckSucc) ;
3494 }
3495 masm.bind(DONE_LABEL);
3496
3497 // Avoid branch to branch on AMD processors
3498 if (EmitSync & 32768) { masm.nop() ; }
3499 }
3500 %}
3501
3502
3503 enc_class enc_pop_rdx() %{
3504 emit_opcode(cbuf,0x5A);
3505 %}
3506
3507 enc_class enc_rethrow() %{
3508 cbuf.set_insts_mark();
3509 emit_opcode(cbuf, 0xE9); // jmp entry
3510 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3511 runtime_call_Relocation::spec(), RELOC_IMM32 );
3512 %}
3513
3514
3515 // Convert a double to an int. Java semantics require we do complex
3516 // manglelations in the corner cases. So we set the rounding mode to
3517 // 'zero', store the darned double down as an int, and reset the
3518 // rounding mode to 'nearest'. The hardware throws an exception which
3519 // patches up the correct value directly to the stack.
3520 enc_class DPR2I_encoding( regDPR src ) %{
3521 // Flip to round-to-zero mode. We attempted to allow invalid-op
3522 // exceptions here, so that a NAN or other corner-case value will
3523 // thrown an exception (but normal values get converted at full speed).
3524 // However, I2C adapters and other float-stack manglers leave pending
3525 // invalid-op exceptions hanging. We would have to clear them before
3526 // enabling them and that is more expensive than just testing for the
3527 // invalid value Intel stores down in the corner cases.
3528 emit_opcode(cbuf,0xD9); // FLDCW trunc
3529 emit_opcode(cbuf,0x2D);
3530 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3531 // Allocate a word
3532 emit_opcode(cbuf,0x83); // SUB ESP,4
3533 emit_opcode(cbuf,0xEC);
3534 emit_d8(cbuf,0x04);
3535 // Encoding assumes a double has been pushed into FPR0.
3536 // Store down the double as an int, popping the FPU stack
3537 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3538 emit_opcode(cbuf,0x1C);
3539 emit_d8(cbuf,0x24);
3540 // Restore the rounding mode; mask the exception
3541 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3542 emit_opcode(cbuf,0x2D);
3543 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3544 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3545 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3546
3547 // Load the converted int; adjust CPU stack
3548 emit_opcode(cbuf,0x58); // POP EAX
3549 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3550 emit_d32 (cbuf,0x80000000); // 0x80000000
3551 emit_opcode(cbuf,0x75); // JNE around_slow_call
3552 emit_d8 (cbuf,0x07); // Size of slow_call
3553 // Push src onto stack slow-path
3554 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3555 emit_d8 (cbuf,0xC0-1+$src$$reg );
3556 // CALL directly to the runtime
3557 cbuf.set_insts_mark();
3558 emit_opcode(cbuf,0xE8); // Call into runtime
3559 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3560 // Carry on here...
3561 %}
3562
3563 enc_class DPR2L_encoding( regDPR src ) %{
3564 emit_opcode(cbuf,0xD9); // FLDCW trunc
3565 emit_opcode(cbuf,0x2D);
3566 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3567 // Allocate a word
3568 emit_opcode(cbuf,0x83); // SUB ESP,8
3569 emit_opcode(cbuf,0xEC);
3570 emit_d8(cbuf,0x08);
3571 // Encoding assumes a double has been pushed into FPR0.
3572 // Store down the double as a long, popping the FPU stack
3573 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3574 emit_opcode(cbuf,0x3C);
3575 emit_d8(cbuf,0x24);
3576 // Restore the rounding mode; mask the exception
3577 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3578 emit_opcode(cbuf,0x2D);
3579 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3580 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3581 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3582
3583 // Load the converted int; adjust CPU stack
3584 emit_opcode(cbuf,0x58); // POP EAX
3585 emit_opcode(cbuf,0x5A); // POP EDX
3586 emit_opcode(cbuf,0x81); // CMP EDX,imm
3587 emit_d8 (cbuf,0xFA); // rdx
3588 emit_d32 (cbuf,0x80000000); // 0x80000000
3589 emit_opcode(cbuf,0x75); // JNE around_slow_call
3590 emit_d8 (cbuf,0x07+4); // Size of slow_call
3591 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3592 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3593 emit_opcode(cbuf,0x75); // JNE around_slow_call
3594 emit_d8 (cbuf,0x07); // Size of slow_call
3595 // Push src onto stack slow-path
3596 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3597 emit_d8 (cbuf,0xC0-1+$src$$reg );
3598 // CALL directly to the runtime
3599 cbuf.set_insts_mark();
3600 emit_opcode(cbuf,0xE8); // Call into runtime
3601 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3602 // Carry on here...
3603 %}
3604
3605 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3606 // Operand was loaded from memory into fp ST (stack top)
3607 // FMUL ST,$src /* D8 C8+i */
3608 emit_opcode(cbuf, 0xD8);
3609 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3610 %}
3611
3612 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3613 // FADDP ST,src2 /* D8 C0+i */
3614 emit_opcode(cbuf, 0xD8);
3615 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3616 //could use FADDP src2,fpST /* DE C0+i */
3617 %}
3618
3619 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3620 // FADDP src2,ST /* DE C0+i */
3621 emit_opcode(cbuf, 0xDE);
3622 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3623 %}
3624
3625 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3626 // Operand has been loaded into fp ST (stack top)
3627 // FSUB ST,$src1
3628 emit_opcode(cbuf, 0xD8);
3629 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3630
3631 // FDIV
3632 emit_opcode(cbuf, 0xD8);
3633 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3634 %}
3635
3636 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3637 // Operand was loaded from memory into fp ST (stack top)
3638 // FADD ST,$src /* D8 C0+i */
3639 emit_opcode(cbuf, 0xD8);
3640 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3641
3642 // FMUL ST,src2 /* D8 C*+i */
3643 emit_opcode(cbuf, 0xD8);
3644 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3645 %}
3646
3647
3648 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3649 // Operand was loaded from memory into fp ST (stack top)
3650 // FADD ST,$src /* D8 C0+i */
3651 emit_opcode(cbuf, 0xD8);
3652 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3653
3654 // FMULP src2,ST /* DE C8+i */
3655 emit_opcode(cbuf, 0xDE);
3656 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3657 %}
3658
3659 // Atomically load the volatile long
3660 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3661 emit_opcode(cbuf,0xDF);
3662 int rm_byte_opcode = 0x05;
3663 int base = $mem$$base;
3664 int index = $mem$$index;
3665 int scale = $mem$$scale;
3666 int displace = $mem$$disp;
3667 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3668 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3669 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3670 %}
3671
3672 // Volatile Store Long. Must be atomic, so move it into
3673 // the FP TOS and then do a 64-bit FIST. Has to probe the
3674 // target address before the store (for null-ptr checks)
3675 // so the memory operand is used twice in the encoding.
3676 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3677 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3678 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3679 emit_opcode(cbuf,0xDF);
3680 int rm_byte_opcode = 0x07;
3681 int base = $mem$$base;
3682 int index = $mem$$index;
3683 int scale = $mem$$scale;
3684 int displace = $mem$$disp;
3685 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3686 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3687 %}
3688
3689 // Safepoint Poll. This polls the safepoint page, and causes an
3690 // exception if it is not readable. Unfortunately, it kills the condition code
3691 // in the process
3692 // We current use TESTL [spp],EDI
3693 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3694
3695 enc_class Safepoint_Poll() %{
3696 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3697 emit_opcode(cbuf,0x85);
3698 emit_rm (cbuf, 0x0, 0x7, 0x5);
3699 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3700 %}
3701 %}
3702
3703
3704 //----------FRAME--------------------------------------------------------------
3705 // Definition of frame structure and management information.
3706 //
3707 // S T A C K L A Y O U T Allocators stack-slot number
3708 // | (to get allocators register number
3709 // G Owned by | | v add OptoReg::stack0())
3710 // r CALLER | |
3711 // o | +--------+ pad to even-align allocators stack-slot
3712 // w V | pad0 | numbers; owned by CALLER
3713 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3714 // h ^ | in | 5
3715 // | | args | 4 Holes in incoming args owned by SELF
3716 // | | | | 3
3717 // | | +--------+
3718 // V | | old out| Empty on Intel, window on Sparc
3719 // | old |preserve| Must be even aligned.
3720 // | SP-+--------+----> Matcher::_old_SP, even aligned
3721 // | | in | 3 area for Intel ret address
3722 // Owned by |preserve| Empty on Sparc.
3723 // SELF +--------+
3724 // | | pad2 | 2 pad to align old SP
3725 // | +--------+ 1
3726 // | | locks | 0
3727 // | +--------+----> OptoReg::stack0(), even aligned
3728 // | | pad1 | 11 pad to align new SP
3729 // | +--------+
3730 // | | | 10
3731 // | | spills | 9 spills
3732 // V | | 8 (pad0 slot for callee)
3733 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3734 // ^ | out | 7
3735 // | | args | 6 Holes in outgoing args owned by CALLEE
3736 // Owned by +--------+
3737 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3738 // | new |preserve| Must be even-aligned.
3739 // | SP-+--------+----> Matcher::_new_SP, even aligned
3740 // | | |
3741 //
3742 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3743 // known from SELF's arguments and the Java calling convention.
3744 // Region 6-7 is determined per call site.
3745 // Note 2: If the calling convention leaves holes in the incoming argument
3746 // area, those holes are owned by SELF. Holes in the outgoing area
3747 // are owned by the CALLEE. Holes should not be nessecary in the
3748 // incoming area, as the Java calling convention is completely under
3749 // the control of the AD file. Doubles can be sorted and packed to
3750 // avoid holes. Holes in the outgoing arguments may be nessecary for
3751 // varargs C calling conventions.
3752 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3753 // even aligned with pad0 as needed.
3754 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3755 // region 6-11 is even aligned; it may be padded out more so that
3756 // the region from SP to FP meets the minimum stack alignment.
3757
3758 frame %{
3759 // What direction does stack grow in (assumed to be same for C & Java)
3760 stack_direction(TOWARDS_LOW);
3761
3762 // These three registers define part of the calling convention
3763 // between compiled code and the interpreter.
3764 inline_cache_reg(EAX); // Inline Cache Register
3765 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3766
3767 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3768 cisc_spilling_operand_name(indOffset32);
3769
3770 // Number of stack slots consumed by locking an object
3771 sync_stack_slots(1);
3772
3773 // Compiled code's Frame Pointer
3774 frame_pointer(ESP);
3775 // Interpreter stores its frame pointer in a register which is
3776 // stored to the stack by I2CAdaptors.
3777 // I2CAdaptors convert from interpreted java to compiled java.
3778 interpreter_frame_pointer(EBP);
3779
3780 // Stack alignment requirement
3781 // Alignment size in bytes (128-bit -> 16 bytes)
3782 stack_alignment(StackAlignmentInBytes);
3783
3784 // Number of stack slots between incoming argument block and the start of
3785 // a new frame. The PROLOG must add this many slots to the stack. The
3786 // EPILOG must remove this many slots. Intel needs one slot for
3787 // return address and one for rbp, (must save rbp)
3788 in_preserve_stack_slots(2+VerifyStackAtCalls);
3789
3790 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3791 // for calls to C. Supports the var-args backing area for register parms.
3792 varargs_C_out_slots_killed(0);
3793
3794 // The after-PROLOG location of the return address. Location of
3795 // return address specifies a type (REG or STACK) and a number
3796 // representing the register number (i.e. - use a register name) or
3797 // stack slot.
3798 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3799 // Otherwise, it is above the locks and verification slot and alignment word
3800 return_addr(STACK - 1 +
3801 round_to((Compile::current()->in_preserve_stack_slots() +
3802 Compile::current()->fixed_slots()),
3803 stack_alignment_in_slots()));
3804
3805 // Body of function which returns an integer array locating
3806 // arguments either in registers or in stack slots. Passed an array
3807 // of ideal registers called "sig" and a "length" count. Stack-slot
3808 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3809 // arguments for a CALLEE. Incoming stack arguments are
3810 // automatically biased by the preserve_stack_slots field above.
3811 calling_convention %{
3812 // No difference between ingoing/outgoing just pass false
3813 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3814 %}
3815
3816
3817 // Body of function which returns an integer array locating
3818 // arguments either in registers or in stack slots. Passed an array
3819 // of ideal registers called "sig" and a "length" count. Stack-slot
3820 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3821 // arguments for a CALLEE. Incoming stack arguments are
3822 // automatically biased by the preserve_stack_slots field above.
3823 c_calling_convention %{
3824 // This is obviously always outgoing
3825 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3826 %}
3827
3828 // Location of C & interpreter return values
3829 c_return_value %{
3830 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3831 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3832 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3833
3834 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3835 // that C functions return float and double results in XMM0.
3836 if( ideal_reg == Op_RegD && UseSSE>=2 )
3837 return OptoRegPair(XMM0b_num,XMM0_num);
3838 if( ideal_reg == Op_RegF && UseSSE>=2 )
3839 return OptoRegPair(OptoReg::Bad,XMM0_num);
3840
3841 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3842 %}
3843
3844 // Location of return values
3845 return_value %{
3846 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3847 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3848 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3849 if( ideal_reg == Op_RegD && UseSSE>=2 )
3850 return OptoRegPair(XMM0b_num,XMM0_num);
3851 if( ideal_reg == Op_RegF && UseSSE>=1 )
3852 return OptoRegPair(OptoReg::Bad,XMM0_num);
3853 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3854 %}
3855
3856 %}
3857
3858 //----------ATTRIBUTES---------------------------------------------------------
3859 //----------Operand Attributes-------------------------------------------------
3860 op_attrib op_cost(0); // Required cost attribute
3861
3862 //----------Instruction Attributes---------------------------------------------
3863 ins_attrib ins_cost(100); // Required cost attribute
3864 ins_attrib ins_size(8); // Required size attribute (in bits)
3865 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3866 // non-matching short branch variant of some
3867 // long branch?
3868 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3869 // specifies the alignment that some part of the instruction (not
3870 // necessarily the start) requires. If > 1, a compute_padding()
3871 // function must be provided for the instruction
3872
3873 //----------OPERANDS-----------------------------------------------------------
3874 // Operand definitions must precede instruction definitions for correct parsing
3875 // in the ADLC because operands constitute user defined types which are used in
3876 // instruction definitions.
3877
3878 //----------Simple Operands----------------------------------------------------
3879 // Immediate Operands
3880 // Integer Immediate
3881 operand immI() %{
3882 match(ConI);
3883
3884 op_cost(10);
3885 format %{ %}
3886 interface(CONST_INTER);
3887 %}
3888
3889 // Constant for test vs zero
3890 operand immI0() %{
3891 predicate(n->get_int() == 0);
3892 match(ConI);
3893
3894 op_cost(0);
3895 format %{ %}
3896 interface(CONST_INTER);
3897 %}
3898
3899 // Constant for increment
3900 operand immI1() %{
3901 predicate(n->get_int() == 1);
3902 match(ConI);
3903
3904 op_cost(0);
3905 format %{ %}
3906 interface(CONST_INTER);
3907 %}
3908
3909 // Constant for decrement
3910 operand immI_M1() %{
3911 predicate(n->get_int() == -1);
3912 match(ConI);
3913
3914 op_cost(0);
3915 format %{ %}
3916 interface(CONST_INTER);
3917 %}
3918
3919 // Valid scale values for addressing modes
3920 operand immI2() %{
3921 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3922 match(ConI);
3923
3924 format %{ %}
3925 interface(CONST_INTER);
3926 %}
3927
3928 operand immI8() %{
3929 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3930 match(ConI);
3931
3932 op_cost(5);
3933 format %{ %}
3934 interface(CONST_INTER);
3935 %}
3936
3937 operand immI16() %{
3938 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3939 match(ConI);
3940
3941 op_cost(10);
3942 format %{ %}
3943 interface(CONST_INTER);
3944 %}
3945
3946 // Constant for long shifts
3947 operand immI_32() %{
3948 predicate( n->get_int() == 32 );
3949 match(ConI);
3950
3951 op_cost(0);
3952 format %{ %}
3953 interface(CONST_INTER);
3954 %}
3955
3956 operand immI_1_31() %{
3957 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3958 match(ConI);
3959
3960 op_cost(0);
3961 format %{ %}
3962 interface(CONST_INTER);
3963 %}
3964
3965 operand immI_32_63() %{
3966 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3967 match(ConI);
3968 op_cost(0);
3969
3970 format %{ %}
3971 interface(CONST_INTER);
3972 %}
3973
3974 operand immI_1() %{
3975 predicate( n->get_int() == 1 );
3976 match(ConI);
3977
3978 op_cost(0);
3979 format %{ %}
3980 interface(CONST_INTER);
3981 %}
3982
3983 operand immI_2() %{
3984 predicate( n->get_int() == 2 );
3985 match(ConI);
3986
3987 op_cost(0);
3988 format %{ %}
3989 interface(CONST_INTER);
3990 %}
3991
3992 operand immI_3() %{
3993 predicate( n->get_int() == 3 );
3994 match(ConI);
3995
3996 op_cost(0);
3997 format %{ %}
3998 interface(CONST_INTER);
3999 %}
4000
4001 // Pointer Immediate
4002 operand immP() %{
4003 match(ConP);
4004
4005 op_cost(10);
4006 format %{ %}
4007 interface(CONST_INTER);
4008 %}
4009
4010 // NULL Pointer Immediate
4011 operand immP0() %{
4012 predicate( n->get_ptr() == 0 );
4013 match(ConP);
4014 op_cost(0);
4015
4016 format %{ %}
4017 interface(CONST_INTER);
4018 %}
4019
4020 // Long Immediate
4021 operand immL() %{
4022 match(ConL);
4023
4024 op_cost(20);
4025 format %{ %}
4026 interface(CONST_INTER);
4027 %}
4028
4029 // Long Immediate zero
4030 operand immL0() %{
4031 predicate( n->get_long() == 0L );
4032 match(ConL);
4033 op_cost(0);
4034
4035 format %{ %}
4036 interface(CONST_INTER);
4037 %}
4038
4039 // Long Immediate zero
4040 operand immL_M1() %{
4041 predicate( n->get_long() == -1L );
4042 match(ConL);
4043 op_cost(0);
4044
4045 format %{ %}
4046 interface(CONST_INTER);
4047 %}
4048
4049 // Long immediate from 0 to 127.
4050 // Used for a shorter form of long mul by 10.
4051 operand immL_127() %{
4052 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4053 match(ConL);
4054 op_cost(0);
4055
4056 format %{ %}
4057 interface(CONST_INTER);
4058 %}
4059
4060 // Long Immediate: low 32-bit mask
4061 operand immL_32bits() %{
4062 predicate(n->get_long() == 0xFFFFFFFFL);
4063 match(ConL);
4064 op_cost(0);
4065
4066 format %{ %}
4067 interface(CONST_INTER);
4068 %}
4069
4070 // Long Immediate: low 32-bit mask
4071 operand immL32() %{
4072 predicate(n->get_long() == (int)(n->get_long()));
4073 match(ConL);
4074 op_cost(20);
4075
4076 format %{ %}
4077 interface(CONST_INTER);
4078 %}
4079
4080 //Double Immediate zero
4081 operand immDPR0() %{
4082 // Do additional (and counter-intuitive) test against NaN to work around VC++
4083 // bug that generates code such that NaNs compare equal to 0.0
4084 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4085 match(ConD);
4086
4087 op_cost(5);
4088 format %{ %}
4089 interface(CONST_INTER);
4090 %}
4091
4092 // Double Immediate one
4093 operand immDPR1() %{
4094 predicate( UseSSE<=1 && n->getd() == 1.0 );
4095 match(ConD);
4096
4097 op_cost(5);
4098 format %{ %}
4099 interface(CONST_INTER);
4100 %}
4101
4102 // Double Immediate
4103 operand immDPR() %{
4104 predicate(UseSSE<=1);
4105 match(ConD);
4106
4107 op_cost(5);
4108 format %{ %}
4109 interface(CONST_INTER);
4110 %}
4111
4112 operand immD() %{
4113 predicate(UseSSE>=2);
4114 match(ConD);
4115
4116 op_cost(5);
4117 format %{ %}
4118 interface(CONST_INTER);
4119 %}
4120
4121 // Double Immediate zero
4122 operand immD0() %{
4123 // Do additional (and counter-intuitive) test against NaN to work around VC++
4124 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4125 // compare equal to -0.0.
4126 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4127 match(ConD);
4128
4129 format %{ %}
4130 interface(CONST_INTER);
4131 %}
4132
4133 // Float Immediate zero
4134 operand immFPR0() %{
4135 predicate(UseSSE == 0 && n->getf() == 0.0F);
4136 match(ConF);
4137
4138 op_cost(5);
4139 format %{ %}
4140 interface(CONST_INTER);
4141 %}
4142
4143 // Float Immediate one
4144 operand immFPR1() %{
4145 predicate(UseSSE == 0 && n->getf() == 1.0F);
4146 match(ConF);
4147
4148 op_cost(5);
4149 format %{ %}
4150 interface(CONST_INTER);
4151 %}
4152
4153 // Float Immediate
4154 operand immFPR() %{
4155 predicate( UseSSE == 0 );
4156 match(ConF);
4157
4158 op_cost(5);
4159 format %{ %}
4160 interface(CONST_INTER);
4161 %}
4162
4163 // Float Immediate
4164 operand immF() %{
4165 predicate(UseSSE >= 1);
4166 match(ConF);
4167
4168 op_cost(5);
4169 format %{ %}
4170 interface(CONST_INTER);
4171 %}
4172
4173 // Float Immediate zero. Zero and not -0.0
4174 operand immF0() %{
4175 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4176 match(ConF);
4177
4178 op_cost(5);
4179 format %{ %}
4180 interface(CONST_INTER);
4181 %}
4182
4183 // Immediates for special shifts (sign extend)
4184
4185 // Constants for increment
4186 operand immI_16() %{
4187 predicate( n->get_int() == 16 );
4188 match(ConI);
4189
4190 format %{ %}
4191 interface(CONST_INTER);
4192 %}
4193
4194 operand immI_24() %{
4195 predicate( n->get_int() == 24 );
4196 match(ConI);
4197
4198 format %{ %}
4199 interface(CONST_INTER);
4200 %}
4201
4202 // Constant for byte-wide masking
4203 operand immI_255() %{
4204 predicate( n->get_int() == 255 );
4205 match(ConI);
4206
4207 format %{ %}
4208 interface(CONST_INTER);
4209 %}
4210
4211 // Constant for short-wide masking
4212 operand immI_65535() %{
4213 predicate(n->get_int() == 65535);
4214 match(ConI);
4215
4216 format %{ %}
4217 interface(CONST_INTER);
4218 %}
4219
4220 // Register Operands
4221 // Integer Register
4222 operand rRegI() %{
4223 constraint(ALLOC_IN_RC(int_reg));
4224 match(RegI);
4225 match(xRegI);
4226 match(eAXRegI);
4227 match(eBXRegI);
4228 match(eCXRegI);
4229 match(eDXRegI);
4230 match(eDIRegI);
4231 match(eSIRegI);
4232
4233 format %{ %}
4234 interface(REG_INTER);
4235 %}
4236
4237 // Subset of Integer Register
4238 operand xRegI(rRegI reg) %{
4239 constraint(ALLOC_IN_RC(int_x_reg));
4240 match(reg);
4241 match(eAXRegI);
4242 match(eBXRegI);
4243 match(eCXRegI);
4244 match(eDXRegI);
4245
4246 format %{ %}
4247 interface(REG_INTER);
4248 %}
4249
4250 // Special Registers
4251 operand eAXRegI(xRegI reg) %{
4252 constraint(ALLOC_IN_RC(eax_reg));
4253 match(reg);
4254 match(rRegI);
4255
4256 format %{ "EAX" %}
4257 interface(REG_INTER);
4258 %}
4259
4260 // Special Registers
4261 operand eBXRegI(xRegI reg) %{
4262 constraint(ALLOC_IN_RC(ebx_reg));
4263 match(reg);
4264 match(rRegI);
4265
4266 format %{ "EBX" %}
4267 interface(REG_INTER);
4268 %}
4269
4270 operand eCXRegI(xRegI reg) %{
4271 constraint(ALLOC_IN_RC(ecx_reg));
4272 match(reg);
4273 match(rRegI);
4274
4275 format %{ "ECX" %}
4276 interface(REG_INTER);
4277 %}
4278
4279 operand eDXRegI(xRegI reg) %{
4280 constraint(ALLOC_IN_RC(edx_reg));
4281 match(reg);
4282 match(rRegI);
4283
4284 format %{ "EDX" %}
4285 interface(REG_INTER);
4286 %}
4287
4288 operand eDIRegI(xRegI reg) %{
4289 constraint(ALLOC_IN_RC(edi_reg));
4290 match(reg);
4291 match(rRegI);
4292
4293 format %{ "EDI" %}
4294 interface(REG_INTER);
4295 %}
4296
4297 operand naxRegI() %{
4298 constraint(ALLOC_IN_RC(nax_reg));
4299 match(RegI);
4300 match(eCXRegI);
4301 match(eDXRegI);
4302 match(eSIRegI);
4303 match(eDIRegI);
4304
4305 format %{ %}
4306 interface(REG_INTER);
4307 %}
4308
4309 operand nadxRegI() %{
4310 constraint(ALLOC_IN_RC(nadx_reg));
4311 match(RegI);
4312 match(eBXRegI);
4313 match(eCXRegI);
4314 match(eSIRegI);
4315 match(eDIRegI);
4316
4317 format %{ %}
4318 interface(REG_INTER);
4319 %}
4320
4321 operand ncxRegI() %{
4322 constraint(ALLOC_IN_RC(ncx_reg));
4323 match(RegI);
4324 match(eAXRegI);
4325 match(eDXRegI);
4326 match(eSIRegI);
4327 match(eDIRegI);
4328
4329 format %{ %}
4330 interface(REG_INTER);
4331 %}
4332
4333 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4334 // //
4335 operand eSIRegI(xRegI reg) %{
4336 constraint(ALLOC_IN_RC(esi_reg));
4337 match(reg);
4338 match(rRegI);
4339
4340 format %{ "ESI" %}
4341 interface(REG_INTER);
4342 %}
4343
4344 // Pointer Register
4345 operand anyRegP() %{
4346 constraint(ALLOC_IN_RC(any_reg));
4347 match(RegP);
4348 match(eAXRegP);
4349 match(eBXRegP);
4350 match(eCXRegP);
4351 match(eDIRegP);
4352 match(eRegP);
4353
4354 format %{ %}
4355 interface(REG_INTER);
4356 %}
4357
4358 operand eRegP() %{
4359 constraint(ALLOC_IN_RC(int_reg));
4360 match(RegP);
4361 match(eAXRegP);
4362 match(eBXRegP);
4363 match(eCXRegP);
4364 match(eDIRegP);
4365
4366 format %{ %}
4367 interface(REG_INTER);
4368 %}
4369
4370 // On windows95, EBP is not safe to use for implicit null tests.
4371 operand eRegP_no_EBP() %{
4372 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4373 match(RegP);
4374 match(eAXRegP);
4375 match(eBXRegP);
4376 match(eCXRegP);
4377 match(eDIRegP);
4378
4379 op_cost(100);
4380 format %{ %}
4381 interface(REG_INTER);
4382 %}
4383
4384 operand naxRegP() %{
4385 constraint(ALLOC_IN_RC(nax_reg));
4386 match(RegP);
4387 match(eBXRegP);
4388 match(eDXRegP);
4389 match(eCXRegP);
4390 match(eSIRegP);
4391 match(eDIRegP);
4392
4393 format %{ %}
4394 interface(REG_INTER);
4395 %}
4396
4397 operand nabxRegP() %{
4398 constraint(ALLOC_IN_RC(nabx_reg));
4399 match(RegP);
4400 match(eCXRegP);
4401 match(eDXRegP);
4402 match(eSIRegP);
4403 match(eDIRegP);
4404
4405 format %{ %}
4406 interface(REG_INTER);
4407 %}
4408
4409 operand pRegP() %{
4410 constraint(ALLOC_IN_RC(p_reg));
4411 match(RegP);
4412 match(eBXRegP);
4413 match(eDXRegP);
4414 match(eSIRegP);
4415 match(eDIRegP);
4416
4417 format %{ %}
4418 interface(REG_INTER);
4419 %}
4420
4421 // Special Registers
4422 // Return a pointer value
4423 operand eAXRegP(eRegP reg) %{
4424 constraint(ALLOC_IN_RC(eax_reg));
4425 match(reg);
4426 format %{ "EAX" %}
4427 interface(REG_INTER);
4428 %}
4429
4430 // Used in AtomicAdd
4431 operand eBXRegP(eRegP reg) %{
4432 constraint(ALLOC_IN_RC(ebx_reg));
4433 match(reg);
4434 format %{ "EBX" %}
4435 interface(REG_INTER);
4436 %}
4437
4438 // Tail-call (interprocedural jump) to interpreter
4439 operand eCXRegP(eRegP reg) %{
4440 constraint(ALLOC_IN_RC(ecx_reg));
4441 match(reg);
4442 format %{ "ECX" %}
4443 interface(REG_INTER);
4444 %}
4445
4446 operand eSIRegP(eRegP reg) %{
4447 constraint(ALLOC_IN_RC(esi_reg));
4448 match(reg);
4449 format %{ "ESI" %}
4450 interface(REG_INTER);
4451 %}
4452
4453 // Used in rep stosw
4454 operand eDIRegP(eRegP reg) %{
4455 constraint(ALLOC_IN_RC(edi_reg));
4456 match(reg);
4457 format %{ "EDI" %}
4458 interface(REG_INTER);
4459 %}
4460
4461 operand eBPRegP() %{
4462 constraint(ALLOC_IN_RC(ebp_reg));
4463 match(RegP);
4464 format %{ "EBP" %}
4465 interface(REG_INTER);
4466 %}
4467
4468 operand eRegL() %{
4469 constraint(ALLOC_IN_RC(long_reg));
4470 match(RegL);
4471 match(eADXRegL);
4472
4473 format %{ %}
4474 interface(REG_INTER);
4475 %}
4476
4477 operand eADXRegL( eRegL reg ) %{
4478 constraint(ALLOC_IN_RC(eadx_reg));
4479 match(reg);
4480
4481 format %{ "EDX:EAX" %}
4482 interface(REG_INTER);
4483 %}
4484
4485 operand eBCXRegL( eRegL reg ) %{
4486 constraint(ALLOC_IN_RC(ebcx_reg));
4487 match(reg);
4488
4489 format %{ "EBX:ECX" %}
4490 interface(REG_INTER);
4491 %}
4492
4493 // Special case for integer high multiply
4494 operand eADXRegL_low_only() %{
4495 constraint(ALLOC_IN_RC(eadx_reg));
4496 match(RegL);
4497
4498 format %{ "EAX" %}
4499 interface(REG_INTER);
4500 %}
4501
4502 // Flags register, used as output of compare instructions
4503 operand eFlagsReg() %{
4504 constraint(ALLOC_IN_RC(int_flags));
4505 match(RegFlags);
4506
4507 format %{ "EFLAGS" %}
4508 interface(REG_INTER);
4509 %}
4510
4511 // Flags register, used as output of FLOATING POINT compare instructions
4512 operand eFlagsRegU() %{
4513 constraint(ALLOC_IN_RC(int_flags));
4514 match(RegFlags);
4515
4516 format %{ "EFLAGS_U" %}
4517 interface(REG_INTER);
4518 %}
4519
4520 operand eFlagsRegUCF() %{
4521 constraint(ALLOC_IN_RC(int_flags));
4522 match(RegFlags);
4523 predicate(false);
4524
4525 format %{ "EFLAGS_U_CF" %}
4526 interface(REG_INTER);
4527 %}
4528
4529 // Condition Code Register used by long compare
4530 operand flagsReg_long_LTGE() %{
4531 constraint(ALLOC_IN_RC(int_flags));
4532 match(RegFlags);
4533 format %{ "FLAGS_LTGE" %}
4534 interface(REG_INTER);
4535 %}
4536 operand flagsReg_long_EQNE() %{
4537 constraint(ALLOC_IN_RC(int_flags));
4538 match(RegFlags);
4539 format %{ "FLAGS_EQNE" %}
4540 interface(REG_INTER);
4541 %}
4542 operand flagsReg_long_LEGT() %{
4543 constraint(ALLOC_IN_RC(int_flags));
4544 match(RegFlags);
4545 format %{ "FLAGS_LEGT" %}
4546 interface(REG_INTER);
4547 %}
4548
4549 // Float register operands
4550 operand regDPR() %{
4551 predicate( UseSSE < 2 );
4552 constraint(ALLOC_IN_RC(fp_dbl_reg));
4553 match(RegD);
4554 match(regDPR1);
4555 match(regDPR2);
4556 format %{ %}
4557 interface(REG_INTER);
4558 %}
4559
4560 operand regDPR1(regDPR reg) %{
4561 predicate( UseSSE < 2 );
4562 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4563 match(reg);
4564 format %{ "FPR1" %}
4565 interface(REG_INTER);
4566 %}
4567
4568 operand regDPR2(regDPR reg) %{
4569 predicate( UseSSE < 2 );
4570 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4571 match(reg);
4572 format %{ "FPR2" %}
4573 interface(REG_INTER);
4574 %}
4575
4576 operand regnotDPR1(regDPR reg) %{
4577 predicate( UseSSE < 2 );
4578 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4579 match(reg);
4580 format %{ %}
4581 interface(REG_INTER);
4582 %}
4583
4584 // Float register operands
4585 operand regFPR() %{
4586 predicate( UseSSE < 2 );
4587 constraint(ALLOC_IN_RC(fp_flt_reg));
4588 match(RegF);
4589 match(regFPR1);
4590 format %{ %}
4591 interface(REG_INTER);
4592 %}
4593
4594 // Float register operands
4595 operand regFPR1(regFPR reg) %{
4596 predicate( UseSSE < 2 );
4597 constraint(ALLOC_IN_RC(fp_flt_reg0));
4598 match(reg);
4599 format %{ "FPR1" %}
4600 interface(REG_INTER);
4601 %}
4602
4603 // XMM Float register operands
4604 operand regF() %{
4605 predicate( UseSSE>=1 );
4606 constraint(ALLOC_IN_RC(float_reg));
4607 match(RegF);
4608 format %{ %}
4609 interface(REG_INTER);
4610 %}
4611
4612 // XMM Double register operands
4613 operand regD() %{
4614 predicate( UseSSE>=2 );
4615 constraint(ALLOC_IN_RC(double_reg));
4616 match(RegD);
4617 format %{ %}
4618 interface(REG_INTER);
4619 %}
4620
4621
4622 //----------Memory Operands----------------------------------------------------
4623 // Direct Memory Operand
4624 operand direct(immP addr) %{
4625 match(addr);
4626
4627 format %{ "[$addr]" %}
4628 interface(MEMORY_INTER) %{
4629 base(0xFFFFFFFF);
4630 index(0x4);
4631 scale(0x0);
4632 disp($addr);
4633 %}
4634 %}
4635
4636 // Indirect Memory Operand
4637 operand indirect(eRegP reg) %{
4638 constraint(ALLOC_IN_RC(int_reg));
4639 match(reg);
4640
4641 format %{ "[$reg]" %}
4642 interface(MEMORY_INTER) %{
4643 base($reg);
4644 index(0x4);
4645 scale(0x0);
4646 disp(0x0);
4647 %}
4648 %}
4649
4650 // Indirect Memory Plus Short Offset Operand
4651 operand indOffset8(eRegP reg, immI8 off) %{
4652 match(AddP reg off);
4653
4654 format %{ "[$reg + $off]" %}
4655 interface(MEMORY_INTER) %{
4656 base($reg);
4657 index(0x4);
4658 scale(0x0);
4659 disp($off);
4660 %}
4661 %}
4662
4663 // Indirect Memory Plus Long Offset Operand
4664 operand indOffset32(eRegP reg, immI off) %{
4665 match(AddP reg off);
4666
4667 format %{ "[$reg + $off]" %}
4668 interface(MEMORY_INTER) %{
4669 base($reg);
4670 index(0x4);
4671 scale(0x0);
4672 disp($off);
4673 %}
4674 %}
4675
4676 // Indirect Memory Plus Long Offset Operand
4677 operand indOffset32X(rRegI reg, immP off) %{
4678 match(AddP off reg);
4679
4680 format %{ "[$reg + $off]" %}
4681 interface(MEMORY_INTER) %{
4682 base($reg);
4683 index(0x4);
4684 scale(0x0);
4685 disp($off);
4686 %}
4687 %}
4688
4689 // Indirect Memory Plus Index Register Plus Offset Operand
4690 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4691 match(AddP (AddP reg ireg) off);
4692
4693 op_cost(10);
4694 format %{"[$reg + $off + $ireg]" %}
4695 interface(MEMORY_INTER) %{
4696 base($reg);
4697 index($ireg);
4698 scale(0x0);
4699 disp($off);
4700 %}
4701 %}
4702
4703 // Indirect Memory Plus Index Register Plus Offset Operand
4704 operand indIndex(eRegP reg, rRegI ireg) %{
4705 match(AddP reg ireg);
4706
4707 op_cost(10);
4708 format %{"[$reg + $ireg]" %}
4709 interface(MEMORY_INTER) %{
4710 base($reg);
4711 index($ireg);
4712 scale(0x0);
4713 disp(0x0);
4714 %}
4715 %}
4716
4717 // // -------------------------------------------------------------------------
4718 // // 486 architecture doesn't support "scale * index + offset" with out a base
4719 // // -------------------------------------------------------------------------
4720 // // Scaled Memory Operands
4721 // // Indirect Memory Times Scale Plus Offset Operand
4722 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4723 // match(AddP off (LShiftI ireg scale));
4724 //
4725 // op_cost(10);
4726 // format %{"[$off + $ireg << $scale]" %}
4727 // interface(MEMORY_INTER) %{
4728 // base(0x4);
4729 // index($ireg);
4730 // scale($scale);
4731 // disp($off);
4732 // %}
4733 // %}
4734
4735 // Indirect Memory Times Scale Plus Index Register
4736 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4737 match(AddP reg (LShiftI ireg scale));
4738
4739 op_cost(10);
4740 format %{"[$reg + $ireg << $scale]" %}
4741 interface(MEMORY_INTER) %{
4742 base($reg);
4743 index($ireg);
4744 scale($scale);
4745 disp(0x0);
4746 %}
4747 %}
4748
4749 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4750 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4751 match(AddP (AddP reg (LShiftI ireg scale)) off);
4752
4753 op_cost(10);
4754 format %{"[$reg + $off + $ireg << $scale]" %}
4755 interface(MEMORY_INTER) %{
4756 base($reg);
4757 index($ireg);
4758 scale($scale);
4759 disp($off);
4760 %}
4761 %}
4762
4763 //----------Load Long Memory Operands------------------------------------------
4764 // The load-long idiom will use it's address expression again after loading
4765 // the first word of the long. If the load-long destination overlaps with
4766 // registers used in the addressing expression, the 2nd half will be loaded
4767 // from a clobbered address. Fix this by requiring that load-long use
4768 // address registers that do not overlap with the load-long target.
4769
4770 // load-long support
4771 operand load_long_RegP() %{
4772 constraint(ALLOC_IN_RC(esi_reg));
4773 match(RegP);
4774 match(eSIRegP);
4775 op_cost(100);
4776 format %{ %}
4777 interface(REG_INTER);
4778 %}
4779
4780 // Indirect Memory Operand Long
4781 operand load_long_indirect(load_long_RegP reg) %{
4782 constraint(ALLOC_IN_RC(esi_reg));
4783 match(reg);
4784
4785 format %{ "[$reg]" %}
4786 interface(MEMORY_INTER) %{
4787 base($reg);
4788 index(0x4);
4789 scale(0x0);
4790 disp(0x0);
4791 %}
4792 %}
4793
4794 // Indirect Memory Plus Long Offset Operand
4795 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4796 match(AddP reg off);
4797
4798 format %{ "[$reg + $off]" %}
4799 interface(MEMORY_INTER) %{
4800 base($reg);
4801 index(0x4);
4802 scale(0x0);
4803 disp($off);
4804 %}
4805 %}
4806
4807 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4808
4809
4810 //----------Special Memory Operands--------------------------------------------
4811 // Stack Slot Operand - This operand is used for loading and storing temporary
4812 // values on the stack where a match requires a value to
4813 // flow through memory.
4814 operand stackSlotP(sRegP reg) %{
4815 constraint(ALLOC_IN_RC(stack_slots));
4816 // No match rule because this operand is only generated in matching
4817 format %{ "[$reg]" %}
4818 interface(MEMORY_INTER) %{
4819 base(0x4); // ESP
4820 index(0x4); // No Index
4821 scale(0x0); // No Scale
4822 disp($reg); // Stack Offset
4823 %}
4824 %}
4825
4826 operand stackSlotI(sRegI reg) %{
4827 constraint(ALLOC_IN_RC(stack_slots));
4828 // No match rule because this operand is only generated in matching
4829 format %{ "[$reg]" %}
4830 interface(MEMORY_INTER) %{
4831 base(0x4); // ESP
4832 index(0x4); // No Index
4833 scale(0x0); // No Scale
4834 disp($reg); // Stack Offset
4835 %}
4836 %}
4837
4838 operand stackSlotF(sRegF reg) %{
4839 constraint(ALLOC_IN_RC(stack_slots));
4840 // No match rule because this operand is only generated in matching
4841 format %{ "[$reg]" %}
4842 interface(MEMORY_INTER) %{
4843 base(0x4); // ESP
4844 index(0x4); // No Index
4845 scale(0x0); // No Scale
4846 disp($reg); // Stack Offset
4847 %}
4848 %}
4849
4850 operand stackSlotD(sRegD reg) %{
4851 constraint(ALLOC_IN_RC(stack_slots));
4852 // No match rule because this operand is only generated in matching
4853 format %{ "[$reg]" %}
4854 interface(MEMORY_INTER) %{
4855 base(0x4); // ESP
4856 index(0x4); // No Index
4857 scale(0x0); // No Scale
4858 disp($reg); // Stack Offset
4859 %}
4860 %}
4861
4862 operand stackSlotL(sRegL reg) %{
4863 constraint(ALLOC_IN_RC(stack_slots));
4864 // No match rule because this operand is only generated in matching
4865 format %{ "[$reg]" %}
4866 interface(MEMORY_INTER) %{
4867 base(0x4); // ESP
4868 index(0x4); // No Index
4869 scale(0x0); // No Scale
4870 disp($reg); // Stack Offset
4871 %}
4872 %}
4873
4874 //----------Memory Operands - Win95 Implicit Null Variants----------------
4875 // Indirect Memory Operand
4876 operand indirect_win95_safe(eRegP_no_EBP reg)
4877 %{
4878 constraint(ALLOC_IN_RC(int_reg));
4879 match(reg);
4880
4881 op_cost(100);
4882 format %{ "[$reg]" %}
4883 interface(MEMORY_INTER) %{
4884 base($reg);
4885 index(0x4);
4886 scale(0x0);
4887 disp(0x0);
4888 %}
4889 %}
4890
4891 // Indirect Memory Plus Short Offset Operand
4892 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4893 %{
4894 match(AddP reg off);
4895
4896 op_cost(100);
4897 format %{ "[$reg + $off]" %}
4898 interface(MEMORY_INTER) %{
4899 base($reg);
4900 index(0x4);
4901 scale(0x0);
4902 disp($off);
4903 %}
4904 %}
4905
4906 // Indirect Memory Plus Long Offset Operand
4907 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4908 %{
4909 match(AddP reg off);
4910
4911 op_cost(100);
4912 format %{ "[$reg + $off]" %}
4913 interface(MEMORY_INTER) %{
4914 base($reg);
4915 index(0x4);
4916 scale(0x0);
4917 disp($off);
4918 %}
4919 %}
4920
4921 // Indirect Memory Plus Index Register Plus Offset Operand
4922 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4923 %{
4924 match(AddP (AddP reg ireg) off);
4925
4926 op_cost(100);
4927 format %{"[$reg + $off + $ireg]" %}
4928 interface(MEMORY_INTER) %{
4929 base($reg);
4930 index($ireg);
4931 scale(0x0);
4932 disp($off);
4933 %}
4934 %}
4935
4936 // Indirect Memory Times Scale Plus Index Register
4937 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4938 %{
4939 match(AddP reg (LShiftI ireg scale));
4940
4941 op_cost(100);
4942 format %{"[$reg + $ireg << $scale]" %}
4943 interface(MEMORY_INTER) %{
4944 base($reg);
4945 index($ireg);
4946 scale($scale);
4947 disp(0x0);
4948 %}
4949 %}
4950
4951 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4952 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4953 %{
4954 match(AddP (AddP reg (LShiftI ireg scale)) off);
4955
4956 op_cost(100);
4957 format %{"[$reg + $off + $ireg << $scale]" %}
4958 interface(MEMORY_INTER) %{
4959 base($reg);
4960 index($ireg);
4961 scale($scale);
4962 disp($off);
4963 %}
4964 %}
4965
4966 //----------Conditional Branch Operands----------------------------------------
4967 // Comparison Op - This is the operation of the comparison, and is limited to
4968 // the following set of codes:
4969 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4970 //
4971 // Other attributes of the comparison, such as unsignedness, are specified
4972 // by the comparison instruction that sets a condition code flags register.
4973 // That result is represented by a flags operand whose subtype is appropriate
4974 // to the unsignedness (etc.) of the comparison.
4975 //
4976 // Later, the instruction which matches both the Comparison Op (a Bool) and
4977 // the flags (produced by the Cmp) specifies the coding of the comparison op
4978 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4979
4980 // Comparision Code
4981 operand cmpOp() %{
4982 match(Bool);
4983
4984 format %{ "" %}
4985 interface(COND_INTER) %{
4986 equal(0x4, "e");
4987 not_equal(0x5, "ne");
4988 less(0xC, "l");
4989 greater_equal(0xD, "ge");
4990 less_equal(0xE, "le");
4991 greater(0xF, "g");
4992 %}
4993 %}
4994
4995 // Comparison Code, unsigned compare. Used by FP also, with
4996 // C2 (unordered) turned into GT or LT already. The other bits
4997 // C0 and C3 are turned into Carry & Zero flags.
4998 operand cmpOpU() %{
4999 match(Bool);
5000
5001 format %{ "" %}
5002 interface(COND_INTER) %{
5003 equal(0x4, "e");
5004 not_equal(0x5, "ne");
5005 less(0x2, "b");
5006 greater_equal(0x3, "nb");
5007 less_equal(0x6, "be");
5008 greater(0x7, "nbe");
5009 %}
5010 %}
5011
5012 // Floating comparisons that don't require any fixup for the unordered case
5013 operand cmpOpUCF() %{
5014 match(Bool);
5015 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5016 n->as_Bool()->_test._test == BoolTest::ge ||
5017 n->as_Bool()->_test._test == BoolTest::le ||
5018 n->as_Bool()->_test._test == BoolTest::gt);
5019 format %{ "" %}
5020 interface(COND_INTER) %{
5021 equal(0x4, "e");
5022 not_equal(0x5, "ne");
5023 less(0x2, "b");
5024 greater_equal(0x3, "nb");
5025 less_equal(0x6, "be");
5026 greater(0x7, "nbe");
5027 %}
5028 %}
5029
5030
5031 // Floating comparisons that can be fixed up with extra conditional jumps
5032 operand cmpOpUCF2() %{
5033 match(Bool);
5034 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5035 n->as_Bool()->_test._test == BoolTest::eq);
5036 format %{ "" %}
5037 interface(COND_INTER) %{
5038 equal(0x4, "e");
5039 not_equal(0x5, "ne");
5040 less(0x2, "b");
5041 greater_equal(0x3, "nb");
5042 less_equal(0x6, "be");
5043 greater(0x7, "nbe");
5044 %}
5045 %}
5046
5047 // Comparison Code for FP conditional move
5048 operand cmpOp_fcmov() %{
5049 match(Bool);
5050
5051 format %{ "" %}
5052 interface(COND_INTER) %{
5053 equal (0x0C8);
5054 not_equal (0x1C8);
5055 less (0x0C0);
5056 greater_equal(0x1C0);
5057 less_equal (0x0D0);
5058 greater (0x1D0);
5059 %}
5060 %}
5061
5062 // Comparision Code used in long compares
5063 operand cmpOp_commute() %{
5064 match(Bool);
5065
5066 format %{ "" %}
5067 interface(COND_INTER) %{
5068 equal(0x4, "e");
5069 not_equal(0x5, "ne");
5070 less(0xF, "g");
5071 greater_equal(0xE, "le");
5072 less_equal(0xD, "ge");
5073 greater(0xC, "l");
5074 %}
5075 %}
5076
5077 //----------OPERAND CLASSES----------------------------------------------------
5078 // Operand Classes are groups of operands that are used as to simplify
5079 // instruction definitions by not requiring the AD writer to specify separate
5080 // instructions for every form of operand when the instruction accepts
5081 // multiple operand types with the same basic encoding and format. The classic
5082 // case of this is memory operands.
5083
5084 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5085 indIndex, indIndexScale, indIndexScaleOffset);
5086
5087 // Long memory operations are encoded in 2 instructions and a +4 offset.
5088 // This means some kind of offset is always required and you cannot use
5089 // an oop as the offset (done when working on static globals).
5090 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5091 indIndex, indIndexScale, indIndexScaleOffset);
5092
5093
5094 //----------PIPELINE-----------------------------------------------------------
5095 // Rules which define the behavior of the target architectures pipeline.
5096 pipeline %{
5097
5098 //----------ATTRIBUTES---------------------------------------------------------
5099 attributes %{
5100 variable_size_instructions; // Fixed size instructions
5101 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5102 instruction_unit_size = 1; // An instruction is 1 bytes long
5103 instruction_fetch_unit_size = 16; // The processor fetches one line
5104 instruction_fetch_units = 1; // of 16 bytes
5105
5106 // List of nop instructions
5107 nops( MachNop );
5108 %}
5109
5110 //----------RESOURCES----------------------------------------------------------
5111 // Resources are the functional units available to the machine
5112
5113 // Generic P2/P3 pipeline
5114 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5115 // 3 instructions decoded per cycle.
5116 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5117 // 2 ALU op, only ALU0 handles mul/div instructions.
5118 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5119 MS0, MS1, MEM = MS0 | MS1,
5120 BR, FPU,
5121 ALU0, ALU1, ALU = ALU0 | ALU1 );
5122
5123 //----------PIPELINE DESCRIPTION-----------------------------------------------
5124 // Pipeline Description specifies the stages in the machine's pipeline
5125
5126 // Generic P2/P3 pipeline
5127 pipe_desc(S0, S1, S2, S3, S4, S5);
5128
5129 //----------PIPELINE CLASSES---------------------------------------------------
5130 // Pipeline Classes describe the stages in which input and output are
5131 // referenced by the hardware pipeline.
5132
5133 // Naming convention: ialu or fpu
5134 // Then: _reg
5135 // Then: _reg if there is a 2nd register
5136 // Then: _long if it's a pair of instructions implementing a long
5137 // Then: _fat if it requires the big decoder
5138 // Or: _mem if it requires the big decoder and a memory unit.
5139
5140 // Integer ALU reg operation
5141 pipe_class ialu_reg(rRegI dst) %{
5142 single_instruction;
5143 dst : S4(write);
5144 dst : S3(read);
5145 DECODE : S0; // any decoder
5146 ALU : S3; // any alu
5147 %}
5148
5149 // Long ALU reg operation
5150 pipe_class ialu_reg_long(eRegL dst) %{
5151 instruction_count(2);
5152 dst : S4(write);
5153 dst : S3(read);
5154 DECODE : S0(2); // any 2 decoders
5155 ALU : S3(2); // both alus
5156 %}
5157
5158 // Integer ALU reg operation using big decoder
5159 pipe_class ialu_reg_fat(rRegI dst) %{
5160 single_instruction;
5161 dst : S4(write);
5162 dst : S3(read);
5163 D0 : S0; // big decoder only
5164 ALU : S3; // any alu
5165 %}
5166
5167 // Long ALU reg operation using big decoder
5168 pipe_class ialu_reg_long_fat(eRegL dst) %{
5169 instruction_count(2);
5170 dst : S4(write);
5171 dst : S3(read);
5172 D0 : S0(2); // big decoder only; twice
5173 ALU : S3(2); // any 2 alus
5174 %}
5175
5176 // Integer ALU reg-reg operation
5177 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5178 single_instruction;
5179 dst : S4(write);
5180 src : S3(read);
5181 DECODE : S0; // any decoder
5182 ALU : S3; // any alu
5183 %}
5184
5185 // Long ALU reg-reg operation
5186 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5187 instruction_count(2);
5188 dst : S4(write);
5189 src : S3(read);
5190 DECODE : S0(2); // any 2 decoders
5191 ALU : S3(2); // both alus
5192 %}
5193
5194 // Integer ALU reg-reg operation
5195 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5196 single_instruction;
5197 dst : S4(write);
5198 src : S3(read);
5199 D0 : S0; // big decoder only
5200 ALU : S3; // any alu
5201 %}
5202
5203 // Long ALU reg-reg operation
5204 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5205 instruction_count(2);
5206 dst : S4(write);
5207 src : S3(read);
5208 D0 : S0(2); // big decoder only; twice
5209 ALU : S3(2); // both alus
5210 %}
5211
5212 // Integer ALU reg-mem operation
5213 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5214 single_instruction;
5215 dst : S5(write);
5216 mem : S3(read);
5217 D0 : S0; // big decoder only
5218 ALU : S4; // any alu
5219 MEM : S3; // any mem
5220 %}
5221
5222 // Long ALU reg-mem operation
5223 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5224 instruction_count(2);
5225 dst : S5(write);
5226 mem : S3(read);
5227 D0 : S0(2); // big decoder only; twice
5228 ALU : S4(2); // any 2 alus
5229 MEM : S3(2); // both mems
5230 %}
5231
5232 // Integer mem operation (prefetch)
5233 pipe_class ialu_mem(memory mem)
5234 %{
5235 single_instruction;
5236 mem : S3(read);
5237 D0 : S0; // big decoder only
5238 MEM : S3; // any mem
5239 %}
5240
5241 // Integer Store to Memory
5242 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5243 single_instruction;
5244 mem : S3(read);
5245 src : S5(read);
5246 D0 : S0; // big decoder only
5247 ALU : S4; // any alu
5248 MEM : S3;
5249 %}
5250
5251 // Long Store to Memory
5252 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5253 instruction_count(2);
5254 mem : S3(read);
5255 src : S5(read);
5256 D0 : S0(2); // big decoder only; twice
5257 ALU : S4(2); // any 2 alus
5258 MEM : S3(2); // Both mems
5259 %}
5260
5261 // Integer Store to Memory
5262 pipe_class ialu_mem_imm(memory mem) %{
5263 single_instruction;
5264 mem : S3(read);
5265 D0 : S0; // big decoder only
5266 ALU : S4; // any alu
5267 MEM : S3;
5268 %}
5269
5270 // Integer ALU0 reg-reg operation
5271 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5272 single_instruction;
5273 dst : S4(write);
5274 src : S3(read);
5275 D0 : S0; // Big decoder only
5276 ALU0 : S3; // only alu0
5277 %}
5278
5279 // Integer ALU0 reg-mem operation
5280 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5281 single_instruction;
5282 dst : S5(write);
5283 mem : S3(read);
5284 D0 : S0; // big decoder only
5285 ALU0 : S4; // ALU0 only
5286 MEM : S3; // any mem
5287 %}
5288
5289 // Integer ALU reg-reg operation
5290 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5291 single_instruction;
5292 cr : S4(write);
5293 src1 : S3(read);
5294 src2 : S3(read);
5295 DECODE : S0; // any decoder
5296 ALU : S3; // any alu
5297 %}
5298
5299 // Integer ALU reg-imm operation
5300 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5301 single_instruction;
5302 cr : S4(write);
5303 src1 : S3(read);
5304 DECODE : S0; // any decoder
5305 ALU : S3; // any alu
5306 %}
5307
5308 // Integer ALU reg-mem operation
5309 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5310 single_instruction;
5311 cr : S4(write);
5312 src1 : S3(read);
5313 src2 : S3(read);
5314 D0 : S0; // big decoder only
5315 ALU : S4; // any alu
5316 MEM : S3;
5317 %}
5318
5319 // Conditional move reg-reg
5320 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5321 instruction_count(4);
5322 y : S4(read);
5323 q : S3(read);
5324 p : S3(read);
5325 DECODE : S0(4); // any decoder
5326 %}
5327
5328 // Conditional move reg-reg
5329 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5330 single_instruction;
5331 dst : S4(write);
5332 src : S3(read);
5333 cr : S3(read);
5334 DECODE : S0; // any decoder
5335 %}
5336
5337 // Conditional move reg-mem
5338 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5339 single_instruction;
5340 dst : S4(write);
5341 src : S3(read);
5342 cr : S3(read);
5343 DECODE : S0; // any decoder
5344 MEM : S3;
5345 %}
5346
5347 // Conditional move reg-reg long
5348 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5349 single_instruction;
5350 dst : S4(write);
5351 src : S3(read);
5352 cr : S3(read);
5353 DECODE : S0(2); // any 2 decoders
5354 %}
5355
5356 // Conditional move double reg-reg
5357 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5358 single_instruction;
5359 dst : S4(write);
5360 src : S3(read);
5361 cr : S3(read);
5362 DECODE : S0; // any decoder
5363 %}
5364
5365 // Float reg-reg operation
5366 pipe_class fpu_reg(regDPR dst) %{
5367 instruction_count(2);
5368 dst : S3(read);
5369 DECODE : S0(2); // any 2 decoders
5370 FPU : S3;
5371 %}
5372
5373 // Float reg-reg operation
5374 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5375 instruction_count(2);
5376 dst : S4(write);
5377 src : S3(read);
5378 DECODE : S0(2); // any 2 decoders
5379 FPU : S3;
5380 %}
5381
5382 // Float reg-reg operation
5383 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5384 instruction_count(3);
5385 dst : S4(write);
5386 src1 : S3(read);
5387 src2 : S3(read);
5388 DECODE : S0(3); // any 3 decoders
5389 FPU : S3(2);
5390 %}
5391
5392 // Float reg-reg operation
5393 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5394 instruction_count(4);
5395 dst : S4(write);
5396 src1 : S3(read);
5397 src2 : S3(read);
5398 src3 : S3(read);
5399 DECODE : S0(4); // any 3 decoders
5400 FPU : S3(2);
5401 %}
5402
5403 // Float reg-reg operation
5404 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5405 instruction_count(4);
5406 dst : S4(write);
5407 src1 : S3(read);
5408 src2 : S3(read);
5409 src3 : S3(read);
5410 DECODE : S1(3); // any 3 decoders
5411 D0 : S0; // Big decoder only
5412 FPU : S3(2);
5413 MEM : S3;
5414 %}
5415
5416 // Float reg-mem operation
5417 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5418 instruction_count(2);
5419 dst : S5(write);
5420 mem : S3(read);
5421 D0 : S0; // big decoder only
5422 DECODE : S1; // any decoder for FPU POP
5423 FPU : S4;
5424 MEM : S3; // any mem
5425 %}
5426
5427 // Float reg-mem operation
5428 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5429 instruction_count(3);
5430 dst : S5(write);
5431 src1 : S3(read);
5432 mem : S3(read);
5433 D0 : S0; // big decoder only
5434 DECODE : S1(2); // any decoder for FPU POP
5435 FPU : S4;
5436 MEM : S3; // any mem
5437 %}
5438
5439 // Float mem-reg operation
5440 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5441 instruction_count(2);
5442 src : S5(read);
5443 mem : S3(read);
5444 DECODE : S0; // any decoder for FPU PUSH
5445 D0 : S1; // big decoder only
5446 FPU : S4;
5447 MEM : S3; // any mem
5448 %}
5449
5450 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5451 instruction_count(3);
5452 src1 : S3(read);
5453 src2 : S3(read);
5454 mem : S3(read);
5455 DECODE : S0(2); // any decoder for FPU PUSH
5456 D0 : S1; // big decoder only
5457 FPU : S4;
5458 MEM : S3; // any mem
5459 %}
5460
5461 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5462 instruction_count(3);
5463 src1 : S3(read);
5464 src2 : S3(read);
5465 mem : S4(read);
5466 DECODE : S0; // any decoder for FPU PUSH
5467 D0 : S0(2); // big decoder only
5468 FPU : S4;
5469 MEM : S3(2); // any mem
5470 %}
5471
5472 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5473 instruction_count(2);
5474 src1 : S3(read);
5475 dst : S4(read);
5476 D0 : S0(2); // big decoder only
5477 MEM : S3(2); // any mem
5478 %}
5479
5480 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5481 instruction_count(3);
5482 src1 : S3(read);
5483 src2 : S3(read);
5484 dst : S4(read);
5485 D0 : S0(3); // big decoder only
5486 FPU : S4;
5487 MEM : S3(3); // any mem
5488 %}
5489
5490 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5491 instruction_count(3);
5492 src1 : S4(read);
5493 mem : S4(read);
5494 DECODE : S0; // any decoder for FPU PUSH
5495 D0 : S0(2); // big decoder only
5496 FPU : S4;
5497 MEM : S3(2); // any mem
5498 %}
5499
5500 // Float load constant
5501 pipe_class fpu_reg_con(regDPR dst) %{
5502 instruction_count(2);
5503 dst : S5(write);
5504 D0 : S0; // big decoder only for the load
5505 DECODE : S1; // any decoder for FPU POP
5506 FPU : S4;
5507 MEM : S3; // any mem
5508 %}
5509
5510 // Float load constant
5511 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5512 instruction_count(3);
5513 dst : S5(write);
5514 src : S3(read);
5515 D0 : S0; // big decoder only for the load
5516 DECODE : S1(2); // any decoder for FPU POP
5517 FPU : S4;
5518 MEM : S3; // any mem
5519 %}
5520
5521 // UnConditional branch
5522 pipe_class pipe_jmp( label labl ) %{
5523 single_instruction;
5524 BR : S3;
5525 %}
5526
5527 // Conditional branch
5528 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5529 single_instruction;
5530 cr : S1(read);
5531 BR : S3;
5532 %}
5533
5534 // Allocation idiom
5535 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5536 instruction_count(1); force_serialization;
5537 fixed_latency(6);
5538 heap_ptr : S3(read);
5539 DECODE : S0(3);
5540 D0 : S2;
5541 MEM : S3;
5542 ALU : S3(2);
5543 dst : S5(write);
5544 BR : S5;
5545 %}
5546
5547 // Generic big/slow expanded idiom
5548 pipe_class pipe_slow( ) %{
5549 instruction_count(10); multiple_bundles; force_serialization;
5550 fixed_latency(100);
5551 D0 : S0(2);
5552 MEM : S3(2);
5553 %}
5554
5555 // The real do-nothing guy
5556 pipe_class empty( ) %{
5557 instruction_count(0);
5558 %}
5559
5560 // Define the class for the Nop node
5561 define %{
5562 MachNop = empty;
5563 %}
5564
5565 %}
5566
5567 //----------INSTRUCTIONS-------------------------------------------------------
5568 //
5569 // match -- States which machine-independent subtree may be replaced
5570 // by this instruction.
5571 // ins_cost -- The estimated cost of this instruction is used by instruction
5572 // selection to identify a minimum cost tree of machine
5573 // instructions that matches a tree of machine-independent
5574 // instructions.
5575 // format -- A string providing the disassembly for this instruction.
5576 // The value of an instruction's operand may be inserted
5577 // by referring to it with a '$' prefix.
5578 // opcode -- Three instruction opcodes may be provided. These are referred
5579 // to within an encode class as $primary, $secondary, and $tertiary
5580 // respectively. The primary opcode is commonly used to
5581 // indicate the type of machine instruction, while secondary
5582 // and tertiary are often used for prefix options or addressing
5583 // modes.
5584 // ins_encode -- A list of encode classes with parameters. The encode class
5585 // name must have been defined in an 'enc_class' specification
5586 // in the encode section of the architecture description.
5587
5588 //----------BSWAP-Instruction--------------------------------------------------
5589 instruct bytes_reverse_int(rRegI dst) %{
5590 match(Set dst (ReverseBytesI dst));
5591
5592 format %{ "BSWAP $dst" %}
5593 opcode(0x0F, 0xC8);
5594 ins_encode( OpcP, OpcSReg(dst) );
5595 ins_pipe( ialu_reg );
5596 %}
5597
5598 instruct bytes_reverse_long(eRegL dst) %{
5599 match(Set dst (ReverseBytesL dst));
5600
5601 format %{ "BSWAP $dst.lo\n\t"
5602 "BSWAP $dst.hi\n\t"
5603 "XCHG $dst.lo $dst.hi" %}
5604
5605 ins_cost(125);
5606 ins_encode( bswap_long_bytes(dst) );
5607 ins_pipe( ialu_reg_reg);
5608 %}
5609
5610 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5611 match(Set dst (ReverseBytesUS dst));
5612 effect(KILL cr);
5613
5614 format %{ "BSWAP $dst\n\t"
5615 "SHR $dst,16\n\t" %}
5616 ins_encode %{
5617 __ bswapl($dst$$Register);
5618 __ shrl($dst$$Register, 16);
5619 %}
5620 ins_pipe( ialu_reg );
5621 %}
5622
5623 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5624 match(Set dst (ReverseBytesS dst));
5625 effect(KILL cr);
5626
5627 format %{ "BSWAP $dst\n\t"
5628 "SAR $dst,16\n\t" %}
5629 ins_encode %{
5630 __ bswapl($dst$$Register);
5631 __ sarl($dst$$Register, 16);
5632 %}
5633 ins_pipe( ialu_reg );
5634 %}
5635
5636
5637 //---------- Zeros Count Instructions ------------------------------------------
5638
5639 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5640 predicate(UseCountLeadingZerosInstruction);
5641 match(Set dst (CountLeadingZerosI src));
5642 effect(KILL cr);
5643
5644 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5645 ins_encode %{
5646 __ lzcntl($dst$$Register, $src$$Register);
5647 %}
5648 ins_pipe(ialu_reg);
5649 %}
5650
5651 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5652 predicate(!UseCountLeadingZerosInstruction);
5653 match(Set dst (CountLeadingZerosI src));
5654 effect(KILL cr);
5655
5656 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5657 "JNZ skip\n\t"
5658 "MOV $dst, -1\n"
5659 "skip:\n\t"
5660 "NEG $dst\n\t"
5661 "ADD $dst, 31" %}
5662 ins_encode %{
5663 Register Rdst = $dst$$Register;
5664 Register Rsrc = $src$$Register;
5665 Label skip;
5666 __ bsrl(Rdst, Rsrc);
5667 __ jccb(Assembler::notZero, skip);
5668 __ movl(Rdst, -1);
5669 __ bind(skip);
5670 __ negl(Rdst);
5671 __ addl(Rdst, BitsPerInt - 1);
5672 %}
5673 ins_pipe(ialu_reg);
5674 %}
5675
5676 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5677 predicate(UseCountLeadingZerosInstruction);
5678 match(Set dst (CountLeadingZerosL src));
5679 effect(TEMP dst, KILL cr);
5680
5681 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5682 "JNC done\n\t"
5683 "LZCNT $dst, $src.lo\n\t"
5684 "ADD $dst, 32\n"
5685 "done:" %}
5686 ins_encode %{
5687 Register Rdst = $dst$$Register;
5688 Register Rsrc = $src$$Register;
5689 Label done;
5690 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5691 __ jccb(Assembler::carryClear, done);
5692 __ lzcntl(Rdst, Rsrc);
5693 __ addl(Rdst, BitsPerInt);
5694 __ bind(done);
5695 %}
5696 ins_pipe(ialu_reg);
5697 %}
5698
5699 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5700 predicate(!UseCountLeadingZerosInstruction);
5701 match(Set dst (CountLeadingZerosL src));
5702 effect(TEMP dst, KILL cr);
5703
5704 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5705 "JZ msw_is_zero\n\t"
5706 "ADD $dst, 32\n\t"
5707 "JMP not_zero\n"
5708 "msw_is_zero:\n\t"
5709 "BSR $dst, $src.lo\n\t"
5710 "JNZ not_zero\n\t"
5711 "MOV $dst, -1\n"
5712 "not_zero:\n\t"
5713 "NEG $dst\n\t"
5714 "ADD $dst, 63\n" %}
5715 ins_encode %{
5716 Register Rdst = $dst$$Register;
5717 Register Rsrc = $src$$Register;
5718 Label msw_is_zero;
5719 Label not_zero;
5720 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5721 __ jccb(Assembler::zero, msw_is_zero);
5722 __ addl(Rdst, BitsPerInt);
5723 __ jmpb(not_zero);
5724 __ bind(msw_is_zero);
5725 __ bsrl(Rdst, Rsrc);
5726 __ jccb(Assembler::notZero, not_zero);
5727 __ movl(Rdst, -1);
5728 __ bind(not_zero);
5729 __ negl(Rdst);
5730 __ addl(Rdst, BitsPerLong - 1);
5731 %}
5732 ins_pipe(ialu_reg);
5733 %}
5734
5735 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5736 match(Set dst (CountTrailingZerosI src));
5737 effect(KILL cr);
5738
5739 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5740 "JNZ done\n\t"
5741 "MOV $dst, 32\n"
5742 "done:" %}
5743 ins_encode %{
5744 Register Rdst = $dst$$Register;
5745 Label done;
5746 __ bsfl(Rdst, $src$$Register);
5747 __ jccb(Assembler::notZero, done);
5748 __ movl(Rdst, BitsPerInt);
5749 __ bind(done);
5750 %}
5751 ins_pipe(ialu_reg);
5752 %}
5753
5754 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5755 match(Set dst (CountTrailingZerosL src));
5756 effect(TEMP dst, KILL cr);
5757
5758 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5759 "JNZ done\n\t"
5760 "BSF $dst, $src.hi\n\t"
5761 "JNZ msw_not_zero\n\t"
5762 "MOV $dst, 32\n"
5763 "msw_not_zero:\n\t"
5764 "ADD $dst, 32\n"
5765 "done:" %}
5766 ins_encode %{
5767 Register Rdst = $dst$$Register;
5768 Register Rsrc = $src$$Register;
5769 Label msw_not_zero;
5770 Label done;
5771 __ bsfl(Rdst, Rsrc);
5772 __ jccb(Assembler::notZero, done);
5773 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5774 __ jccb(Assembler::notZero, msw_not_zero);
5775 __ movl(Rdst, BitsPerInt);
5776 __ bind(msw_not_zero);
5777 __ addl(Rdst, BitsPerInt);
5778 __ bind(done);
5779 %}
5780 ins_pipe(ialu_reg);
5781 %}
5782
5783
5784 //---------- Population Count Instructions -------------------------------------
5785
5786 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5787 predicate(UsePopCountInstruction);
5788 match(Set dst (PopCountI src));
5789 effect(KILL cr);
5790
5791 format %{ "POPCNT $dst, $src" %}
5792 ins_encode %{
5793 __ popcntl($dst$$Register, $src$$Register);
5794 %}
5795 ins_pipe(ialu_reg);
5796 %}
5797
5798 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5799 predicate(UsePopCountInstruction);
5800 match(Set dst (PopCountI (LoadI mem)));
5801 effect(KILL cr);
5802
5803 format %{ "POPCNT $dst, $mem" %}
5804 ins_encode %{
5805 __ popcntl($dst$$Register, $mem$$Address);
5806 %}
5807 ins_pipe(ialu_reg);
5808 %}
5809
5810 // Note: Long.bitCount(long) returns an int.
5811 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5812 predicate(UsePopCountInstruction);
5813 match(Set dst (PopCountL src));
5814 effect(KILL cr, TEMP tmp, TEMP dst);
5815
5816 format %{ "POPCNT $dst, $src.lo\n\t"
5817 "POPCNT $tmp, $src.hi\n\t"
5818 "ADD $dst, $tmp" %}
5819 ins_encode %{
5820 __ popcntl($dst$$Register, $src$$Register);
5821 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5822 __ addl($dst$$Register, $tmp$$Register);
5823 %}
5824 ins_pipe(ialu_reg);
5825 %}
5826
5827 // Note: Long.bitCount(long) returns an int.
5828 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5829 predicate(UsePopCountInstruction);
5830 match(Set dst (PopCountL (LoadL mem)));
5831 effect(KILL cr, TEMP tmp, TEMP dst);
5832
5833 format %{ "POPCNT $dst, $mem\n\t"
5834 "POPCNT $tmp, $mem+4\n\t"
5835 "ADD $dst, $tmp" %}
5836 ins_encode %{
5837 //__ popcntl($dst$$Register, $mem$$Address$$first);
5838 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5839 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
5840 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
5841 __ addl($dst$$Register, $tmp$$Register);
5842 %}
5843 ins_pipe(ialu_reg);
5844 %}
5845
5846
5847 //----------Load/Store/Move Instructions---------------------------------------
5848 //----------Load Instructions--------------------------------------------------
5849 // Load Byte (8bit signed)
5850 instruct loadB(xRegI dst, memory mem) %{
5851 match(Set dst (LoadB mem));
5852
5853 ins_cost(125);
5854 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5855
5856 ins_encode %{
5857 __ movsbl($dst$$Register, $mem$$Address);
5858 %}
5859
5860 ins_pipe(ialu_reg_mem);
5861 %}
5862
5863 // Load Byte (8bit signed) into Long Register
5864 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5865 match(Set dst (ConvI2L (LoadB mem)));
5866 effect(KILL cr);
5867
5868 ins_cost(375);
5869 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5870 "MOV $dst.hi,$dst.lo\n\t"
5871 "SAR $dst.hi,7" %}
5872
5873 ins_encode %{
5874 __ movsbl($dst$$Register, $mem$$Address);
5875 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5876 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5877 %}
5878
5879 ins_pipe(ialu_reg_mem);
5880 %}
5881
5882 // Load Unsigned Byte (8bit UNsigned)
5883 instruct loadUB(xRegI dst, memory mem) %{
5884 match(Set dst (LoadUB mem));
5885
5886 ins_cost(125);
5887 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5888
5889 ins_encode %{
5890 __ movzbl($dst$$Register, $mem$$Address);
5891 %}
5892
5893 ins_pipe(ialu_reg_mem);
5894 %}
5895
5896 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5897 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5898 match(Set dst (ConvI2L (LoadUB mem)));
5899 effect(KILL cr);
5900
5901 ins_cost(250);
5902 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5903 "XOR $dst.hi,$dst.hi" %}
5904
5905 ins_encode %{
5906 Register Rdst = $dst$$Register;
5907 __ movzbl(Rdst, $mem$$Address);
5908 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5909 %}
5910
5911 ins_pipe(ialu_reg_mem);
5912 %}
5913
5914 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5915 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5916 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5917 effect(KILL cr);
5918
5919 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5920 "XOR $dst.hi,$dst.hi\n\t"
5921 "AND $dst.lo,$mask" %}
5922 ins_encode %{
5923 Register Rdst = $dst$$Register;
5924 __ movzbl(Rdst, $mem$$Address);
5925 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5926 __ andl(Rdst, $mask$$constant);
5927 %}
5928 ins_pipe(ialu_reg_mem);
5929 %}
5930
5931 // Load Short (16bit signed)
5932 instruct loadS(rRegI dst, memory mem) %{
5933 match(Set dst (LoadS mem));
5934
5935 ins_cost(125);
5936 format %{ "MOVSX $dst,$mem\t# short" %}
5937
5938 ins_encode %{
5939 __ movswl($dst$$Register, $mem$$Address);
5940 %}
5941
5942 ins_pipe(ialu_reg_mem);
5943 %}
5944
5945 // Load Short (16 bit signed) to Byte (8 bit signed)
5946 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5947 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5948
5949 ins_cost(125);
5950 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5951 ins_encode %{
5952 __ movsbl($dst$$Register, $mem$$Address);
5953 %}
5954 ins_pipe(ialu_reg_mem);
5955 %}
5956
5957 // Load Short (16bit signed) into Long Register
5958 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5959 match(Set dst (ConvI2L (LoadS mem)));
5960 effect(KILL cr);
5961
5962 ins_cost(375);
5963 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5964 "MOV $dst.hi,$dst.lo\n\t"
5965 "SAR $dst.hi,15" %}
5966
5967 ins_encode %{
5968 __ movswl($dst$$Register, $mem$$Address);
5969 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5970 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5971 %}
5972
5973 ins_pipe(ialu_reg_mem);
5974 %}
5975
5976 // Load Unsigned Short/Char (16bit unsigned)
5977 instruct loadUS(rRegI dst, memory mem) %{
5978 match(Set dst (LoadUS mem));
5979
5980 ins_cost(125);
5981 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5982
5983 ins_encode %{
5984 __ movzwl($dst$$Register, $mem$$Address);
5985 %}
5986
5987 ins_pipe(ialu_reg_mem);
5988 %}
5989
5990 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5991 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5992 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5993
5994 ins_cost(125);
5995 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5996 ins_encode %{
5997 __ movsbl($dst$$Register, $mem$$Address);
5998 %}
5999 ins_pipe(ialu_reg_mem);
6000 %}
6001
6002 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6003 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6004 match(Set dst (ConvI2L (LoadUS mem)));
6005 effect(KILL cr);
6006
6007 ins_cost(250);
6008 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6009 "XOR $dst.hi,$dst.hi" %}
6010
6011 ins_encode %{
6012 __ movzwl($dst$$Register, $mem$$Address);
6013 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6014 %}
6015
6016 ins_pipe(ialu_reg_mem);
6017 %}
6018
6019 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6020 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6021 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6022 effect(KILL cr);
6023
6024 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6025 "XOR $dst.hi,$dst.hi" %}
6026 ins_encode %{
6027 Register Rdst = $dst$$Register;
6028 __ movzbl(Rdst, $mem$$Address);
6029 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6030 %}
6031 ins_pipe(ialu_reg_mem);
6032 %}
6033
6034 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6035 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6036 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6037 effect(KILL cr);
6038
6039 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6040 "XOR $dst.hi,$dst.hi\n\t"
6041 "AND $dst.lo,$mask" %}
6042 ins_encode %{
6043 Register Rdst = $dst$$Register;
6044 __ movzwl(Rdst, $mem$$Address);
6045 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6046 __ andl(Rdst, $mask$$constant);
6047 %}
6048 ins_pipe(ialu_reg_mem);
6049 %}
6050
6051 // Load Integer
6052 instruct loadI(rRegI dst, memory mem) %{
6053 match(Set dst (LoadI mem));
6054
6055 ins_cost(125);
6056 format %{ "MOV $dst,$mem\t# int" %}
6057
6058 ins_encode %{
6059 __ movl($dst$$Register, $mem$$Address);
6060 %}
6061
6062 ins_pipe(ialu_reg_mem);
6063 %}
6064
6065 // Load Integer (32 bit signed) to Byte (8 bit signed)
6066 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6067 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6068
6069 ins_cost(125);
6070 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6071 ins_encode %{
6072 __ movsbl($dst$$Register, $mem$$Address);
6073 %}
6074 ins_pipe(ialu_reg_mem);
6075 %}
6076
6077 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6078 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6079 match(Set dst (AndI (LoadI mem) mask));
6080
6081 ins_cost(125);
6082 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6083 ins_encode %{
6084 __ movzbl($dst$$Register, $mem$$Address);
6085 %}
6086 ins_pipe(ialu_reg_mem);
6087 %}
6088
6089 // Load Integer (32 bit signed) to Short (16 bit signed)
6090 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6091 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6092
6093 ins_cost(125);
6094 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6095 ins_encode %{
6096 __ movswl($dst$$Register, $mem$$Address);
6097 %}
6098 ins_pipe(ialu_reg_mem);
6099 %}
6100
6101 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6102 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6103 match(Set dst (AndI (LoadI mem) mask));
6104
6105 ins_cost(125);
6106 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6107 ins_encode %{
6108 __ movzwl($dst$$Register, $mem$$Address);
6109 %}
6110 ins_pipe(ialu_reg_mem);
6111 %}
6112
6113 // Load Integer into Long Register
6114 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6115 match(Set dst (ConvI2L (LoadI mem)));
6116 effect(KILL cr);
6117
6118 ins_cost(375);
6119 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6120 "MOV $dst.hi,$dst.lo\n\t"
6121 "SAR $dst.hi,31" %}
6122
6123 ins_encode %{
6124 __ movl($dst$$Register, $mem$$Address);
6125 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6126 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6127 %}
6128
6129 ins_pipe(ialu_reg_mem);
6130 %}
6131
6132 // Load Integer with mask 0xFF into Long Register
6133 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6134 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6135 effect(KILL cr);
6136
6137 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6138 "XOR $dst.hi,$dst.hi" %}
6139 ins_encode %{
6140 Register Rdst = $dst$$Register;
6141 __ movzbl(Rdst, $mem$$Address);
6142 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6143 %}
6144 ins_pipe(ialu_reg_mem);
6145 %}
6146
6147 // Load Integer with mask 0xFFFF into Long Register
6148 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6149 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6150 effect(KILL cr);
6151
6152 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6153 "XOR $dst.hi,$dst.hi" %}
6154 ins_encode %{
6155 Register Rdst = $dst$$Register;
6156 __ movzwl(Rdst, $mem$$Address);
6157 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6158 %}
6159 ins_pipe(ialu_reg_mem);
6160 %}
6161
6162 // Load Integer with 32-bit mask into Long Register
6163 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6164 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6165 effect(KILL cr);
6166
6167 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6168 "XOR $dst.hi,$dst.hi\n\t"
6169 "AND $dst.lo,$mask" %}
6170 ins_encode %{
6171 Register Rdst = $dst$$Register;
6172 __ movl(Rdst, $mem$$Address);
6173 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6174 __ andl(Rdst, $mask$$constant);
6175 %}
6176 ins_pipe(ialu_reg_mem);
6177 %}
6178
6179 // Load Unsigned Integer into Long Register
6180 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6181 match(Set dst (LoadUI2L mem));
6182 effect(KILL cr);
6183
6184 ins_cost(250);
6185 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6186 "XOR $dst.hi,$dst.hi" %}
6187
6188 ins_encode %{
6189 __ movl($dst$$Register, $mem$$Address);
6190 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6191 %}
6192
6193 ins_pipe(ialu_reg_mem);
6194 %}
6195
6196 // Load Long. Cannot clobber address while loading, so restrict address
6197 // register to ESI
6198 instruct loadL(eRegL dst, load_long_memory mem) %{
6199 predicate(!((LoadLNode*)n)->require_atomic_access());
6200 match(Set dst (LoadL mem));
6201
6202 ins_cost(250);
6203 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6204 "MOV $dst.hi,$mem+4" %}
6205
6206 ins_encode %{
6207 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6208 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6209 __ movl($dst$$Register, Amemlo);
6210 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6211 %}
6212
6213 ins_pipe(ialu_reg_long_mem);
6214 %}
6215
6216 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6217 // then store it down to the stack and reload on the int
6218 // side.
6219 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6220 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6221 match(Set dst (LoadL mem));
6222
6223 ins_cost(200);
6224 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6225 "FISTp $dst" %}
6226 ins_encode(enc_loadL_volatile(mem,dst));
6227 ins_pipe( fpu_reg_mem );
6228 %}
6229
6230 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6231 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6232 match(Set dst (LoadL mem));
6233 effect(TEMP tmp);
6234 ins_cost(180);
6235 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6236 "MOVSD $dst,$tmp" %}
6237 ins_encode %{
6238 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6239 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6240 %}
6241 ins_pipe( pipe_slow );
6242 %}
6243
6244 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6245 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6246 match(Set dst (LoadL mem));
6247 effect(TEMP tmp);
6248 ins_cost(160);
6249 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6250 "MOVD $dst.lo,$tmp\n\t"
6251 "PSRLQ $tmp,32\n\t"
6252 "MOVD $dst.hi,$tmp" %}
6253 ins_encode %{
6254 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6255 __ movdl($dst$$Register, $tmp$$XMMRegister);
6256 __ psrlq($tmp$$XMMRegister, 32);
6257 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6258 %}
6259 ins_pipe( pipe_slow );
6260 %}
6261
6262 // Load Range
6263 instruct loadRange(rRegI dst, memory mem) %{
6264 match(Set dst (LoadRange mem));
6265
6266 ins_cost(125);
6267 format %{ "MOV $dst,$mem" %}
6268 opcode(0x8B);
6269 ins_encode( OpcP, RegMem(dst,mem));
6270 ins_pipe( ialu_reg_mem );
6271 %}
6272
6273
6274 // Load Pointer
6275 instruct loadP(eRegP dst, memory mem) %{
6276 match(Set dst (LoadP mem));
6277
6278 ins_cost(125);
6279 format %{ "MOV $dst,$mem" %}
6280 opcode(0x8B);
6281 ins_encode( OpcP, RegMem(dst,mem));
6282 ins_pipe( ialu_reg_mem );
6283 %}
6284
6285 // Load Klass Pointer
6286 instruct loadKlass(eRegP dst, memory mem) %{
6287 match(Set dst (LoadKlass mem));
6288
6289 ins_cost(125);
6290 format %{ "MOV $dst,$mem" %}
6291 opcode(0x8B);
6292 ins_encode( OpcP, RegMem(dst,mem));
6293 ins_pipe( ialu_reg_mem );
6294 %}
6295
6296 // Load Double
6297 instruct loadDPR(regDPR dst, memory mem) %{
6298 predicate(UseSSE<=1);
6299 match(Set dst (LoadD mem));
6300
6301 ins_cost(150);
6302 format %{ "FLD_D ST,$mem\n\t"
6303 "FSTP $dst" %}
6304 opcode(0xDD); /* DD /0 */
6305 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6306 Pop_Reg_DPR(dst) );
6307 ins_pipe( fpu_reg_mem );
6308 %}
6309
6310 // Load Double to XMM
6311 instruct loadD(regD dst, memory mem) %{
6312 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6313 match(Set dst (LoadD mem));
6314 ins_cost(145);
6315 format %{ "MOVSD $dst,$mem" %}
6316 ins_encode %{
6317 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6318 %}
6319 ins_pipe( pipe_slow );
6320 %}
6321
6322 instruct loadD_partial(regD dst, memory mem) %{
6323 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6324 match(Set dst (LoadD mem));
6325 ins_cost(145);
6326 format %{ "MOVLPD $dst,$mem" %}
6327 ins_encode %{
6328 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6329 %}
6330 ins_pipe( pipe_slow );
6331 %}
6332
6333 // Load to XMM register (single-precision floating point)
6334 // MOVSS instruction
6335 instruct loadF(regF dst, memory mem) %{
6336 predicate(UseSSE>=1);
6337 match(Set dst (LoadF mem));
6338 ins_cost(145);
6339 format %{ "MOVSS $dst,$mem" %}
6340 ins_encode %{
6341 __ movflt ($dst$$XMMRegister, $mem$$Address);
6342 %}
6343 ins_pipe( pipe_slow );
6344 %}
6345
6346 // Load Float
6347 instruct loadFPR(regFPR dst, memory mem) %{
6348 predicate(UseSSE==0);
6349 match(Set dst (LoadF mem));
6350
6351 ins_cost(150);
6352 format %{ "FLD_S ST,$mem\n\t"
6353 "FSTP $dst" %}
6354 opcode(0xD9); /* D9 /0 */
6355 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6356 Pop_Reg_FPR(dst) );
6357 ins_pipe( fpu_reg_mem );
6358 %}
6359
6360 // Load Effective Address
6361 instruct leaP8(eRegP dst, indOffset8 mem) %{
6362 match(Set dst mem);
6363
6364 ins_cost(110);
6365 format %{ "LEA $dst,$mem" %}
6366 opcode(0x8D);
6367 ins_encode( OpcP, RegMem(dst,mem));
6368 ins_pipe( ialu_reg_reg_fat );
6369 %}
6370
6371 instruct leaP32(eRegP dst, indOffset32 mem) %{
6372 match(Set dst mem);
6373
6374 ins_cost(110);
6375 format %{ "LEA $dst,$mem" %}
6376 opcode(0x8D);
6377 ins_encode( OpcP, RegMem(dst,mem));
6378 ins_pipe( ialu_reg_reg_fat );
6379 %}
6380
6381 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6382 match(Set dst mem);
6383
6384 ins_cost(110);
6385 format %{ "LEA $dst,$mem" %}
6386 opcode(0x8D);
6387 ins_encode( OpcP, RegMem(dst,mem));
6388 ins_pipe( ialu_reg_reg_fat );
6389 %}
6390
6391 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6392 match(Set dst mem);
6393
6394 ins_cost(110);
6395 format %{ "LEA $dst,$mem" %}
6396 opcode(0x8D);
6397 ins_encode( OpcP, RegMem(dst,mem));
6398 ins_pipe( ialu_reg_reg_fat );
6399 %}
6400
6401 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6402 match(Set dst mem);
6403
6404 ins_cost(110);
6405 format %{ "LEA $dst,$mem" %}
6406 opcode(0x8D);
6407 ins_encode( OpcP, RegMem(dst,mem));
6408 ins_pipe( ialu_reg_reg_fat );
6409 %}
6410
6411 // Load Constant
6412 instruct loadConI(rRegI dst, immI src) %{
6413 match(Set dst src);
6414
6415 format %{ "MOV $dst,$src" %}
6416 ins_encode( LdImmI(dst, src) );
6417 ins_pipe( ialu_reg_fat );
6418 %}
6419
6420 // Load Constant zero
6421 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6422 match(Set dst src);
6423 effect(KILL cr);
6424
6425 ins_cost(50);
6426 format %{ "XOR $dst,$dst" %}
6427 opcode(0x33); /* + rd */
6428 ins_encode( OpcP, RegReg( dst, dst ) );
6429 ins_pipe( ialu_reg );
6430 %}
6431
6432 instruct loadConP(eRegP dst, immP src) %{
6433 match(Set dst src);
6434
6435 format %{ "MOV $dst,$src" %}
6436 opcode(0xB8); /* + rd */
6437 ins_encode( LdImmP(dst, src) );
6438 ins_pipe( ialu_reg_fat );
6439 %}
6440
6441 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6442 match(Set dst src);
6443 effect(KILL cr);
6444 ins_cost(200);
6445 format %{ "MOV $dst.lo,$src.lo\n\t"
6446 "MOV $dst.hi,$src.hi" %}
6447 opcode(0xB8);
6448 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6449 ins_pipe( ialu_reg_long_fat );
6450 %}
6451
6452 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6453 match(Set dst src);
6454 effect(KILL cr);
6455 ins_cost(150);
6456 format %{ "XOR $dst.lo,$dst.lo\n\t"
6457 "XOR $dst.hi,$dst.hi" %}
6458 opcode(0x33,0x33);
6459 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6460 ins_pipe( ialu_reg_long );
6461 %}
6462
6463 // The instruction usage is guarded by predicate in operand immFPR().
6464 instruct loadConFPR(regFPR dst, immFPR con) %{
6465 match(Set dst con);
6466 ins_cost(125);
6467 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6468 "FSTP $dst" %}
6469 ins_encode %{
6470 __ fld_s($constantaddress($con));
6471 __ fstp_d($dst$$reg);
6472 %}
6473 ins_pipe(fpu_reg_con);
6474 %}
6475
6476 // The instruction usage is guarded by predicate in operand immFPR0().
6477 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6478 match(Set dst con);
6479 ins_cost(125);
6480 format %{ "FLDZ ST\n\t"
6481 "FSTP $dst" %}
6482 ins_encode %{
6483 __ fldz();
6484 __ fstp_d($dst$$reg);
6485 %}
6486 ins_pipe(fpu_reg_con);
6487 %}
6488
6489 // The instruction usage is guarded by predicate in operand immFPR1().
6490 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6491 match(Set dst con);
6492 ins_cost(125);
6493 format %{ "FLD1 ST\n\t"
6494 "FSTP $dst" %}
6495 ins_encode %{
6496 __ fld1();
6497 __ fstp_d($dst$$reg);
6498 %}
6499 ins_pipe(fpu_reg_con);
6500 %}
6501
6502 // The instruction usage is guarded by predicate in operand immF().
6503 instruct loadConF(regF dst, immF con) %{
6504 match(Set dst con);
6505 ins_cost(125);
6506 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6507 ins_encode %{
6508 __ movflt($dst$$XMMRegister, $constantaddress($con));
6509 %}
6510 ins_pipe(pipe_slow);
6511 %}
6512
6513 // The instruction usage is guarded by predicate in operand immF0().
6514 instruct loadConF0(regF dst, immF0 src) %{
6515 match(Set dst src);
6516 ins_cost(100);
6517 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6518 ins_encode %{
6519 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6520 %}
6521 ins_pipe(pipe_slow);
6522 %}
6523
6524 // The instruction usage is guarded by predicate in operand immDPR().
6525 instruct loadConDPR(regDPR dst, immDPR con) %{
6526 match(Set dst con);
6527 ins_cost(125);
6528
6529 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6530 "FSTP $dst" %}
6531 ins_encode %{
6532 __ fld_d($constantaddress($con));
6533 __ fstp_d($dst$$reg);
6534 %}
6535 ins_pipe(fpu_reg_con);
6536 %}
6537
6538 // The instruction usage is guarded by predicate in operand immDPR0().
6539 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6540 match(Set dst con);
6541 ins_cost(125);
6542
6543 format %{ "FLDZ ST\n\t"
6544 "FSTP $dst" %}
6545 ins_encode %{
6546 __ fldz();
6547 __ fstp_d($dst$$reg);
6548 %}
6549 ins_pipe(fpu_reg_con);
6550 %}
6551
6552 // The instruction usage is guarded by predicate in operand immDPR1().
6553 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6554 match(Set dst con);
6555 ins_cost(125);
6556
6557 format %{ "FLD1 ST\n\t"
6558 "FSTP $dst" %}
6559 ins_encode %{
6560 __ fld1();
6561 __ fstp_d($dst$$reg);
6562 %}
6563 ins_pipe(fpu_reg_con);
6564 %}
6565
6566 // The instruction usage is guarded by predicate in operand immD().
6567 instruct loadConD(regD dst, immD con) %{
6568 match(Set dst con);
6569 ins_cost(125);
6570 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6571 ins_encode %{
6572 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6573 %}
6574 ins_pipe(pipe_slow);
6575 %}
6576
6577 // The instruction usage is guarded by predicate in operand immD0().
6578 instruct loadConD0(regD dst, immD0 src) %{
6579 match(Set dst src);
6580 ins_cost(100);
6581 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6582 ins_encode %{
6583 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6584 %}
6585 ins_pipe( pipe_slow );
6586 %}
6587
6588 // Load Stack Slot
6589 instruct loadSSI(rRegI dst, stackSlotI src) %{
6590 match(Set dst src);
6591 ins_cost(125);
6592
6593 format %{ "MOV $dst,$src" %}
6594 opcode(0x8B);
6595 ins_encode( OpcP, RegMem(dst,src));
6596 ins_pipe( ialu_reg_mem );
6597 %}
6598
6599 instruct loadSSL(eRegL dst, stackSlotL src) %{
6600 match(Set dst src);
6601
6602 ins_cost(200);
6603 format %{ "MOV $dst,$src.lo\n\t"
6604 "MOV $dst+4,$src.hi" %}
6605 opcode(0x8B, 0x8B);
6606 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6607 ins_pipe( ialu_mem_long_reg );
6608 %}
6609
6610 // Load Stack Slot
6611 instruct loadSSP(eRegP dst, stackSlotP src) %{
6612 match(Set dst src);
6613 ins_cost(125);
6614
6615 format %{ "MOV $dst,$src" %}
6616 opcode(0x8B);
6617 ins_encode( OpcP, RegMem(dst,src));
6618 ins_pipe( ialu_reg_mem );
6619 %}
6620
6621 // Load Stack Slot
6622 instruct loadSSF(regFPR dst, stackSlotF src) %{
6623 match(Set dst src);
6624 ins_cost(125);
6625
6626 format %{ "FLD_S $src\n\t"
6627 "FSTP $dst" %}
6628 opcode(0xD9); /* D9 /0, FLD m32real */
6629 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6630 Pop_Reg_FPR(dst) );
6631 ins_pipe( fpu_reg_mem );
6632 %}
6633
6634 // Load Stack Slot
6635 instruct loadSSD(regDPR dst, stackSlotD src) %{
6636 match(Set dst src);
6637 ins_cost(125);
6638
6639 format %{ "FLD_D $src\n\t"
6640 "FSTP $dst" %}
6641 opcode(0xDD); /* DD /0, FLD m64real */
6642 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6643 Pop_Reg_DPR(dst) );
6644 ins_pipe( fpu_reg_mem );
6645 %}
6646
6647 // Prefetch instructions.
6648 // Must be safe to execute with invalid address (cannot fault).
6649
6650 instruct prefetchr0( memory mem ) %{
6651 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6652 match(PrefetchRead mem);
6653 ins_cost(0);
6654 size(0);
6655 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6656 ins_encode();
6657 ins_pipe(empty);
6658 %}
6659
6660 instruct prefetchr( memory mem ) %{
6661 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6662 match(PrefetchRead mem);
6663 ins_cost(100);
6664
6665 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6666 ins_encode %{
6667 __ prefetchr($mem$$Address);
6668 %}
6669 ins_pipe(ialu_mem);
6670 %}
6671
6672 instruct prefetchrNTA( memory mem ) %{
6673 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6674 match(PrefetchRead mem);
6675 ins_cost(100);
6676
6677 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6678 ins_encode %{
6679 __ prefetchnta($mem$$Address);
6680 %}
6681 ins_pipe(ialu_mem);
6682 %}
6683
6684 instruct prefetchrT0( memory mem ) %{
6685 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6686 match(PrefetchRead mem);
6687 ins_cost(100);
6688
6689 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6690 ins_encode %{
6691 __ prefetcht0($mem$$Address);
6692 %}
6693 ins_pipe(ialu_mem);
6694 %}
6695
6696 instruct prefetchrT2( memory mem ) %{
6697 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6698 match(PrefetchRead mem);
6699 ins_cost(100);
6700
6701 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6702 ins_encode %{
6703 __ prefetcht2($mem$$Address);
6704 %}
6705 ins_pipe(ialu_mem);
6706 %}
6707
6708 instruct prefetchw0( memory mem ) %{
6709 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6710 match(PrefetchWrite mem);
6711 ins_cost(0);
6712 size(0);
6713 format %{ "Prefetch (non-SSE is empty encoding)" %}
6714 ins_encode();
6715 ins_pipe(empty);
6716 %}
6717
6718 instruct prefetchw( memory mem ) %{
6719 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6720 match( PrefetchWrite mem );
6721 ins_cost(100);
6722
6723 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6724 ins_encode %{
6725 __ prefetchw($mem$$Address);
6726 %}
6727 ins_pipe(ialu_mem);
6728 %}
6729
6730 instruct prefetchwNTA( memory mem ) %{
6731 predicate(UseSSE>=1);
6732 match(PrefetchWrite mem);
6733 ins_cost(100);
6734
6735 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6736 ins_encode %{
6737 __ prefetchnta($mem$$Address);
6738 %}
6739 ins_pipe(ialu_mem);
6740 %}
6741
6742 // Prefetch instructions for allocation.
6743
6744 instruct prefetchAlloc0( memory mem ) %{
6745 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6746 match(PrefetchAllocation mem);
6747 ins_cost(0);
6748 size(0);
6749 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6750 ins_encode();
6751 ins_pipe(empty);
6752 %}
6753
6754 instruct prefetchAlloc( memory mem ) %{
6755 predicate(AllocatePrefetchInstr==3);
6756 match( PrefetchAllocation mem );
6757 ins_cost(100);
6758
6759 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6760 ins_encode %{
6761 __ prefetchw($mem$$Address);
6762 %}
6763 ins_pipe(ialu_mem);
6764 %}
6765
6766 instruct prefetchAllocNTA( memory mem ) %{
6767 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6768 match(PrefetchAllocation mem);
6769 ins_cost(100);
6770
6771 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6772 ins_encode %{
6773 __ prefetchnta($mem$$Address);
6774 %}
6775 ins_pipe(ialu_mem);
6776 %}
6777
6778 instruct prefetchAllocT0( memory mem ) %{
6779 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6780 match(PrefetchAllocation mem);
6781 ins_cost(100);
6782
6783 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6784 ins_encode %{
6785 __ prefetcht0($mem$$Address);
6786 %}
6787 ins_pipe(ialu_mem);
6788 %}
6789
6790 instruct prefetchAllocT2( memory mem ) %{
6791 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6792 match(PrefetchAllocation mem);
6793 ins_cost(100);
6794
6795 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6796 ins_encode %{
6797 __ prefetcht2($mem$$Address);
6798 %}
6799 ins_pipe(ialu_mem);
6800 %}
6801
6802 //----------Store Instructions-------------------------------------------------
6803
6804 // Store Byte
6805 instruct storeB(memory mem, xRegI src) %{
6806 match(Set mem (StoreB mem src));
6807
6808 ins_cost(125);
6809 format %{ "MOV8 $mem,$src" %}
6810 opcode(0x88);
6811 ins_encode( OpcP, RegMem( src, mem ) );
6812 ins_pipe( ialu_mem_reg );
6813 %}
6814
6815 // Store Char/Short
6816 instruct storeC(memory mem, rRegI src) %{
6817 match(Set mem (StoreC mem src));
6818
6819 ins_cost(125);
6820 format %{ "MOV16 $mem,$src" %}
6821 opcode(0x89, 0x66);
6822 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6823 ins_pipe( ialu_mem_reg );
6824 %}
6825
6826 // Store Integer
6827 instruct storeI(memory mem, rRegI src) %{
6828 match(Set mem (StoreI mem src));
6829
6830 ins_cost(125);
6831 format %{ "MOV $mem,$src" %}
6832 opcode(0x89);
6833 ins_encode( OpcP, RegMem( src, mem ) );
6834 ins_pipe( ialu_mem_reg );
6835 %}
6836
6837 // Store Long
6838 instruct storeL(long_memory mem, eRegL src) %{
6839 predicate(!((StoreLNode*)n)->require_atomic_access());
6840 match(Set mem (StoreL mem src));
6841
6842 ins_cost(200);
6843 format %{ "MOV $mem,$src.lo\n\t"
6844 "MOV $mem+4,$src.hi" %}
6845 opcode(0x89, 0x89);
6846 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6847 ins_pipe( ialu_mem_long_reg );
6848 %}
6849
6850 // Store Long to Integer
6851 instruct storeL2I(memory mem, eRegL src) %{
6852 match(Set mem (StoreI mem (ConvL2I src)));
6853
6854 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6855 ins_encode %{
6856 __ movl($mem$$Address, $src$$Register);
6857 %}
6858 ins_pipe(ialu_mem_reg);
6859 %}
6860
6861 // Volatile Store Long. Must be atomic, so move it into
6862 // the FP TOS and then do a 64-bit FIST. Has to probe the
6863 // target address before the store (for null-ptr checks)
6864 // so the memory operand is used twice in the encoding.
6865 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6866 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6867 match(Set mem (StoreL mem src));
6868 effect( KILL cr );
6869 ins_cost(400);
6870 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6871 "FILD $src\n\t"
6872 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6873 opcode(0x3B);
6874 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6875 ins_pipe( fpu_reg_mem );
6876 %}
6877
6878 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6879 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6880 match(Set mem (StoreL mem src));
6881 effect( TEMP tmp, KILL cr );
6882 ins_cost(380);
6883 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6884 "MOVSD $tmp,$src\n\t"
6885 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6886 ins_encode %{
6887 __ cmpl(rax, $mem$$Address);
6888 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6889 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6890 %}
6891 ins_pipe( pipe_slow );
6892 %}
6893
6894 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6895 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6896 match(Set mem (StoreL mem src));
6897 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6898 ins_cost(360);
6899 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6900 "MOVD $tmp,$src.lo\n\t"
6901 "MOVD $tmp2,$src.hi\n\t"
6902 "PUNPCKLDQ $tmp,$tmp2\n\t"
6903 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6904 ins_encode %{
6905 __ cmpl(rax, $mem$$Address);
6906 __ movdl($tmp$$XMMRegister, $src$$Register);
6907 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6908 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6909 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6910 %}
6911 ins_pipe( pipe_slow );
6912 %}
6913
6914 // Store Pointer; for storing unknown oops and raw pointers
6915 instruct storeP(memory mem, anyRegP src) %{
6916 match(Set mem (StoreP mem src));
6917
6918 ins_cost(125);
6919 format %{ "MOV $mem,$src" %}
6920 opcode(0x89);
6921 ins_encode( OpcP, RegMem( src, mem ) );
6922 ins_pipe( ialu_mem_reg );
6923 %}
6924
6925 // Store Integer Immediate
6926 instruct storeImmI(memory mem, immI src) %{
6927 match(Set mem (StoreI mem src));
6928
6929 ins_cost(150);
6930 format %{ "MOV $mem,$src" %}
6931 opcode(0xC7); /* C7 /0 */
6932 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6933 ins_pipe( ialu_mem_imm );
6934 %}
6935
6936 // Store Short/Char Immediate
6937 instruct storeImmI16(memory mem, immI16 src) %{
6938 predicate(UseStoreImmI16);
6939 match(Set mem (StoreC mem src));
6940
6941 ins_cost(150);
6942 format %{ "MOV16 $mem,$src" %}
6943 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6944 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6945 ins_pipe( ialu_mem_imm );
6946 %}
6947
6948 // Store Pointer Immediate; null pointers or constant oops that do not
6949 // need card-mark barriers.
6950 instruct storeImmP(memory mem, immP src) %{
6951 match(Set mem (StoreP mem src));
6952
6953 ins_cost(150);
6954 format %{ "MOV $mem,$src" %}
6955 opcode(0xC7); /* C7 /0 */
6956 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6957 ins_pipe( ialu_mem_imm );
6958 %}
6959
6960 // Store Byte Immediate
6961 instruct storeImmB(memory mem, immI8 src) %{
6962 match(Set mem (StoreB mem src));
6963
6964 ins_cost(150);
6965 format %{ "MOV8 $mem,$src" %}
6966 opcode(0xC6); /* C6 /0 */
6967 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6968 ins_pipe( ialu_mem_imm );
6969 %}
6970
6971 // Store CMS card-mark Immediate
6972 instruct storeImmCM(memory mem, immI8 src) %{
6973 match(Set mem (StoreCM mem src));
6974
6975 ins_cost(150);
6976 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6977 opcode(0xC6); /* C6 /0 */
6978 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6979 ins_pipe( ialu_mem_imm );
6980 %}
6981
6982 // Store Double
6983 instruct storeDPR( memory mem, regDPR1 src) %{
6984 predicate(UseSSE<=1);
6985 match(Set mem (StoreD mem src));
6986
6987 ins_cost(100);
6988 format %{ "FST_D $mem,$src" %}
6989 opcode(0xDD); /* DD /2 */
6990 ins_encode( enc_FPR_store(mem,src) );
6991 ins_pipe( fpu_mem_reg );
6992 %}
6993
6994 // Store double does rounding on x86
6995 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6996 predicate(UseSSE<=1);
6997 match(Set mem (StoreD mem (RoundDouble src)));
6998
6999 ins_cost(100);
7000 format %{ "FST_D $mem,$src\t# round" %}
7001 opcode(0xDD); /* DD /2 */
7002 ins_encode( enc_FPR_store(mem,src) );
7003 ins_pipe( fpu_mem_reg );
7004 %}
7005
7006 // Store XMM register to memory (double-precision floating points)
7007 // MOVSD instruction
7008 instruct storeD(memory mem, regD src) %{
7009 predicate(UseSSE>=2);
7010 match(Set mem (StoreD mem src));
7011 ins_cost(95);
7012 format %{ "MOVSD $mem,$src" %}
7013 ins_encode %{
7014 __ movdbl($mem$$Address, $src$$XMMRegister);
7015 %}
7016 ins_pipe( pipe_slow );
7017 %}
7018
7019 // Store XMM register to memory (single-precision floating point)
7020 // MOVSS instruction
7021 instruct storeF(memory mem, regF src) %{
7022 predicate(UseSSE>=1);
7023 match(Set mem (StoreF mem src));
7024 ins_cost(95);
7025 format %{ "MOVSS $mem,$src" %}
7026 ins_encode %{
7027 __ movflt($mem$$Address, $src$$XMMRegister);
7028 %}
7029 ins_pipe( pipe_slow );
7030 %}
7031
7032 // Store Float
7033 instruct storeFPR( memory mem, regFPR1 src) %{
7034 predicate(UseSSE==0);
7035 match(Set mem (StoreF mem src));
7036
7037 ins_cost(100);
7038 format %{ "FST_S $mem,$src" %}
7039 opcode(0xD9); /* D9 /2 */
7040 ins_encode( enc_FPR_store(mem,src) );
7041 ins_pipe( fpu_mem_reg );
7042 %}
7043
7044 // Store Float does rounding on x86
7045 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7046 predicate(UseSSE==0);
7047 match(Set mem (StoreF mem (RoundFloat src)));
7048
7049 ins_cost(100);
7050 format %{ "FST_S $mem,$src\t# round" %}
7051 opcode(0xD9); /* D9 /2 */
7052 ins_encode( enc_FPR_store(mem,src) );
7053 ins_pipe( fpu_mem_reg );
7054 %}
7055
7056 // Store Float does rounding on x86
7057 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7058 predicate(UseSSE<=1);
7059 match(Set mem (StoreF mem (ConvD2F src)));
7060
7061 ins_cost(100);
7062 format %{ "FST_S $mem,$src\t# D-round" %}
7063 opcode(0xD9); /* D9 /2 */
7064 ins_encode( enc_FPR_store(mem,src) );
7065 ins_pipe( fpu_mem_reg );
7066 %}
7067
7068 // Store immediate Float value (it is faster than store from FPU register)
7069 // The instruction usage is guarded by predicate in operand immFPR().
7070 instruct storeFPR_imm( memory mem, immFPR src) %{
7071 match(Set mem (StoreF mem src));
7072
7073 ins_cost(50);
7074 format %{ "MOV $mem,$src\t# store float" %}
7075 opcode(0xC7); /* C7 /0 */
7076 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7077 ins_pipe( ialu_mem_imm );
7078 %}
7079
7080 // Store immediate Float value (it is faster than store from XMM register)
7081 // The instruction usage is guarded by predicate in operand immF().
7082 instruct storeF_imm( memory mem, immF src) %{
7083 match(Set mem (StoreF mem src));
7084
7085 ins_cost(50);
7086 format %{ "MOV $mem,$src\t# store float" %}
7087 opcode(0xC7); /* C7 /0 */
7088 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7089 ins_pipe( ialu_mem_imm );
7090 %}
7091
7092 // Store Integer to stack slot
7093 instruct storeSSI(stackSlotI dst, rRegI src) %{
7094 match(Set dst src);
7095
7096 ins_cost(100);
7097 format %{ "MOV $dst,$src" %}
7098 opcode(0x89);
7099 ins_encode( OpcPRegSS( dst, src ) );
7100 ins_pipe( ialu_mem_reg );
7101 %}
7102
7103 // Store Integer to stack slot
7104 instruct storeSSP(stackSlotP dst, eRegP src) %{
7105 match(Set dst src);
7106
7107 ins_cost(100);
7108 format %{ "MOV $dst,$src" %}
7109 opcode(0x89);
7110 ins_encode( OpcPRegSS( dst, src ) );
7111 ins_pipe( ialu_mem_reg );
7112 %}
7113
7114 // Store Long to stack slot
7115 instruct storeSSL(stackSlotL dst, eRegL src) %{
7116 match(Set dst src);
7117
7118 ins_cost(200);
7119 format %{ "MOV $dst,$src.lo\n\t"
7120 "MOV $dst+4,$src.hi" %}
7121 opcode(0x89, 0x89);
7122 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7123 ins_pipe( ialu_mem_long_reg );
7124 %}
7125
7126 //----------MemBar Instructions-----------------------------------------------
7127 // Memory barrier flavors
7128
7129 instruct membar_acquire() %{
7130 match(MemBarAcquire);
7131 ins_cost(400);
7132
7133 size(0);
7134 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7135 ins_encode();
7136 ins_pipe(empty);
7137 %}
7138
7139 instruct membar_acquire_lock() %{
7140 match(MemBarAcquireLock);
7141 ins_cost(0);
7142
7143 size(0);
7144 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7145 ins_encode( );
7146 ins_pipe(empty);
7147 %}
7148
7149 instruct membar_release() %{
7150 match(MemBarRelease);
7151 ins_cost(400);
7152
7153 size(0);
7154 format %{ "MEMBAR-release ! (empty encoding)" %}
7155 ins_encode( );
7156 ins_pipe(empty);
7157 %}
7158
7159 instruct membar_release_lock() %{
7160 match(MemBarReleaseLock);
7161 ins_cost(0);
7162
7163 size(0);
7164 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7165 ins_encode( );
7166 ins_pipe(empty);
7167 %}
7168
7169 instruct membar_volatile(eFlagsReg cr) %{
7170 match(MemBarVolatile);
7171 effect(KILL cr);
7172 ins_cost(400);
7173
7174 format %{
7175 $$template
7176 if (os::is_MP()) {
7177 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7178 } else {
7179 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7180 }
7181 %}
7182 ins_encode %{
7183 __ membar(Assembler::StoreLoad);
7184 %}
7185 ins_pipe(pipe_slow);
7186 %}
7187
7188 instruct unnecessary_membar_volatile() %{
7189 match(MemBarVolatile);
7190 predicate(Matcher::post_store_load_barrier(n));
7191 ins_cost(0);
7192
7193 size(0);
7194 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7195 ins_encode( );
7196 ins_pipe(empty);
7197 %}
7198
7199 instruct membar_storestore() %{
7200 match(MemBarStoreStore);
7201 ins_cost(0);
7202
7203 size(0);
7204 format %{ "MEMBAR-storestore (empty encoding)" %}
7205 ins_encode( );
7206 ins_pipe(empty);
7207 %}
7208
7209 //----------Move Instructions--------------------------------------------------
7210 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7211 match(Set dst (CastX2P src));
7212 format %{ "# X2P $dst, $src" %}
7213 ins_encode( /*empty encoding*/ );
7214 ins_cost(0);
7215 ins_pipe(empty);
7216 %}
7217
7218 instruct castP2X(rRegI dst, eRegP src ) %{
7219 match(Set dst (CastP2X src));
7220 ins_cost(50);
7221 format %{ "MOV $dst, $src\t# CastP2X" %}
7222 ins_encode( enc_Copy( dst, src) );
7223 ins_pipe( ialu_reg_reg );
7224 %}
7225
7226 //----------Conditional Move---------------------------------------------------
7227 // Conditional move
7228 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7229 predicate(!VM_Version::supports_cmov() );
7230 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7231 ins_cost(200);
7232 format %{ "J$cop,us skip\t# signed cmove\n\t"
7233 "MOV $dst,$src\n"
7234 "skip:" %}
7235 ins_encode %{
7236 Label Lskip;
7237 // Invert sense of branch from sense of CMOV
7238 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7239 __ movl($dst$$Register, $src$$Register);
7240 __ bind(Lskip);
7241 %}
7242 ins_pipe( pipe_cmov_reg );
7243 %}
7244
7245 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7246 predicate(!VM_Version::supports_cmov() );
7247 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7248 ins_cost(200);
7249 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7250 "MOV $dst,$src\n"
7251 "skip:" %}
7252 ins_encode %{
7253 Label Lskip;
7254 // Invert sense of branch from sense of CMOV
7255 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7256 __ movl($dst$$Register, $src$$Register);
7257 __ bind(Lskip);
7258 %}
7259 ins_pipe( pipe_cmov_reg );
7260 %}
7261
7262 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7263 predicate(VM_Version::supports_cmov() );
7264 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7265 ins_cost(200);
7266 format %{ "CMOV$cop $dst,$src" %}
7267 opcode(0x0F,0x40);
7268 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7269 ins_pipe( pipe_cmov_reg );
7270 %}
7271
7272 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7273 predicate(VM_Version::supports_cmov() );
7274 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7275 ins_cost(200);
7276 format %{ "CMOV$cop $dst,$src" %}
7277 opcode(0x0F,0x40);
7278 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7279 ins_pipe( pipe_cmov_reg );
7280 %}
7281
7282 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7283 predicate(VM_Version::supports_cmov() );
7284 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7285 ins_cost(200);
7286 expand %{
7287 cmovI_regU(cop, cr, dst, src);
7288 %}
7289 %}
7290
7291 // Conditional move
7292 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7293 predicate(VM_Version::supports_cmov() );
7294 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7295 ins_cost(250);
7296 format %{ "CMOV$cop $dst,$src" %}
7297 opcode(0x0F,0x40);
7298 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7299 ins_pipe( pipe_cmov_mem );
7300 %}
7301
7302 // Conditional move
7303 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7304 predicate(VM_Version::supports_cmov() );
7305 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7306 ins_cost(250);
7307 format %{ "CMOV$cop $dst,$src" %}
7308 opcode(0x0F,0x40);
7309 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7310 ins_pipe( pipe_cmov_mem );
7311 %}
7312
7313 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7314 predicate(VM_Version::supports_cmov() );
7315 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7316 ins_cost(250);
7317 expand %{
7318 cmovI_memU(cop, cr, dst, src);
7319 %}
7320 %}
7321
7322 // Conditional move
7323 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7324 predicate(VM_Version::supports_cmov() );
7325 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7326 ins_cost(200);
7327 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7328 opcode(0x0F,0x40);
7329 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7330 ins_pipe( pipe_cmov_reg );
7331 %}
7332
7333 // Conditional move (non-P6 version)
7334 // Note: a CMoveP is generated for stubs and native wrappers
7335 // regardless of whether we are on a P6, so we
7336 // emulate a cmov here
7337 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7338 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7339 ins_cost(300);
7340 format %{ "Jn$cop skip\n\t"
7341 "MOV $dst,$src\t# pointer\n"
7342 "skip:" %}
7343 opcode(0x8b);
7344 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7345 ins_pipe( pipe_cmov_reg );
7346 %}
7347
7348 // Conditional move
7349 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7350 predicate(VM_Version::supports_cmov() );
7351 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7352 ins_cost(200);
7353 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7354 opcode(0x0F,0x40);
7355 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7356 ins_pipe( pipe_cmov_reg );
7357 %}
7358
7359 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7360 predicate(VM_Version::supports_cmov() );
7361 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7362 ins_cost(200);
7363 expand %{
7364 cmovP_regU(cop, cr, dst, src);
7365 %}
7366 %}
7367
7368 // DISABLED: Requires the ADLC to emit a bottom_type call that
7369 // correctly meets the two pointer arguments; one is an incoming
7370 // register but the other is a memory operand. ALSO appears to
7371 // be buggy with implicit null checks.
7372 //
7373 //// Conditional move
7374 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7375 // predicate(VM_Version::supports_cmov() );
7376 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7377 // ins_cost(250);
7378 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7379 // opcode(0x0F,0x40);
7380 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7381 // ins_pipe( pipe_cmov_mem );
7382 //%}
7383 //
7384 //// Conditional move
7385 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7386 // predicate(VM_Version::supports_cmov() );
7387 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7388 // ins_cost(250);
7389 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7390 // opcode(0x0F,0x40);
7391 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7392 // ins_pipe( pipe_cmov_mem );
7393 //%}
7394
7395 // Conditional move
7396 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7397 predicate(UseSSE<=1);
7398 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7399 ins_cost(200);
7400 format %{ "FCMOV$cop $dst,$src\t# double" %}
7401 opcode(0xDA);
7402 ins_encode( enc_cmov_dpr(cop,src) );
7403 ins_pipe( pipe_cmovDPR_reg );
7404 %}
7405
7406 // Conditional move
7407 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7408 predicate(UseSSE==0);
7409 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7410 ins_cost(200);
7411 format %{ "FCMOV$cop $dst,$src\t# float" %}
7412 opcode(0xDA);
7413 ins_encode( enc_cmov_dpr(cop,src) );
7414 ins_pipe( pipe_cmovDPR_reg );
7415 %}
7416
7417 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7418 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7419 predicate(UseSSE<=1);
7420 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7421 ins_cost(200);
7422 format %{ "Jn$cop skip\n\t"
7423 "MOV $dst,$src\t# double\n"
7424 "skip:" %}
7425 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7426 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7427 ins_pipe( pipe_cmovDPR_reg );
7428 %}
7429
7430 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7431 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7432 predicate(UseSSE==0);
7433 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7434 ins_cost(200);
7435 format %{ "Jn$cop skip\n\t"
7436 "MOV $dst,$src\t# float\n"
7437 "skip:" %}
7438 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7439 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7440 ins_pipe( pipe_cmovDPR_reg );
7441 %}
7442
7443 // No CMOVE with SSE/SSE2
7444 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7445 predicate (UseSSE>=1);
7446 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7447 ins_cost(200);
7448 format %{ "Jn$cop skip\n\t"
7449 "MOVSS $dst,$src\t# float\n"
7450 "skip:" %}
7451 ins_encode %{
7452 Label skip;
7453 // Invert sense of branch from sense of CMOV
7454 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7455 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7456 __ bind(skip);
7457 %}
7458 ins_pipe( pipe_slow );
7459 %}
7460
7461 // No CMOVE with SSE/SSE2
7462 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7463 predicate (UseSSE>=2);
7464 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7465 ins_cost(200);
7466 format %{ "Jn$cop skip\n\t"
7467 "MOVSD $dst,$src\t# float\n"
7468 "skip:" %}
7469 ins_encode %{
7470 Label skip;
7471 // Invert sense of branch from sense of CMOV
7472 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7473 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7474 __ bind(skip);
7475 %}
7476 ins_pipe( pipe_slow );
7477 %}
7478
7479 // unsigned version
7480 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7481 predicate (UseSSE>=1);
7482 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7483 ins_cost(200);
7484 format %{ "Jn$cop skip\n\t"
7485 "MOVSS $dst,$src\t# float\n"
7486 "skip:" %}
7487 ins_encode %{
7488 Label skip;
7489 // Invert sense of branch from sense of CMOV
7490 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7491 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7492 __ bind(skip);
7493 %}
7494 ins_pipe( pipe_slow );
7495 %}
7496
7497 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7498 predicate (UseSSE>=1);
7499 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7500 ins_cost(200);
7501 expand %{
7502 fcmovF_regU(cop, cr, dst, src);
7503 %}
7504 %}
7505
7506 // unsigned version
7507 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7508 predicate (UseSSE>=2);
7509 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7510 ins_cost(200);
7511 format %{ "Jn$cop skip\n\t"
7512 "MOVSD $dst,$src\t# float\n"
7513 "skip:" %}
7514 ins_encode %{
7515 Label skip;
7516 // Invert sense of branch from sense of CMOV
7517 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7518 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7519 __ bind(skip);
7520 %}
7521 ins_pipe( pipe_slow );
7522 %}
7523
7524 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7525 predicate (UseSSE>=2);
7526 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7527 ins_cost(200);
7528 expand %{
7529 fcmovD_regU(cop, cr, dst, src);
7530 %}
7531 %}
7532
7533 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7534 predicate(VM_Version::supports_cmov() );
7535 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7536 ins_cost(200);
7537 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7538 "CMOV$cop $dst.hi,$src.hi" %}
7539 opcode(0x0F,0x40);
7540 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7541 ins_pipe( pipe_cmov_reg_long );
7542 %}
7543
7544 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7545 predicate(VM_Version::supports_cmov() );
7546 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7547 ins_cost(200);
7548 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7549 "CMOV$cop $dst.hi,$src.hi" %}
7550 opcode(0x0F,0x40);
7551 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7552 ins_pipe( pipe_cmov_reg_long );
7553 %}
7554
7555 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7556 predicate(VM_Version::supports_cmov() );
7557 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7558 ins_cost(200);
7559 expand %{
7560 cmovL_regU(cop, cr, dst, src);
7561 %}
7562 %}
7563
7564 //----------Arithmetic Instructions--------------------------------------------
7565 //----------Addition Instructions----------------------------------------------
7566 // Integer Addition Instructions
7567 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7568 match(Set dst (AddI dst src));
7569 effect(KILL cr);
7570
7571 size(2);
7572 format %{ "ADD $dst,$src" %}
7573 opcode(0x03);
7574 ins_encode( OpcP, RegReg( dst, src) );
7575 ins_pipe( ialu_reg_reg );
7576 %}
7577
7578 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7579 match(Set dst (AddI dst src));
7580 effect(KILL cr);
7581
7582 format %{ "ADD $dst,$src" %}
7583 opcode(0x81, 0x00); /* /0 id */
7584 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7585 ins_pipe( ialu_reg );
7586 %}
7587
7588 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7589 predicate(UseIncDec);
7590 match(Set dst (AddI dst src));
7591 effect(KILL cr);
7592
7593 size(1);
7594 format %{ "INC $dst" %}
7595 opcode(0x40); /* */
7596 ins_encode( Opc_plus( primary, dst ) );
7597 ins_pipe( ialu_reg );
7598 %}
7599
7600 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7601 match(Set dst (AddI src0 src1));
7602 ins_cost(110);
7603
7604 format %{ "LEA $dst,[$src0 + $src1]" %}
7605 opcode(0x8D); /* 0x8D /r */
7606 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7607 ins_pipe( ialu_reg_reg );
7608 %}
7609
7610 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7611 match(Set dst (AddP src0 src1));
7612 ins_cost(110);
7613
7614 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7615 opcode(0x8D); /* 0x8D /r */
7616 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7617 ins_pipe( ialu_reg_reg );
7618 %}
7619
7620 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7621 predicate(UseIncDec);
7622 match(Set dst (AddI dst src));
7623 effect(KILL cr);
7624
7625 size(1);
7626 format %{ "DEC $dst" %}
7627 opcode(0x48); /* */
7628 ins_encode( Opc_plus( primary, dst ) );
7629 ins_pipe( ialu_reg );
7630 %}
7631
7632 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7633 match(Set dst (AddP dst src));
7634 effect(KILL cr);
7635
7636 size(2);
7637 format %{ "ADD $dst,$src" %}
7638 opcode(0x03);
7639 ins_encode( OpcP, RegReg( dst, src) );
7640 ins_pipe( ialu_reg_reg );
7641 %}
7642
7643 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7644 match(Set dst (AddP dst src));
7645 effect(KILL cr);
7646
7647 format %{ "ADD $dst,$src" %}
7648 opcode(0x81,0x00); /* Opcode 81 /0 id */
7649 // ins_encode( RegImm( dst, src) );
7650 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7651 ins_pipe( ialu_reg );
7652 %}
7653
7654 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7655 match(Set dst (AddI dst (LoadI src)));
7656 effect(KILL cr);
7657
7658 ins_cost(125);
7659 format %{ "ADD $dst,$src" %}
7660 opcode(0x03);
7661 ins_encode( OpcP, RegMem( dst, src) );
7662 ins_pipe( ialu_reg_mem );
7663 %}
7664
7665 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7666 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7667 effect(KILL cr);
7668
7669 ins_cost(150);
7670 format %{ "ADD $dst,$src" %}
7671 opcode(0x01); /* Opcode 01 /r */
7672 ins_encode( OpcP, RegMem( src, dst ) );
7673 ins_pipe( ialu_mem_reg );
7674 %}
7675
7676 // Add Memory with Immediate
7677 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7678 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7679 effect(KILL cr);
7680
7681 ins_cost(125);
7682 format %{ "ADD $dst,$src" %}
7683 opcode(0x81); /* Opcode 81 /0 id */
7684 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7685 ins_pipe( ialu_mem_imm );
7686 %}
7687
7688 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7689 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7690 effect(KILL cr);
7691
7692 ins_cost(125);
7693 format %{ "INC $dst" %}
7694 opcode(0xFF); /* Opcode FF /0 */
7695 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7696 ins_pipe( ialu_mem_imm );
7697 %}
7698
7699 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7700 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7701 effect(KILL cr);
7702
7703 ins_cost(125);
7704 format %{ "DEC $dst" %}
7705 opcode(0xFF); /* Opcode FF /1 */
7706 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7707 ins_pipe( ialu_mem_imm );
7708 %}
7709
7710
7711 instruct checkCastPP( eRegP dst ) %{
7712 match(Set dst (CheckCastPP dst));
7713
7714 size(0);
7715 format %{ "#checkcastPP of $dst" %}
7716 ins_encode( /*empty encoding*/ );
7717 ins_pipe( empty );
7718 %}
7719
7720 instruct castPP( eRegP dst ) %{
7721 match(Set dst (CastPP dst));
7722 format %{ "#castPP of $dst" %}
7723 ins_encode( /*empty encoding*/ );
7724 ins_pipe( empty );
7725 %}
7726
7727 instruct castII( rRegI dst ) %{
7728 match(Set dst (CastII dst));
7729 format %{ "#castII of $dst" %}
7730 ins_encode( /*empty encoding*/ );
7731 ins_cost(0);
7732 ins_pipe( empty );
7733 %}
7734
7735
7736 // Load-locked - same as a regular pointer load when used with compare-swap
7737 instruct loadPLocked(eRegP dst, memory mem) %{
7738 match(Set dst (LoadPLocked mem));
7739
7740 ins_cost(125);
7741 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7742 opcode(0x8B);
7743 ins_encode( OpcP, RegMem(dst,mem));
7744 ins_pipe( ialu_reg_mem );
7745 %}
7746
7747 // Conditional-store of the updated heap-top.
7748 // Used during allocation of the shared heap.
7749 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7750 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7751 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7752 // EAX is killed if there is contention, but then it's also unused.
7753 // In the common case of no contention, EAX holds the new oop address.
7754 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7755 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7756 ins_pipe( pipe_cmpxchg );
7757 %}
7758
7759 // Conditional-store of an int value.
7760 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7761 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7762 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7763 effect(KILL oldval);
7764 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7765 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7766 ins_pipe( pipe_cmpxchg );
7767 %}
7768
7769 // Conditional-store of a long value.
7770 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7771 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7772 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7773 effect(KILL oldval);
7774 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7775 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7776 "XCHG EBX,ECX"
7777 %}
7778 ins_encode %{
7779 // Note: we need to swap rbx, and rcx before and after the
7780 // cmpxchg8 instruction because the instruction uses
7781 // rcx as the high order word of the new value to store but
7782 // our register encoding uses rbx.
7783 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7784 if( os::is_MP() )
7785 __ lock();
7786 __ cmpxchg8($mem$$Address);
7787 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7788 %}
7789 ins_pipe( pipe_cmpxchg );
7790 %}
7791
7792 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7793
7794 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7795 predicate(VM_Version::supports_cx8());
7796 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7797 effect(KILL cr, KILL oldval);
7798 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7799 "MOV $res,0\n\t"
7800 "JNE,s fail\n\t"
7801 "MOV $res,1\n"
7802 "fail:" %}
7803 ins_encode( enc_cmpxchg8(mem_ptr),
7804 enc_flags_ne_to_boolean(res) );
7805 ins_pipe( pipe_cmpxchg );
7806 %}
7807
7808 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7809 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7810 effect(KILL cr, KILL oldval);
7811 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7812 "MOV $res,0\n\t"
7813 "JNE,s fail\n\t"
7814 "MOV $res,1\n"
7815 "fail:" %}
7816 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7817 ins_pipe( pipe_cmpxchg );
7818 %}
7819
7820 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7821 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7822 effect(KILL cr, KILL oldval);
7823 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7824 "MOV $res,0\n\t"
7825 "JNE,s fail\n\t"
7826 "MOV $res,1\n"
7827 "fail:" %}
7828 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7829 ins_pipe( pipe_cmpxchg );
7830 %}
7831
7832 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7833 predicate(n->as_LoadStore()->result_not_used());
7834 match(Set dummy (GetAndAddI mem add));
7835 effect(KILL cr);
7836 format %{ "ADDL [$mem],$add" %}
7837 ins_encode %{
7838 if (os::is_MP()) { __ lock(); }
7839 __ addl($mem$$Address, $add$$constant);
7840 %}
7841 ins_pipe( pipe_cmpxchg );
7842 %}
7843
7844 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7845 match(Set newval (GetAndAddI mem newval));
7846 effect(KILL cr);
7847 format %{ "XADDL [$mem],$newval" %}
7848 ins_encode %{
7849 if (os::is_MP()) { __ lock(); }
7850 __ xaddl($mem$$Address, $newval$$Register);
7851 %}
7852 ins_pipe( pipe_cmpxchg );
7853 %}
7854
7855 instruct xchgI( memory mem, rRegI newval) %{
7856 match(Set newval (GetAndSetI mem newval));
7857 format %{ "XCHGL $newval,[$mem]" %}
7858 ins_encode %{
7859 __ xchgl($newval$$Register, $mem$$Address);
7860 %}
7861 ins_pipe( pipe_cmpxchg );
7862 %}
7863
7864 instruct xchgP( memory mem, pRegP newval) %{
7865 match(Set newval (GetAndSetP mem newval));
7866 format %{ "XCHGL $newval,[$mem]" %}
7867 ins_encode %{
7868 __ xchgl($newval$$Register, $mem$$Address);
7869 %}
7870 ins_pipe( pipe_cmpxchg );
7871 %}
7872
7873 //----------Subtraction Instructions-------------------------------------------
7874 // Integer Subtraction Instructions
7875 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7876 match(Set dst (SubI dst src));
7877 effect(KILL cr);
7878
7879 size(2);
7880 format %{ "SUB $dst,$src" %}
7881 opcode(0x2B);
7882 ins_encode( OpcP, RegReg( dst, src) );
7883 ins_pipe( ialu_reg_reg );
7884 %}
7885
7886 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7887 match(Set dst (SubI dst src));
7888 effect(KILL cr);
7889
7890 format %{ "SUB $dst,$src" %}
7891 opcode(0x81,0x05); /* Opcode 81 /5 */
7892 // ins_encode( RegImm( dst, src) );
7893 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7894 ins_pipe( ialu_reg );
7895 %}
7896
7897 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7898 match(Set dst (SubI dst (LoadI src)));
7899 effect(KILL cr);
7900
7901 ins_cost(125);
7902 format %{ "SUB $dst,$src" %}
7903 opcode(0x2B);
7904 ins_encode( OpcP, RegMem( dst, src) );
7905 ins_pipe( ialu_reg_mem );
7906 %}
7907
7908 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7909 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7910 effect(KILL cr);
7911
7912 ins_cost(150);
7913 format %{ "SUB $dst,$src" %}
7914 opcode(0x29); /* Opcode 29 /r */
7915 ins_encode( OpcP, RegMem( src, dst ) );
7916 ins_pipe( ialu_mem_reg );
7917 %}
7918
7919 // Subtract from a pointer
7920 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7921 match(Set dst (AddP dst (SubI zero src)));
7922 effect(KILL cr);
7923
7924 size(2);
7925 format %{ "SUB $dst,$src" %}
7926 opcode(0x2B);
7927 ins_encode( OpcP, RegReg( dst, src) );
7928 ins_pipe( ialu_reg_reg );
7929 %}
7930
7931 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7932 match(Set dst (SubI zero dst));
7933 effect(KILL cr);
7934
7935 size(2);
7936 format %{ "NEG $dst" %}
7937 opcode(0xF7,0x03); // Opcode F7 /3
7938 ins_encode( OpcP, RegOpc( dst ) );
7939 ins_pipe( ialu_reg );
7940 %}
7941
7942
7943 //----------Multiplication/Division Instructions-------------------------------
7944 // Integer Multiplication Instructions
7945 // Multiply Register
7946 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7947 match(Set dst (MulI dst src));
7948 effect(KILL cr);
7949
7950 size(3);
7951 ins_cost(300);
7952 format %{ "IMUL $dst,$src" %}
7953 opcode(0xAF, 0x0F);
7954 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7955 ins_pipe( ialu_reg_reg_alu0 );
7956 %}
7957
7958 // Multiply 32-bit Immediate
7959 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7960 match(Set dst (MulI src imm));
7961 effect(KILL cr);
7962
7963 ins_cost(300);
7964 format %{ "IMUL $dst,$src,$imm" %}
7965 opcode(0x69); /* 69 /r id */
7966 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7967 ins_pipe( ialu_reg_reg_alu0 );
7968 %}
7969
7970 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7971 match(Set dst src);
7972 effect(KILL cr);
7973
7974 // Note that this is artificially increased to make it more expensive than loadConL
7975 ins_cost(250);
7976 format %{ "MOV EAX,$src\t// low word only" %}
7977 opcode(0xB8);
7978 ins_encode( LdImmL_Lo(dst, src) );
7979 ins_pipe( ialu_reg_fat );
7980 %}
7981
7982 // Multiply by 32-bit Immediate, taking the shifted high order results
7983 // (special case for shift by 32)
7984 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7985 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7986 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7987 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7988 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7989 effect(USE src1, KILL cr);
7990
7991 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7992 ins_cost(0*100 + 1*400 - 150);
7993 format %{ "IMUL EDX:EAX,$src1" %}
7994 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7995 ins_pipe( pipe_slow );
7996 %}
7997
7998 // Multiply by 32-bit Immediate, taking the shifted high order results
7999 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8000 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8001 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8002 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8003 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8004 effect(USE src1, KILL cr);
8005
8006 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8007 ins_cost(1*100 + 1*400 - 150);
8008 format %{ "IMUL EDX:EAX,$src1\n\t"
8009 "SAR EDX,$cnt-32" %}
8010 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8011 ins_pipe( pipe_slow );
8012 %}
8013
8014 // Multiply Memory 32-bit Immediate
8015 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
8016 match(Set dst (MulI (LoadI src) imm));
8017 effect(KILL cr);
8018
8019 ins_cost(300);
8020 format %{ "IMUL $dst,$src,$imm" %}
8021 opcode(0x69); /* 69 /r id */
8022 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8023 ins_pipe( ialu_reg_mem_alu0 );
8024 %}
8025
8026 // Multiply Memory
8027 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8028 match(Set dst (MulI dst (LoadI src)));
8029 effect(KILL cr);
8030
8031 ins_cost(350);
8032 format %{ "IMUL $dst,$src" %}
8033 opcode(0xAF, 0x0F);
8034 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8035 ins_pipe( ialu_reg_mem_alu0 );
8036 %}
8037
8038 // Multiply Register Int to Long
8039 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8040 // Basic Idea: long = (long)int * (long)int
8041 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8042 effect(DEF dst, USE src, USE src1, KILL flags);
8043
8044 ins_cost(300);
8045 format %{ "IMUL $dst,$src1" %}
8046
8047 ins_encode( long_int_multiply( dst, src1 ) );
8048 ins_pipe( ialu_reg_reg_alu0 );
8049 %}
8050
8051 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8052 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8053 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8054 effect(KILL flags);
8055
8056 ins_cost(300);
8057 format %{ "MUL $dst,$src1" %}
8058
8059 ins_encode( long_uint_multiply(dst, src1) );
8060 ins_pipe( ialu_reg_reg_alu0 );
8061 %}
8062
8063 // Multiply Register Long
8064 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8065 match(Set dst (MulL dst src));
8066 effect(KILL cr, TEMP tmp);
8067 ins_cost(4*100+3*400);
8068 // Basic idea: lo(result) = lo(x_lo * y_lo)
8069 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8070 format %{ "MOV $tmp,$src.lo\n\t"
8071 "IMUL $tmp,EDX\n\t"
8072 "MOV EDX,$src.hi\n\t"
8073 "IMUL EDX,EAX\n\t"
8074 "ADD $tmp,EDX\n\t"
8075 "MUL EDX:EAX,$src.lo\n\t"
8076 "ADD EDX,$tmp" %}
8077 ins_encode( long_multiply( dst, src, tmp ) );
8078 ins_pipe( pipe_slow );
8079 %}
8080
8081 // Multiply Register Long where the left operand's high 32 bits are zero
8082 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8083 predicate(is_operand_hi32_zero(n->in(1)));
8084 match(Set dst (MulL dst src));
8085 effect(KILL cr, TEMP tmp);
8086 ins_cost(2*100+2*400);
8087 // Basic idea: lo(result) = lo(x_lo * y_lo)
8088 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8089 format %{ "MOV $tmp,$src.hi\n\t"
8090 "IMUL $tmp,EAX\n\t"
8091 "MUL EDX:EAX,$src.lo\n\t"
8092 "ADD EDX,$tmp" %}
8093 ins_encode %{
8094 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8095 __ imull($tmp$$Register, rax);
8096 __ mull($src$$Register);
8097 __ addl(rdx, $tmp$$Register);
8098 %}
8099 ins_pipe( pipe_slow );
8100 %}
8101
8102 // Multiply Register Long where the right operand's high 32 bits are zero
8103 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8104 predicate(is_operand_hi32_zero(n->in(2)));
8105 match(Set dst (MulL dst src));
8106 effect(KILL cr, TEMP tmp);
8107 ins_cost(2*100+2*400);
8108 // Basic idea: lo(result) = lo(x_lo * y_lo)
8109 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8110 format %{ "MOV $tmp,$src.lo\n\t"
8111 "IMUL $tmp,EDX\n\t"
8112 "MUL EDX:EAX,$src.lo\n\t"
8113 "ADD EDX,$tmp" %}
8114 ins_encode %{
8115 __ movl($tmp$$Register, $src$$Register);
8116 __ imull($tmp$$Register, rdx);
8117 __ mull($src$$Register);
8118 __ addl(rdx, $tmp$$Register);
8119 %}
8120 ins_pipe( pipe_slow );
8121 %}
8122
8123 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8124 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8125 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8126 match(Set dst (MulL dst src));
8127 effect(KILL cr);
8128 ins_cost(1*400);
8129 // Basic idea: lo(result) = lo(x_lo * y_lo)
8130 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8131 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8132 ins_encode %{
8133 __ mull($src$$Register);
8134 %}
8135 ins_pipe( pipe_slow );
8136 %}
8137
8138 // Multiply Register Long by small constant
8139 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8140 match(Set dst (MulL dst src));
8141 effect(KILL cr, TEMP tmp);
8142 ins_cost(2*100+2*400);
8143 size(12);
8144 // Basic idea: lo(result) = lo(src * EAX)
8145 // hi(result) = hi(src * EAX) + lo(src * EDX)
8146 format %{ "IMUL $tmp,EDX,$src\n\t"
8147 "MOV EDX,$src\n\t"
8148 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8149 "ADD EDX,$tmp" %}
8150 ins_encode( long_multiply_con( dst, src, tmp ) );
8151 ins_pipe( pipe_slow );
8152 %}
8153
8154 // Integer DIV with Register
8155 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8156 match(Set rax (DivI rax div));
8157 effect(KILL rdx, KILL cr);
8158 size(26);
8159 ins_cost(30*100+10*100);
8160 format %{ "CMP EAX,0x80000000\n\t"
8161 "JNE,s normal\n\t"
8162 "XOR EDX,EDX\n\t"
8163 "CMP ECX,-1\n\t"
8164 "JE,s done\n"
8165 "normal: CDQ\n\t"
8166 "IDIV $div\n\t"
8167 "done:" %}
8168 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8169 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8170 ins_pipe( ialu_reg_reg_alu0 );
8171 %}
8172
8173 // Divide Register Long
8174 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8175 match(Set dst (DivL src1 src2));
8176 effect( KILL cr, KILL cx, KILL bx );
8177 ins_cost(10000);
8178 format %{ "PUSH $src1.hi\n\t"
8179 "PUSH $src1.lo\n\t"
8180 "PUSH $src2.hi\n\t"
8181 "PUSH $src2.lo\n\t"
8182 "CALL SharedRuntime::ldiv\n\t"
8183 "ADD ESP,16" %}
8184 ins_encode( long_div(src1,src2) );
8185 ins_pipe( pipe_slow );
8186 %}
8187
8188 // Integer DIVMOD with Register, both quotient and mod results
8189 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8190 match(DivModI rax div);
8191 effect(KILL cr);
8192 size(26);
8193 ins_cost(30*100+10*100);
8194 format %{ "CMP EAX,0x80000000\n\t"
8195 "JNE,s normal\n\t"
8196 "XOR EDX,EDX\n\t"
8197 "CMP ECX,-1\n\t"
8198 "JE,s done\n"
8199 "normal: CDQ\n\t"
8200 "IDIV $div\n\t"
8201 "done:" %}
8202 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8203 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8204 ins_pipe( pipe_slow );
8205 %}
8206
8207 // Integer MOD with Register
8208 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8209 match(Set rdx (ModI rax div));
8210 effect(KILL rax, KILL cr);
8211
8212 size(26);
8213 ins_cost(300);
8214 format %{ "CDQ\n\t"
8215 "IDIV $div" %}
8216 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8217 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8218 ins_pipe( ialu_reg_reg_alu0 );
8219 %}
8220
8221 // Remainder Register Long
8222 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8223 match(Set dst (ModL src1 src2));
8224 effect( KILL cr, KILL cx, KILL bx );
8225 ins_cost(10000);
8226 format %{ "PUSH $src1.hi\n\t"
8227 "PUSH $src1.lo\n\t"
8228 "PUSH $src2.hi\n\t"
8229 "PUSH $src2.lo\n\t"
8230 "CALL SharedRuntime::lrem\n\t"
8231 "ADD ESP,16" %}
8232 ins_encode( long_mod(src1,src2) );
8233 ins_pipe( pipe_slow );
8234 %}
8235
8236 // Divide Register Long (no special case since divisor != -1)
8237 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8238 match(Set dst (DivL dst imm));
8239 effect( TEMP tmp, TEMP tmp2, KILL cr );
8240 ins_cost(1000);
8241 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8242 "XOR $tmp2,$tmp2\n\t"
8243 "CMP $tmp,EDX\n\t"
8244 "JA,s fast\n\t"
8245 "MOV $tmp2,EAX\n\t"
8246 "MOV EAX,EDX\n\t"
8247 "MOV EDX,0\n\t"
8248 "JLE,s pos\n\t"
8249 "LNEG EAX : $tmp2\n\t"
8250 "DIV $tmp # unsigned division\n\t"
8251 "XCHG EAX,$tmp2\n\t"
8252 "DIV $tmp\n\t"
8253 "LNEG $tmp2 : EAX\n\t"
8254 "JMP,s done\n"
8255 "pos:\n\t"
8256 "DIV $tmp\n\t"
8257 "XCHG EAX,$tmp2\n"
8258 "fast:\n\t"
8259 "DIV $tmp\n"
8260 "done:\n\t"
8261 "MOV EDX,$tmp2\n\t"
8262 "NEG EDX:EAX # if $imm < 0" %}
8263 ins_encode %{
8264 int con = (int)$imm$$constant;
8265 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8266 int pcon = (con > 0) ? con : -con;
8267 Label Lfast, Lpos, Ldone;
8268
8269 __ movl($tmp$$Register, pcon);
8270 __ xorl($tmp2$$Register,$tmp2$$Register);
8271 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8272 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8273
8274 __ movl($tmp2$$Register, $dst$$Register); // save
8275 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8276 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8277 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8278
8279 // Negative dividend.
8280 // convert value to positive to use unsigned division
8281 __ lneg($dst$$Register, $tmp2$$Register);
8282 __ divl($tmp$$Register);
8283 __ xchgl($dst$$Register, $tmp2$$Register);
8284 __ divl($tmp$$Register);
8285 // revert result back to negative
8286 __ lneg($tmp2$$Register, $dst$$Register);
8287 __ jmpb(Ldone);
8288
8289 __ bind(Lpos);
8290 __ divl($tmp$$Register); // Use unsigned division
8291 __ xchgl($dst$$Register, $tmp2$$Register);
8292 // Fallthrow for final divide, tmp2 has 32 bit hi result
8293
8294 __ bind(Lfast);
8295 // fast path: src is positive
8296 __ divl($tmp$$Register); // Use unsigned division
8297
8298 __ bind(Ldone);
8299 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8300 if (con < 0) {
8301 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8302 }
8303 %}
8304 ins_pipe( pipe_slow );
8305 %}
8306
8307 // Remainder Register Long (remainder fit into 32 bits)
8308 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8309 match(Set dst (ModL dst imm));
8310 effect( TEMP tmp, TEMP tmp2, KILL cr );
8311 ins_cost(1000);
8312 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8313 "CMP $tmp,EDX\n\t"
8314 "JA,s fast\n\t"
8315 "MOV $tmp2,EAX\n\t"
8316 "MOV EAX,EDX\n\t"
8317 "MOV EDX,0\n\t"
8318 "JLE,s pos\n\t"
8319 "LNEG EAX : $tmp2\n\t"
8320 "DIV $tmp # unsigned division\n\t"
8321 "MOV EAX,$tmp2\n\t"
8322 "DIV $tmp\n\t"
8323 "NEG EDX\n\t"
8324 "JMP,s done\n"
8325 "pos:\n\t"
8326 "DIV $tmp\n\t"
8327 "MOV EAX,$tmp2\n"
8328 "fast:\n\t"
8329 "DIV $tmp\n"
8330 "done:\n\t"
8331 "MOV EAX,EDX\n\t"
8332 "SAR EDX,31\n\t" %}
8333 ins_encode %{
8334 int con = (int)$imm$$constant;
8335 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8336 int pcon = (con > 0) ? con : -con;
8337 Label Lfast, Lpos, Ldone;
8338
8339 __ movl($tmp$$Register, pcon);
8340 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8341 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8342
8343 __ movl($tmp2$$Register, $dst$$Register); // save
8344 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8345 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8346 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8347
8348 // Negative dividend.
8349 // convert value to positive to use unsigned division
8350 __ lneg($dst$$Register, $tmp2$$Register);
8351 __ divl($tmp$$Register);
8352 __ movl($dst$$Register, $tmp2$$Register);
8353 __ divl($tmp$$Register);
8354 // revert remainder back to negative
8355 __ negl(HIGH_FROM_LOW($dst$$Register));
8356 __ jmpb(Ldone);
8357
8358 __ bind(Lpos);
8359 __ divl($tmp$$Register);
8360 __ movl($dst$$Register, $tmp2$$Register);
8361
8362 __ bind(Lfast);
8363 // fast path: src is positive
8364 __ divl($tmp$$Register);
8365
8366 __ bind(Ldone);
8367 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8368 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8369
8370 %}
8371 ins_pipe( pipe_slow );
8372 %}
8373
8374 // Integer Shift Instructions
8375 // Shift Left by one
8376 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8377 match(Set dst (LShiftI dst shift));
8378 effect(KILL cr);
8379
8380 size(2);
8381 format %{ "SHL $dst,$shift" %}
8382 opcode(0xD1, 0x4); /* D1 /4 */
8383 ins_encode( OpcP, RegOpc( dst ) );
8384 ins_pipe( ialu_reg );
8385 %}
8386
8387 // Shift Left by 8-bit immediate
8388 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8389 match(Set dst (LShiftI dst shift));
8390 effect(KILL cr);
8391
8392 size(3);
8393 format %{ "SHL $dst,$shift" %}
8394 opcode(0xC1, 0x4); /* C1 /4 ib */
8395 ins_encode( RegOpcImm( dst, shift) );
8396 ins_pipe( ialu_reg );
8397 %}
8398
8399 // Shift Left by variable
8400 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8401 match(Set dst (LShiftI dst shift));
8402 effect(KILL cr);
8403
8404 size(2);
8405 format %{ "SHL $dst,$shift" %}
8406 opcode(0xD3, 0x4); /* D3 /4 */
8407 ins_encode( OpcP, RegOpc( dst ) );
8408 ins_pipe( ialu_reg_reg );
8409 %}
8410
8411 // Arithmetic shift right by one
8412 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8413 match(Set dst (RShiftI dst shift));
8414 effect(KILL cr);
8415
8416 size(2);
8417 format %{ "SAR $dst,$shift" %}
8418 opcode(0xD1, 0x7); /* D1 /7 */
8419 ins_encode( OpcP, RegOpc( dst ) );
8420 ins_pipe( ialu_reg );
8421 %}
8422
8423 // Arithmetic shift right by one
8424 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8425 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8426 effect(KILL cr);
8427 format %{ "SAR $dst,$shift" %}
8428 opcode(0xD1, 0x7); /* D1 /7 */
8429 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8430 ins_pipe( ialu_mem_imm );
8431 %}
8432
8433 // Arithmetic Shift Right by 8-bit immediate
8434 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8435 match(Set dst (RShiftI dst shift));
8436 effect(KILL cr);
8437
8438 size(3);
8439 format %{ "SAR $dst,$shift" %}
8440 opcode(0xC1, 0x7); /* C1 /7 ib */
8441 ins_encode( RegOpcImm( dst, shift ) );
8442 ins_pipe( ialu_mem_imm );
8443 %}
8444
8445 // Arithmetic Shift Right by 8-bit immediate
8446 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8447 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8448 effect(KILL cr);
8449
8450 format %{ "SAR $dst,$shift" %}
8451 opcode(0xC1, 0x7); /* C1 /7 ib */
8452 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8453 ins_pipe( ialu_mem_imm );
8454 %}
8455
8456 // Arithmetic Shift Right by variable
8457 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8458 match(Set dst (RShiftI dst shift));
8459 effect(KILL cr);
8460
8461 size(2);
8462 format %{ "SAR $dst,$shift" %}
8463 opcode(0xD3, 0x7); /* D3 /7 */
8464 ins_encode( OpcP, RegOpc( dst ) );
8465 ins_pipe( ialu_reg_reg );
8466 %}
8467
8468 // Logical shift right by one
8469 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8470 match(Set dst (URShiftI dst shift));
8471 effect(KILL cr);
8472
8473 size(2);
8474 format %{ "SHR $dst,$shift" %}
8475 opcode(0xD1, 0x5); /* D1 /5 */
8476 ins_encode( OpcP, RegOpc( dst ) );
8477 ins_pipe( ialu_reg );
8478 %}
8479
8480 // Logical Shift Right by 8-bit immediate
8481 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8482 match(Set dst (URShiftI dst shift));
8483 effect(KILL cr);
8484
8485 size(3);
8486 format %{ "SHR $dst,$shift" %}
8487 opcode(0xC1, 0x5); /* C1 /5 ib */
8488 ins_encode( RegOpcImm( dst, shift) );
8489 ins_pipe( ialu_reg );
8490 %}
8491
8492
8493 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8494 // This idiom is used by the compiler for the i2b bytecode.
8495 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8496 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8497
8498 size(3);
8499 format %{ "MOVSX $dst,$src :8" %}
8500 ins_encode %{
8501 __ movsbl($dst$$Register, $src$$Register);
8502 %}
8503 ins_pipe(ialu_reg_reg);
8504 %}
8505
8506 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8507 // This idiom is used by the compiler the i2s bytecode.
8508 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8509 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8510
8511 size(3);
8512 format %{ "MOVSX $dst,$src :16" %}
8513 ins_encode %{
8514 __ movswl($dst$$Register, $src$$Register);
8515 %}
8516 ins_pipe(ialu_reg_reg);
8517 %}
8518
8519
8520 // Logical Shift Right by variable
8521 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8522 match(Set dst (URShiftI dst shift));
8523 effect(KILL cr);
8524
8525 size(2);
8526 format %{ "SHR $dst,$shift" %}
8527 opcode(0xD3, 0x5); /* D3 /5 */
8528 ins_encode( OpcP, RegOpc( dst ) );
8529 ins_pipe( ialu_reg_reg );
8530 %}
8531
8532
8533 //----------Logical Instructions-----------------------------------------------
8534 //----------Integer Logical Instructions---------------------------------------
8535 // And Instructions
8536 // And Register with Register
8537 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8538 match(Set dst (AndI dst src));
8539 effect(KILL cr);
8540
8541 size(2);
8542 format %{ "AND $dst,$src" %}
8543 opcode(0x23);
8544 ins_encode( OpcP, RegReg( dst, src) );
8545 ins_pipe( ialu_reg_reg );
8546 %}
8547
8548 // And Register with Immediate
8549 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8550 match(Set dst (AndI dst src));
8551 effect(KILL cr);
8552
8553 format %{ "AND $dst,$src" %}
8554 opcode(0x81,0x04); /* Opcode 81 /4 */
8555 // ins_encode( RegImm( dst, src) );
8556 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8557 ins_pipe( ialu_reg );
8558 %}
8559
8560 // And Register with Memory
8561 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8562 match(Set dst (AndI dst (LoadI src)));
8563 effect(KILL cr);
8564
8565 ins_cost(125);
8566 format %{ "AND $dst,$src" %}
8567 opcode(0x23);
8568 ins_encode( OpcP, RegMem( dst, src) );
8569 ins_pipe( ialu_reg_mem );
8570 %}
8571
8572 // And Memory with Register
8573 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8574 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8575 effect(KILL cr);
8576
8577 ins_cost(150);
8578 format %{ "AND $dst,$src" %}
8579 opcode(0x21); /* Opcode 21 /r */
8580 ins_encode( OpcP, RegMem( src, dst ) );
8581 ins_pipe( ialu_mem_reg );
8582 %}
8583
8584 // And Memory with Immediate
8585 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8586 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8587 effect(KILL cr);
8588
8589 ins_cost(125);
8590 format %{ "AND $dst,$src" %}
8591 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8592 // ins_encode( MemImm( dst, src) );
8593 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8594 ins_pipe( ialu_mem_imm );
8595 %}
8596
8597 // Or Instructions
8598 // Or Register with Register
8599 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8600 match(Set dst (OrI dst src));
8601 effect(KILL cr);
8602
8603 size(2);
8604 format %{ "OR $dst,$src" %}
8605 opcode(0x0B);
8606 ins_encode( OpcP, RegReg( dst, src) );
8607 ins_pipe( ialu_reg_reg );
8608 %}
8609
8610 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8611 match(Set dst (OrI dst (CastP2X src)));
8612 effect(KILL cr);
8613
8614 size(2);
8615 format %{ "OR $dst,$src" %}
8616 opcode(0x0B);
8617 ins_encode( OpcP, RegReg( dst, src) );
8618 ins_pipe( ialu_reg_reg );
8619 %}
8620
8621
8622 // Or Register with Immediate
8623 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8624 match(Set dst (OrI dst src));
8625 effect(KILL cr);
8626
8627 format %{ "OR $dst,$src" %}
8628 opcode(0x81,0x01); /* Opcode 81 /1 id */
8629 // ins_encode( RegImm( dst, src) );
8630 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8631 ins_pipe( ialu_reg );
8632 %}
8633
8634 // Or Register with Memory
8635 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8636 match(Set dst (OrI dst (LoadI src)));
8637 effect(KILL cr);
8638
8639 ins_cost(125);
8640 format %{ "OR $dst,$src" %}
8641 opcode(0x0B);
8642 ins_encode( OpcP, RegMem( dst, src) );
8643 ins_pipe( ialu_reg_mem );
8644 %}
8645
8646 // Or Memory with Register
8647 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8648 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8649 effect(KILL cr);
8650
8651 ins_cost(150);
8652 format %{ "OR $dst,$src" %}
8653 opcode(0x09); /* Opcode 09 /r */
8654 ins_encode( OpcP, RegMem( src, dst ) );
8655 ins_pipe( ialu_mem_reg );
8656 %}
8657
8658 // Or Memory with Immediate
8659 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8660 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8661 effect(KILL cr);
8662
8663 ins_cost(125);
8664 format %{ "OR $dst,$src" %}
8665 opcode(0x81,0x1); /* Opcode 81 /1 id */
8666 // ins_encode( MemImm( dst, src) );
8667 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8668 ins_pipe( ialu_mem_imm );
8669 %}
8670
8671 // ROL/ROR
8672 // ROL expand
8673 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8674 effect(USE_DEF dst, USE shift, KILL cr);
8675
8676 format %{ "ROL $dst, $shift" %}
8677 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8678 ins_encode( OpcP, RegOpc( dst ));
8679 ins_pipe( ialu_reg );
8680 %}
8681
8682 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8683 effect(USE_DEF dst, USE shift, KILL cr);
8684
8685 format %{ "ROL $dst, $shift" %}
8686 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8687 ins_encode( RegOpcImm(dst, shift) );
8688 ins_pipe(ialu_reg);
8689 %}
8690
8691 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8692 effect(USE_DEF dst, USE shift, KILL cr);
8693
8694 format %{ "ROL $dst, $shift" %}
8695 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8696 ins_encode(OpcP, RegOpc(dst));
8697 ins_pipe( ialu_reg_reg );
8698 %}
8699 // end of ROL expand
8700
8701 // ROL 32bit by one once
8702 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8703 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8704
8705 expand %{
8706 rolI_eReg_imm1(dst, lshift, cr);
8707 %}
8708 %}
8709
8710 // ROL 32bit var by imm8 once
8711 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8712 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8713 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8714
8715 expand %{
8716 rolI_eReg_imm8(dst, lshift, cr);
8717 %}
8718 %}
8719
8720 // ROL 32bit var by var once
8721 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8722 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8723
8724 expand %{
8725 rolI_eReg_CL(dst, shift, cr);
8726 %}
8727 %}
8728
8729 // ROL 32bit var by var once
8730 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8731 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8732
8733 expand %{
8734 rolI_eReg_CL(dst, shift, cr);
8735 %}
8736 %}
8737
8738 // ROR expand
8739 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8740 effect(USE_DEF dst, USE shift, KILL cr);
8741
8742 format %{ "ROR $dst, $shift" %}
8743 opcode(0xD1,0x1); /* Opcode D1 /1 */
8744 ins_encode( OpcP, RegOpc( dst ) );
8745 ins_pipe( ialu_reg );
8746 %}
8747
8748 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8749 effect (USE_DEF dst, USE shift, KILL cr);
8750
8751 format %{ "ROR $dst, $shift" %}
8752 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8753 ins_encode( RegOpcImm(dst, shift) );
8754 ins_pipe( ialu_reg );
8755 %}
8756
8757 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8758 effect(USE_DEF dst, USE shift, KILL cr);
8759
8760 format %{ "ROR $dst, $shift" %}
8761 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8762 ins_encode(OpcP, RegOpc(dst));
8763 ins_pipe( ialu_reg_reg );
8764 %}
8765 // end of ROR expand
8766
8767 // ROR right once
8768 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8769 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8770
8771 expand %{
8772 rorI_eReg_imm1(dst, rshift, cr);
8773 %}
8774 %}
8775
8776 // ROR 32bit by immI8 once
8777 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8778 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8779 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8780
8781 expand %{
8782 rorI_eReg_imm8(dst, rshift, cr);
8783 %}
8784 %}
8785
8786 // ROR 32bit var by var once
8787 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8788 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8789
8790 expand %{
8791 rorI_eReg_CL(dst, shift, cr);
8792 %}
8793 %}
8794
8795 // ROR 32bit var by var once
8796 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8797 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8798
8799 expand %{
8800 rorI_eReg_CL(dst, shift, cr);
8801 %}
8802 %}
8803
8804 // Xor Instructions
8805 // Xor Register with Register
8806 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8807 match(Set dst (XorI dst src));
8808 effect(KILL cr);
8809
8810 size(2);
8811 format %{ "XOR $dst,$src" %}
8812 opcode(0x33);
8813 ins_encode( OpcP, RegReg( dst, src) );
8814 ins_pipe( ialu_reg_reg );
8815 %}
8816
8817 // Xor Register with Immediate -1
8818 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8819 match(Set dst (XorI dst imm));
8820
8821 size(2);
8822 format %{ "NOT $dst" %}
8823 ins_encode %{
8824 __ notl($dst$$Register);
8825 %}
8826 ins_pipe( ialu_reg );
8827 %}
8828
8829 // Xor Register with Immediate
8830 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8831 match(Set dst (XorI dst src));
8832 effect(KILL cr);
8833
8834 format %{ "XOR $dst,$src" %}
8835 opcode(0x81,0x06); /* Opcode 81 /6 id */
8836 // ins_encode( RegImm( dst, src) );
8837 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8838 ins_pipe( ialu_reg );
8839 %}
8840
8841 // Xor Register with Memory
8842 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8843 match(Set dst (XorI dst (LoadI src)));
8844 effect(KILL cr);
8845
8846 ins_cost(125);
8847 format %{ "XOR $dst,$src" %}
8848 opcode(0x33);
8849 ins_encode( OpcP, RegMem(dst, src) );
8850 ins_pipe( ialu_reg_mem );
8851 %}
8852
8853 // Xor Memory with Register
8854 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8855 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8856 effect(KILL cr);
8857
8858 ins_cost(150);
8859 format %{ "XOR $dst,$src" %}
8860 opcode(0x31); /* Opcode 31 /r */
8861 ins_encode( OpcP, RegMem( src, dst ) );
8862 ins_pipe( ialu_mem_reg );
8863 %}
8864
8865 // Xor Memory with Immediate
8866 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8867 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8868 effect(KILL cr);
8869
8870 ins_cost(125);
8871 format %{ "XOR $dst,$src" %}
8872 opcode(0x81,0x6); /* Opcode 81 /6 id */
8873 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8874 ins_pipe( ialu_mem_imm );
8875 %}
8876
8877 //----------Convert Int to Boolean---------------------------------------------
8878
8879 instruct movI_nocopy(rRegI dst, rRegI src) %{
8880 effect( DEF dst, USE src );
8881 format %{ "MOV $dst,$src" %}
8882 ins_encode( enc_Copy( dst, src) );
8883 ins_pipe( ialu_reg_reg );
8884 %}
8885
8886 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8887 effect( USE_DEF dst, USE src, KILL cr );
8888
8889 size(4);
8890 format %{ "NEG $dst\n\t"
8891 "ADC $dst,$src" %}
8892 ins_encode( neg_reg(dst),
8893 OpcRegReg(0x13,dst,src) );
8894 ins_pipe( ialu_reg_reg_long );
8895 %}
8896
8897 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8898 match(Set dst (Conv2B src));
8899
8900 expand %{
8901 movI_nocopy(dst,src);
8902 ci2b(dst,src,cr);
8903 %}
8904 %}
8905
8906 instruct movP_nocopy(rRegI dst, eRegP src) %{
8907 effect( DEF dst, USE src );
8908 format %{ "MOV $dst,$src" %}
8909 ins_encode( enc_Copy( dst, src) );
8910 ins_pipe( ialu_reg_reg );
8911 %}
8912
8913 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8914 effect( USE_DEF dst, USE src, KILL cr );
8915 format %{ "NEG $dst\n\t"
8916 "ADC $dst,$src" %}
8917 ins_encode( neg_reg(dst),
8918 OpcRegReg(0x13,dst,src) );
8919 ins_pipe( ialu_reg_reg_long );
8920 %}
8921
8922 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8923 match(Set dst (Conv2B src));
8924
8925 expand %{
8926 movP_nocopy(dst,src);
8927 cp2b(dst,src,cr);
8928 %}
8929 %}
8930
8931 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8932 match(Set dst (CmpLTMask p q));
8933 effect( KILL cr );
8934 ins_cost(400);
8935
8936 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8937 format %{ "XOR $dst,$dst\n\t"
8938 "CMP $p,$q\n\t"
8939 "SETlt $dst\n\t"
8940 "NEG $dst" %}
8941 ins_encode( OpcRegReg(0x33,dst,dst),
8942 OpcRegReg(0x3B,p,q),
8943 setLT_reg(dst), neg_reg(dst) );
8944 ins_pipe( pipe_slow );
8945 %}
8946
8947 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
8948 match(Set dst (CmpLTMask dst zero));
8949 effect( DEF dst, KILL cr );
8950 ins_cost(100);
8951
8952 format %{ "SAR $dst,31" %}
8953 opcode(0xC1, 0x7); /* C1 /7 ib */
8954 ins_encode( RegOpcImm( dst, 0x1F ) );
8955 ins_pipe( ialu_reg );
8956 %}
8957
8958
8959 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8960 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8961 effect( KILL tmp, KILL cr );
8962 ins_cost(400);
8963 // annoyingly, $tmp has no edges so you cant ask for it in
8964 // any format or encoding
8965 format %{ "SUB $p,$q\n\t"
8966 "SBB ECX,ECX\n\t"
8967 "AND ECX,$y\n\t"
8968 "ADD $p,ECX" %}
8969 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8970 ins_pipe( pipe_cmplt );
8971 %}
8972
8973 /* If I enable this, I encourage spilling in the inner loop of compress.
8974 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8975 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8976 effect( USE_KILL tmp, KILL cr );
8977 ins_cost(400);
8978
8979 format %{ "SUB $p,$q\n\t"
8980 "SBB ECX,ECX\n\t"
8981 "AND ECX,$y\n\t"
8982 "ADD $p,ECX" %}
8983 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8984 %}
8985 */
8986
8987 //----------Long Instructions------------------------------------------------
8988 // Add Long Register with Register
8989 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8990 match(Set dst (AddL dst src));
8991 effect(KILL cr);
8992 ins_cost(200);
8993 format %{ "ADD $dst.lo,$src.lo\n\t"
8994 "ADC $dst.hi,$src.hi" %}
8995 opcode(0x03, 0x13);
8996 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8997 ins_pipe( ialu_reg_reg_long );
8998 %}
8999
9000 // Add Long Register with Immediate
9001 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9002 match(Set dst (AddL dst src));
9003 effect(KILL cr);
9004 format %{ "ADD $dst.lo,$src.lo\n\t"
9005 "ADC $dst.hi,$src.hi" %}
9006 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9007 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9008 ins_pipe( ialu_reg_long );
9009 %}
9010
9011 // Add Long Register with Memory
9012 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9013 match(Set dst (AddL dst (LoadL mem)));
9014 effect(KILL cr);
9015 ins_cost(125);
9016 format %{ "ADD $dst.lo,$mem\n\t"
9017 "ADC $dst.hi,$mem+4" %}
9018 opcode(0x03, 0x13);
9019 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9020 ins_pipe( ialu_reg_long_mem );
9021 %}
9022
9023 // Subtract Long Register with Register.
9024 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9025 match(Set dst (SubL dst src));
9026 effect(KILL cr);
9027 ins_cost(200);
9028 format %{ "SUB $dst.lo,$src.lo\n\t"
9029 "SBB $dst.hi,$src.hi" %}
9030 opcode(0x2B, 0x1B);
9031 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9032 ins_pipe( ialu_reg_reg_long );
9033 %}
9034
9035 // Subtract Long Register with Immediate
9036 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9037 match(Set dst (SubL dst src));
9038 effect(KILL cr);
9039 format %{ "SUB $dst.lo,$src.lo\n\t"
9040 "SBB $dst.hi,$src.hi" %}
9041 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9042 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9043 ins_pipe( ialu_reg_long );
9044 %}
9045
9046 // Subtract Long Register with Memory
9047 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9048 match(Set dst (SubL dst (LoadL mem)));
9049 effect(KILL cr);
9050 ins_cost(125);
9051 format %{ "SUB $dst.lo,$mem\n\t"
9052 "SBB $dst.hi,$mem+4" %}
9053 opcode(0x2B, 0x1B);
9054 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9055 ins_pipe( ialu_reg_long_mem );
9056 %}
9057
9058 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9059 match(Set dst (SubL zero dst));
9060 effect(KILL cr);
9061 ins_cost(300);
9062 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9063 ins_encode( neg_long(dst) );
9064 ins_pipe( ialu_reg_reg_long );
9065 %}
9066
9067 // And Long Register with Register
9068 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9069 match(Set dst (AndL dst src));
9070 effect(KILL cr);
9071 format %{ "AND $dst.lo,$src.lo\n\t"
9072 "AND $dst.hi,$src.hi" %}
9073 opcode(0x23,0x23);
9074 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9075 ins_pipe( ialu_reg_reg_long );
9076 %}
9077
9078 // And Long Register with Immediate
9079 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9080 match(Set dst (AndL dst src));
9081 effect(KILL cr);
9082 format %{ "AND $dst.lo,$src.lo\n\t"
9083 "AND $dst.hi,$src.hi" %}
9084 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9085 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9086 ins_pipe( ialu_reg_long );
9087 %}
9088
9089 // And Long Register with Memory
9090 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9091 match(Set dst (AndL dst (LoadL mem)));
9092 effect(KILL cr);
9093 ins_cost(125);
9094 format %{ "AND $dst.lo,$mem\n\t"
9095 "AND $dst.hi,$mem+4" %}
9096 opcode(0x23, 0x23);
9097 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9098 ins_pipe( ialu_reg_long_mem );
9099 %}
9100
9101 // Or Long Register with Register
9102 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9103 match(Set dst (OrL dst src));
9104 effect(KILL cr);
9105 format %{ "OR $dst.lo,$src.lo\n\t"
9106 "OR $dst.hi,$src.hi" %}
9107 opcode(0x0B,0x0B);
9108 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9109 ins_pipe( ialu_reg_reg_long );
9110 %}
9111
9112 // Or Long Register with Immediate
9113 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9114 match(Set dst (OrL dst src));
9115 effect(KILL cr);
9116 format %{ "OR $dst.lo,$src.lo\n\t"
9117 "OR $dst.hi,$src.hi" %}
9118 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9119 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9120 ins_pipe( ialu_reg_long );
9121 %}
9122
9123 // Or Long Register with Memory
9124 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9125 match(Set dst (OrL dst (LoadL mem)));
9126 effect(KILL cr);
9127 ins_cost(125);
9128 format %{ "OR $dst.lo,$mem\n\t"
9129 "OR $dst.hi,$mem+4" %}
9130 opcode(0x0B,0x0B);
9131 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9132 ins_pipe( ialu_reg_long_mem );
9133 %}
9134
9135 // Xor Long Register with Register
9136 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9137 match(Set dst (XorL dst src));
9138 effect(KILL cr);
9139 format %{ "XOR $dst.lo,$src.lo\n\t"
9140 "XOR $dst.hi,$src.hi" %}
9141 opcode(0x33,0x33);
9142 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9143 ins_pipe( ialu_reg_reg_long );
9144 %}
9145
9146 // Xor Long Register with Immediate -1
9147 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9148 match(Set dst (XorL dst imm));
9149 format %{ "NOT $dst.lo\n\t"
9150 "NOT $dst.hi" %}
9151 ins_encode %{
9152 __ notl($dst$$Register);
9153 __ notl(HIGH_FROM_LOW($dst$$Register));
9154 %}
9155 ins_pipe( ialu_reg_long );
9156 %}
9157
9158 // Xor Long Register with Immediate
9159 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9160 match(Set dst (XorL dst src));
9161 effect(KILL cr);
9162 format %{ "XOR $dst.lo,$src.lo\n\t"
9163 "XOR $dst.hi,$src.hi" %}
9164 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9165 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9166 ins_pipe( ialu_reg_long );
9167 %}
9168
9169 // Xor Long Register with Memory
9170 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9171 match(Set dst (XorL dst (LoadL mem)));
9172 effect(KILL cr);
9173 ins_cost(125);
9174 format %{ "XOR $dst.lo,$mem\n\t"
9175 "XOR $dst.hi,$mem+4" %}
9176 opcode(0x33,0x33);
9177 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9178 ins_pipe( ialu_reg_long_mem );
9179 %}
9180
9181 // Shift Left Long by 1
9182 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9183 predicate(UseNewLongLShift);
9184 match(Set dst (LShiftL dst cnt));
9185 effect(KILL cr);
9186 ins_cost(100);
9187 format %{ "ADD $dst.lo,$dst.lo\n\t"
9188 "ADC $dst.hi,$dst.hi" %}
9189 ins_encode %{
9190 __ addl($dst$$Register,$dst$$Register);
9191 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9192 %}
9193 ins_pipe( ialu_reg_long );
9194 %}
9195
9196 // Shift Left Long by 2
9197 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9198 predicate(UseNewLongLShift);
9199 match(Set dst (LShiftL dst cnt));
9200 effect(KILL cr);
9201 ins_cost(100);
9202 format %{ "ADD $dst.lo,$dst.lo\n\t"
9203 "ADC $dst.hi,$dst.hi\n\t"
9204 "ADD $dst.lo,$dst.lo\n\t"
9205 "ADC $dst.hi,$dst.hi" %}
9206 ins_encode %{
9207 __ addl($dst$$Register,$dst$$Register);
9208 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9209 __ addl($dst$$Register,$dst$$Register);
9210 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9211 %}
9212 ins_pipe( ialu_reg_long );
9213 %}
9214
9215 // Shift Left Long by 3
9216 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9217 predicate(UseNewLongLShift);
9218 match(Set dst (LShiftL dst cnt));
9219 effect(KILL cr);
9220 ins_cost(100);
9221 format %{ "ADD $dst.lo,$dst.lo\n\t"
9222 "ADC $dst.hi,$dst.hi\n\t"
9223 "ADD $dst.lo,$dst.lo\n\t"
9224 "ADC $dst.hi,$dst.hi\n\t"
9225 "ADD $dst.lo,$dst.lo\n\t"
9226 "ADC $dst.hi,$dst.hi" %}
9227 ins_encode %{
9228 __ addl($dst$$Register,$dst$$Register);
9229 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9230 __ addl($dst$$Register,$dst$$Register);
9231 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9232 __ addl($dst$$Register,$dst$$Register);
9233 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9234 %}
9235 ins_pipe( ialu_reg_long );
9236 %}
9237
9238 // Shift Left Long by 1-31
9239 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9240 match(Set dst (LShiftL dst cnt));
9241 effect(KILL cr);
9242 ins_cost(200);
9243 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9244 "SHL $dst.lo,$cnt" %}
9245 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9246 ins_encode( move_long_small_shift(dst,cnt) );
9247 ins_pipe( ialu_reg_long );
9248 %}
9249
9250 // Shift Left Long by 32-63
9251 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9252 match(Set dst (LShiftL dst cnt));
9253 effect(KILL cr);
9254 ins_cost(300);
9255 format %{ "MOV $dst.hi,$dst.lo\n"
9256 "\tSHL $dst.hi,$cnt-32\n"
9257 "\tXOR $dst.lo,$dst.lo" %}
9258 opcode(0xC1, 0x4); /* C1 /4 ib */
9259 ins_encode( move_long_big_shift_clr(dst,cnt) );
9260 ins_pipe( ialu_reg_long );
9261 %}
9262
9263 // Shift Left Long by variable
9264 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9265 match(Set dst (LShiftL dst shift));
9266 effect(KILL cr);
9267 ins_cost(500+200);
9268 size(17);
9269 format %{ "TEST $shift,32\n\t"
9270 "JEQ,s small\n\t"
9271 "MOV $dst.hi,$dst.lo\n\t"
9272 "XOR $dst.lo,$dst.lo\n"
9273 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9274 "SHL $dst.lo,$shift" %}
9275 ins_encode( shift_left_long( dst, shift ) );
9276 ins_pipe( pipe_slow );
9277 %}
9278
9279 // Shift Right Long by 1-31
9280 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9281 match(Set dst (URShiftL dst cnt));
9282 effect(KILL cr);
9283 ins_cost(200);
9284 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9285 "SHR $dst.hi,$cnt" %}
9286 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9287 ins_encode( move_long_small_shift(dst,cnt) );
9288 ins_pipe( ialu_reg_long );
9289 %}
9290
9291 // Shift Right Long by 32-63
9292 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9293 match(Set dst (URShiftL dst cnt));
9294 effect(KILL cr);
9295 ins_cost(300);
9296 format %{ "MOV $dst.lo,$dst.hi\n"
9297 "\tSHR $dst.lo,$cnt-32\n"
9298 "\tXOR $dst.hi,$dst.hi" %}
9299 opcode(0xC1, 0x5); /* C1 /5 ib */
9300 ins_encode( move_long_big_shift_clr(dst,cnt) );
9301 ins_pipe( ialu_reg_long );
9302 %}
9303
9304 // Shift Right Long by variable
9305 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9306 match(Set dst (URShiftL dst shift));
9307 effect(KILL cr);
9308 ins_cost(600);
9309 size(17);
9310 format %{ "TEST $shift,32\n\t"
9311 "JEQ,s small\n\t"
9312 "MOV $dst.lo,$dst.hi\n\t"
9313 "XOR $dst.hi,$dst.hi\n"
9314 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9315 "SHR $dst.hi,$shift" %}
9316 ins_encode( shift_right_long( dst, shift ) );
9317 ins_pipe( pipe_slow );
9318 %}
9319
9320 // Shift Right Long by 1-31
9321 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9322 match(Set dst (RShiftL dst cnt));
9323 effect(KILL cr);
9324 ins_cost(200);
9325 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9326 "SAR $dst.hi,$cnt" %}
9327 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9328 ins_encode( move_long_small_shift(dst,cnt) );
9329 ins_pipe( ialu_reg_long );
9330 %}
9331
9332 // Shift Right Long by 32-63
9333 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9334 match(Set dst (RShiftL dst cnt));
9335 effect(KILL cr);
9336 ins_cost(300);
9337 format %{ "MOV $dst.lo,$dst.hi\n"
9338 "\tSAR $dst.lo,$cnt-32\n"
9339 "\tSAR $dst.hi,31" %}
9340 opcode(0xC1, 0x7); /* C1 /7 ib */
9341 ins_encode( move_long_big_shift_sign(dst,cnt) );
9342 ins_pipe( ialu_reg_long );
9343 %}
9344
9345 // Shift Right arithmetic Long by variable
9346 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9347 match(Set dst (RShiftL dst shift));
9348 effect(KILL cr);
9349 ins_cost(600);
9350 size(18);
9351 format %{ "TEST $shift,32\n\t"
9352 "JEQ,s small\n\t"
9353 "MOV $dst.lo,$dst.hi\n\t"
9354 "SAR $dst.hi,31\n"
9355 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9356 "SAR $dst.hi,$shift" %}
9357 ins_encode( shift_right_arith_long( dst, shift ) );
9358 ins_pipe( pipe_slow );
9359 %}
9360
9361
9362 //----------Double Instructions------------------------------------------------
9363 // Double Math
9364
9365 // Compare & branch
9366
9367 // P6 version of float compare, sets condition codes in EFLAGS
9368 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9369 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9370 match(Set cr (CmpD src1 src2));
9371 effect(KILL rax);
9372 ins_cost(150);
9373 format %{ "FLD $src1\n\t"
9374 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9375 "JNP exit\n\t"
9376 "MOV ah,1 // saw a NaN, set CF\n\t"
9377 "SAHF\n"
9378 "exit:\tNOP // avoid branch to branch" %}
9379 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9380 ins_encode( Push_Reg_DPR(src1),
9381 OpcP, RegOpc(src2),
9382 cmpF_P6_fixup );
9383 ins_pipe( pipe_slow );
9384 %}
9385
9386 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9387 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9388 match(Set cr (CmpD src1 src2));
9389 ins_cost(150);
9390 format %{ "FLD $src1\n\t"
9391 "FUCOMIP ST,$src2 // P6 instruction" %}
9392 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9393 ins_encode( Push_Reg_DPR(src1),
9394 OpcP, RegOpc(src2));
9395 ins_pipe( pipe_slow );
9396 %}
9397
9398 // Compare & branch
9399 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9400 predicate(UseSSE<=1);
9401 match(Set cr (CmpD src1 src2));
9402 effect(KILL rax);
9403 ins_cost(200);
9404 format %{ "FLD $src1\n\t"
9405 "FCOMp $src2\n\t"
9406 "FNSTSW AX\n\t"
9407 "TEST AX,0x400\n\t"
9408 "JZ,s flags\n\t"
9409 "MOV AH,1\t# unordered treat as LT\n"
9410 "flags:\tSAHF" %}
9411 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9412 ins_encode( Push_Reg_DPR(src1),
9413 OpcP, RegOpc(src2),
9414 fpu_flags);
9415 ins_pipe( pipe_slow );
9416 %}
9417
9418 // Compare vs zero into -1,0,1
9419 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9420 predicate(UseSSE<=1);
9421 match(Set dst (CmpD3 src1 zero));
9422 effect(KILL cr, KILL rax);
9423 ins_cost(280);
9424 format %{ "FTSTD $dst,$src1" %}
9425 opcode(0xE4, 0xD9);
9426 ins_encode( Push_Reg_DPR(src1),
9427 OpcS, OpcP, PopFPU,
9428 CmpF_Result(dst));
9429 ins_pipe( pipe_slow );
9430 %}
9431
9432 // Compare into -1,0,1
9433 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9434 predicate(UseSSE<=1);
9435 match(Set dst (CmpD3 src1 src2));
9436 effect(KILL cr, KILL rax);
9437 ins_cost(300);
9438 format %{ "FCMPD $dst,$src1,$src2" %}
9439 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9440 ins_encode( Push_Reg_DPR(src1),
9441 OpcP, RegOpc(src2),
9442 CmpF_Result(dst));
9443 ins_pipe( pipe_slow );
9444 %}
9445
9446 // float compare and set condition codes in EFLAGS by XMM regs
9447 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9448 predicate(UseSSE>=2);
9449 match(Set cr (CmpD src1 src2));
9450 ins_cost(145);
9451 format %{ "UCOMISD $src1,$src2\n\t"
9452 "JNP,s exit\n\t"
9453 "PUSHF\t# saw NaN, set CF\n\t"
9454 "AND [rsp], #0xffffff2b\n\t"
9455 "POPF\n"
9456 "exit:" %}
9457 ins_encode %{
9458 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9459 emit_cmpfp_fixup(_masm);
9460 %}
9461 ins_pipe( pipe_slow );
9462 %}
9463
9464 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9465 predicate(UseSSE>=2);
9466 match(Set cr (CmpD src1 src2));
9467 ins_cost(100);
9468 format %{ "UCOMISD $src1,$src2" %}
9469 ins_encode %{
9470 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9471 %}
9472 ins_pipe( pipe_slow );
9473 %}
9474
9475 // float compare and set condition codes in EFLAGS by XMM regs
9476 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9477 predicate(UseSSE>=2);
9478 match(Set cr (CmpD src1 (LoadD src2)));
9479 ins_cost(145);
9480 format %{ "UCOMISD $src1,$src2\n\t"
9481 "JNP,s exit\n\t"
9482 "PUSHF\t# saw NaN, set CF\n\t"
9483 "AND [rsp], #0xffffff2b\n\t"
9484 "POPF\n"
9485 "exit:" %}
9486 ins_encode %{
9487 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9488 emit_cmpfp_fixup(_masm);
9489 %}
9490 ins_pipe( pipe_slow );
9491 %}
9492
9493 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9494 predicate(UseSSE>=2);
9495 match(Set cr (CmpD src1 (LoadD src2)));
9496 ins_cost(100);
9497 format %{ "UCOMISD $src1,$src2" %}
9498 ins_encode %{
9499 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9500 %}
9501 ins_pipe( pipe_slow );
9502 %}
9503
9504 // Compare into -1,0,1 in XMM
9505 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9506 predicate(UseSSE>=2);
9507 match(Set dst (CmpD3 src1 src2));
9508 effect(KILL cr);
9509 ins_cost(255);
9510 format %{ "UCOMISD $src1, $src2\n\t"
9511 "MOV $dst, #-1\n\t"
9512 "JP,s done\n\t"
9513 "JB,s done\n\t"
9514 "SETNE $dst\n\t"
9515 "MOVZB $dst, $dst\n"
9516 "done:" %}
9517 ins_encode %{
9518 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9519 emit_cmpfp3(_masm, $dst$$Register);
9520 %}
9521 ins_pipe( pipe_slow );
9522 %}
9523
9524 // Compare into -1,0,1 in XMM and memory
9525 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9526 predicate(UseSSE>=2);
9527 match(Set dst (CmpD3 src1 (LoadD src2)));
9528 effect(KILL cr);
9529 ins_cost(275);
9530 format %{ "UCOMISD $src1, $src2\n\t"
9531 "MOV $dst, #-1\n\t"
9532 "JP,s done\n\t"
9533 "JB,s done\n\t"
9534 "SETNE $dst\n\t"
9535 "MOVZB $dst, $dst\n"
9536 "done:" %}
9537 ins_encode %{
9538 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9539 emit_cmpfp3(_masm, $dst$$Register);
9540 %}
9541 ins_pipe( pipe_slow );
9542 %}
9543
9544
9545 instruct subDPR_reg(regDPR dst, regDPR src) %{
9546 predicate (UseSSE <=1);
9547 match(Set dst (SubD dst src));
9548
9549 format %{ "FLD $src\n\t"
9550 "DSUBp $dst,ST" %}
9551 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9552 ins_cost(150);
9553 ins_encode( Push_Reg_DPR(src),
9554 OpcP, RegOpc(dst) );
9555 ins_pipe( fpu_reg_reg );
9556 %}
9557
9558 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9559 predicate (UseSSE <=1);
9560 match(Set dst (RoundDouble (SubD src1 src2)));
9561 ins_cost(250);
9562
9563 format %{ "FLD $src2\n\t"
9564 "DSUB ST,$src1\n\t"
9565 "FSTP_D $dst\t# D-round" %}
9566 opcode(0xD8, 0x5);
9567 ins_encode( Push_Reg_DPR(src2),
9568 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9569 ins_pipe( fpu_mem_reg_reg );
9570 %}
9571
9572
9573 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9574 predicate (UseSSE <=1);
9575 match(Set dst (SubD dst (LoadD src)));
9576 ins_cost(150);
9577
9578 format %{ "FLD $src\n\t"
9579 "DSUBp $dst,ST" %}
9580 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9581 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9582 OpcP, RegOpc(dst) );
9583 ins_pipe( fpu_reg_mem );
9584 %}
9585
9586 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9587 predicate (UseSSE<=1);
9588 match(Set dst (AbsD src));
9589 ins_cost(100);
9590 format %{ "FABS" %}
9591 opcode(0xE1, 0xD9);
9592 ins_encode( OpcS, OpcP );
9593 ins_pipe( fpu_reg_reg );
9594 %}
9595
9596 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9597 predicate(UseSSE<=1);
9598 match(Set dst (NegD src));
9599 ins_cost(100);
9600 format %{ "FCHS" %}
9601 opcode(0xE0, 0xD9);
9602 ins_encode( OpcS, OpcP );
9603 ins_pipe( fpu_reg_reg );
9604 %}
9605
9606 instruct addDPR_reg(regDPR dst, regDPR src) %{
9607 predicate(UseSSE<=1);
9608 match(Set dst (AddD dst src));
9609 format %{ "FLD $src\n\t"
9610 "DADD $dst,ST" %}
9611 size(4);
9612 ins_cost(150);
9613 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9614 ins_encode( Push_Reg_DPR(src),
9615 OpcP, RegOpc(dst) );
9616 ins_pipe( fpu_reg_reg );
9617 %}
9618
9619
9620 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9621 predicate(UseSSE<=1);
9622 match(Set dst (RoundDouble (AddD src1 src2)));
9623 ins_cost(250);
9624
9625 format %{ "FLD $src2\n\t"
9626 "DADD ST,$src1\n\t"
9627 "FSTP_D $dst\t# D-round" %}
9628 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9629 ins_encode( Push_Reg_DPR(src2),
9630 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9631 ins_pipe( fpu_mem_reg_reg );
9632 %}
9633
9634
9635 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9636 predicate(UseSSE<=1);
9637 match(Set dst (AddD dst (LoadD src)));
9638 ins_cost(150);
9639
9640 format %{ "FLD $src\n\t"
9641 "DADDp $dst,ST" %}
9642 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9643 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9644 OpcP, RegOpc(dst) );
9645 ins_pipe( fpu_reg_mem );
9646 %}
9647
9648 // add-to-memory
9649 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9650 predicate(UseSSE<=1);
9651 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9652 ins_cost(150);
9653
9654 format %{ "FLD_D $dst\n\t"
9655 "DADD ST,$src\n\t"
9656 "FST_D $dst" %}
9657 opcode(0xDD, 0x0);
9658 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9659 Opcode(0xD8), RegOpc(src),
9660 set_instruction_start,
9661 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9662 ins_pipe( fpu_reg_mem );
9663 %}
9664
9665 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9666 predicate(UseSSE<=1);
9667 match(Set dst (AddD dst con));
9668 ins_cost(125);
9669 format %{ "FLD1\n\t"
9670 "DADDp $dst,ST" %}
9671 ins_encode %{
9672 __ fld1();
9673 __ faddp($dst$$reg);
9674 %}
9675 ins_pipe(fpu_reg);
9676 %}
9677
9678 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9679 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9680 match(Set dst (AddD dst con));
9681 ins_cost(200);
9682 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9683 "DADDp $dst,ST" %}
9684 ins_encode %{
9685 __ fld_d($constantaddress($con));
9686 __ faddp($dst$$reg);
9687 %}
9688 ins_pipe(fpu_reg_mem);
9689 %}
9690
9691 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9692 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9693 match(Set dst (RoundDouble (AddD src con)));
9694 ins_cost(200);
9695 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9696 "DADD ST,$src\n\t"
9697 "FSTP_D $dst\t# D-round" %}
9698 ins_encode %{
9699 __ fld_d($constantaddress($con));
9700 __ fadd($src$$reg);
9701 __ fstp_d(Address(rsp, $dst$$disp));
9702 %}
9703 ins_pipe(fpu_mem_reg_con);
9704 %}
9705
9706 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9707 predicate(UseSSE<=1);
9708 match(Set dst (MulD dst src));
9709 format %{ "FLD $src\n\t"
9710 "DMULp $dst,ST" %}
9711 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9712 ins_cost(150);
9713 ins_encode( Push_Reg_DPR(src),
9714 OpcP, RegOpc(dst) );
9715 ins_pipe( fpu_reg_reg );
9716 %}
9717
9718 // Strict FP instruction biases argument before multiply then
9719 // biases result to avoid double rounding of subnormals.
9720 //
9721 // scale arg1 by multiplying arg1 by 2^(-15360)
9722 // load arg2
9723 // multiply scaled arg1 by arg2
9724 // rescale product by 2^(15360)
9725 //
9726 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9727 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9728 match(Set dst (MulD dst src));
9729 ins_cost(1); // Select this instruction for all strict FP double multiplies
9730
9731 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9732 "DMULp $dst,ST\n\t"
9733 "FLD $src\n\t"
9734 "DMULp $dst,ST\n\t"
9735 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9736 "DMULp $dst,ST\n\t" %}
9737 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9738 ins_encode( strictfp_bias1(dst),
9739 Push_Reg_DPR(src),
9740 OpcP, RegOpc(dst),
9741 strictfp_bias2(dst) );
9742 ins_pipe( fpu_reg_reg );
9743 %}
9744
9745 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9746 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9747 match(Set dst (MulD dst con));
9748 ins_cost(200);
9749 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9750 "DMULp $dst,ST" %}
9751 ins_encode %{
9752 __ fld_d($constantaddress($con));
9753 __ fmulp($dst$$reg);
9754 %}
9755 ins_pipe(fpu_reg_mem);
9756 %}
9757
9758
9759 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9760 predicate( UseSSE<=1 );
9761 match(Set dst (MulD dst (LoadD src)));
9762 ins_cost(200);
9763 format %{ "FLD_D $src\n\t"
9764 "DMULp $dst,ST" %}
9765 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9766 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9767 OpcP, RegOpc(dst) );
9768 ins_pipe( fpu_reg_mem );
9769 %}
9770
9771 //
9772 // Cisc-alternate to reg-reg multiply
9773 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9774 predicate( UseSSE<=1 );
9775 match(Set dst (MulD src (LoadD mem)));
9776 ins_cost(250);
9777 format %{ "FLD_D $mem\n\t"
9778 "DMUL ST,$src\n\t"
9779 "FSTP_D $dst" %}
9780 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9781 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9782 OpcReg_FPR(src),
9783 Pop_Reg_DPR(dst) );
9784 ins_pipe( fpu_reg_reg_mem );
9785 %}
9786
9787
9788 // MACRO3 -- addDPR a mulDPR
9789 // This instruction is a '2-address' instruction in that the result goes
9790 // back to src2. This eliminates a move from the macro; possibly the
9791 // register allocator will have to add it back (and maybe not).
9792 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9793 predicate( UseSSE<=1 );
9794 match(Set src2 (AddD (MulD src0 src1) src2));
9795 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9796 "DMUL ST,$src1\n\t"
9797 "DADDp $src2,ST" %}
9798 ins_cost(250);
9799 opcode(0xDD); /* LoadD DD /0 */
9800 ins_encode( Push_Reg_FPR(src0),
9801 FMul_ST_reg(src1),
9802 FAddP_reg_ST(src2) );
9803 ins_pipe( fpu_reg_reg_reg );
9804 %}
9805
9806
9807 // MACRO3 -- subDPR a mulDPR
9808 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9809 predicate( UseSSE<=1 );
9810 match(Set src2 (SubD (MulD src0 src1) src2));
9811 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9812 "DMUL ST,$src1\n\t"
9813 "DSUBRp $src2,ST" %}
9814 ins_cost(250);
9815 ins_encode( Push_Reg_FPR(src0),
9816 FMul_ST_reg(src1),
9817 Opcode(0xDE), Opc_plus(0xE0,src2));
9818 ins_pipe( fpu_reg_reg_reg );
9819 %}
9820
9821
9822 instruct divDPR_reg(regDPR dst, regDPR src) %{
9823 predicate( UseSSE<=1 );
9824 match(Set dst (DivD dst src));
9825
9826 format %{ "FLD $src\n\t"
9827 "FDIVp $dst,ST" %}
9828 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9829 ins_cost(150);
9830 ins_encode( Push_Reg_DPR(src),
9831 OpcP, RegOpc(dst) );
9832 ins_pipe( fpu_reg_reg );
9833 %}
9834
9835 // Strict FP instruction biases argument before division then
9836 // biases result, to avoid double rounding of subnormals.
9837 //
9838 // scale dividend by multiplying dividend by 2^(-15360)
9839 // load divisor
9840 // divide scaled dividend by divisor
9841 // rescale quotient by 2^(15360)
9842 //
9843 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9844 predicate (UseSSE<=1);
9845 match(Set dst (DivD dst src));
9846 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9847 ins_cost(01);
9848
9849 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9850 "DMULp $dst,ST\n\t"
9851 "FLD $src\n\t"
9852 "FDIVp $dst,ST\n\t"
9853 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9854 "DMULp $dst,ST\n\t" %}
9855 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9856 ins_encode( strictfp_bias1(dst),
9857 Push_Reg_DPR(src),
9858 OpcP, RegOpc(dst),
9859 strictfp_bias2(dst) );
9860 ins_pipe( fpu_reg_reg );
9861 %}
9862
9863 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9864 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9865 match(Set dst (RoundDouble (DivD src1 src2)));
9866
9867 format %{ "FLD $src1\n\t"
9868 "FDIV ST,$src2\n\t"
9869 "FSTP_D $dst\t# D-round" %}
9870 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9871 ins_encode( Push_Reg_DPR(src1),
9872 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9873 ins_pipe( fpu_mem_reg_reg );
9874 %}
9875
9876
9877 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9878 predicate(UseSSE<=1);
9879 match(Set dst (ModD dst src));
9880 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9881
9882 format %{ "DMOD $dst,$src" %}
9883 ins_cost(250);
9884 ins_encode(Push_Reg_Mod_DPR(dst, src),
9885 emitModDPR(),
9886 Push_Result_Mod_DPR(src),
9887 Pop_Reg_DPR(dst));
9888 ins_pipe( pipe_slow );
9889 %}
9890
9891 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9892 predicate(UseSSE>=2);
9893 match(Set dst (ModD src0 src1));
9894 effect(KILL rax, KILL cr);
9895
9896 format %{ "SUB ESP,8\t # DMOD\n"
9897 "\tMOVSD [ESP+0],$src1\n"
9898 "\tFLD_D [ESP+0]\n"
9899 "\tMOVSD [ESP+0],$src0\n"
9900 "\tFLD_D [ESP+0]\n"
9901 "loop:\tFPREM\n"
9902 "\tFWAIT\n"
9903 "\tFNSTSW AX\n"
9904 "\tSAHF\n"
9905 "\tJP loop\n"
9906 "\tFSTP_D [ESP+0]\n"
9907 "\tMOVSD $dst,[ESP+0]\n"
9908 "\tADD ESP,8\n"
9909 "\tFSTP ST0\t # Restore FPU Stack"
9910 %}
9911 ins_cost(250);
9912 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9913 ins_pipe( pipe_slow );
9914 %}
9915
9916 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9917 predicate (UseSSE<=1);
9918 match(Set dst (SinD src));
9919 ins_cost(1800);
9920 format %{ "DSIN $dst" %}
9921 opcode(0xD9, 0xFE);
9922 ins_encode( OpcP, OpcS );
9923 ins_pipe( pipe_slow );
9924 %}
9925
9926 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9927 predicate (UseSSE>=2);
9928 match(Set dst (SinD dst));
9929 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9930 ins_cost(1800);
9931 format %{ "DSIN $dst" %}
9932 opcode(0xD9, 0xFE);
9933 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9934 ins_pipe( pipe_slow );
9935 %}
9936
9937 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9938 predicate (UseSSE<=1);
9939 match(Set dst (CosD src));
9940 ins_cost(1800);
9941 format %{ "DCOS $dst" %}
9942 opcode(0xD9, 0xFF);
9943 ins_encode( OpcP, OpcS );
9944 ins_pipe( pipe_slow );
9945 %}
9946
9947 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9948 predicate (UseSSE>=2);
9949 match(Set dst (CosD dst));
9950 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9951 ins_cost(1800);
9952 format %{ "DCOS $dst" %}
9953 opcode(0xD9, 0xFF);
9954 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9955 ins_pipe( pipe_slow );
9956 %}
9957
9958 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9959 predicate (UseSSE<=1);
9960 match(Set dst(TanD src));
9961 format %{ "DTAN $dst" %}
9962 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9963 Opcode(0xDD), Opcode(0xD8)); // fstp st
9964 ins_pipe( pipe_slow );
9965 %}
9966
9967 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9968 predicate (UseSSE>=2);
9969 match(Set dst(TanD dst));
9970 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9971 format %{ "DTAN $dst" %}
9972 ins_encode( Push_SrcD(dst),
9973 Opcode(0xD9), Opcode(0xF2), // fptan
9974 Opcode(0xDD), Opcode(0xD8), // fstp st
9975 Push_ResultD(dst) );
9976 ins_pipe( pipe_slow );
9977 %}
9978
9979 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9980 predicate (UseSSE<=1);
9981 match(Set dst(AtanD dst src));
9982 format %{ "DATA $dst,$src" %}
9983 opcode(0xD9, 0xF3);
9984 ins_encode( Push_Reg_DPR(src),
9985 OpcP, OpcS, RegOpc(dst) );
9986 ins_pipe( pipe_slow );
9987 %}
9988
9989 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9990 predicate (UseSSE>=2);
9991 match(Set dst(AtanD dst src));
9992 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9993 format %{ "DATA $dst,$src" %}
9994 opcode(0xD9, 0xF3);
9995 ins_encode( Push_SrcD(src),
9996 OpcP, OpcS, Push_ResultD(dst) );
9997 ins_pipe( pipe_slow );
9998 %}
9999
10000 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10001 predicate (UseSSE<=1);
10002 match(Set dst (SqrtD src));
10003 format %{ "DSQRT $dst,$src" %}
10004 opcode(0xFA, 0xD9);
10005 ins_encode( Push_Reg_DPR(src),
10006 OpcS, OpcP, Pop_Reg_DPR(dst) );
10007 ins_pipe( pipe_slow );
10008 %}
10009
10010 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10011 predicate (UseSSE<=1);
10012 match(Set Y (PowD X Y)); // Raise X to the Yth power
10013 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10014 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10015 ins_encode %{
10016 __ subptr(rsp, 8);
10017 __ fld_s($X$$reg - 1);
10018 __ fast_pow();
10019 __ addptr(rsp, 8);
10020 %}
10021 ins_pipe( pipe_slow );
10022 %}
10023
10024 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10025 predicate (UseSSE>=2);
10026 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10027 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10028 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10029 ins_encode %{
10030 __ subptr(rsp, 8);
10031 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10032 __ fld_d(Address(rsp, 0));
10033 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10034 __ fld_d(Address(rsp, 0));
10035 __ fast_pow();
10036 __ fstp_d(Address(rsp, 0));
10037 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10038 __ addptr(rsp, 8);
10039 %}
10040 ins_pipe( pipe_slow );
10041 %}
10042
10043
10044 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10045 predicate (UseSSE<=1);
10046 match(Set dpr1 (ExpD dpr1));
10047 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10048 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10049 ins_encode %{
10050 __ fast_exp();
10051 %}
10052 ins_pipe( pipe_slow );
10053 %}
10054
10055 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10056 predicate (UseSSE>=2);
10057 match(Set dst (ExpD src));
10058 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10059 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10060 ins_encode %{
10061 __ subptr(rsp, 8);
10062 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10063 __ fld_d(Address(rsp, 0));
10064 __ fast_exp();
10065 __ fstp_d(Address(rsp, 0));
10066 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10067 __ addptr(rsp, 8);
10068 %}
10069 ins_pipe( pipe_slow );
10070 %}
10071
10072 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10073 predicate (UseSSE<=1);
10074 // The source Double operand on FPU stack
10075 match(Set dst (Log10D src));
10076 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10077 // fxch ; swap ST(0) with ST(1)
10078 // fyl2x ; compute log_10(2) * log_2(x)
10079 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10080 "FXCH \n\t"
10081 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10082 %}
10083 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10084 Opcode(0xD9), Opcode(0xC9), // fxch
10085 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10086
10087 ins_pipe( pipe_slow );
10088 %}
10089
10090 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10091 predicate (UseSSE>=2);
10092 effect(KILL cr);
10093 match(Set dst (Log10D src));
10094 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10095 // fyl2x ; compute log_10(2) * log_2(x)
10096 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10097 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10098 %}
10099 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10100 Push_SrcD(src),
10101 Opcode(0xD9), Opcode(0xF1), // fyl2x
10102 Push_ResultD(dst));
10103
10104 ins_pipe( pipe_slow );
10105 %}
10106
10107 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10108 predicate (UseSSE<=1);
10109 // The source Double operand on FPU stack
10110 match(Set dst (LogD src));
10111 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10112 // fxch ; swap ST(0) with ST(1)
10113 // fyl2x ; compute log_e(2) * log_2(x)
10114 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10115 "FXCH \n\t"
10116 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10117 %}
10118 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10119 Opcode(0xD9), Opcode(0xC9), // fxch
10120 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10121
10122 ins_pipe( pipe_slow );
10123 %}
10124
10125 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10126 predicate (UseSSE>=2);
10127 effect(KILL cr);
10128 // The source and result Double operands in XMM registers
10129 match(Set dst (LogD src));
10130 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10131 // fyl2x ; compute log_e(2) * log_2(x)
10132 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10133 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10134 %}
10135 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10136 Push_SrcD(src),
10137 Opcode(0xD9), Opcode(0xF1), // fyl2x
10138 Push_ResultD(dst));
10139 ins_pipe( pipe_slow );
10140 %}
10141
10142 //-------------Float Instructions-------------------------------
10143 // Float Math
10144
10145 // Code for float compare:
10146 // fcompp();
10147 // fwait(); fnstsw_ax();
10148 // sahf();
10149 // movl(dst, unordered_result);
10150 // jcc(Assembler::parity, exit);
10151 // movl(dst, less_result);
10152 // jcc(Assembler::below, exit);
10153 // movl(dst, equal_result);
10154 // jcc(Assembler::equal, exit);
10155 // movl(dst, greater_result);
10156 // exit:
10157
10158 // P6 version of float compare, sets condition codes in EFLAGS
10159 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10160 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10161 match(Set cr (CmpF src1 src2));
10162 effect(KILL rax);
10163 ins_cost(150);
10164 format %{ "FLD $src1\n\t"
10165 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10166 "JNP exit\n\t"
10167 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10168 "SAHF\n"
10169 "exit:\tNOP // avoid branch to branch" %}
10170 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10171 ins_encode( Push_Reg_DPR(src1),
10172 OpcP, RegOpc(src2),
10173 cmpF_P6_fixup );
10174 ins_pipe( pipe_slow );
10175 %}
10176
10177 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10178 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10179 match(Set cr (CmpF src1 src2));
10180 ins_cost(100);
10181 format %{ "FLD $src1\n\t"
10182 "FUCOMIP ST,$src2 // P6 instruction" %}
10183 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10184 ins_encode( Push_Reg_DPR(src1),
10185 OpcP, RegOpc(src2));
10186 ins_pipe( pipe_slow );
10187 %}
10188
10189
10190 // Compare & branch
10191 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10192 predicate(UseSSE == 0);
10193 match(Set cr (CmpF src1 src2));
10194 effect(KILL rax);
10195 ins_cost(200);
10196 format %{ "FLD $src1\n\t"
10197 "FCOMp $src2\n\t"
10198 "FNSTSW AX\n\t"
10199 "TEST AX,0x400\n\t"
10200 "JZ,s flags\n\t"
10201 "MOV AH,1\t# unordered treat as LT\n"
10202 "flags:\tSAHF" %}
10203 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10204 ins_encode( Push_Reg_DPR(src1),
10205 OpcP, RegOpc(src2),
10206 fpu_flags);
10207 ins_pipe( pipe_slow );
10208 %}
10209
10210 // Compare vs zero into -1,0,1
10211 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10212 predicate(UseSSE == 0);
10213 match(Set dst (CmpF3 src1 zero));
10214 effect(KILL cr, KILL rax);
10215 ins_cost(280);
10216 format %{ "FTSTF $dst,$src1" %}
10217 opcode(0xE4, 0xD9);
10218 ins_encode( Push_Reg_DPR(src1),
10219 OpcS, OpcP, PopFPU,
10220 CmpF_Result(dst));
10221 ins_pipe( pipe_slow );
10222 %}
10223
10224 // Compare into -1,0,1
10225 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10226 predicate(UseSSE == 0);
10227 match(Set dst (CmpF3 src1 src2));
10228 effect(KILL cr, KILL rax);
10229 ins_cost(300);
10230 format %{ "FCMPF $dst,$src1,$src2" %}
10231 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10232 ins_encode( Push_Reg_DPR(src1),
10233 OpcP, RegOpc(src2),
10234 CmpF_Result(dst));
10235 ins_pipe( pipe_slow );
10236 %}
10237
10238 // float compare and set condition codes in EFLAGS by XMM regs
10239 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10240 predicate(UseSSE>=1);
10241 match(Set cr (CmpF src1 src2));
10242 ins_cost(145);
10243 format %{ "UCOMISS $src1,$src2\n\t"
10244 "JNP,s exit\n\t"
10245 "PUSHF\t# saw NaN, set CF\n\t"
10246 "AND [rsp], #0xffffff2b\n\t"
10247 "POPF\n"
10248 "exit:" %}
10249 ins_encode %{
10250 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10251 emit_cmpfp_fixup(_masm);
10252 %}
10253 ins_pipe( pipe_slow );
10254 %}
10255
10256 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10257 predicate(UseSSE>=1);
10258 match(Set cr (CmpF src1 src2));
10259 ins_cost(100);
10260 format %{ "UCOMISS $src1,$src2" %}
10261 ins_encode %{
10262 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10263 %}
10264 ins_pipe( pipe_slow );
10265 %}
10266
10267 // float compare and set condition codes in EFLAGS by XMM regs
10268 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10269 predicate(UseSSE>=1);
10270 match(Set cr (CmpF src1 (LoadF src2)));
10271 ins_cost(165);
10272 format %{ "UCOMISS $src1,$src2\n\t"
10273 "JNP,s exit\n\t"
10274 "PUSHF\t# saw NaN, set CF\n\t"
10275 "AND [rsp], #0xffffff2b\n\t"
10276 "POPF\n"
10277 "exit:" %}
10278 ins_encode %{
10279 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10280 emit_cmpfp_fixup(_masm);
10281 %}
10282 ins_pipe( pipe_slow );
10283 %}
10284
10285 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10286 predicate(UseSSE>=1);
10287 match(Set cr (CmpF src1 (LoadF src2)));
10288 ins_cost(100);
10289 format %{ "UCOMISS $src1,$src2" %}
10290 ins_encode %{
10291 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10292 %}
10293 ins_pipe( pipe_slow );
10294 %}
10295
10296 // Compare into -1,0,1 in XMM
10297 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10298 predicate(UseSSE>=1);
10299 match(Set dst (CmpF3 src1 src2));
10300 effect(KILL cr);
10301 ins_cost(255);
10302 format %{ "UCOMISS $src1, $src2\n\t"
10303 "MOV $dst, #-1\n\t"
10304 "JP,s done\n\t"
10305 "JB,s done\n\t"
10306 "SETNE $dst\n\t"
10307 "MOVZB $dst, $dst\n"
10308 "done:" %}
10309 ins_encode %{
10310 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10311 emit_cmpfp3(_masm, $dst$$Register);
10312 %}
10313 ins_pipe( pipe_slow );
10314 %}
10315
10316 // Compare into -1,0,1 in XMM and memory
10317 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10318 predicate(UseSSE>=1);
10319 match(Set dst (CmpF3 src1 (LoadF src2)));
10320 effect(KILL cr);
10321 ins_cost(275);
10322 format %{ "UCOMISS $src1, $src2\n\t"
10323 "MOV $dst, #-1\n\t"
10324 "JP,s done\n\t"
10325 "JB,s done\n\t"
10326 "SETNE $dst\n\t"
10327 "MOVZB $dst, $dst\n"
10328 "done:" %}
10329 ins_encode %{
10330 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10331 emit_cmpfp3(_masm, $dst$$Register);
10332 %}
10333 ins_pipe( pipe_slow );
10334 %}
10335
10336 // Spill to obtain 24-bit precision
10337 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10338 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10339 match(Set dst (SubF src1 src2));
10340
10341 format %{ "FSUB $dst,$src1 - $src2" %}
10342 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10343 ins_encode( Push_Reg_FPR(src1),
10344 OpcReg_FPR(src2),
10345 Pop_Mem_FPR(dst) );
10346 ins_pipe( fpu_mem_reg_reg );
10347 %}
10348 //
10349 // This instruction does not round to 24-bits
10350 instruct subFPR_reg(regFPR dst, regFPR src) %{
10351 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10352 match(Set dst (SubF dst src));
10353
10354 format %{ "FSUB $dst,$src" %}
10355 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10356 ins_encode( Push_Reg_FPR(src),
10357 OpcP, RegOpc(dst) );
10358 ins_pipe( fpu_reg_reg );
10359 %}
10360
10361 // Spill to obtain 24-bit precision
10362 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10363 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10364 match(Set dst (AddF src1 src2));
10365
10366 format %{ "FADD $dst,$src1,$src2" %}
10367 opcode(0xD8, 0x0); /* D8 C0+i */
10368 ins_encode( Push_Reg_FPR(src2),
10369 OpcReg_FPR(src1),
10370 Pop_Mem_FPR(dst) );
10371 ins_pipe( fpu_mem_reg_reg );
10372 %}
10373 //
10374 // This instruction does not round to 24-bits
10375 instruct addFPR_reg(regFPR dst, regFPR src) %{
10376 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10377 match(Set dst (AddF dst src));
10378
10379 format %{ "FLD $src\n\t"
10380 "FADDp $dst,ST" %}
10381 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10382 ins_encode( Push_Reg_FPR(src),
10383 OpcP, RegOpc(dst) );
10384 ins_pipe( fpu_reg_reg );
10385 %}
10386
10387 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10388 predicate(UseSSE==0);
10389 match(Set dst (AbsF src));
10390 ins_cost(100);
10391 format %{ "FABS" %}
10392 opcode(0xE1, 0xD9);
10393 ins_encode( OpcS, OpcP );
10394 ins_pipe( fpu_reg_reg );
10395 %}
10396
10397 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10398 predicate(UseSSE==0);
10399 match(Set dst (NegF src));
10400 ins_cost(100);
10401 format %{ "FCHS" %}
10402 opcode(0xE0, 0xD9);
10403 ins_encode( OpcS, OpcP );
10404 ins_pipe( fpu_reg_reg );
10405 %}
10406
10407 // Cisc-alternate to addFPR_reg
10408 // Spill to obtain 24-bit precision
10409 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10410 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10411 match(Set dst (AddF src1 (LoadF src2)));
10412
10413 format %{ "FLD $src2\n\t"
10414 "FADD ST,$src1\n\t"
10415 "FSTP_S $dst" %}
10416 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10417 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10418 OpcReg_FPR(src1),
10419 Pop_Mem_FPR(dst) );
10420 ins_pipe( fpu_mem_reg_mem );
10421 %}
10422 //
10423 // Cisc-alternate to addFPR_reg
10424 // This instruction does not round to 24-bits
10425 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10426 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10427 match(Set dst (AddF dst (LoadF src)));
10428
10429 format %{ "FADD $dst,$src" %}
10430 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10431 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10432 OpcP, RegOpc(dst) );
10433 ins_pipe( fpu_reg_mem );
10434 %}
10435
10436 // // Following two instructions for _222_mpegaudio
10437 // Spill to obtain 24-bit precision
10438 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10439 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10440 match(Set dst (AddF src1 src2));
10441
10442 format %{ "FADD $dst,$src1,$src2" %}
10443 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10444 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10445 OpcReg_FPR(src2),
10446 Pop_Mem_FPR(dst) );
10447 ins_pipe( fpu_mem_reg_mem );
10448 %}
10449
10450 // Cisc-spill variant
10451 // Spill to obtain 24-bit precision
10452 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10453 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10454 match(Set dst (AddF src1 (LoadF src2)));
10455
10456 format %{ "FADD $dst,$src1,$src2 cisc" %}
10457 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10458 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10459 set_instruction_start,
10460 OpcP, RMopc_Mem(secondary,src1),
10461 Pop_Mem_FPR(dst) );
10462 ins_pipe( fpu_mem_mem_mem );
10463 %}
10464
10465 // Spill to obtain 24-bit precision
10466 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10467 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10468 match(Set dst (AddF src1 src2));
10469
10470 format %{ "FADD $dst,$src1,$src2" %}
10471 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10472 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10473 set_instruction_start,
10474 OpcP, RMopc_Mem(secondary,src1),
10475 Pop_Mem_FPR(dst) );
10476 ins_pipe( fpu_mem_mem_mem );
10477 %}
10478
10479
10480 // Spill to obtain 24-bit precision
10481 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10482 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10483 match(Set dst (AddF src con));
10484 format %{ "FLD $src\n\t"
10485 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10486 "FSTP_S $dst" %}
10487 ins_encode %{
10488 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10489 __ fadd_s($constantaddress($con));
10490 __ fstp_s(Address(rsp, $dst$$disp));
10491 %}
10492 ins_pipe(fpu_mem_reg_con);
10493 %}
10494 //
10495 // This instruction does not round to 24-bits
10496 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10497 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10498 match(Set dst (AddF src con));
10499 format %{ "FLD $src\n\t"
10500 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10501 "FSTP $dst" %}
10502 ins_encode %{
10503 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10504 __ fadd_s($constantaddress($con));
10505 __ fstp_d($dst$$reg);
10506 %}
10507 ins_pipe(fpu_reg_reg_con);
10508 %}
10509
10510 // Spill to obtain 24-bit precision
10511 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10512 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10513 match(Set dst (MulF src1 src2));
10514
10515 format %{ "FLD $src1\n\t"
10516 "FMUL $src2\n\t"
10517 "FSTP_S $dst" %}
10518 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10519 ins_encode( Push_Reg_FPR(src1),
10520 OpcReg_FPR(src2),
10521 Pop_Mem_FPR(dst) );
10522 ins_pipe( fpu_mem_reg_reg );
10523 %}
10524 //
10525 // This instruction does not round to 24-bits
10526 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10527 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10528 match(Set dst (MulF src1 src2));
10529
10530 format %{ "FLD $src1\n\t"
10531 "FMUL $src2\n\t"
10532 "FSTP_S $dst" %}
10533 opcode(0xD8, 0x1); /* D8 C8+i */
10534 ins_encode( Push_Reg_FPR(src2),
10535 OpcReg_FPR(src1),
10536 Pop_Reg_FPR(dst) );
10537 ins_pipe( fpu_reg_reg_reg );
10538 %}
10539
10540
10541 // Spill to obtain 24-bit precision
10542 // Cisc-alternate to reg-reg multiply
10543 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10544 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10545 match(Set dst (MulF src1 (LoadF src2)));
10546
10547 format %{ "FLD_S $src2\n\t"
10548 "FMUL $src1\n\t"
10549 "FSTP_S $dst" %}
10550 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10551 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10552 OpcReg_FPR(src1),
10553 Pop_Mem_FPR(dst) );
10554 ins_pipe( fpu_mem_reg_mem );
10555 %}
10556 //
10557 // This instruction does not round to 24-bits
10558 // Cisc-alternate to reg-reg multiply
10559 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10560 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10561 match(Set dst (MulF src1 (LoadF src2)));
10562
10563 format %{ "FMUL $dst,$src1,$src2" %}
10564 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10565 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10566 OpcReg_FPR(src1),
10567 Pop_Reg_FPR(dst) );
10568 ins_pipe( fpu_reg_reg_mem );
10569 %}
10570
10571 // Spill to obtain 24-bit precision
10572 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10573 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10574 match(Set dst (MulF src1 src2));
10575
10576 format %{ "FMUL $dst,$src1,$src2" %}
10577 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10578 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10579 set_instruction_start,
10580 OpcP, RMopc_Mem(secondary,src1),
10581 Pop_Mem_FPR(dst) );
10582 ins_pipe( fpu_mem_mem_mem );
10583 %}
10584
10585 // Spill to obtain 24-bit precision
10586 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10587 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10588 match(Set dst (MulF src con));
10589
10590 format %{ "FLD $src\n\t"
10591 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10592 "FSTP_S $dst" %}
10593 ins_encode %{
10594 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10595 __ fmul_s($constantaddress($con));
10596 __ fstp_s(Address(rsp, $dst$$disp));
10597 %}
10598 ins_pipe(fpu_mem_reg_con);
10599 %}
10600 //
10601 // This instruction does not round to 24-bits
10602 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10603 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10604 match(Set dst (MulF src con));
10605
10606 format %{ "FLD $src\n\t"
10607 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10608 "FSTP $dst" %}
10609 ins_encode %{
10610 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10611 __ fmul_s($constantaddress($con));
10612 __ fstp_d($dst$$reg);
10613 %}
10614 ins_pipe(fpu_reg_reg_con);
10615 %}
10616
10617
10618 //
10619 // MACRO1 -- subsume unshared load into mulFPR
10620 // This instruction does not round to 24-bits
10621 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10622 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10623 match(Set dst (MulF (LoadF mem1) src));
10624
10625 format %{ "FLD $mem1 ===MACRO1===\n\t"
10626 "FMUL ST,$src\n\t"
10627 "FSTP $dst" %}
10628 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10629 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10630 OpcReg_FPR(src),
10631 Pop_Reg_FPR(dst) );
10632 ins_pipe( fpu_reg_reg_mem );
10633 %}
10634 //
10635 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10636 // This instruction does not round to 24-bits
10637 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10638 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10639 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10640 ins_cost(95);
10641
10642 format %{ "FLD $mem1 ===MACRO2===\n\t"
10643 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10644 "FADD ST,$src2\n\t"
10645 "FSTP $dst" %}
10646 opcode(0xD9); /* LoadF D9 /0 */
10647 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10648 FMul_ST_reg(src1),
10649 FAdd_ST_reg(src2),
10650 Pop_Reg_FPR(dst) );
10651 ins_pipe( fpu_reg_mem_reg_reg );
10652 %}
10653
10654 // MACRO3 -- addFPR a mulFPR
10655 // This instruction does not round to 24-bits. It is a '2-address'
10656 // instruction in that the result goes back to src2. This eliminates
10657 // a move from the macro; possibly the register allocator will have
10658 // to add it back (and maybe not).
10659 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10660 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10661 match(Set src2 (AddF (MulF src0 src1) src2));
10662
10663 format %{ "FLD $src0 ===MACRO3===\n\t"
10664 "FMUL ST,$src1\n\t"
10665 "FADDP $src2,ST" %}
10666 opcode(0xD9); /* LoadF D9 /0 */
10667 ins_encode( Push_Reg_FPR(src0),
10668 FMul_ST_reg(src1),
10669 FAddP_reg_ST(src2) );
10670 ins_pipe( fpu_reg_reg_reg );
10671 %}
10672
10673 // MACRO4 -- divFPR subFPR
10674 // This instruction does not round to 24-bits
10675 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10676 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10677 match(Set dst (DivF (SubF src2 src1) src3));
10678
10679 format %{ "FLD $src2 ===MACRO4===\n\t"
10680 "FSUB ST,$src1\n\t"
10681 "FDIV ST,$src3\n\t"
10682 "FSTP $dst" %}
10683 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10684 ins_encode( Push_Reg_FPR(src2),
10685 subFPR_divFPR_encode(src1,src3),
10686 Pop_Reg_FPR(dst) );
10687 ins_pipe( fpu_reg_reg_reg_reg );
10688 %}
10689
10690 // Spill to obtain 24-bit precision
10691 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10692 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10693 match(Set dst (DivF src1 src2));
10694
10695 format %{ "FDIV $dst,$src1,$src2" %}
10696 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10697 ins_encode( Push_Reg_FPR(src1),
10698 OpcReg_FPR(src2),
10699 Pop_Mem_FPR(dst) );
10700 ins_pipe( fpu_mem_reg_reg );
10701 %}
10702 //
10703 // This instruction does not round to 24-bits
10704 instruct divFPR_reg(regFPR dst, regFPR src) %{
10705 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10706 match(Set dst (DivF dst src));
10707
10708 format %{ "FDIV $dst,$src" %}
10709 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10710 ins_encode( Push_Reg_FPR(src),
10711 OpcP, RegOpc(dst) );
10712 ins_pipe( fpu_reg_reg );
10713 %}
10714
10715
10716 // Spill to obtain 24-bit precision
10717 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10718 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10719 match(Set dst (ModF src1 src2));
10720 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10721
10722 format %{ "FMOD $dst,$src1,$src2" %}
10723 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10724 emitModDPR(),
10725 Push_Result_Mod_DPR(src2),
10726 Pop_Mem_FPR(dst));
10727 ins_pipe( pipe_slow );
10728 %}
10729 //
10730 // This instruction does not round to 24-bits
10731 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10732 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10733 match(Set dst (ModF dst src));
10734 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10735
10736 format %{ "FMOD $dst,$src" %}
10737 ins_encode(Push_Reg_Mod_DPR(dst, src),
10738 emitModDPR(),
10739 Push_Result_Mod_DPR(src),
10740 Pop_Reg_FPR(dst));
10741 ins_pipe( pipe_slow );
10742 %}
10743
10744 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10745 predicate(UseSSE>=1);
10746 match(Set dst (ModF src0 src1));
10747 effect(KILL rax, KILL cr);
10748 format %{ "SUB ESP,4\t # FMOD\n"
10749 "\tMOVSS [ESP+0],$src1\n"
10750 "\tFLD_S [ESP+0]\n"
10751 "\tMOVSS [ESP+0],$src0\n"
10752 "\tFLD_S [ESP+0]\n"
10753 "loop:\tFPREM\n"
10754 "\tFWAIT\n"
10755 "\tFNSTSW AX\n"
10756 "\tSAHF\n"
10757 "\tJP loop\n"
10758 "\tFSTP_S [ESP+0]\n"
10759 "\tMOVSS $dst,[ESP+0]\n"
10760 "\tADD ESP,4\n"
10761 "\tFSTP ST0\t # Restore FPU Stack"
10762 %}
10763 ins_cost(250);
10764 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10765 ins_pipe( pipe_slow );
10766 %}
10767
10768
10769 //----------Arithmetic Conversion Instructions---------------------------------
10770 // The conversions operations are all Alpha sorted. Please keep it that way!
10771
10772 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10773 predicate(UseSSE==0);
10774 match(Set dst (RoundFloat src));
10775 ins_cost(125);
10776 format %{ "FST_S $dst,$src\t# F-round" %}
10777 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10778 ins_pipe( fpu_mem_reg );
10779 %}
10780
10781 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10782 predicate(UseSSE<=1);
10783 match(Set dst (RoundDouble src));
10784 ins_cost(125);
10785 format %{ "FST_D $dst,$src\t# D-round" %}
10786 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10787 ins_pipe( fpu_mem_reg );
10788 %}
10789
10790 // Force rounding to 24-bit precision and 6-bit exponent
10791 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10792 predicate(UseSSE==0);
10793 match(Set dst (ConvD2F src));
10794 format %{ "FST_S $dst,$src\t# F-round" %}
10795 expand %{
10796 roundFloat_mem_reg(dst,src);
10797 %}
10798 %}
10799
10800 // Force rounding to 24-bit precision and 6-bit exponent
10801 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10802 predicate(UseSSE==1);
10803 match(Set dst (ConvD2F src));
10804 effect( KILL cr );
10805 format %{ "SUB ESP,4\n\t"
10806 "FST_S [ESP],$src\t# F-round\n\t"
10807 "MOVSS $dst,[ESP]\n\t"
10808 "ADD ESP,4" %}
10809 ins_encode %{
10810 __ subptr(rsp, 4);
10811 if ($src$$reg != FPR1L_enc) {
10812 __ fld_s($src$$reg-1);
10813 __ fstp_s(Address(rsp, 0));
10814 } else {
10815 __ fst_s(Address(rsp, 0));
10816 }
10817 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10818 __ addptr(rsp, 4);
10819 %}
10820 ins_pipe( pipe_slow );
10821 %}
10822
10823 // Force rounding double precision to single precision
10824 instruct convD2F_reg(regF dst, regD src) %{
10825 predicate(UseSSE>=2);
10826 match(Set dst (ConvD2F src));
10827 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10828 ins_encode %{
10829 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10830 %}
10831 ins_pipe( pipe_slow );
10832 %}
10833
10834 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10835 predicate(UseSSE==0);
10836 match(Set dst (ConvF2D src));
10837 format %{ "FST_S $dst,$src\t# D-round" %}
10838 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10839 ins_pipe( fpu_reg_reg );
10840 %}
10841
10842 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10843 predicate(UseSSE==1);
10844 match(Set dst (ConvF2D src));
10845 format %{ "FST_D $dst,$src\t# D-round" %}
10846 expand %{
10847 roundDouble_mem_reg(dst,src);
10848 %}
10849 %}
10850
10851 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10852 predicate(UseSSE==1);
10853 match(Set dst (ConvF2D src));
10854 effect( KILL cr );
10855 format %{ "SUB ESP,4\n\t"
10856 "MOVSS [ESP] $src\n\t"
10857 "FLD_S [ESP]\n\t"
10858 "ADD ESP,4\n\t"
10859 "FSTP $dst\t# D-round" %}
10860 ins_encode %{
10861 __ subptr(rsp, 4);
10862 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10863 __ fld_s(Address(rsp, 0));
10864 __ addptr(rsp, 4);
10865 __ fstp_d($dst$$reg);
10866 %}
10867 ins_pipe( pipe_slow );
10868 %}
10869
10870 instruct convF2D_reg(regD dst, regF src) %{
10871 predicate(UseSSE>=2);
10872 match(Set dst (ConvF2D src));
10873 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10874 ins_encode %{
10875 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10876 %}
10877 ins_pipe( pipe_slow );
10878 %}
10879
10880 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10881 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10882 predicate(UseSSE<=1);
10883 match(Set dst (ConvD2I src));
10884 effect( KILL tmp, KILL cr );
10885 format %{ "FLD $src\t# Convert double to int \n\t"
10886 "FLDCW trunc mode\n\t"
10887 "SUB ESP,4\n\t"
10888 "FISTp [ESP + #0]\n\t"
10889 "FLDCW std/24-bit mode\n\t"
10890 "POP EAX\n\t"
10891 "CMP EAX,0x80000000\n\t"
10892 "JNE,s fast\n\t"
10893 "FLD_D $src\n\t"
10894 "CALL d2i_wrapper\n"
10895 "fast:" %}
10896 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10897 ins_pipe( pipe_slow );
10898 %}
10899
10900 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10901 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10902 predicate(UseSSE>=2);
10903 match(Set dst (ConvD2I src));
10904 effect( KILL tmp, KILL cr );
10905 format %{ "CVTTSD2SI $dst, $src\n\t"
10906 "CMP $dst,0x80000000\n\t"
10907 "JNE,s fast\n\t"
10908 "SUB ESP, 8\n\t"
10909 "MOVSD [ESP], $src\n\t"
10910 "FLD_D [ESP]\n\t"
10911 "ADD ESP, 8\n\t"
10912 "CALL d2i_wrapper\n"
10913 "fast:" %}
10914 ins_encode %{
10915 Label fast;
10916 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10917 __ cmpl($dst$$Register, 0x80000000);
10918 __ jccb(Assembler::notEqual, fast);
10919 __ subptr(rsp, 8);
10920 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10921 __ fld_d(Address(rsp, 0));
10922 __ addptr(rsp, 8);
10923 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10924 __ bind(fast);
10925 %}
10926 ins_pipe( pipe_slow );
10927 %}
10928
10929 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10930 predicate(UseSSE<=1);
10931 match(Set dst (ConvD2L src));
10932 effect( KILL cr );
10933 format %{ "FLD $src\t# Convert double to long\n\t"
10934 "FLDCW trunc mode\n\t"
10935 "SUB ESP,8\n\t"
10936 "FISTp [ESP + #0]\n\t"
10937 "FLDCW std/24-bit mode\n\t"
10938 "POP EAX\n\t"
10939 "POP EDX\n\t"
10940 "CMP EDX,0x80000000\n\t"
10941 "JNE,s fast\n\t"
10942 "TEST EAX,EAX\n\t"
10943 "JNE,s fast\n\t"
10944 "FLD $src\n\t"
10945 "CALL d2l_wrapper\n"
10946 "fast:" %}
10947 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10948 ins_pipe( pipe_slow );
10949 %}
10950
10951 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10952 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10953 predicate (UseSSE>=2);
10954 match(Set dst (ConvD2L src));
10955 effect( KILL cr );
10956 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10957 "MOVSD [ESP],$src\n\t"
10958 "FLD_D [ESP]\n\t"
10959 "FLDCW trunc mode\n\t"
10960 "FISTp [ESP + #0]\n\t"
10961 "FLDCW std/24-bit mode\n\t"
10962 "POP EAX\n\t"
10963 "POP EDX\n\t"
10964 "CMP EDX,0x80000000\n\t"
10965 "JNE,s fast\n\t"
10966 "TEST EAX,EAX\n\t"
10967 "JNE,s fast\n\t"
10968 "SUB ESP,8\n\t"
10969 "MOVSD [ESP],$src\n\t"
10970 "FLD_D [ESP]\n\t"
10971 "ADD ESP,8\n\t"
10972 "CALL d2l_wrapper\n"
10973 "fast:" %}
10974 ins_encode %{
10975 Label fast;
10976 __ subptr(rsp, 8);
10977 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10978 __ fld_d(Address(rsp, 0));
10979 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10980 __ fistp_d(Address(rsp, 0));
10981 // Restore the rounding mode, mask the exception
10982 if (Compile::current()->in_24_bit_fp_mode()) {
10983 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10984 } else {
10985 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10986 }
10987 // Load the converted long, adjust CPU stack
10988 __ pop(rax);
10989 __ pop(rdx);
10990 __ cmpl(rdx, 0x80000000);
10991 __ jccb(Assembler::notEqual, fast);
10992 __ testl(rax, rax);
10993 __ jccb(Assembler::notEqual, fast);
10994 __ subptr(rsp, 8);
10995 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10996 __ fld_d(Address(rsp, 0));
10997 __ addptr(rsp, 8);
10998 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10999 __ bind(fast);
11000 %}
11001 ins_pipe( pipe_slow );
11002 %}
11003
11004 // Convert a double to an int. Java semantics require we do complex
11005 // manglations in the corner cases. So we set the rounding mode to
11006 // 'zero', store the darned double down as an int, and reset the
11007 // rounding mode to 'nearest'. The hardware stores a flag value down
11008 // if we would overflow or converted a NAN; we check for this and
11009 // and go the slow path if needed.
11010 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11011 predicate(UseSSE==0);
11012 match(Set dst (ConvF2I src));
11013 effect( KILL tmp, KILL cr );
11014 format %{ "FLD $src\t# Convert float to int \n\t"
11015 "FLDCW trunc mode\n\t"
11016 "SUB ESP,4\n\t"
11017 "FISTp [ESP + #0]\n\t"
11018 "FLDCW std/24-bit mode\n\t"
11019 "POP EAX\n\t"
11020 "CMP EAX,0x80000000\n\t"
11021 "JNE,s fast\n\t"
11022 "FLD $src\n\t"
11023 "CALL d2i_wrapper\n"
11024 "fast:" %}
11025 // DPR2I_encoding works for FPR2I
11026 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11027 ins_pipe( pipe_slow );
11028 %}
11029
11030 // Convert a float in xmm to an int reg.
11031 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11032 predicate(UseSSE>=1);
11033 match(Set dst (ConvF2I src));
11034 effect( KILL tmp, KILL cr );
11035 format %{ "CVTTSS2SI $dst, $src\n\t"
11036 "CMP $dst,0x80000000\n\t"
11037 "JNE,s fast\n\t"
11038 "SUB ESP, 4\n\t"
11039 "MOVSS [ESP], $src\n\t"
11040 "FLD [ESP]\n\t"
11041 "ADD ESP, 4\n\t"
11042 "CALL d2i_wrapper\n"
11043 "fast:" %}
11044 ins_encode %{
11045 Label fast;
11046 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11047 __ cmpl($dst$$Register, 0x80000000);
11048 __ jccb(Assembler::notEqual, fast);
11049 __ subptr(rsp, 4);
11050 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11051 __ fld_s(Address(rsp, 0));
11052 __ addptr(rsp, 4);
11053 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11054 __ bind(fast);
11055 %}
11056 ins_pipe( pipe_slow );
11057 %}
11058
11059 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11060 predicate(UseSSE==0);
11061 match(Set dst (ConvF2L src));
11062 effect( KILL cr );
11063 format %{ "FLD $src\t# Convert float to long\n\t"
11064 "FLDCW trunc mode\n\t"
11065 "SUB ESP,8\n\t"
11066 "FISTp [ESP + #0]\n\t"
11067 "FLDCW std/24-bit mode\n\t"
11068 "POP EAX\n\t"
11069 "POP EDX\n\t"
11070 "CMP EDX,0x80000000\n\t"
11071 "JNE,s fast\n\t"
11072 "TEST EAX,EAX\n\t"
11073 "JNE,s fast\n\t"
11074 "FLD $src\n\t"
11075 "CALL d2l_wrapper\n"
11076 "fast:" %}
11077 // DPR2L_encoding works for FPR2L
11078 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11079 ins_pipe( pipe_slow );
11080 %}
11081
11082 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11083 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11084 predicate (UseSSE>=1);
11085 match(Set dst (ConvF2L src));
11086 effect( KILL cr );
11087 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11088 "MOVSS [ESP],$src\n\t"
11089 "FLD_S [ESP]\n\t"
11090 "FLDCW trunc mode\n\t"
11091 "FISTp [ESP + #0]\n\t"
11092 "FLDCW std/24-bit mode\n\t"
11093 "POP EAX\n\t"
11094 "POP EDX\n\t"
11095 "CMP EDX,0x80000000\n\t"
11096 "JNE,s fast\n\t"
11097 "TEST EAX,EAX\n\t"
11098 "JNE,s fast\n\t"
11099 "SUB ESP,4\t# Convert float to long\n\t"
11100 "MOVSS [ESP],$src\n\t"
11101 "FLD_S [ESP]\n\t"
11102 "ADD ESP,4\n\t"
11103 "CALL d2l_wrapper\n"
11104 "fast:" %}
11105 ins_encode %{
11106 Label fast;
11107 __ subptr(rsp, 8);
11108 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11109 __ fld_s(Address(rsp, 0));
11110 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11111 __ fistp_d(Address(rsp, 0));
11112 // Restore the rounding mode, mask the exception
11113 if (Compile::current()->in_24_bit_fp_mode()) {
11114 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11115 } else {
11116 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11117 }
11118 // Load the converted long, adjust CPU stack
11119 __ pop(rax);
11120 __ pop(rdx);
11121 __ cmpl(rdx, 0x80000000);
11122 __ jccb(Assembler::notEqual, fast);
11123 __ testl(rax, rax);
11124 __ jccb(Assembler::notEqual, fast);
11125 __ subptr(rsp, 4);
11126 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11127 __ fld_s(Address(rsp, 0));
11128 __ addptr(rsp, 4);
11129 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11130 __ bind(fast);
11131 %}
11132 ins_pipe( pipe_slow );
11133 %}
11134
11135 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11136 predicate( UseSSE<=1 );
11137 match(Set dst (ConvI2D src));
11138 format %{ "FILD $src\n\t"
11139 "FSTP $dst" %}
11140 opcode(0xDB, 0x0); /* DB /0 */
11141 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11142 ins_pipe( fpu_reg_mem );
11143 %}
11144
11145 instruct convI2D_reg(regD dst, rRegI src) %{
11146 predicate( UseSSE>=2 && !UseXmmI2D );
11147 match(Set dst (ConvI2D src));
11148 format %{ "CVTSI2SD $dst,$src" %}
11149 ins_encode %{
11150 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11151 %}
11152 ins_pipe( pipe_slow );
11153 %}
11154
11155 instruct convI2D_mem(regD dst, memory mem) %{
11156 predicate( UseSSE>=2 );
11157 match(Set dst (ConvI2D (LoadI mem)));
11158 format %{ "CVTSI2SD $dst,$mem" %}
11159 ins_encode %{
11160 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11161 %}
11162 ins_pipe( pipe_slow );
11163 %}
11164
11165 instruct convXI2D_reg(regD dst, rRegI src)
11166 %{
11167 predicate( UseSSE>=2 && UseXmmI2D );
11168 match(Set dst (ConvI2D src));
11169
11170 format %{ "MOVD $dst,$src\n\t"
11171 "CVTDQ2PD $dst,$dst\t# i2d" %}
11172 ins_encode %{
11173 __ movdl($dst$$XMMRegister, $src$$Register);
11174 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11175 %}
11176 ins_pipe(pipe_slow); // XXX
11177 %}
11178
11179 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11180 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11181 match(Set dst (ConvI2D (LoadI mem)));
11182 format %{ "FILD $mem\n\t"
11183 "FSTP $dst" %}
11184 opcode(0xDB); /* DB /0 */
11185 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11186 Pop_Reg_DPR(dst));
11187 ins_pipe( fpu_reg_mem );
11188 %}
11189
11190 // Convert a byte to a float; no rounding step needed.
11191 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11192 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11193 match(Set dst (ConvI2F src));
11194 format %{ "FILD $src\n\t"
11195 "FSTP $dst" %}
11196
11197 opcode(0xDB, 0x0); /* DB /0 */
11198 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11199 ins_pipe( fpu_reg_mem );
11200 %}
11201
11202 // In 24-bit mode, force exponent rounding by storing back out
11203 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11204 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11205 match(Set dst (ConvI2F src));
11206 ins_cost(200);
11207 format %{ "FILD $src\n\t"
11208 "FSTP_S $dst" %}
11209 opcode(0xDB, 0x0); /* DB /0 */
11210 ins_encode( Push_Mem_I(src),
11211 Pop_Mem_FPR(dst));
11212 ins_pipe( fpu_mem_mem );
11213 %}
11214
11215 // In 24-bit mode, force exponent rounding by storing back out
11216 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11217 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11218 match(Set dst (ConvI2F (LoadI mem)));
11219 ins_cost(200);
11220 format %{ "FILD $mem\n\t"
11221 "FSTP_S $dst" %}
11222 opcode(0xDB); /* DB /0 */
11223 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11224 Pop_Mem_FPR(dst));
11225 ins_pipe( fpu_mem_mem );
11226 %}
11227
11228 // This instruction does not round to 24-bits
11229 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11230 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11231 match(Set dst (ConvI2F src));
11232 format %{ "FILD $src\n\t"
11233 "FSTP $dst" %}
11234 opcode(0xDB, 0x0); /* DB /0 */
11235 ins_encode( Push_Mem_I(src),
11236 Pop_Reg_FPR(dst));
11237 ins_pipe( fpu_reg_mem );
11238 %}
11239
11240 // This instruction does not round to 24-bits
11241 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11242 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11243 match(Set dst (ConvI2F (LoadI mem)));
11244 format %{ "FILD $mem\n\t"
11245 "FSTP $dst" %}
11246 opcode(0xDB); /* DB /0 */
11247 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11248 Pop_Reg_FPR(dst));
11249 ins_pipe( fpu_reg_mem );
11250 %}
11251
11252 // Convert an int to a float in xmm; no rounding step needed.
11253 instruct convI2F_reg(regF dst, rRegI src) %{
11254 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11255 match(Set dst (ConvI2F src));
11256 format %{ "CVTSI2SS $dst, $src" %}
11257 ins_encode %{
11258 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11259 %}
11260 ins_pipe( pipe_slow );
11261 %}
11262
11263 instruct convXI2F_reg(regF dst, rRegI src)
11264 %{
11265 predicate( UseSSE>=2 && UseXmmI2F );
11266 match(Set dst (ConvI2F src));
11267
11268 format %{ "MOVD $dst,$src\n\t"
11269 "CVTDQ2PS $dst,$dst\t# i2f" %}
11270 ins_encode %{
11271 __ movdl($dst$$XMMRegister, $src$$Register);
11272 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11273 %}
11274 ins_pipe(pipe_slow); // XXX
11275 %}
11276
11277 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11278 match(Set dst (ConvI2L src));
11279 effect(KILL cr);
11280 ins_cost(375);
11281 format %{ "MOV $dst.lo,$src\n\t"
11282 "MOV $dst.hi,$src\n\t"
11283 "SAR $dst.hi,31" %}
11284 ins_encode(convert_int_long(dst,src));
11285 ins_pipe( ialu_reg_reg_long );
11286 %}
11287
11288 // Zero-extend convert int to long
11289 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11290 match(Set dst (AndL (ConvI2L src) mask) );
11291 effect( KILL flags );
11292 ins_cost(250);
11293 format %{ "MOV $dst.lo,$src\n\t"
11294 "XOR $dst.hi,$dst.hi" %}
11295 opcode(0x33); // XOR
11296 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11297 ins_pipe( ialu_reg_reg_long );
11298 %}
11299
11300 // Zero-extend long
11301 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11302 match(Set dst (AndL src mask) );
11303 effect( KILL flags );
11304 ins_cost(250);
11305 format %{ "MOV $dst.lo,$src.lo\n\t"
11306 "XOR $dst.hi,$dst.hi\n\t" %}
11307 opcode(0x33); // XOR
11308 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11309 ins_pipe( ialu_reg_reg_long );
11310 %}
11311
11312 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11313 predicate (UseSSE<=1);
11314 match(Set dst (ConvL2D src));
11315 effect( KILL cr );
11316 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11317 "PUSH $src.lo\n\t"
11318 "FILD ST,[ESP + #0]\n\t"
11319 "ADD ESP,8\n\t"
11320 "FSTP_D $dst\t# D-round" %}
11321 opcode(0xDF, 0x5); /* DF /5 */
11322 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11323 ins_pipe( pipe_slow );
11324 %}
11325
11326 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11327 predicate (UseSSE>=2);
11328 match(Set dst (ConvL2D src));
11329 effect( KILL cr );
11330 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11331 "PUSH $src.lo\n\t"
11332 "FILD_D [ESP]\n\t"
11333 "FSTP_D [ESP]\n\t"
11334 "MOVSD $dst,[ESP]\n\t"
11335 "ADD ESP,8" %}
11336 opcode(0xDF, 0x5); /* DF /5 */
11337 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11338 ins_pipe( pipe_slow );
11339 %}
11340
11341 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11342 predicate (UseSSE>=1);
11343 match(Set dst (ConvL2F src));
11344 effect( KILL cr );
11345 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11346 "PUSH $src.lo\n\t"
11347 "FILD_D [ESP]\n\t"
11348 "FSTP_S [ESP]\n\t"
11349 "MOVSS $dst,[ESP]\n\t"
11350 "ADD ESP,8" %}
11351 opcode(0xDF, 0x5); /* DF /5 */
11352 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11353 ins_pipe( pipe_slow );
11354 %}
11355
11356 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11357 match(Set dst (ConvL2F src));
11358 effect( KILL cr );
11359 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11360 "PUSH $src.lo\n\t"
11361 "FILD ST,[ESP + #0]\n\t"
11362 "ADD ESP,8\n\t"
11363 "FSTP_S $dst\t# F-round" %}
11364 opcode(0xDF, 0x5); /* DF /5 */
11365 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11366 ins_pipe( pipe_slow );
11367 %}
11368
11369 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11370 match(Set dst (ConvL2I src));
11371 effect( DEF dst, USE src );
11372 format %{ "MOV $dst,$src.lo" %}
11373 ins_encode(enc_CopyL_Lo(dst,src));
11374 ins_pipe( ialu_reg_reg );
11375 %}
11376
11377
11378 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11379 match(Set dst (MoveF2I src));
11380 effect( DEF dst, USE src );
11381 ins_cost(100);
11382 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11383 ins_encode %{
11384 __ movl($dst$$Register, Address(rsp, $src$$disp));
11385 %}
11386 ins_pipe( ialu_reg_mem );
11387 %}
11388
11389 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11390 predicate(UseSSE==0);
11391 match(Set dst (MoveF2I src));
11392 effect( DEF dst, USE src );
11393
11394 ins_cost(125);
11395 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11396 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11397 ins_pipe( fpu_mem_reg );
11398 %}
11399
11400 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11401 predicate(UseSSE>=1);
11402 match(Set dst (MoveF2I src));
11403 effect( DEF dst, USE src );
11404
11405 ins_cost(95);
11406 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11407 ins_encode %{
11408 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11409 %}
11410 ins_pipe( pipe_slow );
11411 %}
11412
11413 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11414 predicate(UseSSE>=2);
11415 match(Set dst (MoveF2I src));
11416 effect( DEF dst, USE src );
11417 ins_cost(85);
11418 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11419 ins_encode %{
11420 __ movdl($dst$$Register, $src$$XMMRegister);
11421 %}
11422 ins_pipe( pipe_slow );
11423 %}
11424
11425 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11426 match(Set dst (MoveI2F src));
11427 effect( DEF dst, USE src );
11428
11429 ins_cost(100);
11430 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11431 ins_encode %{
11432 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11433 %}
11434 ins_pipe( ialu_mem_reg );
11435 %}
11436
11437
11438 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11439 predicate(UseSSE==0);
11440 match(Set dst (MoveI2F src));
11441 effect(DEF dst, USE src);
11442
11443 ins_cost(125);
11444 format %{ "FLD_S $src\n\t"
11445 "FSTP $dst\t# MoveI2F_stack_reg" %}
11446 opcode(0xD9); /* D9 /0, FLD m32real */
11447 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11448 Pop_Reg_FPR(dst) );
11449 ins_pipe( fpu_reg_mem );
11450 %}
11451
11452 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11453 predicate(UseSSE>=1);
11454 match(Set dst (MoveI2F src));
11455 effect( DEF dst, USE src );
11456
11457 ins_cost(95);
11458 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11459 ins_encode %{
11460 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11461 %}
11462 ins_pipe( pipe_slow );
11463 %}
11464
11465 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11466 predicate(UseSSE>=2);
11467 match(Set dst (MoveI2F src));
11468 effect( DEF dst, USE src );
11469
11470 ins_cost(85);
11471 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11472 ins_encode %{
11473 __ movdl($dst$$XMMRegister, $src$$Register);
11474 %}
11475 ins_pipe( pipe_slow );
11476 %}
11477
11478 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11479 match(Set dst (MoveD2L src));
11480 effect(DEF dst, USE src);
11481
11482 ins_cost(250);
11483 format %{ "MOV $dst.lo,$src\n\t"
11484 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11485 opcode(0x8B, 0x8B);
11486 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11487 ins_pipe( ialu_mem_long_reg );
11488 %}
11489
11490 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11491 predicate(UseSSE<=1);
11492 match(Set dst (MoveD2L src));
11493 effect(DEF dst, USE src);
11494
11495 ins_cost(125);
11496 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11497 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11498 ins_pipe( fpu_mem_reg );
11499 %}
11500
11501 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11502 predicate(UseSSE>=2);
11503 match(Set dst (MoveD2L src));
11504 effect(DEF dst, USE src);
11505 ins_cost(95);
11506 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11507 ins_encode %{
11508 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11509 %}
11510 ins_pipe( pipe_slow );
11511 %}
11512
11513 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11514 predicate(UseSSE>=2);
11515 match(Set dst (MoveD2L src));
11516 effect(DEF dst, USE src, TEMP tmp);
11517 ins_cost(85);
11518 format %{ "MOVD $dst.lo,$src\n\t"
11519 "PSHUFLW $tmp,$src,0x4E\n\t"
11520 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11521 ins_encode %{
11522 __ movdl($dst$$Register, $src$$XMMRegister);
11523 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11524 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11525 %}
11526 ins_pipe( pipe_slow );
11527 %}
11528
11529 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11530 match(Set dst (MoveL2D src));
11531 effect(DEF dst, USE src);
11532
11533 ins_cost(200);
11534 format %{ "MOV $dst,$src.lo\n\t"
11535 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11536 opcode(0x89, 0x89);
11537 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11538 ins_pipe( ialu_mem_long_reg );
11539 %}
11540
11541
11542 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11543 predicate(UseSSE<=1);
11544 match(Set dst (MoveL2D src));
11545 effect(DEF dst, USE src);
11546 ins_cost(125);
11547
11548 format %{ "FLD_D $src\n\t"
11549 "FSTP $dst\t# MoveL2D_stack_reg" %}
11550 opcode(0xDD); /* DD /0, FLD m64real */
11551 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11552 Pop_Reg_DPR(dst) );
11553 ins_pipe( fpu_reg_mem );
11554 %}
11555
11556
11557 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11558 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11559 match(Set dst (MoveL2D src));
11560 effect(DEF dst, USE src);
11561
11562 ins_cost(95);
11563 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11564 ins_encode %{
11565 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11566 %}
11567 ins_pipe( pipe_slow );
11568 %}
11569
11570 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11571 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11572 match(Set dst (MoveL2D src));
11573 effect(DEF dst, USE src);
11574
11575 ins_cost(95);
11576 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11577 ins_encode %{
11578 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11579 %}
11580 ins_pipe( pipe_slow );
11581 %}
11582
11583 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11584 predicate(UseSSE>=2);
11585 match(Set dst (MoveL2D src));
11586 effect(TEMP dst, USE src, TEMP tmp);
11587 ins_cost(85);
11588 format %{ "MOVD $dst,$src.lo\n\t"
11589 "MOVD $tmp,$src.hi\n\t"
11590 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11591 ins_encode %{
11592 __ movdl($dst$$XMMRegister, $src$$Register);
11593 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11594 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11595 %}
11596 ins_pipe( pipe_slow );
11597 %}
11598
11599
11600 // =======================================================================
11601 // fast clearing of an array
11602 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11603 match(Set dummy (ClearArray cnt base));
11604 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11605 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11606 "XOR EAX,EAX\n\t"
11607 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11608 opcode(0,0x4);
11609 ins_encode( Opcode(0xD1), RegOpc(ECX),
11610 OpcRegReg(0x33,EAX,EAX),
11611 Opcode(0xF3), Opcode(0xAB) );
11612 ins_pipe( pipe_slow );
11613 %}
11614
11615 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11616 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11617 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11618 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11619
11620 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11621 ins_encode %{
11622 __ string_compare($str1$$Register, $str2$$Register,
11623 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11624 $tmp1$$XMMRegister);
11625 %}
11626 ins_pipe( pipe_slow );
11627 %}
11628
11629 // fast string equals
11630 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11631 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11632 match(Set result (StrEquals (Binary str1 str2) cnt));
11633 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11634
11635 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11636 ins_encode %{
11637 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11638 $cnt$$Register, $result$$Register, $tmp3$$Register,
11639 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11640 %}
11641 ins_pipe( pipe_slow );
11642 %}
11643
11644 // fast search of substring with known size.
11645 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11646 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11647 predicate(UseSSE42Intrinsics);
11648 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11649 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11650
11651 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11652 ins_encode %{
11653 int icnt2 = (int)$int_cnt2$$constant;
11654 if (icnt2 >= 8) {
11655 // IndexOf for constant substrings with size >= 8 elements
11656 // which don't need to be loaded through stack.
11657 __ string_indexofC8($str1$$Register, $str2$$Register,
11658 $cnt1$$Register, $cnt2$$Register,
11659 icnt2, $result$$Register,
11660 $vec$$XMMRegister, $tmp$$Register);
11661 } else {
11662 // Small strings are loaded through stack if they cross page boundary.
11663 __ string_indexof($str1$$Register, $str2$$Register,
11664 $cnt1$$Register, $cnt2$$Register,
11665 icnt2, $result$$Register,
11666 $vec$$XMMRegister, $tmp$$Register);
11667 }
11668 %}
11669 ins_pipe( pipe_slow );
11670 %}
11671
11672 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11673 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11674 predicate(UseSSE42Intrinsics);
11675 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11676 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11677
11678 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11679 ins_encode %{
11680 __ string_indexof($str1$$Register, $str2$$Register,
11681 $cnt1$$Register, $cnt2$$Register,
11682 (-1), $result$$Register,
11683 $vec$$XMMRegister, $tmp$$Register);
11684 %}
11685 ins_pipe( pipe_slow );
11686 %}
11687
11688 // fast array equals
11689 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11690 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11691 %{
11692 match(Set result (AryEq ary1 ary2));
11693 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11694 //ins_cost(300);
11695
11696 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11697 ins_encode %{
11698 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11699 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11700 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11701 %}
11702 ins_pipe( pipe_slow );
11703 %}
11704
11705 //----------Control Flow Instructions------------------------------------------
11706 // Signed compare Instructions
11707 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11708 match(Set cr (CmpI op1 op2));
11709 effect( DEF cr, USE op1, USE op2 );
11710 format %{ "CMP $op1,$op2" %}
11711 opcode(0x3B); /* Opcode 3B /r */
11712 ins_encode( OpcP, RegReg( op1, op2) );
11713 ins_pipe( ialu_cr_reg_reg );
11714 %}
11715
11716 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11717 match(Set cr (CmpI op1 op2));
11718 effect( DEF cr, USE op1 );
11719 format %{ "CMP $op1,$op2" %}
11720 opcode(0x81,0x07); /* Opcode 81 /7 */
11721 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11722 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11723 ins_pipe( ialu_cr_reg_imm );
11724 %}
11725
11726 // Cisc-spilled version of cmpI_eReg
11727 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11728 match(Set cr (CmpI op1 (LoadI op2)));
11729
11730 format %{ "CMP $op1,$op2" %}
11731 ins_cost(500);
11732 opcode(0x3B); /* Opcode 3B /r */
11733 ins_encode( OpcP, RegMem( op1, op2) );
11734 ins_pipe( ialu_cr_reg_mem );
11735 %}
11736
11737 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11738 match(Set cr (CmpI src zero));
11739 effect( DEF cr, USE src );
11740
11741 format %{ "TEST $src,$src" %}
11742 opcode(0x85);
11743 ins_encode( OpcP, RegReg( src, src ) );
11744 ins_pipe( ialu_cr_reg_imm );
11745 %}
11746
11747 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11748 match(Set cr (CmpI (AndI src con) zero));
11749
11750 format %{ "TEST $src,$con" %}
11751 opcode(0xF7,0x00);
11752 ins_encode( OpcP, RegOpc(src), Con32(con) );
11753 ins_pipe( ialu_cr_reg_imm );
11754 %}
11755
11756 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11757 match(Set cr (CmpI (AndI src mem) zero));
11758
11759 format %{ "TEST $src,$mem" %}
11760 opcode(0x85);
11761 ins_encode( OpcP, RegMem( src, mem ) );
11762 ins_pipe( ialu_cr_reg_mem );
11763 %}
11764
11765 // Unsigned compare Instructions; really, same as signed except they
11766 // produce an eFlagsRegU instead of eFlagsReg.
11767 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11768 match(Set cr (CmpU op1 op2));
11769
11770 format %{ "CMPu $op1,$op2" %}
11771 opcode(0x3B); /* Opcode 3B /r */
11772 ins_encode( OpcP, RegReg( op1, op2) );
11773 ins_pipe( ialu_cr_reg_reg );
11774 %}
11775
11776 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11777 match(Set cr (CmpU op1 op2));
11778
11779 format %{ "CMPu $op1,$op2" %}
11780 opcode(0x81,0x07); /* Opcode 81 /7 */
11781 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11782 ins_pipe( ialu_cr_reg_imm );
11783 %}
11784
11785 // // Cisc-spilled version of cmpU_eReg
11786 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11787 match(Set cr (CmpU op1 (LoadI op2)));
11788
11789 format %{ "CMPu $op1,$op2" %}
11790 ins_cost(500);
11791 opcode(0x3B); /* Opcode 3B /r */
11792 ins_encode( OpcP, RegMem( op1, op2) );
11793 ins_pipe( ialu_cr_reg_mem );
11794 %}
11795
11796 // // Cisc-spilled version of cmpU_eReg
11797 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11798 // match(Set cr (CmpU (LoadI op1) op2));
11799 //
11800 // format %{ "CMPu $op1,$op2" %}
11801 // ins_cost(500);
11802 // opcode(0x39); /* Opcode 39 /r */
11803 // ins_encode( OpcP, RegMem( op1, op2) );
11804 //%}
11805
11806 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11807 match(Set cr (CmpU src zero));
11808
11809 format %{ "TESTu $src,$src" %}
11810 opcode(0x85);
11811 ins_encode( OpcP, RegReg( src, src ) );
11812 ins_pipe( ialu_cr_reg_imm );
11813 %}
11814
11815 // Unsigned pointer compare Instructions
11816 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11817 match(Set cr (CmpP op1 op2));
11818
11819 format %{ "CMPu $op1,$op2" %}
11820 opcode(0x3B); /* Opcode 3B /r */
11821 ins_encode( OpcP, RegReg( op1, op2) );
11822 ins_pipe( ialu_cr_reg_reg );
11823 %}
11824
11825 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11826 match(Set cr (CmpP op1 op2));
11827
11828 format %{ "CMPu $op1,$op2" %}
11829 opcode(0x81,0x07); /* Opcode 81 /7 */
11830 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11831 ins_pipe( ialu_cr_reg_imm );
11832 %}
11833
11834 // // Cisc-spilled version of cmpP_eReg
11835 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11836 match(Set cr (CmpP op1 (LoadP op2)));
11837
11838 format %{ "CMPu $op1,$op2" %}
11839 ins_cost(500);
11840 opcode(0x3B); /* Opcode 3B /r */
11841 ins_encode( OpcP, RegMem( op1, op2) );
11842 ins_pipe( ialu_cr_reg_mem );
11843 %}
11844
11845 // // Cisc-spilled version of cmpP_eReg
11846 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11847 // match(Set cr (CmpP (LoadP op1) op2));
11848 //
11849 // format %{ "CMPu $op1,$op2" %}
11850 // ins_cost(500);
11851 // opcode(0x39); /* Opcode 39 /r */
11852 // ins_encode( OpcP, RegMem( op1, op2) );
11853 //%}
11854
11855 // Compare raw pointer (used in out-of-heap check).
11856 // Only works because non-oop pointers must be raw pointers
11857 // and raw pointers have no anti-dependencies.
11858 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11859 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
11860 match(Set cr (CmpP op1 (LoadP op2)));
11861
11862 format %{ "CMPu $op1,$op2" %}
11863 opcode(0x3B); /* Opcode 3B /r */
11864 ins_encode( OpcP, RegMem( op1, op2) );
11865 ins_pipe( ialu_cr_reg_mem );
11866 %}
11867
11868 //
11869 // This will generate a signed flags result. This should be ok
11870 // since any compare to a zero should be eq/neq.
11871 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11872 match(Set cr (CmpP src zero));
11873
11874 format %{ "TEST $src,$src" %}
11875 opcode(0x85);
11876 ins_encode( OpcP, RegReg( src, src ) );
11877 ins_pipe( ialu_cr_reg_imm );
11878 %}
11879
11880 // Cisc-spilled version of testP_reg
11881 // This will generate a signed flags result. This should be ok
11882 // since any compare to a zero should be eq/neq.
11883 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11884 match(Set cr (CmpP (LoadP op) zero));
11885
11886 format %{ "TEST $op,0xFFFFFFFF" %}
11887 ins_cost(500);
11888 opcode(0xF7); /* Opcode F7 /0 */
11889 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11890 ins_pipe( ialu_cr_reg_imm );
11891 %}
11892
11893 // Yanked all unsigned pointer compare operations.
11894 // Pointer compares are done with CmpP which is already unsigned.
11895
11896 //----------Max and Min--------------------------------------------------------
11897 // Min Instructions
11898 ////
11899 // *** Min and Max using the conditional move are slower than the
11900 // *** branch version on a Pentium III.
11901 // // Conditional move for min
11902 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11903 // effect( USE_DEF op2, USE op1, USE cr );
11904 // format %{ "CMOVlt $op2,$op1\t! min" %}
11905 // opcode(0x4C,0x0F);
11906 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11907 // ins_pipe( pipe_cmov_reg );
11908 //%}
11909 //
11910 //// Min Register with Register (P6 version)
11911 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11912 // predicate(VM_Version::supports_cmov() );
11913 // match(Set op2 (MinI op1 op2));
11914 // ins_cost(200);
11915 // expand %{
11916 // eFlagsReg cr;
11917 // compI_eReg(cr,op1,op2);
11918 // cmovI_reg_lt(op2,op1,cr);
11919 // %}
11920 //%}
11921
11922 // Min Register with Register (generic version)
11923 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11924 match(Set dst (MinI dst src));
11925 effect(KILL flags);
11926 ins_cost(300);
11927
11928 format %{ "MIN $dst,$src" %}
11929 opcode(0xCC);
11930 ins_encode( min_enc(dst,src) );
11931 ins_pipe( pipe_slow );
11932 %}
11933
11934 // Max Register with Register
11935 // *** Min and Max using the conditional move are slower than the
11936 // *** branch version on a Pentium III.
11937 // // Conditional move for max
11938 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11939 // effect( USE_DEF op2, USE op1, USE cr );
11940 // format %{ "CMOVgt $op2,$op1\t! max" %}
11941 // opcode(0x4F,0x0F);
11942 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11943 // ins_pipe( pipe_cmov_reg );
11944 //%}
11945 //
11946 // // Max Register with Register (P6 version)
11947 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11948 // predicate(VM_Version::supports_cmov() );
11949 // match(Set op2 (MaxI op1 op2));
11950 // ins_cost(200);
11951 // expand %{
11952 // eFlagsReg cr;
11953 // compI_eReg(cr,op1,op2);
11954 // cmovI_reg_gt(op2,op1,cr);
11955 // %}
11956 //%}
11957
11958 // Max Register with Register (generic version)
11959 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11960 match(Set dst (MaxI dst src));
11961 effect(KILL flags);
11962 ins_cost(300);
11963
11964 format %{ "MAX $dst,$src" %}
11965 opcode(0xCC);
11966 ins_encode( max_enc(dst,src) );
11967 ins_pipe( pipe_slow );
11968 %}
11969
11970 // ============================================================================
11971 // Counted Loop limit node which represents exact final iterator value.
11972 // Note: the resulting value should fit into integer range since
11973 // counted loops have limit check on overflow.
11974 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11975 match(Set limit (LoopLimit (Binary init limit) stride));
11976 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11977 ins_cost(300);
11978
11979 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11980 ins_encode %{
11981 int strd = (int)$stride$$constant;
11982 assert(strd != 1 && strd != -1, "sanity");
11983 int m1 = (strd > 0) ? 1 : -1;
11984 // Convert limit to long (EAX:EDX)
11985 __ cdql();
11986 // Convert init to long (init:tmp)
11987 __ movl($tmp$$Register, $init$$Register);
11988 __ sarl($tmp$$Register, 31);
11989 // $limit - $init
11990 __ subl($limit$$Register, $init$$Register);
11991 __ sbbl($limit_hi$$Register, $tmp$$Register);
11992 // + ($stride - 1)
11993 if (strd > 0) {
11994 __ addl($limit$$Register, (strd - 1));
11995 __ adcl($limit_hi$$Register, 0);
11996 __ movl($tmp$$Register, strd);
11997 } else {
11998 __ addl($limit$$Register, (strd + 1));
11999 __ adcl($limit_hi$$Register, -1);
12000 __ lneg($limit_hi$$Register, $limit$$Register);
12001 __ movl($tmp$$Register, -strd);
12002 }
12003 // signed devision: (EAX:EDX) / pos_stride
12004 __ idivl($tmp$$Register);
12005 if (strd < 0) {
12006 // restore sign
12007 __ negl($tmp$$Register);
12008 }
12009 // (EAX) * stride
12010 __ mull($tmp$$Register);
12011 // + init (ignore upper bits)
12012 __ addl($limit$$Register, $init$$Register);
12013 %}
12014 ins_pipe( pipe_slow );
12015 %}
12016
12017 // ============================================================================
12018 // Branch Instructions
12019 // Jump Table
12020 instruct jumpXtnd(rRegI switch_val) %{
12021 match(Jump switch_val);
12022 ins_cost(350);
12023 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12024 ins_encode %{
12025 // Jump to Address(table_base + switch_reg)
12026 Address index(noreg, $switch_val$$Register, Address::times_1);
12027 __ jump(ArrayAddress($constantaddress, index));
12028 %}
12029 ins_pipe(pipe_jmp);
12030 %}
12031
12032 // Jump Direct - Label defines a relative address from JMP+1
12033 instruct jmpDir(label labl) %{
12034 match(Goto);
12035 effect(USE labl);
12036
12037 ins_cost(300);
12038 format %{ "JMP $labl" %}
12039 size(5);
12040 ins_encode %{
12041 Label* L = $labl$$label;
12042 __ jmp(*L, false); // Always long jump
12043 %}
12044 ins_pipe( pipe_jmp );
12045 %}
12046
12047 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12048 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12049 match(If cop cr);
12050 effect(USE labl);
12051
12052 ins_cost(300);
12053 format %{ "J$cop $labl" %}
12054 size(6);
12055 ins_encode %{
12056 Label* L = $labl$$label;
12057 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12058 %}
12059 ins_pipe( pipe_jcc );
12060 %}
12061
12062 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12063 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12064 match(CountedLoopEnd cop cr);
12065 effect(USE labl);
12066
12067 ins_cost(300);
12068 format %{ "J$cop $labl\t# Loop end" %}
12069 size(6);
12070 ins_encode %{
12071 Label* L = $labl$$label;
12072 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12073 %}
12074 ins_pipe( pipe_jcc );
12075 %}
12076
12077 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12078 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12079 match(CountedLoopEnd cop cmp);
12080 effect(USE labl);
12081
12082 ins_cost(300);
12083 format %{ "J$cop,u $labl\t# Loop end" %}
12084 size(6);
12085 ins_encode %{
12086 Label* L = $labl$$label;
12087 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12088 %}
12089 ins_pipe( pipe_jcc );
12090 %}
12091
12092 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12093 match(CountedLoopEnd cop cmp);
12094 effect(USE labl);
12095
12096 ins_cost(200);
12097 format %{ "J$cop,u $labl\t# Loop end" %}
12098 size(6);
12099 ins_encode %{
12100 Label* L = $labl$$label;
12101 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12102 %}
12103 ins_pipe( pipe_jcc );
12104 %}
12105
12106 // Jump Direct Conditional - using unsigned comparison
12107 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12108 match(If cop cmp);
12109 effect(USE labl);
12110
12111 ins_cost(300);
12112 format %{ "J$cop,u $labl" %}
12113 size(6);
12114 ins_encode %{
12115 Label* L = $labl$$label;
12116 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12117 %}
12118 ins_pipe(pipe_jcc);
12119 %}
12120
12121 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12122 match(If cop cmp);
12123 effect(USE labl);
12124
12125 ins_cost(200);
12126 format %{ "J$cop,u $labl" %}
12127 size(6);
12128 ins_encode %{
12129 Label* L = $labl$$label;
12130 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12131 %}
12132 ins_pipe(pipe_jcc);
12133 %}
12134
12135 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12136 match(If cop cmp);
12137 effect(USE labl);
12138
12139 ins_cost(200);
12140 format %{ $$template
12141 if ($cop$$cmpcode == Assembler::notEqual) {
12142 $$emit$$"JP,u $labl\n\t"
12143 $$emit$$"J$cop,u $labl"
12144 } else {
12145 $$emit$$"JP,u done\n\t"
12146 $$emit$$"J$cop,u $labl\n\t"
12147 $$emit$$"done:"
12148 }
12149 %}
12150 ins_encode %{
12151 Label* l = $labl$$label;
12152 if ($cop$$cmpcode == Assembler::notEqual) {
12153 __ jcc(Assembler::parity, *l, false);
12154 __ jcc(Assembler::notEqual, *l, false);
12155 } else if ($cop$$cmpcode == Assembler::equal) {
12156 Label done;
12157 __ jccb(Assembler::parity, done);
12158 __ jcc(Assembler::equal, *l, false);
12159 __ bind(done);
12160 } else {
12161 ShouldNotReachHere();
12162 }
12163 %}
12164 ins_pipe(pipe_jcc);
12165 %}
12166
12167 // ============================================================================
12168 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12169 // array for an instance of the superklass. Set a hidden internal cache on a
12170 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12171 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12172 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12173 match(Set result (PartialSubtypeCheck sub super));
12174 effect( KILL rcx, KILL cr );
12175
12176 ins_cost(1100); // slightly larger than the next version
12177 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12178 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12179 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12180 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12181 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12182 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12183 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12184 "miss:\t" %}
12185
12186 opcode(0x1); // Force a XOR of EDI
12187 ins_encode( enc_PartialSubtypeCheck() );
12188 ins_pipe( pipe_slow );
12189 %}
12190
12191 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12192 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12193 effect( KILL rcx, KILL result );
12194
12195 ins_cost(1000);
12196 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12197 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12198 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12199 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12200 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12201 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12202 "miss:\t" %}
12203
12204 opcode(0x0); // No need to XOR EDI
12205 ins_encode( enc_PartialSubtypeCheck() );
12206 ins_pipe( pipe_slow );
12207 %}
12208
12209 // ============================================================================
12210 // Branch Instructions -- short offset versions
12211 //
12212 // These instructions are used to replace jumps of a long offset (the default
12213 // match) with jumps of a shorter offset. These instructions are all tagged
12214 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12215 // match rules in general matching. Instead, the ADLC generates a conversion
12216 // method in the MachNode which can be used to do in-place replacement of the
12217 // long variant with the shorter variant. The compiler will determine if a
12218 // branch can be taken by the is_short_branch_offset() predicate in the machine
12219 // specific code section of the file.
12220
12221 // Jump Direct - Label defines a relative address from JMP+1
12222 instruct jmpDir_short(label labl) %{
12223 match(Goto);
12224 effect(USE labl);
12225
12226 ins_cost(300);
12227 format %{ "JMP,s $labl" %}
12228 size(2);
12229 ins_encode %{
12230 Label* L = $labl$$label;
12231 __ jmpb(*L);
12232 %}
12233 ins_pipe( pipe_jmp );
12234 ins_short_branch(1);
12235 %}
12236
12237 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12238 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12239 match(If cop cr);
12240 effect(USE labl);
12241
12242 ins_cost(300);
12243 format %{ "J$cop,s $labl" %}
12244 size(2);
12245 ins_encode %{
12246 Label* L = $labl$$label;
12247 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12248 %}
12249 ins_pipe( pipe_jcc );
12250 ins_short_branch(1);
12251 %}
12252
12253 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12254 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12255 match(CountedLoopEnd cop cr);
12256 effect(USE labl);
12257
12258 ins_cost(300);
12259 format %{ "J$cop,s $labl\t# Loop end" %}
12260 size(2);
12261 ins_encode %{
12262 Label* L = $labl$$label;
12263 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12264 %}
12265 ins_pipe( pipe_jcc );
12266 ins_short_branch(1);
12267 %}
12268
12269 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12270 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12271 match(CountedLoopEnd cop cmp);
12272 effect(USE labl);
12273
12274 ins_cost(300);
12275 format %{ "J$cop,us $labl\t# Loop end" %}
12276 size(2);
12277 ins_encode %{
12278 Label* L = $labl$$label;
12279 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12280 %}
12281 ins_pipe( pipe_jcc );
12282 ins_short_branch(1);
12283 %}
12284
12285 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12286 match(CountedLoopEnd cop cmp);
12287 effect(USE labl);
12288
12289 ins_cost(300);
12290 format %{ "J$cop,us $labl\t# Loop end" %}
12291 size(2);
12292 ins_encode %{
12293 Label* L = $labl$$label;
12294 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12295 %}
12296 ins_pipe( pipe_jcc );
12297 ins_short_branch(1);
12298 %}
12299
12300 // Jump Direct Conditional - using unsigned comparison
12301 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12302 match(If cop cmp);
12303 effect(USE labl);
12304
12305 ins_cost(300);
12306 format %{ "J$cop,us $labl" %}
12307 size(2);
12308 ins_encode %{
12309 Label* L = $labl$$label;
12310 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12311 %}
12312 ins_pipe( pipe_jcc );
12313 ins_short_branch(1);
12314 %}
12315
12316 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12317 match(If cop cmp);
12318 effect(USE labl);
12319
12320 ins_cost(300);
12321 format %{ "J$cop,us $labl" %}
12322 size(2);
12323 ins_encode %{
12324 Label* L = $labl$$label;
12325 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12326 %}
12327 ins_pipe( pipe_jcc );
12328 ins_short_branch(1);
12329 %}
12330
12331 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12332 match(If cop cmp);
12333 effect(USE labl);
12334
12335 ins_cost(300);
12336 format %{ $$template
12337 if ($cop$$cmpcode == Assembler::notEqual) {
12338 $$emit$$"JP,u,s $labl\n\t"
12339 $$emit$$"J$cop,u,s $labl"
12340 } else {
12341 $$emit$$"JP,u,s done\n\t"
12342 $$emit$$"J$cop,u,s $labl\n\t"
12343 $$emit$$"done:"
12344 }
12345 %}
12346 size(4);
12347 ins_encode %{
12348 Label* l = $labl$$label;
12349 if ($cop$$cmpcode == Assembler::notEqual) {
12350 __ jccb(Assembler::parity, *l);
12351 __ jccb(Assembler::notEqual, *l);
12352 } else if ($cop$$cmpcode == Assembler::equal) {
12353 Label done;
12354 __ jccb(Assembler::parity, done);
12355 __ jccb(Assembler::equal, *l);
12356 __ bind(done);
12357 } else {
12358 ShouldNotReachHere();
12359 }
12360 %}
12361 ins_pipe(pipe_jcc);
12362 ins_short_branch(1);
12363 %}
12364
12365 // ============================================================================
12366 // Long Compare
12367 //
12368 // Currently we hold longs in 2 registers. Comparing such values efficiently
12369 // is tricky. The flavor of compare used depends on whether we are testing
12370 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12371 // The GE test is the negated LT test. The LE test can be had by commuting
12372 // the operands (yielding a GE test) and then negating; negate again for the
12373 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12374 // NE test is negated from that.
12375
12376 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12377 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12378 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12379 // are collapsed internally in the ADLC's dfa-gen code. The match for
12380 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12381 // foo match ends up with the wrong leaf. One fix is to not match both
12382 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12383 // both forms beat the trinary form of long-compare and both are very useful
12384 // on Intel which has so few registers.
12385
12386 // Manifest a CmpL result in an integer register. Very painful.
12387 // This is the test to avoid.
12388 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12389 match(Set dst (CmpL3 src1 src2));
12390 effect( KILL flags );
12391 ins_cost(1000);
12392 format %{ "XOR $dst,$dst\n\t"
12393 "CMP $src1.hi,$src2.hi\n\t"
12394 "JLT,s m_one\n\t"
12395 "JGT,s p_one\n\t"
12396 "CMP $src1.lo,$src2.lo\n\t"
12397 "JB,s m_one\n\t"
12398 "JEQ,s done\n"
12399 "p_one:\tINC $dst\n\t"
12400 "JMP,s done\n"
12401 "m_one:\tDEC $dst\n"
12402 "done:" %}
12403 ins_encode %{
12404 Label p_one, m_one, done;
12405 __ xorptr($dst$$Register, $dst$$Register);
12406 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12407 __ jccb(Assembler::less, m_one);
12408 __ jccb(Assembler::greater, p_one);
12409 __ cmpl($src1$$Register, $src2$$Register);
12410 __ jccb(Assembler::below, m_one);
12411 __ jccb(Assembler::equal, done);
12412 __ bind(p_one);
12413 __ incrementl($dst$$Register);
12414 __ jmpb(done);
12415 __ bind(m_one);
12416 __ decrementl($dst$$Register);
12417 __ bind(done);
12418 %}
12419 ins_pipe( pipe_slow );
12420 %}
12421
12422 //======
12423 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12424 // compares. Can be used for LE or GT compares by reversing arguments.
12425 // NOT GOOD FOR EQ/NE tests.
12426 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12427 match( Set flags (CmpL src zero ));
12428 ins_cost(100);
12429 format %{ "TEST $src.hi,$src.hi" %}
12430 opcode(0x85);
12431 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12432 ins_pipe( ialu_cr_reg_reg );
12433 %}
12434
12435 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12436 // compares. Can be used for LE or GT compares by reversing arguments.
12437 // NOT GOOD FOR EQ/NE tests.
12438 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12439 match( Set flags (CmpL src1 src2 ));
12440 effect( TEMP tmp );
12441 ins_cost(300);
12442 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12443 "MOV $tmp,$src1.hi\n\t"
12444 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12445 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12446 ins_pipe( ialu_cr_reg_reg );
12447 %}
12448
12449 // Long compares reg < zero/req OR reg >= zero/req.
12450 // Just a wrapper for a normal branch, plus the predicate test.
12451 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12452 match(If cmp flags);
12453 effect(USE labl);
12454 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12455 expand %{
12456 jmpCon(cmp,flags,labl); // JLT or JGE...
12457 %}
12458 %}
12459
12460 // Compare 2 longs and CMOVE longs.
12461 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12462 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12463 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12464 ins_cost(400);
12465 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12466 "CMOV$cmp $dst.hi,$src.hi" %}
12467 opcode(0x0F,0x40);
12468 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12469 ins_pipe( pipe_cmov_reg_long );
12470 %}
12471
12472 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12473 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12474 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12475 ins_cost(500);
12476 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12477 "CMOV$cmp $dst.hi,$src.hi" %}
12478 opcode(0x0F,0x40);
12479 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12480 ins_pipe( pipe_cmov_reg_long );
12481 %}
12482
12483 // Compare 2 longs and CMOVE ints.
12484 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12485 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12486 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12487 ins_cost(200);
12488 format %{ "CMOV$cmp $dst,$src" %}
12489 opcode(0x0F,0x40);
12490 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12491 ins_pipe( pipe_cmov_reg );
12492 %}
12493
12494 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12495 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12496 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12497 ins_cost(250);
12498 format %{ "CMOV$cmp $dst,$src" %}
12499 opcode(0x0F,0x40);
12500 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12501 ins_pipe( pipe_cmov_mem );
12502 %}
12503
12504 // Compare 2 longs and CMOVE ints.
12505 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12506 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12507 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12508 ins_cost(200);
12509 format %{ "CMOV$cmp $dst,$src" %}
12510 opcode(0x0F,0x40);
12511 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12512 ins_pipe( pipe_cmov_reg );
12513 %}
12514
12515 // Compare 2 longs and CMOVE doubles
12516 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12517 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12518 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12519 ins_cost(200);
12520 expand %{
12521 fcmovDPR_regS(cmp,flags,dst,src);
12522 %}
12523 %}
12524
12525 // Compare 2 longs and CMOVE doubles
12526 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12527 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12528 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12529 ins_cost(200);
12530 expand %{
12531 fcmovD_regS(cmp,flags,dst,src);
12532 %}
12533 %}
12534
12535 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12536 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12537 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12538 ins_cost(200);
12539 expand %{
12540 fcmovFPR_regS(cmp,flags,dst,src);
12541 %}
12542 %}
12543
12544 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12545 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12546 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12547 ins_cost(200);
12548 expand %{
12549 fcmovF_regS(cmp,flags,dst,src);
12550 %}
12551 %}
12552
12553 //======
12554 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12555 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12556 match( Set flags (CmpL src zero ));
12557 effect(TEMP tmp);
12558 ins_cost(200);
12559 format %{ "MOV $tmp,$src.lo\n\t"
12560 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12561 ins_encode( long_cmp_flags0( src, tmp ) );
12562 ins_pipe( ialu_reg_reg_long );
12563 %}
12564
12565 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12566 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12567 match( Set flags (CmpL src1 src2 ));
12568 ins_cost(200+300);
12569 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12570 "JNE,s skip\n\t"
12571 "CMP $src1.hi,$src2.hi\n\t"
12572 "skip:\t" %}
12573 ins_encode( long_cmp_flags1( src1, src2 ) );
12574 ins_pipe( ialu_cr_reg_reg );
12575 %}
12576
12577 // Long compare reg == zero/reg OR reg != zero/reg
12578 // Just a wrapper for a normal branch, plus the predicate test.
12579 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12580 match(If cmp flags);
12581 effect(USE labl);
12582 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12583 expand %{
12584 jmpCon(cmp,flags,labl); // JEQ or JNE...
12585 %}
12586 %}
12587
12588 // Compare 2 longs and CMOVE longs.
12589 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12590 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12591 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12592 ins_cost(400);
12593 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12594 "CMOV$cmp $dst.hi,$src.hi" %}
12595 opcode(0x0F,0x40);
12596 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12597 ins_pipe( pipe_cmov_reg_long );
12598 %}
12599
12600 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12601 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12602 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12603 ins_cost(500);
12604 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12605 "CMOV$cmp $dst.hi,$src.hi" %}
12606 opcode(0x0F,0x40);
12607 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12608 ins_pipe( pipe_cmov_reg_long );
12609 %}
12610
12611 // Compare 2 longs and CMOVE ints.
12612 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12613 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12614 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12615 ins_cost(200);
12616 format %{ "CMOV$cmp $dst,$src" %}
12617 opcode(0x0F,0x40);
12618 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12619 ins_pipe( pipe_cmov_reg );
12620 %}
12621
12622 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12623 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12624 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12625 ins_cost(250);
12626 format %{ "CMOV$cmp $dst,$src" %}
12627 opcode(0x0F,0x40);
12628 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12629 ins_pipe( pipe_cmov_mem );
12630 %}
12631
12632 // Compare 2 longs and CMOVE ints.
12633 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12634 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12635 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12636 ins_cost(200);
12637 format %{ "CMOV$cmp $dst,$src" %}
12638 opcode(0x0F,0x40);
12639 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12640 ins_pipe( pipe_cmov_reg );
12641 %}
12642
12643 // Compare 2 longs and CMOVE doubles
12644 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12645 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12646 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12647 ins_cost(200);
12648 expand %{
12649 fcmovDPR_regS(cmp,flags,dst,src);
12650 %}
12651 %}
12652
12653 // Compare 2 longs and CMOVE doubles
12654 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12655 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12656 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12657 ins_cost(200);
12658 expand %{
12659 fcmovD_regS(cmp,flags,dst,src);
12660 %}
12661 %}
12662
12663 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12664 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12665 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12666 ins_cost(200);
12667 expand %{
12668 fcmovFPR_regS(cmp,flags,dst,src);
12669 %}
12670 %}
12671
12672 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12673 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12674 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12675 ins_cost(200);
12676 expand %{
12677 fcmovF_regS(cmp,flags,dst,src);
12678 %}
12679 %}
12680
12681 //======
12682 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12683 // Same as cmpL_reg_flags_LEGT except must negate src
12684 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12685 match( Set flags (CmpL src zero ));
12686 effect( TEMP tmp );
12687 ins_cost(300);
12688 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12689 "CMP $tmp,$src.lo\n\t"
12690 "SBB $tmp,$src.hi\n\t" %}
12691 ins_encode( long_cmp_flags3(src, tmp) );
12692 ins_pipe( ialu_reg_reg_long );
12693 %}
12694
12695 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12696 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12697 // requires a commuted test to get the same result.
12698 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12699 match( Set flags (CmpL src1 src2 ));
12700 effect( TEMP tmp );
12701 ins_cost(300);
12702 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12703 "MOV $tmp,$src2.hi\n\t"
12704 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12705 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12706 ins_pipe( ialu_cr_reg_reg );
12707 %}
12708
12709 // Long compares reg < zero/req OR reg >= zero/req.
12710 // Just a wrapper for a normal branch, plus the predicate test
12711 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12712 match(If cmp flags);
12713 effect(USE labl);
12714 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12715 ins_cost(300);
12716 expand %{
12717 jmpCon(cmp,flags,labl); // JGT or JLE...
12718 %}
12719 %}
12720
12721 // Compare 2 longs and CMOVE longs.
12722 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12723 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12724 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12725 ins_cost(400);
12726 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12727 "CMOV$cmp $dst.hi,$src.hi" %}
12728 opcode(0x0F,0x40);
12729 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12730 ins_pipe( pipe_cmov_reg_long );
12731 %}
12732
12733 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12734 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12735 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12736 ins_cost(500);
12737 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12738 "CMOV$cmp $dst.hi,$src.hi+4" %}
12739 opcode(0x0F,0x40);
12740 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12741 ins_pipe( pipe_cmov_reg_long );
12742 %}
12743
12744 // Compare 2 longs and CMOVE ints.
12745 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12746 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12747 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12748 ins_cost(200);
12749 format %{ "CMOV$cmp $dst,$src" %}
12750 opcode(0x0F,0x40);
12751 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12752 ins_pipe( pipe_cmov_reg );
12753 %}
12754
12755 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12756 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12757 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12758 ins_cost(250);
12759 format %{ "CMOV$cmp $dst,$src" %}
12760 opcode(0x0F,0x40);
12761 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12762 ins_pipe( pipe_cmov_mem );
12763 %}
12764
12765 // Compare 2 longs and CMOVE ptrs.
12766 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12767 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12768 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12769 ins_cost(200);
12770 format %{ "CMOV$cmp $dst,$src" %}
12771 opcode(0x0F,0x40);
12772 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12773 ins_pipe( pipe_cmov_reg );
12774 %}
12775
12776 // Compare 2 longs and CMOVE doubles
12777 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12778 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12779 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12780 ins_cost(200);
12781 expand %{
12782 fcmovDPR_regS(cmp,flags,dst,src);
12783 %}
12784 %}
12785
12786 // Compare 2 longs and CMOVE doubles
12787 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12788 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12789 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12790 ins_cost(200);
12791 expand %{
12792 fcmovD_regS(cmp,flags,dst,src);
12793 %}
12794 %}
12795
12796 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12797 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12798 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12799 ins_cost(200);
12800 expand %{
12801 fcmovFPR_regS(cmp,flags,dst,src);
12802 %}
12803 %}
12804
12805
12806 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12807 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12808 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12809 ins_cost(200);
12810 expand %{
12811 fcmovF_regS(cmp,flags,dst,src);
12812 %}
12813 %}
12814
12815
12816 // ============================================================================
12817 // Procedure Call/Return Instructions
12818 // Call Java Static Instruction
12819 // Note: If this code changes, the corresponding ret_addr_offset() and
12820 // compute_padding() functions will have to be adjusted.
12821 instruct CallStaticJavaDirect(method meth) %{
12822 match(CallStaticJava);
12823 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12824 effect(USE meth);
12825
12826 ins_cost(300);
12827 format %{ "CALL,static " %}
12828 opcode(0xE8); /* E8 cd */
12829 ins_encode( pre_call_FPU,
12830 Java_Static_Call( meth ),
12831 call_epilog,
12832 post_call_FPU );
12833 ins_pipe( pipe_slow );
12834 ins_alignment(4);
12835 %}
12836
12837 // Call Java Static Instruction (method handle version)
12838 // Note: If this code changes, the corresponding ret_addr_offset() and
12839 // compute_padding() functions will have to be adjusted.
12840 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12841 match(CallStaticJava);
12842 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12843 effect(USE meth);
12844 // EBP is saved by all callees (for interpreter stack correction).
12845 // We use it here for a similar purpose, in {preserve,restore}_SP.
12846
12847 ins_cost(300);
12848 format %{ "CALL,static/MethodHandle " %}
12849 opcode(0xE8); /* E8 cd */
12850 ins_encode( pre_call_FPU,
12851 preserve_SP,
12852 Java_Static_Call( meth ),
12853 restore_SP,
12854 call_epilog,
12855 post_call_FPU );
12856 ins_pipe( pipe_slow );
12857 ins_alignment(4);
12858 %}
12859
12860 // Call Java Dynamic Instruction
12861 // Note: If this code changes, the corresponding ret_addr_offset() and
12862 // compute_padding() functions will have to be adjusted.
12863 instruct CallDynamicJavaDirect(method meth) %{
12864 match(CallDynamicJava);
12865 effect(USE meth);
12866
12867 ins_cost(300);
12868 format %{ "MOV EAX,(oop)-1\n\t"
12869 "CALL,dynamic" %}
12870 opcode(0xE8); /* E8 cd */
12871 ins_encode( pre_call_FPU,
12872 Java_Dynamic_Call( meth ),
12873 call_epilog,
12874 post_call_FPU );
12875 ins_pipe( pipe_slow );
12876 ins_alignment(4);
12877 %}
12878
12879 // Call Runtime Instruction
12880 instruct CallRuntimeDirect(method meth) %{
12881 match(CallRuntime );
12882 effect(USE meth);
12883
12884 ins_cost(300);
12885 format %{ "CALL,runtime " %}
12886 opcode(0xE8); /* E8 cd */
12887 // Use FFREEs to clear entries in float stack
12888 ins_encode( pre_call_FPU,
12889 FFree_Float_Stack_All,
12890 Java_To_Runtime( meth ),
12891 post_call_FPU );
12892 ins_pipe( pipe_slow );
12893 %}
12894
12895 // Call runtime without safepoint
12896 instruct CallLeafDirect(method meth) %{
12897 match(CallLeaf);
12898 effect(USE meth);
12899
12900 ins_cost(300);
12901 format %{ "CALL_LEAF,runtime " %}
12902 opcode(0xE8); /* E8 cd */
12903 ins_encode( pre_call_FPU,
12904 FFree_Float_Stack_All,
12905 Java_To_Runtime( meth ),
12906 Verify_FPU_For_Leaf, post_call_FPU );
12907 ins_pipe( pipe_slow );
12908 %}
12909
12910 instruct CallLeafNoFPDirect(method meth) %{
12911 match(CallLeafNoFP);
12912 effect(USE meth);
12913
12914 ins_cost(300);
12915 format %{ "CALL_LEAF_NOFP,runtime " %}
12916 opcode(0xE8); /* E8 cd */
12917 ins_encode(Java_To_Runtime(meth));
12918 ins_pipe( pipe_slow );
12919 %}
12920
12921
12922 // Return Instruction
12923 // Remove the return address & jump to it.
12924 instruct Ret() %{
12925 match(Return);
12926 format %{ "RET" %}
12927 opcode(0xC3);
12928 ins_encode(OpcP);
12929 ins_pipe( pipe_jmp );
12930 %}
12931
12932 // Tail Call; Jump from runtime stub to Java code.
12933 // Also known as an 'interprocedural jump'.
12934 // Target of jump will eventually return to caller.
12935 // TailJump below removes the return address.
12936 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12937 match(TailCall jump_target method_oop );
12938 ins_cost(300);
12939 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12940 opcode(0xFF, 0x4); /* Opcode FF /4 */
12941 ins_encode( OpcP, RegOpc(jump_target) );
12942 ins_pipe( pipe_jmp );
12943 %}
12944
12945
12946 // Tail Jump; remove the return address; jump to target.
12947 // TailCall above leaves the return address around.
12948 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12949 match( TailJump jump_target ex_oop );
12950 ins_cost(300);
12951 format %{ "POP EDX\t# pop return address into dummy\n\t"
12952 "JMP $jump_target " %}
12953 opcode(0xFF, 0x4); /* Opcode FF /4 */
12954 ins_encode( enc_pop_rdx,
12955 OpcP, RegOpc(jump_target) );
12956 ins_pipe( pipe_jmp );
12957 %}
12958
12959 // Create exception oop: created by stack-crawling runtime code.
12960 // Created exception is now available to this handler, and is setup
12961 // just prior to jumping to this handler. No code emitted.
12962 instruct CreateException( eAXRegP ex_oop )
12963 %{
12964 match(Set ex_oop (CreateEx));
12965
12966 size(0);
12967 // use the following format syntax
12968 format %{ "# exception oop is in EAX; no code emitted" %}
12969 ins_encode();
12970 ins_pipe( empty );
12971 %}
12972
12973
12974 // Rethrow exception:
12975 // The exception oop will come in the first argument position.
12976 // Then JUMP (not call) to the rethrow stub code.
12977 instruct RethrowException()
12978 %{
12979 match(Rethrow);
12980
12981 // use the following format syntax
12982 format %{ "JMP rethrow_stub" %}
12983 ins_encode(enc_rethrow);
12984 ins_pipe( pipe_jmp );
12985 %}
12986
12987 // inlined locking and unlocking
12988
12989
12990 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12991 match( Set cr (FastLock object box) );
12992 effect( TEMP tmp, TEMP scr, USE_KILL box );
12993 ins_cost(300);
12994 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12995 ins_encode( Fast_Lock(object,box,tmp,scr) );
12996 ins_pipe( pipe_slow );
12997 %}
12998
12999 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13000 match( Set cr (FastUnlock object box) );
13001 effect( TEMP tmp, USE_KILL box );
13002 ins_cost(300);
13003 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13004 ins_encode( Fast_Unlock(object,box,tmp) );
13005 ins_pipe( pipe_slow );
13006 %}
13007
13008
13009
13010 // ============================================================================
13011 // Safepoint Instruction
13012 instruct safePoint_poll(eFlagsReg cr) %{
13013 match(SafePoint);
13014 effect(KILL cr);
13015
13016 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13017 // On SPARC that might be acceptable as we can generate the address with
13018 // just a sethi, saving an or. By polling at offset 0 we can end up
13019 // putting additional pressure on the index-0 in the D$. Because of
13020 // alignment (just like the situation at hand) the lower indices tend
13021 // to see more traffic. It'd be better to change the polling address
13022 // to offset 0 of the last $line in the polling page.
13023
13024 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13025 ins_cost(125);
13026 size(6) ;
13027 ins_encode( Safepoint_Poll() );
13028 ins_pipe( ialu_reg_mem );
13029 %}
13030
13031
13032 // ============================================================================
13033 // This name is KNOWN by the ADLC and cannot be changed.
13034 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13035 // for this guy.
13036 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13037 match(Set dst (ThreadLocal));
13038 effect(DEF dst, KILL cr);
13039
13040 format %{ "MOV $dst, Thread::current()" %}
13041 ins_encode %{
13042 Register dstReg = as_Register($dst$$reg);
13043 __ get_thread(dstReg);
13044 %}
13045 ins_pipe( ialu_reg_fat );
13046 %}
13047
13048
13049
13050 //----------PEEPHOLE RULES-----------------------------------------------------
13051 // These must follow all instruction definitions as they use the names
13052 // defined in the instructions definitions.
13053 //
13054 // peepmatch ( root_instr_name [preceding_instruction]* );
13055 //
13056 // peepconstraint %{
13057 // (instruction_number.operand_name relational_op instruction_number.operand_name
13058 // [, ...] );
13059 // // instruction numbers are zero-based using left to right order in peepmatch
13060 //
13061 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13062 // // provide an instruction_number.operand_name for each operand that appears
13063 // // in the replacement instruction's match rule
13064 //
13065 // ---------VM FLAGS---------------------------------------------------------
13066 //
13067 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13068 //
13069 // Each peephole rule is given an identifying number starting with zero and
13070 // increasing by one in the order seen by the parser. An individual peephole
13071 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13072 // on the command-line.
13073 //
13074 // ---------CURRENT LIMITATIONS----------------------------------------------
13075 //
13076 // Only match adjacent instructions in same basic block
13077 // Only equality constraints
13078 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13079 // Only one replacement instruction
13080 //
13081 // ---------EXAMPLE----------------------------------------------------------
13082 //
13083 // // pertinent parts of existing instructions in architecture description
13084 // instruct movI(rRegI dst, rRegI src) %{
13085 // match(Set dst (CopyI src));
13086 // %}
13087 //
13088 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13089 // match(Set dst (AddI dst src));
13090 // effect(KILL cr);
13091 // %}
13092 //
13093 // // Change (inc mov) to lea
13094 // peephole %{
13095 // // increment preceeded by register-register move
13096 // peepmatch ( incI_eReg movI );
13097 // // require that the destination register of the increment
13098 // // match the destination register of the move
13099 // peepconstraint ( 0.dst == 1.dst );
13100 // // construct a replacement instruction that sets
13101 // // the destination to ( move's source register + one )
13102 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13103 // %}
13104 //
13105 // Implementation no longer uses movX instructions since
13106 // machine-independent system no longer uses CopyX nodes.
13107 //
13108 // peephole %{
13109 // peepmatch ( incI_eReg movI );
13110 // peepconstraint ( 0.dst == 1.dst );
13111 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13112 // %}
13113 //
13114 // peephole %{
13115 // peepmatch ( decI_eReg movI );
13116 // peepconstraint ( 0.dst == 1.dst );
13117 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13118 // %}
13119 //
13120 // peephole %{
13121 // peepmatch ( addI_eReg_imm movI );
13122 // peepconstraint ( 0.dst == 1.dst );
13123 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13124 // %}
13125 //
13126 // peephole %{
13127 // peepmatch ( addP_eReg_imm movP );
13128 // peepconstraint ( 0.dst == 1.dst );
13129 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13130 // %}
13131
13132 // // Change load of spilled value to only a spill
13133 // instruct storeI(memory mem, rRegI src) %{
13134 // match(Set mem (StoreI mem src));
13135 // %}
13136 //
13137 // instruct loadI(rRegI dst, memory mem) %{
13138 // match(Set dst (LoadI mem));
13139 // %}
13140 //
13141 peephole %{
13142 peepmatch ( loadI storeI );
13143 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13144 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13145 %}
13146
13147 //----------SMARTSPILL RULES---------------------------------------------------
13148 // These must follow all instruction definitions as they use the names
13149 // defined in the instructions definitions.