1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "assembler_sparc.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "runtime/java.hpp"
29 #include "runtime/stubCodeGenerator.hpp"
30 #include "vm_version_sparc.hpp"
31 #ifdef TARGET_OS_FAMILY_linux
32 # include "os_linux.inline.hpp"
33 #endif
34 #ifdef TARGET_OS_FAMILY_solaris
35 # include "os_solaris.inline.hpp"
36 #endif
37
38 int VM_Version::_features = VM_Version::unknown_m;
39 const char* VM_Version::_features_str = "";
40
41 void VM_Version::initialize() {
42 _features = determine_features();
43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
45 PrefetchFieldsAhead = prefetch_fields_ahead();
46
47 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
48 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
49 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
50
51 // Allocation prefetch settings
52 intx cache_line_size = prefetch_data_size();
53 if( cache_line_size > AllocatePrefetchStepSize )
54 AllocatePrefetchStepSize = cache_line_size;
55
56 assert(AllocatePrefetchLines > 0, "invalid value");
57 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
58 AllocatePrefetchLines = 3;
59 assert(AllocateInstancePrefetchLines > 0, "invalid value");
60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
61 AllocateInstancePrefetchLines = 1;
62
63 AllocatePrefetchDistance = allocate_prefetch_distance();
64 AllocatePrefetchStyle = allocate_prefetch_style();
65
66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
67 (AllocatePrefetchDistance > 0), "invalid value");
68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
69 (AllocatePrefetchDistance <= 0)) {
70 AllocatePrefetchDistance = AllocatePrefetchStepSize;
71 }
72
73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
74 warning("BIS instructions are not available on this CPU");
75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
76 }
77
78 if (has_v9()) {
79 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
80 if (ArraycopySrcPrefetchDistance >= 4096)
81 ArraycopySrcPrefetchDistance = 4064;
82 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
83 if (ArraycopyDstPrefetchDistance >= 4096)
84 ArraycopyDstPrefetchDistance = 4064;
85 } else {
86 if (ArraycopySrcPrefetchDistance > 0) {
87 warning("prefetch instructions are not available on this CPU");
88 FLAG_SET_DEFAULT(ArraycopySrcPrefetchDistance, 0);
89 }
90 if (ArraycopyDstPrefetchDistance > 0) {
91 warning("prefetch instructions are not available on this CPU");
92 FLAG_SET_DEFAULT(ArraycopyDstPrefetchDistance, 0);
93 }
94 }
95
96 UseSSE = 0; // Only on x86 and x64
97
98 _supports_cx8 = has_v9();
99 _supports_atomic_getset4 = true; // swap instruction
100
101 if (is_niagara()) {
102 // Indirect branch is the same cost as direct
103 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
104 FLAG_SET_DEFAULT(UseInlineCaches, false);
105 }
106 // Align loops on a single instruction boundary.
107 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
108 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
109 }
110 // When using CMS or G1, we cannot use memset() in BOT updates
111 // because the sun4v/CMT version in libc_psr uses BIS which
112 // exposes "phantom zeros" to concurrent readers. See 6948537.
113 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
114 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
115 }
116 #ifdef _LP64
117 // 32-bit oops don't make sense for the 64-bit VM on sparc
118 // since the 32-bit VM has the same registers and smaller objects.
119 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
120 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
121 #endif // _LP64
122 #ifdef COMPILER2
123 // Indirect branch is the same cost as direct
124 if (FLAG_IS_DEFAULT(UseJumpTables)) {
125 FLAG_SET_DEFAULT(UseJumpTables, true);
126 }
127 // Single-issue, so entry and loop tops are
128 // aligned on a single instruction boundary
129 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
130 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
131 }
132 if (is_niagara_plus()) {
133 if (has_blk_init() && UseTLAB &&
134 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
135 // Use BIS instruction for TLAB allocation prefetch.
136 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
137 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
138 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
139 }
140 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
141 // Use smaller prefetch distance with BIS
142 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
143 }
144 }
145 if (is_T4()) {
146 // Double number of prefetched cache lines on T4
147 // since L2 cache line size is smaller (32 bytes).
148 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
149 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
150 }
151 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
152 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
153 }
154 }
155 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
156 // Use different prefetch distance without BIS
157 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
158 }
159 if (AllocatePrefetchInstr == 1) {
160 // Need a space at the end of TLAB for BIS since it
161 // will fault when accessing memory outside of heap.
162
163 // +1 for rounding up to next cache line, +1 to be safe
164 int lines = AllocatePrefetchLines + 2;
165 int step_size = AllocatePrefetchStepSize;
166 int distance = AllocatePrefetchDistance;
167 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
168 }
169 }
170 #endif
171 }
172
173 // Use hardware population count instruction if available.
174 if (has_hardware_popc()) {
175 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
176 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
177 }
178 } else if (UsePopCountInstruction) {
179 warning("POPC instruction is not available on this CPU");
180 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
181 }
182
183 // T4 and newer Sparc cpus have new compare and branch instruction.
184 if (has_cbcond()) {
185 if (FLAG_IS_DEFAULT(UseCBCond)) {
186 FLAG_SET_DEFAULT(UseCBCond, true);
187 }
188 } else if (UseCBCond) {
189 warning("CBCOND instruction is not available on this CPU");
190 FLAG_SET_DEFAULT(UseCBCond, false);
191 }
192
193 assert(BlockZeroingLowLimit > 0, "invalid value");
194 if (has_block_zeroing()) {
195 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
196 FLAG_SET_DEFAULT(UseBlockZeroing, true);
197 }
198 } else if (UseBlockZeroing) {
199 warning("BIS zeroing instructions are not available on this CPU");
200 FLAG_SET_DEFAULT(UseBlockZeroing, false);
201 }
202
203 assert(BlockCopyLowLimit > 0, "invalid value");
204 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache
205 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
206 FLAG_SET_DEFAULT(UseBlockCopy, true);
207 }
208 } else if (UseBlockCopy) {
209 warning("BIS instructions are not available or expensive on this CPU");
210 FLAG_SET_DEFAULT(UseBlockCopy, false);
211 }
212
213 #ifdef COMPILER2
214 // T4 and newer Sparc cpus have fast RDPC.
215 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
216 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
217 }
218
219 // Currently not supported anywhere.
220 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
221
222 MaxVectorSize = 8;
223
224 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
225 #endif
226
227 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
228 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
229
230 char buf[512];
231 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
232 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
233 (has_hardware_popc() ? ", popc" : ""),
234 (has_vis1() ? ", vis1" : ""),
235 (has_vis2() ? ", vis2" : ""),
236 (has_vis3() ? ", vis3" : ""),
237 (has_blk_init() ? ", blk_init" : ""),
238 (has_cbcond() ? ", cbcond" : ""),
239 (is_ultra3() ? ", ultra3" : ""),
240 (is_sun4v() ? ", sun4v" : ""),
241 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
242 (is_sparc64() ? ", sparc64" : ""),
243 (!has_hardware_mul32() ? ", no-mul32" : ""),
244 (!has_hardware_div32() ? ", no-div32" : ""),
245 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
246
247 // buf is started with ", " or is empty
248 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
249
250 // UseVIS is set to the smallest of what hardware supports and what
251 // the command line requires. I.e., you cannot set UseVIS to 3 on
252 // older UltraSparc which do not support it.
253 if (UseVIS > 3) UseVIS=3;
254 if (UseVIS < 0) UseVIS=0;
255 if (!has_vis3()) // Drop to 2 if no VIS3 support
256 UseVIS = MIN2((intx)2,UseVIS);
257 if (!has_vis2()) // Drop to 1 if no VIS2 support
258 UseVIS = MIN2((intx)1,UseVIS);
259 if (!has_vis1()) // Drop to 0 if no VIS1 support
260 UseVIS = 0;
261
262 #ifndef PRODUCT
263 if (PrintMiscellaneous && Verbose) {
264 tty->print("Allocation");
265 if (AllocatePrefetchStyle <= 0) {
266 tty->print_cr(": no prefetching");
267 } else {
268 tty->print(" prefetching: ");
269 if (AllocatePrefetchInstr == 0) {
270 tty->print("PREFETCH");
271 } else if (AllocatePrefetchInstr == 1) {
272 tty->print("BIS");
273 }
274 if (AllocatePrefetchLines > 1) {
275 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
276 } else {
277 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
278 }
279 }
280 if (PrefetchCopyIntervalInBytes > 0) {
281 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
282 }
283 if (PrefetchScanIntervalInBytes > 0) {
284 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
285 }
286 if (PrefetchFieldsAhead > 0) {
287 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
288 }
289 }
290 #endif // PRODUCT
291 }
292
293 void VM_Version::print_features() {
294 tty->print_cr("Version:%s", cpu_features());
295 }
296
297 int VM_Version::determine_features() {
298 if (UseV8InstrsOnly) {
299 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
300 return generic_v8_m;
301 }
302
303 int features = platform_features(unknown_m); // platform_features() is os_arch specific
304
305 if (features == unknown_m) {
306 features = generic_v9_m;
307 warning("Cannot recognize SPARC version. Default to V9");
308 }
309
310 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
311 if (UseNiagaraInstrs) { // Force code generation for Niagara
312 if (is_T_family(features)) {
313 // Happy to accomodate...
314 } else {
315 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
316 features |= T_family_m;
317 }
318 } else {
319 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
320 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
321 features &= ~(T_family_m | T1_model_m);
322 } else {
323 // Happy to accomodate...
324 }
325 }
326
327 return features;
328 }
329
330 static int saved_features = 0;
331
332 void VM_Version::allow_all() {
333 saved_features = _features;
334 _features = all_features_m;
335 }
336
337 void VM_Version::revert() {
338 _features = saved_features;
339 }
340
341 unsigned int VM_Version::calc_parallel_worker_threads() {
342 unsigned int result;
343 if (is_M_series()) {
344 // for now, use same gc thread calculation for M-series as for niagara-plus
345 // in future, we may want to tweak parameters for nof_parallel_worker_thread
346 result = nof_parallel_worker_threads(5, 16, 8);
347 } else if (is_niagara_plus()) {
348 result = nof_parallel_worker_threads(5, 16, 8);
349 } else {
350 result = nof_parallel_worker_threads(5, 8, 8);
351 }
352 return result;
353 }