1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_FPU_size() {
232 if (Compile::current()->in_24_bit_fp_mode())
233 return 6; // fldcw
234 return 0;
235 }
236
237 static int preserve_SP_size() {
238 return 2; // op, rm(reg/reg)
239 }
240
241 // !!!!! Special hack to get all type of calls to specify the byte offset
242 // from the start of the call to the point where the return address
243 // will point.
244 int MachCallStaticJavaNode::ret_addr_offset() {
245 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
246 if (_method_handle_invoke)
247 offset += preserve_SP_size();
248 return offset;
249 }
250
251 int MachCallDynamicJavaNode::ret_addr_offset() {
252 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
253 }
254
255 static int sizeof_FFree_Float_Stack_All = -1;
256
257 int MachCallRuntimeNode::ret_addr_offset() {
258 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
259 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
260 }
261
262 // Indicate if the safepoint node needs the polling page as an input.
263 // Since x86 does have absolute addressing, it doesn't.
264 bool SafePointNode::needs_polling_address_input() {
265 return false;
266 }
267
268 //
269 // Compute padding required for nodes which need alignment
270 //
271
272 // The address of the call instruction needs to be 4-byte aligned to
273 // ensure that it does not span a cache line so that it can be patched.
274 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
275 current_offset += pre_call_FPU_size(); // skip fldcw, if any
276 current_offset += 1; // skip call opcode byte
277 return round_to(current_offset, alignment_required()) - current_offset;
278 }
279
280 // The address of the call instruction needs to be 4-byte aligned to
281 // ensure that it does not span a cache line so that it can be patched.
282 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
283 current_offset += pre_call_FPU_size(); // skip fldcw, if any
284 current_offset += preserve_SP_size(); // skip mov rbp, rsp
285 current_offset += 1; // skip call opcode byte
286 return round_to(current_offset, alignment_required()) - current_offset;
287 }
288
289 // The address of the call instruction needs to be 4-byte aligned to
290 // ensure that it does not span a cache line so that it can be patched.
291 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
292 current_offset += pre_call_FPU_size(); // skip fldcw, if any
293 current_offset += 5; // skip MOV instruction
294 current_offset += 1; // skip call opcode byte
295 return round_to(current_offset, alignment_required()) - current_offset;
296 }
297
298 // EMIT_RM()
299 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
300 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
301 cbuf.insts()->emit_int8(c);
302 }
303
304 // EMIT_CC()
305 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
306 unsigned char c = (unsigned char)( f1 | f2 );
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_OPCODE()
311 void emit_opcode(CodeBuffer &cbuf, int code) {
312 cbuf.insts()->emit_int8((unsigned char) code);
313 }
314
315 // EMIT_OPCODE() w/ relocation information
316 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
317 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
318 emit_opcode(cbuf, code);
319 }
320
321 // EMIT_D8()
322 void emit_d8(CodeBuffer &cbuf, int d8) {
323 cbuf.insts()->emit_int8((unsigned char) d8);
324 }
325
326 // EMIT_D16()
327 void emit_d16(CodeBuffer &cbuf, int d16) {
328 cbuf.insts()->emit_int16(d16);
329 }
330
331 // EMIT_D32()
332 void emit_d32(CodeBuffer &cbuf, int d32) {
333 cbuf.insts()->emit_int32(d32);
334 }
335
336 // emit 32 bit value and construct relocation entry from relocInfo::relocType
337 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
338 int format) {
339 cbuf.relocate(cbuf.insts_mark(), reloc, format);
340 cbuf.insts()->emit_int32(d32);
341 }
342
343 // emit 32 bit value and construct relocation entry from RelocationHolder
344 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
345 int format) {
346 #ifdef ASSERT
347 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
348 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
349 }
350 #endif
351 cbuf.relocate(cbuf.insts_mark(), rspec, format);
352 cbuf.insts()->emit_int32(d32);
353 }
354
355 // Access stack slot for load or store
356 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
357 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
358 if( -128 <= disp && disp <= 127 ) {
359 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
360 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
361 emit_d8 (cbuf, disp); // Displacement // R/M byte
362 } else {
363 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
365 emit_d32(cbuf, disp); // Displacement // R/M byte
366 }
367 }
368
369 // rRegI ereg, memory mem) %{ // emit_reg_mem
370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
371 // There is no index & no scale, use form without SIB byte
372 if ((index == 0x4) &&
373 (scale == 0) && (base != ESP_enc)) {
374 // If no displacement, mode is 0x0; unless base is [EBP]
375 if ( (displace == 0) && (base != EBP_enc) ) {
376 emit_rm(cbuf, 0x0, reg_encoding, base);
377 }
378 else { // If 8-bit displacement, mode 0x1
379 if ((displace >= -128) && (displace <= 127)
380 && (disp_reloc == relocInfo::none) ) {
381 emit_rm(cbuf, 0x1, reg_encoding, base);
382 emit_d8(cbuf, displace);
383 }
384 else { // If 32-bit displacement
385 if (base == -1) { // Special flag for absolute address
386 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
387 // (manual lies; no SIB needed here)
388 if ( disp_reloc != relocInfo::none ) {
389 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
390 } else {
391 emit_d32 (cbuf, displace);
392 }
393 }
394 else { // Normal base + offset
395 emit_rm(cbuf, 0x2, reg_encoding, base);
396 if ( disp_reloc != relocInfo::none ) {
397 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
398 } else {
399 emit_d32 (cbuf, displace);
400 }
401 }
402 }
403 }
404 }
405 else { // Else, encode with the SIB byte
406 // If no displacement, mode is 0x0; unless base is [EBP]
407 if (displace == 0 && (base != EBP_enc)) { // If no displacement
408 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
409 emit_rm(cbuf, scale, index, base);
410 }
411 else { // If 8-bit displacement, mode 0x1
412 if ((displace >= -128) && (displace <= 127)
413 && (disp_reloc == relocInfo::none) ) {
414 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 emit_d8(cbuf, displace);
417 }
418 else { // If 32-bit displacement
419 if (base == 0x04 ) {
420 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, 0x04);
422 } else {
423 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
424 emit_rm(cbuf, scale, index, base);
425 }
426 if ( disp_reloc != relocInfo::none ) {
427 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
428 } else {
429 emit_d32 (cbuf, displace);
430 }
431 }
432 }
433 }
434 }
435
436
437 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
438 if( dst_encoding == src_encoding ) {
439 // reg-reg copy, use an empty encoding
440 } else {
441 emit_opcode( cbuf, 0x8B );
442 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
443 }
444 }
445
446 void emit_cmpfp_fixup(MacroAssembler& _masm) {
447 Label exit;
448 __ jccb(Assembler::noParity, exit);
449 __ pushf();
450 //
451 // comiss/ucomiss instructions set ZF,PF,CF flags and
452 // zero OF,AF,SF for NaN values.
453 // Fixup flags by zeroing ZF,PF so that compare of NaN
454 // values returns 'less than' result (CF is set).
455 // Leave the rest of flags unchanged.
456 //
457 // 7 6 5 4 3 2 1 0
458 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
459 // 0 0 1 0 1 0 1 1 (0x2B)
460 //
461 __ andl(Address(rsp, 0), 0xffffff2b);
462 __ popf();
463 __ bind(exit);
464 }
465
466 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
467 Label done;
468 __ movl(dst, -1);
469 __ jcc(Assembler::parity, done);
470 __ jcc(Assembler::below, done);
471 __ setb(Assembler::notEqual, dst);
472 __ movzbl(dst, dst);
473 __ bind(done);
474 }
475
476
477 //=============================================================================
478 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
479
480 int Compile::ConstantTable::calculate_table_base_offset() const {
481 return 0; // absolute addressing, no offset
482 }
483
484 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
485 // Empty encoding
486 }
487
488 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
489 return 0;
490 }
491
492 #ifndef PRODUCT
493 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
494 st->print("# MachConstantBaseNode (empty encoding)");
495 }
496 #endif
497
498
499 //=============================================================================
500 #ifndef PRODUCT
501 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
502 Compile* C = ra_->C;
503
504 int framesize = C->frame_slots() << LogBytesPerInt;
505 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
506 // Remove wordSize for return addr which is already pushed.
507 framesize -= wordSize;
508
509 if (C->need_stack_bang(framesize)) {
510 framesize -= wordSize;
511 st->print("# stack bang");
512 st->print("\n\t");
513 st->print("PUSH EBP\t# Save EBP");
514 if (framesize) {
515 st->print("\n\t");
516 st->print("SUB ESP, #%d\t# Create frame",framesize);
517 }
518 } else {
519 st->print("SUB ESP, #%d\t# Create frame",framesize);
520 st->print("\n\t");
521 framesize -= wordSize;
522 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
523 }
524
525 if (VerifyStackAtCalls) {
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
529 }
530
531 if( C->in_24_bit_fp_mode() ) {
532 st->print("\n\t");
533 st->print("FLDCW \t# load 24 bit fpu control word");
534 }
535 if (UseSSE >= 2 && VerifyFPU) {
536 st->print("\n\t");
537 st->print("# verify FPU stack (must be clean on entry)");
538 }
539
540 #ifdef ASSERT
541 if (VerifyStackAtCalls) {
542 st->print("\n\t");
543 st->print("# stack alignment check");
544 }
545 #endif
546 st->cr();
547 }
548 #endif
549
550
551 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
552 Compile* C = ra_->C;
553 MacroAssembler _masm(&cbuf);
554
555 int framesize = C->frame_slots() << LogBytesPerInt;
556
557 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
558
559 C->set_frame_complete(cbuf.insts_size());
560
561 if (C->has_mach_constant_base_node()) {
562 // NOTE: We set the table base offset here because users might be
563 // emitted before MachConstantBaseNode.
564 Compile::ConstantTable& constant_table = C->constant_table();
565 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
566 }
567 }
568
569 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
570 return MachNode::size(ra_); // too many variables; just compute it the hard way
571 }
572
573 int MachPrologNode::reloc() const {
574 return 0; // a large enough number
575 }
576
577 //=============================================================================
578 #ifndef PRODUCT
579 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
580 Compile *C = ra_->C;
581 int framesize = C->frame_slots() << LogBytesPerInt;
582 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
583 // Remove two words for return addr and rbp,
584 framesize -= 2*wordSize;
585
586 if( C->in_24_bit_fp_mode() ) {
587 st->print("FLDCW standard control word");
588 st->cr(); st->print("\t");
589 }
590 if( framesize ) {
591 st->print("ADD ESP,%d\t# Destroy frame",framesize);
592 st->cr(); st->print("\t");
593 }
594 st->print_cr("POPL EBP"); st->print("\t");
595 if( do_polling() && C->is_method_compilation() ) {
596 st->print("TEST PollPage,EAX\t! Poll Safepoint");
597 st->cr(); st->print("\t");
598 }
599 }
600 #endif
601
602 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
603 Compile *C = ra_->C;
604
605 // If method set FPU control word, restore to standard control word
606 if( C->in_24_bit_fp_mode() ) {
607 MacroAssembler masm(&cbuf);
608 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
609 }
610
611 int framesize = C->frame_slots() << LogBytesPerInt;
612 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
613 // Remove two words for return addr and rbp,
614 framesize -= 2*wordSize;
615
616 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
617
618 if( framesize >= 128 ) {
619 emit_opcode(cbuf, 0x81); // add SP, #framesize
620 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
621 emit_d32(cbuf, framesize);
622 }
623 else if( framesize ) {
624 emit_opcode(cbuf, 0x83); // add SP, #framesize
625 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
626 emit_d8(cbuf, framesize);
627 }
628
629 emit_opcode(cbuf, 0x58 | EBP_enc);
630
631 if( do_polling() && C->is_method_compilation() ) {
632 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
633 emit_opcode(cbuf,0x85);
634 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
635 emit_d32(cbuf, (intptr_t)os::get_polling_page());
636 }
637 }
638
639 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
640 Compile *C = ra_->C;
641 // If method set FPU control word, restore to standard control word
642 int size = C->in_24_bit_fp_mode() ? 6 : 0;
643 if( do_polling() && C->is_method_compilation() ) size += 6;
644
645 int framesize = C->frame_slots() << LogBytesPerInt;
646 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
647 // Remove two words for return addr and rbp,
648 framesize -= 2*wordSize;
649
650 size++; // popl rbp,
651
652 if( framesize >= 128 ) {
653 size += 6;
654 } else {
655 size += framesize ? 3 : 0;
656 }
657 return size;
658 }
659
660 int MachEpilogNode::reloc() const {
661 return 0; // a large enough number
662 }
663
664 const Pipeline * MachEpilogNode::pipeline() const {
665 return MachNode::pipeline_class();
666 }
667
668 int MachEpilogNode::safepoint_offset() const { return 0; }
669
670 //=============================================================================
671
672 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
673 static enum RC rc_class( OptoReg::Name reg ) {
674
675 if( !OptoReg::is_valid(reg) ) return rc_bad;
676 if (OptoReg::is_stack(reg)) return rc_stack;
677
678 VMReg r = OptoReg::as_VMReg(reg);
679 if (r->is_Register()) return rc_int;
680 if (r->is_FloatRegister()) {
681 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
682 return rc_float;
683 }
684 assert(r->is_XMMRegister(), "must be");
685 return rc_xmm;
686 }
687
688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
689 int opcode, const char *op_str, int size, outputStream* st ) {
690 if( cbuf ) {
691 emit_opcode (*cbuf, opcode );
692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
693 #ifndef PRODUCT
694 } else if( !do_size ) {
695 if( size != 0 ) st->print("\n\t");
696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
698 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
699 } else { // FLD, FST, PUSH, POP
700 st->print("%s [ESP + #%d]",op_str,offset);
701 }
702 #endif
703 }
704 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
705 return size+3+offset_size;
706 }
707
708 // Helper for XMM registers. Extra opcode bits, limited syntax.
709 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
710 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
711 if (cbuf) {
712 MacroAssembler _masm(cbuf);
713 if (reg_lo+1 == reg_hi) { // double move?
714 if (is_load) {
715 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
716 } else {
717 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
718 }
719 } else {
720 if (is_load) {
721 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
722 } else {
723 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
724 }
725 }
726 #ifndef PRODUCT
727 } else if (!do_size) {
728 if (size != 0) st->print("\n\t");
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) st->print("%s %s,[ESP + #%d]",
731 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
732 Matcher::regName[reg_lo], offset);
733 else st->print("MOVSD [ESP + #%d],%s",
734 offset, Matcher::regName[reg_lo]);
735 } else {
736 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
737 Matcher::regName[reg_lo], offset);
738 else st->print("MOVSS [ESP + #%d],%s",
739 offset, Matcher::regName[reg_lo]);
740 }
741 #endif
742 }
743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
745 return size+5+offset_size;
746 }
747
748
749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
750 int src_hi, int dst_hi, int size, outputStream* st ) {
751 if (cbuf) {
752 MacroAssembler _masm(cbuf);
753 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
754 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
755 as_XMMRegister(Matcher::_regEncode[src_lo]));
756 } else {
757 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
758 as_XMMRegister(Matcher::_regEncode[src_lo]));
759 }
760 #ifndef PRODUCT
761 } else if (!do_size) {
762 if (size != 0) st->print("\n\t");
763 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
764 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
765 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
766 } else {
767 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
768 }
769 } else {
770 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
771 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
772 } else {
773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
774 }
775 }
776 #endif
777 }
778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
779 // Only MOVAPS SSE prefix uses 1 byte.
780 int sz = 4;
781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
783 return size + sz;
784 }
785
786 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
787 int src_hi, int dst_hi, int size, outputStream* st ) {
788 // 32-bit
789 if (cbuf) {
790 MacroAssembler _masm(cbuf);
791 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
792 as_Register(Matcher::_regEncode[src_lo]));
793 #ifndef PRODUCT
794 } else if (!do_size) {
795 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
796 #endif
797 }
798 return 4;
799 }
800
801
802 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
808 as_XMMRegister(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
816
817 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
818 if( cbuf ) {
819 emit_opcode(*cbuf, 0x8B );
820 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
821 #ifndef PRODUCT
822 } else if( !do_size ) {
823 if( size != 0 ) st->print("\n\t");
824 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
825 #endif
826 }
827 return size+2;
828 }
829
830 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
831 int offset, int size, outputStream* st ) {
832 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
833 if( cbuf ) {
834 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
835 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
836 #ifndef PRODUCT
837 } else if( !do_size ) {
838 if( size != 0 ) st->print("\n\t");
839 st->print("FLD %s",Matcher::regName[src_lo]);
840 #endif
841 }
842 size += 2;
843 }
844
845 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
846 const char *op_str;
847 int op;
848 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
849 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
850 op = 0xDD;
851 } else { // 32-bit store
852 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
853 op = 0xD9;
854 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
855 }
856
857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
858 }
859
860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
862 int src_hi, int dst_hi, uint ireg, outputStream* st);
863
864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
865 int stack_offset, int reg, uint ireg, outputStream* st);
866
867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
868 int dst_offset, uint ireg, outputStream* st) {
869 int calc_size = 0;
870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
872 switch (ireg) {
873 case Op_VecS:
874 calc_size = 3+src_offset_size + 3+dst_offset_size;
875 break;
876 case Op_VecD:
877 calc_size = 3+src_offset_size + 3+dst_offset_size;
878 src_offset += 4;
879 dst_offset += 4;
880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
882 calc_size += 3+src_offset_size + 3+dst_offset_size;
883 break;
884 case Op_VecX:
885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
886 break;
887 case Op_VecY:
888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
889 break;
890 default:
891 ShouldNotReachHere();
892 }
893 if (cbuf) {
894 MacroAssembler _masm(cbuf);
895 int offset = __ offset();
896 switch (ireg) {
897 case Op_VecS:
898 __ pushl(Address(rsp, src_offset));
899 __ popl (Address(rsp, dst_offset));
900 break;
901 case Op_VecD:
902 __ pushl(Address(rsp, src_offset));
903 __ popl (Address(rsp, dst_offset));
904 __ pushl(Address(rsp, src_offset+4));
905 __ popl (Address(rsp, dst_offset+4));
906 break;
907 case Op_VecX:
908 __ movdqu(Address(rsp, -16), xmm0);
909 __ movdqu(xmm0, Address(rsp, src_offset));
910 __ movdqu(Address(rsp, dst_offset), xmm0);
911 __ movdqu(xmm0, Address(rsp, -16));
912 break;
913 case Op_VecY:
914 __ vmovdqu(Address(rsp, -32), xmm0);
915 __ vmovdqu(xmm0, Address(rsp, src_offset));
916 __ vmovdqu(Address(rsp, dst_offset), xmm0);
917 __ vmovdqu(xmm0, Address(rsp, -32));
918 break;
919 default:
920 ShouldNotReachHere();
921 }
922 int size = __ offset() - offset;
923 assert(size == calc_size, "incorrect size calculattion");
924 return size;
925 #ifndef PRODUCT
926 } else if (!do_size) {
927 switch (ireg) {
928 case Op_VecS:
929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
930 "popl [rsp + #%d]",
931 src_offset, dst_offset);
932 break;
933 case Op_VecD:
934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
935 "popq [rsp + #%d]\n\t"
936 "pushl [rsp + #%d]\n\t"
937 "popq [rsp + #%d]",
938 src_offset, dst_offset, src_offset+4, dst_offset+4);
939 break;
940 case Op_VecX:
941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
942 "movdqu xmm0, [rsp + #%d]\n\t"
943 "movdqu [rsp + #%d], xmm0\n\t"
944 "movdqu xmm0, [rsp - #16]",
945 src_offset, dst_offset);
946 break;
947 case Op_VecY:
948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
949 "vmovdqu xmm0, [rsp + #%d]\n\t"
950 "vmovdqu [rsp + #%d], xmm0\n\t"
951 "vmovdqu xmm0, [rsp - #32]",
952 src_offset, dst_offset);
953 break;
954 default:
955 ShouldNotReachHere();
956 }
957 #endif
958 }
959 return calc_size;
960 }
961
962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
963 // Get registers to move
964 OptoReg::Name src_second = ra_->get_reg_second(in(1));
965 OptoReg::Name src_first = ra_->get_reg_first(in(1));
966 OptoReg::Name dst_second = ra_->get_reg_second(this );
967 OptoReg::Name dst_first = ra_->get_reg_first(this );
968
969 enum RC src_second_rc = rc_class(src_second);
970 enum RC src_first_rc = rc_class(src_first);
971 enum RC dst_second_rc = rc_class(dst_second);
972 enum RC dst_first_rc = rc_class(dst_first);
973
974 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
975
976 // Generate spill code!
977 int size = 0;
978
979 if( src_first == dst_first && src_second == dst_second )
980 return size; // Self copy, no move
981
982 if (bottom_type()->isa_vect() != NULL) {
983 uint ireg = ideal_reg();
984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
988 // mem -> mem
989 int src_offset = ra_->reg2offset(src_first);
990 int dst_offset = ra_->reg2offset(dst_first);
991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 int stack_offset = ra_->reg2offset(dst_first);
996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
998 int stack_offset = ra_->reg2offset(src_first);
999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1000 } else {
1001 ShouldNotReachHere();
1002 }
1003 }
1004
1005 // --------------------------------------
1006 // Check for mem-mem move. push/pop to move.
1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1008 if( src_second == dst_first ) { // overlapping stack copy ranges
1009 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1010 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1011 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1012 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1013 }
1014 // move low bits
1015 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1016 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1017 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1018 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1019 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1020 }
1021 return size;
1022 }
1023
1024 // --------------------------------------
1025 // Check for integer reg-reg copy
1026 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1027 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1028
1029 // Check for integer store
1030 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1031 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1032
1033 // Check for integer load
1034 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1035 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1036
1037 // Check for integer reg-xmm reg copy
1038 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1039 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1040 "no 64 bit integer-float reg moves" );
1041 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1042 }
1043 // --------------------------------------
1044 // Check for float reg-reg copy
1045 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1046 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1047 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1048 if( cbuf ) {
1049
1050 // Note the mucking with the register encode to compensate for the 0/1
1051 // indexing issue mentioned in a comment in the reg_def sections
1052 // for FPR registers many lines above here.
1053
1054 if( src_first != FPR1L_num ) {
1055 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1056 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1057 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1058 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1059 } else {
1060 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1061 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1062 }
1063 #ifndef PRODUCT
1064 } else if( !do_size ) {
1065 if( size != 0 ) st->print("\n\t");
1066 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1067 else st->print( "FST %s", Matcher::regName[dst_first]);
1068 #endif
1069 }
1070 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1071 }
1072
1073 // Check for float store
1074 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1075 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1076 }
1077
1078 // Check for float load
1079 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1080 int offset = ra_->reg2offset(src_first);
1081 const char *op_str;
1082 int op;
1083 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1084 op_str = "FLD_D";
1085 op = 0xDD;
1086 } else { // 32-bit load
1087 op_str = "FLD_S";
1088 op = 0xD9;
1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1090 }
1091 if( cbuf ) {
1092 emit_opcode (*cbuf, op );
1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1096 #ifndef PRODUCT
1097 } else if( !do_size ) {
1098 if( size != 0 ) st->print("\n\t");
1099 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1100 #endif
1101 }
1102 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1103 return size + 3+offset_size+2;
1104 }
1105
1106 // Check for xmm reg-reg copy
1107 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1108 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1109 (src_first+1 == src_second && dst_first+1 == dst_second),
1110 "no non-adjacent float-moves" );
1111 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1112 }
1113
1114 // Check for xmm reg-integer reg copy
1115 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1116 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1117 "no 64 bit float-integer reg moves" );
1118 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1119 }
1120
1121 // Check for xmm store
1122 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1123 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1124 }
1125
1126 // Check for float xmm load
1127 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1128 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1129 }
1130
1131 // Copy from float reg to xmm reg
1132 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1133 // copy to the top of stack from floating point reg
1134 // and use LEA to preserve flags
1135 if( cbuf ) {
1136 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1137 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1138 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1139 emit_d8(*cbuf,0xF8);
1140 #ifndef PRODUCT
1141 } else if( !do_size ) {
1142 if( size != 0 ) st->print("\n\t");
1143 st->print("LEA ESP,[ESP-8]");
1144 #endif
1145 }
1146 size += 4;
1147
1148 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1149
1150 // Copy from the temp memory to the xmm reg.
1151 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1152
1153 if( cbuf ) {
1154 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1155 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1156 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1157 emit_d8(*cbuf,0x08);
1158 #ifndef PRODUCT
1159 } else if( !do_size ) {
1160 if( size != 0 ) st->print("\n\t");
1161 st->print("LEA ESP,[ESP+8]");
1162 #endif
1163 }
1164 size += 4;
1165 return size;
1166 }
1167
1168 assert( size > 0, "missed a case" );
1169
1170 // --------------------------------------------------------------------
1171 // Check for second bits still needing moving.
1172 if( src_second == dst_second )
1173 return size; // Self copy; no move
1174 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1175
1176 // Check for second word int-int move
1177 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1178 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1179
1180 // Check for second word integer store
1181 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1182 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1183
1184 // Check for second word integer load
1185 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1186 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1187
1188
1189 Unimplemented();
1190 }
1191
1192 #ifndef PRODUCT
1193 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1194 implementation( NULL, ra_, false, st );
1195 }
1196 #endif
1197
1198 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1199 implementation( &cbuf, ra_, false, NULL );
1200 }
1201
1202 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1203 return implementation( NULL, ra_, true, NULL );
1204 }
1205
1206
1207 //=============================================================================
1208 #ifndef PRODUCT
1209 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1210 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1211 int reg = ra_->get_reg_first(this);
1212 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1213 }
1214 #endif
1215
1216 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1217 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1218 int reg = ra_->get_encode(this);
1219 if( offset >= 128 ) {
1220 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1221 emit_rm(cbuf, 0x2, reg, 0x04);
1222 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1223 emit_d32(cbuf, offset);
1224 }
1225 else {
1226 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1227 emit_rm(cbuf, 0x1, reg, 0x04);
1228 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1229 emit_d8(cbuf, offset);
1230 }
1231 }
1232
1233 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1235 if( offset >= 128 ) {
1236 return 7;
1237 }
1238 else {
1239 return 4;
1240 }
1241 }
1242
1243 //=============================================================================
1244
1245 // emit call stub, compiled java to interpreter
1246 void emit_java_to_interp(CodeBuffer &cbuf ) {
1247 // Stub is fixed up when the corresponding call is converted from calling
1248 // compiled code to calling interpreted code.
1249 // mov rbx,0
1250 // jmp -1
1251
1252 address mark = cbuf.insts_mark(); // get mark within main instrs section
1253
1254 // Note that the code buffer's insts_mark is always relative to insts.
1255 // That's why we must use the macroassembler to generate a stub.
1256 MacroAssembler _masm(&cbuf);
1257
1258 address base =
1259 __ start_a_stub(Compile::MAX_stubs_size);
1260 if (base == NULL) return; // CodeBuffer::expand failed
1261 // static stub relocation stores the instruction address of the call
1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1263 // static stub relocation also tags the Method* in the code-stream.
1264 __ mov_metadata(rbx, (Metadata*)NULL); // method is zapped till fixup time
1265 // This is recognized as unresolved by relocs/nativeInst/ic code
1266 __ jump(RuntimeAddress(__ pc()));
1267
1268 __ end_a_stub();
1269 // Update current stubs pointer and restore insts_end.
1270 }
1271 // size of call stub, compiled java to interpretor
1272 uint size_java_to_interp() {
1273 return 10; // movl; jmp
1274 }
1275 // relocation entries for call stub, compiled java to interpretor
1276 uint reloc_java_to_interp() {
1277 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1278 }
1279
1280 //=============================================================================
1281 #ifndef PRODUCT
1282 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1283 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1284 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1285 st->print_cr("\tNOP");
1286 st->print_cr("\tNOP");
1287 if( !OptoBreakpoint )
1288 st->print_cr("\tNOP");
1289 }
1290 #endif
1291
1292 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1293 MacroAssembler masm(&cbuf);
1294 #ifdef ASSERT
1295 uint insts_size = cbuf.insts_size();
1296 #endif
1297 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1298 masm.jump_cc(Assembler::notEqual,
1299 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1300 /* WARNING these NOPs are critical so that verified entry point is properly
1301 aligned for patching by NativeJump::patch_verified_entry() */
1302 int nops_cnt = 2;
1303 if( !OptoBreakpoint ) // Leave space for int3
1304 nops_cnt += 1;
1305 masm.nop(nops_cnt);
1306
1307 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1308 }
1309
1310 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1311 return OptoBreakpoint ? 11 : 12;
1312 }
1313
1314
1315 //=============================================================================
1316 uint size_exception_handler() {
1317 // NativeCall instruction size is the same as NativeJump.
1318 // exception handler starts out as jump and can be patched to
1319 // a call be deoptimization. (4932387)
1320 // Note that this value is also credited (in output.cpp) to
1321 // the size of the code section.
1322 return NativeJump::instruction_size;
1323 }
1324
1325 // Emit exception handler code. Stuff framesize into a register
1326 // and call a VM stub routine.
1327 int emit_exception_handler(CodeBuffer& cbuf) {
1328
1329 // Note that the code buffer's insts_mark is always relative to insts.
1330 // That's why we must use the macroassembler to generate a handler.
1331 MacroAssembler _masm(&cbuf);
1332 address base =
1333 __ start_a_stub(size_exception_handler());
1334 if (base == NULL) return 0; // CodeBuffer::expand failed
1335 int offset = __ offset();
1336 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1337 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1338 __ end_a_stub();
1339 return offset;
1340 }
1341
1342 uint size_deopt_handler() {
1343 // NativeCall instruction size is the same as NativeJump.
1344 // exception handler starts out as jump and can be patched to
1345 // a call be deoptimization. (4932387)
1346 // Note that this value is also credited (in output.cpp) to
1347 // the size of the code section.
1348 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1349 }
1350
1351 // Emit deopt handler code.
1352 int emit_deopt_handler(CodeBuffer& cbuf) {
1353
1354 // Note that the code buffer's insts_mark is always relative to insts.
1355 // That's why we must use the macroassembler to generate a handler.
1356 MacroAssembler _masm(&cbuf);
1357 address base =
1358 __ start_a_stub(size_exception_handler());
1359 if (base == NULL) return 0; // CodeBuffer::expand failed
1360 int offset = __ offset();
1361 InternalAddress here(__ pc());
1362 __ pushptr(here.addr());
1363
1364 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1365 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1366 __ end_a_stub();
1367 return offset;
1368 }
1369
1370 int Matcher::regnum_to_fpu_offset(int regnum) {
1371 return regnum - 32; // The FP registers are in the second chunk
1372 }
1373
1374 // This is UltraSparc specific, true just means we have fast l2f conversion
1375 const bool Matcher::convL2FSupported(void) {
1376 return true;
1377 }
1378
1379 // Is this branch offset short enough that a short branch can be used?
1380 //
1381 // NOTE: If the platform does not provide any short branch variants, then
1382 // this method should return false for offset 0.
1383 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1384 // The passed offset is relative to address of the branch.
1385 // On 86 a branch displacement is calculated relative to address
1386 // of a next instruction.
1387 offset -= br_size;
1388
1389 // the short version of jmpConUCF2 contains multiple branches,
1390 // making the reach slightly less
1391 if (rule == jmpConUCF2_rule)
1392 return (-126 <= offset && offset <= 125);
1393 return (-128 <= offset && offset <= 127);
1394 }
1395
1396 const bool Matcher::isSimpleConstant64(jlong value) {
1397 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1398 return false;
1399 }
1400
1401 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1402 const bool Matcher::init_array_count_is_in_bytes = false;
1403
1404 // Threshold size for cleararray.
1405 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1406
1407 // Needs 2 CMOV's for longs.
1408 const int Matcher::long_cmove_cost() { return 1; }
1409
1410 // No CMOVF/CMOVD with SSE/SSE2
1411 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1412
1413 // Should the Matcher clone shifts on addressing modes, expecting them to
1414 // be subsumed into complex addressing expressions or compute them into
1415 // registers? True for Intel but false for most RISCs
1416 const bool Matcher::clone_shift_expressions = true;
1417
1418 // Do we need to mask the count passed to shift instructions or does
1419 // the cpu only look at the lower 5/6 bits anyway?
1420 const bool Matcher::need_masked_shift_count = false;
1421
1422 bool Matcher::narrow_oop_use_complex_address() {
1423 ShouldNotCallThis();
1424 return true;
1425 }
1426
1427 bool Matcher::narrow_klass_use_complex_address() {
1428 ShouldNotCallThis();
1429 return true;
1430 }
1431
1432
1433 // Is it better to copy float constants, or load them directly from memory?
1434 // Intel can load a float constant from a direct address, requiring no
1435 // extra registers. Most RISCs will have to materialize an address into a
1436 // register first, so they would do better to copy the constant from stack.
1437 const bool Matcher::rematerialize_float_constants = true;
1438
1439 // If CPU can load and store mis-aligned doubles directly then no fixup is
1440 // needed. Else we split the double into 2 integer pieces and move it
1441 // piece-by-piece. Only happens when passing doubles into C code as the
1442 // Java calling convention forces doubles to be aligned.
1443 const bool Matcher::misaligned_doubles_ok = true;
1444
1445
1446 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1447 // Get the memory operand from the node
1448 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1449 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1450 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1451 uint opcnt = 1; // First operand
1452 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1453 while( idx >= skipped+num_edges ) {
1454 skipped += num_edges;
1455 opcnt++; // Bump operand count
1456 assert( opcnt < numopnds, "Accessing non-existent operand" );
1457 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1458 }
1459
1460 MachOper *memory = node->_opnds[opcnt];
1461 MachOper *new_memory = NULL;
1462 switch (memory->opcode()) {
1463 case DIRECT:
1464 case INDOFFSET32X:
1465 // No transformation necessary.
1466 return;
1467 case INDIRECT:
1468 new_memory = new (C) indirect_win95_safeOper( );
1469 break;
1470 case INDOFFSET8:
1471 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1472 break;
1473 case INDOFFSET32:
1474 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1475 break;
1476 case INDINDEXOFFSET:
1477 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1478 break;
1479 case INDINDEXSCALE:
1480 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1481 break;
1482 case INDINDEXSCALEOFFSET:
1483 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1484 break;
1485 case LOAD_LONG_INDIRECT:
1486 case LOAD_LONG_INDOFFSET32:
1487 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1488 return;
1489 default:
1490 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1491 return;
1492 }
1493 node->_opnds[opcnt] = new_memory;
1494 }
1495
1496 // Advertise here if the CPU requires explicit rounding operations
1497 // to implement the UseStrictFP mode.
1498 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1499
1500 // Are floats conerted to double when stored to stack during deoptimization?
1501 // On x32 it is stored with convertion only when FPU is used for floats.
1502 bool Matcher::float_in_double() { return (UseSSE == 0); }
1503
1504 // Do ints take an entire long register or just half?
1505 const bool Matcher::int_in_long = false;
1506
1507 // Return whether or not this register is ever used as an argument. This
1508 // function is used on startup to build the trampoline stubs in generateOptoStub.
1509 // Registers not mentioned will be killed by the VM call in the trampoline, and
1510 // arguments in those registers not be available to the callee.
1511 bool Matcher::can_be_java_arg( int reg ) {
1512 if( reg == ECX_num || reg == EDX_num ) return true;
1513 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1514 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1515 return false;
1516 }
1517
1518 bool Matcher::is_spillable_arg( int reg ) {
1519 return can_be_java_arg(reg);
1520 }
1521
1522 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1523 // Use hardware integer DIV instruction when
1524 // it is faster than a code which use multiply.
1525 // Only when constant divisor fits into 32 bit
1526 // (min_jint is excluded to get only correct
1527 // positive 32 bit values from negative).
1528 return VM_Version::has_fast_idiv() &&
1529 (divisor == (int)divisor && divisor != min_jint);
1530 }
1531
1532 // Register for DIVI projection of divmodI
1533 RegMask Matcher::divI_proj_mask() {
1534 return EAX_REG_mask();
1535 }
1536
1537 // Register for MODI projection of divmodI
1538 RegMask Matcher::modI_proj_mask() {
1539 return EDX_REG_mask();
1540 }
1541
1542 // Register for DIVL projection of divmodL
1543 RegMask Matcher::divL_proj_mask() {
1544 ShouldNotReachHere();
1545 return RegMask();
1546 }
1547
1548 // Register for MODL projection of divmodL
1549 RegMask Matcher::modL_proj_mask() {
1550 ShouldNotReachHere();
1551 return RegMask();
1552 }
1553
1554 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1555 return EBP_REG_mask();
1556 }
1557
1558 // Returns true if the high 32 bits of the value is known to be zero.
1559 bool is_operand_hi32_zero(Node* n) {
1560 int opc = n->Opcode();
1561 if (opc == Op_LoadUI2L) {
1562 return true;
1563 }
1564 if (opc == Op_AndL) {
1565 Node* o2 = n->in(2);
1566 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1567 return true;
1568 }
1569 }
1570 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1571 return true;
1572 }
1573 return false;
1574 }
1575
1576 %}
1577
1578 //----------ENCODING BLOCK-----------------------------------------------------
1579 // This block specifies the encoding classes used by the compiler to output
1580 // byte streams. Encoding classes generate functions which are called by
1581 // Machine Instruction Nodes in order to generate the bit encoding of the
1582 // instruction. Operands specify their base encoding interface with the
1583 // interface keyword. There are currently supported four interfaces,
1584 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1585 // operand to generate a function which returns its register number when
1586 // queried. CONST_INTER causes an operand to generate a function which
1587 // returns the value of the constant when queried. MEMORY_INTER causes an
1588 // operand to generate four functions which return the Base Register, the
1589 // Index Register, the Scale Value, and the Offset Value of the operand when
1590 // queried. COND_INTER causes an operand to generate six functions which
1591 // return the encoding code (ie - encoding bits for the instruction)
1592 // associated with each basic boolean condition for a conditional instruction.
1593 // Instructions specify two basic values for encoding. They use the
1594 // ins_encode keyword to specify their encoding class (which must be one of
1595 // the class names specified in the encoding block), and they use the
1596 // opcode keyword to specify, in order, their primary, secondary, and
1597 // tertiary opcode. Only the opcode sections which a particular instruction
1598 // needs for encoding need to be specified.
1599 encode %{
1600 // Build emit functions for each basic byte or larger field in the intel
1601 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1602 // code in the enc_class source block. Emit functions will live in the
1603 // main source block for now. In future, we can generalize this by
1604 // adding a syntax that specifies the sizes of fields in an order,
1605 // so that the adlc can build the emit functions automagically
1606
1607 // Emit primary opcode
1608 enc_class OpcP %{
1609 emit_opcode(cbuf, $primary);
1610 %}
1611
1612 // Emit secondary opcode
1613 enc_class OpcS %{
1614 emit_opcode(cbuf, $secondary);
1615 %}
1616
1617 // Emit opcode directly
1618 enc_class Opcode(immI d8) %{
1619 emit_opcode(cbuf, $d8$$constant);
1620 %}
1621
1622 enc_class SizePrefix %{
1623 emit_opcode(cbuf,0x66);
1624 %}
1625
1626 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1627 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1628 %}
1629
1630 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1631 emit_opcode(cbuf,$opcode$$constant);
1632 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1633 %}
1634
1635 enc_class mov_r32_imm0( rRegI dst ) %{
1636 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1637 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1638 %}
1639
1640 enc_class cdq_enc %{
1641 // Full implementation of Java idiv and irem; checks for
1642 // special case as described in JVM spec., p.243 & p.271.
1643 //
1644 // normal case special case
1645 //
1646 // input : rax,: dividend min_int
1647 // reg: divisor -1
1648 //
1649 // output: rax,: quotient (= rax, idiv reg) min_int
1650 // rdx: remainder (= rax, irem reg) 0
1651 //
1652 // Code sequnce:
1653 //
1654 // 81 F8 00 00 00 80 cmp rax,80000000h
1655 // 0F 85 0B 00 00 00 jne normal_case
1656 // 33 D2 xor rdx,edx
1657 // 83 F9 FF cmp rcx,0FFh
1658 // 0F 84 03 00 00 00 je done
1659 // normal_case:
1660 // 99 cdq
1661 // F7 F9 idiv rax,ecx
1662 // done:
1663 //
1664 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1665 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1666 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1667 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1668 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1669 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1670 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1671 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1672 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1673 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1674 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1675 // normal_case:
1676 emit_opcode(cbuf,0x99); // cdq
1677 // idiv (note: must be emitted by the user of this rule)
1678 // normal:
1679 %}
1680
1681 // Dense encoding for older common ops
1682 enc_class Opc_plus(immI opcode, rRegI reg) %{
1683 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1684 %}
1685
1686
1687 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1688 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1689 // Check for 8-bit immediate, and set sign extend bit in opcode
1690 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1691 emit_opcode(cbuf, $primary | 0x02);
1692 }
1693 else { // If 32-bit immediate
1694 emit_opcode(cbuf, $primary);
1695 }
1696 %}
1697
1698 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1699 // Emit primary opcode and set sign-extend bit
1700 // Check for 8-bit immediate, and set sign extend bit in opcode
1701 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1702 emit_opcode(cbuf, $primary | 0x02); }
1703 else { // If 32-bit immediate
1704 emit_opcode(cbuf, $primary);
1705 }
1706 // Emit r/m byte with secondary opcode, after primary opcode.
1707 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1708 %}
1709
1710 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1711 // Check for 8-bit immediate, and set sign extend bit in opcode
1712 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1713 $$$emit8$imm$$constant;
1714 }
1715 else { // If 32-bit immediate
1716 // Output immediate
1717 $$$emit32$imm$$constant;
1718 }
1719 %}
1720
1721 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1722 // Emit primary opcode and set sign-extend bit
1723 // Check for 8-bit immediate, and set sign extend bit in opcode
1724 int con = (int)$imm$$constant; // Throw away top bits
1725 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1726 // Emit r/m byte with secondary opcode, after primary opcode.
1727 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1728 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1729 else emit_d32(cbuf,con);
1730 %}
1731
1732 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1733 // Emit primary opcode and set sign-extend bit
1734 // Check for 8-bit immediate, and set sign extend bit in opcode
1735 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1736 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1737 // Emit r/m byte with tertiary opcode, after primary opcode.
1738 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1739 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1740 else emit_d32(cbuf,con);
1741 %}
1742
1743 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1744 emit_cc(cbuf, $secondary, $dst$$reg );
1745 %}
1746
1747 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1748 int destlo = $dst$$reg;
1749 int desthi = HIGH_FROM_LOW(destlo);
1750 // bswap lo
1751 emit_opcode(cbuf, 0x0F);
1752 emit_cc(cbuf, 0xC8, destlo);
1753 // bswap hi
1754 emit_opcode(cbuf, 0x0F);
1755 emit_cc(cbuf, 0xC8, desthi);
1756 // xchg lo and hi
1757 emit_opcode(cbuf, 0x87);
1758 emit_rm(cbuf, 0x3, destlo, desthi);
1759 %}
1760
1761 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1762 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1763 %}
1764
1765 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1766 $$$emit8$primary;
1767 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1768 %}
1769
1770 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1771 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1772 emit_d8(cbuf, op >> 8 );
1773 emit_d8(cbuf, op & 255);
1774 %}
1775
1776 // emulate a CMOV with a conditional branch around a MOV
1777 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1778 // Invert sense of branch from sense of CMOV
1779 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1780 emit_d8( cbuf, $brOffs$$constant );
1781 %}
1782
1783 enc_class enc_PartialSubtypeCheck( ) %{
1784 Register Redi = as_Register(EDI_enc); // result register
1785 Register Reax = as_Register(EAX_enc); // super class
1786 Register Recx = as_Register(ECX_enc); // killed
1787 Register Resi = as_Register(ESI_enc); // sub class
1788 Label miss;
1789
1790 MacroAssembler _masm(&cbuf);
1791 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1792 NULL, &miss,
1793 /*set_cond_codes:*/ true);
1794 if ($primary) {
1795 __ xorptr(Redi, Redi);
1796 }
1797 __ bind(miss);
1798 %}
1799
1800 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1801 MacroAssembler masm(&cbuf);
1802 int start = masm.offset();
1803 if (UseSSE >= 2) {
1804 if (VerifyFPU) {
1805 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1806 }
1807 } else {
1808 // External c_calling_convention expects the FPU stack to be 'clean'.
1809 // Compiled code leaves it dirty. Do cleanup now.
1810 masm.empty_FPU_stack();
1811 }
1812 if (sizeof_FFree_Float_Stack_All == -1) {
1813 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1814 } else {
1815 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1816 }
1817 %}
1818
1819 enc_class Verify_FPU_For_Leaf %{
1820 if( VerifyFPU ) {
1821 MacroAssembler masm(&cbuf);
1822 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1823 }
1824 %}
1825
1826 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1827 // This is the instruction starting address for relocation info.
1828 cbuf.set_insts_mark();
1829 $$$emit8$primary;
1830 // CALL directly to the runtime
1831 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1832 runtime_call_Relocation::spec(), RELOC_IMM32 );
1833
1834 if (UseSSE >= 2) {
1835 MacroAssembler _masm(&cbuf);
1836 BasicType rt = tf()->return_type();
1837
1838 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1839 // A C runtime call where the return value is unused. In SSE2+
1840 // mode the result needs to be removed from the FPU stack. It's
1841 // likely that this function call could be removed by the
1842 // optimizer if the C function is a pure function.
1843 __ ffree(0);
1844 } else if (rt == T_FLOAT) {
1845 __ lea(rsp, Address(rsp, -4));
1846 __ fstp_s(Address(rsp, 0));
1847 __ movflt(xmm0, Address(rsp, 0));
1848 __ lea(rsp, Address(rsp, 4));
1849 } else if (rt == T_DOUBLE) {
1850 __ lea(rsp, Address(rsp, -8));
1851 __ fstp_d(Address(rsp, 0));
1852 __ movdbl(xmm0, Address(rsp, 0));
1853 __ lea(rsp, Address(rsp, 8));
1854 }
1855 }
1856 %}
1857
1858
1859 enc_class pre_call_FPU %{
1860 // If method sets FPU control word restore it here
1861 debug_only(int off0 = cbuf.insts_size());
1862 if( Compile::current()->in_24_bit_fp_mode() ) {
1863 MacroAssembler masm(&cbuf);
1864 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1865 }
1866 debug_only(int off1 = cbuf.insts_size());
1867 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1868 %}
1869
1870 enc_class post_call_FPU %{
1871 // If method sets FPU control word do it here also
1872 if( Compile::current()->in_24_bit_fp_mode() ) {
1873 MacroAssembler masm(&cbuf);
1874 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1875 }
1876 %}
1877
1878 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1879 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1880 // who we intended to call.
1881 cbuf.set_insts_mark();
1882 $$$emit8$primary;
1883 if ( !_method ) {
1884 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1885 runtime_call_Relocation::spec(), RELOC_IMM32 );
1886 } else if(_optimized_virtual) {
1887 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1888 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1889 } else {
1890 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1891 static_call_Relocation::spec(), RELOC_IMM32 );
1892 }
1893 if( _method ) { // Emit stub for static call
1894 emit_java_to_interp(cbuf);
1895 }
1896 %}
1897
1898 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1899 MacroAssembler _masm(&cbuf);
1900 __ ic_call((address)$meth$$method);
1901 %}
1902
1903 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1904 int disp = in_bytes(Method::from_compiled_offset());
1905 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1906
1907 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1908 cbuf.set_insts_mark();
1909 $$$emit8$primary;
1910 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1911 emit_d8(cbuf, disp); // Displacement
1912
1913 %}
1914
1915 // Following encoding is no longer used, but may be restored if calling
1916 // convention changes significantly.
1917 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1918 //
1919 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1920 // // int ic_reg = Matcher::inline_cache_reg();
1921 // // int ic_encode = Matcher::_regEncode[ic_reg];
1922 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1923 // // int imo_encode = Matcher::_regEncode[imo_reg];
1924 //
1925 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1926 // // // so we load it immediately before the call
1927 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1928 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1929 //
1930 // // xor rbp,ebp
1931 // emit_opcode(cbuf, 0x33);
1932 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1933 //
1934 // // CALL to interpreter.
1935 // cbuf.set_insts_mark();
1936 // $$$emit8$primary;
1937 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1938 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1939 // %}
1940
1941 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1942 $$$emit8$primary;
1943 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1944 $$$emit8$shift$$constant;
1945 %}
1946
1947 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1948 // Load immediate does not have a zero or sign extended version
1949 // for 8-bit immediates
1950 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1951 $$$emit32$src$$constant;
1952 %}
1953
1954 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1955 // Load immediate does not have a zero or sign extended version
1956 // for 8-bit immediates
1957 emit_opcode(cbuf, $primary + $dst$$reg);
1958 $$$emit32$src$$constant;
1959 %}
1960
1961 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1962 // Load immediate does not have a zero or sign extended version
1963 // for 8-bit immediates
1964 int dst_enc = $dst$$reg;
1965 int src_con = $src$$constant & 0x0FFFFFFFFL;
1966 if (src_con == 0) {
1967 // xor dst, dst
1968 emit_opcode(cbuf, 0x33);
1969 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1970 } else {
1971 emit_opcode(cbuf, $primary + dst_enc);
1972 emit_d32(cbuf, src_con);
1973 }
1974 %}
1975
1976 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1977 // Load immediate does not have a zero or sign extended version
1978 // for 8-bit immediates
1979 int dst_enc = $dst$$reg + 2;
1980 int src_con = ((julong)($src$$constant)) >> 32;
1981 if (src_con == 0) {
1982 // xor dst, dst
1983 emit_opcode(cbuf, 0x33);
1984 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1985 } else {
1986 emit_opcode(cbuf, $primary + dst_enc);
1987 emit_d32(cbuf, src_con);
1988 }
1989 %}
1990
1991
1992 // Encode a reg-reg copy. If it is useless, then empty encoding.
1993 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1994 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1995 %}
1996
1997 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1998 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1999 %}
2000
2001 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
2002 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2003 %}
2004
2005 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2006 $$$emit8$primary;
2007 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2008 %}
2009
2010 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2011 $$$emit8$secondary;
2012 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2013 %}
2014
2015 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2016 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2017 %}
2018
2019 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2020 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2021 %}
2022
2023 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2024 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2025 %}
2026
2027 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2028 // Output immediate
2029 $$$emit32$src$$constant;
2030 %}
2031
2032 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2033 // Output Float immediate bits
2034 jfloat jf = $src$$constant;
2035 int jf_as_bits = jint_cast( jf );
2036 emit_d32(cbuf, jf_as_bits);
2037 %}
2038
2039 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2040 // Output Float immediate bits
2041 jfloat jf = $src$$constant;
2042 int jf_as_bits = jint_cast( jf );
2043 emit_d32(cbuf, jf_as_bits);
2044 %}
2045
2046 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2047 // Output immediate
2048 $$$emit16$src$$constant;
2049 %}
2050
2051 enc_class Con_d32(immI src) %{
2052 emit_d32(cbuf,$src$$constant);
2053 %}
2054
2055 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2056 // Output immediate memory reference
2057 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2058 emit_d32(cbuf, 0x00);
2059 %}
2060
2061 enc_class lock_prefix( ) %{
2062 if( os::is_MP() )
2063 emit_opcode(cbuf,0xF0); // [Lock]
2064 %}
2065
2066 // Cmp-xchg long value.
2067 // Note: we need to swap rbx, and rcx before and after the
2068 // cmpxchg8 instruction because the instruction uses
2069 // rcx as the high order word of the new value to store but
2070 // our register encoding uses rbx,.
2071 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2072
2073 // XCHG rbx,ecx
2074 emit_opcode(cbuf,0x87);
2075 emit_opcode(cbuf,0xD9);
2076 // [Lock]
2077 if( os::is_MP() )
2078 emit_opcode(cbuf,0xF0);
2079 // CMPXCHG8 [Eptr]
2080 emit_opcode(cbuf,0x0F);
2081 emit_opcode(cbuf,0xC7);
2082 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2083 // XCHG rbx,ecx
2084 emit_opcode(cbuf,0x87);
2085 emit_opcode(cbuf,0xD9);
2086 %}
2087
2088 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2089 // [Lock]
2090 if( os::is_MP() )
2091 emit_opcode(cbuf,0xF0);
2092
2093 // CMPXCHG [Eptr]
2094 emit_opcode(cbuf,0x0F);
2095 emit_opcode(cbuf,0xB1);
2096 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2097 %}
2098
2099 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2100 int res_encoding = $res$$reg;
2101
2102 // MOV res,0
2103 emit_opcode( cbuf, 0xB8 + res_encoding);
2104 emit_d32( cbuf, 0 );
2105 // JNE,s fail
2106 emit_opcode(cbuf,0x75);
2107 emit_d8(cbuf, 5 );
2108 // MOV res,1
2109 emit_opcode( cbuf, 0xB8 + res_encoding);
2110 emit_d32( cbuf, 1 );
2111 // fail:
2112 %}
2113
2114 enc_class set_instruction_start( ) %{
2115 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2116 %}
2117
2118 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2119 int reg_encoding = $ereg$$reg;
2120 int base = $mem$$base;
2121 int index = $mem$$index;
2122 int scale = $mem$$scale;
2123 int displace = $mem$$disp;
2124 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2125 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2126 %}
2127
2128 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2129 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2130 int base = $mem$$base;
2131 int index = $mem$$index;
2132 int scale = $mem$$scale;
2133 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2134 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2135 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2136 %}
2137
2138 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2139 int r1, r2;
2140 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2141 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2142 emit_opcode(cbuf,0x0F);
2143 emit_opcode(cbuf,$tertiary);
2144 emit_rm(cbuf, 0x3, r1, r2);
2145 emit_d8(cbuf,$cnt$$constant);
2146 emit_d8(cbuf,$primary);
2147 emit_rm(cbuf, 0x3, $secondary, r1);
2148 emit_d8(cbuf,$cnt$$constant);
2149 %}
2150
2151 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2152 emit_opcode( cbuf, 0x8B ); // Move
2153 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2154 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2155 emit_d8(cbuf,$primary);
2156 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2157 emit_d8(cbuf,$cnt$$constant-32);
2158 }
2159 emit_d8(cbuf,$primary);
2160 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2161 emit_d8(cbuf,31);
2162 %}
2163
2164 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2165 int r1, r2;
2166 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2167 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2168
2169 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2170 emit_rm(cbuf, 0x3, r1, r2);
2171 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2172 emit_opcode(cbuf,$primary);
2173 emit_rm(cbuf, 0x3, $secondary, r1);
2174 emit_d8(cbuf,$cnt$$constant-32);
2175 }
2176 emit_opcode(cbuf,0x33); // XOR r2,r2
2177 emit_rm(cbuf, 0x3, r2, r2);
2178 %}
2179
2180 // Clone of RegMem but accepts an extra parameter to access each
2181 // half of a double in memory; it never needs relocation info.
2182 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2183 emit_opcode(cbuf,$opcode$$constant);
2184 int reg_encoding = $rm_reg$$reg;
2185 int base = $mem$$base;
2186 int index = $mem$$index;
2187 int scale = $mem$$scale;
2188 int displace = $mem$$disp + $disp_for_half$$constant;
2189 relocInfo::relocType disp_reloc = relocInfo::none;
2190 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2191 %}
2192
2193 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2194 //
2195 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2196 // and it never needs relocation information.
2197 // Frequently used to move data between FPU's Stack Top and memory.
2198 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2199 int rm_byte_opcode = $rm_opcode$$constant;
2200 int base = $mem$$base;
2201 int index = $mem$$index;
2202 int scale = $mem$$scale;
2203 int displace = $mem$$disp;
2204 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2205 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2206 %}
2207
2208 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2209 int rm_byte_opcode = $rm_opcode$$constant;
2210 int base = $mem$$base;
2211 int index = $mem$$index;
2212 int scale = $mem$$scale;
2213 int displace = $mem$$disp;
2214 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2215 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2216 %}
2217
2218 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2219 int reg_encoding = $dst$$reg;
2220 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2221 int index = 0x04; // 0x04 indicates no index
2222 int scale = 0x00; // 0x00 indicates no scale
2223 int displace = $src1$$constant; // 0x00 indicates no displacement
2224 relocInfo::relocType disp_reloc = relocInfo::none;
2225 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2226 %}
2227
2228 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2229 // Compare dst,src
2230 emit_opcode(cbuf,0x3B);
2231 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2232 // jmp dst < src around move
2233 emit_opcode(cbuf,0x7C);
2234 emit_d8(cbuf,2);
2235 // move dst,src
2236 emit_opcode(cbuf,0x8B);
2237 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2238 %}
2239
2240 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2241 // Compare dst,src
2242 emit_opcode(cbuf,0x3B);
2243 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2244 // jmp dst > src around move
2245 emit_opcode(cbuf,0x7F);
2246 emit_d8(cbuf,2);
2247 // move dst,src
2248 emit_opcode(cbuf,0x8B);
2249 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2250 %}
2251
2252 enc_class enc_FPR_store(memory mem, regDPR src) %{
2253 // If src is FPR1, we can just FST to store it.
2254 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2255 int reg_encoding = 0x2; // Just store
2256 int base = $mem$$base;
2257 int index = $mem$$index;
2258 int scale = $mem$$scale;
2259 int displace = $mem$$disp;
2260 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2261 if( $src$$reg != FPR1L_enc ) {
2262 reg_encoding = 0x3; // Store & pop
2263 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2264 emit_d8( cbuf, 0xC0-1+$src$$reg );
2265 }
2266 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2267 emit_opcode(cbuf,$primary);
2268 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2269 %}
2270
2271 enc_class neg_reg(rRegI dst) %{
2272 // NEG $dst
2273 emit_opcode(cbuf,0xF7);
2274 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2275 %}
2276
2277 enc_class setLT_reg(eCXRegI dst) %{
2278 // SETLT $dst
2279 emit_opcode(cbuf,0x0F);
2280 emit_opcode(cbuf,0x9C);
2281 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2282 %}
2283
2284 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2285 int tmpReg = $tmp$$reg;
2286
2287 // SUB $p,$q
2288 emit_opcode(cbuf,0x2B);
2289 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2290 // SBB $tmp,$tmp
2291 emit_opcode(cbuf,0x1B);
2292 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2293 // AND $tmp,$y
2294 emit_opcode(cbuf,0x23);
2295 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2296 // ADD $p,$tmp
2297 emit_opcode(cbuf,0x03);
2298 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2299 %}
2300
2301 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2302 int tmpReg = $tmp$$reg;
2303
2304 // SUB $p,$q
2305 emit_opcode(cbuf,0x2B);
2306 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2307 // SBB $tmp,$tmp
2308 emit_opcode(cbuf,0x1B);
2309 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2310 // AND $tmp,$y
2311 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2312 emit_opcode(cbuf,0x23);
2313 int reg_encoding = tmpReg;
2314 int base = $mem$$base;
2315 int index = $mem$$index;
2316 int scale = $mem$$scale;
2317 int displace = $mem$$disp;
2318 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2319 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2320 // ADD $p,$tmp
2321 emit_opcode(cbuf,0x03);
2322 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2323 %}
2324
2325 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2326 // TEST shift,32
2327 emit_opcode(cbuf,0xF7);
2328 emit_rm(cbuf, 0x3, 0, ECX_enc);
2329 emit_d32(cbuf,0x20);
2330 // JEQ,s small
2331 emit_opcode(cbuf, 0x74);
2332 emit_d8(cbuf, 0x04);
2333 // MOV $dst.hi,$dst.lo
2334 emit_opcode( cbuf, 0x8B );
2335 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2336 // CLR $dst.lo
2337 emit_opcode(cbuf, 0x33);
2338 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2339 // small:
2340 // SHLD $dst.hi,$dst.lo,$shift
2341 emit_opcode(cbuf,0x0F);
2342 emit_opcode(cbuf,0xA5);
2343 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2344 // SHL $dst.lo,$shift"
2345 emit_opcode(cbuf,0xD3);
2346 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2347 %}
2348
2349 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2350 // TEST shift,32
2351 emit_opcode(cbuf,0xF7);
2352 emit_rm(cbuf, 0x3, 0, ECX_enc);
2353 emit_d32(cbuf,0x20);
2354 // JEQ,s small
2355 emit_opcode(cbuf, 0x74);
2356 emit_d8(cbuf, 0x04);
2357 // MOV $dst.lo,$dst.hi
2358 emit_opcode( cbuf, 0x8B );
2359 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2360 // CLR $dst.hi
2361 emit_opcode(cbuf, 0x33);
2362 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2363 // small:
2364 // SHRD $dst.lo,$dst.hi,$shift
2365 emit_opcode(cbuf,0x0F);
2366 emit_opcode(cbuf,0xAD);
2367 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2368 // SHR $dst.hi,$shift"
2369 emit_opcode(cbuf,0xD3);
2370 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2371 %}
2372
2373 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2374 // TEST shift,32
2375 emit_opcode(cbuf,0xF7);
2376 emit_rm(cbuf, 0x3, 0, ECX_enc);
2377 emit_d32(cbuf,0x20);
2378 // JEQ,s small
2379 emit_opcode(cbuf, 0x74);
2380 emit_d8(cbuf, 0x05);
2381 // MOV $dst.lo,$dst.hi
2382 emit_opcode( cbuf, 0x8B );
2383 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2384 // SAR $dst.hi,31
2385 emit_opcode(cbuf, 0xC1);
2386 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2387 emit_d8(cbuf, 0x1F );
2388 // small:
2389 // SHRD $dst.lo,$dst.hi,$shift
2390 emit_opcode(cbuf,0x0F);
2391 emit_opcode(cbuf,0xAD);
2392 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2393 // SAR $dst.hi,$shift"
2394 emit_opcode(cbuf,0xD3);
2395 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2396 %}
2397
2398
2399 // ----------------- Encodings for floating point unit -----------------
2400 // May leave result in FPU-TOS or FPU reg depending on opcodes
2401 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2402 $$$emit8$primary;
2403 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2404 %}
2405
2406 // Pop argument in FPR0 with FSTP ST(0)
2407 enc_class PopFPU() %{
2408 emit_opcode( cbuf, 0xDD );
2409 emit_d8( cbuf, 0xD8 );
2410 %}
2411
2412 // !!!!! equivalent to Pop_Reg_F
2413 enc_class Pop_Reg_DPR( regDPR dst ) %{
2414 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2415 emit_d8( cbuf, 0xD8+$dst$$reg );
2416 %}
2417
2418 enc_class Push_Reg_DPR( regDPR dst ) %{
2419 emit_opcode( cbuf, 0xD9 );
2420 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2421 %}
2422
2423 enc_class strictfp_bias1( regDPR dst ) %{
2424 emit_opcode( cbuf, 0xDB ); // FLD m80real
2425 emit_opcode( cbuf, 0x2D );
2426 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2427 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2428 emit_opcode( cbuf, 0xC8+$dst$$reg );
2429 %}
2430
2431 enc_class strictfp_bias2( regDPR dst ) %{
2432 emit_opcode( cbuf, 0xDB ); // FLD m80real
2433 emit_opcode( cbuf, 0x2D );
2434 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2435 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2436 emit_opcode( cbuf, 0xC8+$dst$$reg );
2437 %}
2438
2439 // Special case for moving an integer register to a stack slot.
2440 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2441 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2442 %}
2443
2444 // Special case for moving a register to a stack slot.
2445 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2446 // Opcode already emitted
2447 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2448 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2449 emit_d32(cbuf, $dst$$disp); // Displacement
2450 %}
2451
2452 // Push the integer in stackSlot 'src' onto FP-stack
2453 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2454 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2455 %}
2456
2457 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2458 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2459 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2460 %}
2461
2462 // Same as Pop_Mem_F except for opcode
2463 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2464 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2465 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2466 %}
2467
2468 enc_class Pop_Reg_FPR( regFPR dst ) %{
2469 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2470 emit_d8( cbuf, 0xD8+$dst$$reg );
2471 %}
2472
2473 enc_class Push_Reg_FPR( regFPR dst ) %{
2474 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2475 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2476 %}
2477
2478 // Push FPU's float to a stack-slot, and pop FPU-stack
2479 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2480 int pop = 0x02;
2481 if ($src$$reg != FPR1L_enc) {
2482 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2483 emit_d8( cbuf, 0xC0-1+$src$$reg );
2484 pop = 0x03;
2485 }
2486 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2487 %}
2488
2489 // Push FPU's double to a stack-slot, and pop FPU-stack
2490 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2491 int pop = 0x02;
2492 if ($src$$reg != FPR1L_enc) {
2493 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2494 emit_d8( cbuf, 0xC0-1+$src$$reg );
2495 pop = 0x03;
2496 }
2497 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2498 %}
2499
2500 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2501 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2502 int pop = 0xD0 - 1; // -1 since we skip FLD
2503 if ($src$$reg != FPR1L_enc) {
2504 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2505 emit_d8( cbuf, 0xC0-1+$src$$reg );
2506 pop = 0xD8;
2507 }
2508 emit_opcode( cbuf, 0xDD );
2509 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2510 %}
2511
2512
2513 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2514 // load dst in FPR0
2515 emit_opcode( cbuf, 0xD9 );
2516 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2517 if ($src$$reg != FPR1L_enc) {
2518 // fincstp
2519 emit_opcode (cbuf, 0xD9);
2520 emit_opcode (cbuf, 0xF7);
2521 // swap src with FPR1:
2522 // FXCH FPR1 with src
2523 emit_opcode(cbuf, 0xD9);
2524 emit_d8(cbuf, 0xC8-1+$src$$reg );
2525 // fdecstp
2526 emit_opcode (cbuf, 0xD9);
2527 emit_opcode (cbuf, 0xF6);
2528 }
2529 %}
2530
2531 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2532 MacroAssembler _masm(&cbuf);
2533 __ subptr(rsp, 8);
2534 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2535 __ fld_d(Address(rsp, 0));
2536 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2537 __ fld_d(Address(rsp, 0));
2538 %}
2539
2540 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2541 MacroAssembler _masm(&cbuf);
2542 __ subptr(rsp, 4);
2543 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2544 __ fld_s(Address(rsp, 0));
2545 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2546 __ fld_s(Address(rsp, 0));
2547 %}
2548
2549 enc_class Push_ResultD(regD dst) %{
2550 MacroAssembler _masm(&cbuf);
2551 __ fstp_d(Address(rsp, 0));
2552 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2553 __ addptr(rsp, 8);
2554 %}
2555
2556 enc_class Push_ResultF(regF dst, immI d8) %{
2557 MacroAssembler _masm(&cbuf);
2558 __ fstp_s(Address(rsp, 0));
2559 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2560 __ addptr(rsp, $d8$$constant);
2561 %}
2562
2563 enc_class Push_SrcD(regD src) %{
2564 MacroAssembler _masm(&cbuf);
2565 __ subptr(rsp, 8);
2566 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2567 __ fld_d(Address(rsp, 0));
2568 %}
2569
2570 enc_class push_stack_temp_qword() %{
2571 MacroAssembler _masm(&cbuf);
2572 __ subptr(rsp, 8);
2573 %}
2574
2575 enc_class pop_stack_temp_qword() %{
2576 MacroAssembler _masm(&cbuf);
2577 __ addptr(rsp, 8);
2578 %}
2579
2580 enc_class push_xmm_to_fpr1(regD src) %{
2581 MacroAssembler _masm(&cbuf);
2582 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2583 __ fld_d(Address(rsp, 0));
2584 %}
2585
2586 enc_class Push_Result_Mod_DPR( regDPR src) %{
2587 if ($src$$reg != FPR1L_enc) {
2588 // fincstp
2589 emit_opcode (cbuf, 0xD9);
2590 emit_opcode (cbuf, 0xF7);
2591 // FXCH FPR1 with src
2592 emit_opcode(cbuf, 0xD9);
2593 emit_d8(cbuf, 0xC8-1+$src$$reg );
2594 // fdecstp
2595 emit_opcode (cbuf, 0xD9);
2596 emit_opcode (cbuf, 0xF6);
2597 }
2598 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2599 // // FSTP FPR$dst$$reg
2600 // emit_opcode( cbuf, 0xDD );
2601 // emit_d8( cbuf, 0xD8+$dst$$reg );
2602 %}
2603
2604 enc_class fnstsw_sahf_skip_parity() %{
2605 // fnstsw ax
2606 emit_opcode( cbuf, 0xDF );
2607 emit_opcode( cbuf, 0xE0 );
2608 // sahf
2609 emit_opcode( cbuf, 0x9E );
2610 // jnp ::skip
2611 emit_opcode( cbuf, 0x7B );
2612 emit_opcode( cbuf, 0x05 );
2613 %}
2614
2615 enc_class emitModDPR() %{
2616 // fprem must be iterative
2617 // :: loop
2618 // fprem
2619 emit_opcode( cbuf, 0xD9 );
2620 emit_opcode( cbuf, 0xF8 );
2621 // wait
2622 emit_opcode( cbuf, 0x9b );
2623 // fnstsw ax
2624 emit_opcode( cbuf, 0xDF );
2625 emit_opcode( cbuf, 0xE0 );
2626 // sahf
2627 emit_opcode( cbuf, 0x9E );
2628 // jp ::loop
2629 emit_opcode( cbuf, 0x0F );
2630 emit_opcode( cbuf, 0x8A );
2631 emit_opcode( cbuf, 0xF4 );
2632 emit_opcode( cbuf, 0xFF );
2633 emit_opcode( cbuf, 0xFF );
2634 emit_opcode( cbuf, 0xFF );
2635 %}
2636
2637 enc_class fpu_flags() %{
2638 // fnstsw_ax
2639 emit_opcode( cbuf, 0xDF);
2640 emit_opcode( cbuf, 0xE0);
2641 // test ax,0x0400
2642 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2643 emit_opcode( cbuf, 0xA9 );
2644 emit_d16 ( cbuf, 0x0400 );
2645 // // // This sequence works, but stalls for 12-16 cycles on PPro
2646 // // test rax,0x0400
2647 // emit_opcode( cbuf, 0xA9 );
2648 // emit_d32 ( cbuf, 0x00000400 );
2649 //
2650 // jz exit (no unordered comparison)
2651 emit_opcode( cbuf, 0x74 );
2652 emit_d8 ( cbuf, 0x02 );
2653 // mov ah,1 - treat as LT case (set carry flag)
2654 emit_opcode( cbuf, 0xB4 );
2655 emit_d8 ( cbuf, 0x01 );
2656 // sahf
2657 emit_opcode( cbuf, 0x9E);
2658 %}
2659
2660 enc_class cmpF_P6_fixup() %{
2661 // Fixup the integer flags in case comparison involved a NaN
2662 //
2663 // JNP exit (no unordered comparison, P-flag is set by NaN)
2664 emit_opcode( cbuf, 0x7B );
2665 emit_d8 ( cbuf, 0x03 );
2666 // MOV AH,1 - treat as LT case (set carry flag)
2667 emit_opcode( cbuf, 0xB4 );
2668 emit_d8 ( cbuf, 0x01 );
2669 // SAHF
2670 emit_opcode( cbuf, 0x9E);
2671 // NOP // target for branch to avoid branch to branch
2672 emit_opcode( cbuf, 0x90);
2673 %}
2674
2675 // fnstsw_ax();
2676 // sahf();
2677 // movl(dst, nan_result);
2678 // jcc(Assembler::parity, exit);
2679 // movl(dst, less_result);
2680 // jcc(Assembler::below, exit);
2681 // movl(dst, equal_result);
2682 // jcc(Assembler::equal, exit);
2683 // movl(dst, greater_result);
2684
2685 // less_result = 1;
2686 // greater_result = -1;
2687 // equal_result = 0;
2688 // nan_result = -1;
2689
2690 enc_class CmpF_Result(rRegI dst) %{
2691 // fnstsw_ax();
2692 emit_opcode( cbuf, 0xDF);
2693 emit_opcode( cbuf, 0xE0);
2694 // sahf
2695 emit_opcode( cbuf, 0x9E);
2696 // movl(dst, nan_result);
2697 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2698 emit_d32( cbuf, -1 );
2699 // jcc(Assembler::parity, exit);
2700 emit_opcode( cbuf, 0x7A );
2701 emit_d8 ( cbuf, 0x13 );
2702 // movl(dst, less_result);
2703 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2704 emit_d32( cbuf, -1 );
2705 // jcc(Assembler::below, exit);
2706 emit_opcode( cbuf, 0x72 );
2707 emit_d8 ( cbuf, 0x0C );
2708 // movl(dst, equal_result);
2709 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2710 emit_d32( cbuf, 0 );
2711 // jcc(Assembler::equal, exit);
2712 emit_opcode( cbuf, 0x74 );
2713 emit_d8 ( cbuf, 0x05 );
2714 // movl(dst, greater_result);
2715 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2716 emit_d32( cbuf, 1 );
2717 %}
2718
2719
2720 // Compare the longs and set flags
2721 // BROKEN! Do Not use as-is
2722 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2723 // CMP $src1.hi,$src2.hi
2724 emit_opcode( cbuf, 0x3B );
2725 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2726 // JNE,s done
2727 emit_opcode(cbuf,0x75);
2728 emit_d8(cbuf, 2 );
2729 // CMP $src1.lo,$src2.lo
2730 emit_opcode( cbuf, 0x3B );
2731 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2732 // done:
2733 %}
2734
2735 enc_class convert_int_long( regL dst, rRegI src ) %{
2736 // mov $dst.lo,$src
2737 int dst_encoding = $dst$$reg;
2738 int src_encoding = $src$$reg;
2739 encode_Copy( cbuf, dst_encoding , src_encoding );
2740 // mov $dst.hi,$src
2741 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2742 // sar $dst.hi,31
2743 emit_opcode( cbuf, 0xC1 );
2744 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2745 emit_d8(cbuf, 0x1F );
2746 %}
2747
2748 enc_class convert_long_double( eRegL src ) %{
2749 // push $src.hi
2750 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2751 // push $src.lo
2752 emit_opcode(cbuf, 0x50+$src$$reg );
2753 // fild 64-bits at [SP]
2754 emit_opcode(cbuf,0xdf);
2755 emit_d8(cbuf, 0x6C);
2756 emit_d8(cbuf, 0x24);
2757 emit_d8(cbuf, 0x00);
2758 // pop stack
2759 emit_opcode(cbuf, 0x83); // add SP, #8
2760 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2761 emit_d8(cbuf, 0x8);
2762 %}
2763
2764 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2765 // IMUL EDX:EAX,$src1
2766 emit_opcode( cbuf, 0xF7 );
2767 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2768 // SAR EDX,$cnt-32
2769 int shift_count = ((int)$cnt$$constant) - 32;
2770 if (shift_count > 0) {
2771 emit_opcode(cbuf, 0xC1);
2772 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2773 emit_d8(cbuf, shift_count);
2774 }
2775 %}
2776
2777 // this version doesn't have add sp, 8
2778 enc_class convert_long_double2( eRegL src ) %{
2779 // push $src.hi
2780 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2781 // push $src.lo
2782 emit_opcode(cbuf, 0x50+$src$$reg );
2783 // fild 64-bits at [SP]
2784 emit_opcode(cbuf,0xdf);
2785 emit_d8(cbuf, 0x6C);
2786 emit_d8(cbuf, 0x24);
2787 emit_d8(cbuf, 0x00);
2788 %}
2789
2790 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2791 // Basic idea: long = (long)int * (long)int
2792 // IMUL EDX:EAX, src
2793 emit_opcode( cbuf, 0xF7 );
2794 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2795 %}
2796
2797 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2798 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2799 // MUL EDX:EAX, src
2800 emit_opcode( cbuf, 0xF7 );
2801 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2802 %}
2803
2804 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2805 // Basic idea: lo(result) = lo(x_lo * y_lo)
2806 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2807 // MOV $tmp,$src.lo
2808 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2809 // IMUL $tmp,EDX
2810 emit_opcode( cbuf, 0x0F );
2811 emit_opcode( cbuf, 0xAF );
2812 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2813 // MOV EDX,$src.hi
2814 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2815 // IMUL EDX,EAX
2816 emit_opcode( cbuf, 0x0F );
2817 emit_opcode( cbuf, 0xAF );
2818 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2819 // ADD $tmp,EDX
2820 emit_opcode( cbuf, 0x03 );
2821 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2822 // MUL EDX:EAX,$src.lo
2823 emit_opcode( cbuf, 0xF7 );
2824 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2825 // ADD EDX,ESI
2826 emit_opcode( cbuf, 0x03 );
2827 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2828 %}
2829
2830 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2831 // Basic idea: lo(result) = lo(src * y_lo)
2832 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2833 // IMUL $tmp,EDX,$src
2834 emit_opcode( cbuf, 0x6B );
2835 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2836 emit_d8( cbuf, (int)$src$$constant );
2837 // MOV EDX,$src
2838 emit_opcode(cbuf, 0xB8 + EDX_enc);
2839 emit_d32( cbuf, (int)$src$$constant );
2840 // MUL EDX:EAX,EDX
2841 emit_opcode( cbuf, 0xF7 );
2842 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2843 // ADD EDX,ESI
2844 emit_opcode( cbuf, 0x03 );
2845 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2846 %}
2847
2848 enc_class long_div( eRegL src1, eRegL src2 ) %{
2849 // PUSH src1.hi
2850 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2851 // PUSH src1.lo
2852 emit_opcode(cbuf, 0x50+$src1$$reg );
2853 // PUSH src2.hi
2854 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2855 // PUSH src2.lo
2856 emit_opcode(cbuf, 0x50+$src2$$reg );
2857 // CALL directly to the runtime
2858 cbuf.set_insts_mark();
2859 emit_opcode(cbuf,0xE8); // Call into runtime
2860 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2861 // Restore stack
2862 emit_opcode(cbuf, 0x83); // add SP, #framesize
2863 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2864 emit_d8(cbuf, 4*4);
2865 %}
2866
2867 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2868 // PUSH src1.hi
2869 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2870 // PUSH src1.lo
2871 emit_opcode(cbuf, 0x50+$src1$$reg );
2872 // PUSH src2.hi
2873 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2874 // PUSH src2.lo
2875 emit_opcode(cbuf, 0x50+$src2$$reg );
2876 // CALL directly to the runtime
2877 cbuf.set_insts_mark();
2878 emit_opcode(cbuf,0xE8); // Call into runtime
2879 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2880 // Restore stack
2881 emit_opcode(cbuf, 0x83); // add SP, #framesize
2882 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2883 emit_d8(cbuf, 4*4);
2884 %}
2885
2886 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2887 // MOV $tmp,$src.lo
2888 emit_opcode(cbuf, 0x8B);
2889 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2890 // OR $tmp,$src.hi
2891 emit_opcode(cbuf, 0x0B);
2892 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2893 %}
2894
2895 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2896 // CMP $src1.lo,$src2.lo
2897 emit_opcode( cbuf, 0x3B );
2898 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2899 // JNE,s skip
2900 emit_cc(cbuf, 0x70, 0x5);
2901 emit_d8(cbuf,2);
2902 // CMP $src1.hi,$src2.hi
2903 emit_opcode( cbuf, 0x3B );
2904 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2905 %}
2906
2907 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2908 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2909 emit_opcode( cbuf, 0x3B );
2910 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2911 // MOV $tmp,$src1.hi
2912 emit_opcode( cbuf, 0x8B );
2913 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2914 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2915 emit_opcode( cbuf, 0x1B );
2916 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2917 %}
2918
2919 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2920 // XOR $tmp,$tmp
2921 emit_opcode(cbuf,0x33); // XOR
2922 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2923 // CMP $tmp,$src.lo
2924 emit_opcode( cbuf, 0x3B );
2925 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2926 // SBB $tmp,$src.hi
2927 emit_opcode( cbuf, 0x1B );
2928 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2929 %}
2930
2931 // Sniff, sniff... smells like Gnu Superoptimizer
2932 enc_class neg_long( eRegL dst ) %{
2933 emit_opcode(cbuf,0xF7); // NEG hi
2934 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2935 emit_opcode(cbuf,0xF7); // NEG lo
2936 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2937 emit_opcode(cbuf,0x83); // SBB hi,0
2938 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2939 emit_d8 (cbuf,0 );
2940 %}
2941
2942
2943 // Because the transitions from emitted code to the runtime
2944 // monitorenter/exit helper stubs are so slow it's critical that
2945 // we inline both the stack-locking fast-path and the inflated fast path.
2946 //
2947 // See also: cmpFastLock and cmpFastUnlock.
2948 //
2949 // What follows is a specialized inline transliteration of the code
2950 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2951 // another option would be to emit TrySlowEnter and TrySlowExit methods
2952 // at startup-time. These methods would accept arguments as
2953 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2954 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2955 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2956 // In practice, however, the # of lock sites is bounded and is usually small.
2957 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2958 // if the processor uses simple bimodal branch predictors keyed by EIP
2959 // Since the helper routines would be called from multiple synchronization
2960 // sites.
2961 //
2962 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2963 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2964 // to those specialized methods. That'd give us a mostly platform-independent
2965 // implementation that the JITs could optimize and inline at their pleasure.
2966 // Done correctly, the only time we'd need to cross to native could would be
2967 // to park() or unpark() threads. We'd also need a few more unsafe operators
2968 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2969 // (b) explicit barriers or fence operations.
2970 //
2971 // TODO:
2972 //
2973 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2974 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2975 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2976 // the lock operators would typically be faster than reifying Self.
2977 //
2978 // * Ideally I'd define the primitives as:
2979 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2980 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2981 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2982 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2983 // Furthermore the register assignments are overconstrained, possibly resulting in
2984 // sub-optimal code near the synchronization site.
2985 //
2986 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2987 // Alternately, use a better sp-proximity test.
2988 //
2989 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2990 // Either one is sufficient to uniquely identify a thread.
2991 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2992 //
2993 // * Intrinsify notify() and notifyAll() for the common cases where the
2994 // object is locked by the calling thread but the waitlist is empty.
2995 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2996 //
2997 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2998 // But beware of excessive branch density on AMD Opterons.
2999 //
3000 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3001 // or failure of the fast-path. If the fast-path fails then we pass
3002 // control to the slow-path, typically in C. In Fast_Lock and
3003 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3004 // will emit a conditional branch immediately after the node.
3005 // So we have branches to branches and lots of ICC.ZF games.
3006 // Instead, it might be better to have C2 pass a "FailureLabel"
3007 // into Fast_Lock and Fast_Unlock. In the case of success, control
3008 // will drop through the node. ICC.ZF is undefined at exit.
3009 // In the case of failure, the node will branch directly to the
3010 // FailureLabel
3011
3012
3013 // obj: object to lock
3014 // box: on-stack box address (displaced header location) - KILLED
3015 // rax,: tmp -- KILLED
3016 // scr: tmp -- KILLED
3017 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3018
3019 Register objReg = as_Register($obj$$reg);
3020 Register boxReg = as_Register($box$$reg);
3021 Register tmpReg = as_Register($tmp$$reg);
3022 Register scrReg = as_Register($scr$$reg);
3023
3024 // Ensure the register assignents are disjoint
3025 guarantee (objReg != boxReg, "") ;
3026 guarantee (objReg != tmpReg, "") ;
3027 guarantee (objReg != scrReg, "") ;
3028 guarantee (boxReg != tmpReg, "") ;
3029 guarantee (boxReg != scrReg, "") ;
3030 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3031
3032 MacroAssembler masm(&cbuf);
3033
3034 if (_counters != NULL) {
3035 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3036 }
3037 if (EmitSync & 1) {
3038 // set box->dhw = unused_mark (3)
3039 // Force all sync thru slow-path: slow_enter() and slow_exit()
3040 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3041 masm.cmpptr (rsp, (int32_t)0) ;
3042 } else
3043 if (EmitSync & 2) {
3044 Label DONE_LABEL ;
3045 if (UseBiasedLocking) {
3046 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3047 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3048 }
3049
3050 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3051 masm.orptr (tmpReg, 0x1);
3052 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3053 if (os::is_MP()) { masm.lock(); }
3054 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3055 masm.jcc(Assembler::equal, DONE_LABEL);
3056 // Recursive locking
3057 masm.subptr(tmpReg, rsp);
3058 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3059 masm.movptr(Address(boxReg, 0), tmpReg);
3060 masm.bind(DONE_LABEL) ;
3061 } else {
3062 // Possible cases that we'll encounter in fast_lock
3063 // ------------------------------------------------
3064 // * Inflated
3065 // -- unlocked
3066 // -- Locked
3067 // = by self
3068 // = by other
3069 // * biased
3070 // -- by Self
3071 // -- by other
3072 // * neutral
3073 // * stack-locked
3074 // -- by self
3075 // = sp-proximity test hits
3076 // = sp-proximity test generates false-negative
3077 // -- by other
3078 //
3079
3080 Label IsInflated, DONE_LABEL, PopDone ;
3081
3082 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3083 // order to reduce the number of conditional branches in the most common cases.
3084 // Beware -- there's a subtle invariant that fetch of the markword
3085 // at [FETCH], below, will never observe a biased encoding (*101b).
3086 // If this invariant is not held we risk exclusion (safety) failure.
3087 if (UseBiasedLocking && !UseOptoBiasInlining) {
3088 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3089 }
3090
3091 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3092 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3093 masm.jccb (Assembler::notZero, IsInflated) ;
3094
3095 // Attempt stack-locking ...
3096 masm.orptr (tmpReg, 0x1);
3097 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3098 if (os::is_MP()) { masm.lock(); }
3099 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3100 if (_counters != NULL) {
3101 masm.cond_inc32(Assembler::equal,
3102 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3103 }
3104 masm.jccb (Assembler::equal, DONE_LABEL);
3105
3106 // Recursive locking
3107 masm.subptr(tmpReg, rsp);
3108 masm.andptr(tmpReg, 0xFFFFF003 );
3109 masm.movptr(Address(boxReg, 0), tmpReg);
3110 if (_counters != NULL) {
3111 masm.cond_inc32(Assembler::equal,
3112 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3113 }
3114 masm.jmp (DONE_LABEL) ;
3115
3116 masm.bind (IsInflated) ;
3117
3118 // The object is inflated.
3119 //
3120 // TODO-FIXME: eliminate the ugly use of manifest constants:
3121 // Use markOopDesc::monitor_value instead of "2".
3122 // use markOop::unused_mark() instead of "3".
3123 // The tmpReg value is an objectMonitor reference ORed with
3124 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3125 // objectmonitor pointer by masking off the "2" bit or we can just
3126 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3127 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3128 //
3129 // I use the latter as it avoids AGI stalls.
3130 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3131 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3132 //
3133 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3134
3135 // boxReg refers to the on-stack BasicLock in the current frame.
3136 // We'd like to write:
3137 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3138 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3139 // additional latency as we have another ST in the store buffer that must drain.
3140
3141 if (EmitSync & 8192) {
3142 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3143 masm.get_thread (scrReg) ;
3144 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3145 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3146 if (os::is_MP()) { masm.lock(); }
3147 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3148 } else
3149 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3150 masm.movptr(scrReg, boxReg) ;
3151 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3152
3153 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3154 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3155 // prefetchw [eax + Offset(_owner)-2]
3156 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3157 }
3158
3159 if ((EmitSync & 64) == 0) {
3160 // Optimistic form: consider XORL tmpReg,tmpReg
3161 masm.movptr(tmpReg, NULL_WORD) ;
3162 } else {
3163 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3164 // Test-And-CAS instead of CAS
3165 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3166 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3167 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3168 }
3169
3170 // Appears unlocked - try to swing _owner from null to non-null.
3171 // Ideally, I'd manifest "Self" with get_thread and then attempt
3172 // to CAS the register containing Self into m->Owner.
3173 // But we don't have enough registers, so instead we can either try to CAS
3174 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3175 // we later store "Self" into m->Owner. Transiently storing a stack address
3176 // (rsp or the address of the box) into m->owner is harmless.
3177 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3178 if (os::is_MP()) { masm.lock(); }
3179 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3180 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3181 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3182 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3183 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3184 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3185
3186 // If the CAS fails we can either retry or pass control to the slow-path.
3187 // We use the latter tactic.
3188 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3189 // If the CAS was successful ...
3190 // Self has acquired the lock
3191 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3192 // Intentional fall-through into DONE_LABEL ...
3193 } else {
3194 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3195 masm.movptr(boxReg, tmpReg) ;
3196
3197 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3198 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3199 // prefetchw [eax + Offset(_owner)-2]
3200 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3201 }
3202
3203 if ((EmitSync & 64) == 0) {
3204 // Optimistic form
3205 masm.xorptr (tmpReg, tmpReg) ;
3206 } else {
3207 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3208 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3209 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3210 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3211 }
3212
3213 // Appears unlocked - try to swing _owner from null to non-null.
3214 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3215 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3216 masm.get_thread (scrReg) ;
3217 if (os::is_MP()) { masm.lock(); }
3218 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3219
3220 // If the CAS fails we can either retry or pass control to the slow-path.
3221 // We use the latter tactic.
3222 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3223 // If the CAS was successful ...
3224 // Self has acquired the lock
3225 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3226 // Intentional fall-through into DONE_LABEL ...
3227 }
3228
3229 // DONE_LABEL is a hot target - we'd really like to place it at the
3230 // start of cache line by padding with NOPs.
3231 // See the AMD and Intel software optimization manuals for the
3232 // most efficient "long" NOP encodings.
3233 // Unfortunately none of our alignment mechanisms suffice.
3234 masm.bind(DONE_LABEL);
3235
3236 // Avoid branch-to-branch on AMD processors
3237 // This appears to be superstition.
3238 if (EmitSync & 32) masm.nop() ;
3239
3240
3241 // At DONE_LABEL the icc ZFlag is set as follows ...
3242 // Fast_Unlock uses the same protocol.
3243 // ZFlag == 1 -> Success
3244 // ZFlag == 0 -> Failure - force control through the slow-path
3245 }
3246 %}
3247
3248 // obj: object to unlock
3249 // box: box address (displaced header location), killed. Must be EAX.
3250 // rbx,: killed tmp; cannot be obj nor box.
3251 //
3252 // Some commentary on balanced locking:
3253 //
3254 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3255 // Methods that don't have provably balanced locking are forced to run in the
3256 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3257 // The interpreter provides two properties:
3258 // I1: At return-time the interpreter automatically and quietly unlocks any
3259 // objects acquired the current activation (frame). Recall that the
3260 // interpreter maintains an on-stack list of locks currently held by
3261 // a frame.
3262 // I2: If a method attempts to unlock an object that is not held by the
3263 // the frame the interpreter throws IMSX.
3264 //
3265 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3266 // B() doesn't have provably balanced locking so it runs in the interpreter.
3267 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3268 // is still locked by A().
3269 //
3270 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3271 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3272 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3273 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3274
3275 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3276
3277 Register objReg = as_Register($obj$$reg);
3278 Register boxReg = as_Register($box$$reg);
3279 Register tmpReg = as_Register($tmp$$reg);
3280
3281 guarantee (objReg != boxReg, "") ;
3282 guarantee (objReg != tmpReg, "") ;
3283 guarantee (boxReg != tmpReg, "") ;
3284 guarantee (boxReg == as_Register(EAX_enc), "") ;
3285 MacroAssembler masm(&cbuf);
3286
3287 if (EmitSync & 4) {
3288 // Disable - inhibit all inlining. Force control through the slow-path
3289 masm.cmpptr (rsp, 0) ;
3290 } else
3291 if (EmitSync & 8) {
3292 Label DONE_LABEL ;
3293 if (UseBiasedLocking) {
3294 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3295 }
3296 // classic stack-locking code ...
3297 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3298 masm.testptr(tmpReg, tmpReg) ;
3299 masm.jcc (Assembler::zero, DONE_LABEL) ;
3300 if (os::is_MP()) { masm.lock(); }
3301 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3302 masm.bind(DONE_LABEL);
3303 } else {
3304 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3305
3306 // Critically, the biased locking test must have precedence over
3307 // and appear before the (box->dhw == 0) recursive stack-lock test.
3308 if (UseBiasedLocking && !UseOptoBiasInlining) {
3309 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3310 }
3311
3312 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3313 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3314 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3315
3316 masm.testptr(tmpReg, 0x02) ; // Inflated?
3317 masm.jccb (Assembler::zero, Stacked) ;
3318
3319 masm.bind (Inflated) ;
3320 // It's inflated.
3321 // Despite our balanced locking property we still check that m->_owner == Self
3322 // as java routines or native JNI code called by this thread might
3323 // have released the lock.
3324 // Refer to the comments in synchronizer.cpp for how we might encode extra
3325 // state in _succ so we can avoid fetching EntryList|cxq.
3326 //
3327 // I'd like to add more cases in fast_lock() and fast_unlock() --
3328 // such as recursive enter and exit -- but we have to be wary of
3329 // I$ bloat, T$ effects and BP$ effects.
3330 //
3331 // If there's no contention try a 1-0 exit. That is, exit without
3332 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3333 // we detect and recover from the race that the 1-0 exit admits.
3334 //
3335 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3336 // before it STs null into _owner, releasing the lock. Updates
3337 // to data protected by the critical section must be visible before
3338 // we drop the lock (and thus before any other thread could acquire
3339 // the lock and observe the fields protected by the lock).
3340 // IA32's memory-model is SPO, so STs are ordered with respect to
3341 // each other and there's no need for an explicit barrier (fence).
3342 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3343
3344 masm.get_thread (boxReg) ;
3345 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3346 // prefetchw [ebx + Offset(_owner)-2]
3347 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3348 }
3349
3350 // Note that we could employ various encoding schemes to reduce
3351 // the number of loads below (currently 4) to just 2 or 3.
3352 // Refer to the comments in synchronizer.cpp.
3353 // In practice the chain of fetches doesn't seem to impact performance, however.
3354 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3355 // Attempt to reduce branch density - AMD's branch predictor.
3356 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3357 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3358 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3359 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3360 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3361 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3362 masm.jmpb (DONE_LABEL) ;
3363 } else {
3364 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3365 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3366 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3367 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3368 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3369 masm.jccb (Assembler::notZero, CheckSucc) ;
3370 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3371 masm.jmpb (DONE_LABEL) ;
3372 }
3373
3374 // The Following code fragment (EmitSync & 65536) improves the performance of
3375 // contended applications and contended synchronization microbenchmarks.
3376 // Unfortunately the emission of the code - even though not executed - causes regressions
3377 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3378 // with an equal number of never-executed NOPs results in the same regression.
3379 // We leave it off by default.
3380
3381 if ((EmitSync & 65536) != 0) {
3382 Label LSuccess, LGoSlowPath ;
3383
3384 masm.bind (CheckSucc) ;
3385
3386 // Optional pre-test ... it's safe to elide this
3387 if ((EmitSync & 16) == 0) {
3388 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3389 masm.jccb (Assembler::zero, LGoSlowPath) ;
3390 }
3391
3392 // We have a classic Dekker-style idiom:
3393 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3394 // There are a number of ways to implement the barrier:
3395 // (1) lock:andl &m->_owner, 0
3396 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3397 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3398 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3399 // (2) If supported, an explicit MFENCE is appealing.
3400 // In older IA32 processors MFENCE is slower than lock:add or xchg
3401 // particularly if the write-buffer is full as might be the case if
3402 // if stores closely precede the fence or fence-equivalent instruction.
3403 // In more modern implementations MFENCE appears faster, however.
3404 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3405 // The $lines underlying the top-of-stack should be in M-state.
3406 // The locked add instruction is serializing, of course.
3407 // (4) Use xchg, which is serializing
3408 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3409 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3410 // The integer condition codes will tell us if succ was 0.
3411 // Since _succ and _owner should reside in the same $line and
3412 // we just stored into _owner, it's likely that the $line
3413 // remains in M-state for the lock:orl.
3414 //
3415 // We currently use (3), although it's likely that switching to (2)
3416 // is correct for the future.
3417
3418 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3419 if (os::is_MP()) {
3420 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3421 masm.mfence();
3422 } else {
3423 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3424 }
3425 }
3426 // Ratify _succ remains non-null
3427 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3428 masm.jccb (Assembler::notZero, LSuccess) ;
3429
3430 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3431 if (os::is_MP()) { masm.lock(); }
3432 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3433 masm.jccb (Assembler::notEqual, LSuccess) ;
3434 // Since we're low on registers we installed rsp as a placeholding in _owner.
3435 // Now install Self over rsp. This is safe as we're transitioning from
3436 // non-null to non=null
3437 masm.get_thread (boxReg) ;
3438 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3439 // Intentional fall-through into LGoSlowPath ...
3440
3441 masm.bind (LGoSlowPath) ;
3442 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3443 masm.jmpb (DONE_LABEL) ;
3444
3445 masm.bind (LSuccess) ;
3446 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3447 masm.jmpb (DONE_LABEL) ;
3448 }
3449
3450 masm.bind (Stacked) ;
3451 // It's not inflated and it's not recursively stack-locked and it's not biased.
3452 // It must be stack-locked.
3453 // Try to reset the header to displaced header.
3454 // The "box" value on the stack is stable, so we can reload
3455 // and be assured we observe the same value as above.
3456 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3457 if (os::is_MP()) { masm.lock(); }
3458 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3459 // Intention fall-thru into DONE_LABEL
3460
3461
3462 // DONE_LABEL is a hot target - we'd really like to place it at the
3463 // start of cache line by padding with NOPs.
3464 // See the AMD and Intel software optimization manuals for the
3465 // most efficient "long" NOP encodings.
3466 // Unfortunately none of our alignment mechanisms suffice.
3467 if ((EmitSync & 65536) == 0) {
3468 masm.bind (CheckSucc) ;
3469 }
3470 masm.bind(DONE_LABEL);
3471
3472 // Avoid branch to branch on AMD processors
3473 if (EmitSync & 32768) { masm.nop() ; }
3474 }
3475 %}
3476
3477
3478 enc_class enc_pop_rdx() %{
3479 emit_opcode(cbuf,0x5A);
3480 %}
3481
3482 enc_class enc_rethrow() %{
3483 cbuf.set_insts_mark();
3484 emit_opcode(cbuf, 0xE9); // jmp entry
3485 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3486 runtime_call_Relocation::spec(), RELOC_IMM32 );
3487 %}
3488
3489
3490 // Convert a double to an int. Java semantics require we do complex
3491 // manglelations in the corner cases. So we set the rounding mode to
3492 // 'zero', store the darned double down as an int, and reset the
3493 // rounding mode to 'nearest'. The hardware throws an exception which
3494 // patches up the correct value directly to the stack.
3495 enc_class DPR2I_encoding( regDPR src ) %{
3496 // Flip to round-to-zero mode. We attempted to allow invalid-op
3497 // exceptions here, so that a NAN or other corner-case value will
3498 // thrown an exception (but normal values get converted at full speed).
3499 // However, I2C adapters and other float-stack manglers leave pending
3500 // invalid-op exceptions hanging. We would have to clear them before
3501 // enabling them and that is more expensive than just testing for the
3502 // invalid value Intel stores down in the corner cases.
3503 emit_opcode(cbuf,0xD9); // FLDCW trunc
3504 emit_opcode(cbuf,0x2D);
3505 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3506 // Allocate a word
3507 emit_opcode(cbuf,0x83); // SUB ESP,4
3508 emit_opcode(cbuf,0xEC);
3509 emit_d8(cbuf,0x04);
3510 // Encoding assumes a double has been pushed into FPR0.
3511 // Store down the double as an int, popping the FPU stack
3512 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3513 emit_opcode(cbuf,0x1C);
3514 emit_d8(cbuf,0x24);
3515 // Restore the rounding mode; mask the exception
3516 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3517 emit_opcode(cbuf,0x2D);
3518 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3519 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3520 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3521
3522 // Load the converted int; adjust CPU stack
3523 emit_opcode(cbuf,0x58); // POP EAX
3524 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3525 emit_d32 (cbuf,0x80000000); // 0x80000000
3526 emit_opcode(cbuf,0x75); // JNE around_slow_call
3527 emit_d8 (cbuf,0x07); // Size of slow_call
3528 // Push src onto stack slow-path
3529 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3530 emit_d8 (cbuf,0xC0-1+$src$$reg );
3531 // CALL directly to the runtime
3532 cbuf.set_insts_mark();
3533 emit_opcode(cbuf,0xE8); // Call into runtime
3534 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3535 // Carry on here...
3536 %}
3537
3538 enc_class DPR2L_encoding( regDPR src ) %{
3539 emit_opcode(cbuf,0xD9); // FLDCW trunc
3540 emit_opcode(cbuf,0x2D);
3541 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3542 // Allocate a word
3543 emit_opcode(cbuf,0x83); // SUB ESP,8
3544 emit_opcode(cbuf,0xEC);
3545 emit_d8(cbuf,0x08);
3546 // Encoding assumes a double has been pushed into FPR0.
3547 // Store down the double as a long, popping the FPU stack
3548 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3549 emit_opcode(cbuf,0x3C);
3550 emit_d8(cbuf,0x24);
3551 // Restore the rounding mode; mask the exception
3552 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3553 emit_opcode(cbuf,0x2D);
3554 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3555 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3556 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3557
3558 // Load the converted int; adjust CPU stack
3559 emit_opcode(cbuf,0x58); // POP EAX
3560 emit_opcode(cbuf,0x5A); // POP EDX
3561 emit_opcode(cbuf,0x81); // CMP EDX,imm
3562 emit_d8 (cbuf,0xFA); // rdx
3563 emit_d32 (cbuf,0x80000000); // 0x80000000
3564 emit_opcode(cbuf,0x75); // JNE around_slow_call
3565 emit_d8 (cbuf,0x07+4); // Size of slow_call
3566 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3567 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3568 emit_opcode(cbuf,0x75); // JNE around_slow_call
3569 emit_d8 (cbuf,0x07); // Size of slow_call
3570 // Push src onto stack slow-path
3571 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3572 emit_d8 (cbuf,0xC0-1+$src$$reg );
3573 // CALL directly to the runtime
3574 cbuf.set_insts_mark();
3575 emit_opcode(cbuf,0xE8); // Call into runtime
3576 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3577 // Carry on here...
3578 %}
3579
3580 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3581 // Operand was loaded from memory into fp ST (stack top)
3582 // FMUL ST,$src /* D8 C8+i */
3583 emit_opcode(cbuf, 0xD8);
3584 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3585 %}
3586
3587 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3588 // FADDP ST,src2 /* D8 C0+i */
3589 emit_opcode(cbuf, 0xD8);
3590 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3591 //could use FADDP src2,fpST /* DE C0+i */
3592 %}
3593
3594 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3595 // FADDP src2,ST /* DE C0+i */
3596 emit_opcode(cbuf, 0xDE);
3597 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3598 %}
3599
3600 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3601 // Operand has been loaded into fp ST (stack top)
3602 // FSUB ST,$src1
3603 emit_opcode(cbuf, 0xD8);
3604 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3605
3606 // FDIV
3607 emit_opcode(cbuf, 0xD8);
3608 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3609 %}
3610
3611 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3612 // Operand was loaded from memory into fp ST (stack top)
3613 // FADD ST,$src /* D8 C0+i */
3614 emit_opcode(cbuf, 0xD8);
3615 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3616
3617 // FMUL ST,src2 /* D8 C*+i */
3618 emit_opcode(cbuf, 0xD8);
3619 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3620 %}
3621
3622
3623 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3624 // Operand was loaded from memory into fp ST (stack top)
3625 // FADD ST,$src /* D8 C0+i */
3626 emit_opcode(cbuf, 0xD8);
3627 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3628
3629 // FMULP src2,ST /* DE C8+i */
3630 emit_opcode(cbuf, 0xDE);
3631 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3632 %}
3633
3634 // Atomically load the volatile long
3635 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3636 emit_opcode(cbuf,0xDF);
3637 int rm_byte_opcode = 0x05;
3638 int base = $mem$$base;
3639 int index = $mem$$index;
3640 int scale = $mem$$scale;
3641 int displace = $mem$$disp;
3642 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3643 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3644 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3645 %}
3646
3647 // Volatile Store Long. Must be atomic, so move it into
3648 // the FP TOS and then do a 64-bit FIST. Has to probe the
3649 // target address before the store (for null-ptr checks)
3650 // so the memory operand is used twice in the encoding.
3651 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3652 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3653 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3654 emit_opcode(cbuf,0xDF);
3655 int rm_byte_opcode = 0x07;
3656 int base = $mem$$base;
3657 int index = $mem$$index;
3658 int scale = $mem$$scale;
3659 int displace = $mem$$disp;
3660 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3661 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3662 %}
3663
3664 // Safepoint Poll. This polls the safepoint page, and causes an
3665 // exception if it is not readable. Unfortunately, it kills the condition code
3666 // in the process
3667 // We current use TESTL [spp],EDI
3668 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3669
3670 enc_class Safepoint_Poll() %{
3671 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3672 emit_opcode(cbuf,0x85);
3673 emit_rm (cbuf, 0x0, 0x7, 0x5);
3674 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3675 %}
3676 %}
3677
3678
3679 //----------FRAME--------------------------------------------------------------
3680 // Definition of frame structure and management information.
3681 //
3682 // S T A C K L A Y O U T Allocators stack-slot number
3683 // | (to get allocators register number
3684 // G Owned by | | v add OptoReg::stack0())
3685 // r CALLER | |
3686 // o | +--------+ pad to even-align allocators stack-slot
3687 // w V | pad0 | numbers; owned by CALLER
3688 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3689 // h ^ | in | 5
3690 // | | args | 4 Holes in incoming args owned by SELF
3691 // | | | | 3
3692 // | | +--------+
3693 // V | | old out| Empty on Intel, window on Sparc
3694 // | old |preserve| Must be even aligned.
3695 // | SP-+--------+----> Matcher::_old_SP, even aligned
3696 // | | in | 3 area for Intel ret address
3697 // Owned by |preserve| Empty on Sparc.
3698 // SELF +--------+
3699 // | | pad2 | 2 pad to align old SP
3700 // | +--------+ 1
3701 // | | locks | 0
3702 // | +--------+----> OptoReg::stack0(), even aligned
3703 // | | pad1 | 11 pad to align new SP
3704 // | +--------+
3705 // | | | 10
3706 // | | spills | 9 spills
3707 // V | | 8 (pad0 slot for callee)
3708 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3709 // ^ | out | 7
3710 // | | args | 6 Holes in outgoing args owned by CALLEE
3711 // Owned by +--------+
3712 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3713 // | new |preserve| Must be even-aligned.
3714 // | SP-+--------+----> Matcher::_new_SP, even aligned
3715 // | | |
3716 //
3717 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3718 // known from SELF's arguments and the Java calling convention.
3719 // Region 6-7 is determined per call site.
3720 // Note 2: If the calling convention leaves holes in the incoming argument
3721 // area, those holes are owned by SELF. Holes in the outgoing area
3722 // are owned by the CALLEE. Holes should not be nessecary in the
3723 // incoming area, as the Java calling convention is completely under
3724 // the control of the AD file. Doubles can be sorted and packed to
3725 // avoid holes. Holes in the outgoing arguments may be nessecary for
3726 // varargs C calling conventions.
3727 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3728 // even aligned with pad0 as needed.
3729 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3730 // region 6-11 is even aligned; it may be padded out more so that
3731 // the region from SP to FP meets the minimum stack alignment.
3732
3733 frame %{
3734 // What direction does stack grow in (assumed to be same for C & Java)
3735 stack_direction(TOWARDS_LOW);
3736
3737 // These three registers define part of the calling convention
3738 // between compiled code and the interpreter.
3739 inline_cache_reg(EAX); // Inline Cache Register
3740 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3741
3742 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3743 cisc_spilling_operand_name(indOffset32);
3744
3745 // Number of stack slots consumed by locking an object
3746 sync_stack_slots(1);
3747
3748 // Compiled code's Frame Pointer
3749 frame_pointer(ESP);
3750 // Interpreter stores its frame pointer in a register which is
3751 // stored to the stack by I2CAdaptors.
3752 // I2CAdaptors convert from interpreted java to compiled java.
3753 interpreter_frame_pointer(EBP);
3754
3755 // Stack alignment requirement
3756 // Alignment size in bytes (128-bit -> 16 bytes)
3757 stack_alignment(StackAlignmentInBytes);
3758
3759 // Number of stack slots between incoming argument block and the start of
3760 // a new frame. The PROLOG must add this many slots to the stack. The
3761 // EPILOG must remove this many slots. Intel needs one slot for
3762 // return address and one for rbp, (must save rbp)
3763 in_preserve_stack_slots(2+VerifyStackAtCalls);
3764
3765 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3766 // for calls to C. Supports the var-args backing area for register parms.
3767 varargs_C_out_slots_killed(0);
3768
3769 // The after-PROLOG location of the return address. Location of
3770 // return address specifies a type (REG or STACK) and a number
3771 // representing the register number (i.e. - use a register name) or
3772 // stack slot.
3773 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3774 // Otherwise, it is above the locks and verification slot and alignment word
3775 return_addr(STACK - 1 +
3776 round_to((Compile::current()->in_preserve_stack_slots() +
3777 Compile::current()->fixed_slots()),
3778 stack_alignment_in_slots()));
3779
3780 // Body of function which returns an integer array locating
3781 // arguments either in registers or in stack slots. Passed an array
3782 // of ideal registers called "sig" and a "length" count. Stack-slot
3783 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3784 // arguments for a CALLEE. Incoming stack arguments are
3785 // automatically biased by the preserve_stack_slots field above.
3786 calling_convention %{
3787 // No difference between ingoing/outgoing just pass false
3788 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3789 %}
3790
3791
3792 // Body of function which returns an integer array locating
3793 // arguments either in registers or in stack slots. Passed an array
3794 // of ideal registers called "sig" and a "length" count. Stack-slot
3795 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3796 // arguments for a CALLEE. Incoming stack arguments are
3797 // automatically biased by the preserve_stack_slots field above.
3798 c_calling_convention %{
3799 // This is obviously always outgoing
3800 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3801 %}
3802
3803 // Location of C & interpreter return values
3804 c_return_value %{
3805 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3806 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3807 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3808
3809 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3810 // that C functions return float and double results in XMM0.
3811 if( ideal_reg == Op_RegD && UseSSE>=2 )
3812 return OptoRegPair(XMM0b_num,XMM0_num);
3813 if( ideal_reg == Op_RegF && UseSSE>=2 )
3814 return OptoRegPair(OptoReg::Bad,XMM0_num);
3815
3816 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3817 %}
3818
3819 // Location of return values
3820 return_value %{
3821 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3822 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3823 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3824 if( ideal_reg == Op_RegD && UseSSE>=2 )
3825 return OptoRegPair(XMM0b_num,XMM0_num);
3826 if( ideal_reg == Op_RegF && UseSSE>=1 )
3827 return OptoRegPair(OptoReg::Bad,XMM0_num);
3828 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3829 %}
3830
3831 %}
3832
3833 //----------ATTRIBUTES---------------------------------------------------------
3834 //----------Operand Attributes-------------------------------------------------
3835 op_attrib op_cost(0); // Required cost attribute
3836
3837 //----------Instruction Attributes---------------------------------------------
3838 ins_attrib ins_cost(100); // Required cost attribute
3839 ins_attrib ins_size(8); // Required size attribute (in bits)
3840 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3841 // non-matching short branch variant of some
3842 // long branch?
3843 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3844 // specifies the alignment that some part of the instruction (not
3845 // necessarily the start) requires. If > 1, a compute_padding()
3846 // function must be provided for the instruction
3847
3848 //----------OPERANDS-----------------------------------------------------------
3849 // Operand definitions must precede instruction definitions for correct parsing
3850 // in the ADLC because operands constitute user defined types which are used in
3851 // instruction definitions.
3852
3853 //----------Simple Operands----------------------------------------------------
3854 // Immediate Operands
3855 // Integer Immediate
3856 operand immI() %{
3857 match(ConI);
3858
3859 op_cost(10);
3860 format %{ %}
3861 interface(CONST_INTER);
3862 %}
3863
3864 // Constant for test vs zero
3865 operand immI0() %{
3866 predicate(n->get_int() == 0);
3867 match(ConI);
3868
3869 op_cost(0);
3870 format %{ %}
3871 interface(CONST_INTER);
3872 %}
3873
3874 // Constant for increment
3875 operand immI1() %{
3876 predicate(n->get_int() == 1);
3877 match(ConI);
3878
3879 op_cost(0);
3880 format %{ %}
3881 interface(CONST_INTER);
3882 %}
3883
3884 // Constant for decrement
3885 operand immI_M1() %{
3886 predicate(n->get_int() == -1);
3887 match(ConI);
3888
3889 op_cost(0);
3890 format %{ %}
3891 interface(CONST_INTER);
3892 %}
3893
3894 // Valid scale values for addressing modes
3895 operand immI2() %{
3896 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3897 match(ConI);
3898
3899 format %{ %}
3900 interface(CONST_INTER);
3901 %}
3902
3903 operand immI8() %{
3904 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3905 match(ConI);
3906
3907 op_cost(5);
3908 format %{ %}
3909 interface(CONST_INTER);
3910 %}
3911
3912 operand immI16() %{
3913 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3914 match(ConI);
3915
3916 op_cost(10);
3917 format %{ %}
3918 interface(CONST_INTER);
3919 %}
3920
3921 // Constant for long shifts
3922 operand immI_32() %{
3923 predicate( n->get_int() == 32 );
3924 match(ConI);
3925
3926 op_cost(0);
3927 format %{ %}
3928 interface(CONST_INTER);
3929 %}
3930
3931 operand immI_1_31() %{
3932 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3933 match(ConI);
3934
3935 op_cost(0);
3936 format %{ %}
3937 interface(CONST_INTER);
3938 %}
3939
3940 operand immI_32_63() %{
3941 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3942 match(ConI);
3943 op_cost(0);
3944
3945 format %{ %}
3946 interface(CONST_INTER);
3947 %}
3948
3949 operand immI_1() %{
3950 predicate( n->get_int() == 1 );
3951 match(ConI);
3952
3953 op_cost(0);
3954 format %{ %}
3955 interface(CONST_INTER);
3956 %}
3957
3958 operand immI_2() %{
3959 predicate( n->get_int() == 2 );
3960 match(ConI);
3961
3962 op_cost(0);
3963 format %{ %}
3964 interface(CONST_INTER);
3965 %}
3966
3967 operand immI_3() %{
3968 predicate( n->get_int() == 3 );
3969 match(ConI);
3970
3971 op_cost(0);
3972 format %{ %}
3973 interface(CONST_INTER);
3974 %}
3975
3976 // Pointer Immediate
3977 operand immP() %{
3978 match(ConP);
3979
3980 op_cost(10);
3981 format %{ %}
3982 interface(CONST_INTER);
3983 %}
3984
3985 // NULL Pointer Immediate
3986 operand immP0() %{
3987 predicate( n->get_ptr() == 0 );
3988 match(ConP);
3989 op_cost(0);
3990
3991 format %{ %}
3992 interface(CONST_INTER);
3993 %}
3994
3995 // Long Immediate
3996 operand immL() %{
3997 match(ConL);
3998
3999 op_cost(20);
4000 format %{ %}
4001 interface(CONST_INTER);
4002 %}
4003
4004 // Long Immediate zero
4005 operand immL0() %{
4006 predicate( n->get_long() == 0L );
4007 match(ConL);
4008 op_cost(0);
4009
4010 format %{ %}
4011 interface(CONST_INTER);
4012 %}
4013
4014 // Long Immediate zero
4015 operand immL_M1() %{
4016 predicate( n->get_long() == -1L );
4017 match(ConL);
4018 op_cost(0);
4019
4020 format %{ %}
4021 interface(CONST_INTER);
4022 %}
4023
4024 // Long immediate from 0 to 127.
4025 // Used for a shorter form of long mul by 10.
4026 operand immL_127() %{
4027 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4028 match(ConL);
4029 op_cost(0);
4030
4031 format %{ %}
4032 interface(CONST_INTER);
4033 %}
4034
4035 // Long Immediate: low 32-bit mask
4036 operand immL_32bits() %{
4037 predicate(n->get_long() == 0xFFFFFFFFL);
4038 match(ConL);
4039 op_cost(0);
4040
4041 format %{ %}
4042 interface(CONST_INTER);
4043 %}
4044
4045 // Long Immediate: low 32-bit mask
4046 operand immL32() %{
4047 predicate(n->get_long() == (int)(n->get_long()));
4048 match(ConL);
4049 op_cost(20);
4050
4051 format %{ %}
4052 interface(CONST_INTER);
4053 %}
4054
4055 //Double Immediate zero
4056 operand immDPR0() %{
4057 // Do additional (and counter-intuitive) test against NaN to work around VC++
4058 // bug that generates code such that NaNs compare equal to 0.0
4059 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4060 match(ConD);
4061
4062 op_cost(5);
4063 format %{ %}
4064 interface(CONST_INTER);
4065 %}
4066
4067 // Double Immediate one
4068 operand immDPR1() %{
4069 predicate( UseSSE<=1 && n->getd() == 1.0 );
4070 match(ConD);
4071
4072 op_cost(5);
4073 format %{ %}
4074 interface(CONST_INTER);
4075 %}
4076
4077 // Double Immediate
4078 operand immDPR() %{
4079 predicate(UseSSE<=1);
4080 match(ConD);
4081
4082 op_cost(5);
4083 format %{ %}
4084 interface(CONST_INTER);
4085 %}
4086
4087 operand immD() %{
4088 predicate(UseSSE>=2);
4089 match(ConD);
4090
4091 op_cost(5);
4092 format %{ %}
4093 interface(CONST_INTER);
4094 %}
4095
4096 // Double Immediate zero
4097 operand immD0() %{
4098 // Do additional (and counter-intuitive) test against NaN to work around VC++
4099 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4100 // compare equal to -0.0.
4101 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4102 match(ConD);
4103
4104 format %{ %}
4105 interface(CONST_INTER);
4106 %}
4107
4108 // Float Immediate zero
4109 operand immFPR0() %{
4110 predicate(UseSSE == 0 && n->getf() == 0.0F);
4111 match(ConF);
4112
4113 op_cost(5);
4114 format %{ %}
4115 interface(CONST_INTER);
4116 %}
4117
4118 // Float Immediate one
4119 operand immFPR1() %{
4120 predicate(UseSSE == 0 && n->getf() == 1.0F);
4121 match(ConF);
4122
4123 op_cost(5);
4124 format %{ %}
4125 interface(CONST_INTER);
4126 %}
4127
4128 // Float Immediate
4129 operand immFPR() %{
4130 predicate( UseSSE == 0 );
4131 match(ConF);
4132
4133 op_cost(5);
4134 format %{ %}
4135 interface(CONST_INTER);
4136 %}
4137
4138 // Float Immediate
4139 operand immF() %{
4140 predicate(UseSSE >= 1);
4141 match(ConF);
4142
4143 op_cost(5);
4144 format %{ %}
4145 interface(CONST_INTER);
4146 %}
4147
4148 // Float Immediate zero. Zero and not -0.0
4149 operand immF0() %{
4150 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4151 match(ConF);
4152
4153 op_cost(5);
4154 format %{ %}
4155 interface(CONST_INTER);
4156 %}
4157
4158 // Immediates for special shifts (sign extend)
4159
4160 // Constants for increment
4161 operand immI_16() %{
4162 predicate( n->get_int() == 16 );
4163 match(ConI);
4164
4165 format %{ %}
4166 interface(CONST_INTER);
4167 %}
4168
4169 operand immI_24() %{
4170 predicate( n->get_int() == 24 );
4171 match(ConI);
4172
4173 format %{ %}
4174 interface(CONST_INTER);
4175 %}
4176
4177 // Constant for byte-wide masking
4178 operand immI_255() %{
4179 predicate( n->get_int() == 255 );
4180 match(ConI);
4181
4182 format %{ %}
4183 interface(CONST_INTER);
4184 %}
4185
4186 // Constant for short-wide masking
4187 operand immI_65535() %{
4188 predicate(n->get_int() == 65535);
4189 match(ConI);
4190
4191 format %{ %}
4192 interface(CONST_INTER);
4193 %}
4194
4195 // Register Operands
4196 // Integer Register
4197 operand rRegI() %{
4198 constraint(ALLOC_IN_RC(int_reg));
4199 match(RegI);
4200 match(xRegI);
4201 match(eAXRegI);
4202 match(eBXRegI);
4203 match(eCXRegI);
4204 match(eDXRegI);
4205 match(eDIRegI);
4206 match(eSIRegI);
4207
4208 format %{ %}
4209 interface(REG_INTER);
4210 %}
4211
4212 // Subset of Integer Register
4213 operand xRegI(rRegI reg) %{
4214 constraint(ALLOC_IN_RC(int_x_reg));
4215 match(reg);
4216 match(eAXRegI);
4217 match(eBXRegI);
4218 match(eCXRegI);
4219 match(eDXRegI);
4220
4221 format %{ %}
4222 interface(REG_INTER);
4223 %}
4224
4225 // Special Registers
4226 operand eAXRegI(xRegI reg) %{
4227 constraint(ALLOC_IN_RC(eax_reg));
4228 match(reg);
4229 match(rRegI);
4230
4231 format %{ "EAX" %}
4232 interface(REG_INTER);
4233 %}
4234
4235 // Special Registers
4236 operand eBXRegI(xRegI reg) %{
4237 constraint(ALLOC_IN_RC(ebx_reg));
4238 match(reg);
4239 match(rRegI);
4240
4241 format %{ "EBX" %}
4242 interface(REG_INTER);
4243 %}
4244
4245 operand eCXRegI(xRegI reg) %{
4246 constraint(ALLOC_IN_RC(ecx_reg));
4247 match(reg);
4248 match(rRegI);
4249
4250 format %{ "ECX" %}
4251 interface(REG_INTER);
4252 %}
4253
4254 operand eDXRegI(xRegI reg) %{
4255 constraint(ALLOC_IN_RC(edx_reg));
4256 match(reg);
4257 match(rRegI);
4258
4259 format %{ "EDX" %}
4260 interface(REG_INTER);
4261 %}
4262
4263 operand eDIRegI(xRegI reg) %{
4264 constraint(ALLOC_IN_RC(edi_reg));
4265 match(reg);
4266 match(rRegI);
4267
4268 format %{ "EDI" %}
4269 interface(REG_INTER);
4270 %}
4271
4272 operand naxRegI() %{
4273 constraint(ALLOC_IN_RC(nax_reg));
4274 match(RegI);
4275 match(eCXRegI);
4276 match(eDXRegI);
4277 match(eSIRegI);
4278 match(eDIRegI);
4279
4280 format %{ %}
4281 interface(REG_INTER);
4282 %}
4283
4284 operand nadxRegI() %{
4285 constraint(ALLOC_IN_RC(nadx_reg));
4286 match(RegI);
4287 match(eBXRegI);
4288 match(eCXRegI);
4289 match(eSIRegI);
4290 match(eDIRegI);
4291
4292 format %{ %}
4293 interface(REG_INTER);
4294 %}
4295
4296 operand ncxRegI() %{
4297 constraint(ALLOC_IN_RC(ncx_reg));
4298 match(RegI);
4299 match(eAXRegI);
4300 match(eDXRegI);
4301 match(eSIRegI);
4302 match(eDIRegI);
4303
4304 format %{ %}
4305 interface(REG_INTER);
4306 %}
4307
4308 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4309 // //
4310 operand eSIRegI(xRegI reg) %{
4311 constraint(ALLOC_IN_RC(esi_reg));
4312 match(reg);
4313 match(rRegI);
4314
4315 format %{ "ESI" %}
4316 interface(REG_INTER);
4317 %}
4318
4319 // Pointer Register
4320 operand anyRegP() %{
4321 constraint(ALLOC_IN_RC(any_reg));
4322 match(RegP);
4323 match(eAXRegP);
4324 match(eBXRegP);
4325 match(eCXRegP);
4326 match(eDIRegP);
4327 match(eRegP);
4328
4329 format %{ %}
4330 interface(REG_INTER);
4331 %}
4332
4333 operand eRegP() %{
4334 constraint(ALLOC_IN_RC(int_reg));
4335 match(RegP);
4336 match(eAXRegP);
4337 match(eBXRegP);
4338 match(eCXRegP);
4339 match(eDIRegP);
4340
4341 format %{ %}
4342 interface(REG_INTER);
4343 %}
4344
4345 // On windows95, EBP is not safe to use for implicit null tests.
4346 operand eRegP_no_EBP() %{
4347 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4348 match(RegP);
4349 match(eAXRegP);
4350 match(eBXRegP);
4351 match(eCXRegP);
4352 match(eDIRegP);
4353
4354 op_cost(100);
4355 format %{ %}
4356 interface(REG_INTER);
4357 %}
4358
4359 operand naxRegP() %{
4360 constraint(ALLOC_IN_RC(nax_reg));
4361 match(RegP);
4362 match(eBXRegP);
4363 match(eDXRegP);
4364 match(eCXRegP);
4365 match(eSIRegP);
4366 match(eDIRegP);
4367
4368 format %{ %}
4369 interface(REG_INTER);
4370 %}
4371
4372 operand nabxRegP() %{
4373 constraint(ALLOC_IN_RC(nabx_reg));
4374 match(RegP);
4375 match(eCXRegP);
4376 match(eDXRegP);
4377 match(eSIRegP);
4378 match(eDIRegP);
4379
4380 format %{ %}
4381 interface(REG_INTER);
4382 %}
4383
4384 operand pRegP() %{
4385 constraint(ALLOC_IN_RC(p_reg));
4386 match(RegP);
4387 match(eBXRegP);
4388 match(eDXRegP);
4389 match(eSIRegP);
4390 match(eDIRegP);
4391
4392 format %{ %}
4393 interface(REG_INTER);
4394 %}
4395
4396 // Special Registers
4397 // Return a pointer value
4398 operand eAXRegP(eRegP reg) %{
4399 constraint(ALLOC_IN_RC(eax_reg));
4400 match(reg);
4401 format %{ "EAX" %}
4402 interface(REG_INTER);
4403 %}
4404
4405 // Used in AtomicAdd
4406 operand eBXRegP(eRegP reg) %{
4407 constraint(ALLOC_IN_RC(ebx_reg));
4408 match(reg);
4409 format %{ "EBX" %}
4410 interface(REG_INTER);
4411 %}
4412
4413 // Tail-call (interprocedural jump) to interpreter
4414 operand eCXRegP(eRegP reg) %{
4415 constraint(ALLOC_IN_RC(ecx_reg));
4416 match(reg);
4417 format %{ "ECX" %}
4418 interface(REG_INTER);
4419 %}
4420
4421 operand eSIRegP(eRegP reg) %{
4422 constraint(ALLOC_IN_RC(esi_reg));
4423 match(reg);
4424 format %{ "ESI" %}
4425 interface(REG_INTER);
4426 %}
4427
4428 // Used in rep stosw
4429 operand eDIRegP(eRegP reg) %{
4430 constraint(ALLOC_IN_RC(edi_reg));
4431 match(reg);
4432 format %{ "EDI" %}
4433 interface(REG_INTER);
4434 %}
4435
4436 operand eBPRegP() %{
4437 constraint(ALLOC_IN_RC(ebp_reg));
4438 match(RegP);
4439 format %{ "EBP" %}
4440 interface(REG_INTER);
4441 %}
4442
4443 operand eRegL() %{
4444 constraint(ALLOC_IN_RC(long_reg));
4445 match(RegL);
4446 match(eADXRegL);
4447
4448 format %{ %}
4449 interface(REG_INTER);
4450 %}
4451
4452 operand eADXRegL( eRegL reg ) %{
4453 constraint(ALLOC_IN_RC(eadx_reg));
4454 match(reg);
4455
4456 format %{ "EDX:EAX" %}
4457 interface(REG_INTER);
4458 %}
4459
4460 operand eBCXRegL( eRegL reg ) %{
4461 constraint(ALLOC_IN_RC(ebcx_reg));
4462 match(reg);
4463
4464 format %{ "EBX:ECX" %}
4465 interface(REG_INTER);
4466 %}
4467
4468 // Special case for integer high multiply
4469 operand eADXRegL_low_only() %{
4470 constraint(ALLOC_IN_RC(eadx_reg));
4471 match(RegL);
4472
4473 format %{ "EAX" %}
4474 interface(REG_INTER);
4475 %}
4476
4477 // Flags register, used as output of compare instructions
4478 operand eFlagsReg() %{
4479 constraint(ALLOC_IN_RC(int_flags));
4480 match(RegFlags);
4481
4482 format %{ "EFLAGS" %}
4483 interface(REG_INTER);
4484 %}
4485
4486 // Flags register, used as output of FLOATING POINT compare instructions
4487 operand eFlagsRegU() %{
4488 constraint(ALLOC_IN_RC(int_flags));
4489 match(RegFlags);
4490
4491 format %{ "EFLAGS_U" %}
4492 interface(REG_INTER);
4493 %}
4494
4495 operand eFlagsRegUCF() %{
4496 constraint(ALLOC_IN_RC(int_flags));
4497 match(RegFlags);
4498 predicate(false);
4499
4500 format %{ "EFLAGS_U_CF" %}
4501 interface(REG_INTER);
4502 %}
4503
4504 // Condition Code Register used by long compare
4505 operand flagsReg_long_LTGE() %{
4506 constraint(ALLOC_IN_RC(int_flags));
4507 match(RegFlags);
4508 format %{ "FLAGS_LTGE" %}
4509 interface(REG_INTER);
4510 %}
4511 operand flagsReg_long_EQNE() %{
4512 constraint(ALLOC_IN_RC(int_flags));
4513 match(RegFlags);
4514 format %{ "FLAGS_EQNE" %}
4515 interface(REG_INTER);
4516 %}
4517 operand flagsReg_long_LEGT() %{
4518 constraint(ALLOC_IN_RC(int_flags));
4519 match(RegFlags);
4520 format %{ "FLAGS_LEGT" %}
4521 interface(REG_INTER);
4522 %}
4523
4524 // Float register operands
4525 operand regDPR() %{
4526 predicate( UseSSE < 2 );
4527 constraint(ALLOC_IN_RC(fp_dbl_reg));
4528 match(RegD);
4529 match(regDPR1);
4530 match(regDPR2);
4531 format %{ %}
4532 interface(REG_INTER);
4533 %}
4534
4535 operand regDPR1(regDPR reg) %{
4536 predicate( UseSSE < 2 );
4537 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4538 match(reg);
4539 format %{ "FPR1" %}
4540 interface(REG_INTER);
4541 %}
4542
4543 operand regDPR2(regDPR reg) %{
4544 predicate( UseSSE < 2 );
4545 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4546 match(reg);
4547 format %{ "FPR2" %}
4548 interface(REG_INTER);
4549 %}
4550
4551 operand regnotDPR1(regDPR reg) %{
4552 predicate( UseSSE < 2 );
4553 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4554 match(reg);
4555 format %{ %}
4556 interface(REG_INTER);
4557 %}
4558
4559 // Float register operands
4560 operand regFPR() %{
4561 predicate( UseSSE < 2 );
4562 constraint(ALLOC_IN_RC(fp_flt_reg));
4563 match(RegF);
4564 match(regFPR1);
4565 format %{ %}
4566 interface(REG_INTER);
4567 %}
4568
4569 // Float register operands
4570 operand regFPR1(regFPR reg) %{
4571 predicate( UseSSE < 2 );
4572 constraint(ALLOC_IN_RC(fp_flt_reg0));
4573 match(reg);
4574 format %{ "FPR1" %}
4575 interface(REG_INTER);
4576 %}
4577
4578 // XMM Float register operands
4579 operand regF() %{
4580 predicate( UseSSE>=1 );
4581 constraint(ALLOC_IN_RC(float_reg));
4582 match(RegF);
4583 format %{ %}
4584 interface(REG_INTER);
4585 %}
4586
4587 // XMM Double register operands
4588 operand regD() %{
4589 predicate( UseSSE>=2 );
4590 constraint(ALLOC_IN_RC(double_reg));
4591 match(RegD);
4592 format %{ %}
4593 interface(REG_INTER);
4594 %}
4595
4596
4597 //----------Memory Operands----------------------------------------------------
4598 // Direct Memory Operand
4599 operand direct(immP addr) %{
4600 match(addr);
4601
4602 format %{ "[$addr]" %}
4603 interface(MEMORY_INTER) %{
4604 base(0xFFFFFFFF);
4605 index(0x4);
4606 scale(0x0);
4607 disp($addr);
4608 %}
4609 %}
4610
4611 // Indirect Memory Operand
4612 operand indirect(eRegP reg) %{
4613 constraint(ALLOC_IN_RC(int_reg));
4614 match(reg);
4615
4616 format %{ "[$reg]" %}
4617 interface(MEMORY_INTER) %{
4618 base($reg);
4619 index(0x4);
4620 scale(0x0);
4621 disp(0x0);
4622 %}
4623 %}
4624
4625 // Indirect Memory Plus Short Offset Operand
4626 operand indOffset8(eRegP reg, immI8 off) %{
4627 match(AddP reg off);
4628
4629 format %{ "[$reg + $off]" %}
4630 interface(MEMORY_INTER) %{
4631 base($reg);
4632 index(0x4);
4633 scale(0x0);
4634 disp($off);
4635 %}
4636 %}
4637
4638 // Indirect Memory Plus Long Offset Operand
4639 operand indOffset32(eRegP reg, immI off) %{
4640 match(AddP reg off);
4641
4642 format %{ "[$reg + $off]" %}
4643 interface(MEMORY_INTER) %{
4644 base($reg);
4645 index(0x4);
4646 scale(0x0);
4647 disp($off);
4648 %}
4649 %}
4650
4651 // Indirect Memory Plus Long Offset Operand
4652 operand indOffset32X(rRegI reg, immP off) %{
4653 match(AddP off reg);
4654
4655 format %{ "[$reg + $off]" %}
4656 interface(MEMORY_INTER) %{
4657 base($reg);
4658 index(0x4);
4659 scale(0x0);
4660 disp($off);
4661 %}
4662 %}
4663
4664 // Indirect Memory Plus Index Register Plus Offset Operand
4665 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4666 match(AddP (AddP reg ireg) off);
4667
4668 op_cost(10);
4669 format %{"[$reg + $off + $ireg]" %}
4670 interface(MEMORY_INTER) %{
4671 base($reg);
4672 index($ireg);
4673 scale(0x0);
4674 disp($off);
4675 %}
4676 %}
4677
4678 // Indirect Memory Plus Index Register Plus Offset Operand
4679 operand indIndex(eRegP reg, rRegI ireg) %{
4680 match(AddP reg ireg);
4681
4682 op_cost(10);
4683 format %{"[$reg + $ireg]" %}
4684 interface(MEMORY_INTER) %{
4685 base($reg);
4686 index($ireg);
4687 scale(0x0);
4688 disp(0x0);
4689 %}
4690 %}
4691
4692 // // -------------------------------------------------------------------------
4693 // // 486 architecture doesn't support "scale * index + offset" with out a base
4694 // // -------------------------------------------------------------------------
4695 // // Scaled Memory Operands
4696 // // Indirect Memory Times Scale Plus Offset Operand
4697 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4698 // match(AddP off (LShiftI ireg scale));
4699 //
4700 // op_cost(10);
4701 // format %{"[$off + $ireg << $scale]" %}
4702 // interface(MEMORY_INTER) %{
4703 // base(0x4);
4704 // index($ireg);
4705 // scale($scale);
4706 // disp($off);
4707 // %}
4708 // %}
4709
4710 // Indirect Memory Times Scale Plus Index Register
4711 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4712 match(AddP reg (LShiftI ireg scale));
4713
4714 op_cost(10);
4715 format %{"[$reg + $ireg << $scale]" %}
4716 interface(MEMORY_INTER) %{
4717 base($reg);
4718 index($ireg);
4719 scale($scale);
4720 disp(0x0);
4721 %}
4722 %}
4723
4724 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4725 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4726 match(AddP (AddP reg (LShiftI ireg scale)) off);
4727
4728 op_cost(10);
4729 format %{"[$reg + $off + $ireg << $scale]" %}
4730 interface(MEMORY_INTER) %{
4731 base($reg);
4732 index($ireg);
4733 scale($scale);
4734 disp($off);
4735 %}
4736 %}
4737
4738 //----------Load Long Memory Operands------------------------------------------
4739 // The load-long idiom will use it's address expression again after loading
4740 // the first word of the long. If the load-long destination overlaps with
4741 // registers used in the addressing expression, the 2nd half will be loaded
4742 // from a clobbered address. Fix this by requiring that load-long use
4743 // address registers that do not overlap with the load-long target.
4744
4745 // load-long support
4746 operand load_long_RegP() %{
4747 constraint(ALLOC_IN_RC(esi_reg));
4748 match(RegP);
4749 match(eSIRegP);
4750 op_cost(100);
4751 format %{ %}
4752 interface(REG_INTER);
4753 %}
4754
4755 // Indirect Memory Operand Long
4756 operand load_long_indirect(load_long_RegP reg) %{
4757 constraint(ALLOC_IN_RC(esi_reg));
4758 match(reg);
4759
4760 format %{ "[$reg]" %}
4761 interface(MEMORY_INTER) %{
4762 base($reg);
4763 index(0x4);
4764 scale(0x0);
4765 disp(0x0);
4766 %}
4767 %}
4768
4769 // Indirect Memory Plus Long Offset Operand
4770 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4771 match(AddP reg off);
4772
4773 format %{ "[$reg + $off]" %}
4774 interface(MEMORY_INTER) %{
4775 base($reg);
4776 index(0x4);
4777 scale(0x0);
4778 disp($off);
4779 %}
4780 %}
4781
4782 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4783
4784
4785 //----------Special Memory Operands--------------------------------------------
4786 // Stack Slot Operand - This operand is used for loading and storing temporary
4787 // values on the stack where a match requires a value to
4788 // flow through memory.
4789 operand stackSlotP(sRegP reg) %{
4790 constraint(ALLOC_IN_RC(stack_slots));
4791 // No match rule because this operand is only generated in matching
4792 format %{ "[$reg]" %}
4793 interface(MEMORY_INTER) %{
4794 base(0x4); // ESP
4795 index(0x4); // No Index
4796 scale(0x0); // No Scale
4797 disp($reg); // Stack Offset
4798 %}
4799 %}
4800
4801 operand stackSlotI(sRegI reg) %{
4802 constraint(ALLOC_IN_RC(stack_slots));
4803 // No match rule because this operand is only generated in matching
4804 format %{ "[$reg]" %}
4805 interface(MEMORY_INTER) %{
4806 base(0x4); // ESP
4807 index(0x4); // No Index
4808 scale(0x0); // No Scale
4809 disp($reg); // Stack Offset
4810 %}
4811 %}
4812
4813 operand stackSlotF(sRegF reg) %{
4814 constraint(ALLOC_IN_RC(stack_slots));
4815 // No match rule because this operand is only generated in matching
4816 format %{ "[$reg]" %}
4817 interface(MEMORY_INTER) %{
4818 base(0x4); // ESP
4819 index(0x4); // No Index
4820 scale(0x0); // No Scale
4821 disp($reg); // Stack Offset
4822 %}
4823 %}
4824
4825 operand stackSlotD(sRegD reg) %{
4826 constraint(ALLOC_IN_RC(stack_slots));
4827 // No match rule because this operand is only generated in matching
4828 format %{ "[$reg]" %}
4829 interface(MEMORY_INTER) %{
4830 base(0x4); // ESP
4831 index(0x4); // No Index
4832 scale(0x0); // No Scale
4833 disp($reg); // Stack Offset
4834 %}
4835 %}
4836
4837 operand stackSlotL(sRegL reg) %{
4838 constraint(ALLOC_IN_RC(stack_slots));
4839 // No match rule because this operand is only generated in matching
4840 format %{ "[$reg]" %}
4841 interface(MEMORY_INTER) %{
4842 base(0x4); // ESP
4843 index(0x4); // No Index
4844 scale(0x0); // No Scale
4845 disp($reg); // Stack Offset
4846 %}
4847 %}
4848
4849 //----------Memory Operands - Win95 Implicit Null Variants----------------
4850 // Indirect Memory Operand
4851 operand indirect_win95_safe(eRegP_no_EBP reg)
4852 %{
4853 constraint(ALLOC_IN_RC(int_reg));
4854 match(reg);
4855
4856 op_cost(100);
4857 format %{ "[$reg]" %}
4858 interface(MEMORY_INTER) %{
4859 base($reg);
4860 index(0x4);
4861 scale(0x0);
4862 disp(0x0);
4863 %}
4864 %}
4865
4866 // Indirect Memory Plus Short Offset Operand
4867 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4868 %{
4869 match(AddP reg off);
4870
4871 op_cost(100);
4872 format %{ "[$reg + $off]" %}
4873 interface(MEMORY_INTER) %{
4874 base($reg);
4875 index(0x4);
4876 scale(0x0);
4877 disp($off);
4878 %}
4879 %}
4880
4881 // Indirect Memory Plus Long Offset Operand
4882 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4883 %{
4884 match(AddP reg off);
4885
4886 op_cost(100);
4887 format %{ "[$reg + $off]" %}
4888 interface(MEMORY_INTER) %{
4889 base($reg);
4890 index(0x4);
4891 scale(0x0);
4892 disp($off);
4893 %}
4894 %}
4895
4896 // Indirect Memory Plus Index Register Plus Offset Operand
4897 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4898 %{
4899 match(AddP (AddP reg ireg) off);
4900
4901 op_cost(100);
4902 format %{"[$reg + $off + $ireg]" %}
4903 interface(MEMORY_INTER) %{
4904 base($reg);
4905 index($ireg);
4906 scale(0x0);
4907 disp($off);
4908 %}
4909 %}
4910
4911 // Indirect Memory Times Scale Plus Index Register
4912 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4913 %{
4914 match(AddP reg (LShiftI ireg scale));
4915
4916 op_cost(100);
4917 format %{"[$reg + $ireg << $scale]" %}
4918 interface(MEMORY_INTER) %{
4919 base($reg);
4920 index($ireg);
4921 scale($scale);
4922 disp(0x0);
4923 %}
4924 %}
4925
4926 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4927 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4928 %{
4929 match(AddP (AddP reg (LShiftI ireg scale)) off);
4930
4931 op_cost(100);
4932 format %{"[$reg + $off + $ireg << $scale]" %}
4933 interface(MEMORY_INTER) %{
4934 base($reg);
4935 index($ireg);
4936 scale($scale);
4937 disp($off);
4938 %}
4939 %}
4940
4941 //----------Conditional Branch Operands----------------------------------------
4942 // Comparison Op - This is the operation of the comparison, and is limited to
4943 // the following set of codes:
4944 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4945 //
4946 // Other attributes of the comparison, such as unsignedness, are specified
4947 // by the comparison instruction that sets a condition code flags register.
4948 // That result is represented by a flags operand whose subtype is appropriate
4949 // to the unsignedness (etc.) of the comparison.
4950 //
4951 // Later, the instruction which matches both the Comparison Op (a Bool) and
4952 // the flags (produced by the Cmp) specifies the coding of the comparison op
4953 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4954
4955 // Comparision Code
4956 operand cmpOp() %{
4957 match(Bool);
4958
4959 format %{ "" %}
4960 interface(COND_INTER) %{
4961 equal(0x4, "e");
4962 not_equal(0x5, "ne");
4963 less(0xC, "l");
4964 greater_equal(0xD, "ge");
4965 less_equal(0xE, "le");
4966 greater(0xF, "g");
4967 %}
4968 %}
4969
4970 // Comparison Code, unsigned compare. Used by FP also, with
4971 // C2 (unordered) turned into GT or LT already. The other bits
4972 // C0 and C3 are turned into Carry & Zero flags.
4973 operand cmpOpU() %{
4974 match(Bool);
4975
4976 format %{ "" %}
4977 interface(COND_INTER) %{
4978 equal(0x4, "e");
4979 not_equal(0x5, "ne");
4980 less(0x2, "b");
4981 greater_equal(0x3, "nb");
4982 less_equal(0x6, "be");
4983 greater(0x7, "nbe");
4984 %}
4985 %}
4986
4987 // Floating comparisons that don't require any fixup for the unordered case
4988 operand cmpOpUCF() %{
4989 match(Bool);
4990 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4991 n->as_Bool()->_test._test == BoolTest::ge ||
4992 n->as_Bool()->_test._test == BoolTest::le ||
4993 n->as_Bool()->_test._test == BoolTest::gt);
4994 format %{ "" %}
4995 interface(COND_INTER) %{
4996 equal(0x4, "e");
4997 not_equal(0x5, "ne");
4998 less(0x2, "b");
4999 greater_equal(0x3, "nb");
5000 less_equal(0x6, "be");
5001 greater(0x7, "nbe");
5002 %}
5003 %}
5004
5005
5006 // Floating comparisons that can be fixed up with extra conditional jumps
5007 operand cmpOpUCF2() %{
5008 match(Bool);
5009 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5010 n->as_Bool()->_test._test == BoolTest::eq);
5011 format %{ "" %}
5012 interface(COND_INTER) %{
5013 equal(0x4, "e");
5014 not_equal(0x5, "ne");
5015 less(0x2, "b");
5016 greater_equal(0x3, "nb");
5017 less_equal(0x6, "be");
5018 greater(0x7, "nbe");
5019 %}
5020 %}
5021
5022 // Comparison Code for FP conditional move
5023 operand cmpOp_fcmov() %{
5024 match(Bool);
5025
5026 format %{ "" %}
5027 interface(COND_INTER) %{
5028 equal (0x0C8);
5029 not_equal (0x1C8);
5030 less (0x0C0);
5031 greater_equal(0x1C0);
5032 less_equal (0x0D0);
5033 greater (0x1D0);
5034 %}
5035 %}
5036
5037 // Comparision Code used in long compares
5038 operand cmpOp_commute() %{
5039 match(Bool);
5040
5041 format %{ "" %}
5042 interface(COND_INTER) %{
5043 equal(0x4, "e");
5044 not_equal(0x5, "ne");
5045 less(0xF, "g");
5046 greater_equal(0xE, "le");
5047 less_equal(0xD, "ge");
5048 greater(0xC, "l");
5049 %}
5050 %}
5051
5052 //----------OPERAND CLASSES----------------------------------------------------
5053 // Operand Classes are groups of operands that are used as to simplify
5054 // instruction definitions by not requiring the AD writer to specify separate
5055 // instructions for every form of operand when the instruction accepts
5056 // multiple operand types with the same basic encoding and format. The classic
5057 // case of this is memory operands.
5058
5059 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5060 indIndex, indIndexScale, indIndexScaleOffset);
5061
5062 // Long memory operations are encoded in 2 instructions and a +4 offset.
5063 // This means some kind of offset is always required and you cannot use
5064 // an oop as the offset (done when working on static globals).
5065 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5066 indIndex, indIndexScale, indIndexScaleOffset);
5067
5068
5069 //----------PIPELINE-----------------------------------------------------------
5070 // Rules which define the behavior of the target architectures pipeline.
5071 pipeline %{
5072
5073 //----------ATTRIBUTES---------------------------------------------------------
5074 attributes %{
5075 variable_size_instructions; // Fixed size instructions
5076 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5077 instruction_unit_size = 1; // An instruction is 1 bytes long
5078 instruction_fetch_unit_size = 16; // The processor fetches one line
5079 instruction_fetch_units = 1; // of 16 bytes
5080
5081 // List of nop instructions
5082 nops( MachNop );
5083 %}
5084
5085 //----------RESOURCES----------------------------------------------------------
5086 // Resources are the functional units available to the machine
5087
5088 // Generic P2/P3 pipeline
5089 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5090 // 3 instructions decoded per cycle.
5091 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5092 // 2 ALU op, only ALU0 handles mul/div instructions.
5093 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5094 MS0, MS1, MEM = MS0 | MS1,
5095 BR, FPU,
5096 ALU0, ALU1, ALU = ALU0 | ALU1 );
5097
5098 //----------PIPELINE DESCRIPTION-----------------------------------------------
5099 // Pipeline Description specifies the stages in the machine's pipeline
5100
5101 // Generic P2/P3 pipeline
5102 pipe_desc(S0, S1, S2, S3, S4, S5);
5103
5104 //----------PIPELINE CLASSES---------------------------------------------------
5105 // Pipeline Classes describe the stages in which input and output are
5106 // referenced by the hardware pipeline.
5107
5108 // Naming convention: ialu or fpu
5109 // Then: _reg
5110 // Then: _reg if there is a 2nd register
5111 // Then: _long if it's a pair of instructions implementing a long
5112 // Then: _fat if it requires the big decoder
5113 // Or: _mem if it requires the big decoder and a memory unit.
5114
5115 // Integer ALU reg operation
5116 pipe_class ialu_reg(rRegI dst) %{
5117 single_instruction;
5118 dst : S4(write);
5119 dst : S3(read);
5120 DECODE : S0; // any decoder
5121 ALU : S3; // any alu
5122 %}
5123
5124 // Long ALU reg operation
5125 pipe_class ialu_reg_long(eRegL dst) %{
5126 instruction_count(2);
5127 dst : S4(write);
5128 dst : S3(read);
5129 DECODE : S0(2); // any 2 decoders
5130 ALU : S3(2); // both alus
5131 %}
5132
5133 // Integer ALU reg operation using big decoder
5134 pipe_class ialu_reg_fat(rRegI dst) %{
5135 single_instruction;
5136 dst : S4(write);
5137 dst : S3(read);
5138 D0 : S0; // big decoder only
5139 ALU : S3; // any alu
5140 %}
5141
5142 // Long ALU reg operation using big decoder
5143 pipe_class ialu_reg_long_fat(eRegL dst) %{
5144 instruction_count(2);
5145 dst : S4(write);
5146 dst : S3(read);
5147 D0 : S0(2); // big decoder only; twice
5148 ALU : S3(2); // any 2 alus
5149 %}
5150
5151 // Integer ALU reg-reg operation
5152 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5153 single_instruction;
5154 dst : S4(write);
5155 src : S3(read);
5156 DECODE : S0; // any decoder
5157 ALU : S3; // any alu
5158 %}
5159
5160 // Long ALU reg-reg operation
5161 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5162 instruction_count(2);
5163 dst : S4(write);
5164 src : S3(read);
5165 DECODE : S0(2); // any 2 decoders
5166 ALU : S3(2); // both alus
5167 %}
5168
5169 // Integer ALU reg-reg operation
5170 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5171 single_instruction;
5172 dst : S4(write);
5173 src : S3(read);
5174 D0 : S0; // big decoder only
5175 ALU : S3; // any alu
5176 %}
5177
5178 // Long ALU reg-reg operation
5179 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5180 instruction_count(2);
5181 dst : S4(write);
5182 src : S3(read);
5183 D0 : S0(2); // big decoder only; twice
5184 ALU : S3(2); // both alus
5185 %}
5186
5187 // Integer ALU reg-mem operation
5188 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5189 single_instruction;
5190 dst : S5(write);
5191 mem : S3(read);
5192 D0 : S0; // big decoder only
5193 ALU : S4; // any alu
5194 MEM : S3; // any mem
5195 %}
5196
5197 // Long ALU reg-mem operation
5198 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5199 instruction_count(2);
5200 dst : S5(write);
5201 mem : S3(read);
5202 D0 : S0(2); // big decoder only; twice
5203 ALU : S4(2); // any 2 alus
5204 MEM : S3(2); // both mems
5205 %}
5206
5207 // Integer mem operation (prefetch)
5208 pipe_class ialu_mem(memory mem)
5209 %{
5210 single_instruction;
5211 mem : S3(read);
5212 D0 : S0; // big decoder only
5213 MEM : S3; // any mem
5214 %}
5215
5216 // Integer Store to Memory
5217 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5218 single_instruction;
5219 mem : S3(read);
5220 src : S5(read);
5221 D0 : S0; // big decoder only
5222 ALU : S4; // any alu
5223 MEM : S3;
5224 %}
5225
5226 // Long Store to Memory
5227 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5228 instruction_count(2);
5229 mem : S3(read);
5230 src : S5(read);
5231 D0 : S0(2); // big decoder only; twice
5232 ALU : S4(2); // any 2 alus
5233 MEM : S3(2); // Both mems
5234 %}
5235
5236 // Integer Store to Memory
5237 pipe_class ialu_mem_imm(memory mem) %{
5238 single_instruction;
5239 mem : S3(read);
5240 D0 : S0; // big decoder only
5241 ALU : S4; // any alu
5242 MEM : S3;
5243 %}
5244
5245 // Integer ALU0 reg-reg operation
5246 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5247 single_instruction;
5248 dst : S4(write);
5249 src : S3(read);
5250 D0 : S0; // Big decoder only
5251 ALU0 : S3; // only alu0
5252 %}
5253
5254 // Integer ALU0 reg-mem operation
5255 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5256 single_instruction;
5257 dst : S5(write);
5258 mem : S3(read);
5259 D0 : S0; // big decoder only
5260 ALU0 : S4; // ALU0 only
5261 MEM : S3; // any mem
5262 %}
5263
5264 // Integer ALU reg-reg operation
5265 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5266 single_instruction;
5267 cr : S4(write);
5268 src1 : S3(read);
5269 src2 : S3(read);
5270 DECODE : S0; // any decoder
5271 ALU : S3; // any alu
5272 %}
5273
5274 // Integer ALU reg-imm operation
5275 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5276 single_instruction;
5277 cr : S4(write);
5278 src1 : S3(read);
5279 DECODE : S0; // any decoder
5280 ALU : S3; // any alu
5281 %}
5282
5283 // Integer ALU reg-mem operation
5284 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5285 single_instruction;
5286 cr : S4(write);
5287 src1 : S3(read);
5288 src2 : S3(read);
5289 D0 : S0; // big decoder only
5290 ALU : S4; // any alu
5291 MEM : S3;
5292 %}
5293
5294 // Conditional move reg-reg
5295 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5296 instruction_count(4);
5297 y : S4(read);
5298 q : S3(read);
5299 p : S3(read);
5300 DECODE : S0(4); // any decoder
5301 %}
5302
5303 // Conditional move reg-reg
5304 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5305 single_instruction;
5306 dst : S4(write);
5307 src : S3(read);
5308 cr : S3(read);
5309 DECODE : S0; // any decoder
5310 %}
5311
5312 // Conditional move reg-mem
5313 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5314 single_instruction;
5315 dst : S4(write);
5316 src : S3(read);
5317 cr : S3(read);
5318 DECODE : S0; // any decoder
5319 MEM : S3;
5320 %}
5321
5322 // Conditional move reg-reg long
5323 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5324 single_instruction;
5325 dst : S4(write);
5326 src : S3(read);
5327 cr : S3(read);
5328 DECODE : S0(2); // any 2 decoders
5329 %}
5330
5331 // Conditional move double reg-reg
5332 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5333 single_instruction;
5334 dst : S4(write);
5335 src : S3(read);
5336 cr : S3(read);
5337 DECODE : S0; // any decoder
5338 %}
5339
5340 // Float reg-reg operation
5341 pipe_class fpu_reg(regDPR dst) %{
5342 instruction_count(2);
5343 dst : S3(read);
5344 DECODE : S0(2); // any 2 decoders
5345 FPU : S3;
5346 %}
5347
5348 // Float reg-reg operation
5349 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5350 instruction_count(2);
5351 dst : S4(write);
5352 src : S3(read);
5353 DECODE : S0(2); // any 2 decoders
5354 FPU : S3;
5355 %}
5356
5357 // Float reg-reg operation
5358 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5359 instruction_count(3);
5360 dst : S4(write);
5361 src1 : S3(read);
5362 src2 : S3(read);
5363 DECODE : S0(3); // any 3 decoders
5364 FPU : S3(2);
5365 %}
5366
5367 // Float reg-reg operation
5368 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5369 instruction_count(4);
5370 dst : S4(write);
5371 src1 : S3(read);
5372 src2 : S3(read);
5373 src3 : S3(read);
5374 DECODE : S0(4); // any 3 decoders
5375 FPU : S3(2);
5376 %}
5377
5378 // Float reg-reg operation
5379 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5380 instruction_count(4);
5381 dst : S4(write);
5382 src1 : S3(read);
5383 src2 : S3(read);
5384 src3 : S3(read);
5385 DECODE : S1(3); // any 3 decoders
5386 D0 : S0; // Big decoder only
5387 FPU : S3(2);
5388 MEM : S3;
5389 %}
5390
5391 // Float reg-mem operation
5392 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5393 instruction_count(2);
5394 dst : S5(write);
5395 mem : S3(read);
5396 D0 : S0; // big decoder only
5397 DECODE : S1; // any decoder for FPU POP
5398 FPU : S4;
5399 MEM : S3; // any mem
5400 %}
5401
5402 // Float reg-mem operation
5403 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5404 instruction_count(3);
5405 dst : S5(write);
5406 src1 : S3(read);
5407 mem : S3(read);
5408 D0 : S0; // big decoder only
5409 DECODE : S1(2); // any decoder for FPU POP
5410 FPU : S4;
5411 MEM : S3; // any mem
5412 %}
5413
5414 // Float mem-reg operation
5415 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5416 instruction_count(2);
5417 src : S5(read);
5418 mem : S3(read);
5419 DECODE : S0; // any decoder for FPU PUSH
5420 D0 : S1; // big decoder only
5421 FPU : S4;
5422 MEM : S3; // any mem
5423 %}
5424
5425 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5426 instruction_count(3);
5427 src1 : S3(read);
5428 src2 : S3(read);
5429 mem : S3(read);
5430 DECODE : S0(2); // any decoder for FPU PUSH
5431 D0 : S1; // big decoder only
5432 FPU : S4;
5433 MEM : S3; // any mem
5434 %}
5435
5436 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5437 instruction_count(3);
5438 src1 : S3(read);
5439 src2 : S3(read);
5440 mem : S4(read);
5441 DECODE : S0; // any decoder for FPU PUSH
5442 D0 : S0(2); // big decoder only
5443 FPU : S4;
5444 MEM : S3(2); // any mem
5445 %}
5446
5447 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5448 instruction_count(2);
5449 src1 : S3(read);
5450 dst : S4(read);
5451 D0 : S0(2); // big decoder only
5452 MEM : S3(2); // any mem
5453 %}
5454
5455 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5456 instruction_count(3);
5457 src1 : S3(read);
5458 src2 : S3(read);
5459 dst : S4(read);
5460 D0 : S0(3); // big decoder only
5461 FPU : S4;
5462 MEM : S3(3); // any mem
5463 %}
5464
5465 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5466 instruction_count(3);
5467 src1 : S4(read);
5468 mem : S4(read);
5469 DECODE : S0; // any decoder for FPU PUSH
5470 D0 : S0(2); // big decoder only
5471 FPU : S4;
5472 MEM : S3(2); // any mem
5473 %}
5474
5475 // Float load constant
5476 pipe_class fpu_reg_con(regDPR dst) %{
5477 instruction_count(2);
5478 dst : S5(write);
5479 D0 : S0; // big decoder only for the load
5480 DECODE : S1; // any decoder for FPU POP
5481 FPU : S4;
5482 MEM : S3; // any mem
5483 %}
5484
5485 // Float load constant
5486 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5487 instruction_count(3);
5488 dst : S5(write);
5489 src : S3(read);
5490 D0 : S0; // big decoder only for the load
5491 DECODE : S1(2); // any decoder for FPU POP
5492 FPU : S4;
5493 MEM : S3; // any mem
5494 %}
5495
5496 // UnConditional branch
5497 pipe_class pipe_jmp( label labl ) %{
5498 single_instruction;
5499 BR : S3;
5500 %}
5501
5502 // Conditional branch
5503 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5504 single_instruction;
5505 cr : S1(read);
5506 BR : S3;
5507 %}
5508
5509 // Allocation idiom
5510 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5511 instruction_count(1); force_serialization;
5512 fixed_latency(6);
5513 heap_ptr : S3(read);
5514 DECODE : S0(3);
5515 D0 : S2;
5516 MEM : S3;
5517 ALU : S3(2);
5518 dst : S5(write);
5519 BR : S5;
5520 %}
5521
5522 // Generic big/slow expanded idiom
5523 pipe_class pipe_slow( ) %{
5524 instruction_count(10); multiple_bundles; force_serialization;
5525 fixed_latency(100);
5526 D0 : S0(2);
5527 MEM : S3(2);
5528 %}
5529
5530 // The real do-nothing guy
5531 pipe_class empty( ) %{
5532 instruction_count(0);
5533 %}
5534
5535 // Define the class for the Nop node
5536 define %{
5537 MachNop = empty;
5538 %}
5539
5540 %}
5541
5542 //----------INSTRUCTIONS-------------------------------------------------------
5543 //
5544 // match -- States which machine-independent subtree may be replaced
5545 // by this instruction.
5546 // ins_cost -- The estimated cost of this instruction is used by instruction
5547 // selection to identify a minimum cost tree of machine
5548 // instructions that matches a tree of machine-independent
5549 // instructions.
5550 // format -- A string providing the disassembly for this instruction.
5551 // The value of an instruction's operand may be inserted
5552 // by referring to it with a '$' prefix.
5553 // opcode -- Three instruction opcodes may be provided. These are referred
5554 // to within an encode class as $primary, $secondary, and $tertiary
5555 // respectively. The primary opcode is commonly used to
5556 // indicate the type of machine instruction, while secondary
5557 // and tertiary are often used for prefix options or addressing
5558 // modes.
5559 // ins_encode -- A list of encode classes with parameters. The encode class
5560 // name must have been defined in an 'enc_class' specification
5561 // in the encode section of the architecture description.
5562
5563 //----------BSWAP-Instruction--------------------------------------------------
5564 instruct bytes_reverse_int(rRegI dst) %{
5565 match(Set dst (ReverseBytesI dst));
5566
5567 format %{ "BSWAP $dst" %}
5568 opcode(0x0F, 0xC8);
5569 ins_encode( OpcP, OpcSReg(dst) );
5570 ins_pipe( ialu_reg );
5571 %}
5572
5573 instruct bytes_reverse_long(eRegL dst) %{
5574 match(Set dst (ReverseBytesL dst));
5575
5576 format %{ "BSWAP $dst.lo\n\t"
5577 "BSWAP $dst.hi\n\t"
5578 "XCHG $dst.lo $dst.hi" %}
5579
5580 ins_cost(125);
5581 ins_encode( bswap_long_bytes(dst) );
5582 ins_pipe( ialu_reg_reg);
5583 %}
5584
5585 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5586 match(Set dst (ReverseBytesUS dst));
5587 effect(KILL cr);
5588
5589 format %{ "BSWAP $dst\n\t"
5590 "SHR $dst,16\n\t" %}
5591 ins_encode %{
5592 __ bswapl($dst$$Register);
5593 __ shrl($dst$$Register, 16);
5594 %}
5595 ins_pipe( ialu_reg );
5596 %}
5597
5598 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5599 match(Set dst (ReverseBytesS dst));
5600 effect(KILL cr);
5601
5602 format %{ "BSWAP $dst\n\t"
5603 "SAR $dst,16\n\t" %}
5604 ins_encode %{
5605 __ bswapl($dst$$Register);
5606 __ sarl($dst$$Register, 16);
5607 %}
5608 ins_pipe( ialu_reg );
5609 %}
5610
5611
5612 //---------- Zeros Count Instructions ------------------------------------------
5613
5614 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5615 predicate(UseCountLeadingZerosInstruction);
5616 match(Set dst (CountLeadingZerosI src));
5617 effect(KILL cr);
5618
5619 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5620 ins_encode %{
5621 __ lzcntl($dst$$Register, $src$$Register);
5622 %}
5623 ins_pipe(ialu_reg);
5624 %}
5625
5626 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5627 predicate(!UseCountLeadingZerosInstruction);
5628 match(Set dst (CountLeadingZerosI src));
5629 effect(KILL cr);
5630
5631 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5632 "JNZ skip\n\t"
5633 "MOV $dst, -1\n"
5634 "skip:\n\t"
5635 "NEG $dst\n\t"
5636 "ADD $dst, 31" %}
5637 ins_encode %{
5638 Register Rdst = $dst$$Register;
5639 Register Rsrc = $src$$Register;
5640 Label skip;
5641 __ bsrl(Rdst, Rsrc);
5642 __ jccb(Assembler::notZero, skip);
5643 __ movl(Rdst, -1);
5644 __ bind(skip);
5645 __ negl(Rdst);
5646 __ addl(Rdst, BitsPerInt - 1);
5647 %}
5648 ins_pipe(ialu_reg);
5649 %}
5650
5651 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5652 predicate(UseCountLeadingZerosInstruction);
5653 match(Set dst (CountLeadingZerosL src));
5654 effect(TEMP dst, KILL cr);
5655
5656 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5657 "JNC done\n\t"
5658 "LZCNT $dst, $src.lo\n\t"
5659 "ADD $dst, 32\n"
5660 "done:" %}
5661 ins_encode %{
5662 Register Rdst = $dst$$Register;
5663 Register Rsrc = $src$$Register;
5664 Label done;
5665 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5666 __ jccb(Assembler::carryClear, done);
5667 __ lzcntl(Rdst, Rsrc);
5668 __ addl(Rdst, BitsPerInt);
5669 __ bind(done);
5670 %}
5671 ins_pipe(ialu_reg);
5672 %}
5673
5674 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5675 predicate(!UseCountLeadingZerosInstruction);
5676 match(Set dst (CountLeadingZerosL src));
5677 effect(TEMP dst, KILL cr);
5678
5679 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5680 "JZ msw_is_zero\n\t"
5681 "ADD $dst, 32\n\t"
5682 "JMP not_zero\n"
5683 "msw_is_zero:\n\t"
5684 "BSR $dst, $src.lo\n\t"
5685 "JNZ not_zero\n\t"
5686 "MOV $dst, -1\n"
5687 "not_zero:\n\t"
5688 "NEG $dst\n\t"
5689 "ADD $dst, 63\n" %}
5690 ins_encode %{
5691 Register Rdst = $dst$$Register;
5692 Register Rsrc = $src$$Register;
5693 Label msw_is_zero;
5694 Label not_zero;
5695 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5696 __ jccb(Assembler::zero, msw_is_zero);
5697 __ addl(Rdst, BitsPerInt);
5698 __ jmpb(not_zero);
5699 __ bind(msw_is_zero);
5700 __ bsrl(Rdst, Rsrc);
5701 __ jccb(Assembler::notZero, not_zero);
5702 __ movl(Rdst, -1);
5703 __ bind(not_zero);
5704 __ negl(Rdst);
5705 __ addl(Rdst, BitsPerLong - 1);
5706 %}
5707 ins_pipe(ialu_reg);
5708 %}
5709
5710 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5711 match(Set dst (CountTrailingZerosI src));
5712 effect(KILL cr);
5713
5714 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5715 "JNZ done\n\t"
5716 "MOV $dst, 32\n"
5717 "done:" %}
5718 ins_encode %{
5719 Register Rdst = $dst$$Register;
5720 Label done;
5721 __ bsfl(Rdst, $src$$Register);
5722 __ jccb(Assembler::notZero, done);
5723 __ movl(Rdst, BitsPerInt);
5724 __ bind(done);
5725 %}
5726 ins_pipe(ialu_reg);
5727 %}
5728
5729 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5730 match(Set dst (CountTrailingZerosL src));
5731 effect(TEMP dst, KILL cr);
5732
5733 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5734 "JNZ done\n\t"
5735 "BSF $dst, $src.hi\n\t"
5736 "JNZ msw_not_zero\n\t"
5737 "MOV $dst, 32\n"
5738 "msw_not_zero:\n\t"
5739 "ADD $dst, 32\n"
5740 "done:" %}
5741 ins_encode %{
5742 Register Rdst = $dst$$Register;
5743 Register Rsrc = $src$$Register;
5744 Label msw_not_zero;
5745 Label done;
5746 __ bsfl(Rdst, Rsrc);
5747 __ jccb(Assembler::notZero, done);
5748 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5749 __ jccb(Assembler::notZero, msw_not_zero);
5750 __ movl(Rdst, BitsPerInt);
5751 __ bind(msw_not_zero);
5752 __ addl(Rdst, BitsPerInt);
5753 __ bind(done);
5754 %}
5755 ins_pipe(ialu_reg);
5756 %}
5757
5758
5759 //---------- Population Count Instructions -------------------------------------
5760
5761 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5762 predicate(UsePopCountInstruction);
5763 match(Set dst (PopCountI src));
5764 effect(KILL cr);
5765
5766 format %{ "POPCNT $dst, $src" %}
5767 ins_encode %{
5768 __ popcntl($dst$$Register, $src$$Register);
5769 %}
5770 ins_pipe(ialu_reg);
5771 %}
5772
5773 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5774 predicate(UsePopCountInstruction);
5775 match(Set dst (PopCountI (LoadI mem)));
5776 effect(KILL cr);
5777
5778 format %{ "POPCNT $dst, $mem" %}
5779 ins_encode %{
5780 __ popcntl($dst$$Register, $mem$$Address);
5781 %}
5782 ins_pipe(ialu_reg);
5783 %}
5784
5785 // Note: Long.bitCount(long) returns an int.
5786 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5787 predicate(UsePopCountInstruction);
5788 match(Set dst (PopCountL src));
5789 effect(KILL cr, TEMP tmp, TEMP dst);
5790
5791 format %{ "POPCNT $dst, $src.lo\n\t"
5792 "POPCNT $tmp, $src.hi\n\t"
5793 "ADD $dst, $tmp" %}
5794 ins_encode %{
5795 __ popcntl($dst$$Register, $src$$Register);
5796 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5797 __ addl($dst$$Register, $tmp$$Register);
5798 %}
5799 ins_pipe(ialu_reg);
5800 %}
5801
5802 // Note: Long.bitCount(long) returns an int.
5803 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5804 predicate(UsePopCountInstruction);
5805 match(Set dst (PopCountL (LoadL mem)));
5806 effect(KILL cr, TEMP tmp, TEMP dst);
5807
5808 format %{ "POPCNT $dst, $mem\n\t"
5809 "POPCNT $tmp, $mem+4\n\t"
5810 "ADD $dst, $tmp" %}
5811 ins_encode %{
5812 //__ popcntl($dst$$Register, $mem$$Address$$first);
5813 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5814 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5815 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5816 __ addl($dst$$Register, $tmp$$Register);
5817 %}
5818 ins_pipe(ialu_reg);
5819 %}
5820
5821
5822 //----------Load/Store/Move Instructions---------------------------------------
5823 //----------Load Instructions--------------------------------------------------
5824 // Load Byte (8bit signed)
5825 instruct loadB(xRegI dst, memory mem) %{
5826 match(Set dst (LoadB mem));
5827
5828 ins_cost(125);
5829 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5830
5831 ins_encode %{
5832 __ movsbl($dst$$Register, $mem$$Address);
5833 %}
5834
5835 ins_pipe(ialu_reg_mem);
5836 %}
5837
5838 // Load Byte (8bit signed) into Long Register
5839 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5840 match(Set dst (ConvI2L (LoadB mem)));
5841 effect(KILL cr);
5842
5843 ins_cost(375);
5844 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5845 "MOV $dst.hi,$dst.lo\n\t"
5846 "SAR $dst.hi,7" %}
5847
5848 ins_encode %{
5849 __ movsbl($dst$$Register, $mem$$Address);
5850 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5851 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5852 %}
5853
5854 ins_pipe(ialu_reg_mem);
5855 %}
5856
5857 // Load Unsigned Byte (8bit UNsigned)
5858 instruct loadUB(xRegI dst, memory mem) %{
5859 match(Set dst (LoadUB mem));
5860
5861 ins_cost(125);
5862 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5863
5864 ins_encode %{
5865 __ movzbl($dst$$Register, $mem$$Address);
5866 %}
5867
5868 ins_pipe(ialu_reg_mem);
5869 %}
5870
5871 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5872 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5873 match(Set dst (ConvI2L (LoadUB mem)));
5874 effect(KILL cr);
5875
5876 ins_cost(250);
5877 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5878 "XOR $dst.hi,$dst.hi" %}
5879
5880 ins_encode %{
5881 Register Rdst = $dst$$Register;
5882 __ movzbl(Rdst, $mem$$Address);
5883 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5884 %}
5885
5886 ins_pipe(ialu_reg_mem);
5887 %}
5888
5889 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5890 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5891 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5892 effect(KILL cr);
5893
5894 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5895 "XOR $dst.hi,$dst.hi\n\t"
5896 "AND $dst.lo,$mask" %}
5897 ins_encode %{
5898 Register Rdst = $dst$$Register;
5899 __ movzbl(Rdst, $mem$$Address);
5900 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5901 __ andl(Rdst, $mask$$constant);
5902 %}
5903 ins_pipe(ialu_reg_mem);
5904 %}
5905
5906 // Load Short (16bit signed)
5907 instruct loadS(rRegI dst, memory mem) %{
5908 match(Set dst (LoadS mem));
5909
5910 ins_cost(125);
5911 format %{ "MOVSX $dst,$mem\t# short" %}
5912
5913 ins_encode %{
5914 __ movswl($dst$$Register, $mem$$Address);
5915 %}
5916
5917 ins_pipe(ialu_reg_mem);
5918 %}
5919
5920 // Load Short (16 bit signed) to Byte (8 bit signed)
5921 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5922 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5923
5924 ins_cost(125);
5925 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5926 ins_encode %{
5927 __ movsbl($dst$$Register, $mem$$Address);
5928 %}
5929 ins_pipe(ialu_reg_mem);
5930 %}
5931
5932 // Load Short (16bit signed) into Long Register
5933 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5934 match(Set dst (ConvI2L (LoadS mem)));
5935 effect(KILL cr);
5936
5937 ins_cost(375);
5938 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5939 "MOV $dst.hi,$dst.lo\n\t"
5940 "SAR $dst.hi,15" %}
5941
5942 ins_encode %{
5943 __ movswl($dst$$Register, $mem$$Address);
5944 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5945 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5946 %}
5947
5948 ins_pipe(ialu_reg_mem);
5949 %}
5950
5951 // Load Unsigned Short/Char (16bit unsigned)
5952 instruct loadUS(rRegI dst, memory mem) %{
5953 match(Set dst (LoadUS mem));
5954
5955 ins_cost(125);
5956 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5957
5958 ins_encode %{
5959 __ movzwl($dst$$Register, $mem$$Address);
5960 %}
5961
5962 ins_pipe(ialu_reg_mem);
5963 %}
5964
5965 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5966 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5967 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5968
5969 ins_cost(125);
5970 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5971 ins_encode %{
5972 __ movsbl($dst$$Register, $mem$$Address);
5973 %}
5974 ins_pipe(ialu_reg_mem);
5975 %}
5976
5977 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5978 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5979 match(Set dst (ConvI2L (LoadUS mem)));
5980 effect(KILL cr);
5981
5982 ins_cost(250);
5983 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5984 "XOR $dst.hi,$dst.hi" %}
5985
5986 ins_encode %{
5987 __ movzwl($dst$$Register, $mem$$Address);
5988 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5989 %}
5990
5991 ins_pipe(ialu_reg_mem);
5992 %}
5993
5994 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5995 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5996 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5997 effect(KILL cr);
5998
5999 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6000 "XOR $dst.hi,$dst.hi" %}
6001 ins_encode %{
6002 Register Rdst = $dst$$Register;
6003 __ movzbl(Rdst, $mem$$Address);
6004 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6005 %}
6006 ins_pipe(ialu_reg_mem);
6007 %}
6008
6009 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6010 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6011 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6012 effect(KILL cr);
6013
6014 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6015 "XOR $dst.hi,$dst.hi\n\t"
6016 "AND $dst.lo,$mask" %}
6017 ins_encode %{
6018 Register Rdst = $dst$$Register;
6019 __ movzwl(Rdst, $mem$$Address);
6020 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6021 __ andl(Rdst, $mask$$constant);
6022 %}
6023 ins_pipe(ialu_reg_mem);
6024 %}
6025
6026 // Load Integer
6027 instruct loadI(rRegI dst, memory mem) %{
6028 match(Set dst (LoadI mem));
6029
6030 ins_cost(125);
6031 format %{ "MOV $dst,$mem\t# int" %}
6032
6033 ins_encode %{
6034 __ movl($dst$$Register, $mem$$Address);
6035 %}
6036
6037 ins_pipe(ialu_reg_mem);
6038 %}
6039
6040 // Load Integer (32 bit signed) to Byte (8 bit signed)
6041 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6042 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6043
6044 ins_cost(125);
6045 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6046 ins_encode %{
6047 __ movsbl($dst$$Register, $mem$$Address);
6048 %}
6049 ins_pipe(ialu_reg_mem);
6050 %}
6051
6052 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6053 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6054 match(Set dst (AndI (LoadI mem) mask));
6055
6056 ins_cost(125);
6057 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6058 ins_encode %{
6059 __ movzbl($dst$$Register, $mem$$Address);
6060 %}
6061 ins_pipe(ialu_reg_mem);
6062 %}
6063
6064 // Load Integer (32 bit signed) to Short (16 bit signed)
6065 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6066 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6067
6068 ins_cost(125);
6069 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6070 ins_encode %{
6071 __ movswl($dst$$Register, $mem$$Address);
6072 %}
6073 ins_pipe(ialu_reg_mem);
6074 %}
6075
6076 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6077 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6078 match(Set dst (AndI (LoadI mem) mask));
6079
6080 ins_cost(125);
6081 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6082 ins_encode %{
6083 __ movzwl($dst$$Register, $mem$$Address);
6084 %}
6085 ins_pipe(ialu_reg_mem);
6086 %}
6087
6088 // Load Integer into Long Register
6089 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6090 match(Set dst (ConvI2L (LoadI mem)));
6091 effect(KILL cr);
6092
6093 ins_cost(375);
6094 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6095 "MOV $dst.hi,$dst.lo\n\t"
6096 "SAR $dst.hi,31" %}
6097
6098 ins_encode %{
6099 __ movl($dst$$Register, $mem$$Address);
6100 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6101 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6102 %}
6103
6104 ins_pipe(ialu_reg_mem);
6105 %}
6106
6107 // Load Integer with mask 0xFF into Long Register
6108 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6109 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6110 effect(KILL cr);
6111
6112 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6113 "XOR $dst.hi,$dst.hi" %}
6114 ins_encode %{
6115 Register Rdst = $dst$$Register;
6116 __ movzbl(Rdst, $mem$$Address);
6117 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6118 %}
6119 ins_pipe(ialu_reg_mem);
6120 %}
6121
6122 // Load Integer with mask 0xFFFF into Long Register
6123 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6124 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6125 effect(KILL cr);
6126
6127 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6128 "XOR $dst.hi,$dst.hi" %}
6129 ins_encode %{
6130 Register Rdst = $dst$$Register;
6131 __ movzwl(Rdst, $mem$$Address);
6132 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6133 %}
6134 ins_pipe(ialu_reg_mem);
6135 %}
6136
6137 // Load Integer with 32-bit mask into Long Register
6138 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6139 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6140 effect(KILL cr);
6141
6142 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6143 "XOR $dst.hi,$dst.hi\n\t"
6144 "AND $dst.lo,$mask" %}
6145 ins_encode %{
6146 Register Rdst = $dst$$Register;
6147 __ movl(Rdst, $mem$$Address);
6148 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6149 __ andl(Rdst, $mask$$constant);
6150 %}
6151 ins_pipe(ialu_reg_mem);
6152 %}
6153
6154 // Load Unsigned Integer into Long Register
6155 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6156 match(Set dst (LoadUI2L mem));
6157 effect(KILL cr);
6158
6159 ins_cost(250);
6160 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6161 "XOR $dst.hi,$dst.hi" %}
6162
6163 ins_encode %{
6164 __ movl($dst$$Register, $mem$$Address);
6165 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6166 %}
6167
6168 ins_pipe(ialu_reg_mem);
6169 %}
6170
6171 // Load Long. Cannot clobber address while loading, so restrict address
6172 // register to ESI
6173 instruct loadL(eRegL dst, load_long_memory mem) %{
6174 predicate(!((LoadLNode*)n)->require_atomic_access());
6175 match(Set dst (LoadL mem));
6176
6177 ins_cost(250);
6178 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6179 "MOV $dst.hi,$mem+4" %}
6180
6181 ins_encode %{
6182 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6183 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6184 __ movl($dst$$Register, Amemlo);
6185 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6186 %}
6187
6188 ins_pipe(ialu_reg_long_mem);
6189 %}
6190
6191 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6192 // then store it down to the stack and reload on the int
6193 // side.
6194 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6195 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6196 match(Set dst (LoadL mem));
6197
6198 ins_cost(200);
6199 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6200 "FISTp $dst" %}
6201 ins_encode(enc_loadL_volatile(mem,dst));
6202 ins_pipe( fpu_reg_mem );
6203 %}
6204
6205 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6206 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6207 match(Set dst (LoadL mem));
6208 effect(TEMP tmp);
6209 ins_cost(180);
6210 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6211 "MOVSD $dst,$tmp" %}
6212 ins_encode %{
6213 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6214 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6215 %}
6216 ins_pipe( pipe_slow );
6217 %}
6218
6219 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6220 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6221 match(Set dst (LoadL mem));
6222 effect(TEMP tmp);
6223 ins_cost(160);
6224 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6225 "MOVD $dst.lo,$tmp\n\t"
6226 "PSRLQ $tmp,32\n\t"
6227 "MOVD $dst.hi,$tmp" %}
6228 ins_encode %{
6229 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6230 __ movdl($dst$$Register, $tmp$$XMMRegister);
6231 __ psrlq($tmp$$XMMRegister, 32);
6232 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6233 %}
6234 ins_pipe( pipe_slow );
6235 %}
6236
6237 // Load Range
6238 instruct loadRange(rRegI dst, memory mem) %{
6239 match(Set dst (LoadRange mem));
6240
6241 ins_cost(125);
6242 format %{ "MOV $dst,$mem" %}
6243 opcode(0x8B);
6244 ins_encode( OpcP, RegMem(dst,mem));
6245 ins_pipe( ialu_reg_mem );
6246 %}
6247
6248
6249 // Load Pointer
6250 instruct loadP(eRegP dst, memory mem) %{
6251 match(Set dst (LoadP mem));
6252
6253 ins_cost(125);
6254 format %{ "MOV $dst,$mem" %}
6255 opcode(0x8B);
6256 ins_encode( OpcP, RegMem(dst,mem));
6257 ins_pipe( ialu_reg_mem );
6258 %}
6259
6260 // Load Klass Pointer
6261 instruct loadKlass(eRegP dst, memory mem) %{
6262 match(Set dst (LoadKlass mem));
6263
6264 ins_cost(125);
6265 format %{ "MOV $dst,$mem" %}
6266 opcode(0x8B);
6267 ins_encode( OpcP, RegMem(dst,mem));
6268 ins_pipe( ialu_reg_mem );
6269 %}
6270
6271 // Load Double
6272 instruct loadDPR(regDPR dst, memory mem) %{
6273 predicate(UseSSE<=1);
6274 match(Set dst (LoadD mem));
6275
6276 ins_cost(150);
6277 format %{ "FLD_D ST,$mem\n\t"
6278 "FSTP $dst" %}
6279 opcode(0xDD); /* DD /0 */
6280 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6281 Pop_Reg_DPR(dst) );
6282 ins_pipe( fpu_reg_mem );
6283 %}
6284
6285 // Load Double to XMM
6286 instruct loadD(regD dst, memory mem) %{
6287 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6288 match(Set dst (LoadD mem));
6289 ins_cost(145);
6290 format %{ "MOVSD $dst,$mem" %}
6291 ins_encode %{
6292 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6293 %}
6294 ins_pipe( pipe_slow );
6295 %}
6296
6297 instruct loadD_partial(regD dst, memory mem) %{
6298 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6299 match(Set dst (LoadD mem));
6300 ins_cost(145);
6301 format %{ "MOVLPD $dst,$mem" %}
6302 ins_encode %{
6303 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6304 %}
6305 ins_pipe( pipe_slow );
6306 %}
6307
6308 // Load to XMM register (single-precision floating point)
6309 // MOVSS instruction
6310 instruct loadF(regF dst, memory mem) %{
6311 predicate(UseSSE>=1);
6312 match(Set dst (LoadF mem));
6313 ins_cost(145);
6314 format %{ "MOVSS $dst,$mem" %}
6315 ins_encode %{
6316 __ movflt ($dst$$XMMRegister, $mem$$Address);
6317 %}
6318 ins_pipe( pipe_slow );
6319 %}
6320
6321 // Load Float
6322 instruct loadFPR(regFPR dst, memory mem) %{
6323 predicate(UseSSE==0);
6324 match(Set dst (LoadF mem));
6325
6326 ins_cost(150);
6327 format %{ "FLD_S ST,$mem\n\t"
6328 "FSTP $dst" %}
6329 opcode(0xD9); /* D9 /0 */
6330 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6331 Pop_Reg_FPR(dst) );
6332 ins_pipe( fpu_reg_mem );
6333 %}
6334
6335 // Load Effective Address
6336 instruct leaP8(eRegP dst, indOffset8 mem) %{
6337 match(Set dst mem);
6338
6339 ins_cost(110);
6340 format %{ "LEA $dst,$mem" %}
6341 opcode(0x8D);
6342 ins_encode( OpcP, RegMem(dst,mem));
6343 ins_pipe( ialu_reg_reg_fat );
6344 %}
6345
6346 instruct leaP32(eRegP dst, indOffset32 mem) %{
6347 match(Set dst mem);
6348
6349 ins_cost(110);
6350 format %{ "LEA $dst,$mem" %}
6351 opcode(0x8D);
6352 ins_encode( OpcP, RegMem(dst,mem));
6353 ins_pipe( ialu_reg_reg_fat );
6354 %}
6355
6356 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6357 match(Set dst mem);
6358
6359 ins_cost(110);
6360 format %{ "LEA $dst,$mem" %}
6361 opcode(0x8D);
6362 ins_encode( OpcP, RegMem(dst,mem));
6363 ins_pipe( ialu_reg_reg_fat );
6364 %}
6365
6366 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6367 match(Set dst mem);
6368
6369 ins_cost(110);
6370 format %{ "LEA $dst,$mem" %}
6371 opcode(0x8D);
6372 ins_encode( OpcP, RegMem(dst,mem));
6373 ins_pipe( ialu_reg_reg_fat );
6374 %}
6375
6376 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6377 match(Set dst mem);
6378
6379 ins_cost(110);
6380 format %{ "LEA $dst,$mem" %}
6381 opcode(0x8D);
6382 ins_encode( OpcP, RegMem(dst,mem));
6383 ins_pipe( ialu_reg_reg_fat );
6384 %}
6385
6386 // Load Constant
6387 instruct loadConI(rRegI dst, immI src) %{
6388 match(Set dst src);
6389
6390 format %{ "MOV $dst,$src" %}
6391 ins_encode( LdImmI(dst, src) );
6392 ins_pipe( ialu_reg_fat );
6393 %}
6394
6395 // Load Constant zero
6396 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6397 match(Set dst src);
6398 effect(KILL cr);
6399
6400 ins_cost(50);
6401 format %{ "XOR $dst,$dst" %}
6402 opcode(0x33); /* + rd */
6403 ins_encode( OpcP, RegReg( dst, dst ) );
6404 ins_pipe( ialu_reg );
6405 %}
6406
6407 instruct loadConP(eRegP dst, immP src) %{
6408 match(Set dst src);
6409
6410 format %{ "MOV $dst,$src" %}
6411 opcode(0xB8); /* + rd */
6412 ins_encode( LdImmP(dst, src) );
6413 ins_pipe( ialu_reg_fat );
6414 %}
6415
6416 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6417 match(Set dst src);
6418 effect(KILL cr);
6419 ins_cost(200);
6420 format %{ "MOV $dst.lo,$src.lo\n\t"
6421 "MOV $dst.hi,$src.hi" %}
6422 opcode(0xB8);
6423 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6424 ins_pipe( ialu_reg_long_fat );
6425 %}
6426
6427 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6428 match(Set dst src);
6429 effect(KILL cr);
6430 ins_cost(150);
6431 format %{ "XOR $dst.lo,$dst.lo\n\t"
6432 "XOR $dst.hi,$dst.hi" %}
6433 opcode(0x33,0x33);
6434 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6435 ins_pipe( ialu_reg_long );
6436 %}
6437
6438 // The instruction usage is guarded by predicate in operand immFPR().
6439 instruct loadConFPR(regFPR dst, immFPR con) %{
6440 match(Set dst con);
6441 ins_cost(125);
6442 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6443 "FSTP $dst" %}
6444 ins_encode %{
6445 __ fld_s($constantaddress($con));
6446 __ fstp_d($dst$$reg);
6447 %}
6448 ins_pipe(fpu_reg_con);
6449 %}
6450
6451 // The instruction usage is guarded by predicate in operand immFPR0().
6452 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6453 match(Set dst con);
6454 ins_cost(125);
6455 format %{ "FLDZ ST\n\t"
6456 "FSTP $dst" %}
6457 ins_encode %{
6458 __ fldz();
6459 __ fstp_d($dst$$reg);
6460 %}
6461 ins_pipe(fpu_reg_con);
6462 %}
6463
6464 // The instruction usage is guarded by predicate in operand immFPR1().
6465 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6466 match(Set dst con);
6467 ins_cost(125);
6468 format %{ "FLD1 ST\n\t"
6469 "FSTP $dst" %}
6470 ins_encode %{
6471 __ fld1();
6472 __ fstp_d($dst$$reg);
6473 %}
6474 ins_pipe(fpu_reg_con);
6475 %}
6476
6477 // The instruction usage is guarded by predicate in operand immF().
6478 instruct loadConF(regF dst, immF con) %{
6479 match(Set dst con);
6480 ins_cost(125);
6481 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6482 ins_encode %{
6483 __ movflt($dst$$XMMRegister, $constantaddress($con));
6484 %}
6485 ins_pipe(pipe_slow);
6486 %}
6487
6488 // The instruction usage is guarded by predicate in operand immF0().
6489 instruct loadConF0(regF dst, immF0 src) %{
6490 match(Set dst src);
6491 ins_cost(100);
6492 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6493 ins_encode %{
6494 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6495 %}
6496 ins_pipe(pipe_slow);
6497 %}
6498
6499 // The instruction usage is guarded by predicate in operand immDPR().
6500 instruct loadConDPR(regDPR dst, immDPR con) %{
6501 match(Set dst con);
6502 ins_cost(125);
6503
6504 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6505 "FSTP $dst" %}
6506 ins_encode %{
6507 __ fld_d($constantaddress($con));
6508 __ fstp_d($dst$$reg);
6509 %}
6510 ins_pipe(fpu_reg_con);
6511 %}
6512
6513 // The instruction usage is guarded by predicate in operand immDPR0().
6514 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6515 match(Set dst con);
6516 ins_cost(125);
6517
6518 format %{ "FLDZ ST\n\t"
6519 "FSTP $dst" %}
6520 ins_encode %{
6521 __ fldz();
6522 __ fstp_d($dst$$reg);
6523 %}
6524 ins_pipe(fpu_reg_con);
6525 %}
6526
6527 // The instruction usage is guarded by predicate in operand immDPR1().
6528 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6529 match(Set dst con);
6530 ins_cost(125);
6531
6532 format %{ "FLD1 ST\n\t"
6533 "FSTP $dst" %}
6534 ins_encode %{
6535 __ fld1();
6536 __ fstp_d($dst$$reg);
6537 %}
6538 ins_pipe(fpu_reg_con);
6539 %}
6540
6541 // The instruction usage is guarded by predicate in operand immD().
6542 instruct loadConD(regD dst, immD con) %{
6543 match(Set dst con);
6544 ins_cost(125);
6545 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6546 ins_encode %{
6547 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6548 %}
6549 ins_pipe(pipe_slow);
6550 %}
6551
6552 // The instruction usage is guarded by predicate in operand immD0().
6553 instruct loadConD0(regD dst, immD0 src) %{
6554 match(Set dst src);
6555 ins_cost(100);
6556 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6557 ins_encode %{
6558 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6559 %}
6560 ins_pipe( pipe_slow );
6561 %}
6562
6563 // Load Stack Slot
6564 instruct loadSSI(rRegI dst, stackSlotI src) %{
6565 match(Set dst src);
6566 ins_cost(125);
6567
6568 format %{ "MOV $dst,$src" %}
6569 opcode(0x8B);
6570 ins_encode( OpcP, RegMem(dst,src));
6571 ins_pipe( ialu_reg_mem );
6572 %}
6573
6574 instruct loadSSL(eRegL dst, stackSlotL src) %{
6575 match(Set dst src);
6576
6577 ins_cost(200);
6578 format %{ "MOV $dst,$src.lo\n\t"
6579 "MOV $dst+4,$src.hi" %}
6580 opcode(0x8B, 0x8B);
6581 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6582 ins_pipe( ialu_mem_long_reg );
6583 %}
6584
6585 // Load Stack Slot
6586 instruct loadSSP(eRegP dst, stackSlotP src) %{
6587 match(Set dst src);
6588 ins_cost(125);
6589
6590 format %{ "MOV $dst,$src" %}
6591 opcode(0x8B);
6592 ins_encode( OpcP, RegMem(dst,src));
6593 ins_pipe( ialu_reg_mem );
6594 %}
6595
6596 // Load Stack Slot
6597 instruct loadSSF(regFPR dst, stackSlotF src) %{
6598 match(Set dst src);
6599 ins_cost(125);
6600
6601 format %{ "FLD_S $src\n\t"
6602 "FSTP $dst" %}
6603 opcode(0xD9); /* D9 /0, FLD m32real */
6604 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6605 Pop_Reg_FPR(dst) );
6606 ins_pipe( fpu_reg_mem );
6607 %}
6608
6609 // Load Stack Slot
6610 instruct loadSSD(regDPR dst, stackSlotD src) %{
6611 match(Set dst src);
6612 ins_cost(125);
6613
6614 format %{ "FLD_D $src\n\t"
6615 "FSTP $dst" %}
6616 opcode(0xDD); /* DD /0, FLD m64real */
6617 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6618 Pop_Reg_DPR(dst) );
6619 ins_pipe( fpu_reg_mem );
6620 %}
6621
6622 // Prefetch instructions.
6623 // Must be safe to execute with invalid address (cannot fault).
6624
6625 instruct prefetchr0( memory mem ) %{
6626 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6627 match(PrefetchRead mem);
6628 ins_cost(0);
6629 size(0);
6630 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6631 ins_encode();
6632 ins_pipe(empty);
6633 %}
6634
6635 instruct prefetchr( memory mem ) %{
6636 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6637 match(PrefetchRead mem);
6638 ins_cost(100);
6639
6640 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6641 ins_encode %{
6642 __ prefetchr($mem$$Address);
6643 %}
6644 ins_pipe(ialu_mem);
6645 %}
6646
6647 instruct prefetchrNTA( memory mem ) %{
6648 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6649 match(PrefetchRead mem);
6650 ins_cost(100);
6651
6652 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6653 ins_encode %{
6654 __ prefetchnta($mem$$Address);
6655 %}
6656 ins_pipe(ialu_mem);
6657 %}
6658
6659 instruct prefetchrT0( memory mem ) %{
6660 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6661 match(PrefetchRead mem);
6662 ins_cost(100);
6663
6664 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6665 ins_encode %{
6666 __ prefetcht0($mem$$Address);
6667 %}
6668 ins_pipe(ialu_mem);
6669 %}
6670
6671 instruct prefetchrT2( memory mem ) %{
6672 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6673 match(PrefetchRead mem);
6674 ins_cost(100);
6675
6676 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6677 ins_encode %{
6678 __ prefetcht2($mem$$Address);
6679 %}
6680 ins_pipe(ialu_mem);
6681 %}
6682
6683 instruct prefetchw0( memory mem ) %{
6684 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6685 match(PrefetchWrite mem);
6686 ins_cost(0);
6687 size(0);
6688 format %{ "Prefetch (non-SSE is empty encoding)" %}
6689 ins_encode();
6690 ins_pipe(empty);
6691 %}
6692
6693 instruct prefetchw( memory mem ) %{
6694 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6695 match( PrefetchWrite mem );
6696 ins_cost(100);
6697
6698 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6699 ins_encode %{
6700 __ prefetchw($mem$$Address);
6701 %}
6702 ins_pipe(ialu_mem);
6703 %}
6704
6705 instruct prefetchwNTA( memory mem ) %{
6706 predicate(UseSSE>=1);
6707 match(PrefetchWrite mem);
6708 ins_cost(100);
6709
6710 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6711 ins_encode %{
6712 __ prefetchnta($mem$$Address);
6713 %}
6714 ins_pipe(ialu_mem);
6715 %}
6716
6717 // Prefetch instructions for allocation.
6718
6719 instruct prefetchAlloc0( memory mem ) %{
6720 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6721 match(PrefetchAllocation mem);
6722 ins_cost(0);
6723 size(0);
6724 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6725 ins_encode();
6726 ins_pipe(empty);
6727 %}
6728
6729 instruct prefetchAlloc( memory mem ) %{
6730 predicate(AllocatePrefetchInstr==3);
6731 match( PrefetchAllocation mem );
6732 ins_cost(100);
6733
6734 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6735 ins_encode %{
6736 __ prefetchw($mem$$Address);
6737 %}
6738 ins_pipe(ialu_mem);
6739 %}
6740
6741 instruct prefetchAllocNTA( memory mem ) %{
6742 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6743 match(PrefetchAllocation mem);
6744 ins_cost(100);
6745
6746 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6747 ins_encode %{
6748 __ prefetchnta($mem$$Address);
6749 %}
6750 ins_pipe(ialu_mem);
6751 %}
6752
6753 instruct prefetchAllocT0( memory mem ) %{
6754 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6755 match(PrefetchAllocation mem);
6756 ins_cost(100);
6757
6758 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6759 ins_encode %{
6760 __ prefetcht0($mem$$Address);
6761 %}
6762 ins_pipe(ialu_mem);
6763 %}
6764
6765 instruct prefetchAllocT2( memory mem ) %{
6766 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6767 match(PrefetchAllocation mem);
6768 ins_cost(100);
6769
6770 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6771 ins_encode %{
6772 __ prefetcht2($mem$$Address);
6773 %}
6774 ins_pipe(ialu_mem);
6775 %}
6776
6777 //----------Store Instructions-------------------------------------------------
6778
6779 // Store Byte
6780 instruct storeB(memory mem, xRegI src) %{
6781 match(Set mem (StoreB mem src));
6782
6783 ins_cost(125);
6784 format %{ "MOV8 $mem,$src" %}
6785 opcode(0x88);
6786 ins_encode( OpcP, RegMem( src, mem ) );
6787 ins_pipe( ialu_mem_reg );
6788 %}
6789
6790 // Store Char/Short
6791 instruct storeC(memory mem, rRegI src) %{
6792 match(Set mem (StoreC mem src));
6793
6794 ins_cost(125);
6795 format %{ "MOV16 $mem,$src" %}
6796 opcode(0x89, 0x66);
6797 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6798 ins_pipe( ialu_mem_reg );
6799 %}
6800
6801 // Store Integer
6802 instruct storeI(memory mem, rRegI src) %{
6803 match(Set mem (StoreI mem src));
6804
6805 ins_cost(125);
6806 format %{ "MOV $mem,$src" %}
6807 opcode(0x89);
6808 ins_encode( OpcP, RegMem( src, mem ) );
6809 ins_pipe( ialu_mem_reg );
6810 %}
6811
6812 // Store Long
6813 instruct storeL(long_memory mem, eRegL src) %{
6814 predicate(!((StoreLNode*)n)->require_atomic_access());
6815 match(Set mem (StoreL mem src));
6816
6817 ins_cost(200);
6818 format %{ "MOV $mem,$src.lo\n\t"
6819 "MOV $mem+4,$src.hi" %}
6820 opcode(0x89, 0x89);
6821 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6822 ins_pipe( ialu_mem_long_reg );
6823 %}
6824
6825 // Store Long to Integer
6826 instruct storeL2I(memory mem, eRegL src) %{
6827 match(Set mem (StoreI mem (ConvL2I src)));
6828
6829 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6830 ins_encode %{
6831 __ movl($mem$$Address, $src$$Register);
6832 %}
6833 ins_pipe(ialu_mem_reg);
6834 %}
6835
6836 // Volatile Store Long. Must be atomic, so move it into
6837 // the FP TOS and then do a 64-bit FIST. Has to probe the
6838 // target address before the store (for null-ptr checks)
6839 // so the memory operand is used twice in the encoding.
6840 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6841 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6842 match(Set mem (StoreL mem src));
6843 effect( KILL cr );
6844 ins_cost(400);
6845 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6846 "FILD $src\n\t"
6847 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6848 opcode(0x3B);
6849 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6850 ins_pipe( fpu_reg_mem );
6851 %}
6852
6853 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6854 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6855 match(Set mem (StoreL mem src));
6856 effect( TEMP tmp, KILL cr );
6857 ins_cost(380);
6858 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6859 "MOVSD $tmp,$src\n\t"
6860 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6861 ins_encode %{
6862 __ cmpl(rax, $mem$$Address);
6863 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6864 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6865 %}
6866 ins_pipe( pipe_slow );
6867 %}
6868
6869 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6870 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6871 match(Set mem (StoreL mem src));
6872 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6873 ins_cost(360);
6874 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6875 "MOVD $tmp,$src.lo\n\t"
6876 "MOVD $tmp2,$src.hi\n\t"
6877 "PUNPCKLDQ $tmp,$tmp2\n\t"
6878 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6879 ins_encode %{
6880 __ cmpl(rax, $mem$$Address);
6881 __ movdl($tmp$$XMMRegister, $src$$Register);
6882 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6883 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6884 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6885 %}
6886 ins_pipe( pipe_slow );
6887 %}
6888
6889 // Store Pointer; for storing unknown oops and raw pointers
6890 instruct storeP(memory mem, anyRegP src) %{
6891 match(Set mem (StoreP mem src));
6892
6893 ins_cost(125);
6894 format %{ "MOV $mem,$src" %}
6895 opcode(0x89);
6896 ins_encode( OpcP, RegMem( src, mem ) );
6897 ins_pipe( ialu_mem_reg );
6898 %}
6899
6900 // Store Integer Immediate
6901 instruct storeImmI(memory mem, immI src) %{
6902 match(Set mem (StoreI mem src));
6903
6904 ins_cost(150);
6905 format %{ "MOV $mem,$src" %}
6906 opcode(0xC7); /* C7 /0 */
6907 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6908 ins_pipe( ialu_mem_imm );
6909 %}
6910
6911 // Store Short/Char Immediate
6912 instruct storeImmI16(memory mem, immI16 src) %{
6913 predicate(UseStoreImmI16);
6914 match(Set mem (StoreC mem src));
6915
6916 ins_cost(150);
6917 format %{ "MOV16 $mem,$src" %}
6918 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6919 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6920 ins_pipe( ialu_mem_imm );
6921 %}
6922
6923 // Store Pointer Immediate; null pointers or constant oops that do not
6924 // need card-mark barriers.
6925 instruct storeImmP(memory mem, immP src) %{
6926 match(Set mem (StoreP mem src));
6927
6928 ins_cost(150);
6929 format %{ "MOV $mem,$src" %}
6930 opcode(0xC7); /* C7 /0 */
6931 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6932 ins_pipe( ialu_mem_imm );
6933 %}
6934
6935 // Store Byte Immediate
6936 instruct storeImmB(memory mem, immI8 src) %{
6937 match(Set mem (StoreB mem src));
6938
6939 ins_cost(150);
6940 format %{ "MOV8 $mem,$src" %}
6941 opcode(0xC6); /* C6 /0 */
6942 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6943 ins_pipe( ialu_mem_imm );
6944 %}
6945
6946 // Store CMS card-mark Immediate
6947 instruct storeImmCM(memory mem, immI8 src) %{
6948 match(Set mem (StoreCM mem src));
6949
6950 ins_cost(150);
6951 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6952 opcode(0xC6); /* C6 /0 */
6953 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6954 ins_pipe( ialu_mem_imm );
6955 %}
6956
6957 // Store Double
6958 instruct storeDPR( memory mem, regDPR1 src) %{
6959 predicate(UseSSE<=1);
6960 match(Set mem (StoreD mem src));
6961
6962 ins_cost(100);
6963 format %{ "FST_D $mem,$src" %}
6964 opcode(0xDD); /* DD /2 */
6965 ins_encode( enc_FPR_store(mem,src) );
6966 ins_pipe( fpu_mem_reg );
6967 %}
6968
6969 // Store double does rounding on x86
6970 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6971 predicate(UseSSE<=1);
6972 match(Set mem (StoreD mem (RoundDouble src)));
6973
6974 ins_cost(100);
6975 format %{ "FST_D $mem,$src\t# round" %}
6976 opcode(0xDD); /* DD /2 */
6977 ins_encode( enc_FPR_store(mem,src) );
6978 ins_pipe( fpu_mem_reg );
6979 %}
6980
6981 // Store XMM register to memory (double-precision floating points)
6982 // MOVSD instruction
6983 instruct storeD(memory mem, regD src) %{
6984 predicate(UseSSE>=2);
6985 match(Set mem (StoreD mem src));
6986 ins_cost(95);
6987 format %{ "MOVSD $mem,$src" %}
6988 ins_encode %{
6989 __ movdbl($mem$$Address, $src$$XMMRegister);
6990 %}
6991 ins_pipe( pipe_slow );
6992 %}
6993
6994 // Store XMM register to memory (single-precision floating point)
6995 // MOVSS instruction
6996 instruct storeF(memory mem, regF src) %{
6997 predicate(UseSSE>=1);
6998 match(Set mem (StoreF mem src));
6999 ins_cost(95);
7000 format %{ "MOVSS $mem,$src" %}
7001 ins_encode %{
7002 __ movflt($mem$$Address, $src$$XMMRegister);
7003 %}
7004 ins_pipe( pipe_slow );
7005 %}
7006
7007 // Store Float
7008 instruct storeFPR( memory mem, regFPR1 src) %{
7009 predicate(UseSSE==0);
7010 match(Set mem (StoreF mem src));
7011
7012 ins_cost(100);
7013 format %{ "FST_S $mem,$src" %}
7014 opcode(0xD9); /* D9 /2 */
7015 ins_encode( enc_FPR_store(mem,src) );
7016 ins_pipe( fpu_mem_reg );
7017 %}
7018
7019 // Store Float does rounding on x86
7020 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7021 predicate(UseSSE==0);
7022 match(Set mem (StoreF mem (RoundFloat src)));
7023
7024 ins_cost(100);
7025 format %{ "FST_S $mem,$src\t# round" %}
7026 opcode(0xD9); /* D9 /2 */
7027 ins_encode( enc_FPR_store(mem,src) );
7028 ins_pipe( fpu_mem_reg );
7029 %}
7030
7031 // Store Float does rounding on x86
7032 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7033 predicate(UseSSE<=1);
7034 match(Set mem (StoreF mem (ConvD2F src)));
7035
7036 ins_cost(100);
7037 format %{ "FST_S $mem,$src\t# D-round" %}
7038 opcode(0xD9); /* D9 /2 */
7039 ins_encode( enc_FPR_store(mem,src) );
7040 ins_pipe( fpu_mem_reg );
7041 %}
7042
7043 // Store immediate Float value (it is faster than store from FPU register)
7044 // The instruction usage is guarded by predicate in operand immFPR().
7045 instruct storeFPR_imm( memory mem, immFPR src) %{
7046 match(Set mem (StoreF mem src));
7047
7048 ins_cost(50);
7049 format %{ "MOV $mem,$src\t# store float" %}
7050 opcode(0xC7); /* C7 /0 */
7051 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7052 ins_pipe( ialu_mem_imm );
7053 %}
7054
7055 // Store immediate Float value (it is faster than store from XMM register)
7056 // The instruction usage is guarded by predicate in operand immF().
7057 instruct storeF_imm( memory mem, immF src) %{
7058 match(Set mem (StoreF mem src));
7059
7060 ins_cost(50);
7061 format %{ "MOV $mem,$src\t# store float" %}
7062 opcode(0xC7); /* C7 /0 */
7063 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7064 ins_pipe( ialu_mem_imm );
7065 %}
7066
7067 // Store Integer to stack slot
7068 instruct storeSSI(stackSlotI dst, rRegI src) %{
7069 match(Set dst src);
7070
7071 ins_cost(100);
7072 format %{ "MOV $dst,$src" %}
7073 opcode(0x89);
7074 ins_encode( OpcPRegSS( dst, src ) );
7075 ins_pipe( ialu_mem_reg );
7076 %}
7077
7078 // Store Integer to stack slot
7079 instruct storeSSP(stackSlotP dst, eRegP src) %{
7080 match(Set dst src);
7081
7082 ins_cost(100);
7083 format %{ "MOV $dst,$src" %}
7084 opcode(0x89);
7085 ins_encode( OpcPRegSS( dst, src ) );
7086 ins_pipe( ialu_mem_reg );
7087 %}
7088
7089 // Store Long to stack slot
7090 instruct storeSSL(stackSlotL dst, eRegL src) %{
7091 match(Set dst src);
7092
7093 ins_cost(200);
7094 format %{ "MOV $dst,$src.lo\n\t"
7095 "MOV $dst+4,$src.hi" %}
7096 opcode(0x89, 0x89);
7097 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7098 ins_pipe( ialu_mem_long_reg );
7099 %}
7100
7101 //----------MemBar Instructions-----------------------------------------------
7102 // Memory barrier flavors
7103
7104 instruct membar_acquire() %{
7105 match(MemBarAcquire);
7106 ins_cost(400);
7107
7108 size(0);
7109 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7110 ins_encode();
7111 ins_pipe(empty);
7112 %}
7113
7114 instruct membar_acquire_lock() %{
7115 match(MemBarAcquireLock);
7116 ins_cost(0);
7117
7118 size(0);
7119 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7120 ins_encode( );
7121 ins_pipe(empty);
7122 %}
7123
7124 instruct membar_release() %{
7125 match(MemBarRelease);
7126 ins_cost(400);
7127
7128 size(0);
7129 format %{ "MEMBAR-release ! (empty encoding)" %}
7130 ins_encode( );
7131 ins_pipe(empty);
7132 %}
7133
7134 instruct membar_release_lock() %{
7135 match(MemBarReleaseLock);
7136 ins_cost(0);
7137
7138 size(0);
7139 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7140 ins_encode( );
7141 ins_pipe(empty);
7142 %}
7143
7144 instruct membar_volatile(eFlagsReg cr) %{
7145 match(MemBarVolatile);
7146 effect(KILL cr);
7147 ins_cost(400);
7148
7149 format %{
7150 $$template
7151 if (os::is_MP()) {
7152 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7153 } else {
7154 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7155 }
7156 %}
7157 ins_encode %{
7158 __ membar(Assembler::StoreLoad);
7159 %}
7160 ins_pipe(pipe_slow);
7161 %}
7162
7163 instruct unnecessary_membar_volatile() %{
7164 match(MemBarVolatile);
7165 predicate(Matcher::post_store_load_barrier(n));
7166 ins_cost(0);
7167
7168 size(0);
7169 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7170 ins_encode( );
7171 ins_pipe(empty);
7172 %}
7173
7174 instruct membar_storestore() %{
7175 match(MemBarStoreStore);
7176 ins_cost(0);
7177
7178 size(0);
7179 format %{ "MEMBAR-storestore (empty encoding)" %}
7180 ins_encode( );
7181 ins_pipe(empty);
7182 %}
7183
7184 //----------Move Instructions--------------------------------------------------
7185 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7186 match(Set dst (CastX2P src));
7187 format %{ "# X2P $dst, $src" %}
7188 ins_encode( /*empty encoding*/ );
7189 ins_cost(0);
7190 ins_pipe(empty);
7191 %}
7192
7193 instruct castP2X(rRegI dst, eRegP src ) %{
7194 match(Set dst (CastP2X src));
7195 ins_cost(50);
7196 format %{ "MOV $dst, $src\t# CastP2X" %}
7197 ins_encode( enc_Copy( dst, src) );
7198 ins_pipe( ialu_reg_reg );
7199 %}
7200
7201 //----------Conditional Move---------------------------------------------------
7202 // Conditional move
7203 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7204 predicate(!VM_Version::supports_cmov() );
7205 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7206 ins_cost(200);
7207 format %{ "J$cop,us skip\t# signed cmove\n\t"
7208 "MOV $dst,$src\n"
7209 "skip:" %}
7210 ins_encode %{
7211 Label Lskip;
7212 // Invert sense of branch from sense of CMOV
7213 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7214 __ movl($dst$$Register, $src$$Register);
7215 __ bind(Lskip);
7216 %}
7217 ins_pipe( pipe_cmov_reg );
7218 %}
7219
7220 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7221 predicate(!VM_Version::supports_cmov() );
7222 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7223 ins_cost(200);
7224 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7225 "MOV $dst,$src\n"
7226 "skip:" %}
7227 ins_encode %{
7228 Label Lskip;
7229 // Invert sense of branch from sense of CMOV
7230 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7231 __ movl($dst$$Register, $src$$Register);
7232 __ bind(Lskip);
7233 %}
7234 ins_pipe( pipe_cmov_reg );
7235 %}
7236
7237 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7238 predicate(VM_Version::supports_cmov() );
7239 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7240 ins_cost(200);
7241 format %{ "CMOV$cop $dst,$src" %}
7242 opcode(0x0F,0x40);
7243 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7244 ins_pipe( pipe_cmov_reg );
7245 %}
7246
7247 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7248 predicate(VM_Version::supports_cmov() );
7249 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7250 ins_cost(200);
7251 format %{ "CMOV$cop $dst,$src" %}
7252 opcode(0x0F,0x40);
7253 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7254 ins_pipe( pipe_cmov_reg );
7255 %}
7256
7257 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7258 predicate(VM_Version::supports_cmov() );
7259 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7260 ins_cost(200);
7261 expand %{
7262 cmovI_regU(cop, cr, dst, src);
7263 %}
7264 %}
7265
7266 // Conditional move
7267 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7268 predicate(VM_Version::supports_cmov() );
7269 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7270 ins_cost(250);
7271 format %{ "CMOV$cop $dst,$src" %}
7272 opcode(0x0F,0x40);
7273 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7274 ins_pipe( pipe_cmov_mem );
7275 %}
7276
7277 // Conditional move
7278 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7279 predicate(VM_Version::supports_cmov() );
7280 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7281 ins_cost(250);
7282 format %{ "CMOV$cop $dst,$src" %}
7283 opcode(0x0F,0x40);
7284 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7285 ins_pipe( pipe_cmov_mem );
7286 %}
7287
7288 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7289 predicate(VM_Version::supports_cmov() );
7290 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7291 ins_cost(250);
7292 expand %{
7293 cmovI_memU(cop, cr, dst, src);
7294 %}
7295 %}
7296
7297 // Conditional move
7298 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7299 predicate(VM_Version::supports_cmov() );
7300 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7301 ins_cost(200);
7302 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7303 opcode(0x0F,0x40);
7304 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7305 ins_pipe( pipe_cmov_reg );
7306 %}
7307
7308 // Conditional move (non-P6 version)
7309 // Note: a CMoveP is generated for stubs and native wrappers
7310 // regardless of whether we are on a P6, so we
7311 // emulate a cmov here
7312 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7313 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7314 ins_cost(300);
7315 format %{ "Jn$cop skip\n\t"
7316 "MOV $dst,$src\t# pointer\n"
7317 "skip:" %}
7318 opcode(0x8b);
7319 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7320 ins_pipe( pipe_cmov_reg );
7321 %}
7322
7323 // Conditional move
7324 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7325 predicate(VM_Version::supports_cmov() );
7326 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7327 ins_cost(200);
7328 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7329 opcode(0x0F,0x40);
7330 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7331 ins_pipe( pipe_cmov_reg );
7332 %}
7333
7334 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7335 predicate(VM_Version::supports_cmov() );
7336 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7337 ins_cost(200);
7338 expand %{
7339 cmovP_regU(cop, cr, dst, src);
7340 %}
7341 %}
7342
7343 // DISABLED: Requires the ADLC to emit a bottom_type call that
7344 // correctly meets the two pointer arguments; one is an incoming
7345 // register but the other is a memory operand. ALSO appears to
7346 // be buggy with implicit null checks.
7347 //
7348 //// Conditional move
7349 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7350 // predicate(VM_Version::supports_cmov() );
7351 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7352 // ins_cost(250);
7353 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7354 // opcode(0x0F,0x40);
7355 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7356 // ins_pipe( pipe_cmov_mem );
7357 //%}
7358 //
7359 //// Conditional move
7360 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7361 // predicate(VM_Version::supports_cmov() );
7362 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7363 // ins_cost(250);
7364 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7365 // opcode(0x0F,0x40);
7366 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7367 // ins_pipe( pipe_cmov_mem );
7368 //%}
7369
7370 // Conditional move
7371 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7372 predicate(UseSSE<=1);
7373 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7374 ins_cost(200);
7375 format %{ "FCMOV$cop $dst,$src\t# double" %}
7376 opcode(0xDA);
7377 ins_encode( enc_cmov_dpr(cop,src) );
7378 ins_pipe( pipe_cmovDPR_reg );
7379 %}
7380
7381 // Conditional move
7382 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7383 predicate(UseSSE==0);
7384 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7385 ins_cost(200);
7386 format %{ "FCMOV$cop $dst,$src\t# float" %}
7387 opcode(0xDA);
7388 ins_encode( enc_cmov_dpr(cop,src) );
7389 ins_pipe( pipe_cmovDPR_reg );
7390 %}
7391
7392 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7393 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7394 predicate(UseSSE<=1);
7395 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7396 ins_cost(200);
7397 format %{ "Jn$cop skip\n\t"
7398 "MOV $dst,$src\t# double\n"
7399 "skip:" %}
7400 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7401 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7402 ins_pipe( pipe_cmovDPR_reg );
7403 %}
7404
7405 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7406 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7407 predicate(UseSSE==0);
7408 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7409 ins_cost(200);
7410 format %{ "Jn$cop skip\n\t"
7411 "MOV $dst,$src\t# float\n"
7412 "skip:" %}
7413 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7414 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7415 ins_pipe( pipe_cmovDPR_reg );
7416 %}
7417
7418 // No CMOVE with SSE/SSE2
7419 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7420 predicate (UseSSE>=1);
7421 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7422 ins_cost(200);
7423 format %{ "Jn$cop skip\n\t"
7424 "MOVSS $dst,$src\t# float\n"
7425 "skip:" %}
7426 ins_encode %{
7427 Label skip;
7428 // Invert sense of branch from sense of CMOV
7429 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7430 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7431 __ bind(skip);
7432 %}
7433 ins_pipe( pipe_slow );
7434 %}
7435
7436 // No CMOVE with SSE/SSE2
7437 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7438 predicate (UseSSE>=2);
7439 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7440 ins_cost(200);
7441 format %{ "Jn$cop skip\n\t"
7442 "MOVSD $dst,$src\t# float\n"
7443 "skip:" %}
7444 ins_encode %{
7445 Label skip;
7446 // Invert sense of branch from sense of CMOV
7447 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7448 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7449 __ bind(skip);
7450 %}
7451 ins_pipe( pipe_slow );
7452 %}
7453
7454 // unsigned version
7455 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7456 predicate (UseSSE>=1);
7457 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7458 ins_cost(200);
7459 format %{ "Jn$cop skip\n\t"
7460 "MOVSS $dst,$src\t# float\n"
7461 "skip:" %}
7462 ins_encode %{
7463 Label skip;
7464 // Invert sense of branch from sense of CMOV
7465 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7466 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7467 __ bind(skip);
7468 %}
7469 ins_pipe( pipe_slow );
7470 %}
7471
7472 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7473 predicate (UseSSE>=1);
7474 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7475 ins_cost(200);
7476 expand %{
7477 fcmovF_regU(cop, cr, dst, src);
7478 %}
7479 %}
7480
7481 // unsigned version
7482 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7483 predicate (UseSSE>=2);
7484 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7485 ins_cost(200);
7486 format %{ "Jn$cop skip\n\t"
7487 "MOVSD $dst,$src\t# float\n"
7488 "skip:" %}
7489 ins_encode %{
7490 Label skip;
7491 // Invert sense of branch from sense of CMOV
7492 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7493 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7494 __ bind(skip);
7495 %}
7496 ins_pipe( pipe_slow );
7497 %}
7498
7499 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7500 predicate (UseSSE>=2);
7501 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7502 ins_cost(200);
7503 expand %{
7504 fcmovD_regU(cop, cr, dst, src);
7505 %}
7506 %}
7507
7508 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7509 predicate(VM_Version::supports_cmov() );
7510 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7511 ins_cost(200);
7512 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7513 "CMOV$cop $dst.hi,$src.hi" %}
7514 opcode(0x0F,0x40);
7515 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7516 ins_pipe( pipe_cmov_reg_long );
7517 %}
7518
7519 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7520 predicate(VM_Version::supports_cmov() );
7521 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7522 ins_cost(200);
7523 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7524 "CMOV$cop $dst.hi,$src.hi" %}
7525 opcode(0x0F,0x40);
7526 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7527 ins_pipe( pipe_cmov_reg_long );
7528 %}
7529
7530 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7531 predicate(VM_Version::supports_cmov() );
7532 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7533 ins_cost(200);
7534 expand %{
7535 cmovL_regU(cop, cr, dst, src);
7536 %}
7537 %}
7538
7539 //----------Arithmetic Instructions--------------------------------------------
7540 //----------Addition Instructions----------------------------------------------
7541 // Integer Addition Instructions
7542 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7543 match(Set dst (AddI dst src));
7544 effect(KILL cr);
7545
7546 size(2);
7547 format %{ "ADD $dst,$src" %}
7548 opcode(0x03);
7549 ins_encode( OpcP, RegReg( dst, src) );
7550 ins_pipe( ialu_reg_reg );
7551 %}
7552
7553 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7554 match(Set dst (AddI dst src));
7555 effect(KILL cr);
7556
7557 format %{ "ADD $dst,$src" %}
7558 opcode(0x81, 0x00); /* /0 id */
7559 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7560 ins_pipe( ialu_reg );
7561 %}
7562
7563 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7564 predicate(UseIncDec);
7565 match(Set dst (AddI dst src));
7566 effect(KILL cr);
7567
7568 size(1);
7569 format %{ "INC $dst" %}
7570 opcode(0x40); /* */
7571 ins_encode( Opc_plus( primary, dst ) );
7572 ins_pipe( ialu_reg );
7573 %}
7574
7575 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7576 match(Set dst (AddI src0 src1));
7577 ins_cost(110);
7578
7579 format %{ "LEA $dst,[$src0 + $src1]" %}
7580 opcode(0x8D); /* 0x8D /r */
7581 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7582 ins_pipe( ialu_reg_reg );
7583 %}
7584
7585 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7586 match(Set dst (AddP src0 src1));
7587 ins_cost(110);
7588
7589 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7590 opcode(0x8D); /* 0x8D /r */
7591 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7592 ins_pipe( ialu_reg_reg );
7593 %}
7594
7595 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7596 predicate(UseIncDec);
7597 match(Set dst (AddI dst src));
7598 effect(KILL cr);
7599
7600 size(1);
7601 format %{ "DEC $dst" %}
7602 opcode(0x48); /* */
7603 ins_encode( Opc_plus( primary, dst ) );
7604 ins_pipe( ialu_reg );
7605 %}
7606
7607 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7608 match(Set dst (AddP dst src));
7609 effect(KILL cr);
7610
7611 size(2);
7612 format %{ "ADD $dst,$src" %}
7613 opcode(0x03);
7614 ins_encode( OpcP, RegReg( dst, src) );
7615 ins_pipe( ialu_reg_reg );
7616 %}
7617
7618 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7619 match(Set dst (AddP dst src));
7620 effect(KILL cr);
7621
7622 format %{ "ADD $dst,$src" %}
7623 opcode(0x81,0x00); /* Opcode 81 /0 id */
7624 // ins_encode( RegImm( dst, src) );
7625 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7626 ins_pipe( ialu_reg );
7627 %}
7628
7629 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7630 match(Set dst (AddI dst (LoadI src)));
7631 effect(KILL cr);
7632
7633 ins_cost(125);
7634 format %{ "ADD $dst,$src" %}
7635 opcode(0x03);
7636 ins_encode( OpcP, RegMem( dst, src) );
7637 ins_pipe( ialu_reg_mem );
7638 %}
7639
7640 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7641 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7642 effect(KILL cr);
7643
7644 ins_cost(150);
7645 format %{ "ADD $dst,$src" %}
7646 opcode(0x01); /* Opcode 01 /r */
7647 ins_encode( OpcP, RegMem( src, dst ) );
7648 ins_pipe( ialu_mem_reg );
7649 %}
7650
7651 // Add Memory with Immediate
7652 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7653 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7654 effect(KILL cr);
7655
7656 ins_cost(125);
7657 format %{ "ADD $dst,$src" %}
7658 opcode(0x81); /* Opcode 81 /0 id */
7659 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7660 ins_pipe( ialu_mem_imm );
7661 %}
7662
7663 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7664 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7665 effect(KILL cr);
7666
7667 ins_cost(125);
7668 format %{ "INC $dst" %}
7669 opcode(0xFF); /* Opcode FF /0 */
7670 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7671 ins_pipe( ialu_mem_imm );
7672 %}
7673
7674 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7675 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7676 effect(KILL cr);
7677
7678 ins_cost(125);
7679 format %{ "DEC $dst" %}
7680 opcode(0xFF); /* Opcode FF /1 */
7681 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7682 ins_pipe( ialu_mem_imm );
7683 %}
7684
7685
7686 instruct checkCastPP( eRegP dst ) %{
7687 match(Set dst (CheckCastPP dst));
7688
7689 size(0);
7690 format %{ "#checkcastPP of $dst" %}
7691 ins_encode( /*empty encoding*/ );
7692 ins_pipe( empty );
7693 %}
7694
7695 instruct castPP( eRegP dst ) %{
7696 match(Set dst (CastPP dst));
7697 format %{ "#castPP of $dst" %}
7698 ins_encode( /*empty encoding*/ );
7699 ins_pipe( empty );
7700 %}
7701
7702 instruct castII( rRegI dst ) %{
7703 match(Set dst (CastII dst));
7704 format %{ "#castII of $dst" %}
7705 ins_encode( /*empty encoding*/ );
7706 ins_cost(0);
7707 ins_pipe( empty );
7708 %}
7709
7710
7711 // Load-locked - same as a regular pointer load when used with compare-swap
7712 instruct loadPLocked(eRegP dst, memory mem) %{
7713 match(Set dst (LoadPLocked mem));
7714
7715 ins_cost(125);
7716 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7717 opcode(0x8B);
7718 ins_encode( OpcP, RegMem(dst,mem));
7719 ins_pipe( ialu_reg_mem );
7720 %}
7721
7722 // Conditional-store of the updated heap-top.
7723 // Used during allocation of the shared heap.
7724 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7725 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7726 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7727 // EAX is killed if there is contention, but then it's also unused.
7728 // In the common case of no contention, EAX holds the new oop address.
7729 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7730 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7731 ins_pipe( pipe_cmpxchg );
7732 %}
7733
7734 // Conditional-store of an int value.
7735 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7736 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7737 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7738 effect(KILL oldval);
7739 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7740 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7741 ins_pipe( pipe_cmpxchg );
7742 %}
7743
7744 // Conditional-store of a long value.
7745 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7746 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7747 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7748 effect(KILL oldval);
7749 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7750 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7751 "XCHG EBX,ECX"
7752 %}
7753 ins_encode %{
7754 // Note: we need to swap rbx, and rcx before and after the
7755 // cmpxchg8 instruction because the instruction uses
7756 // rcx as the high order word of the new value to store but
7757 // our register encoding uses rbx.
7758 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7759 if( os::is_MP() )
7760 __ lock();
7761 __ cmpxchg8($mem$$Address);
7762 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7763 %}
7764 ins_pipe( pipe_cmpxchg );
7765 %}
7766
7767 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7768
7769 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7770 predicate(VM_Version::supports_cx8());
7771 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7772 effect(KILL cr, KILL oldval);
7773 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7774 "MOV $res,0\n\t"
7775 "JNE,s fail\n\t"
7776 "MOV $res,1\n"
7777 "fail:" %}
7778 ins_encode( enc_cmpxchg8(mem_ptr),
7779 enc_flags_ne_to_boolean(res) );
7780 ins_pipe( pipe_cmpxchg );
7781 %}
7782
7783 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7784 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7785 effect(KILL cr, KILL oldval);
7786 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7787 "MOV $res,0\n\t"
7788 "JNE,s fail\n\t"
7789 "MOV $res,1\n"
7790 "fail:" %}
7791 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7792 ins_pipe( pipe_cmpxchg );
7793 %}
7794
7795 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7796 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7797 effect(KILL cr, KILL oldval);
7798 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7799 "MOV $res,0\n\t"
7800 "JNE,s fail\n\t"
7801 "MOV $res,1\n"
7802 "fail:" %}
7803 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7804 ins_pipe( pipe_cmpxchg );
7805 %}
7806
7807 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7808 predicate(n->as_LoadStore()->result_not_used());
7809 match(Set dummy (GetAndAddI mem add));
7810 effect(KILL cr);
7811 format %{ "ADDL [$mem],$add" %}
7812 ins_encode %{
7813 if (os::is_MP()) { __ lock(); }
7814 __ addl($mem$$Address, $add$$constant);
7815 %}
7816 ins_pipe( pipe_cmpxchg );
7817 %}
7818
7819 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7820 match(Set newval (GetAndAddI mem newval));
7821 effect(KILL cr);
7822 format %{ "XADDL [$mem],$newval" %}
7823 ins_encode %{
7824 if (os::is_MP()) { __ lock(); }
7825 __ xaddl($mem$$Address, $newval$$Register);
7826 %}
7827 ins_pipe( pipe_cmpxchg );
7828 %}
7829
7830 instruct xchgI( memory mem, rRegI newval) %{
7831 match(Set newval (GetAndSetI mem newval));
7832 format %{ "XCHGL $newval,[$mem]" %}
7833 ins_encode %{
7834 __ xchgl($newval$$Register, $mem$$Address);
7835 %}
7836 ins_pipe( pipe_cmpxchg );
7837 %}
7838
7839 instruct xchgP( memory mem, pRegP newval) %{
7840 match(Set newval (GetAndSetP mem newval));
7841 format %{ "XCHGL $newval,[$mem]" %}
7842 ins_encode %{
7843 __ xchgl($newval$$Register, $mem$$Address);
7844 %}
7845 ins_pipe( pipe_cmpxchg );
7846 %}
7847
7848 //----------Subtraction Instructions-------------------------------------------
7849 // Integer Subtraction Instructions
7850 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7851 match(Set dst (SubI dst src));
7852 effect(KILL cr);
7853
7854 size(2);
7855 format %{ "SUB $dst,$src" %}
7856 opcode(0x2B);
7857 ins_encode( OpcP, RegReg( dst, src) );
7858 ins_pipe( ialu_reg_reg );
7859 %}
7860
7861 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7862 match(Set dst (SubI dst src));
7863 effect(KILL cr);
7864
7865 format %{ "SUB $dst,$src" %}
7866 opcode(0x81,0x05); /* Opcode 81 /5 */
7867 // ins_encode( RegImm( dst, src) );
7868 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7869 ins_pipe( ialu_reg );
7870 %}
7871
7872 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7873 match(Set dst (SubI dst (LoadI src)));
7874 effect(KILL cr);
7875
7876 ins_cost(125);
7877 format %{ "SUB $dst,$src" %}
7878 opcode(0x2B);
7879 ins_encode( OpcP, RegMem( dst, src) );
7880 ins_pipe( ialu_reg_mem );
7881 %}
7882
7883 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7884 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7885 effect(KILL cr);
7886
7887 ins_cost(150);
7888 format %{ "SUB $dst,$src" %}
7889 opcode(0x29); /* Opcode 29 /r */
7890 ins_encode( OpcP, RegMem( src, dst ) );
7891 ins_pipe( ialu_mem_reg );
7892 %}
7893
7894 // Subtract from a pointer
7895 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7896 match(Set dst (AddP dst (SubI zero src)));
7897 effect(KILL cr);
7898
7899 size(2);
7900 format %{ "SUB $dst,$src" %}
7901 opcode(0x2B);
7902 ins_encode( OpcP, RegReg( dst, src) );
7903 ins_pipe( ialu_reg_reg );
7904 %}
7905
7906 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7907 match(Set dst (SubI zero dst));
7908 effect(KILL cr);
7909
7910 size(2);
7911 format %{ "NEG $dst" %}
7912 opcode(0xF7,0x03); // Opcode F7 /3
7913 ins_encode( OpcP, RegOpc( dst ) );
7914 ins_pipe( ialu_reg );
7915 %}
7916
7917
7918 //----------Multiplication/Division Instructions-------------------------------
7919 // Integer Multiplication Instructions
7920 // Multiply Register
7921 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7922 match(Set dst (MulI dst src));
7923 effect(KILL cr);
7924
7925 size(3);
7926 ins_cost(300);
7927 format %{ "IMUL $dst,$src" %}
7928 opcode(0xAF, 0x0F);
7929 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7930 ins_pipe( ialu_reg_reg_alu0 );
7931 %}
7932
7933 // Multiply 32-bit Immediate
7934 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7935 match(Set dst (MulI src imm));
7936 effect(KILL cr);
7937
7938 ins_cost(300);
7939 format %{ "IMUL $dst,$src,$imm" %}
7940 opcode(0x69); /* 69 /r id */
7941 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7942 ins_pipe( ialu_reg_reg_alu0 );
7943 %}
7944
7945 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7946 match(Set dst src);
7947 effect(KILL cr);
7948
7949 // Note that this is artificially increased to make it more expensive than loadConL
7950 ins_cost(250);
7951 format %{ "MOV EAX,$src\t// low word only" %}
7952 opcode(0xB8);
7953 ins_encode( LdImmL_Lo(dst, src) );
7954 ins_pipe( ialu_reg_fat );
7955 %}
7956
7957 // Multiply by 32-bit Immediate, taking the shifted high order results
7958 // (special case for shift by 32)
7959 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7960 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7961 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7962 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7963 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7964 effect(USE src1, KILL cr);
7965
7966 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7967 ins_cost(0*100 + 1*400 - 150);
7968 format %{ "IMUL EDX:EAX,$src1" %}
7969 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7970 ins_pipe( pipe_slow );
7971 %}
7972
7973 // Multiply by 32-bit Immediate, taking the shifted high order results
7974 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7975 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7976 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7977 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7978 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7979 effect(USE src1, KILL cr);
7980
7981 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7982 ins_cost(1*100 + 1*400 - 150);
7983 format %{ "IMUL EDX:EAX,$src1\n\t"
7984 "SAR EDX,$cnt-32" %}
7985 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7986 ins_pipe( pipe_slow );
7987 %}
7988
7989 // Multiply Memory 32-bit Immediate
7990 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7991 match(Set dst (MulI (LoadI src) imm));
7992 effect(KILL cr);
7993
7994 ins_cost(300);
7995 format %{ "IMUL $dst,$src,$imm" %}
7996 opcode(0x69); /* 69 /r id */
7997 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7998 ins_pipe( ialu_reg_mem_alu0 );
7999 %}
8000
8001 // Multiply Memory
8002 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8003 match(Set dst (MulI dst (LoadI src)));
8004 effect(KILL cr);
8005
8006 ins_cost(350);
8007 format %{ "IMUL $dst,$src" %}
8008 opcode(0xAF, 0x0F);
8009 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8010 ins_pipe( ialu_reg_mem_alu0 );
8011 %}
8012
8013 // Multiply Register Int to Long
8014 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8015 // Basic Idea: long = (long)int * (long)int
8016 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8017 effect(DEF dst, USE src, USE src1, KILL flags);
8018
8019 ins_cost(300);
8020 format %{ "IMUL $dst,$src1" %}
8021
8022 ins_encode( long_int_multiply( dst, src1 ) );
8023 ins_pipe( ialu_reg_reg_alu0 );
8024 %}
8025
8026 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8027 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8028 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8029 effect(KILL flags);
8030
8031 ins_cost(300);
8032 format %{ "MUL $dst,$src1" %}
8033
8034 ins_encode( long_uint_multiply(dst, src1) );
8035 ins_pipe( ialu_reg_reg_alu0 );
8036 %}
8037
8038 // Multiply Register Long
8039 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8040 match(Set dst (MulL dst src));
8041 effect(KILL cr, TEMP tmp);
8042 ins_cost(4*100+3*400);
8043 // Basic idea: lo(result) = lo(x_lo * y_lo)
8044 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8045 format %{ "MOV $tmp,$src.lo\n\t"
8046 "IMUL $tmp,EDX\n\t"
8047 "MOV EDX,$src.hi\n\t"
8048 "IMUL EDX,EAX\n\t"
8049 "ADD $tmp,EDX\n\t"
8050 "MUL EDX:EAX,$src.lo\n\t"
8051 "ADD EDX,$tmp" %}
8052 ins_encode( long_multiply( dst, src, tmp ) );
8053 ins_pipe( pipe_slow );
8054 %}
8055
8056 // Multiply Register Long where the left operand's high 32 bits are zero
8057 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8058 predicate(is_operand_hi32_zero(n->in(1)));
8059 match(Set dst (MulL dst src));
8060 effect(KILL cr, TEMP tmp);
8061 ins_cost(2*100+2*400);
8062 // Basic idea: lo(result) = lo(x_lo * y_lo)
8063 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8064 format %{ "MOV $tmp,$src.hi\n\t"
8065 "IMUL $tmp,EAX\n\t"
8066 "MUL EDX:EAX,$src.lo\n\t"
8067 "ADD EDX,$tmp" %}
8068 ins_encode %{
8069 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8070 __ imull($tmp$$Register, rax);
8071 __ mull($src$$Register);
8072 __ addl(rdx, $tmp$$Register);
8073 %}
8074 ins_pipe( pipe_slow );
8075 %}
8076
8077 // Multiply Register Long where the right operand's high 32 bits are zero
8078 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8079 predicate(is_operand_hi32_zero(n->in(2)));
8080 match(Set dst (MulL dst src));
8081 effect(KILL cr, TEMP tmp);
8082 ins_cost(2*100+2*400);
8083 // Basic idea: lo(result) = lo(x_lo * y_lo)
8084 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8085 format %{ "MOV $tmp,$src.lo\n\t"
8086 "IMUL $tmp,EDX\n\t"
8087 "MUL EDX:EAX,$src.lo\n\t"
8088 "ADD EDX,$tmp" %}
8089 ins_encode %{
8090 __ movl($tmp$$Register, $src$$Register);
8091 __ imull($tmp$$Register, rdx);
8092 __ mull($src$$Register);
8093 __ addl(rdx, $tmp$$Register);
8094 %}
8095 ins_pipe( pipe_slow );
8096 %}
8097
8098 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8099 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8100 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8101 match(Set dst (MulL dst src));
8102 effect(KILL cr);
8103 ins_cost(1*400);
8104 // Basic idea: lo(result) = lo(x_lo * y_lo)
8105 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8106 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8107 ins_encode %{
8108 __ mull($src$$Register);
8109 %}
8110 ins_pipe( pipe_slow );
8111 %}
8112
8113 // Multiply Register Long by small constant
8114 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8115 match(Set dst (MulL dst src));
8116 effect(KILL cr, TEMP tmp);
8117 ins_cost(2*100+2*400);
8118 size(12);
8119 // Basic idea: lo(result) = lo(src * EAX)
8120 // hi(result) = hi(src * EAX) + lo(src * EDX)
8121 format %{ "IMUL $tmp,EDX,$src\n\t"
8122 "MOV EDX,$src\n\t"
8123 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8124 "ADD EDX,$tmp" %}
8125 ins_encode( long_multiply_con( dst, src, tmp ) );
8126 ins_pipe( pipe_slow );
8127 %}
8128
8129 // Integer DIV with Register
8130 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8131 match(Set rax (DivI rax div));
8132 effect(KILL rdx, KILL cr);
8133 size(26);
8134 ins_cost(30*100+10*100);
8135 format %{ "CMP EAX,0x80000000\n\t"
8136 "JNE,s normal\n\t"
8137 "XOR EDX,EDX\n\t"
8138 "CMP ECX,-1\n\t"
8139 "JE,s done\n"
8140 "normal: CDQ\n\t"
8141 "IDIV $div\n\t"
8142 "done:" %}
8143 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8144 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8145 ins_pipe( ialu_reg_reg_alu0 );
8146 %}
8147
8148 // Divide Register Long
8149 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8150 match(Set dst (DivL src1 src2));
8151 effect( KILL cr, KILL cx, KILL bx );
8152 ins_cost(10000);
8153 format %{ "PUSH $src1.hi\n\t"
8154 "PUSH $src1.lo\n\t"
8155 "PUSH $src2.hi\n\t"
8156 "PUSH $src2.lo\n\t"
8157 "CALL SharedRuntime::ldiv\n\t"
8158 "ADD ESP,16" %}
8159 ins_encode( long_div(src1,src2) );
8160 ins_pipe( pipe_slow );
8161 %}
8162
8163 // Integer DIVMOD with Register, both quotient and mod results
8164 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8165 match(DivModI rax div);
8166 effect(KILL cr);
8167 size(26);
8168 ins_cost(30*100+10*100);
8169 format %{ "CMP EAX,0x80000000\n\t"
8170 "JNE,s normal\n\t"
8171 "XOR EDX,EDX\n\t"
8172 "CMP ECX,-1\n\t"
8173 "JE,s done\n"
8174 "normal: CDQ\n\t"
8175 "IDIV $div\n\t"
8176 "done:" %}
8177 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8178 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8179 ins_pipe( pipe_slow );
8180 %}
8181
8182 // Integer MOD with Register
8183 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8184 match(Set rdx (ModI rax div));
8185 effect(KILL rax, KILL cr);
8186
8187 size(26);
8188 ins_cost(300);
8189 format %{ "CDQ\n\t"
8190 "IDIV $div" %}
8191 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8192 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8193 ins_pipe( ialu_reg_reg_alu0 );
8194 %}
8195
8196 // Remainder Register Long
8197 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8198 match(Set dst (ModL src1 src2));
8199 effect( KILL cr, KILL cx, KILL bx );
8200 ins_cost(10000);
8201 format %{ "PUSH $src1.hi\n\t"
8202 "PUSH $src1.lo\n\t"
8203 "PUSH $src2.hi\n\t"
8204 "PUSH $src2.lo\n\t"
8205 "CALL SharedRuntime::lrem\n\t"
8206 "ADD ESP,16" %}
8207 ins_encode( long_mod(src1,src2) );
8208 ins_pipe( pipe_slow );
8209 %}
8210
8211 // Divide Register Long (no special case since divisor != -1)
8212 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8213 match(Set dst (DivL dst imm));
8214 effect( TEMP tmp, TEMP tmp2, KILL cr );
8215 ins_cost(1000);
8216 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8217 "XOR $tmp2,$tmp2\n\t"
8218 "CMP $tmp,EDX\n\t"
8219 "JA,s fast\n\t"
8220 "MOV $tmp2,EAX\n\t"
8221 "MOV EAX,EDX\n\t"
8222 "MOV EDX,0\n\t"
8223 "JLE,s pos\n\t"
8224 "LNEG EAX : $tmp2\n\t"
8225 "DIV $tmp # unsigned division\n\t"
8226 "XCHG EAX,$tmp2\n\t"
8227 "DIV $tmp\n\t"
8228 "LNEG $tmp2 : EAX\n\t"
8229 "JMP,s done\n"
8230 "pos:\n\t"
8231 "DIV $tmp\n\t"
8232 "XCHG EAX,$tmp2\n"
8233 "fast:\n\t"
8234 "DIV $tmp\n"
8235 "done:\n\t"
8236 "MOV EDX,$tmp2\n\t"
8237 "NEG EDX:EAX # if $imm < 0" %}
8238 ins_encode %{
8239 int con = (int)$imm$$constant;
8240 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8241 int pcon = (con > 0) ? con : -con;
8242 Label Lfast, Lpos, Ldone;
8243
8244 __ movl($tmp$$Register, pcon);
8245 __ xorl($tmp2$$Register,$tmp2$$Register);
8246 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8247 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8248
8249 __ movl($tmp2$$Register, $dst$$Register); // save
8250 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8251 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8252 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8253
8254 // Negative dividend.
8255 // convert value to positive to use unsigned division
8256 __ lneg($dst$$Register, $tmp2$$Register);
8257 __ divl($tmp$$Register);
8258 __ xchgl($dst$$Register, $tmp2$$Register);
8259 __ divl($tmp$$Register);
8260 // revert result back to negative
8261 __ lneg($tmp2$$Register, $dst$$Register);
8262 __ jmpb(Ldone);
8263
8264 __ bind(Lpos);
8265 __ divl($tmp$$Register); // Use unsigned division
8266 __ xchgl($dst$$Register, $tmp2$$Register);
8267 // Fallthrow for final divide, tmp2 has 32 bit hi result
8268
8269 __ bind(Lfast);
8270 // fast path: src is positive
8271 __ divl($tmp$$Register); // Use unsigned division
8272
8273 __ bind(Ldone);
8274 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8275 if (con < 0) {
8276 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8277 }
8278 %}
8279 ins_pipe( pipe_slow );
8280 %}
8281
8282 // Remainder Register Long (remainder fit into 32 bits)
8283 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8284 match(Set dst (ModL dst imm));
8285 effect( TEMP tmp, TEMP tmp2, KILL cr );
8286 ins_cost(1000);
8287 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8288 "CMP $tmp,EDX\n\t"
8289 "JA,s fast\n\t"
8290 "MOV $tmp2,EAX\n\t"
8291 "MOV EAX,EDX\n\t"
8292 "MOV EDX,0\n\t"
8293 "JLE,s pos\n\t"
8294 "LNEG EAX : $tmp2\n\t"
8295 "DIV $tmp # unsigned division\n\t"
8296 "MOV EAX,$tmp2\n\t"
8297 "DIV $tmp\n\t"
8298 "NEG EDX\n\t"
8299 "JMP,s done\n"
8300 "pos:\n\t"
8301 "DIV $tmp\n\t"
8302 "MOV EAX,$tmp2\n"
8303 "fast:\n\t"
8304 "DIV $tmp\n"
8305 "done:\n\t"
8306 "MOV EAX,EDX\n\t"
8307 "SAR EDX,31\n\t" %}
8308 ins_encode %{
8309 int con = (int)$imm$$constant;
8310 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8311 int pcon = (con > 0) ? con : -con;
8312 Label Lfast, Lpos, Ldone;
8313
8314 __ movl($tmp$$Register, pcon);
8315 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8316 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8317
8318 __ movl($tmp2$$Register, $dst$$Register); // save
8319 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8320 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8321 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8322
8323 // Negative dividend.
8324 // convert value to positive to use unsigned division
8325 __ lneg($dst$$Register, $tmp2$$Register);
8326 __ divl($tmp$$Register);
8327 __ movl($dst$$Register, $tmp2$$Register);
8328 __ divl($tmp$$Register);
8329 // revert remainder back to negative
8330 __ negl(HIGH_FROM_LOW($dst$$Register));
8331 __ jmpb(Ldone);
8332
8333 __ bind(Lpos);
8334 __ divl($tmp$$Register);
8335 __ movl($dst$$Register, $tmp2$$Register);
8336
8337 __ bind(Lfast);
8338 // fast path: src is positive
8339 __ divl($tmp$$Register);
8340
8341 __ bind(Ldone);
8342 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8343 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8344
8345 %}
8346 ins_pipe( pipe_slow );
8347 %}
8348
8349 // Integer Shift Instructions
8350 // Shift Left by one
8351 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8352 match(Set dst (LShiftI dst shift));
8353 effect(KILL cr);
8354
8355 size(2);
8356 format %{ "SHL $dst,$shift" %}
8357 opcode(0xD1, 0x4); /* D1 /4 */
8358 ins_encode( OpcP, RegOpc( dst ) );
8359 ins_pipe( ialu_reg );
8360 %}
8361
8362 // Shift Left by 8-bit immediate
8363 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8364 match(Set dst (LShiftI dst shift));
8365 effect(KILL cr);
8366
8367 size(3);
8368 format %{ "SHL $dst,$shift" %}
8369 opcode(0xC1, 0x4); /* C1 /4 ib */
8370 ins_encode( RegOpcImm( dst, shift) );
8371 ins_pipe( ialu_reg );
8372 %}
8373
8374 // Shift Left by variable
8375 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8376 match(Set dst (LShiftI dst shift));
8377 effect(KILL cr);
8378
8379 size(2);
8380 format %{ "SHL $dst,$shift" %}
8381 opcode(0xD3, 0x4); /* D3 /4 */
8382 ins_encode( OpcP, RegOpc( dst ) );
8383 ins_pipe( ialu_reg_reg );
8384 %}
8385
8386 // Arithmetic shift right by one
8387 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8388 match(Set dst (RShiftI dst shift));
8389 effect(KILL cr);
8390
8391 size(2);
8392 format %{ "SAR $dst,$shift" %}
8393 opcode(0xD1, 0x7); /* D1 /7 */
8394 ins_encode( OpcP, RegOpc( dst ) );
8395 ins_pipe( ialu_reg );
8396 %}
8397
8398 // Arithmetic shift right by one
8399 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8400 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8401 effect(KILL cr);
8402 format %{ "SAR $dst,$shift" %}
8403 opcode(0xD1, 0x7); /* D1 /7 */
8404 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8405 ins_pipe( ialu_mem_imm );
8406 %}
8407
8408 // Arithmetic Shift Right by 8-bit immediate
8409 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8410 match(Set dst (RShiftI dst shift));
8411 effect(KILL cr);
8412
8413 size(3);
8414 format %{ "SAR $dst,$shift" %}
8415 opcode(0xC1, 0x7); /* C1 /7 ib */
8416 ins_encode( RegOpcImm( dst, shift ) );
8417 ins_pipe( ialu_mem_imm );
8418 %}
8419
8420 // Arithmetic Shift Right by 8-bit immediate
8421 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8422 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8423 effect(KILL cr);
8424
8425 format %{ "SAR $dst,$shift" %}
8426 opcode(0xC1, 0x7); /* C1 /7 ib */
8427 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8428 ins_pipe( ialu_mem_imm );
8429 %}
8430
8431 // Arithmetic Shift Right by variable
8432 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8433 match(Set dst (RShiftI dst shift));
8434 effect(KILL cr);
8435
8436 size(2);
8437 format %{ "SAR $dst,$shift" %}
8438 opcode(0xD3, 0x7); /* D3 /7 */
8439 ins_encode( OpcP, RegOpc( dst ) );
8440 ins_pipe( ialu_reg_reg );
8441 %}
8442
8443 // Logical shift right by one
8444 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8445 match(Set dst (URShiftI dst shift));
8446 effect(KILL cr);
8447
8448 size(2);
8449 format %{ "SHR $dst,$shift" %}
8450 opcode(0xD1, 0x5); /* D1 /5 */
8451 ins_encode( OpcP, RegOpc( dst ) );
8452 ins_pipe( ialu_reg );
8453 %}
8454
8455 // Logical Shift Right by 8-bit immediate
8456 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8457 match(Set dst (URShiftI dst shift));
8458 effect(KILL cr);
8459
8460 size(3);
8461 format %{ "SHR $dst,$shift" %}
8462 opcode(0xC1, 0x5); /* C1 /5 ib */
8463 ins_encode( RegOpcImm( dst, shift) );
8464 ins_pipe( ialu_reg );
8465 %}
8466
8467
8468 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8469 // This idiom is used by the compiler for the i2b bytecode.
8470 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8471 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8472
8473 size(3);
8474 format %{ "MOVSX $dst,$src :8" %}
8475 ins_encode %{
8476 __ movsbl($dst$$Register, $src$$Register);
8477 %}
8478 ins_pipe(ialu_reg_reg);
8479 %}
8480
8481 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8482 // This idiom is used by the compiler the i2s bytecode.
8483 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8484 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8485
8486 size(3);
8487 format %{ "MOVSX $dst,$src :16" %}
8488 ins_encode %{
8489 __ movswl($dst$$Register, $src$$Register);
8490 %}
8491 ins_pipe(ialu_reg_reg);
8492 %}
8493
8494
8495 // Logical Shift Right by variable
8496 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8497 match(Set dst (URShiftI dst shift));
8498 effect(KILL cr);
8499
8500 size(2);
8501 format %{ "SHR $dst,$shift" %}
8502 opcode(0xD3, 0x5); /* D3 /5 */
8503 ins_encode( OpcP, RegOpc( dst ) );
8504 ins_pipe( ialu_reg_reg );
8505 %}
8506
8507
8508 //----------Logical Instructions-----------------------------------------------
8509 //----------Integer Logical Instructions---------------------------------------
8510 // And Instructions
8511 // And Register with Register
8512 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8513 match(Set dst (AndI dst src));
8514 effect(KILL cr);
8515
8516 size(2);
8517 format %{ "AND $dst,$src" %}
8518 opcode(0x23);
8519 ins_encode( OpcP, RegReg( dst, src) );
8520 ins_pipe( ialu_reg_reg );
8521 %}
8522
8523 // And Register with Immediate
8524 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8525 match(Set dst (AndI dst src));
8526 effect(KILL cr);
8527
8528 format %{ "AND $dst,$src" %}
8529 opcode(0x81,0x04); /* Opcode 81 /4 */
8530 // ins_encode( RegImm( dst, src) );
8531 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8532 ins_pipe( ialu_reg );
8533 %}
8534
8535 // And Register with Memory
8536 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8537 match(Set dst (AndI dst (LoadI src)));
8538 effect(KILL cr);
8539
8540 ins_cost(125);
8541 format %{ "AND $dst,$src" %}
8542 opcode(0x23);
8543 ins_encode( OpcP, RegMem( dst, src) );
8544 ins_pipe( ialu_reg_mem );
8545 %}
8546
8547 // And Memory with Register
8548 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8549 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8550 effect(KILL cr);
8551
8552 ins_cost(150);
8553 format %{ "AND $dst,$src" %}
8554 opcode(0x21); /* Opcode 21 /r */
8555 ins_encode( OpcP, RegMem( src, dst ) );
8556 ins_pipe( ialu_mem_reg );
8557 %}
8558
8559 // And Memory with Immediate
8560 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8561 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8562 effect(KILL cr);
8563
8564 ins_cost(125);
8565 format %{ "AND $dst,$src" %}
8566 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8567 // ins_encode( MemImm( dst, src) );
8568 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8569 ins_pipe( ialu_mem_imm );
8570 %}
8571
8572 // Or Instructions
8573 // Or Register with Register
8574 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8575 match(Set dst (OrI dst src));
8576 effect(KILL cr);
8577
8578 size(2);
8579 format %{ "OR $dst,$src" %}
8580 opcode(0x0B);
8581 ins_encode( OpcP, RegReg( dst, src) );
8582 ins_pipe( ialu_reg_reg );
8583 %}
8584
8585 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8586 match(Set dst (OrI dst (CastP2X src)));
8587 effect(KILL cr);
8588
8589 size(2);
8590 format %{ "OR $dst,$src" %}
8591 opcode(0x0B);
8592 ins_encode( OpcP, RegReg( dst, src) );
8593 ins_pipe( ialu_reg_reg );
8594 %}
8595
8596
8597 // Or Register with Immediate
8598 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8599 match(Set dst (OrI dst src));
8600 effect(KILL cr);
8601
8602 format %{ "OR $dst,$src" %}
8603 opcode(0x81,0x01); /* Opcode 81 /1 id */
8604 // ins_encode( RegImm( dst, src) );
8605 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8606 ins_pipe( ialu_reg );
8607 %}
8608
8609 // Or Register with Memory
8610 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8611 match(Set dst (OrI dst (LoadI src)));
8612 effect(KILL cr);
8613
8614 ins_cost(125);
8615 format %{ "OR $dst,$src" %}
8616 opcode(0x0B);
8617 ins_encode( OpcP, RegMem( dst, src) );
8618 ins_pipe( ialu_reg_mem );
8619 %}
8620
8621 // Or Memory with Register
8622 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8623 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8624 effect(KILL cr);
8625
8626 ins_cost(150);
8627 format %{ "OR $dst,$src" %}
8628 opcode(0x09); /* Opcode 09 /r */
8629 ins_encode( OpcP, RegMem( src, dst ) );
8630 ins_pipe( ialu_mem_reg );
8631 %}
8632
8633 // Or Memory with Immediate
8634 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8635 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8636 effect(KILL cr);
8637
8638 ins_cost(125);
8639 format %{ "OR $dst,$src" %}
8640 opcode(0x81,0x1); /* Opcode 81 /1 id */
8641 // ins_encode( MemImm( dst, src) );
8642 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8643 ins_pipe( ialu_mem_imm );
8644 %}
8645
8646 // ROL/ROR
8647 // ROL expand
8648 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8649 effect(USE_DEF dst, USE shift, KILL cr);
8650
8651 format %{ "ROL $dst, $shift" %}
8652 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8653 ins_encode( OpcP, RegOpc( dst ));
8654 ins_pipe( ialu_reg );
8655 %}
8656
8657 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8658 effect(USE_DEF dst, USE shift, KILL cr);
8659
8660 format %{ "ROL $dst, $shift" %}
8661 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8662 ins_encode( RegOpcImm(dst, shift) );
8663 ins_pipe(ialu_reg);
8664 %}
8665
8666 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8667 effect(USE_DEF dst, USE shift, KILL cr);
8668
8669 format %{ "ROL $dst, $shift" %}
8670 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8671 ins_encode(OpcP, RegOpc(dst));
8672 ins_pipe( ialu_reg_reg );
8673 %}
8674 // end of ROL expand
8675
8676 // ROL 32bit by one once
8677 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8678 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8679
8680 expand %{
8681 rolI_eReg_imm1(dst, lshift, cr);
8682 %}
8683 %}
8684
8685 // ROL 32bit var by imm8 once
8686 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8687 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8688 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8689
8690 expand %{
8691 rolI_eReg_imm8(dst, lshift, cr);
8692 %}
8693 %}
8694
8695 // ROL 32bit var by var once
8696 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8697 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8698
8699 expand %{
8700 rolI_eReg_CL(dst, shift, cr);
8701 %}
8702 %}
8703
8704 // ROL 32bit var by var once
8705 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8706 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8707
8708 expand %{
8709 rolI_eReg_CL(dst, shift, cr);
8710 %}
8711 %}
8712
8713 // ROR expand
8714 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8715 effect(USE_DEF dst, USE shift, KILL cr);
8716
8717 format %{ "ROR $dst, $shift" %}
8718 opcode(0xD1,0x1); /* Opcode D1 /1 */
8719 ins_encode( OpcP, RegOpc( dst ) );
8720 ins_pipe( ialu_reg );
8721 %}
8722
8723 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8724 effect (USE_DEF dst, USE shift, KILL cr);
8725
8726 format %{ "ROR $dst, $shift" %}
8727 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8728 ins_encode( RegOpcImm(dst, shift) );
8729 ins_pipe( ialu_reg );
8730 %}
8731
8732 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8733 effect(USE_DEF dst, USE shift, KILL cr);
8734
8735 format %{ "ROR $dst, $shift" %}
8736 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8737 ins_encode(OpcP, RegOpc(dst));
8738 ins_pipe( ialu_reg_reg );
8739 %}
8740 // end of ROR expand
8741
8742 // ROR right once
8743 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8744 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8745
8746 expand %{
8747 rorI_eReg_imm1(dst, rshift, cr);
8748 %}
8749 %}
8750
8751 // ROR 32bit by immI8 once
8752 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8753 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8754 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8755
8756 expand %{
8757 rorI_eReg_imm8(dst, rshift, cr);
8758 %}
8759 %}
8760
8761 // ROR 32bit var by var once
8762 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8763 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8764
8765 expand %{
8766 rorI_eReg_CL(dst, shift, cr);
8767 %}
8768 %}
8769
8770 // ROR 32bit var by var once
8771 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8772 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8773
8774 expand %{
8775 rorI_eReg_CL(dst, shift, cr);
8776 %}
8777 %}
8778
8779 // Xor Instructions
8780 // Xor Register with Register
8781 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8782 match(Set dst (XorI dst src));
8783 effect(KILL cr);
8784
8785 size(2);
8786 format %{ "XOR $dst,$src" %}
8787 opcode(0x33);
8788 ins_encode( OpcP, RegReg( dst, src) );
8789 ins_pipe( ialu_reg_reg );
8790 %}
8791
8792 // Xor Register with Immediate -1
8793 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8794 match(Set dst (XorI dst imm));
8795
8796 size(2);
8797 format %{ "NOT $dst" %}
8798 ins_encode %{
8799 __ notl($dst$$Register);
8800 %}
8801 ins_pipe( ialu_reg );
8802 %}
8803
8804 // Xor Register with Immediate
8805 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8806 match(Set dst (XorI dst src));
8807 effect(KILL cr);
8808
8809 format %{ "XOR $dst,$src" %}
8810 opcode(0x81,0x06); /* Opcode 81 /6 id */
8811 // ins_encode( RegImm( dst, src) );
8812 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8813 ins_pipe( ialu_reg );
8814 %}
8815
8816 // Xor Register with Memory
8817 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8818 match(Set dst (XorI dst (LoadI src)));
8819 effect(KILL cr);
8820
8821 ins_cost(125);
8822 format %{ "XOR $dst,$src" %}
8823 opcode(0x33);
8824 ins_encode( OpcP, RegMem(dst, src) );
8825 ins_pipe( ialu_reg_mem );
8826 %}
8827
8828 // Xor Memory with Register
8829 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8830 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8831 effect(KILL cr);
8832
8833 ins_cost(150);
8834 format %{ "XOR $dst,$src" %}
8835 opcode(0x31); /* Opcode 31 /r */
8836 ins_encode( OpcP, RegMem( src, dst ) );
8837 ins_pipe( ialu_mem_reg );
8838 %}
8839
8840 // Xor Memory with Immediate
8841 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8842 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8843 effect(KILL cr);
8844
8845 ins_cost(125);
8846 format %{ "XOR $dst,$src" %}
8847 opcode(0x81,0x6); /* Opcode 81 /6 id */
8848 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8849 ins_pipe( ialu_mem_imm );
8850 %}
8851
8852 //----------Convert Int to Boolean---------------------------------------------
8853
8854 instruct movI_nocopy(rRegI dst, rRegI src) %{
8855 effect( DEF dst, USE src );
8856 format %{ "MOV $dst,$src" %}
8857 ins_encode( enc_Copy( dst, src) );
8858 ins_pipe( ialu_reg_reg );
8859 %}
8860
8861 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8862 effect( USE_DEF dst, USE src, KILL cr );
8863
8864 size(4);
8865 format %{ "NEG $dst\n\t"
8866 "ADC $dst,$src" %}
8867 ins_encode( neg_reg(dst),
8868 OpcRegReg(0x13,dst,src) );
8869 ins_pipe( ialu_reg_reg_long );
8870 %}
8871
8872 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8873 match(Set dst (Conv2B src));
8874
8875 expand %{
8876 movI_nocopy(dst,src);
8877 ci2b(dst,src,cr);
8878 %}
8879 %}
8880
8881 instruct movP_nocopy(rRegI dst, eRegP src) %{
8882 effect( DEF dst, USE src );
8883 format %{ "MOV $dst,$src" %}
8884 ins_encode( enc_Copy( dst, src) );
8885 ins_pipe( ialu_reg_reg );
8886 %}
8887
8888 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8889 effect( USE_DEF dst, USE src, KILL cr );
8890 format %{ "NEG $dst\n\t"
8891 "ADC $dst,$src" %}
8892 ins_encode( neg_reg(dst),
8893 OpcRegReg(0x13,dst,src) );
8894 ins_pipe( ialu_reg_reg_long );
8895 %}
8896
8897 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8898 match(Set dst (Conv2B src));
8899
8900 expand %{
8901 movP_nocopy(dst,src);
8902 cp2b(dst,src,cr);
8903 %}
8904 %}
8905
8906 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8907 match(Set dst (CmpLTMask p q));
8908 effect( KILL cr );
8909 ins_cost(400);
8910
8911 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8912 format %{ "XOR $dst,$dst\n\t"
8913 "CMP $p,$q\n\t"
8914 "SETlt $dst\n\t"
8915 "NEG $dst" %}
8916 ins_encode( OpcRegReg(0x33,dst,dst),
8917 OpcRegReg(0x3B,p,q),
8918 setLT_reg(dst), neg_reg(dst) );
8919 ins_pipe( pipe_slow );
8920 %}
8921
8922 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
8923 match(Set dst (CmpLTMask dst zero));
8924 effect( DEF dst, KILL cr );
8925 ins_cost(100);
8926
8927 format %{ "SAR $dst,31" %}
8928 opcode(0xC1, 0x7); /* C1 /7 ib */
8929 ins_encode( RegOpcImm( dst, 0x1F ) );
8930 ins_pipe( ialu_reg );
8931 %}
8932
8933
8934 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8935 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8936 effect( KILL tmp, KILL cr );
8937 ins_cost(400);
8938 // annoyingly, $tmp has no edges so you cant ask for it in
8939 // any format or encoding
8940 format %{ "SUB $p,$q\n\t"
8941 "SBB ECX,ECX\n\t"
8942 "AND ECX,$y\n\t"
8943 "ADD $p,ECX" %}
8944 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8945 ins_pipe( pipe_cmplt );
8946 %}
8947
8948 /* If I enable this, I encourage spilling in the inner loop of compress.
8949 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8950 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8951 effect( USE_KILL tmp, KILL cr );
8952 ins_cost(400);
8953
8954 format %{ "SUB $p,$q\n\t"
8955 "SBB ECX,ECX\n\t"
8956 "AND ECX,$y\n\t"
8957 "ADD $p,ECX" %}
8958 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8959 %}
8960 */
8961
8962 //----------Long Instructions------------------------------------------------
8963 // Add Long Register with Register
8964 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8965 match(Set dst (AddL dst src));
8966 effect(KILL cr);
8967 ins_cost(200);
8968 format %{ "ADD $dst.lo,$src.lo\n\t"
8969 "ADC $dst.hi,$src.hi" %}
8970 opcode(0x03, 0x13);
8971 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8972 ins_pipe( ialu_reg_reg_long );
8973 %}
8974
8975 // Add Long Register with Immediate
8976 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8977 match(Set dst (AddL dst src));
8978 effect(KILL cr);
8979 format %{ "ADD $dst.lo,$src.lo\n\t"
8980 "ADC $dst.hi,$src.hi" %}
8981 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8982 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8983 ins_pipe( ialu_reg_long );
8984 %}
8985
8986 // Add Long Register with Memory
8987 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8988 match(Set dst (AddL dst (LoadL mem)));
8989 effect(KILL cr);
8990 ins_cost(125);
8991 format %{ "ADD $dst.lo,$mem\n\t"
8992 "ADC $dst.hi,$mem+4" %}
8993 opcode(0x03, 0x13);
8994 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8995 ins_pipe( ialu_reg_long_mem );
8996 %}
8997
8998 // Subtract Long Register with Register.
8999 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9000 match(Set dst (SubL dst src));
9001 effect(KILL cr);
9002 ins_cost(200);
9003 format %{ "SUB $dst.lo,$src.lo\n\t"
9004 "SBB $dst.hi,$src.hi" %}
9005 opcode(0x2B, 0x1B);
9006 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9007 ins_pipe( ialu_reg_reg_long );
9008 %}
9009
9010 // Subtract Long Register with Immediate
9011 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9012 match(Set dst (SubL dst src));
9013 effect(KILL cr);
9014 format %{ "SUB $dst.lo,$src.lo\n\t"
9015 "SBB $dst.hi,$src.hi" %}
9016 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9017 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9018 ins_pipe( ialu_reg_long );
9019 %}
9020
9021 // Subtract Long Register with Memory
9022 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9023 match(Set dst (SubL dst (LoadL mem)));
9024 effect(KILL cr);
9025 ins_cost(125);
9026 format %{ "SUB $dst.lo,$mem\n\t"
9027 "SBB $dst.hi,$mem+4" %}
9028 opcode(0x2B, 0x1B);
9029 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9030 ins_pipe( ialu_reg_long_mem );
9031 %}
9032
9033 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9034 match(Set dst (SubL zero dst));
9035 effect(KILL cr);
9036 ins_cost(300);
9037 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9038 ins_encode( neg_long(dst) );
9039 ins_pipe( ialu_reg_reg_long );
9040 %}
9041
9042 // And Long Register with Register
9043 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9044 match(Set dst (AndL dst src));
9045 effect(KILL cr);
9046 format %{ "AND $dst.lo,$src.lo\n\t"
9047 "AND $dst.hi,$src.hi" %}
9048 opcode(0x23,0x23);
9049 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9050 ins_pipe( ialu_reg_reg_long );
9051 %}
9052
9053 // And Long Register with Immediate
9054 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9055 match(Set dst (AndL dst src));
9056 effect(KILL cr);
9057 format %{ "AND $dst.lo,$src.lo\n\t"
9058 "AND $dst.hi,$src.hi" %}
9059 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9060 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9061 ins_pipe( ialu_reg_long );
9062 %}
9063
9064 // And Long Register with Memory
9065 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9066 match(Set dst (AndL dst (LoadL mem)));
9067 effect(KILL cr);
9068 ins_cost(125);
9069 format %{ "AND $dst.lo,$mem\n\t"
9070 "AND $dst.hi,$mem+4" %}
9071 opcode(0x23, 0x23);
9072 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9073 ins_pipe( ialu_reg_long_mem );
9074 %}
9075
9076 // Or Long Register with Register
9077 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9078 match(Set dst (OrL dst src));
9079 effect(KILL cr);
9080 format %{ "OR $dst.lo,$src.lo\n\t"
9081 "OR $dst.hi,$src.hi" %}
9082 opcode(0x0B,0x0B);
9083 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9084 ins_pipe( ialu_reg_reg_long );
9085 %}
9086
9087 // Or Long Register with Immediate
9088 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9089 match(Set dst (OrL dst src));
9090 effect(KILL cr);
9091 format %{ "OR $dst.lo,$src.lo\n\t"
9092 "OR $dst.hi,$src.hi" %}
9093 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9094 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9095 ins_pipe( ialu_reg_long );
9096 %}
9097
9098 // Or Long Register with Memory
9099 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9100 match(Set dst (OrL dst (LoadL mem)));
9101 effect(KILL cr);
9102 ins_cost(125);
9103 format %{ "OR $dst.lo,$mem\n\t"
9104 "OR $dst.hi,$mem+4" %}
9105 opcode(0x0B,0x0B);
9106 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9107 ins_pipe( ialu_reg_long_mem );
9108 %}
9109
9110 // Xor Long Register with Register
9111 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9112 match(Set dst (XorL dst src));
9113 effect(KILL cr);
9114 format %{ "XOR $dst.lo,$src.lo\n\t"
9115 "XOR $dst.hi,$src.hi" %}
9116 opcode(0x33,0x33);
9117 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9118 ins_pipe( ialu_reg_reg_long );
9119 %}
9120
9121 // Xor Long Register with Immediate -1
9122 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9123 match(Set dst (XorL dst imm));
9124 format %{ "NOT $dst.lo\n\t"
9125 "NOT $dst.hi" %}
9126 ins_encode %{
9127 __ notl($dst$$Register);
9128 __ notl(HIGH_FROM_LOW($dst$$Register));
9129 %}
9130 ins_pipe( ialu_reg_long );
9131 %}
9132
9133 // Xor Long Register with Immediate
9134 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9135 match(Set dst (XorL dst src));
9136 effect(KILL cr);
9137 format %{ "XOR $dst.lo,$src.lo\n\t"
9138 "XOR $dst.hi,$src.hi" %}
9139 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9140 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9141 ins_pipe( ialu_reg_long );
9142 %}
9143
9144 // Xor Long Register with Memory
9145 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9146 match(Set dst (XorL dst (LoadL mem)));
9147 effect(KILL cr);
9148 ins_cost(125);
9149 format %{ "XOR $dst.lo,$mem\n\t"
9150 "XOR $dst.hi,$mem+4" %}
9151 opcode(0x33,0x33);
9152 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9153 ins_pipe( ialu_reg_long_mem );
9154 %}
9155
9156 // Shift Left Long by 1
9157 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9158 predicate(UseNewLongLShift);
9159 match(Set dst (LShiftL dst cnt));
9160 effect(KILL cr);
9161 ins_cost(100);
9162 format %{ "ADD $dst.lo,$dst.lo\n\t"
9163 "ADC $dst.hi,$dst.hi" %}
9164 ins_encode %{
9165 __ addl($dst$$Register,$dst$$Register);
9166 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9167 %}
9168 ins_pipe( ialu_reg_long );
9169 %}
9170
9171 // Shift Left Long by 2
9172 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9173 predicate(UseNewLongLShift);
9174 match(Set dst (LShiftL dst cnt));
9175 effect(KILL cr);
9176 ins_cost(100);
9177 format %{ "ADD $dst.lo,$dst.lo\n\t"
9178 "ADC $dst.hi,$dst.hi\n\t"
9179 "ADD $dst.lo,$dst.lo\n\t"
9180 "ADC $dst.hi,$dst.hi" %}
9181 ins_encode %{
9182 __ addl($dst$$Register,$dst$$Register);
9183 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9184 __ addl($dst$$Register,$dst$$Register);
9185 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9186 %}
9187 ins_pipe( ialu_reg_long );
9188 %}
9189
9190 // Shift Left Long by 3
9191 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9192 predicate(UseNewLongLShift);
9193 match(Set dst (LShiftL dst cnt));
9194 effect(KILL cr);
9195 ins_cost(100);
9196 format %{ "ADD $dst.lo,$dst.lo\n\t"
9197 "ADC $dst.hi,$dst.hi\n\t"
9198 "ADD $dst.lo,$dst.lo\n\t"
9199 "ADC $dst.hi,$dst.hi\n\t"
9200 "ADD $dst.lo,$dst.lo\n\t"
9201 "ADC $dst.hi,$dst.hi" %}
9202 ins_encode %{
9203 __ addl($dst$$Register,$dst$$Register);
9204 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9205 __ addl($dst$$Register,$dst$$Register);
9206 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9207 __ addl($dst$$Register,$dst$$Register);
9208 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9209 %}
9210 ins_pipe( ialu_reg_long );
9211 %}
9212
9213 // Shift Left Long by 1-31
9214 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9215 match(Set dst (LShiftL dst cnt));
9216 effect(KILL cr);
9217 ins_cost(200);
9218 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9219 "SHL $dst.lo,$cnt" %}
9220 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9221 ins_encode( move_long_small_shift(dst,cnt) );
9222 ins_pipe( ialu_reg_long );
9223 %}
9224
9225 // Shift Left Long by 32-63
9226 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9227 match(Set dst (LShiftL dst cnt));
9228 effect(KILL cr);
9229 ins_cost(300);
9230 format %{ "MOV $dst.hi,$dst.lo\n"
9231 "\tSHL $dst.hi,$cnt-32\n"
9232 "\tXOR $dst.lo,$dst.lo" %}
9233 opcode(0xC1, 0x4); /* C1 /4 ib */
9234 ins_encode( move_long_big_shift_clr(dst,cnt) );
9235 ins_pipe( ialu_reg_long );
9236 %}
9237
9238 // Shift Left Long by variable
9239 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9240 match(Set dst (LShiftL dst shift));
9241 effect(KILL cr);
9242 ins_cost(500+200);
9243 size(17);
9244 format %{ "TEST $shift,32\n\t"
9245 "JEQ,s small\n\t"
9246 "MOV $dst.hi,$dst.lo\n\t"
9247 "XOR $dst.lo,$dst.lo\n"
9248 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9249 "SHL $dst.lo,$shift" %}
9250 ins_encode( shift_left_long( dst, shift ) );
9251 ins_pipe( pipe_slow );
9252 %}
9253
9254 // Shift Right Long by 1-31
9255 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9256 match(Set dst (URShiftL dst cnt));
9257 effect(KILL cr);
9258 ins_cost(200);
9259 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9260 "SHR $dst.hi,$cnt" %}
9261 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9262 ins_encode( move_long_small_shift(dst,cnt) );
9263 ins_pipe( ialu_reg_long );
9264 %}
9265
9266 // Shift Right Long by 32-63
9267 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9268 match(Set dst (URShiftL dst cnt));
9269 effect(KILL cr);
9270 ins_cost(300);
9271 format %{ "MOV $dst.lo,$dst.hi\n"
9272 "\tSHR $dst.lo,$cnt-32\n"
9273 "\tXOR $dst.hi,$dst.hi" %}
9274 opcode(0xC1, 0x5); /* C1 /5 ib */
9275 ins_encode( move_long_big_shift_clr(dst,cnt) );
9276 ins_pipe( ialu_reg_long );
9277 %}
9278
9279 // Shift Right Long by variable
9280 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9281 match(Set dst (URShiftL dst shift));
9282 effect(KILL cr);
9283 ins_cost(600);
9284 size(17);
9285 format %{ "TEST $shift,32\n\t"
9286 "JEQ,s small\n\t"
9287 "MOV $dst.lo,$dst.hi\n\t"
9288 "XOR $dst.hi,$dst.hi\n"
9289 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9290 "SHR $dst.hi,$shift" %}
9291 ins_encode( shift_right_long( dst, shift ) );
9292 ins_pipe( pipe_slow );
9293 %}
9294
9295 // Shift Right Long by 1-31
9296 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9297 match(Set dst (RShiftL dst cnt));
9298 effect(KILL cr);
9299 ins_cost(200);
9300 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9301 "SAR $dst.hi,$cnt" %}
9302 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9303 ins_encode( move_long_small_shift(dst,cnt) );
9304 ins_pipe( ialu_reg_long );
9305 %}
9306
9307 // Shift Right Long by 32-63
9308 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9309 match(Set dst (RShiftL dst cnt));
9310 effect(KILL cr);
9311 ins_cost(300);
9312 format %{ "MOV $dst.lo,$dst.hi\n"
9313 "\tSAR $dst.lo,$cnt-32\n"
9314 "\tSAR $dst.hi,31" %}
9315 opcode(0xC1, 0x7); /* C1 /7 ib */
9316 ins_encode( move_long_big_shift_sign(dst,cnt) );
9317 ins_pipe( ialu_reg_long );
9318 %}
9319
9320 // Shift Right arithmetic Long by variable
9321 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9322 match(Set dst (RShiftL dst shift));
9323 effect(KILL cr);
9324 ins_cost(600);
9325 size(18);
9326 format %{ "TEST $shift,32\n\t"
9327 "JEQ,s small\n\t"
9328 "MOV $dst.lo,$dst.hi\n\t"
9329 "SAR $dst.hi,31\n"
9330 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9331 "SAR $dst.hi,$shift" %}
9332 ins_encode( shift_right_arith_long( dst, shift ) );
9333 ins_pipe( pipe_slow );
9334 %}
9335
9336
9337 //----------Double Instructions------------------------------------------------
9338 // Double Math
9339
9340 // Compare & branch
9341
9342 // P6 version of float compare, sets condition codes in EFLAGS
9343 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9344 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9345 match(Set cr (CmpD src1 src2));
9346 effect(KILL rax);
9347 ins_cost(150);
9348 format %{ "FLD $src1\n\t"
9349 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9350 "JNP exit\n\t"
9351 "MOV ah,1 // saw a NaN, set CF\n\t"
9352 "SAHF\n"
9353 "exit:\tNOP // avoid branch to branch" %}
9354 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9355 ins_encode( Push_Reg_DPR(src1),
9356 OpcP, RegOpc(src2),
9357 cmpF_P6_fixup );
9358 ins_pipe( pipe_slow );
9359 %}
9360
9361 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9362 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9363 match(Set cr (CmpD src1 src2));
9364 ins_cost(150);
9365 format %{ "FLD $src1\n\t"
9366 "FUCOMIP ST,$src2 // P6 instruction" %}
9367 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9368 ins_encode( Push_Reg_DPR(src1),
9369 OpcP, RegOpc(src2));
9370 ins_pipe( pipe_slow );
9371 %}
9372
9373 // Compare & branch
9374 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9375 predicate(UseSSE<=1);
9376 match(Set cr (CmpD src1 src2));
9377 effect(KILL rax);
9378 ins_cost(200);
9379 format %{ "FLD $src1\n\t"
9380 "FCOMp $src2\n\t"
9381 "FNSTSW AX\n\t"
9382 "TEST AX,0x400\n\t"
9383 "JZ,s flags\n\t"
9384 "MOV AH,1\t# unordered treat as LT\n"
9385 "flags:\tSAHF" %}
9386 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9387 ins_encode( Push_Reg_DPR(src1),
9388 OpcP, RegOpc(src2),
9389 fpu_flags);
9390 ins_pipe( pipe_slow );
9391 %}
9392
9393 // Compare vs zero into -1,0,1
9394 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9395 predicate(UseSSE<=1);
9396 match(Set dst (CmpD3 src1 zero));
9397 effect(KILL cr, KILL rax);
9398 ins_cost(280);
9399 format %{ "FTSTD $dst,$src1" %}
9400 opcode(0xE4, 0xD9);
9401 ins_encode( Push_Reg_DPR(src1),
9402 OpcS, OpcP, PopFPU,
9403 CmpF_Result(dst));
9404 ins_pipe( pipe_slow );
9405 %}
9406
9407 // Compare into -1,0,1
9408 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9409 predicate(UseSSE<=1);
9410 match(Set dst (CmpD3 src1 src2));
9411 effect(KILL cr, KILL rax);
9412 ins_cost(300);
9413 format %{ "FCMPD $dst,$src1,$src2" %}
9414 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9415 ins_encode( Push_Reg_DPR(src1),
9416 OpcP, RegOpc(src2),
9417 CmpF_Result(dst));
9418 ins_pipe( pipe_slow );
9419 %}
9420
9421 // float compare and set condition codes in EFLAGS by XMM regs
9422 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9423 predicate(UseSSE>=2);
9424 match(Set cr (CmpD src1 src2));
9425 ins_cost(145);
9426 format %{ "UCOMISD $src1,$src2\n\t"
9427 "JNP,s exit\n\t"
9428 "PUSHF\t# saw NaN, set CF\n\t"
9429 "AND [rsp], #0xffffff2b\n\t"
9430 "POPF\n"
9431 "exit:" %}
9432 ins_encode %{
9433 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9434 emit_cmpfp_fixup(_masm);
9435 %}
9436 ins_pipe( pipe_slow );
9437 %}
9438
9439 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9440 predicate(UseSSE>=2);
9441 match(Set cr (CmpD src1 src2));
9442 ins_cost(100);
9443 format %{ "UCOMISD $src1,$src2" %}
9444 ins_encode %{
9445 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9446 %}
9447 ins_pipe( pipe_slow );
9448 %}
9449
9450 // float compare and set condition codes in EFLAGS by XMM regs
9451 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9452 predicate(UseSSE>=2);
9453 match(Set cr (CmpD src1 (LoadD src2)));
9454 ins_cost(145);
9455 format %{ "UCOMISD $src1,$src2\n\t"
9456 "JNP,s exit\n\t"
9457 "PUSHF\t# saw NaN, set CF\n\t"
9458 "AND [rsp], #0xffffff2b\n\t"
9459 "POPF\n"
9460 "exit:" %}
9461 ins_encode %{
9462 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9463 emit_cmpfp_fixup(_masm);
9464 %}
9465 ins_pipe( pipe_slow );
9466 %}
9467
9468 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9469 predicate(UseSSE>=2);
9470 match(Set cr (CmpD src1 (LoadD src2)));
9471 ins_cost(100);
9472 format %{ "UCOMISD $src1,$src2" %}
9473 ins_encode %{
9474 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9475 %}
9476 ins_pipe( pipe_slow );
9477 %}
9478
9479 // Compare into -1,0,1 in XMM
9480 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9481 predicate(UseSSE>=2);
9482 match(Set dst (CmpD3 src1 src2));
9483 effect(KILL cr);
9484 ins_cost(255);
9485 format %{ "UCOMISD $src1, $src2\n\t"
9486 "MOV $dst, #-1\n\t"
9487 "JP,s done\n\t"
9488 "JB,s done\n\t"
9489 "SETNE $dst\n\t"
9490 "MOVZB $dst, $dst\n"
9491 "done:" %}
9492 ins_encode %{
9493 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9494 emit_cmpfp3(_masm, $dst$$Register);
9495 %}
9496 ins_pipe( pipe_slow );
9497 %}
9498
9499 // Compare into -1,0,1 in XMM and memory
9500 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9501 predicate(UseSSE>=2);
9502 match(Set dst (CmpD3 src1 (LoadD src2)));
9503 effect(KILL cr);
9504 ins_cost(275);
9505 format %{ "UCOMISD $src1, $src2\n\t"
9506 "MOV $dst, #-1\n\t"
9507 "JP,s done\n\t"
9508 "JB,s done\n\t"
9509 "SETNE $dst\n\t"
9510 "MOVZB $dst, $dst\n"
9511 "done:" %}
9512 ins_encode %{
9513 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9514 emit_cmpfp3(_masm, $dst$$Register);
9515 %}
9516 ins_pipe( pipe_slow );
9517 %}
9518
9519
9520 instruct subDPR_reg(regDPR dst, regDPR src) %{
9521 predicate (UseSSE <=1);
9522 match(Set dst (SubD dst src));
9523
9524 format %{ "FLD $src\n\t"
9525 "DSUBp $dst,ST" %}
9526 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9527 ins_cost(150);
9528 ins_encode( Push_Reg_DPR(src),
9529 OpcP, RegOpc(dst) );
9530 ins_pipe( fpu_reg_reg );
9531 %}
9532
9533 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9534 predicate (UseSSE <=1);
9535 match(Set dst (RoundDouble (SubD src1 src2)));
9536 ins_cost(250);
9537
9538 format %{ "FLD $src2\n\t"
9539 "DSUB ST,$src1\n\t"
9540 "FSTP_D $dst\t# D-round" %}
9541 opcode(0xD8, 0x5);
9542 ins_encode( Push_Reg_DPR(src2),
9543 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9544 ins_pipe( fpu_mem_reg_reg );
9545 %}
9546
9547
9548 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9549 predicate (UseSSE <=1);
9550 match(Set dst (SubD dst (LoadD src)));
9551 ins_cost(150);
9552
9553 format %{ "FLD $src\n\t"
9554 "DSUBp $dst,ST" %}
9555 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9556 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9557 OpcP, RegOpc(dst) );
9558 ins_pipe( fpu_reg_mem );
9559 %}
9560
9561 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9562 predicate (UseSSE<=1);
9563 match(Set dst (AbsD src));
9564 ins_cost(100);
9565 format %{ "FABS" %}
9566 opcode(0xE1, 0xD9);
9567 ins_encode( OpcS, OpcP );
9568 ins_pipe( fpu_reg_reg );
9569 %}
9570
9571 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9572 predicate(UseSSE<=1);
9573 match(Set dst (NegD src));
9574 ins_cost(100);
9575 format %{ "FCHS" %}
9576 opcode(0xE0, 0xD9);
9577 ins_encode( OpcS, OpcP );
9578 ins_pipe( fpu_reg_reg );
9579 %}
9580
9581 instruct addDPR_reg(regDPR dst, regDPR src) %{
9582 predicate(UseSSE<=1);
9583 match(Set dst (AddD dst src));
9584 format %{ "FLD $src\n\t"
9585 "DADD $dst,ST" %}
9586 size(4);
9587 ins_cost(150);
9588 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9589 ins_encode( Push_Reg_DPR(src),
9590 OpcP, RegOpc(dst) );
9591 ins_pipe( fpu_reg_reg );
9592 %}
9593
9594
9595 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9596 predicate(UseSSE<=1);
9597 match(Set dst (RoundDouble (AddD src1 src2)));
9598 ins_cost(250);
9599
9600 format %{ "FLD $src2\n\t"
9601 "DADD ST,$src1\n\t"
9602 "FSTP_D $dst\t# D-round" %}
9603 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9604 ins_encode( Push_Reg_DPR(src2),
9605 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9606 ins_pipe( fpu_mem_reg_reg );
9607 %}
9608
9609
9610 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9611 predicate(UseSSE<=1);
9612 match(Set dst (AddD dst (LoadD src)));
9613 ins_cost(150);
9614
9615 format %{ "FLD $src\n\t"
9616 "DADDp $dst,ST" %}
9617 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9618 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9619 OpcP, RegOpc(dst) );
9620 ins_pipe( fpu_reg_mem );
9621 %}
9622
9623 // add-to-memory
9624 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9625 predicate(UseSSE<=1);
9626 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9627 ins_cost(150);
9628
9629 format %{ "FLD_D $dst\n\t"
9630 "DADD ST,$src\n\t"
9631 "FST_D $dst" %}
9632 opcode(0xDD, 0x0);
9633 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9634 Opcode(0xD8), RegOpc(src),
9635 set_instruction_start,
9636 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9637 ins_pipe( fpu_reg_mem );
9638 %}
9639
9640 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9641 predicate(UseSSE<=1);
9642 match(Set dst (AddD dst con));
9643 ins_cost(125);
9644 format %{ "FLD1\n\t"
9645 "DADDp $dst,ST" %}
9646 ins_encode %{
9647 __ fld1();
9648 __ faddp($dst$$reg);
9649 %}
9650 ins_pipe(fpu_reg);
9651 %}
9652
9653 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9654 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9655 match(Set dst (AddD dst con));
9656 ins_cost(200);
9657 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9658 "DADDp $dst,ST" %}
9659 ins_encode %{
9660 __ fld_d($constantaddress($con));
9661 __ faddp($dst$$reg);
9662 %}
9663 ins_pipe(fpu_reg_mem);
9664 %}
9665
9666 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9667 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9668 match(Set dst (RoundDouble (AddD src con)));
9669 ins_cost(200);
9670 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9671 "DADD ST,$src\n\t"
9672 "FSTP_D $dst\t# D-round" %}
9673 ins_encode %{
9674 __ fld_d($constantaddress($con));
9675 __ fadd($src$$reg);
9676 __ fstp_d(Address(rsp, $dst$$disp));
9677 %}
9678 ins_pipe(fpu_mem_reg_con);
9679 %}
9680
9681 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9682 predicate(UseSSE<=1);
9683 match(Set dst (MulD dst src));
9684 format %{ "FLD $src\n\t"
9685 "DMULp $dst,ST" %}
9686 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9687 ins_cost(150);
9688 ins_encode( Push_Reg_DPR(src),
9689 OpcP, RegOpc(dst) );
9690 ins_pipe( fpu_reg_reg );
9691 %}
9692
9693 // Strict FP instruction biases argument before multiply then
9694 // biases result to avoid double rounding of subnormals.
9695 //
9696 // scale arg1 by multiplying arg1 by 2^(-15360)
9697 // load arg2
9698 // multiply scaled arg1 by arg2
9699 // rescale product by 2^(15360)
9700 //
9701 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9702 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9703 match(Set dst (MulD dst src));
9704 ins_cost(1); // Select this instruction for all strict FP double multiplies
9705
9706 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9707 "DMULp $dst,ST\n\t"
9708 "FLD $src\n\t"
9709 "DMULp $dst,ST\n\t"
9710 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9711 "DMULp $dst,ST\n\t" %}
9712 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9713 ins_encode( strictfp_bias1(dst),
9714 Push_Reg_DPR(src),
9715 OpcP, RegOpc(dst),
9716 strictfp_bias2(dst) );
9717 ins_pipe( fpu_reg_reg );
9718 %}
9719
9720 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9721 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9722 match(Set dst (MulD dst con));
9723 ins_cost(200);
9724 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9725 "DMULp $dst,ST" %}
9726 ins_encode %{
9727 __ fld_d($constantaddress($con));
9728 __ fmulp($dst$$reg);
9729 %}
9730 ins_pipe(fpu_reg_mem);
9731 %}
9732
9733
9734 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9735 predicate( UseSSE<=1 );
9736 match(Set dst (MulD dst (LoadD src)));
9737 ins_cost(200);
9738 format %{ "FLD_D $src\n\t"
9739 "DMULp $dst,ST" %}
9740 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9741 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9742 OpcP, RegOpc(dst) );
9743 ins_pipe( fpu_reg_mem );
9744 %}
9745
9746 //
9747 // Cisc-alternate to reg-reg multiply
9748 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9749 predicate( UseSSE<=1 );
9750 match(Set dst (MulD src (LoadD mem)));
9751 ins_cost(250);
9752 format %{ "FLD_D $mem\n\t"
9753 "DMUL ST,$src\n\t"
9754 "FSTP_D $dst" %}
9755 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9756 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9757 OpcReg_FPR(src),
9758 Pop_Reg_DPR(dst) );
9759 ins_pipe( fpu_reg_reg_mem );
9760 %}
9761
9762
9763 // MACRO3 -- addDPR a mulDPR
9764 // This instruction is a '2-address' instruction in that the result goes
9765 // back to src2. This eliminates a move from the macro; possibly the
9766 // register allocator will have to add it back (and maybe not).
9767 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9768 predicate( UseSSE<=1 );
9769 match(Set src2 (AddD (MulD src0 src1) src2));
9770 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9771 "DMUL ST,$src1\n\t"
9772 "DADDp $src2,ST" %}
9773 ins_cost(250);
9774 opcode(0xDD); /* LoadD DD /0 */
9775 ins_encode( Push_Reg_FPR(src0),
9776 FMul_ST_reg(src1),
9777 FAddP_reg_ST(src2) );
9778 ins_pipe( fpu_reg_reg_reg );
9779 %}
9780
9781
9782 // MACRO3 -- subDPR a mulDPR
9783 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9784 predicate( UseSSE<=1 );
9785 match(Set src2 (SubD (MulD src0 src1) src2));
9786 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9787 "DMUL ST,$src1\n\t"
9788 "DSUBRp $src2,ST" %}
9789 ins_cost(250);
9790 ins_encode( Push_Reg_FPR(src0),
9791 FMul_ST_reg(src1),
9792 Opcode(0xDE), Opc_plus(0xE0,src2));
9793 ins_pipe( fpu_reg_reg_reg );
9794 %}
9795
9796
9797 instruct divDPR_reg(regDPR dst, regDPR src) %{
9798 predicate( UseSSE<=1 );
9799 match(Set dst (DivD dst src));
9800
9801 format %{ "FLD $src\n\t"
9802 "FDIVp $dst,ST" %}
9803 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9804 ins_cost(150);
9805 ins_encode( Push_Reg_DPR(src),
9806 OpcP, RegOpc(dst) );
9807 ins_pipe( fpu_reg_reg );
9808 %}
9809
9810 // Strict FP instruction biases argument before division then
9811 // biases result, to avoid double rounding of subnormals.
9812 //
9813 // scale dividend by multiplying dividend by 2^(-15360)
9814 // load divisor
9815 // divide scaled dividend by divisor
9816 // rescale quotient by 2^(15360)
9817 //
9818 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9819 predicate (UseSSE<=1);
9820 match(Set dst (DivD dst src));
9821 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9822 ins_cost(01);
9823
9824 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9825 "DMULp $dst,ST\n\t"
9826 "FLD $src\n\t"
9827 "FDIVp $dst,ST\n\t"
9828 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9829 "DMULp $dst,ST\n\t" %}
9830 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9831 ins_encode( strictfp_bias1(dst),
9832 Push_Reg_DPR(src),
9833 OpcP, RegOpc(dst),
9834 strictfp_bias2(dst) );
9835 ins_pipe( fpu_reg_reg );
9836 %}
9837
9838 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9839 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9840 match(Set dst (RoundDouble (DivD src1 src2)));
9841
9842 format %{ "FLD $src1\n\t"
9843 "FDIV ST,$src2\n\t"
9844 "FSTP_D $dst\t# D-round" %}
9845 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9846 ins_encode( Push_Reg_DPR(src1),
9847 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9848 ins_pipe( fpu_mem_reg_reg );
9849 %}
9850
9851
9852 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9853 predicate(UseSSE<=1);
9854 match(Set dst (ModD dst src));
9855 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9856
9857 format %{ "DMOD $dst,$src" %}
9858 ins_cost(250);
9859 ins_encode(Push_Reg_Mod_DPR(dst, src),
9860 emitModDPR(),
9861 Push_Result_Mod_DPR(src),
9862 Pop_Reg_DPR(dst));
9863 ins_pipe( pipe_slow );
9864 %}
9865
9866 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9867 predicate(UseSSE>=2);
9868 match(Set dst (ModD src0 src1));
9869 effect(KILL rax, KILL cr);
9870
9871 format %{ "SUB ESP,8\t # DMOD\n"
9872 "\tMOVSD [ESP+0],$src1\n"
9873 "\tFLD_D [ESP+0]\n"
9874 "\tMOVSD [ESP+0],$src0\n"
9875 "\tFLD_D [ESP+0]\n"
9876 "loop:\tFPREM\n"
9877 "\tFWAIT\n"
9878 "\tFNSTSW AX\n"
9879 "\tSAHF\n"
9880 "\tJP loop\n"
9881 "\tFSTP_D [ESP+0]\n"
9882 "\tMOVSD $dst,[ESP+0]\n"
9883 "\tADD ESP,8\n"
9884 "\tFSTP ST0\t # Restore FPU Stack"
9885 %}
9886 ins_cost(250);
9887 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9888 ins_pipe( pipe_slow );
9889 %}
9890
9891 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9892 predicate (UseSSE<=1);
9893 match(Set dst (SinD src));
9894 ins_cost(1800);
9895 format %{ "DSIN $dst" %}
9896 opcode(0xD9, 0xFE);
9897 ins_encode( OpcP, OpcS );
9898 ins_pipe( pipe_slow );
9899 %}
9900
9901 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9902 predicate (UseSSE>=2);
9903 match(Set dst (SinD dst));
9904 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9905 ins_cost(1800);
9906 format %{ "DSIN $dst" %}
9907 opcode(0xD9, 0xFE);
9908 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9909 ins_pipe( pipe_slow );
9910 %}
9911
9912 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9913 predicate (UseSSE<=1);
9914 match(Set dst (CosD src));
9915 ins_cost(1800);
9916 format %{ "DCOS $dst" %}
9917 opcode(0xD9, 0xFF);
9918 ins_encode( OpcP, OpcS );
9919 ins_pipe( pipe_slow );
9920 %}
9921
9922 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9923 predicate (UseSSE>=2);
9924 match(Set dst (CosD dst));
9925 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9926 ins_cost(1800);
9927 format %{ "DCOS $dst" %}
9928 opcode(0xD9, 0xFF);
9929 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9930 ins_pipe( pipe_slow );
9931 %}
9932
9933 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9934 predicate (UseSSE<=1);
9935 match(Set dst(TanD src));
9936 format %{ "DTAN $dst" %}
9937 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9938 Opcode(0xDD), Opcode(0xD8)); // fstp st
9939 ins_pipe( pipe_slow );
9940 %}
9941
9942 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9943 predicate (UseSSE>=2);
9944 match(Set dst(TanD dst));
9945 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9946 format %{ "DTAN $dst" %}
9947 ins_encode( Push_SrcD(dst),
9948 Opcode(0xD9), Opcode(0xF2), // fptan
9949 Opcode(0xDD), Opcode(0xD8), // fstp st
9950 Push_ResultD(dst) );
9951 ins_pipe( pipe_slow );
9952 %}
9953
9954 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9955 predicate (UseSSE<=1);
9956 match(Set dst(AtanD dst src));
9957 format %{ "DATA $dst,$src" %}
9958 opcode(0xD9, 0xF3);
9959 ins_encode( Push_Reg_DPR(src),
9960 OpcP, OpcS, RegOpc(dst) );
9961 ins_pipe( pipe_slow );
9962 %}
9963
9964 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9965 predicate (UseSSE>=2);
9966 match(Set dst(AtanD dst src));
9967 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9968 format %{ "DATA $dst,$src" %}
9969 opcode(0xD9, 0xF3);
9970 ins_encode( Push_SrcD(src),
9971 OpcP, OpcS, Push_ResultD(dst) );
9972 ins_pipe( pipe_slow );
9973 %}
9974
9975 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9976 predicate (UseSSE<=1);
9977 match(Set dst (SqrtD src));
9978 format %{ "DSQRT $dst,$src" %}
9979 opcode(0xFA, 0xD9);
9980 ins_encode( Push_Reg_DPR(src),
9981 OpcS, OpcP, Pop_Reg_DPR(dst) );
9982 ins_pipe( pipe_slow );
9983 %}
9984
9985 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9986 predicate (UseSSE<=1);
9987 match(Set Y (PowD X Y)); // Raise X to the Yth power
9988 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9989 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9990 ins_encode %{
9991 __ subptr(rsp, 8);
9992 __ fld_s($X$$reg - 1);
9993 __ fast_pow();
9994 __ addptr(rsp, 8);
9995 %}
9996 ins_pipe( pipe_slow );
9997 %}
9998
9999 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10000 predicate (UseSSE>=2);
10001 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10002 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10003 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10004 ins_encode %{
10005 __ subptr(rsp, 8);
10006 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10007 __ fld_d(Address(rsp, 0));
10008 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10009 __ fld_d(Address(rsp, 0));
10010 __ fast_pow();
10011 __ fstp_d(Address(rsp, 0));
10012 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10013 __ addptr(rsp, 8);
10014 %}
10015 ins_pipe( pipe_slow );
10016 %}
10017
10018
10019 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10020 predicate (UseSSE<=1);
10021 match(Set dpr1 (ExpD dpr1));
10022 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10023 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10024 ins_encode %{
10025 __ fast_exp();
10026 %}
10027 ins_pipe( pipe_slow );
10028 %}
10029
10030 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10031 predicate (UseSSE>=2);
10032 match(Set dst (ExpD src));
10033 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10034 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10035 ins_encode %{
10036 __ subptr(rsp, 8);
10037 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10038 __ fld_d(Address(rsp, 0));
10039 __ fast_exp();
10040 __ fstp_d(Address(rsp, 0));
10041 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10042 __ addptr(rsp, 8);
10043 %}
10044 ins_pipe( pipe_slow );
10045 %}
10046
10047 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10048 predicate (UseSSE<=1);
10049 // The source Double operand on FPU stack
10050 match(Set dst (Log10D src));
10051 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10052 // fxch ; swap ST(0) with ST(1)
10053 // fyl2x ; compute log_10(2) * log_2(x)
10054 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10055 "FXCH \n\t"
10056 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10057 %}
10058 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10059 Opcode(0xD9), Opcode(0xC9), // fxch
10060 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10061
10062 ins_pipe( pipe_slow );
10063 %}
10064
10065 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10066 predicate (UseSSE>=2);
10067 effect(KILL cr);
10068 match(Set dst (Log10D src));
10069 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10070 // fyl2x ; compute log_10(2) * log_2(x)
10071 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10072 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10073 %}
10074 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10075 Push_SrcD(src),
10076 Opcode(0xD9), Opcode(0xF1), // fyl2x
10077 Push_ResultD(dst));
10078
10079 ins_pipe( pipe_slow );
10080 %}
10081
10082 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10083 predicate (UseSSE<=1);
10084 // The source Double operand on FPU stack
10085 match(Set dst (LogD src));
10086 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10087 // fxch ; swap ST(0) with ST(1)
10088 // fyl2x ; compute log_e(2) * log_2(x)
10089 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10090 "FXCH \n\t"
10091 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10092 %}
10093 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10094 Opcode(0xD9), Opcode(0xC9), // fxch
10095 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10096
10097 ins_pipe( pipe_slow );
10098 %}
10099
10100 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10101 predicate (UseSSE>=2);
10102 effect(KILL cr);
10103 // The source and result Double operands in XMM registers
10104 match(Set dst (LogD src));
10105 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10106 // fyl2x ; compute log_e(2) * log_2(x)
10107 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10108 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10109 %}
10110 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10111 Push_SrcD(src),
10112 Opcode(0xD9), Opcode(0xF1), // fyl2x
10113 Push_ResultD(dst));
10114 ins_pipe( pipe_slow );
10115 %}
10116
10117 //-------------Float Instructions-------------------------------
10118 // Float Math
10119
10120 // Code for float compare:
10121 // fcompp();
10122 // fwait(); fnstsw_ax();
10123 // sahf();
10124 // movl(dst, unordered_result);
10125 // jcc(Assembler::parity, exit);
10126 // movl(dst, less_result);
10127 // jcc(Assembler::below, exit);
10128 // movl(dst, equal_result);
10129 // jcc(Assembler::equal, exit);
10130 // movl(dst, greater_result);
10131 // exit:
10132
10133 // P6 version of float compare, sets condition codes in EFLAGS
10134 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10135 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10136 match(Set cr (CmpF src1 src2));
10137 effect(KILL rax);
10138 ins_cost(150);
10139 format %{ "FLD $src1\n\t"
10140 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10141 "JNP exit\n\t"
10142 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10143 "SAHF\n"
10144 "exit:\tNOP // avoid branch to branch" %}
10145 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10146 ins_encode( Push_Reg_DPR(src1),
10147 OpcP, RegOpc(src2),
10148 cmpF_P6_fixup );
10149 ins_pipe( pipe_slow );
10150 %}
10151
10152 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10153 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10154 match(Set cr (CmpF src1 src2));
10155 ins_cost(100);
10156 format %{ "FLD $src1\n\t"
10157 "FUCOMIP ST,$src2 // P6 instruction" %}
10158 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10159 ins_encode( Push_Reg_DPR(src1),
10160 OpcP, RegOpc(src2));
10161 ins_pipe( pipe_slow );
10162 %}
10163
10164
10165 // Compare & branch
10166 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10167 predicate(UseSSE == 0);
10168 match(Set cr (CmpF src1 src2));
10169 effect(KILL rax);
10170 ins_cost(200);
10171 format %{ "FLD $src1\n\t"
10172 "FCOMp $src2\n\t"
10173 "FNSTSW AX\n\t"
10174 "TEST AX,0x400\n\t"
10175 "JZ,s flags\n\t"
10176 "MOV AH,1\t# unordered treat as LT\n"
10177 "flags:\tSAHF" %}
10178 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10179 ins_encode( Push_Reg_DPR(src1),
10180 OpcP, RegOpc(src2),
10181 fpu_flags);
10182 ins_pipe( pipe_slow );
10183 %}
10184
10185 // Compare vs zero into -1,0,1
10186 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10187 predicate(UseSSE == 0);
10188 match(Set dst (CmpF3 src1 zero));
10189 effect(KILL cr, KILL rax);
10190 ins_cost(280);
10191 format %{ "FTSTF $dst,$src1" %}
10192 opcode(0xE4, 0xD9);
10193 ins_encode( Push_Reg_DPR(src1),
10194 OpcS, OpcP, PopFPU,
10195 CmpF_Result(dst));
10196 ins_pipe( pipe_slow );
10197 %}
10198
10199 // Compare into -1,0,1
10200 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10201 predicate(UseSSE == 0);
10202 match(Set dst (CmpF3 src1 src2));
10203 effect(KILL cr, KILL rax);
10204 ins_cost(300);
10205 format %{ "FCMPF $dst,$src1,$src2" %}
10206 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10207 ins_encode( Push_Reg_DPR(src1),
10208 OpcP, RegOpc(src2),
10209 CmpF_Result(dst));
10210 ins_pipe( pipe_slow );
10211 %}
10212
10213 // float compare and set condition codes in EFLAGS by XMM regs
10214 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10215 predicate(UseSSE>=1);
10216 match(Set cr (CmpF src1 src2));
10217 ins_cost(145);
10218 format %{ "UCOMISS $src1,$src2\n\t"
10219 "JNP,s exit\n\t"
10220 "PUSHF\t# saw NaN, set CF\n\t"
10221 "AND [rsp], #0xffffff2b\n\t"
10222 "POPF\n"
10223 "exit:" %}
10224 ins_encode %{
10225 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10226 emit_cmpfp_fixup(_masm);
10227 %}
10228 ins_pipe( pipe_slow );
10229 %}
10230
10231 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10232 predicate(UseSSE>=1);
10233 match(Set cr (CmpF src1 src2));
10234 ins_cost(100);
10235 format %{ "UCOMISS $src1,$src2" %}
10236 ins_encode %{
10237 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10238 %}
10239 ins_pipe( pipe_slow );
10240 %}
10241
10242 // float compare and set condition codes in EFLAGS by XMM regs
10243 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10244 predicate(UseSSE>=1);
10245 match(Set cr (CmpF src1 (LoadF src2)));
10246 ins_cost(165);
10247 format %{ "UCOMISS $src1,$src2\n\t"
10248 "JNP,s exit\n\t"
10249 "PUSHF\t# saw NaN, set CF\n\t"
10250 "AND [rsp], #0xffffff2b\n\t"
10251 "POPF\n"
10252 "exit:" %}
10253 ins_encode %{
10254 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10255 emit_cmpfp_fixup(_masm);
10256 %}
10257 ins_pipe( pipe_slow );
10258 %}
10259
10260 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10261 predicate(UseSSE>=1);
10262 match(Set cr (CmpF src1 (LoadF src2)));
10263 ins_cost(100);
10264 format %{ "UCOMISS $src1,$src2" %}
10265 ins_encode %{
10266 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10267 %}
10268 ins_pipe( pipe_slow );
10269 %}
10270
10271 // Compare into -1,0,1 in XMM
10272 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10273 predicate(UseSSE>=1);
10274 match(Set dst (CmpF3 src1 src2));
10275 effect(KILL cr);
10276 ins_cost(255);
10277 format %{ "UCOMISS $src1, $src2\n\t"
10278 "MOV $dst, #-1\n\t"
10279 "JP,s done\n\t"
10280 "JB,s done\n\t"
10281 "SETNE $dst\n\t"
10282 "MOVZB $dst, $dst\n"
10283 "done:" %}
10284 ins_encode %{
10285 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10286 emit_cmpfp3(_masm, $dst$$Register);
10287 %}
10288 ins_pipe( pipe_slow );
10289 %}
10290
10291 // Compare into -1,0,1 in XMM and memory
10292 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10293 predicate(UseSSE>=1);
10294 match(Set dst (CmpF3 src1 (LoadF src2)));
10295 effect(KILL cr);
10296 ins_cost(275);
10297 format %{ "UCOMISS $src1, $src2\n\t"
10298 "MOV $dst, #-1\n\t"
10299 "JP,s done\n\t"
10300 "JB,s done\n\t"
10301 "SETNE $dst\n\t"
10302 "MOVZB $dst, $dst\n"
10303 "done:" %}
10304 ins_encode %{
10305 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10306 emit_cmpfp3(_masm, $dst$$Register);
10307 %}
10308 ins_pipe( pipe_slow );
10309 %}
10310
10311 // Spill to obtain 24-bit precision
10312 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10313 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10314 match(Set dst (SubF src1 src2));
10315
10316 format %{ "FSUB $dst,$src1 - $src2" %}
10317 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10318 ins_encode( Push_Reg_FPR(src1),
10319 OpcReg_FPR(src2),
10320 Pop_Mem_FPR(dst) );
10321 ins_pipe( fpu_mem_reg_reg );
10322 %}
10323 //
10324 // This instruction does not round to 24-bits
10325 instruct subFPR_reg(regFPR dst, regFPR src) %{
10326 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10327 match(Set dst (SubF dst src));
10328
10329 format %{ "FSUB $dst,$src" %}
10330 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10331 ins_encode( Push_Reg_FPR(src),
10332 OpcP, RegOpc(dst) );
10333 ins_pipe( fpu_reg_reg );
10334 %}
10335
10336 // Spill to obtain 24-bit precision
10337 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10338 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10339 match(Set dst (AddF src1 src2));
10340
10341 format %{ "FADD $dst,$src1,$src2" %}
10342 opcode(0xD8, 0x0); /* D8 C0+i */
10343 ins_encode( Push_Reg_FPR(src2),
10344 OpcReg_FPR(src1),
10345 Pop_Mem_FPR(dst) );
10346 ins_pipe( fpu_mem_reg_reg );
10347 %}
10348 //
10349 // This instruction does not round to 24-bits
10350 instruct addFPR_reg(regFPR dst, regFPR src) %{
10351 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10352 match(Set dst (AddF dst src));
10353
10354 format %{ "FLD $src\n\t"
10355 "FADDp $dst,ST" %}
10356 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10357 ins_encode( Push_Reg_FPR(src),
10358 OpcP, RegOpc(dst) );
10359 ins_pipe( fpu_reg_reg );
10360 %}
10361
10362 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10363 predicate(UseSSE==0);
10364 match(Set dst (AbsF src));
10365 ins_cost(100);
10366 format %{ "FABS" %}
10367 opcode(0xE1, 0xD9);
10368 ins_encode( OpcS, OpcP );
10369 ins_pipe( fpu_reg_reg );
10370 %}
10371
10372 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10373 predicate(UseSSE==0);
10374 match(Set dst (NegF src));
10375 ins_cost(100);
10376 format %{ "FCHS" %}
10377 opcode(0xE0, 0xD9);
10378 ins_encode( OpcS, OpcP );
10379 ins_pipe( fpu_reg_reg );
10380 %}
10381
10382 // Cisc-alternate to addFPR_reg
10383 // Spill to obtain 24-bit precision
10384 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10385 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10386 match(Set dst (AddF src1 (LoadF src2)));
10387
10388 format %{ "FLD $src2\n\t"
10389 "FADD ST,$src1\n\t"
10390 "FSTP_S $dst" %}
10391 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10392 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10393 OpcReg_FPR(src1),
10394 Pop_Mem_FPR(dst) );
10395 ins_pipe( fpu_mem_reg_mem );
10396 %}
10397 //
10398 // Cisc-alternate to addFPR_reg
10399 // This instruction does not round to 24-bits
10400 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10401 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10402 match(Set dst (AddF dst (LoadF src)));
10403
10404 format %{ "FADD $dst,$src" %}
10405 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10406 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10407 OpcP, RegOpc(dst) );
10408 ins_pipe( fpu_reg_mem );
10409 %}
10410
10411 // // Following two instructions for _222_mpegaudio
10412 // Spill to obtain 24-bit precision
10413 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10414 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10415 match(Set dst (AddF src1 src2));
10416
10417 format %{ "FADD $dst,$src1,$src2" %}
10418 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10419 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10420 OpcReg_FPR(src2),
10421 Pop_Mem_FPR(dst) );
10422 ins_pipe( fpu_mem_reg_mem );
10423 %}
10424
10425 // Cisc-spill variant
10426 // Spill to obtain 24-bit precision
10427 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10428 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10429 match(Set dst (AddF src1 (LoadF src2)));
10430
10431 format %{ "FADD $dst,$src1,$src2 cisc" %}
10432 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10433 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10434 set_instruction_start,
10435 OpcP, RMopc_Mem(secondary,src1),
10436 Pop_Mem_FPR(dst) );
10437 ins_pipe( fpu_mem_mem_mem );
10438 %}
10439
10440 // Spill to obtain 24-bit precision
10441 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10442 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10443 match(Set dst (AddF src1 src2));
10444
10445 format %{ "FADD $dst,$src1,$src2" %}
10446 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10447 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10448 set_instruction_start,
10449 OpcP, RMopc_Mem(secondary,src1),
10450 Pop_Mem_FPR(dst) );
10451 ins_pipe( fpu_mem_mem_mem );
10452 %}
10453
10454
10455 // Spill to obtain 24-bit precision
10456 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10457 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10458 match(Set dst (AddF src con));
10459 format %{ "FLD $src\n\t"
10460 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10461 "FSTP_S $dst" %}
10462 ins_encode %{
10463 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10464 __ fadd_s($constantaddress($con));
10465 __ fstp_s(Address(rsp, $dst$$disp));
10466 %}
10467 ins_pipe(fpu_mem_reg_con);
10468 %}
10469 //
10470 // This instruction does not round to 24-bits
10471 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10472 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10473 match(Set dst (AddF src con));
10474 format %{ "FLD $src\n\t"
10475 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10476 "FSTP $dst" %}
10477 ins_encode %{
10478 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10479 __ fadd_s($constantaddress($con));
10480 __ fstp_d($dst$$reg);
10481 %}
10482 ins_pipe(fpu_reg_reg_con);
10483 %}
10484
10485 // Spill to obtain 24-bit precision
10486 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10487 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10488 match(Set dst (MulF src1 src2));
10489
10490 format %{ "FLD $src1\n\t"
10491 "FMUL $src2\n\t"
10492 "FSTP_S $dst" %}
10493 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10494 ins_encode( Push_Reg_FPR(src1),
10495 OpcReg_FPR(src2),
10496 Pop_Mem_FPR(dst) );
10497 ins_pipe( fpu_mem_reg_reg );
10498 %}
10499 //
10500 // This instruction does not round to 24-bits
10501 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10502 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10503 match(Set dst (MulF src1 src2));
10504
10505 format %{ "FLD $src1\n\t"
10506 "FMUL $src2\n\t"
10507 "FSTP_S $dst" %}
10508 opcode(0xD8, 0x1); /* D8 C8+i */
10509 ins_encode( Push_Reg_FPR(src2),
10510 OpcReg_FPR(src1),
10511 Pop_Reg_FPR(dst) );
10512 ins_pipe( fpu_reg_reg_reg );
10513 %}
10514
10515
10516 // Spill to obtain 24-bit precision
10517 // Cisc-alternate to reg-reg multiply
10518 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10519 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10520 match(Set dst (MulF src1 (LoadF src2)));
10521
10522 format %{ "FLD_S $src2\n\t"
10523 "FMUL $src1\n\t"
10524 "FSTP_S $dst" %}
10525 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10526 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10527 OpcReg_FPR(src1),
10528 Pop_Mem_FPR(dst) );
10529 ins_pipe( fpu_mem_reg_mem );
10530 %}
10531 //
10532 // This instruction does not round to 24-bits
10533 // Cisc-alternate to reg-reg multiply
10534 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10535 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10536 match(Set dst (MulF src1 (LoadF src2)));
10537
10538 format %{ "FMUL $dst,$src1,$src2" %}
10539 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10540 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10541 OpcReg_FPR(src1),
10542 Pop_Reg_FPR(dst) );
10543 ins_pipe( fpu_reg_reg_mem );
10544 %}
10545
10546 // Spill to obtain 24-bit precision
10547 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10548 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10549 match(Set dst (MulF src1 src2));
10550
10551 format %{ "FMUL $dst,$src1,$src2" %}
10552 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10553 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10554 set_instruction_start,
10555 OpcP, RMopc_Mem(secondary,src1),
10556 Pop_Mem_FPR(dst) );
10557 ins_pipe( fpu_mem_mem_mem );
10558 %}
10559
10560 // Spill to obtain 24-bit precision
10561 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10562 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10563 match(Set dst (MulF src con));
10564
10565 format %{ "FLD $src\n\t"
10566 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10567 "FSTP_S $dst" %}
10568 ins_encode %{
10569 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10570 __ fmul_s($constantaddress($con));
10571 __ fstp_s(Address(rsp, $dst$$disp));
10572 %}
10573 ins_pipe(fpu_mem_reg_con);
10574 %}
10575 //
10576 // This instruction does not round to 24-bits
10577 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10578 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10579 match(Set dst (MulF src con));
10580
10581 format %{ "FLD $src\n\t"
10582 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10583 "FSTP $dst" %}
10584 ins_encode %{
10585 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10586 __ fmul_s($constantaddress($con));
10587 __ fstp_d($dst$$reg);
10588 %}
10589 ins_pipe(fpu_reg_reg_con);
10590 %}
10591
10592
10593 //
10594 // MACRO1 -- subsume unshared load into mulFPR
10595 // This instruction does not round to 24-bits
10596 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10597 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10598 match(Set dst (MulF (LoadF mem1) src));
10599
10600 format %{ "FLD $mem1 ===MACRO1===\n\t"
10601 "FMUL ST,$src\n\t"
10602 "FSTP $dst" %}
10603 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10604 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10605 OpcReg_FPR(src),
10606 Pop_Reg_FPR(dst) );
10607 ins_pipe( fpu_reg_reg_mem );
10608 %}
10609 //
10610 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10611 // This instruction does not round to 24-bits
10612 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10613 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10614 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10615 ins_cost(95);
10616
10617 format %{ "FLD $mem1 ===MACRO2===\n\t"
10618 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10619 "FADD ST,$src2\n\t"
10620 "FSTP $dst" %}
10621 opcode(0xD9); /* LoadF D9 /0 */
10622 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10623 FMul_ST_reg(src1),
10624 FAdd_ST_reg(src2),
10625 Pop_Reg_FPR(dst) );
10626 ins_pipe( fpu_reg_mem_reg_reg );
10627 %}
10628
10629 // MACRO3 -- addFPR a mulFPR
10630 // This instruction does not round to 24-bits. It is a '2-address'
10631 // instruction in that the result goes back to src2. This eliminates
10632 // a move from the macro; possibly the register allocator will have
10633 // to add it back (and maybe not).
10634 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10635 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10636 match(Set src2 (AddF (MulF src0 src1) src2));
10637
10638 format %{ "FLD $src0 ===MACRO3===\n\t"
10639 "FMUL ST,$src1\n\t"
10640 "FADDP $src2,ST" %}
10641 opcode(0xD9); /* LoadF D9 /0 */
10642 ins_encode( Push_Reg_FPR(src0),
10643 FMul_ST_reg(src1),
10644 FAddP_reg_ST(src2) );
10645 ins_pipe( fpu_reg_reg_reg );
10646 %}
10647
10648 // MACRO4 -- divFPR subFPR
10649 // This instruction does not round to 24-bits
10650 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10651 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10652 match(Set dst (DivF (SubF src2 src1) src3));
10653
10654 format %{ "FLD $src2 ===MACRO4===\n\t"
10655 "FSUB ST,$src1\n\t"
10656 "FDIV ST,$src3\n\t"
10657 "FSTP $dst" %}
10658 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10659 ins_encode( Push_Reg_FPR(src2),
10660 subFPR_divFPR_encode(src1,src3),
10661 Pop_Reg_FPR(dst) );
10662 ins_pipe( fpu_reg_reg_reg_reg );
10663 %}
10664
10665 // Spill to obtain 24-bit precision
10666 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10667 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10668 match(Set dst (DivF src1 src2));
10669
10670 format %{ "FDIV $dst,$src1,$src2" %}
10671 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10672 ins_encode( Push_Reg_FPR(src1),
10673 OpcReg_FPR(src2),
10674 Pop_Mem_FPR(dst) );
10675 ins_pipe( fpu_mem_reg_reg );
10676 %}
10677 //
10678 // This instruction does not round to 24-bits
10679 instruct divFPR_reg(regFPR dst, regFPR src) %{
10680 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10681 match(Set dst (DivF dst src));
10682
10683 format %{ "FDIV $dst,$src" %}
10684 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10685 ins_encode( Push_Reg_FPR(src),
10686 OpcP, RegOpc(dst) );
10687 ins_pipe( fpu_reg_reg );
10688 %}
10689
10690
10691 // Spill to obtain 24-bit precision
10692 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10693 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10694 match(Set dst (ModF src1 src2));
10695 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10696
10697 format %{ "FMOD $dst,$src1,$src2" %}
10698 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10699 emitModDPR(),
10700 Push_Result_Mod_DPR(src2),
10701 Pop_Mem_FPR(dst));
10702 ins_pipe( pipe_slow );
10703 %}
10704 //
10705 // This instruction does not round to 24-bits
10706 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10707 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10708 match(Set dst (ModF dst src));
10709 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10710
10711 format %{ "FMOD $dst,$src" %}
10712 ins_encode(Push_Reg_Mod_DPR(dst, src),
10713 emitModDPR(),
10714 Push_Result_Mod_DPR(src),
10715 Pop_Reg_FPR(dst));
10716 ins_pipe( pipe_slow );
10717 %}
10718
10719 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10720 predicate(UseSSE>=1);
10721 match(Set dst (ModF src0 src1));
10722 effect(KILL rax, KILL cr);
10723 format %{ "SUB ESP,4\t # FMOD\n"
10724 "\tMOVSS [ESP+0],$src1\n"
10725 "\tFLD_S [ESP+0]\n"
10726 "\tMOVSS [ESP+0],$src0\n"
10727 "\tFLD_S [ESP+0]\n"
10728 "loop:\tFPREM\n"
10729 "\tFWAIT\n"
10730 "\tFNSTSW AX\n"
10731 "\tSAHF\n"
10732 "\tJP loop\n"
10733 "\tFSTP_S [ESP+0]\n"
10734 "\tMOVSS $dst,[ESP+0]\n"
10735 "\tADD ESP,4\n"
10736 "\tFSTP ST0\t # Restore FPU Stack"
10737 %}
10738 ins_cost(250);
10739 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10740 ins_pipe( pipe_slow );
10741 %}
10742
10743
10744 //----------Arithmetic Conversion Instructions---------------------------------
10745 // The conversions operations are all Alpha sorted. Please keep it that way!
10746
10747 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10748 predicate(UseSSE==0);
10749 match(Set dst (RoundFloat src));
10750 ins_cost(125);
10751 format %{ "FST_S $dst,$src\t# F-round" %}
10752 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10753 ins_pipe( fpu_mem_reg );
10754 %}
10755
10756 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10757 predicate(UseSSE<=1);
10758 match(Set dst (RoundDouble src));
10759 ins_cost(125);
10760 format %{ "FST_D $dst,$src\t# D-round" %}
10761 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10762 ins_pipe( fpu_mem_reg );
10763 %}
10764
10765 // Force rounding to 24-bit precision and 6-bit exponent
10766 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10767 predicate(UseSSE==0);
10768 match(Set dst (ConvD2F src));
10769 format %{ "FST_S $dst,$src\t# F-round" %}
10770 expand %{
10771 roundFloat_mem_reg(dst,src);
10772 %}
10773 %}
10774
10775 // Force rounding to 24-bit precision and 6-bit exponent
10776 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10777 predicate(UseSSE==1);
10778 match(Set dst (ConvD2F src));
10779 effect( KILL cr );
10780 format %{ "SUB ESP,4\n\t"
10781 "FST_S [ESP],$src\t# F-round\n\t"
10782 "MOVSS $dst,[ESP]\n\t"
10783 "ADD ESP,4" %}
10784 ins_encode %{
10785 __ subptr(rsp, 4);
10786 if ($src$$reg != FPR1L_enc) {
10787 __ fld_s($src$$reg-1);
10788 __ fstp_s(Address(rsp, 0));
10789 } else {
10790 __ fst_s(Address(rsp, 0));
10791 }
10792 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10793 __ addptr(rsp, 4);
10794 %}
10795 ins_pipe( pipe_slow );
10796 %}
10797
10798 // Force rounding double precision to single precision
10799 instruct convD2F_reg(regF dst, regD src) %{
10800 predicate(UseSSE>=2);
10801 match(Set dst (ConvD2F src));
10802 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10803 ins_encode %{
10804 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10805 %}
10806 ins_pipe( pipe_slow );
10807 %}
10808
10809 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10810 predicate(UseSSE==0);
10811 match(Set dst (ConvF2D src));
10812 format %{ "FST_S $dst,$src\t# D-round" %}
10813 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10814 ins_pipe( fpu_reg_reg );
10815 %}
10816
10817 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10818 predicate(UseSSE==1);
10819 match(Set dst (ConvF2D src));
10820 format %{ "FST_D $dst,$src\t# D-round" %}
10821 expand %{
10822 roundDouble_mem_reg(dst,src);
10823 %}
10824 %}
10825
10826 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10827 predicate(UseSSE==1);
10828 match(Set dst (ConvF2D src));
10829 effect( KILL cr );
10830 format %{ "SUB ESP,4\n\t"
10831 "MOVSS [ESP] $src\n\t"
10832 "FLD_S [ESP]\n\t"
10833 "ADD ESP,4\n\t"
10834 "FSTP $dst\t# D-round" %}
10835 ins_encode %{
10836 __ subptr(rsp, 4);
10837 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10838 __ fld_s(Address(rsp, 0));
10839 __ addptr(rsp, 4);
10840 __ fstp_d($dst$$reg);
10841 %}
10842 ins_pipe( pipe_slow );
10843 %}
10844
10845 instruct convF2D_reg(regD dst, regF src) %{
10846 predicate(UseSSE>=2);
10847 match(Set dst (ConvF2D src));
10848 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10849 ins_encode %{
10850 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10851 %}
10852 ins_pipe( pipe_slow );
10853 %}
10854
10855 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10856 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10857 predicate(UseSSE<=1);
10858 match(Set dst (ConvD2I src));
10859 effect( KILL tmp, KILL cr );
10860 format %{ "FLD $src\t# Convert double to int \n\t"
10861 "FLDCW trunc mode\n\t"
10862 "SUB ESP,4\n\t"
10863 "FISTp [ESP + #0]\n\t"
10864 "FLDCW std/24-bit mode\n\t"
10865 "POP EAX\n\t"
10866 "CMP EAX,0x80000000\n\t"
10867 "JNE,s fast\n\t"
10868 "FLD_D $src\n\t"
10869 "CALL d2i_wrapper\n"
10870 "fast:" %}
10871 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10872 ins_pipe( pipe_slow );
10873 %}
10874
10875 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10876 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10877 predicate(UseSSE>=2);
10878 match(Set dst (ConvD2I src));
10879 effect( KILL tmp, KILL cr );
10880 format %{ "CVTTSD2SI $dst, $src\n\t"
10881 "CMP $dst,0x80000000\n\t"
10882 "JNE,s fast\n\t"
10883 "SUB ESP, 8\n\t"
10884 "MOVSD [ESP], $src\n\t"
10885 "FLD_D [ESP]\n\t"
10886 "ADD ESP, 8\n\t"
10887 "CALL d2i_wrapper\n"
10888 "fast:" %}
10889 ins_encode %{
10890 Label fast;
10891 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10892 __ cmpl($dst$$Register, 0x80000000);
10893 __ jccb(Assembler::notEqual, fast);
10894 __ subptr(rsp, 8);
10895 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10896 __ fld_d(Address(rsp, 0));
10897 __ addptr(rsp, 8);
10898 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10899 __ bind(fast);
10900 %}
10901 ins_pipe( pipe_slow );
10902 %}
10903
10904 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10905 predicate(UseSSE<=1);
10906 match(Set dst (ConvD2L src));
10907 effect( KILL cr );
10908 format %{ "FLD $src\t# Convert double to long\n\t"
10909 "FLDCW trunc mode\n\t"
10910 "SUB ESP,8\n\t"
10911 "FISTp [ESP + #0]\n\t"
10912 "FLDCW std/24-bit mode\n\t"
10913 "POP EAX\n\t"
10914 "POP EDX\n\t"
10915 "CMP EDX,0x80000000\n\t"
10916 "JNE,s fast\n\t"
10917 "TEST EAX,EAX\n\t"
10918 "JNE,s fast\n\t"
10919 "FLD $src\n\t"
10920 "CALL d2l_wrapper\n"
10921 "fast:" %}
10922 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10923 ins_pipe( pipe_slow );
10924 %}
10925
10926 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10927 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10928 predicate (UseSSE>=2);
10929 match(Set dst (ConvD2L src));
10930 effect( KILL cr );
10931 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10932 "MOVSD [ESP],$src\n\t"
10933 "FLD_D [ESP]\n\t"
10934 "FLDCW trunc mode\n\t"
10935 "FISTp [ESP + #0]\n\t"
10936 "FLDCW std/24-bit mode\n\t"
10937 "POP EAX\n\t"
10938 "POP EDX\n\t"
10939 "CMP EDX,0x80000000\n\t"
10940 "JNE,s fast\n\t"
10941 "TEST EAX,EAX\n\t"
10942 "JNE,s fast\n\t"
10943 "SUB ESP,8\n\t"
10944 "MOVSD [ESP],$src\n\t"
10945 "FLD_D [ESP]\n\t"
10946 "ADD ESP,8\n\t"
10947 "CALL d2l_wrapper\n"
10948 "fast:" %}
10949 ins_encode %{
10950 Label fast;
10951 __ subptr(rsp, 8);
10952 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10953 __ fld_d(Address(rsp, 0));
10954 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10955 __ fistp_d(Address(rsp, 0));
10956 // Restore the rounding mode, mask the exception
10957 if (Compile::current()->in_24_bit_fp_mode()) {
10958 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10959 } else {
10960 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10961 }
10962 // Load the converted long, adjust CPU stack
10963 __ pop(rax);
10964 __ pop(rdx);
10965 __ cmpl(rdx, 0x80000000);
10966 __ jccb(Assembler::notEqual, fast);
10967 __ testl(rax, rax);
10968 __ jccb(Assembler::notEqual, fast);
10969 __ subptr(rsp, 8);
10970 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10971 __ fld_d(Address(rsp, 0));
10972 __ addptr(rsp, 8);
10973 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10974 __ bind(fast);
10975 %}
10976 ins_pipe( pipe_slow );
10977 %}
10978
10979 // Convert a double to an int. Java semantics require we do complex
10980 // manglations in the corner cases. So we set the rounding mode to
10981 // 'zero', store the darned double down as an int, and reset the
10982 // rounding mode to 'nearest'. The hardware stores a flag value down
10983 // if we would overflow or converted a NAN; we check for this and
10984 // and go the slow path if needed.
10985 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10986 predicate(UseSSE==0);
10987 match(Set dst (ConvF2I src));
10988 effect( KILL tmp, KILL cr );
10989 format %{ "FLD $src\t# Convert float to int \n\t"
10990 "FLDCW trunc mode\n\t"
10991 "SUB ESP,4\n\t"
10992 "FISTp [ESP + #0]\n\t"
10993 "FLDCW std/24-bit mode\n\t"
10994 "POP EAX\n\t"
10995 "CMP EAX,0x80000000\n\t"
10996 "JNE,s fast\n\t"
10997 "FLD $src\n\t"
10998 "CALL d2i_wrapper\n"
10999 "fast:" %}
11000 // DPR2I_encoding works for FPR2I
11001 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11002 ins_pipe( pipe_slow );
11003 %}
11004
11005 // Convert a float in xmm to an int reg.
11006 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11007 predicate(UseSSE>=1);
11008 match(Set dst (ConvF2I src));
11009 effect( KILL tmp, KILL cr );
11010 format %{ "CVTTSS2SI $dst, $src\n\t"
11011 "CMP $dst,0x80000000\n\t"
11012 "JNE,s fast\n\t"
11013 "SUB ESP, 4\n\t"
11014 "MOVSS [ESP], $src\n\t"
11015 "FLD [ESP]\n\t"
11016 "ADD ESP, 4\n\t"
11017 "CALL d2i_wrapper\n"
11018 "fast:" %}
11019 ins_encode %{
11020 Label fast;
11021 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11022 __ cmpl($dst$$Register, 0x80000000);
11023 __ jccb(Assembler::notEqual, fast);
11024 __ subptr(rsp, 4);
11025 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11026 __ fld_s(Address(rsp, 0));
11027 __ addptr(rsp, 4);
11028 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11029 __ bind(fast);
11030 %}
11031 ins_pipe( pipe_slow );
11032 %}
11033
11034 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11035 predicate(UseSSE==0);
11036 match(Set dst (ConvF2L src));
11037 effect( KILL cr );
11038 format %{ "FLD $src\t# Convert float to long\n\t"
11039 "FLDCW trunc mode\n\t"
11040 "SUB ESP,8\n\t"
11041 "FISTp [ESP + #0]\n\t"
11042 "FLDCW std/24-bit mode\n\t"
11043 "POP EAX\n\t"
11044 "POP EDX\n\t"
11045 "CMP EDX,0x80000000\n\t"
11046 "JNE,s fast\n\t"
11047 "TEST EAX,EAX\n\t"
11048 "JNE,s fast\n\t"
11049 "FLD $src\n\t"
11050 "CALL d2l_wrapper\n"
11051 "fast:" %}
11052 // DPR2L_encoding works for FPR2L
11053 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11054 ins_pipe( pipe_slow );
11055 %}
11056
11057 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11058 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11059 predicate (UseSSE>=1);
11060 match(Set dst (ConvF2L src));
11061 effect( KILL cr );
11062 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11063 "MOVSS [ESP],$src\n\t"
11064 "FLD_S [ESP]\n\t"
11065 "FLDCW trunc mode\n\t"
11066 "FISTp [ESP + #0]\n\t"
11067 "FLDCW std/24-bit mode\n\t"
11068 "POP EAX\n\t"
11069 "POP EDX\n\t"
11070 "CMP EDX,0x80000000\n\t"
11071 "JNE,s fast\n\t"
11072 "TEST EAX,EAX\n\t"
11073 "JNE,s fast\n\t"
11074 "SUB ESP,4\t# Convert float to long\n\t"
11075 "MOVSS [ESP],$src\n\t"
11076 "FLD_S [ESP]\n\t"
11077 "ADD ESP,4\n\t"
11078 "CALL d2l_wrapper\n"
11079 "fast:" %}
11080 ins_encode %{
11081 Label fast;
11082 __ subptr(rsp, 8);
11083 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11084 __ fld_s(Address(rsp, 0));
11085 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11086 __ fistp_d(Address(rsp, 0));
11087 // Restore the rounding mode, mask the exception
11088 if (Compile::current()->in_24_bit_fp_mode()) {
11089 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11090 } else {
11091 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11092 }
11093 // Load the converted long, adjust CPU stack
11094 __ pop(rax);
11095 __ pop(rdx);
11096 __ cmpl(rdx, 0x80000000);
11097 __ jccb(Assembler::notEqual, fast);
11098 __ testl(rax, rax);
11099 __ jccb(Assembler::notEqual, fast);
11100 __ subptr(rsp, 4);
11101 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11102 __ fld_s(Address(rsp, 0));
11103 __ addptr(rsp, 4);
11104 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11105 __ bind(fast);
11106 %}
11107 ins_pipe( pipe_slow );
11108 %}
11109
11110 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11111 predicate( UseSSE<=1 );
11112 match(Set dst (ConvI2D src));
11113 format %{ "FILD $src\n\t"
11114 "FSTP $dst" %}
11115 opcode(0xDB, 0x0); /* DB /0 */
11116 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11117 ins_pipe( fpu_reg_mem );
11118 %}
11119
11120 instruct convI2D_reg(regD dst, rRegI src) %{
11121 predicate( UseSSE>=2 && !UseXmmI2D );
11122 match(Set dst (ConvI2D src));
11123 format %{ "CVTSI2SD $dst,$src" %}
11124 ins_encode %{
11125 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11126 %}
11127 ins_pipe( pipe_slow );
11128 %}
11129
11130 instruct convI2D_mem(regD dst, memory mem) %{
11131 predicate( UseSSE>=2 );
11132 match(Set dst (ConvI2D (LoadI mem)));
11133 format %{ "CVTSI2SD $dst,$mem" %}
11134 ins_encode %{
11135 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11136 %}
11137 ins_pipe( pipe_slow );
11138 %}
11139
11140 instruct convXI2D_reg(regD dst, rRegI src)
11141 %{
11142 predicate( UseSSE>=2 && UseXmmI2D );
11143 match(Set dst (ConvI2D src));
11144
11145 format %{ "MOVD $dst,$src\n\t"
11146 "CVTDQ2PD $dst,$dst\t# i2d" %}
11147 ins_encode %{
11148 __ movdl($dst$$XMMRegister, $src$$Register);
11149 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11150 %}
11151 ins_pipe(pipe_slow); // XXX
11152 %}
11153
11154 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11155 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11156 match(Set dst (ConvI2D (LoadI mem)));
11157 format %{ "FILD $mem\n\t"
11158 "FSTP $dst" %}
11159 opcode(0xDB); /* DB /0 */
11160 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11161 Pop_Reg_DPR(dst));
11162 ins_pipe( fpu_reg_mem );
11163 %}
11164
11165 // Convert a byte to a float; no rounding step needed.
11166 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11167 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11168 match(Set dst (ConvI2F src));
11169 format %{ "FILD $src\n\t"
11170 "FSTP $dst" %}
11171
11172 opcode(0xDB, 0x0); /* DB /0 */
11173 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11174 ins_pipe( fpu_reg_mem );
11175 %}
11176
11177 // In 24-bit mode, force exponent rounding by storing back out
11178 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11179 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11180 match(Set dst (ConvI2F src));
11181 ins_cost(200);
11182 format %{ "FILD $src\n\t"
11183 "FSTP_S $dst" %}
11184 opcode(0xDB, 0x0); /* DB /0 */
11185 ins_encode( Push_Mem_I(src),
11186 Pop_Mem_FPR(dst));
11187 ins_pipe( fpu_mem_mem );
11188 %}
11189
11190 // In 24-bit mode, force exponent rounding by storing back out
11191 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11192 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11193 match(Set dst (ConvI2F (LoadI mem)));
11194 ins_cost(200);
11195 format %{ "FILD $mem\n\t"
11196 "FSTP_S $dst" %}
11197 opcode(0xDB); /* DB /0 */
11198 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11199 Pop_Mem_FPR(dst));
11200 ins_pipe( fpu_mem_mem );
11201 %}
11202
11203 // This instruction does not round to 24-bits
11204 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11205 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11206 match(Set dst (ConvI2F src));
11207 format %{ "FILD $src\n\t"
11208 "FSTP $dst" %}
11209 opcode(0xDB, 0x0); /* DB /0 */
11210 ins_encode( Push_Mem_I(src),
11211 Pop_Reg_FPR(dst));
11212 ins_pipe( fpu_reg_mem );
11213 %}
11214
11215 // This instruction does not round to 24-bits
11216 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11217 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11218 match(Set dst (ConvI2F (LoadI mem)));
11219 format %{ "FILD $mem\n\t"
11220 "FSTP $dst" %}
11221 opcode(0xDB); /* DB /0 */
11222 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11223 Pop_Reg_FPR(dst));
11224 ins_pipe( fpu_reg_mem );
11225 %}
11226
11227 // Convert an int to a float in xmm; no rounding step needed.
11228 instruct convI2F_reg(regF dst, rRegI src) %{
11229 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11230 match(Set dst (ConvI2F src));
11231 format %{ "CVTSI2SS $dst, $src" %}
11232 ins_encode %{
11233 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11234 %}
11235 ins_pipe( pipe_slow );
11236 %}
11237
11238 instruct convXI2F_reg(regF dst, rRegI src)
11239 %{
11240 predicate( UseSSE>=2 && UseXmmI2F );
11241 match(Set dst (ConvI2F src));
11242
11243 format %{ "MOVD $dst,$src\n\t"
11244 "CVTDQ2PS $dst,$dst\t# i2f" %}
11245 ins_encode %{
11246 __ movdl($dst$$XMMRegister, $src$$Register);
11247 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11248 %}
11249 ins_pipe(pipe_slow); // XXX
11250 %}
11251
11252 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11253 match(Set dst (ConvI2L src));
11254 effect(KILL cr);
11255 ins_cost(375);
11256 format %{ "MOV $dst.lo,$src\n\t"
11257 "MOV $dst.hi,$src\n\t"
11258 "SAR $dst.hi,31" %}
11259 ins_encode(convert_int_long(dst,src));
11260 ins_pipe( ialu_reg_reg_long );
11261 %}
11262
11263 // Zero-extend convert int to long
11264 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11265 match(Set dst (AndL (ConvI2L src) mask) );
11266 effect( KILL flags );
11267 ins_cost(250);
11268 format %{ "MOV $dst.lo,$src\n\t"
11269 "XOR $dst.hi,$dst.hi" %}
11270 opcode(0x33); // XOR
11271 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11272 ins_pipe( ialu_reg_reg_long );
11273 %}
11274
11275 // Zero-extend long
11276 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11277 match(Set dst (AndL src mask) );
11278 effect( KILL flags );
11279 ins_cost(250);
11280 format %{ "MOV $dst.lo,$src.lo\n\t"
11281 "XOR $dst.hi,$dst.hi\n\t" %}
11282 opcode(0x33); // XOR
11283 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11284 ins_pipe( ialu_reg_reg_long );
11285 %}
11286
11287 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11288 predicate (UseSSE<=1);
11289 match(Set dst (ConvL2D src));
11290 effect( KILL cr );
11291 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11292 "PUSH $src.lo\n\t"
11293 "FILD ST,[ESP + #0]\n\t"
11294 "ADD ESP,8\n\t"
11295 "FSTP_D $dst\t# D-round" %}
11296 opcode(0xDF, 0x5); /* DF /5 */
11297 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11298 ins_pipe( pipe_slow );
11299 %}
11300
11301 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11302 predicate (UseSSE>=2);
11303 match(Set dst (ConvL2D src));
11304 effect( KILL cr );
11305 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11306 "PUSH $src.lo\n\t"
11307 "FILD_D [ESP]\n\t"
11308 "FSTP_D [ESP]\n\t"
11309 "MOVSD $dst,[ESP]\n\t"
11310 "ADD ESP,8" %}
11311 opcode(0xDF, 0x5); /* DF /5 */
11312 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11313 ins_pipe( pipe_slow );
11314 %}
11315
11316 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11317 predicate (UseSSE>=1);
11318 match(Set dst (ConvL2F src));
11319 effect( KILL cr );
11320 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11321 "PUSH $src.lo\n\t"
11322 "FILD_D [ESP]\n\t"
11323 "FSTP_S [ESP]\n\t"
11324 "MOVSS $dst,[ESP]\n\t"
11325 "ADD ESP,8" %}
11326 opcode(0xDF, 0x5); /* DF /5 */
11327 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11328 ins_pipe( pipe_slow );
11329 %}
11330
11331 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11332 match(Set dst (ConvL2F src));
11333 effect( KILL cr );
11334 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11335 "PUSH $src.lo\n\t"
11336 "FILD ST,[ESP + #0]\n\t"
11337 "ADD ESP,8\n\t"
11338 "FSTP_S $dst\t# F-round" %}
11339 opcode(0xDF, 0x5); /* DF /5 */
11340 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11341 ins_pipe( pipe_slow );
11342 %}
11343
11344 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11345 match(Set dst (ConvL2I src));
11346 effect( DEF dst, USE src );
11347 format %{ "MOV $dst,$src.lo" %}
11348 ins_encode(enc_CopyL_Lo(dst,src));
11349 ins_pipe( ialu_reg_reg );
11350 %}
11351
11352
11353 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11354 match(Set dst (MoveF2I src));
11355 effect( DEF dst, USE src );
11356 ins_cost(100);
11357 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11358 ins_encode %{
11359 __ movl($dst$$Register, Address(rsp, $src$$disp));
11360 %}
11361 ins_pipe( ialu_reg_mem );
11362 %}
11363
11364 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11365 predicate(UseSSE==0);
11366 match(Set dst (MoveF2I src));
11367 effect( DEF dst, USE src );
11368
11369 ins_cost(125);
11370 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11371 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11372 ins_pipe( fpu_mem_reg );
11373 %}
11374
11375 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11376 predicate(UseSSE>=1);
11377 match(Set dst (MoveF2I src));
11378 effect( DEF dst, USE src );
11379
11380 ins_cost(95);
11381 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11382 ins_encode %{
11383 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11384 %}
11385 ins_pipe( pipe_slow );
11386 %}
11387
11388 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11389 predicate(UseSSE>=2);
11390 match(Set dst (MoveF2I src));
11391 effect( DEF dst, USE src );
11392 ins_cost(85);
11393 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11394 ins_encode %{
11395 __ movdl($dst$$Register, $src$$XMMRegister);
11396 %}
11397 ins_pipe( pipe_slow );
11398 %}
11399
11400 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11401 match(Set dst (MoveI2F src));
11402 effect( DEF dst, USE src );
11403
11404 ins_cost(100);
11405 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11406 ins_encode %{
11407 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11408 %}
11409 ins_pipe( ialu_mem_reg );
11410 %}
11411
11412
11413 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11414 predicate(UseSSE==0);
11415 match(Set dst (MoveI2F src));
11416 effect(DEF dst, USE src);
11417
11418 ins_cost(125);
11419 format %{ "FLD_S $src\n\t"
11420 "FSTP $dst\t# MoveI2F_stack_reg" %}
11421 opcode(0xD9); /* D9 /0, FLD m32real */
11422 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11423 Pop_Reg_FPR(dst) );
11424 ins_pipe( fpu_reg_mem );
11425 %}
11426
11427 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11428 predicate(UseSSE>=1);
11429 match(Set dst (MoveI2F src));
11430 effect( DEF dst, USE src );
11431
11432 ins_cost(95);
11433 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11434 ins_encode %{
11435 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11436 %}
11437 ins_pipe( pipe_slow );
11438 %}
11439
11440 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11441 predicate(UseSSE>=2);
11442 match(Set dst (MoveI2F src));
11443 effect( DEF dst, USE src );
11444
11445 ins_cost(85);
11446 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11447 ins_encode %{
11448 __ movdl($dst$$XMMRegister, $src$$Register);
11449 %}
11450 ins_pipe( pipe_slow );
11451 %}
11452
11453 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11454 match(Set dst (MoveD2L src));
11455 effect(DEF dst, USE src);
11456
11457 ins_cost(250);
11458 format %{ "MOV $dst.lo,$src\n\t"
11459 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11460 opcode(0x8B, 0x8B);
11461 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11462 ins_pipe( ialu_mem_long_reg );
11463 %}
11464
11465 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11466 predicate(UseSSE<=1);
11467 match(Set dst (MoveD2L src));
11468 effect(DEF dst, USE src);
11469
11470 ins_cost(125);
11471 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11472 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11473 ins_pipe( fpu_mem_reg );
11474 %}
11475
11476 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11477 predicate(UseSSE>=2);
11478 match(Set dst (MoveD2L src));
11479 effect(DEF dst, USE src);
11480 ins_cost(95);
11481 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11482 ins_encode %{
11483 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11484 %}
11485 ins_pipe( pipe_slow );
11486 %}
11487
11488 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11489 predicate(UseSSE>=2);
11490 match(Set dst (MoveD2L src));
11491 effect(DEF dst, USE src, TEMP tmp);
11492 ins_cost(85);
11493 format %{ "MOVD $dst.lo,$src\n\t"
11494 "PSHUFLW $tmp,$src,0x4E\n\t"
11495 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11496 ins_encode %{
11497 __ movdl($dst$$Register, $src$$XMMRegister);
11498 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11499 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11500 %}
11501 ins_pipe( pipe_slow );
11502 %}
11503
11504 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11505 match(Set dst (MoveL2D src));
11506 effect(DEF dst, USE src);
11507
11508 ins_cost(200);
11509 format %{ "MOV $dst,$src.lo\n\t"
11510 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11511 opcode(0x89, 0x89);
11512 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11513 ins_pipe( ialu_mem_long_reg );
11514 %}
11515
11516
11517 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11518 predicate(UseSSE<=1);
11519 match(Set dst (MoveL2D src));
11520 effect(DEF dst, USE src);
11521 ins_cost(125);
11522
11523 format %{ "FLD_D $src\n\t"
11524 "FSTP $dst\t# MoveL2D_stack_reg" %}
11525 opcode(0xDD); /* DD /0, FLD m64real */
11526 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11527 Pop_Reg_DPR(dst) );
11528 ins_pipe( fpu_reg_mem );
11529 %}
11530
11531
11532 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11533 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11534 match(Set dst (MoveL2D src));
11535 effect(DEF dst, USE src);
11536
11537 ins_cost(95);
11538 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11539 ins_encode %{
11540 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11541 %}
11542 ins_pipe( pipe_slow );
11543 %}
11544
11545 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11546 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11547 match(Set dst (MoveL2D src));
11548 effect(DEF dst, USE src);
11549
11550 ins_cost(95);
11551 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11552 ins_encode %{
11553 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11554 %}
11555 ins_pipe( pipe_slow );
11556 %}
11557
11558 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11559 predicate(UseSSE>=2);
11560 match(Set dst (MoveL2D src));
11561 effect(TEMP dst, USE src, TEMP tmp);
11562 ins_cost(85);
11563 format %{ "MOVD $dst,$src.lo\n\t"
11564 "MOVD $tmp,$src.hi\n\t"
11565 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11566 ins_encode %{
11567 __ movdl($dst$$XMMRegister, $src$$Register);
11568 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11569 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11570 %}
11571 ins_pipe( pipe_slow );
11572 %}
11573
11574
11575 // =======================================================================
11576 // fast clearing of an array
11577 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11578 match(Set dummy (ClearArray cnt base));
11579 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11580 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11581 "XOR EAX,EAX\n\t"
11582 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11583 opcode(0,0x4);
11584 ins_encode( Opcode(0xD1), RegOpc(ECX),
11585 OpcRegReg(0x33,EAX,EAX),
11586 Opcode(0xF3), Opcode(0xAB) );
11587 ins_pipe( pipe_slow );
11588 %}
11589
11590 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11591 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11592 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11593 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11594
11595 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11596 ins_encode %{
11597 __ string_compare($str1$$Register, $str2$$Register,
11598 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11599 $tmp1$$XMMRegister);
11600 %}
11601 ins_pipe( pipe_slow );
11602 %}
11603
11604 // fast string equals
11605 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11606 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11607 match(Set result (StrEquals (Binary str1 str2) cnt));
11608 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11609
11610 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11611 ins_encode %{
11612 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11613 $cnt$$Register, $result$$Register, $tmp3$$Register,
11614 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11615 %}
11616 ins_pipe( pipe_slow );
11617 %}
11618
11619 // fast search of substring with known size.
11620 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11621 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11622 predicate(UseSSE42Intrinsics);
11623 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11624 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11625
11626 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11627 ins_encode %{
11628 int icnt2 = (int)$int_cnt2$$constant;
11629 if (icnt2 >= 8) {
11630 // IndexOf for constant substrings with size >= 8 elements
11631 // which don't need to be loaded through stack.
11632 __ string_indexofC8($str1$$Register, $str2$$Register,
11633 $cnt1$$Register, $cnt2$$Register,
11634 icnt2, $result$$Register,
11635 $vec$$XMMRegister, $tmp$$Register);
11636 } else {
11637 // Small strings are loaded through stack if they cross page boundary.
11638 __ string_indexof($str1$$Register, $str2$$Register,
11639 $cnt1$$Register, $cnt2$$Register,
11640 icnt2, $result$$Register,
11641 $vec$$XMMRegister, $tmp$$Register);
11642 }
11643 %}
11644 ins_pipe( pipe_slow );
11645 %}
11646
11647 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11648 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11649 predicate(UseSSE42Intrinsics);
11650 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11651 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11652
11653 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11654 ins_encode %{
11655 __ string_indexof($str1$$Register, $str2$$Register,
11656 $cnt1$$Register, $cnt2$$Register,
11657 (-1), $result$$Register,
11658 $vec$$XMMRegister, $tmp$$Register);
11659 %}
11660 ins_pipe( pipe_slow );
11661 %}
11662
11663 // fast array equals
11664 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11665 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11666 %{
11667 match(Set result (AryEq ary1 ary2));
11668 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11669 //ins_cost(300);
11670
11671 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11672 ins_encode %{
11673 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11674 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11675 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11676 %}
11677 ins_pipe( pipe_slow );
11678 %}
11679
11680 //----------Control Flow Instructions------------------------------------------
11681 // Signed compare Instructions
11682 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11683 match(Set cr (CmpI op1 op2));
11684 effect( DEF cr, USE op1, USE op2 );
11685 format %{ "CMP $op1,$op2" %}
11686 opcode(0x3B); /* Opcode 3B /r */
11687 ins_encode( OpcP, RegReg( op1, op2) );
11688 ins_pipe( ialu_cr_reg_reg );
11689 %}
11690
11691 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11692 match(Set cr (CmpI op1 op2));
11693 effect( DEF cr, USE op1 );
11694 format %{ "CMP $op1,$op2" %}
11695 opcode(0x81,0x07); /* Opcode 81 /7 */
11696 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11697 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11698 ins_pipe( ialu_cr_reg_imm );
11699 %}
11700
11701 // Cisc-spilled version of cmpI_eReg
11702 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11703 match(Set cr (CmpI op1 (LoadI op2)));
11704
11705 format %{ "CMP $op1,$op2" %}
11706 ins_cost(500);
11707 opcode(0x3B); /* Opcode 3B /r */
11708 ins_encode( OpcP, RegMem( op1, op2) );
11709 ins_pipe( ialu_cr_reg_mem );
11710 %}
11711
11712 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11713 match(Set cr (CmpI src zero));
11714 effect( DEF cr, USE src );
11715
11716 format %{ "TEST $src,$src" %}
11717 opcode(0x85);
11718 ins_encode( OpcP, RegReg( src, src ) );
11719 ins_pipe( ialu_cr_reg_imm );
11720 %}
11721
11722 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11723 match(Set cr (CmpI (AndI src con) zero));
11724
11725 format %{ "TEST $src,$con" %}
11726 opcode(0xF7,0x00);
11727 ins_encode( OpcP, RegOpc(src), Con32(con) );
11728 ins_pipe( ialu_cr_reg_imm );
11729 %}
11730
11731 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11732 match(Set cr (CmpI (AndI src mem) zero));
11733
11734 format %{ "TEST $src,$mem" %}
11735 opcode(0x85);
11736 ins_encode( OpcP, RegMem( src, mem ) );
11737 ins_pipe( ialu_cr_reg_mem );
11738 %}
11739
11740 // Unsigned compare Instructions; really, same as signed except they
11741 // produce an eFlagsRegU instead of eFlagsReg.
11742 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11743 match(Set cr (CmpU op1 op2));
11744
11745 format %{ "CMPu $op1,$op2" %}
11746 opcode(0x3B); /* Opcode 3B /r */
11747 ins_encode( OpcP, RegReg( op1, op2) );
11748 ins_pipe( ialu_cr_reg_reg );
11749 %}
11750
11751 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11752 match(Set cr (CmpU op1 op2));
11753
11754 format %{ "CMPu $op1,$op2" %}
11755 opcode(0x81,0x07); /* Opcode 81 /7 */
11756 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11757 ins_pipe( ialu_cr_reg_imm );
11758 %}
11759
11760 // // Cisc-spilled version of cmpU_eReg
11761 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11762 match(Set cr (CmpU op1 (LoadI op2)));
11763
11764 format %{ "CMPu $op1,$op2" %}
11765 ins_cost(500);
11766 opcode(0x3B); /* Opcode 3B /r */
11767 ins_encode( OpcP, RegMem( op1, op2) );
11768 ins_pipe( ialu_cr_reg_mem );
11769 %}
11770
11771 // // Cisc-spilled version of cmpU_eReg
11772 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11773 // match(Set cr (CmpU (LoadI op1) op2));
11774 //
11775 // format %{ "CMPu $op1,$op2" %}
11776 // ins_cost(500);
11777 // opcode(0x39); /* Opcode 39 /r */
11778 // ins_encode( OpcP, RegMem( op1, op2) );
11779 //%}
11780
11781 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11782 match(Set cr (CmpU src zero));
11783
11784 format %{ "TESTu $src,$src" %}
11785 opcode(0x85);
11786 ins_encode( OpcP, RegReg( src, src ) );
11787 ins_pipe( ialu_cr_reg_imm );
11788 %}
11789
11790 // Unsigned pointer compare Instructions
11791 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11792 match(Set cr (CmpP op1 op2));
11793
11794 format %{ "CMPu $op1,$op2" %}
11795 opcode(0x3B); /* Opcode 3B /r */
11796 ins_encode( OpcP, RegReg( op1, op2) );
11797 ins_pipe( ialu_cr_reg_reg );
11798 %}
11799
11800 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11801 match(Set cr (CmpP op1 op2));
11802
11803 format %{ "CMPu $op1,$op2" %}
11804 opcode(0x81,0x07); /* Opcode 81 /7 */
11805 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11806 ins_pipe( ialu_cr_reg_imm );
11807 %}
11808
11809 // // Cisc-spilled version of cmpP_eReg
11810 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11811 match(Set cr (CmpP op1 (LoadP op2)));
11812
11813 format %{ "CMPu $op1,$op2" %}
11814 ins_cost(500);
11815 opcode(0x3B); /* Opcode 3B /r */
11816 ins_encode( OpcP, RegMem( op1, op2) );
11817 ins_pipe( ialu_cr_reg_mem );
11818 %}
11819
11820 // // Cisc-spilled version of cmpP_eReg
11821 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11822 // match(Set cr (CmpP (LoadP op1) op2));
11823 //
11824 // format %{ "CMPu $op1,$op2" %}
11825 // ins_cost(500);
11826 // opcode(0x39); /* Opcode 39 /r */
11827 // ins_encode( OpcP, RegMem( op1, op2) );
11828 //%}
11829
11830 // Compare raw pointer (used in out-of-heap check).
11831 // Only works because non-oop pointers must be raw pointers
11832 // and raw pointers have no anti-dependencies.
11833 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11834 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11835 match(Set cr (CmpP op1 (LoadP op2)));
11836
11837 format %{ "CMPu $op1,$op2" %}
11838 opcode(0x3B); /* Opcode 3B /r */
11839 ins_encode( OpcP, RegMem( op1, op2) );
11840 ins_pipe( ialu_cr_reg_mem );
11841 %}
11842
11843 //
11844 // This will generate a signed flags result. This should be ok
11845 // since any compare to a zero should be eq/neq.
11846 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11847 match(Set cr (CmpP src zero));
11848
11849 format %{ "TEST $src,$src" %}
11850 opcode(0x85);
11851 ins_encode( OpcP, RegReg( src, src ) );
11852 ins_pipe( ialu_cr_reg_imm );
11853 %}
11854
11855 // Cisc-spilled version of testP_reg
11856 // This will generate a signed flags result. This should be ok
11857 // since any compare to a zero should be eq/neq.
11858 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11859 match(Set cr (CmpP (LoadP op) zero));
11860
11861 format %{ "TEST $op,0xFFFFFFFF" %}
11862 ins_cost(500);
11863 opcode(0xF7); /* Opcode F7 /0 */
11864 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11865 ins_pipe( ialu_cr_reg_imm );
11866 %}
11867
11868 // Yanked all unsigned pointer compare operations.
11869 // Pointer compares are done with CmpP which is already unsigned.
11870
11871 //----------Max and Min--------------------------------------------------------
11872 // Min Instructions
11873 ////
11874 // *** Min and Max using the conditional move are slower than the
11875 // *** branch version on a Pentium III.
11876 // // Conditional move for min
11877 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11878 // effect( USE_DEF op2, USE op1, USE cr );
11879 // format %{ "CMOVlt $op2,$op1\t! min" %}
11880 // opcode(0x4C,0x0F);
11881 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11882 // ins_pipe( pipe_cmov_reg );
11883 //%}
11884 //
11885 //// Min Register with Register (P6 version)
11886 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11887 // predicate(VM_Version::supports_cmov() );
11888 // match(Set op2 (MinI op1 op2));
11889 // ins_cost(200);
11890 // expand %{
11891 // eFlagsReg cr;
11892 // compI_eReg(cr,op1,op2);
11893 // cmovI_reg_lt(op2,op1,cr);
11894 // %}
11895 //%}
11896
11897 // Min Register with Register (generic version)
11898 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11899 match(Set dst (MinI dst src));
11900 effect(KILL flags);
11901 ins_cost(300);
11902
11903 format %{ "MIN $dst,$src" %}
11904 opcode(0xCC);
11905 ins_encode( min_enc(dst,src) );
11906 ins_pipe( pipe_slow );
11907 %}
11908
11909 // Max Register with Register
11910 // *** Min and Max using the conditional move are slower than the
11911 // *** branch version on a Pentium III.
11912 // // Conditional move for max
11913 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11914 // effect( USE_DEF op2, USE op1, USE cr );
11915 // format %{ "CMOVgt $op2,$op1\t! max" %}
11916 // opcode(0x4F,0x0F);
11917 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11918 // ins_pipe( pipe_cmov_reg );
11919 //%}
11920 //
11921 // // Max Register with Register (P6 version)
11922 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11923 // predicate(VM_Version::supports_cmov() );
11924 // match(Set op2 (MaxI op1 op2));
11925 // ins_cost(200);
11926 // expand %{
11927 // eFlagsReg cr;
11928 // compI_eReg(cr,op1,op2);
11929 // cmovI_reg_gt(op2,op1,cr);
11930 // %}
11931 //%}
11932
11933 // Max Register with Register (generic version)
11934 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11935 match(Set dst (MaxI dst src));
11936 effect(KILL flags);
11937 ins_cost(300);
11938
11939 format %{ "MAX $dst,$src" %}
11940 opcode(0xCC);
11941 ins_encode( max_enc(dst,src) );
11942 ins_pipe( pipe_slow );
11943 %}
11944
11945 // ============================================================================
11946 // Counted Loop limit node which represents exact final iterator value.
11947 // Note: the resulting value should fit into integer range since
11948 // counted loops have limit check on overflow.
11949 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11950 match(Set limit (LoopLimit (Binary init limit) stride));
11951 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11952 ins_cost(300);
11953
11954 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11955 ins_encode %{
11956 int strd = (int)$stride$$constant;
11957 assert(strd != 1 && strd != -1, "sanity");
11958 int m1 = (strd > 0) ? 1 : -1;
11959 // Convert limit to long (EAX:EDX)
11960 __ cdql();
11961 // Convert init to long (init:tmp)
11962 __ movl($tmp$$Register, $init$$Register);
11963 __ sarl($tmp$$Register, 31);
11964 // $limit - $init
11965 __ subl($limit$$Register, $init$$Register);
11966 __ sbbl($limit_hi$$Register, $tmp$$Register);
11967 // + ($stride - 1)
11968 if (strd > 0) {
11969 __ addl($limit$$Register, (strd - 1));
11970 __ adcl($limit_hi$$Register, 0);
11971 __ movl($tmp$$Register, strd);
11972 } else {
11973 __ addl($limit$$Register, (strd + 1));
11974 __ adcl($limit_hi$$Register, -1);
11975 __ lneg($limit_hi$$Register, $limit$$Register);
11976 __ movl($tmp$$Register, -strd);
11977 }
11978 // signed devision: (EAX:EDX) / pos_stride
11979 __ idivl($tmp$$Register);
11980 if (strd < 0) {
11981 // restore sign
11982 __ negl($tmp$$Register);
11983 }
11984 // (EAX) * stride
11985 __ mull($tmp$$Register);
11986 // + init (ignore upper bits)
11987 __ addl($limit$$Register, $init$$Register);
11988 %}
11989 ins_pipe( pipe_slow );
11990 %}
11991
11992 // ============================================================================
11993 // Branch Instructions
11994 // Jump Table
11995 instruct jumpXtnd(rRegI switch_val) %{
11996 match(Jump switch_val);
11997 ins_cost(350);
11998 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
11999 ins_encode %{
12000 // Jump to Address(table_base + switch_reg)
12001 Address index(noreg, $switch_val$$Register, Address::times_1);
12002 __ jump(ArrayAddress($constantaddress, index));
12003 %}
12004 ins_pipe(pipe_jmp);
12005 %}
12006
12007 // Jump Direct - Label defines a relative address from JMP+1
12008 instruct jmpDir(label labl) %{
12009 match(Goto);
12010 effect(USE labl);
12011
12012 ins_cost(300);
12013 format %{ "JMP $labl" %}
12014 size(5);
12015 ins_encode %{
12016 Label* L = $labl$$label;
12017 __ jmp(*L, false); // Always long jump
12018 %}
12019 ins_pipe( pipe_jmp );
12020 %}
12021
12022 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12023 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12024 match(If cop cr);
12025 effect(USE labl);
12026
12027 ins_cost(300);
12028 format %{ "J$cop $labl" %}
12029 size(6);
12030 ins_encode %{
12031 Label* L = $labl$$label;
12032 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12033 %}
12034 ins_pipe( pipe_jcc );
12035 %}
12036
12037 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12038 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12039 match(CountedLoopEnd cop cr);
12040 effect(USE labl);
12041
12042 ins_cost(300);
12043 format %{ "J$cop $labl\t# Loop end" %}
12044 size(6);
12045 ins_encode %{
12046 Label* L = $labl$$label;
12047 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12048 %}
12049 ins_pipe( pipe_jcc );
12050 %}
12051
12052 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12053 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12054 match(CountedLoopEnd cop cmp);
12055 effect(USE labl);
12056
12057 ins_cost(300);
12058 format %{ "J$cop,u $labl\t# Loop end" %}
12059 size(6);
12060 ins_encode %{
12061 Label* L = $labl$$label;
12062 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12063 %}
12064 ins_pipe( pipe_jcc );
12065 %}
12066
12067 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12068 match(CountedLoopEnd cop cmp);
12069 effect(USE labl);
12070
12071 ins_cost(200);
12072 format %{ "J$cop,u $labl\t# Loop end" %}
12073 size(6);
12074 ins_encode %{
12075 Label* L = $labl$$label;
12076 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12077 %}
12078 ins_pipe( pipe_jcc );
12079 %}
12080
12081 // Jump Direct Conditional - using unsigned comparison
12082 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12083 match(If cop cmp);
12084 effect(USE labl);
12085
12086 ins_cost(300);
12087 format %{ "J$cop,u $labl" %}
12088 size(6);
12089 ins_encode %{
12090 Label* L = $labl$$label;
12091 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12092 %}
12093 ins_pipe(pipe_jcc);
12094 %}
12095
12096 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12097 match(If cop cmp);
12098 effect(USE labl);
12099
12100 ins_cost(200);
12101 format %{ "J$cop,u $labl" %}
12102 size(6);
12103 ins_encode %{
12104 Label* L = $labl$$label;
12105 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12106 %}
12107 ins_pipe(pipe_jcc);
12108 %}
12109
12110 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12111 match(If cop cmp);
12112 effect(USE labl);
12113
12114 ins_cost(200);
12115 format %{ $$template
12116 if ($cop$$cmpcode == Assembler::notEqual) {
12117 $$emit$$"JP,u $labl\n\t"
12118 $$emit$$"J$cop,u $labl"
12119 } else {
12120 $$emit$$"JP,u done\n\t"
12121 $$emit$$"J$cop,u $labl\n\t"
12122 $$emit$$"done:"
12123 }
12124 %}
12125 ins_encode %{
12126 Label* l = $labl$$label;
12127 if ($cop$$cmpcode == Assembler::notEqual) {
12128 __ jcc(Assembler::parity, *l, false);
12129 __ jcc(Assembler::notEqual, *l, false);
12130 } else if ($cop$$cmpcode == Assembler::equal) {
12131 Label done;
12132 __ jccb(Assembler::parity, done);
12133 __ jcc(Assembler::equal, *l, false);
12134 __ bind(done);
12135 } else {
12136 ShouldNotReachHere();
12137 }
12138 %}
12139 ins_pipe(pipe_jcc);
12140 %}
12141
12142 // ============================================================================
12143 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12144 // array for an instance of the superklass. Set a hidden internal cache on a
12145 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12146 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12147 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12148 match(Set result (PartialSubtypeCheck sub super));
12149 effect( KILL rcx, KILL cr );
12150
12151 ins_cost(1100); // slightly larger than the next version
12152 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12153 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12154 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12155 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12156 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12157 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12158 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12159 "miss:\t" %}
12160
12161 opcode(0x1); // Force a XOR of EDI
12162 ins_encode( enc_PartialSubtypeCheck() );
12163 ins_pipe( pipe_slow );
12164 %}
12165
12166 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12167 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12168 effect( KILL rcx, KILL result );
12169
12170 ins_cost(1000);
12171 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12172 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12173 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12174 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12175 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12176 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12177 "miss:\t" %}
12178
12179 opcode(0x0); // No need to XOR EDI
12180 ins_encode( enc_PartialSubtypeCheck() );
12181 ins_pipe( pipe_slow );
12182 %}
12183
12184 // ============================================================================
12185 // Branch Instructions -- short offset versions
12186 //
12187 // These instructions are used to replace jumps of a long offset (the default
12188 // match) with jumps of a shorter offset. These instructions are all tagged
12189 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12190 // match rules in general matching. Instead, the ADLC generates a conversion
12191 // method in the MachNode which can be used to do in-place replacement of the
12192 // long variant with the shorter variant. The compiler will determine if a
12193 // branch can be taken by the is_short_branch_offset() predicate in the machine
12194 // specific code section of the file.
12195
12196 // Jump Direct - Label defines a relative address from JMP+1
12197 instruct jmpDir_short(label labl) %{
12198 match(Goto);
12199 effect(USE labl);
12200
12201 ins_cost(300);
12202 format %{ "JMP,s $labl" %}
12203 size(2);
12204 ins_encode %{
12205 Label* L = $labl$$label;
12206 __ jmpb(*L);
12207 %}
12208 ins_pipe( pipe_jmp );
12209 ins_short_branch(1);
12210 %}
12211
12212 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12213 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12214 match(If cop cr);
12215 effect(USE labl);
12216
12217 ins_cost(300);
12218 format %{ "J$cop,s $labl" %}
12219 size(2);
12220 ins_encode %{
12221 Label* L = $labl$$label;
12222 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12223 %}
12224 ins_pipe( pipe_jcc );
12225 ins_short_branch(1);
12226 %}
12227
12228 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12229 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12230 match(CountedLoopEnd cop cr);
12231 effect(USE labl);
12232
12233 ins_cost(300);
12234 format %{ "J$cop,s $labl\t# Loop end" %}
12235 size(2);
12236 ins_encode %{
12237 Label* L = $labl$$label;
12238 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12239 %}
12240 ins_pipe( pipe_jcc );
12241 ins_short_branch(1);
12242 %}
12243
12244 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12245 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12246 match(CountedLoopEnd cop cmp);
12247 effect(USE labl);
12248
12249 ins_cost(300);
12250 format %{ "J$cop,us $labl\t# Loop end" %}
12251 size(2);
12252 ins_encode %{
12253 Label* L = $labl$$label;
12254 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12255 %}
12256 ins_pipe( pipe_jcc );
12257 ins_short_branch(1);
12258 %}
12259
12260 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12261 match(CountedLoopEnd cop cmp);
12262 effect(USE labl);
12263
12264 ins_cost(300);
12265 format %{ "J$cop,us $labl\t# Loop end" %}
12266 size(2);
12267 ins_encode %{
12268 Label* L = $labl$$label;
12269 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12270 %}
12271 ins_pipe( pipe_jcc );
12272 ins_short_branch(1);
12273 %}
12274
12275 // Jump Direct Conditional - using unsigned comparison
12276 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12277 match(If cop cmp);
12278 effect(USE labl);
12279
12280 ins_cost(300);
12281 format %{ "J$cop,us $labl" %}
12282 size(2);
12283 ins_encode %{
12284 Label* L = $labl$$label;
12285 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12286 %}
12287 ins_pipe( pipe_jcc );
12288 ins_short_branch(1);
12289 %}
12290
12291 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12292 match(If cop cmp);
12293 effect(USE labl);
12294
12295 ins_cost(300);
12296 format %{ "J$cop,us $labl" %}
12297 size(2);
12298 ins_encode %{
12299 Label* L = $labl$$label;
12300 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12301 %}
12302 ins_pipe( pipe_jcc );
12303 ins_short_branch(1);
12304 %}
12305
12306 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12307 match(If cop cmp);
12308 effect(USE labl);
12309
12310 ins_cost(300);
12311 format %{ $$template
12312 if ($cop$$cmpcode == Assembler::notEqual) {
12313 $$emit$$"JP,u,s $labl\n\t"
12314 $$emit$$"J$cop,u,s $labl"
12315 } else {
12316 $$emit$$"JP,u,s done\n\t"
12317 $$emit$$"J$cop,u,s $labl\n\t"
12318 $$emit$$"done:"
12319 }
12320 %}
12321 size(4);
12322 ins_encode %{
12323 Label* l = $labl$$label;
12324 if ($cop$$cmpcode == Assembler::notEqual) {
12325 __ jccb(Assembler::parity, *l);
12326 __ jccb(Assembler::notEqual, *l);
12327 } else if ($cop$$cmpcode == Assembler::equal) {
12328 Label done;
12329 __ jccb(Assembler::parity, done);
12330 __ jccb(Assembler::equal, *l);
12331 __ bind(done);
12332 } else {
12333 ShouldNotReachHere();
12334 }
12335 %}
12336 ins_pipe(pipe_jcc);
12337 ins_short_branch(1);
12338 %}
12339
12340 // ============================================================================
12341 // Long Compare
12342 //
12343 // Currently we hold longs in 2 registers. Comparing such values efficiently
12344 // is tricky. The flavor of compare used depends on whether we are testing
12345 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12346 // The GE test is the negated LT test. The LE test can be had by commuting
12347 // the operands (yielding a GE test) and then negating; negate again for the
12348 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12349 // NE test is negated from that.
12350
12351 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12352 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12353 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12354 // are collapsed internally in the ADLC's dfa-gen code. The match for
12355 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12356 // foo match ends up with the wrong leaf. One fix is to not match both
12357 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12358 // both forms beat the trinary form of long-compare and both are very useful
12359 // on Intel which has so few registers.
12360
12361 // Manifest a CmpL result in an integer register. Very painful.
12362 // This is the test to avoid.
12363 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12364 match(Set dst (CmpL3 src1 src2));
12365 effect( KILL flags );
12366 ins_cost(1000);
12367 format %{ "XOR $dst,$dst\n\t"
12368 "CMP $src1.hi,$src2.hi\n\t"
12369 "JLT,s m_one\n\t"
12370 "JGT,s p_one\n\t"
12371 "CMP $src1.lo,$src2.lo\n\t"
12372 "JB,s m_one\n\t"
12373 "JEQ,s done\n"
12374 "p_one:\tINC $dst\n\t"
12375 "JMP,s done\n"
12376 "m_one:\tDEC $dst\n"
12377 "done:" %}
12378 ins_encode %{
12379 Label p_one, m_one, done;
12380 __ xorptr($dst$$Register, $dst$$Register);
12381 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12382 __ jccb(Assembler::less, m_one);
12383 __ jccb(Assembler::greater, p_one);
12384 __ cmpl($src1$$Register, $src2$$Register);
12385 __ jccb(Assembler::below, m_one);
12386 __ jccb(Assembler::equal, done);
12387 __ bind(p_one);
12388 __ incrementl($dst$$Register);
12389 __ jmpb(done);
12390 __ bind(m_one);
12391 __ decrementl($dst$$Register);
12392 __ bind(done);
12393 %}
12394 ins_pipe( pipe_slow );
12395 %}
12396
12397 //======
12398 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12399 // compares. Can be used for LE or GT compares by reversing arguments.
12400 // NOT GOOD FOR EQ/NE tests.
12401 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12402 match( Set flags (CmpL src zero ));
12403 ins_cost(100);
12404 format %{ "TEST $src.hi,$src.hi" %}
12405 opcode(0x85);
12406 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12407 ins_pipe( ialu_cr_reg_reg );
12408 %}
12409
12410 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12411 // compares. Can be used for LE or GT compares by reversing arguments.
12412 // NOT GOOD FOR EQ/NE tests.
12413 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12414 match( Set flags (CmpL src1 src2 ));
12415 effect( TEMP tmp );
12416 ins_cost(300);
12417 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12418 "MOV $tmp,$src1.hi\n\t"
12419 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12420 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12421 ins_pipe( ialu_cr_reg_reg );
12422 %}
12423
12424 // Long compares reg < zero/req OR reg >= zero/req.
12425 // Just a wrapper for a normal branch, plus the predicate test.
12426 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12427 match(If cmp flags);
12428 effect(USE labl);
12429 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12430 expand %{
12431 jmpCon(cmp,flags,labl); // JLT or JGE...
12432 %}
12433 %}
12434
12435 // Compare 2 longs and CMOVE longs.
12436 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12437 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12438 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12439 ins_cost(400);
12440 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12441 "CMOV$cmp $dst.hi,$src.hi" %}
12442 opcode(0x0F,0x40);
12443 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12444 ins_pipe( pipe_cmov_reg_long );
12445 %}
12446
12447 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12448 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12449 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12450 ins_cost(500);
12451 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12452 "CMOV$cmp $dst.hi,$src.hi" %}
12453 opcode(0x0F,0x40);
12454 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12455 ins_pipe( pipe_cmov_reg_long );
12456 %}
12457
12458 // Compare 2 longs and CMOVE ints.
12459 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12460 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12461 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12462 ins_cost(200);
12463 format %{ "CMOV$cmp $dst,$src" %}
12464 opcode(0x0F,0x40);
12465 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12466 ins_pipe( pipe_cmov_reg );
12467 %}
12468
12469 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12470 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12471 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12472 ins_cost(250);
12473 format %{ "CMOV$cmp $dst,$src" %}
12474 opcode(0x0F,0x40);
12475 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12476 ins_pipe( pipe_cmov_mem );
12477 %}
12478
12479 // Compare 2 longs and CMOVE ints.
12480 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12481 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12482 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12483 ins_cost(200);
12484 format %{ "CMOV$cmp $dst,$src" %}
12485 opcode(0x0F,0x40);
12486 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12487 ins_pipe( pipe_cmov_reg );
12488 %}
12489
12490 // Compare 2 longs and CMOVE doubles
12491 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12492 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12493 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12494 ins_cost(200);
12495 expand %{
12496 fcmovDPR_regS(cmp,flags,dst,src);
12497 %}
12498 %}
12499
12500 // Compare 2 longs and CMOVE doubles
12501 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12502 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12503 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12504 ins_cost(200);
12505 expand %{
12506 fcmovD_regS(cmp,flags,dst,src);
12507 %}
12508 %}
12509
12510 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12511 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12512 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12513 ins_cost(200);
12514 expand %{
12515 fcmovFPR_regS(cmp,flags,dst,src);
12516 %}
12517 %}
12518
12519 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12520 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12521 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12522 ins_cost(200);
12523 expand %{
12524 fcmovF_regS(cmp,flags,dst,src);
12525 %}
12526 %}
12527
12528 //======
12529 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12530 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12531 match( Set flags (CmpL src zero ));
12532 effect(TEMP tmp);
12533 ins_cost(200);
12534 format %{ "MOV $tmp,$src.lo\n\t"
12535 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12536 ins_encode( long_cmp_flags0( src, tmp ) );
12537 ins_pipe( ialu_reg_reg_long );
12538 %}
12539
12540 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12541 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12542 match( Set flags (CmpL src1 src2 ));
12543 ins_cost(200+300);
12544 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12545 "JNE,s skip\n\t"
12546 "CMP $src1.hi,$src2.hi\n\t"
12547 "skip:\t" %}
12548 ins_encode( long_cmp_flags1( src1, src2 ) );
12549 ins_pipe( ialu_cr_reg_reg );
12550 %}
12551
12552 // Long compare reg == zero/reg OR reg != zero/reg
12553 // Just a wrapper for a normal branch, plus the predicate test.
12554 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12555 match(If cmp flags);
12556 effect(USE labl);
12557 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12558 expand %{
12559 jmpCon(cmp,flags,labl); // JEQ or JNE...
12560 %}
12561 %}
12562
12563 // Compare 2 longs and CMOVE longs.
12564 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12565 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12566 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12567 ins_cost(400);
12568 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12569 "CMOV$cmp $dst.hi,$src.hi" %}
12570 opcode(0x0F,0x40);
12571 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12572 ins_pipe( pipe_cmov_reg_long );
12573 %}
12574
12575 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12576 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12577 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12578 ins_cost(500);
12579 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12580 "CMOV$cmp $dst.hi,$src.hi" %}
12581 opcode(0x0F,0x40);
12582 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12583 ins_pipe( pipe_cmov_reg_long );
12584 %}
12585
12586 // Compare 2 longs and CMOVE ints.
12587 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12588 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12589 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12590 ins_cost(200);
12591 format %{ "CMOV$cmp $dst,$src" %}
12592 opcode(0x0F,0x40);
12593 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12594 ins_pipe( pipe_cmov_reg );
12595 %}
12596
12597 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12598 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12599 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12600 ins_cost(250);
12601 format %{ "CMOV$cmp $dst,$src" %}
12602 opcode(0x0F,0x40);
12603 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12604 ins_pipe( pipe_cmov_mem );
12605 %}
12606
12607 // Compare 2 longs and CMOVE ints.
12608 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12609 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12610 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12611 ins_cost(200);
12612 format %{ "CMOV$cmp $dst,$src" %}
12613 opcode(0x0F,0x40);
12614 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12615 ins_pipe( pipe_cmov_reg );
12616 %}
12617
12618 // Compare 2 longs and CMOVE doubles
12619 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12620 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12621 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12622 ins_cost(200);
12623 expand %{
12624 fcmovDPR_regS(cmp,flags,dst,src);
12625 %}
12626 %}
12627
12628 // Compare 2 longs and CMOVE doubles
12629 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12630 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12631 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12632 ins_cost(200);
12633 expand %{
12634 fcmovD_regS(cmp,flags,dst,src);
12635 %}
12636 %}
12637
12638 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12639 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12640 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12641 ins_cost(200);
12642 expand %{
12643 fcmovFPR_regS(cmp,flags,dst,src);
12644 %}
12645 %}
12646
12647 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12648 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12649 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12650 ins_cost(200);
12651 expand %{
12652 fcmovF_regS(cmp,flags,dst,src);
12653 %}
12654 %}
12655
12656 //======
12657 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12658 // Same as cmpL_reg_flags_LEGT except must negate src
12659 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12660 match( Set flags (CmpL src zero ));
12661 effect( TEMP tmp );
12662 ins_cost(300);
12663 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12664 "CMP $tmp,$src.lo\n\t"
12665 "SBB $tmp,$src.hi\n\t" %}
12666 ins_encode( long_cmp_flags3(src, tmp) );
12667 ins_pipe( ialu_reg_reg_long );
12668 %}
12669
12670 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12671 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12672 // requires a commuted test to get the same result.
12673 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12674 match( Set flags (CmpL src1 src2 ));
12675 effect( TEMP tmp );
12676 ins_cost(300);
12677 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12678 "MOV $tmp,$src2.hi\n\t"
12679 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12680 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12681 ins_pipe( ialu_cr_reg_reg );
12682 %}
12683
12684 // Long compares reg < zero/req OR reg >= zero/req.
12685 // Just a wrapper for a normal branch, plus the predicate test
12686 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12687 match(If cmp flags);
12688 effect(USE labl);
12689 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12690 ins_cost(300);
12691 expand %{
12692 jmpCon(cmp,flags,labl); // JGT or JLE...
12693 %}
12694 %}
12695
12696 // Compare 2 longs and CMOVE longs.
12697 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12698 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12699 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12700 ins_cost(400);
12701 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12702 "CMOV$cmp $dst.hi,$src.hi" %}
12703 opcode(0x0F,0x40);
12704 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12705 ins_pipe( pipe_cmov_reg_long );
12706 %}
12707
12708 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12709 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12710 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12711 ins_cost(500);
12712 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12713 "CMOV$cmp $dst.hi,$src.hi+4" %}
12714 opcode(0x0F,0x40);
12715 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12716 ins_pipe( pipe_cmov_reg_long );
12717 %}
12718
12719 // Compare 2 longs and CMOVE ints.
12720 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12721 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12722 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12723 ins_cost(200);
12724 format %{ "CMOV$cmp $dst,$src" %}
12725 opcode(0x0F,0x40);
12726 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12727 ins_pipe( pipe_cmov_reg );
12728 %}
12729
12730 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12731 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12732 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12733 ins_cost(250);
12734 format %{ "CMOV$cmp $dst,$src" %}
12735 opcode(0x0F,0x40);
12736 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12737 ins_pipe( pipe_cmov_mem );
12738 %}
12739
12740 // Compare 2 longs and CMOVE ptrs.
12741 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12742 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12743 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12744 ins_cost(200);
12745 format %{ "CMOV$cmp $dst,$src" %}
12746 opcode(0x0F,0x40);
12747 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12748 ins_pipe( pipe_cmov_reg );
12749 %}
12750
12751 // Compare 2 longs and CMOVE doubles
12752 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12753 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12754 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12755 ins_cost(200);
12756 expand %{
12757 fcmovDPR_regS(cmp,flags,dst,src);
12758 %}
12759 %}
12760
12761 // Compare 2 longs and CMOVE doubles
12762 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12763 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12764 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12765 ins_cost(200);
12766 expand %{
12767 fcmovD_regS(cmp,flags,dst,src);
12768 %}
12769 %}
12770
12771 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12772 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12773 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12774 ins_cost(200);
12775 expand %{
12776 fcmovFPR_regS(cmp,flags,dst,src);
12777 %}
12778 %}
12779
12780
12781 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12782 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12783 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12784 ins_cost(200);
12785 expand %{
12786 fcmovF_regS(cmp,flags,dst,src);
12787 %}
12788 %}
12789
12790
12791 // ============================================================================
12792 // Procedure Call/Return Instructions
12793 // Call Java Static Instruction
12794 // Note: If this code changes, the corresponding ret_addr_offset() and
12795 // compute_padding() functions will have to be adjusted.
12796 instruct CallStaticJavaDirect(method meth) %{
12797 match(CallStaticJava);
12798 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12799 effect(USE meth);
12800
12801 ins_cost(300);
12802 format %{ "CALL,static " %}
12803 opcode(0xE8); /* E8 cd */
12804 ins_encode( pre_call_FPU,
12805 Java_Static_Call( meth ),
12806 call_epilog,
12807 post_call_FPU );
12808 ins_pipe( pipe_slow );
12809 ins_alignment(4);
12810 %}
12811
12812 // Call Java Static Instruction (method handle version)
12813 // Note: If this code changes, the corresponding ret_addr_offset() and
12814 // compute_padding() functions will have to be adjusted.
12815 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12816 match(CallStaticJava);
12817 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12818 effect(USE meth);
12819 // EBP is saved by all callees (for interpreter stack correction).
12820 // We use it here for a similar purpose, in {preserve,restore}_SP.
12821
12822 ins_cost(300);
12823 format %{ "CALL,static/MethodHandle " %}
12824 opcode(0xE8); /* E8 cd */
12825 ins_encode( pre_call_FPU,
12826 preserve_SP,
12827 Java_Static_Call( meth ),
12828 restore_SP,
12829 call_epilog,
12830 post_call_FPU );
12831 ins_pipe( pipe_slow );
12832 ins_alignment(4);
12833 %}
12834
12835 // Call Java Dynamic Instruction
12836 // Note: If this code changes, the corresponding ret_addr_offset() and
12837 // compute_padding() functions will have to be adjusted.
12838 instruct CallDynamicJavaDirect(method meth) %{
12839 match(CallDynamicJava);
12840 effect(USE meth);
12841
12842 ins_cost(300);
12843 format %{ "MOV EAX,(oop)-1\n\t"
12844 "CALL,dynamic" %}
12845 opcode(0xE8); /* E8 cd */
12846 ins_encode( pre_call_FPU,
12847 Java_Dynamic_Call( meth ),
12848 call_epilog,
12849 post_call_FPU );
12850 ins_pipe( pipe_slow );
12851 ins_alignment(4);
12852 %}
12853
12854 // Call Runtime Instruction
12855 instruct CallRuntimeDirect(method meth) %{
12856 match(CallRuntime );
12857 effect(USE meth);
12858
12859 ins_cost(300);
12860 format %{ "CALL,runtime " %}
12861 opcode(0xE8); /* E8 cd */
12862 // Use FFREEs to clear entries in float stack
12863 ins_encode( pre_call_FPU,
12864 FFree_Float_Stack_All,
12865 Java_To_Runtime( meth ),
12866 post_call_FPU );
12867 ins_pipe( pipe_slow );
12868 %}
12869
12870 // Call runtime without safepoint
12871 instruct CallLeafDirect(method meth) %{
12872 match(CallLeaf);
12873 effect(USE meth);
12874
12875 ins_cost(300);
12876 format %{ "CALL_LEAF,runtime " %}
12877 opcode(0xE8); /* E8 cd */
12878 ins_encode( pre_call_FPU,
12879 FFree_Float_Stack_All,
12880 Java_To_Runtime( meth ),
12881 Verify_FPU_For_Leaf, post_call_FPU );
12882 ins_pipe( pipe_slow );
12883 %}
12884
12885 instruct CallLeafNoFPDirect(method meth) %{
12886 match(CallLeafNoFP);
12887 effect(USE meth);
12888
12889 ins_cost(300);
12890 format %{ "CALL_LEAF_NOFP,runtime " %}
12891 opcode(0xE8); /* E8 cd */
12892 ins_encode(Java_To_Runtime(meth));
12893 ins_pipe( pipe_slow );
12894 %}
12895
12896
12897 // Return Instruction
12898 // Remove the return address & jump to it.
12899 instruct Ret() %{
12900 match(Return);
12901 format %{ "RET" %}
12902 opcode(0xC3);
12903 ins_encode(OpcP);
12904 ins_pipe( pipe_jmp );
12905 %}
12906
12907 // Tail Call; Jump from runtime stub to Java code.
12908 // Also known as an 'interprocedural jump'.
12909 // Target of jump will eventually return to caller.
12910 // TailJump below removes the return address.
12911 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12912 match(TailCall jump_target method_oop );
12913 ins_cost(300);
12914 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12915 opcode(0xFF, 0x4); /* Opcode FF /4 */
12916 ins_encode( OpcP, RegOpc(jump_target) );
12917 ins_pipe( pipe_jmp );
12918 %}
12919
12920
12921 // Tail Jump; remove the return address; jump to target.
12922 // TailCall above leaves the return address around.
12923 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12924 match( TailJump jump_target ex_oop );
12925 ins_cost(300);
12926 format %{ "POP EDX\t# pop return address into dummy\n\t"
12927 "JMP $jump_target " %}
12928 opcode(0xFF, 0x4); /* Opcode FF /4 */
12929 ins_encode( enc_pop_rdx,
12930 OpcP, RegOpc(jump_target) );
12931 ins_pipe( pipe_jmp );
12932 %}
12933
12934 // Create exception oop: created by stack-crawling runtime code.
12935 // Created exception is now available to this handler, and is setup
12936 // just prior to jumping to this handler. No code emitted.
12937 instruct CreateException( eAXRegP ex_oop )
12938 %{
12939 match(Set ex_oop (CreateEx));
12940
12941 size(0);
12942 // use the following format syntax
12943 format %{ "# exception oop is in EAX; no code emitted" %}
12944 ins_encode();
12945 ins_pipe( empty );
12946 %}
12947
12948
12949 // Rethrow exception:
12950 // The exception oop will come in the first argument position.
12951 // Then JUMP (not call) to the rethrow stub code.
12952 instruct RethrowException()
12953 %{
12954 match(Rethrow);
12955
12956 // use the following format syntax
12957 format %{ "JMP rethrow_stub" %}
12958 ins_encode(enc_rethrow);
12959 ins_pipe( pipe_jmp );
12960 %}
12961
12962 // inlined locking and unlocking
12963
12964
12965 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12966 match( Set cr (FastLock object box) );
12967 effect( TEMP tmp, TEMP scr, USE_KILL box );
12968 ins_cost(300);
12969 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12970 ins_encode( Fast_Lock(object,box,tmp,scr) );
12971 ins_pipe( pipe_slow );
12972 %}
12973
12974 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12975 match( Set cr (FastUnlock object box) );
12976 effect( TEMP tmp, USE_KILL box );
12977 ins_cost(300);
12978 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12979 ins_encode( Fast_Unlock(object,box,tmp) );
12980 ins_pipe( pipe_slow );
12981 %}
12982
12983
12984
12985 // ============================================================================
12986 // Safepoint Instruction
12987 instruct safePoint_poll(eFlagsReg cr) %{
12988 match(SafePoint);
12989 effect(KILL cr);
12990
12991 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12992 // On SPARC that might be acceptable as we can generate the address with
12993 // just a sethi, saving an or. By polling at offset 0 we can end up
12994 // putting additional pressure on the index-0 in the D$. Because of
12995 // alignment (just like the situation at hand) the lower indices tend
12996 // to see more traffic. It'd be better to change the polling address
12997 // to offset 0 of the last $line in the polling page.
12998
12999 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13000 ins_cost(125);
13001 size(6) ;
13002 ins_encode( Safepoint_Poll() );
13003 ins_pipe( ialu_reg_mem );
13004 %}
13005
13006
13007 // ============================================================================
13008 // This name is KNOWN by the ADLC and cannot be changed.
13009 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13010 // for this guy.
13011 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13012 match(Set dst (ThreadLocal));
13013 effect(DEF dst, KILL cr);
13014
13015 format %{ "MOV $dst, Thread::current()" %}
13016 ins_encode %{
13017 Register dstReg = as_Register($dst$$reg);
13018 __ get_thread(dstReg);
13019 %}
13020 ins_pipe( ialu_reg_fat );
13021 %}
13022
13023
13024
13025 //----------PEEPHOLE RULES-----------------------------------------------------
13026 // These must follow all instruction definitions as they use the names
13027 // defined in the instructions definitions.
13028 //
13029 // peepmatch ( root_instr_name [preceding_instruction]* );
13030 //
13031 // peepconstraint %{
13032 // (instruction_number.operand_name relational_op instruction_number.operand_name
13033 // [, ...] );
13034 // // instruction numbers are zero-based using left to right order in peepmatch
13035 //
13036 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13037 // // provide an instruction_number.operand_name for each operand that appears
13038 // // in the replacement instruction's match rule
13039 //
13040 // ---------VM FLAGS---------------------------------------------------------
13041 //
13042 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13043 //
13044 // Each peephole rule is given an identifying number starting with zero and
13045 // increasing by one in the order seen by the parser. An individual peephole
13046 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13047 // on the command-line.
13048 //
13049 // ---------CURRENT LIMITATIONS----------------------------------------------
13050 //
13051 // Only match adjacent instructions in same basic block
13052 // Only equality constraints
13053 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13054 // Only one replacement instruction
13055 //
13056 // ---------EXAMPLE----------------------------------------------------------
13057 //
13058 // // pertinent parts of existing instructions in architecture description
13059 // instruct movI(rRegI dst, rRegI src) %{
13060 // match(Set dst (CopyI src));
13061 // %}
13062 //
13063 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13064 // match(Set dst (AddI dst src));
13065 // effect(KILL cr);
13066 // %}
13067 //
13068 // // Change (inc mov) to lea
13069 // peephole %{
13070 // // increment preceeded by register-register move
13071 // peepmatch ( incI_eReg movI );
13072 // // require that the destination register of the increment
13073 // // match the destination register of the move
13074 // peepconstraint ( 0.dst == 1.dst );
13075 // // construct a replacement instruction that sets
13076 // // the destination to ( move's source register + one )
13077 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13078 // %}
13079 //
13080 // Implementation no longer uses movX instructions since
13081 // machine-independent system no longer uses CopyX nodes.
13082 //
13083 // peephole %{
13084 // peepmatch ( incI_eReg movI );
13085 // peepconstraint ( 0.dst == 1.dst );
13086 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13087 // %}
13088 //
13089 // peephole %{
13090 // peepmatch ( decI_eReg movI );
13091 // peepconstraint ( 0.dst == 1.dst );
13092 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13093 // %}
13094 //
13095 // peephole %{
13096 // peepmatch ( addI_eReg_imm movI );
13097 // peepconstraint ( 0.dst == 1.dst );
13098 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13099 // %}
13100 //
13101 // peephole %{
13102 // peepmatch ( addP_eReg_imm movP );
13103 // peepconstraint ( 0.dst == 1.dst );
13104 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13105 // %}
13106
13107 // // Change load of spilled value to only a spill
13108 // instruct storeI(memory mem, rRegI src) %{
13109 // match(Set mem (StoreI mem src));
13110 // %}
13111 //
13112 // instruct loadI(rRegI dst, memory mem) %{
13113 // match(Set dst (LoadI mem));
13114 // %}
13115 //
13116 peephole %{
13117 peepmatch ( loadI storeI );
13118 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13119 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13120 %}
13121
13122 //----------SMARTSPILL RULES---------------------------------------------------
13123 // These must follow all instruction definitions as they use the names
13124 // defined in the instructions definitions.