1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/callnode.hpp"
29 #include "opto/connode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/opcodes.hpp"
34 #include "opto/regmask.hpp"
35 #include "opto/rootnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "opto/type.hpp"
38 #include "runtime/atomic.hpp"
39 #include "runtime/os.hpp"
40 #ifdef TARGET_ARCH_MODEL_x86_32
41 # include "adfiles/ad_x86_32.hpp"
42 #endif
43 #ifdef TARGET_ARCH_MODEL_x86_64
44 # include "adfiles/ad_x86_64.hpp"
45 #endif
46 #ifdef TARGET_ARCH_MODEL_sparc
47 # include "adfiles/ad_sparc.hpp"
48 #endif
49 #ifdef TARGET_ARCH_MODEL_zero
50 # include "adfiles/ad_zero.hpp"
51 #endif
52 #ifdef TARGET_ARCH_MODEL_arm
53 # include "adfiles/ad_arm.hpp"
54 #endif
55 #ifdef TARGET_ARCH_MODEL_ppc
56 # include "adfiles/ad_ppc.hpp"
57 #endif
58
59 OptoReg::Name OptoReg::c_frame_pointer;
60
61
62
63 const int Matcher::base2reg[Type::lastype] = {
64 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN,
65 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */
66 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */
67 0, 0/*abio*/,
68 Op_RegP /* Return address */, 0, /* the memories */
69 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD,
70 0 /*bottom*/
71 };
72
73 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
74 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
75 RegMask Matcher::STACK_ONLY_mask;
76 RegMask Matcher::c_frame_ptr_mask;
77 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
78 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
79
80 //---------------------------Matcher-------------------------------------------
81 Matcher::Matcher( Node_List &proj_list ) :
82 PhaseTransform( Phase::Ins_Select ),
83 #ifdef ASSERT
84 _old2new_map(C->comp_arena()),
85 _new2old_map(C->comp_arena()),
86 #endif
87 _shared_nodes(C->comp_arena()),
88 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
89 _swallowed(swallowed),
90 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
91 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
92 _must_clone(must_clone), _proj_list(proj_list),
93 _register_save_policy(register_save_policy),
94 _c_reg_save_policy(c_reg_save_policy),
95 _register_save_type(register_save_type),
96 _ruleName(ruleName),
97 _allocation_started(false),
98 _states_arena(Chunk::medium_size),
99 _visited(&_states_arena),
100 _shared(&_states_arena),
101 _dontcare(&_states_arena) {
102 C->set_matcher(this);
103
104 idealreg2spillmask [Op_RegI] = NULL;
105 idealreg2spillmask [Op_RegN] = NULL;
106 idealreg2spillmask [Op_RegL] = NULL;
107 idealreg2spillmask [Op_RegF] = NULL;
108 idealreg2spillmask [Op_RegD] = NULL;
109 idealreg2spillmask [Op_RegP] = NULL;
110
111 idealreg2debugmask [Op_RegI] = NULL;
112 idealreg2debugmask [Op_RegN] = NULL;
113 idealreg2debugmask [Op_RegL] = NULL;
114 idealreg2debugmask [Op_RegF] = NULL;
115 idealreg2debugmask [Op_RegD] = NULL;
116 idealreg2debugmask [Op_RegP] = NULL;
117
118 idealreg2mhdebugmask[Op_RegI] = NULL;
119 idealreg2mhdebugmask[Op_RegN] = NULL;
120 idealreg2mhdebugmask[Op_RegL] = NULL;
121 idealreg2mhdebugmask[Op_RegF] = NULL;
122 idealreg2mhdebugmask[Op_RegD] = NULL;
123 idealreg2mhdebugmask[Op_RegP] = NULL;
124
125 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
126 }
127
128 //------------------------------warp_incoming_stk_arg------------------------
129 // This warps a VMReg into an OptoReg::Name
130 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
131 OptoReg::Name warped;
132 if( reg->is_stack() ) { // Stack slot argument?
133 warped = OptoReg::add(_old_SP, reg->reg2stack() );
134 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
135 if( warped >= _in_arg_limit )
136 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
137 if (!RegMask::can_represent(warped)) {
138 // the compiler cannot represent this method's calling sequence
139 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
140 return OptoReg::Bad;
141 }
142 return warped;
143 }
144 return OptoReg::as_OptoReg(reg);
145 }
146
147 //---------------------------compute_old_SP------------------------------------
148 OptoReg::Name Compile::compute_old_SP() {
149 int fixed = fixed_slots();
150 int preserve = in_preserve_stack_slots();
151 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
152 }
153
154
155
156 #ifdef ASSERT
157 void Matcher::verify_new_nodes_only(Node* xroot) {
158 // Make sure that the new graph only references new nodes
159 ResourceMark rm;
160 Unique_Node_List worklist;
161 VectorSet visited(Thread::current()->resource_area());
162 worklist.push(xroot);
163 while (worklist.size() > 0) {
164 Node* n = worklist.pop();
165 visited <<= n->_idx;
166 assert(C->node_arena()->contains(n), "dead node");
167 for (uint j = 0; j < n->req(); j++) {
168 Node* in = n->in(j);
169 if (in != NULL) {
170 assert(C->node_arena()->contains(in), "dead node");
171 if (!visited.test(in->_idx)) {
172 worklist.push(in);
173 }
174 }
175 }
176 }
177 }
178 #endif
179
180
181 //---------------------------match---------------------------------------------
182 void Matcher::match( ) {
183 if( MaxLabelRootDepth < 100 ) { // Too small?
184 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
185 MaxLabelRootDepth = 100;
186 }
187 // One-time initialization of some register masks.
188 init_spill_mask( C->root()->in(1) );
189 _return_addr_mask = return_addr();
190 #ifdef _LP64
191 // Pointers take 2 slots in 64-bit land
192 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
193 #endif
194
195 // Map a Java-signature return type into return register-value
196 // machine registers for 0, 1 and 2 returned values.
197 const TypeTuple *range = C->tf()->range();
198 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
199 // Get ideal-register return type
200 int ireg = base2reg[range->field_at(TypeFunc::Parms)->base()];
201 // Get machine return register
202 uint sop = C->start()->Opcode();
203 OptoRegPair regs = return_value(ireg, false);
204
205 // And mask for same
206 _return_value_mask = RegMask(regs.first());
207 if( OptoReg::is_valid(regs.second()) )
208 _return_value_mask.Insert(regs.second());
209 }
210
211 // ---------------
212 // Frame Layout
213
214 // Need the method signature to determine the incoming argument types,
215 // because the types determine which registers the incoming arguments are
216 // in, and this affects the matched code.
217 const TypeTuple *domain = C->tf()->domain();
218 uint argcnt = domain->cnt() - TypeFunc::Parms;
219 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
220 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
221 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
222 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
223 uint i;
224 for( i = 0; i<argcnt; i++ ) {
225 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
226 }
227
228 // Pass array of ideal registers and length to USER code (from the AD file)
229 // that will convert this to an array of register numbers.
230 const StartNode *start = C->start();
231 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
232 #ifdef ASSERT
233 // Sanity check users' calling convention. Real handy while trying to
234 // get the initial port correct.
235 { for (uint i = 0; i<argcnt; i++) {
236 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
237 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
238 _parm_regs[i].set_bad();
239 continue;
240 }
241 VMReg parm_reg = vm_parm_regs[i].first();
242 assert(parm_reg->is_valid(), "invalid arg?");
243 if (parm_reg->is_reg()) {
244 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
245 assert(can_be_java_arg(opto_parm_reg) ||
246 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
247 opto_parm_reg == inline_cache_reg(),
248 "parameters in register must be preserved by runtime stubs");
249 }
250 for (uint j = 0; j < i; j++) {
251 assert(parm_reg != vm_parm_regs[j].first(),
252 "calling conv. must produce distinct regs");
253 }
254 }
255 }
256 #endif
257
258 // Do some initial frame layout.
259
260 // Compute the old incoming SP (may be called FP) as
261 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
262 _old_SP = C->compute_old_SP();
263 assert( is_even(_old_SP), "must be even" );
264
265 // Compute highest incoming stack argument as
266 // _old_SP + out_preserve_stack_slots + incoming argument size.
267 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
268 assert( is_even(_in_arg_limit), "out_preserve must be even" );
269 for( i = 0; i < argcnt; i++ ) {
270 // Permit args to have no register
271 _calling_convention_mask[i].Clear();
272 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
273 continue;
274 }
275 // calling_convention returns stack arguments as a count of
276 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
277 // the allocators point of view, taking into account all the
278 // preserve area, locks & pad2.
279
280 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
281 if( OptoReg::is_valid(reg1))
282 _calling_convention_mask[i].Insert(reg1);
283
284 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
285 if( OptoReg::is_valid(reg2))
286 _calling_convention_mask[i].Insert(reg2);
287
288 // Saved biased stack-slot register number
289 _parm_regs[i].set_pair(reg2, reg1);
290 }
291
292 // Finally, make sure the incoming arguments take up an even number of
293 // words, in case the arguments or locals need to contain doubleword stack
294 // slots. The rest of the system assumes that stack slot pairs (in
295 // particular, in the spill area) which look aligned will in fact be
296 // aligned relative to the stack pointer in the target machine. Double
297 // stack slots will always be allocated aligned.
298 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
299
300 // Compute highest outgoing stack argument as
301 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
302 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
303 assert( is_even(_out_arg_limit), "out_preserve must be even" );
304
305 if (!RegMask::can_represent(OptoReg::add(_out_arg_limit,-1))) {
306 // the compiler cannot represent this method's calling sequence
307 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
308 }
309
310 if (C->failing()) return; // bailed out on incoming arg failure
311
312 // ---------------
313 // Collect roots of matcher trees. Every node for which
314 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
315 // can be a valid interior of some tree.
316 find_shared( C->root() );
317 find_shared( C->top() );
318
319 C->print_method("Before Matching");
320
321 // Create new ideal node ConP #NULL even if it does exist in old space
322 // to avoid false sharing if the corresponding mach node is not used.
323 // The corresponding mach node is only used in rare cases for derived
324 // pointers.
325 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
326
327 // Swap out to old-space; emptying new-space
328 Arena *old = C->node_arena()->move_contents(C->old_arena());
329
330 // Save debug and profile information for nodes in old space:
331 _old_node_note_array = C->node_note_array();
332 if (_old_node_note_array != NULL) {
333 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
334 (C->comp_arena(), _old_node_note_array->length(),
335 0, NULL));
336 }
337
338 // Pre-size the new_node table to avoid the need for range checks.
339 grow_new_node_array(C->unique());
340
341 // Reset node counter so MachNodes start with _idx at 0
342 int nodes = C->unique(); // save value
343 C->set_unique(0);
344
345 // Recursively match trees from old space into new space.
346 // Correct leaves of new-space Nodes; they point to old-space.
347 _visited.Clear(); // Clear visit bits for xform call
348 C->set_cached_top_node(xform( C->top(), nodes ));
349 if (!C->failing()) {
350 Node* xroot = xform( C->root(), 1 );
351 if (xroot == NULL) {
352 Matcher::soft_match_failure(); // recursive matching process failed
353 C->record_method_not_compilable("instruction match failed");
354 } else {
355 // During matching shared constants were attached to C->root()
356 // because xroot wasn't available yet, so transfer the uses to
357 // the xroot.
358 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
359 Node* n = C->root()->fast_out(j);
360 if (C->node_arena()->contains(n)) {
361 assert(n->in(0) == C->root(), "should be control user");
362 n->set_req(0, xroot);
363 --j;
364 --jmax;
365 }
366 }
367
368 // Generate new mach node for ConP #NULL
369 assert(new_ideal_null != NULL, "sanity");
370 _mach_null = match_tree(new_ideal_null);
371 // Don't set control, it will confuse GCM since there are no uses.
372 // The control will be set when this node is used first time
373 // in find_base_for_derived().
374 assert(_mach_null != NULL, "");
375
376 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
377
378 #ifdef ASSERT
379 verify_new_nodes_only(xroot);
380 #endif
381 }
382 }
383 if (C->top() == NULL || C->root() == NULL) {
384 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
385 }
386 if (C->failing()) {
387 // delete old;
388 old->destruct_contents();
389 return;
390 }
391 assert( C->top(), "" );
392 assert( C->root(), "" );
393 validate_null_checks();
394
395 // Now smoke old-space
396 NOT_DEBUG( old->destruct_contents() );
397
398 // ------------------------
399 // Set up save-on-entry registers
400 Fixup_Save_On_Entry( );
401 }
402
403
404 //------------------------------Fixup_Save_On_Entry----------------------------
405 // The stated purpose of this routine is to take care of save-on-entry
406 // registers. However, the overall goal of the Match phase is to convert into
407 // machine-specific instructions which have RegMasks to guide allocation.
408 // So what this procedure really does is put a valid RegMask on each input
409 // to the machine-specific variations of all Return, TailCall and Halt
410 // instructions. It also adds edgs to define the save-on-entry values (and of
411 // course gives them a mask).
412
413 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
414 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
415 // Do all the pre-defined register masks
416 rms[TypeFunc::Control ] = RegMask::Empty;
417 rms[TypeFunc::I_O ] = RegMask::Empty;
418 rms[TypeFunc::Memory ] = RegMask::Empty;
419 rms[TypeFunc::ReturnAdr] = ret_adr;
420 rms[TypeFunc::FramePtr ] = fp;
421 return rms;
422 }
423
424 //---------------------------init_first_stack_mask-----------------------------
425 // Create the initial stack mask used by values spilling to the stack.
426 // Disallow any debug info in outgoing argument areas by setting the
427 // initial mask accordingly.
428 void Matcher::init_first_stack_mask() {
429
430 // Allocate storage for spill masks as masks for the appropriate load type.
431 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * 3*6);
432
433 idealreg2spillmask [Op_RegN] = &rms[0];
434 idealreg2spillmask [Op_RegI] = &rms[1];
435 idealreg2spillmask [Op_RegL] = &rms[2];
436 idealreg2spillmask [Op_RegF] = &rms[3];
437 idealreg2spillmask [Op_RegD] = &rms[4];
438 idealreg2spillmask [Op_RegP] = &rms[5];
439
440 idealreg2debugmask [Op_RegN] = &rms[6];
441 idealreg2debugmask [Op_RegI] = &rms[7];
442 idealreg2debugmask [Op_RegL] = &rms[8];
443 idealreg2debugmask [Op_RegF] = &rms[9];
444 idealreg2debugmask [Op_RegD] = &rms[10];
445 idealreg2debugmask [Op_RegP] = &rms[11];
446
447 idealreg2mhdebugmask[Op_RegN] = &rms[12];
448 idealreg2mhdebugmask[Op_RegI] = &rms[13];
449 idealreg2mhdebugmask[Op_RegL] = &rms[14];
450 idealreg2mhdebugmask[Op_RegF] = &rms[15];
451 idealreg2mhdebugmask[Op_RegD] = &rms[16];
452 idealreg2mhdebugmask[Op_RegP] = &rms[17];
453
454 OptoReg::Name i;
455
456 // At first, start with the empty mask
457 C->FIRST_STACK_mask().Clear();
458
459 // Add in the incoming argument area
460 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
461 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1))
462 C->FIRST_STACK_mask().Insert(i);
463
464 // Add in all bits past the outgoing argument area
465 guarantee(RegMask::can_represent(OptoReg::add(_out_arg_limit,-1)),
466 "must be able to represent all call arguments in reg mask");
467 init = _out_arg_limit;
468 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
469 C->FIRST_STACK_mask().Insert(i);
470
471 // Finally, set the "infinite stack" bit.
472 C->FIRST_STACK_mask().set_AllStack();
473
474 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
475 #ifdef _LP64
476 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
477 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
478 #endif
479 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
480 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
481 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
482 idealreg2spillmask[Op_RegL]->OR(C->FIRST_STACK_mask());
483 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
484 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
485 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
486 idealreg2spillmask[Op_RegD]->OR(C->FIRST_STACK_mask());
487 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
488 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
489
490 if (UseFPUForSpilling) {
491 // This mask logic assumes that the spill operations are
492 // symmetric and that the registers involved are the same size.
493 // On sparc for instance we may have to use 64 bit moves will
494 // kill 2 registers when used with F0-F31.
495 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
496 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
497 #ifdef _LP64
498 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
499 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
500 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
501 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
502 #else
503 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
504 #endif
505 }
506
507 // Make up debug masks. Any spill slot plus callee-save registers.
508 // Caller-save registers are assumed to be trashable by the various
509 // inline-cache fixup routines.
510 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
511 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
512 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
513 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
514 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
515 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
516
517 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
518 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
519 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
520 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
521 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
522 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
523
524 // Prevent stub compilations from attempting to reference
525 // callee-saved registers from debug info
526 bool exclude_soe = !Compile::current()->is_method_compilation();
527
528 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
529 // registers the caller has to save do not work
530 if( _register_save_policy[i] == 'C' ||
531 _register_save_policy[i] == 'A' ||
532 (_register_save_policy[i] == 'E' && exclude_soe) ) {
533 idealreg2debugmask [Op_RegN]->Remove(i);
534 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
535 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
536 idealreg2debugmask [Op_RegF]->Remove(i); // masks
537 idealreg2debugmask [Op_RegD]->Remove(i);
538 idealreg2debugmask [Op_RegP]->Remove(i);
539
540 idealreg2mhdebugmask[Op_RegN]->Remove(i);
541 idealreg2mhdebugmask[Op_RegI]->Remove(i);
542 idealreg2mhdebugmask[Op_RegL]->Remove(i);
543 idealreg2mhdebugmask[Op_RegF]->Remove(i);
544 idealreg2mhdebugmask[Op_RegD]->Remove(i);
545 idealreg2mhdebugmask[Op_RegP]->Remove(i);
546 }
547 }
548
549 // Subtract the register we use to save the SP for MethodHandle
550 // invokes to from the debug mask.
551 const RegMask save_mask = method_handle_invoke_SP_save_mask();
552 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
553 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
554 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
555 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
556 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
557 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
558 }
559
560 //---------------------------is_save_on_entry----------------------------------
561 bool Matcher::is_save_on_entry( int reg ) {
562 return
563 _register_save_policy[reg] == 'E' ||
564 _register_save_policy[reg] == 'A' || // Save-on-entry register?
565 // Also save argument registers in the trampolining stubs
566 (C->save_argument_registers() && is_spillable_arg(reg));
567 }
568
569 //---------------------------Fixup_Save_On_Entry-------------------------------
570 void Matcher::Fixup_Save_On_Entry( ) {
571 init_first_stack_mask();
572
573 Node *root = C->root(); // Short name for root
574 // Count number of save-on-entry registers.
575 uint soe_cnt = number_of_saved_registers();
576 uint i;
577
578 // Find the procedure Start Node
579 StartNode *start = C->start();
580 assert( start, "Expect a start node" );
581
582 // Save argument registers in the trampolining stubs
583 if( C->save_argument_registers() )
584 for( i = 0; i < _last_Mach_Reg; i++ )
585 if( is_spillable_arg(i) )
586 soe_cnt++;
587
588 // Input RegMask array shared by all Returns.
589 // The type for doubles and longs has a count of 2, but
590 // there is only 1 returned value
591 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
592 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
593 // Returns have 0 or 1 returned values depending on call signature.
594 // Return register is specified by return_value in the AD file.
595 if (ret_edge_cnt > TypeFunc::Parms)
596 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
597
598 // Input RegMask array shared by all Rethrows.
599 uint reth_edge_cnt = TypeFunc::Parms+1;
600 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
601 // Rethrow takes exception oop only, but in the argument 0 slot.
602 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
603 #ifdef _LP64
604 // Need two slots for ptrs in 64-bit land
605 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
606 #endif
607
608 // Input RegMask array shared by all TailCalls
609 uint tail_call_edge_cnt = TypeFunc::Parms+2;
610 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
611
612 // Input RegMask array shared by all TailJumps
613 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
614 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
615
616 // TailCalls have 2 returned values (target & moop), whose masks come
617 // from the usual MachNode/MachOper mechanism. Find a sample
618 // TailCall to extract these masks and put the correct masks into
619 // the tail_call_rms array.
620 for( i=1; i < root->req(); i++ ) {
621 MachReturnNode *m = root->in(i)->as_MachReturn();
622 if( m->ideal_Opcode() == Op_TailCall ) {
623 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
624 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
625 break;
626 }
627 }
628
629 // TailJumps have 2 returned values (target & ex_oop), whose masks come
630 // from the usual MachNode/MachOper mechanism. Find a sample
631 // TailJump to extract these masks and put the correct masks into
632 // the tail_jump_rms array.
633 for( i=1; i < root->req(); i++ ) {
634 MachReturnNode *m = root->in(i)->as_MachReturn();
635 if( m->ideal_Opcode() == Op_TailJump ) {
636 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
637 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
638 break;
639 }
640 }
641
642 // Input RegMask array shared by all Halts
643 uint halt_edge_cnt = TypeFunc::Parms;
644 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
645
646 // Capture the return input masks into each exit flavor
647 for( i=1; i < root->req(); i++ ) {
648 MachReturnNode *exit = root->in(i)->as_MachReturn();
649 switch( exit->ideal_Opcode() ) {
650 case Op_Return : exit->_in_rms = ret_rms; break;
651 case Op_Rethrow : exit->_in_rms = reth_rms; break;
652 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
653 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
654 case Op_Halt : exit->_in_rms = halt_rms; break;
655 default : ShouldNotReachHere();
656 }
657 }
658
659 // Next unused projection number from Start.
660 int proj_cnt = C->tf()->domain()->cnt();
661
662 // Do all the save-on-entry registers. Make projections from Start for
663 // them, and give them a use at the exit points. To the allocator, they
664 // look like incoming register arguments.
665 for( i = 0; i < _last_Mach_Reg; i++ ) {
666 if( is_save_on_entry(i) ) {
667
668 // Add the save-on-entry to the mask array
669 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
670 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
671 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
672 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
673 // Halts need the SOE registers, but only in the stack as debug info.
674 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
675 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
676
677 Node *mproj;
678
679 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
680 // into a single RegD.
681 if( (i&1) == 0 &&
682 _register_save_type[i ] == Op_RegF &&
683 _register_save_type[i+1] == Op_RegF &&
684 is_save_on_entry(i+1) ) {
685 // Add other bit for double
686 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
687 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
688 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
689 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
690 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
691 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
692 proj_cnt += 2; // Skip 2 for doubles
693 }
694 else if( (i&1) == 1 && // Else check for high half of double
695 _register_save_type[i-1] == Op_RegF &&
696 _register_save_type[i ] == Op_RegF &&
697 is_save_on_entry(i-1) ) {
698 ret_rms [ ret_edge_cnt] = RegMask::Empty;
699 reth_rms [ reth_edge_cnt] = RegMask::Empty;
700 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
701 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
702 halt_rms [ halt_edge_cnt] = RegMask::Empty;
703 mproj = C->top();
704 }
705 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
706 // into a single RegL.
707 else if( (i&1) == 0 &&
708 _register_save_type[i ] == Op_RegI &&
709 _register_save_type[i+1] == Op_RegI &&
710 is_save_on_entry(i+1) ) {
711 // Add other bit for long
712 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
713 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
714 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
715 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
716 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
717 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
718 proj_cnt += 2; // Skip 2 for longs
719 }
720 else if( (i&1) == 1 && // Else check for high half of long
721 _register_save_type[i-1] == Op_RegI &&
722 _register_save_type[i ] == Op_RegI &&
723 is_save_on_entry(i-1) ) {
724 ret_rms [ ret_edge_cnt] = RegMask::Empty;
725 reth_rms [ reth_edge_cnt] = RegMask::Empty;
726 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
727 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
728 halt_rms [ halt_edge_cnt] = RegMask::Empty;
729 mproj = C->top();
730 } else {
731 // Make a projection for it off the Start
732 mproj = new (C, 1) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
733 }
734
735 ret_edge_cnt ++;
736 reth_edge_cnt ++;
737 tail_call_edge_cnt ++;
738 tail_jump_edge_cnt ++;
739 halt_edge_cnt ++;
740
741 // Add a use of the SOE register to all exit paths
742 for( uint j=1; j < root->req(); j++ )
743 root->in(j)->add_req(mproj);
744 } // End of if a save-on-entry register
745 } // End of for all machine registers
746 }
747
748 //------------------------------init_spill_mask--------------------------------
749 void Matcher::init_spill_mask( Node *ret ) {
750 if( idealreg2regmask[Op_RegI] ) return; // One time only init
751
752 OptoReg::c_frame_pointer = c_frame_pointer();
753 c_frame_ptr_mask = c_frame_pointer();
754 #ifdef _LP64
755 // pointers are twice as big
756 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
757 #endif
758
759 // Start at OptoReg::stack0()
760 STACK_ONLY_mask.Clear();
761 OptoReg::Name init = OptoReg::stack2reg(0);
762 // STACK_ONLY_mask is all stack bits
763 OptoReg::Name i;
764 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
765 STACK_ONLY_mask.Insert(i);
766 // Also set the "infinite stack" bit.
767 STACK_ONLY_mask.set_AllStack();
768
769 // Copy the register names over into the shared world
770 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
771 // SharedInfo::regName[i] = regName[i];
772 // Handy RegMasks per machine register
773 mreg2regmask[i].Insert(i);
774 }
775
776 // Grab the Frame Pointer
777 Node *fp = ret->in(TypeFunc::FramePtr);
778 Node *mem = ret->in(TypeFunc::Memory);
779 const TypePtr* atp = TypePtr::BOTTOM;
780 // Share frame pointer while making spill ops
781 set_shared(fp);
782
783 // Compute generic short-offset Loads
784 #ifdef _LP64
785 MachNode *spillCP = match_tree(new (C, 3) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
786 #endif
787 MachNode *spillI = match_tree(new (C, 3) LoadINode(NULL,mem,fp,atp));
788 MachNode *spillL = match_tree(new (C, 3) LoadLNode(NULL,mem,fp,atp));
789 MachNode *spillF = match_tree(new (C, 3) LoadFNode(NULL,mem,fp,atp));
790 MachNode *spillD = match_tree(new (C, 3) LoadDNode(NULL,mem,fp,atp));
791 MachNode *spillP = match_tree(new (C, 3) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
792 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
793 spillD != NULL && spillP != NULL, "");
794
795 // Get the ADLC notion of the right regmask, for each basic type.
796 #ifdef _LP64
797 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
798 #endif
799 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
800 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
801 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
802 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
803 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
804 }
805
806 #ifdef ASSERT
807 static void match_alias_type(Compile* C, Node* n, Node* m) {
808 if (!VerifyAliases) return; // do not go looking for trouble by default
809 const TypePtr* nat = n->adr_type();
810 const TypePtr* mat = m->adr_type();
811 int nidx = C->get_alias_index(nat);
812 int midx = C->get_alias_index(mat);
813 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
814 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
815 for (uint i = 1; i < n->req(); i++) {
816 Node* n1 = n->in(i);
817 const TypePtr* n1at = n1->adr_type();
818 if (n1at != NULL) {
819 nat = n1at;
820 nidx = C->get_alias_index(n1at);
821 }
822 }
823 }
824 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
825 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
826 switch (n->Opcode()) {
827 case Op_PrefetchRead:
828 case Op_PrefetchWrite:
829 case Op_PrefetchAllocation:
830 nidx = Compile::AliasIdxRaw;
831 nat = TypeRawPtr::BOTTOM;
832 break;
833 }
834 }
835 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
836 switch (n->Opcode()) {
837 case Op_ClearArray:
838 midx = Compile::AliasIdxRaw;
839 mat = TypeRawPtr::BOTTOM;
840 break;
841 }
842 }
843 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
844 switch (n->Opcode()) {
845 case Op_Return:
846 case Op_Rethrow:
847 case Op_Halt:
848 case Op_TailCall:
849 case Op_TailJump:
850 nidx = Compile::AliasIdxBot;
851 nat = TypePtr::BOTTOM;
852 break;
853 }
854 }
855 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
856 switch (n->Opcode()) {
857 case Op_StrComp:
858 case Op_StrEquals:
859 case Op_StrIndexOf:
860 case Op_AryEq:
861 case Op_MemBarVolatile:
862 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
863 nidx = Compile::AliasIdxTop;
864 nat = NULL;
865 break;
866 }
867 }
868 if (nidx != midx) {
869 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
870 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
871 n->dump();
872 m->dump();
873 }
874 assert(C->subsume_loads() && C->must_alias(nat, midx),
875 "must not lose alias info when matching");
876 }
877 }
878 #endif
879
880
881 //------------------------------MStack-----------------------------------------
882 // State and MStack class used in xform() and find_shared() iterative methods.
883 enum Node_State { Pre_Visit, // node has to be pre-visited
884 Visit, // visit node
885 Post_Visit, // post-visit node
886 Alt_Post_Visit // alternative post-visit path
887 };
888
889 class MStack: public Node_Stack {
890 public:
891 MStack(int size) : Node_Stack(size) { }
892
893 void push(Node *n, Node_State ns) {
894 Node_Stack::push(n, (uint)ns);
895 }
896 void push(Node *n, Node_State ns, Node *parent, int indx) {
897 ++_inode_top;
898 if ((_inode_top + 1) >= _inode_max) grow();
899 _inode_top->node = parent;
900 _inode_top->indx = (uint)indx;
901 ++_inode_top;
902 _inode_top->node = n;
903 _inode_top->indx = (uint)ns;
904 }
905 Node *parent() {
906 pop();
907 return node();
908 }
909 Node_State state() const {
910 return (Node_State)index();
911 }
912 void set_state(Node_State ns) {
913 set_index((uint)ns);
914 }
915 };
916
917
918 //------------------------------xform------------------------------------------
919 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
920 // Node in new-space. Given a new-space Node, recursively walk his children.
921 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
922 Node *Matcher::xform( Node *n, int max_stack ) {
923 // Use one stack to keep both: child's node/state and parent's node/index
924 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
925 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
926
927 while (mstack.is_nonempty()) {
928 n = mstack.node(); // Leave node on stack
929 Node_State nstate = mstack.state();
930 if (nstate == Visit) {
931 mstack.set_state(Post_Visit);
932 Node *oldn = n;
933 // Old-space or new-space check
934 if (!C->node_arena()->contains(n)) {
935 // Old space!
936 Node* m;
937 if (has_new_node(n)) { // Not yet Label/Reduced
938 m = new_node(n);
939 } else {
940 if (!is_dontcare(n)) { // Matcher can match this guy
941 // Calls match special. They match alone with no children.
942 // Their children, the incoming arguments, match normally.
943 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
944 if (C->failing()) return NULL;
945 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
946 } else { // Nothing the matcher cares about
947 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
948 // Convert to machine-dependent projection
949 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
950 #ifdef ASSERT
951 _new2old_map.map(m->_idx, n);
952 #endif
953 if (m->in(0) != NULL) // m might be top
954 collect_null_checks(m, n);
955 } else { // Else just a regular 'ol guy
956 m = n->clone(); // So just clone into new-space
957 #ifdef ASSERT
958 _new2old_map.map(m->_idx, n);
959 #endif
960 // Def-Use edges will be added incrementally as Uses
961 // of this node are matched.
962 assert(m->outcnt() == 0, "no Uses of this clone yet");
963 }
964 }
965
966 set_new_node(n, m); // Map old to new
967 if (_old_node_note_array != NULL) {
968 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
969 n->_idx);
970 C->set_node_notes_at(m->_idx, nn);
971 }
972 debug_only(match_alias_type(C, n, m));
973 }
974 n = m; // n is now a new-space node
975 mstack.set_node(n);
976 }
977
978 // New space!
979 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
980
981 int i;
982 // Put precedence edges on stack first (match them last).
983 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
984 Node *m = oldn->in(i);
985 if (m == NULL) break;
986 // set -1 to call add_prec() instead of set_req() during Step1
987 mstack.push(m, Visit, n, -1);
988 }
989
990 // For constant debug info, I'd rather have unmatched constants.
991 int cnt = n->req();
992 JVMState* jvms = n->jvms();
993 int debug_cnt = jvms ? jvms->debug_start() : cnt;
994
995 // Now do only debug info. Clone constants rather than matching.
996 // Constants are represented directly in the debug info without
997 // the need for executable machine instructions.
998 // Monitor boxes are also represented directly.
999 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1000 Node *m = n->in(i); // Get input
1001 int op = m->Opcode();
1002 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1003 if( op == Op_ConI || op == Op_ConP || op == Op_ConN ||
1004 op == Op_ConF || op == Op_ConD || op == Op_ConL
1005 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1006 ) {
1007 m = m->clone();
1008 #ifdef ASSERT
1009 _new2old_map.map(m->_idx, n);
1010 #endif
1011 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1012 mstack.push(m->in(0), Visit, m, 0);
1013 } else {
1014 mstack.push(m, Visit, n, i);
1015 }
1016 }
1017
1018 // And now walk his children, and convert his inputs to new-space.
1019 for( ; i >= 0; --i ) { // For all normal inputs do
1020 Node *m = n->in(i); // Get input
1021 if(m != NULL)
1022 mstack.push(m, Visit, n, i);
1023 }
1024
1025 }
1026 else if (nstate == Post_Visit) {
1027 // Set xformed input
1028 Node *p = mstack.parent();
1029 if (p != NULL) { // root doesn't have parent
1030 int i = (int)mstack.index();
1031 if (i >= 0)
1032 p->set_req(i, n); // required input
1033 else if (i == -1)
1034 p->add_prec(n); // precedence input
1035 else
1036 ShouldNotReachHere();
1037 }
1038 mstack.pop(); // remove processed node from stack
1039 }
1040 else {
1041 ShouldNotReachHere();
1042 }
1043 } // while (mstack.is_nonempty())
1044 return n; // Return new-space Node
1045 }
1046
1047 //------------------------------warp_outgoing_stk_arg------------------------
1048 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1049 // Convert outgoing argument location to a pre-biased stack offset
1050 if (reg->is_stack()) {
1051 OptoReg::Name warped = reg->reg2stack();
1052 // Adjust the stack slot offset to be the register number used
1053 // by the allocator.
1054 warped = OptoReg::add(begin_out_arg_area, warped);
1055 // Keep track of the largest numbered stack slot used for an arg.
1056 // Largest used slot per call-site indicates the amount of stack
1057 // that is killed by the call.
1058 if( warped >= out_arg_limit_per_call )
1059 out_arg_limit_per_call = OptoReg::add(warped,1);
1060 if (!RegMask::can_represent(warped)) {
1061 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1062 return OptoReg::Bad;
1063 }
1064 return warped;
1065 }
1066 return OptoReg::as_OptoReg(reg);
1067 }
1068
1069
1070 //------------------------------match_sfpt-------------------------------------
1071 // Helper function to match call instructions. Calls match special.
1072 // They match alone with no children. Their children, the incoming
1073 // arguments, match normally.
1074 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1075 MachSafePointNode *msfpt = NULL;
1076 MachCallNode *mcall = NULL;
1077 uint cnt;
1078 // Split out case for SafePoint vs Call
1079 CallNode *call;
1080 const TypeTuple *domain;
1081 ciMethod* method = NULL;
1082 bool is_method_handle_invoke = false; // for special kill effects
1083 if( sfpt->is_Call() ) {
1084 call = sfpt->as_Call();
1085 domain = call->tf()->domain();
1086 cnt = domain->cnt();
1087
1088 // Match just the call, nothing else
1089 MachNode *m = match_tree(call);
1090 if (C->failing()) return NULL;
1091 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1092
1093 // Copy data from the Ideal SafePoint to the machine version
1094 mcall = m->as_MachCall();
1095
1096 mcall->set_tf( call->tf());
1097 mcall->set_entry_point(call->entry_point());
1098 mcall->set_cnt( call->cnt());
1099
1100 if( mcall->is_MachCallJava() ) {
1101 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1102 const CallJavaNode *call_java = call->as_CallJava();
1103 method = call_java->method();
1104 mcall_java->_method = method;
1105 mcall_java->_bci = call_java->_bci;
1106 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1107 is_method_handle_invoke = call_java->is_method_handle_invoke();
1108 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1109 if (is_method_handle_invoke) {
1110 C->set_has_method_handle_invokes(true);
1111 }
1112 if( mcall_java->is_MachCallStaticJava() )
1113 mcall_java->as_MachCallStaticJava()->_name =
1114 call_java->as_CallStaticJava()->_name;
1115 if( mcall_java->is_MachCallDynamicJava() )
1116 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1117 call_java->as_CallDynamicJava()->_vtable_index;
1118 }
1119 else if( mcall->is_MachCallRuntime() ) {
1120 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1121 }
1122 msfpt = mcall;
1123 }
1124 // This is a non-call safepoint
1125 else {
1126 call = NULL;
1127 domain = NULL;
1128 MachNode *mn = match_tree(sfpt);
1129 if (C->failing()) return NULL;
1130 msfpt = mn->as_MachSafePoint();
1131 cnt = TypeFunc::Parms;
1132 }
1133
1134 // Advertise the correct memory effects (for anti-dependence computation).
1135 msfpt->set_adr_type(sfpt->adr_type());
1136
1137 // Allocate a private array of RegMasks. These RegMasks are not shared.
1138 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1139 // Empty them all.
1140 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1141
1142 // Do all the pre-defined non-Empty register masks
1143 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1144 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1145
1146 // Place first outgoing argument can possibly be put.
1147 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1148 assert( is_even(begin_out_arg_area), "" );
1149 // Compute max outgoing register number per call site.
1150 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1151 // Calls to C may hammer extra stack slots above and beyond any arguments.
1152 // These are usually backing store for register arguments for varargs.
1153 if( call != NULL && call->is_CallRuntime() )
1154 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1155
1156
1157 // Do the normal argument list (parameters) register masks
1158 int argcnt = cnt - TypeFunc::Parms;
1159 if( argcnt > 0 ) { // Skip it all if we have no args
1160 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1161 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1162 int i;
1163 for( i = 0; i < argcnt; i++ ) {
1164 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1165 }
1166 // V-call to pick proper calling convention
1167 call->calling_convention( sig_bt, parm_regs, argcnt );
1168
1169 #ifdef ASSERT
1170 // Sanity check users' calling convention. Really handy during
1171 // the initial porting effort. Fairly expensive otherwise.
1172 { for (int i = 0; i<argcnt; i++) {
1173 if( !parm_regs[i].first()->is_valid() &&
1174 !parm_regs[i].second()->is_valid() ) continue;
1175 VMReg reg1 = parm_regs[i].first();
1176 VMReg reg2 = parm_regs[i].second();
1177 for (int j = 0; j < i; j++) {
1178 if( !parm_regs[j].first()->is_valid() &&
1179 !parm_regs[j].second()->is_valid() ) continue;
1180 VMReg reg3 = parm_regs[j].first();
1181 VMReg reg4 = parm_regs[j].second();
1182 if( !reg1->is_valid() ) {
1183 assert( !reg2->is_valid(), "valid halvsies" );
1184 } else if( !reg3->is_valid() ) {
1185 assert( !reg4->is_valid(), "valid halvsies" );
1186 } else {
1187 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1188 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1189 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1190 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1191 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1192 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1193 }
1194 }
1195 }
1196 }
1197 #endif
1198
1199 // Visit each argument. Compute its outgoing register mask.
1200 // Return results now can have 2 bits returned.
1201 // Compute max over all outgoing arguments both per call-site
1202 // and over the entire method.
1203 for( i = 0; i < argcnt; i++ ) {
1204 // Address of incoming argument mask to fill in
1205 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1206 if( !parm_regs[i].first()->is_valid() &&
1207 !parm_regs[i].second()->is_valid() ) {
1208 continue; // Avoid Halves
1209 }
1210 // Grab first register, adjust stack slots and insert in mask.
1211 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1212 if (OptoReg::is_valid(reg1))
1213 rm->Insert( reg1 );
1214 // Grab second register (if any), adjust stack slots and insert in mask.
1215 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1216 if (OptoReg::is_valid(reg2))
1217 rm->Insert( reg2 );
1218 } // End of for all arguments
1219
1220 // Compute number of stack slots needed to restore stack in case of
1221 // Pascal-style argument popping.
1222 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1223 }
1224
1225 if (is_method_handle_invoke) {
1226 // Kill some extra stack space in case method handles want to do
1227 // a little in-place argument insertion.
1228 int regs_per_word = NOT_LP64(1) LP64_ONLY(2); // %%% make a global const!
1229 out_arg_limit_per_call += MethodHandlePushLimit * regs_per_word;
1230 // Do not update mcall->_argsize because (a) the extra space is not
1231 // pushed as arguments and (b) _argsize is dead (not used anywhere).
1232 }
1233
1234 // Compute the max stack slot killed by any call. These will not be
1235 // available for debug info, and will be used to adjust FIRST_STACK_mask
1236 // after all call sites have been visited.
1237 if( _out_arg_limit < out_arg_limit_per_call)
1238 _out_arg_limit = out_arg_limit_per_call;
1239
1240 if (mcall) {
1241 // Kill the outgoing argument area, including any non-argument holes and
1242 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1243 // Since the max-per-method covers the max-per-call-site and debug info
1244 // is excluded on the max-per-method basis, debug info cannot land in
1245 // this killed area.
1246 uint r_cnt = mcall->tf()->range()->cnt();
1247 MachProjNode *proj = new (C, 1) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1248 if (!RegMask::can_represent(OptoReg::Name(out_arg_limit_per_call-1))) {
1249 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1250 } else {
1251 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1252 proj->_rout.Insert(OptoReg::Name(i));
1253 }
1254 if( proj->_rout.is_NotEmpty() )
1255 _proj_list.push(proj);
1256 }
1257 // Transfer the safepoint information from the call to the mcall
1258 // Move the JVMState list
1259 msfpt->set_jvms(sfpt->jvms());
1260 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1261 jvms->set_map(sfpt);
1262 }
1263
1264 // Debug inputs begin just after the last incoming parameter
1265 assert( (mcall == NULL) || (mcall->jvms() == NULL) ||
1266 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" );
1267
1268 // Move the OopMap
1269 msfpt->_oop_map = sfpt->_oop_map;
1270
1271 // Registers killed by the call are set in the local scheduling pass
1272 // of Global Code Motion.
1273 return msfpt;
1274 }
1275
1276 //---------------------------match_tree----------------------------------------
1277 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1278 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1279 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1280 // a Load's result RegMask for memoization in idealreg2regmask[]
1281 MachNode *Matcher::match_tree( const Node *n ) {
1282 assert( n->Opcode() != Op_Phi, "cannot match" );
1283 assert( !n->is_block_start(), "cannot match" );
1284 // Set the mark for all locally allocated State objects.
1285 // When this call returns, the _states_arena arena will be reset
1286 // freeing all State objects.
1287 ResourceMark rm( &_states_arena );
1288
1289 LabelRootDepth = 0;
1290
1291 // StoreNodes require their Memory input to match any LoadNodes
1292 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1293 #ifdef ASSERT
1294 Node* save_mem_node = _mem_node;
1295 _mem_node = n->is_Store() ? (Node*)n : NULL;
1296 #endif
1297 // State object for root node of match tree
1298 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1299 State *s = new (&_states_arena) State;
1300 s->_kids[0] = NULL;
1301 s->_kids[1] = NULL;
1302 s->_leaf = (Node*)n;
1303 // Label the input tree, allocating labels from top-level arena
1304 Label_Root( n, s, n->in(0), mem );
1305 if (C->failing()) return NULL;
1306
1307 // The minimum cost match for the whole tree is found at the root State
1308 uint mincost = max_juint;
1309 uint cost = max_juint;
1310 uint i;
1311 for( i = 0; i < NUM_OPERANDS; i++ ) {
1312 if( s->valid(i) && // valid entry and
1313 s->_cost[i] < cost && // low cost and
1314 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1315 cost = s->_cost[mincost=i];
1316 }
1317 if (mincost == max_juint) {
1318 #ifndef PRODUCT
1319 tty->print("No matching rule for:");
1320 s->dump();
1321 #endif
1322 Matcher::soft_match_failure();
1323 return NULL;
1324 }
1325 // Reduce input tree based upon the state labels to machine Nodes
1326 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1327 #ifdef ASSERT
1328 _old2new_map.map(n->_idx, m);
1329 _new2old_map.map(m->_idx, (Node*)n);
1330 #endif
1331
1332 // Add any Matcher-ignored edges
1333 uint cnt = n->req();
1334 uint start = 1;
1335 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1336 if( n->is_AddP() ) {
1337 assert( mem == (Node*)1, "" );
1338 start = AddPNode::Base+1;
1339 }
1340 for( i = start; i < cnt; i++ ) {
1341 if( !n->match_edge(i) ) {
1342 if( i < m->req() )
1343 m->ins_req( i, n->in(i) );
1344 else
1345 m->add_req( n->in(i) );
1346 }
1347 }
1348
1349 debug_only( _mem_node = save_mem_node; )
1350 return m;
1351 }
1352
1353
1354 //------------------------------match_into_reg---------------------------------
1355 // Choose to either match this Node in a register or part of the current
1356 // match tree. Return true for requiring a register and false for matching
1357 // as part of the current match tree.
1358 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1359
1360 const Type *t = m->bottom_type();
1361
1362 if( t->singleton() ) {
1363 // Never force constants into registers. Allow them to match as
1364 // constants or registers. Copies of the same value will share
1365 // the same register. See find_shared_node.
1366 return false;
1367 } else { // Not a constant
1368 // Stop recursion if they have different Controls.
1369 // Slot 0 of constants is not really a Control.
1370 if( control && m->in(0) && control != m->in(0) ) {
1371
1372 // Actually, we can live with the most conservative control we
1373 // find, if it post-dominates the others. This allows us to
1374 // pick up load/op/store trees where the load can float a little
1375 // above the store.
1376 Node *x = control;
1377 const uint max_scan = 6; // Arbitrary scan cutoff
1378 uint j;
1379 for( j=0; j<max_scan; j++ ) {
1380 if( x->is_Region() ) // Bail out at merge points
1381 return true;
1382 x = x->in(0);
1383 if( x == m->in(0) ) // Does 'control' post-dominate
1384 break; // m->in(0)? If so, we can use it
1385 }
1386 if( j == max_scan ) // No post-domination before scan end?
1387 return true; // Then break the match tree up
1388 }
1389 if (m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) {
1390 // These are commonly used in address expressions and can
1391 // efficiently fold into them on X64 in some cases.
1392 return false;
1393 }
1394 }
1395
1396 // Not forceable cloning. If shared, put it into a register.
1397 return shared;
1398 }
1399
1400
1401 //------------------------------Instruction Selection--------------------------
1402 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1403 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1404 // things the Matcher does not match (e.g., Memory), and things with different
1405 // Controls (hence forced into different blocks). We pass in the Control
1406 // selected for this entire State tree.
1407
1408 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1409 // Store and the Load must have identical Memories (as well as identical
1410 // pointers). Since the Matcher does not have anything for Memory (and
1411 // does not handle DAGs), I have to match the Memory input myself. If the
1412 // Tree root is a Store, I require all Loads to have the identical memory.
1413 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1414 // Since Label_Root is a recursive function, its possible that we might run
1415 // out of stack space. See bugs 6272980 & 6227033 for more info.
1416 LabelRootDepth++;
1417 if (LabelRootDepth > MaxLabelRootDepth) {
1418 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1419 return NULL;
1420 }
1421 uint care = 0; // Edges matcher cares about
1422 uint cnt = n->req();
1423 uint i = 0;
1424
1425 // Examine children for memory state
1426 // Can only subsume a child into your match-tree if that child's memory state
1427 // is not modified along the path to another input.
1428 // It is unsafe even if the other inputs are separate roots.
1429 Node *input_mem = NULL;
1430 for( i = 1; i < cnt; i++ ) {
1431 if( !n->match_edge(i) ) continue;
1432 Node *m = n->in(i); // Get ith input
1433 assert( m, "expect non-null children" );
1434 if( m->is_Load() ) {
1435 if( input_mem == NULL ) {
1436 input_mem = m->in(MemNode::Memory);
1437 } else if( input_mem != m->in(MemNode::Memory) ) {
1438 input_mem = NodeSentinel;
1439 }
1440 }
1441 }
1442
1443 for( i = 1; i < cnt; i++ ){// For my children
1444 if( !n->match_edge(i) ) continue;
1445 Node *m = n->in(i); // Get ith input
1446 // Allocate states out of a private arena
1447 State *s = new (&_states_arena) State;
1448 svec->_kids[care++] = s;
1449 assert( care <= 2, "binary only for now" );
1450
1451 // Recursively label the State tree.
1452 s->_kids[0] = NULL;
1453 s->_kids[1] = NULL;
1454 s->_leaf = m;
1455
1456 // Check for leaves of the State Tree; things that cannot be a part of
1457 // the current tree. If it finds any, that value is matched as a
1458 // register operand. If not, then the normal matching is used.
1459 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1460 //
1461 // Stop recursion if this is LoadNode and the root of this tree is a
1462 // StoreNode and the load & store have different memories.
1463 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1464 // Can NOT include the match of a subtree when its memory state
1465 // is used by any of the other subtrees
1466 (input_mem == NodeSentinel) ) {
1467 #ifndef PRODUCT
1468 // Print when we exclude matching due to different memory states at input-loads
1469 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1470 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1471 tty->print_cr("invalid input_mem");
1472 }
1473 #endif
1474 // Switch to a register-only opcode; this value must be in a register
1475 // and cannot be subsumed as part of a larger instruction.
1476 s->DFA( m->ideal_reg(), m );
1477
1478 } else {
1479 // If match tree has no control and we do, adopt it for entire tree
1480 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1481 control = m->in(0); // Pick up control
1482 // Else match as a normal part of the match tree.
1483 control = Label_Root(m,s,control,mem);
1484 if (C->failing()) return NULL;
1485 }
1486 }
1487
1488
1489 // Call DFA to match this node, and return
1490 svec->DFA( n->Opcode(), n );
1491
1492 #ifdef ASSERT
1493 uint x;
1494 for( x = 0; x < _LAST_MACH_OPER; x++ )
1495 if( svec->valid(x) )
1496 break;
1497
1498 if (x >= _LAST_MACH_OPER) {
1499 n->dump();
1500 svec->dump();
1501 assert( false, "bad AD file" );
1502 }
1503 #endif
1504 return control;
1505 }
1506
1507
1508 // Con nodes reduced using the same rule can share their MachNode
1509 // which reduces the number of copies of a constant in the final
1510 // program. The register allocator is free to split uses later to
1511 // split live ranges.
1512 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1513 if (!leaf->is_Con() && !leaf->is_DecodeN()) return NULL;
1514
1515 // See if this Con has already been reduced using this rule.
1516 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1517 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1518 if (last != NULL && rule == last->rule()) {
1519 // Don't expect control change for DecodeN
1520 if (leaf->is_DecodeN())
1521 return last;
1522 // Get the new space root.
1523 Node* xroot = new_node(C->root());
1524 if (xroot == NULL) {
1525 // This shouldn't happen give the order of matching.
1526 return NULL;
1527 }
1528
1529 // Shared constants need to have their control be root so they
1530 // can be scheduled properly.
1531 Node* control = last->in(0);
1532 if (control != xroot) {
1533 if (control == NULL || control == C->root()) {
1534 last->set_req(0, xroot);
1535 } else {
1536 assert(false, "unexpected control");
1537 return NULL;
1538 }
1539 }
1540 return last;
1541 }
1542 return NULL;
1543 }
1544
1545
1546 //------------------------------ReduceInst-------------------------------------
1547 // Reduce a State tree (with given Control) into a tree of MachNodes.
1548 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1549 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1550 // Each MachNode has a number of complicated MachOper operands; each
1551 // MachOper also covers a further tree of Ideal Nodes.
1552
1553 // The root of the Ideal match tree is always an instruction, so we enter
1554 // the recursion here. After building the MachNode, we need to recurse
1555 // the tree checking for these cases:
1556 // (1) Child is an instruction -
1557 // Build the instruction (recursively), add it as an edge.
1558 // Build a simple operand (register) to hold the result of the instruction.
1559 // (2) Child is an interior part of an instruction -
1560 // Skip over it (do nothing)
1561 // (3) Child is the start of a operand -
1562 // Build the operand, place it inside the instruction
1563 // Call ReduceOper.
1564 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1565 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1566
1567 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1568 if (shared_node != NULL) {
1569 return shared_node;
1570 }
1571
1572 // Build the object to represent this state & prepare for recursive calls
1573 MachNode *mach = s->MachNodeGenerator( rule, C );
1574 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1575 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1576 Node *leaf = s->_leaf;
1577 // Check for instruction or instruction chain rule
1578 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1579 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1580 "duplicating node that's already been matched");
1581 // Instruction
1582 mach->add_req( leaf->in(0) ); // Set initial control
1583 // Reduce interior of complex instruction
1584 ReduceInst_Interior( s, rule, mem, mach, 1 );
1585 } else {
1586 // Instruction chain rules are data-dependent on their inputs
1587 mach->add_req(0); // Set initial control to none
1588 ReduceInst_Chain_Rule( s, rule, mem, mach );
1589 }
1590
1591 // If a Memory was used, insert a Memory edge
1592 if( mem != (Node*)1 ) {
1593 mach->ins_req(MemNode::Memory,mem);
1594 #ifdef ASSERT
1595 // Verify adr type after matching memory operation
1596 const MachOper* oper = mach->memory_operand();
1597 if (oper != NULL && oper != (MachOper*)-1) {
1598 // It has a unique memory operand. Find corresponding ideal mem node.
1599 Node* m = NULL;
1600 if (leaf->is_Mem()) {
1601 m = leaf;
1602 } else {
1603 m = _mem_node;
1604 assert(m != NULL && m->is_Mem(), "expecting memory node");
1605 }
1606 const Type* mach_at = mach->adr_type();
1607 // DecodeN node consumed by an address may have different type
1608 // then its input. Don't compare types for such case.
1609 if (m->adr_type() != mach_at &&
1610 (m->in(MemNode::Address)->is_DecodeN() ||
1611 m->in(MemNode::Address)->is_AddP() &&
1612 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeN() ||
1613 m->in(MemNode::Address)->is_AddP() &&
1614 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1615 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeN())) {
1616 mach_at = m->adr_type();
1617 }
1618 if (m->adr_type() != mach_at) {
1619 m->dump();
1620 tty->print_cr("mach:");
1621 mach->dump(1);
1622 }
1623 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1624 }
1625 #endif
1626 }
1627
1628 // If the _leaf is an AddP, insert the base edge
1629 if( leaf->is_AddP() )
1630 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1631
1632 uint num_proj = _proj_list.size();
1633
1634 // Perform any 1-to-many expansions required
1635 MachNode *ex = mach->Expand(s,_proj_list, mem);
1636 if( ex != mach ) {
1637 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1638 if( ex->in(1)->is_Con() )
1639 ex->in(1)->set_req(0, C->root());
1640 // Remove old node from the graph
1641 for( uint i=0; i<mach->req(); i++ ) {
1642 mach->set_req(i,NULL);
1643 }
1644 #ifdef ASSERT
1645 _new2old_map.map(ex->_idx, s->_leaf);
1646 #endif
1647 }
1648
1649 // PhaseChaitin::fixup_spills will sometimes generate spill code
1650 // via the matcher. By the time, nodes have been wired into the CFG,
1651 // and any further nodes generated by expand rules will be left hanging
1652 // in space, and will not get emitted as output code. Catch this.
1653 // Also, catch any new register allocation constraints ("projections")
1654 // generated belatedly during spill code generation.
1655 if (_allocation_started) {
1656 guarantee(ex == mach, "no expand rules during spill generation");
1657 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation");
1658 }
1659
1660 if (leaf->is_Con() || leaf->is_DecodeN()) {
1661 // Record the con for sharing
1662 _shared_nodes.map(leaf->_idx, ex);
1663 }
1664
1665 return ex;
1666 }
1667
1668 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1669 // 'op' is what I am expecting to receive
1670 int op = _leftOp[rule];
1671 // Operand type to catch childs result
1672 // This is what my child will give me.
1673 int opnd_class_instance = s->_rule[op];
1674 // Choose between operand class or not.
1675 // This is what I will receive.
1676 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1677 // New rule for child. Chase operand classes to get the actual rule.
1678 int newrule = s->_rule[catch_op];
1679
1680 if( newrule < NUM_OPERANDS ) {
1681 // Chain from operand or operand class, may be output of shared node
1682 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1683 "Bad AD file: Instruction chain rule must chain from operand");
1684 // Insert operand into array of operands for this instruction
1685 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1686
1687 ReduceOper( s, newrule, mem, mach );
1688 } else {
1689 // Chain from the result of an instruction
1690 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1691 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1692 Node *mem1 = (Node*)1;
1693 debug_only(Node *save_mem_node = _mem_node;)
1694 mach->add_req( ReduceInst(s, newrule, mem1) );
1695 debug_only(_mem_node = save_mem_node;)
1696 }
1697 return;
1698 }
1699
1700
1701 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1702 if( s->_leaf->is_Load() ) {
1703 Node *mem2 = s->_leaf->in(MemNode::Memory);
1704 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1705 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1706 mem = mem2;
1707 }
1708 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1709 if( mach->in(0) == NULL )
1710 mach->set_req(0, s->_leaf->in(0));
1711 }
1712
1713 // Now recursively walk the state tree & add operand list.
1714 for( uint i=0; i<2; i++ ) { // binary tree
1715 State *newstate = s->_kids[i];
1716 if( newstate == NULL ) break; // Might only have 1 child
1717 // 'op' is what I am expecting to receive
1718 int op;
1719 if( i == 0 ) {
1720 op = _leftOp[rule];
1721 } else {
1722 op = _rightOp[rule];
1723 }
1724 // Operand type to catch childs result
1725 // This is what my child will give me.
1726 int opnd_class_instance = newstate->_rule[op];
1727 // Choose between operand class or not.
1728 // This is what I will receive.
1729 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1730 // New rule for child. Chase operand classes to get the actual rule.
1731 int newrule = newstate->_rule[catch_op];
1732
1733 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1734 // Operand/operandClass
1735 // Insert operand into array of operands for this instruction
1736 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1737 ReduceOper( newstate, newrule, mem, mach );
1738
1739 } else { // Child is internal operand or new instruction
1740 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1741 // internal operand --> call ReduceInst_Interior
1742 // Interior of complex instruction. Do nothing but recurse.
1743 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1744 } else {
1745 // instruction --> call build operand( ) to catch result
1746 // --> ReduceInst( newrule )
1747 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1748 Node *mem1 = (Node*)1;
1749 debug_only(Node *save_mem_node = _mem_node;)
1750 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1751 debug_only(_mem_node = save_mem_node;)
1752 }
1753 }
1754 assert( mach->_opnds[num_opnds-1], "" );
1755 }
1756 return num_opnds;
1757 }
1758
1759 // This routine walks the interior of possible complex operands.
1760 // At each point we check our children in the match tree:
1761 // (1) No children -
1762 // We are a leaf; add _leaf field as an input to the MachNode
1763 // (2) Child is an internal operand -
1764 // Skip over it ( do nothing )
1765 // (3) Child is an instruction -
1766 // Call ReduceInst recursively and
1767 // and instruction as an input to the MachNode
1768 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1769 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1770 State *kid = s->_kids[0];
1771 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1772
1773 // Leaf? And not subsumed?
1774 if( kid == NULL && !_swallowed[rule] ) {
1775 mach->add_req( s->_leaf ); // Add leaf pointer
1776 return; // Bail out
1777 }
1778
1779 if( s->_leaf->is_Load() ) {
1780 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1781 mem = s->_leaf->in(MemNode::Memory);
1782 debug_only(_mem_node = s->_leaf;)
1783 }
1784 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1785 if( !mach->in(0) )
1786 mach->set_req(0,s->_leaf->in(0));
1787 else {
1788 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1789 }
1790 }
1791
1792 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1793 int newrule;
1794 if( i == 0 )
1795 newrule = kid->_rule[_leftOp[rule]];
1796 else
1797 newrule = kid->_rule[_rightOp[rule]];
1798
1799 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1800 // Internal operand; recurse but do nothing else
1801 ReduceOper( kid, newrule, mem, mach );
1802
1803 } else { // Child is a new instruction
1804 // Reduce the instruction, and add a direct pointer from this
1805 // machine instruction to the newly reduced one.
1806 Node *mem1 = (Node*)1;
1807 debug_only(Node *save_mem_node = _mem_node;)
1808 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1809 debug_only(_mem_node = save_mem_node;)
1810 }
1811 }
1812 }
1813
1814
1815 // -------------------------------------------------------------------------
1816 // Java-Java calling convention
1817 // (what you use when Java calls Java)
1818
1819 //------------------------------find_receiver----------------------------------
1820 // For a given signature, return the OptoReg for parameter 0.
1821 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1822 VMRegPair regs;
1823 BasicType sig_bt = T_OBJECT;
1824 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1825 // Return argument 0 register. In the LP64 build pointers
1826 // take 2 registers, but the VM wants only the 'main' name.
1827 return OptoReg::as_OptoReg(regs.first());
1828 }
1829
1830 // A method-klass-holder may be passed in the inline_cache_reg
1831 // and then expanded into the inline_cache_reg and a method_oop register
1832 // defined in ad_<arch>.cpp
1833
1834
1835 //------------------------------find_shared------------------------------------
1836 // Set bits if Node is shared or otherwise a root
1837 void Matcher::find_shared( Node *n ) {
1838 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
1839 MStack mstack(C->unique() * 2);
1840 // Mark nodes as address_visited if they are inputs to an address expression
1841 VectorSet address_visited(Thread::current()->resource_area());
1842 mstack.push(n, Visit); // Don't need to pre-visit root node
1843 while (mstack.is_nonempty()) {
1844 n = mstack.node(); // Leave node on stack
1845 Node_State nstate = mstack.state();
1846 uint nop = n->Opcode();
1847 if (nstate == Pre_Visit) {
1848 if (address_visited.test(n->_idx)) { // Visited in address already?
1849 // Flag as visited and shared now.
1850 set_visited(n);
1851 }
1852 if (is_visited(n)) { // Visited already?
1853 // Node is shared and has no reason to clone. Flag it as shared.
1854 // This causes it to match into a register for the sharing.
1855 set_shared(n); // Flag as shared and
1856 mstack.pop(); // remove node from stack
1857 continue;
1858 }
1859 nstate = Visit; // Not already visited; so visit now
1860 }
1861 if (nstate == Visit) {
1862 mstack.set_state(Post_Visit);
1863 set_visited(n); // Flag as visited now
1864 bool mem_op = false;
1865
1866 switch( nop ) { // Handle some opcodes special
1867 case Op_Phi: // Treat Phis as shared roots
1868 case Op_Parm:
1869 case Op_Proj: // All handled specially during matching
1870 case Op_SafePointScalarObject:
1871 set_shared(n);
1872 set_dontcare(n);
1873 break;
1874 case Op_If:
1875 case Op_CountedLoopEnd:
1876 mstack.set_state(Alt_Post_Visit); // Alternative way
1877 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
1878 // with matching cmp/branch in 1 instruction. The Matcher needs the
1879 // Bool and CmpX side-by-side, because it can only get at constants
1880 // that are at the leaves of Match trees, and the Bool's condition acts
1881 // as a constant here.
1882 mstack.push(n->in(1), Visit); // Clone the Bool
1883 mstack.push(n->in(0), Pre_Visit); // Visit control input
1884 continue; // while (mstack.is_nonempty())
1885 case Op_ConvI2D: // These forms efficiently match with a prior
1886 case Op_ConvI2F: // Load but not a following Store
1887 if( n->in(1)->is_Load() && // Prior load
1888 n->outcnt() == 1 && // Not already shared
1889 n->unique_out()->is_Store() ) // Following store
1890 set_shared(n); // Force it to be a root
1891 break;
1892 case Op_ReverseBytesI:
1893 case Op_ReverseBytesL:
1894 if( n->in(1)->is_Load() && // Prior load
1895 n->outcnt() == 1 ) // Not already shared
1896 set_shared(n); // Force it to be a root
1897 break;
1898 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
1899 case Op_IfFalse:
1900 case Op_IfTrue:
1901 case Op_MachProj:
1902 case Op_MergeMem:
1903 case Op_Catch:
1904 case Op_CatchProj:
1905 case Op_CProj:
1906 case Op_JumpProj:
1907 case Op_JProj:
1908 case Op_NeverBranch:
1909 set_dontcare(n);
1910 break;
1911 case Op_Jump:
1912 mstack.push(n->in(1), Visit); // Switch Value
1913 mstack.push(n->in(0), Pre_Visit); // Visit Control input
1914 continue; // while (mstack.is_nonempty())
1915 case Op_StrComp:
1916 case Op_StrEquals:
1917 case Op_StrIndexOf:
1918 case Op_AryEq:
1919 set_shared(n); // Force result into register (it will be anyways)
1920 break;
1921 case Op_ConP: { // Convert pointers above the centerline to NUL
1922 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1923 const TypePtr* tp = tn->type()->is_ptr();
1924 if (tp->_ptr == TypePtr::AnyNull) {
1925 tn->set_type(TypePtr::NULL_PTR);
1926 }
1927 break;
1928 }
1929 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
1930 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1931 const TypePtr* tp = tn->type()->make_ptr();
1932 if (tp && tp->_ptr == TypePtr::AnyNull) {
1933 tn->set_type(TypeNarrowOop::NULL_PTR);
1934 }
1935 break;
1936 }
1937 case Op_Binary: // These are introduced in the Post_Visit state.
1938 ShouldNotReachHere();
1939 break;
1940 case Op_ClearArray:
1941 case Op_SafePoint:
1942 mem_op = true;
1943 break;
1944 default:
1945 if( n->is_Store() ) {
1946 // Do match stores, despite no ideal reg
1947 mem_op = true;
1948 break;
1949 }
1950 if( n->is_Mem() ) { // Loads and LoadStores
1951 mem_op = true;
1952 // Loads must be root of match tree due to prior load conflict
1953 if( C->subsume_loads() == false )
1954 set_shared(n);
1955 }
1956 // Fall into default case
1957 if( !n->ideal_reg() )
1958 set_dontcare(n); // Unmatchable Nodes
1959 } // end_switch
1960
1961 for(int i = n->req() - 1; i >= 0; --i) { // For my children
1962 Node *m = n->in(i); // Get ith input
1963 if (m == NULL) continue; // Ignore NULLs
1964 uint mop = m->Opcode();
1965
1966 // Must clone all producers of flags, or we will not match correctly.
1967 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
1968 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
1969 // are also there, so we may match a float-branch to int-flags and
1970 // expect the allocator to haul the flags from the int-side to the
1971 // fp-side. No can do.
1972 if( _must_clone[mop] ) {
1973 mstack.push(m, Visit);
1974 continue; // for(int i = ...)
1975 }
1976
1977 if( mop == Op_AddP && m->in(AddPNode::Base)->Opcode() == Op_DecodeN ) {
1978 // Bases used in addresses must be shared but since
1979 // they are shared through a DecodeN they may appear
1980 // to have a single use so force sharing here.
1981 set_shared(m->in(AddPNode::Base)->in(1));
1982 }
1983
1984 // Clone addressing expressions as they are "free" in memory access instructions
1985 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
1986 // Some inputs for address expression are not put on stack
1987 // to avoid marking them as shared and forcing them into register
1988 // if they are used only in address expressions.
1989 // But they should be marked as shared if there are other uses
1990 // besides address expressions.
1991
1992 Node *off = m->in(AddPNode::Offset);
1993 if( off->is_Con() &&
1994 // When there are other uses besides address expressions
1995 // put it on stack and mark as shared.
1996 !is_visited(m) ) {
1997 address_visited.test_set(m->_idx); // Flag as address_visited
1998 Node *adr = m->in(AddPNode::Address);
1999
2000 // Intel, ARM and friends can handle 2 adds in addressing mode
2001 if( clone_shift_expressions && adr->is_AddP() &&
2002 // AtomicAdd is not an addressing expression.
2003 // Cheap to find it by looking for screwy base.
2004 !adr->in(AddPNode::Base)->is_top() &&
2005 // Are there other uses besides address expressions?
2006 !is_visited(adr) ) {
2007 address_visited.set(adr->_idx); // Flag as address_visited
2008 Node *shift = adr->in(AddPNode::Offset);
2009 // Check for shift by small constant as well
2010 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2011 shift->in(2)->get_int() <= 3 &&
2012 // Are there other uses besides address expressions?
2013 !is_visited(shift) ) {
2014 address_visited.set(shift->_idx); // Flag as address_visited
2015 mstack.push(shift->in(2), Visit);
2016 Node *conv = shift->in(1);
2017 #ifdef _LP64
2018 // Allow Matcher to match the rule which bypass
2019 // ConvI2L operation for an array index on LP64
2020 // if the index value is positive.
2021 if( conv->Opcode() == Op_ConvI2L &&
2022 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2023 // Are there other uses besides address expressions?
2024 !is_visited(conv) ) {
2025 address_visited.set(conv->_idx); // Flag as address_visited
2026 mstack.push(conv->in(1), Pre_Visit);
2027 } else
2028 #endif
2029 mstack.push(conv, Pre_Visit);
2030 } else {
2031 mstack.push(shift, Pre_Visit);
2032 }
2033 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2034 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2035 } else { // Sparc, Alpha, PPC and friends
2036 mstack.push(adr, Pre_Visit);
2037 }
2038
2039 // Clone X+offset as it also folds into most addressing expressions
2040 mstack.push(off, Visit);
2041 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2042 continue; // for(int i = ...)
2043 } // if( off->is_Con() )
2044 } // if( mem_op &&
2045 mstack.push(m, Pre_Visit);
2046 } // for(int i = ...)
2047 }
2048 else if (nstate == Alt_Post_Visit) {
2049 mstack.pop(); // Remove node from stack
2050 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2051 // shared and all users of the Bool need to move the Cmp in parallel.
2052 // This leaves both the Bool and the If pointing at the Cmp. To
2053 // prevent the Matcher from trying to Match the Cmp along both paths
2054 // BoolNode::match_edge always returns a zero.
2055
2056 // We reorder the Op_If in a pre-order manner, so we can visit without
2057 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2058 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2059 }
2060 else if (nstate == Post_Visit) {
2061 mstack.pop(); // Remove node from stack
2062
2063 // Now hack a few special opcodes
2064 switch( n->Opcode() ) { // Handle some opcodes special
2065 case Op_StorePConditional:
2066 case Op_StoreIConditional:
2067 case Op_StoreLConditional:
2068 case Op_CompareAndSwapI:
2069 case Op_CompareAndSwapL:
2070 case Op_CompareAndSwapP:
2071 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2072 Node *newval = n->in(MemNode::ValueIn );
2073 Node *oldval = n->in(LoadStoreNode::ExpectedIn);
2074 Node *pair = new (C, 3) BinaryNode( oldval, newval );
2075 n->set_req(MemNode::ValueIn,pair);
2076 n->del_req(LoadStoreNode::ExpectedIn);
2077 break;
2078 }
2079 case Op_CMoveD: // Convert trinary to binary-tree
2080 case Op_CMoveF:
2081 case Op_CMoveI:
2082 case Op_CMoveL:
2083 case Op_CMoveN:
2084 case Op_CMoveP: {
2085 // Restructure into a binary tree for Matching. It's possible that
2086 // we could move this code up next to the graph reshaping for IfNodes
2087 // or vice-versa, but I do not want to debug this for Ladybird.
2088 // 10/2/2000 CNC.
2089 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(1)->in(1));
2090 n->set_req(1,pair1);
2091 Node *pair2 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2092 n->set_req(2,pair2);
2093 n->del_req(3);
2094 break;
2095 }
2096 case Op_LoopLimit: {
2097 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(2));
2098 n->set_req(1,pair1);
2099 n->set_req(2,n->in(3));
2100 n->del_req(3);
2101 break;
2102 }
2103 case Op_StrEquals: {
2104 Node *pair1 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2105 n->set_req(2,pair1);
2106 n->set_req(3,n->in(4));
2107 n->del_req(4);
2108 break;
2109 }
2110 case Op_StrComp:
2111 case Op_StrIndexOf: {
2112 Node *pair1 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2113 n->set_req(2,pair1);
2114 Node *pair2 = new (C, 3) BinaryNode(n->in(4),n->in(5));
2115 n->set_req(3,pair2);
2116 n->del_req(5);
2117 n->del_req(4);
2118 break;
2119 }
2120 default:
2121 break;
2122 }
2123 }
2124 else {
2125 ShouldNotReachHere();
2126 }
2127 } // end of while (mstack.is_nonempty())
2128 }
2129
2130 #ifdef ASSERT
2131 // machine-independent root to machine-dependent root
2132 void Matcher::dump_old2new_map() {
2133 _old2new_map.dump();
2134 }
2135 #endif
2136
2137 //---------------------------collect_null_checks-------------------------------
2138 // Find null checks in the ideal graph; write a machine-specific node for
2139 // it. Used by later implicit-null-check handling. Actually collects
2140 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2141 // value being tested.
2142 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2143 Node *iff = proj->in(0);
2144 if( iff->Opcode() == Op_If ) {
2145 // During matching If's have Bool & Cmp side-by-side
2146 BoolNode *b = iff->in(1)->as_Bool();
2147 Node *cmp = iff->in(2);
2148 int opc = cmp->Opcode();
2149 if (opc != Op_CmpP && opc != Op_CmpN) return;
2150
2151 const Type* ct = cmp->in(2)->bottom_type();
2152 if (ct == TypePtr::NULL_PTR ||
2153 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2154
2155 bool push_it = false;
2156 if( proj->Opcode() == Op_IfTrue ) {
2157 extern int all_null_checks_found;
2158 all_null_checks_found++;
2159 if( b->_test._test == BoolTest::ne ) {
2160 push_it = true;
2161 }
2162 } else {
2163 assert( proj->Opcode() == Op_IfFalse, "" );
2164 if( b->_test._test == BoolTest::eq ) {
2165 push_it = true;
2166 }
2167 }
2168 if( push_it ) {
2169 _null_check_tests.push(proj);
2170 Node* val = cmp->in(1);
2171 #ifdef _LP64
2172 if (val->bottom_type()->isa_narrowoop() &&
2173 !Matcher::narrow_oop_use_complex_address()) {
2174 //
2175 // Look for DecodeN node which should be pinned to orig_proj.
2176 // On platforms (Sparc) which can not handle 2 adds
2177 // in addressing mode we have to keep a DecodeN node and
2178 // use it to do implicit NULL check in address.
2179 //
2180 // DecodeN node was pinned to non-null path (orig_proj) during
2181 // CastPP transformation in final_graph_reshaping_impl().
2182 //
2183 uint cnt = orig_proj->outcnt();
2184 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2185 Node* d = orig_proj->raw_out(i);
2186 if (d->is_DecodeN() && d->in(1) == val) {
2187 val = d;
2188 val->set_req(0, NULL); // Unpin now.
2189 // Mark this as special case to distinguish from
2190 // a regular case: CmpP(DecodeN, NULL).
2191 val = (Node*)(((intptr_t)val) | 1);
2192 break;
2193 }
2194 }
2195 }
2196 #endif
2197 _null_check_tests.push(val);
2198 }
2199 }
2200 }
2201 }
2202
2203 //---------------------------validate_null_checks------------------------------
2204 // Its possible that the value being NULL checked is not the root of a match
2205 // tree. If so, I cannot use the value in an implicit null check.
2206 void Matcher::validate_null_checks( ) {
2207 uint cnt = _null_check_tests.size();
2208 for( uint i=0; i < cnt; i+=2 ) {
2209 Node *test = _null_check_tests[i];
2210 Node *val = _null_check_tests[i+1];
2211 bool is_decoden = ((intptr_t)val) & 1;
2212 val = (Node*)(((intptr_t)val) & ~1);
2213 if (has_new_node(val)) {
2214 Node* new_val = new_node(val);
2215 if (is_decoden) {
2216 assert(val->is_DecodeN() && val->in(0) == NULL, "sanity");
2217 // Note: new_val may have a control edge if
2218 // the original ideal node DecodeN was matched before
2219 // it was unpinned in Matcher::collect_null_checks().
2220 // Unpin the mach node and mark it.
2221 new_val->set_req(0, NULL);
2222 new_val = (Node*)(((intptr_t)new_val) | 1);
2223 }
2224 // Is a match-tree root, so replace with the matched value
2225 _null_check_tests.map(i+1, new_val);
2226 } else {
2227 // Yank from candidate list
2228 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2229 _null_check_tests.map(i,_null_check_tests[--cnt]);
2230 _null_check_tests.pop();
2231 _null_check_tests.pop();
2232 i-=2;
2233 }
2234 }
2235 }
2236
2237 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2238 // atomic instruction acting as a store_load barrier without any
2239 // intervening volatile load, and thus we don't need a barrier here.
2240 // We retain the Node to act as a compiler ordering barrier.
2241 bool Matcher::post_store_load_barrier(const Node *vmb) {
2242 Compile *C = Compile::current();
2243 assert( vmb->is_MemBar(), "" );
2244 assert( vmb->Opcode() != Op_MemBarAcquire, "" );
2245 const MemBarNode *mem = (const MemBarNode*)vmb;
2246
2247 // Get the Proj node, ctrl, that can be used to iterate forward
2248 Node *ctrl = NULL;
2249 DUIterator_Fast imax, i = mem->fast_outs(imax);
2250 while( true ) {
2251 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2252 assert( ctrl->is_Proj(), "only projections here" );
2253 ProjNode *proj = (ProjNode*)ctrl;
2254 if( proj->_con == TypeFunc::Control &&
2255 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2256 break;
2257 i++;
2258 }
2259
2260 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2261 Node *x = ctrl->fast_out(j);
2262 int xop = x->Opcode();
2263
2264 // We don't need current barrier if we see another or a lock
2265 // before seeing volatile load.
2266 //
2267 // Op_Fastunlock previously appeared in the Op_* list below.
2268 // With the advent of 1-0 lock operations we're no longer guaranteed
2269 // that a monitor exit operation contains a serializing instruction.
2270
2271 if (xop == Op_MemBarVolatile ||
2272 xop == Op_FastLock ||
2273 xop == Op_CompareAndSwapL ||
2274 xop == Op_CompareAndSwapP ||
2275 xop == Op_CompareAndSwapN ||
2276 xop == Op_CompareAndSwapI)
2277 return true;
2278
2279 if (x->is_MemBar()) {
2280 // We must retain this membar if there is an upcoming volatile
2281 // load, which will be preceded by acquire membar.
2282 if (xop == Op_MemBarAcquire)
2283 return false;
2284 // For other kinds of barriers, check by pretending we
2285 // are them, and seeing if we can be removed.
2286 else
2287 return post_store_load_barrier((const MemBarNode*)x);
2288 }
2289
2290 // Delicate code to detect case of an upcoming fastlock block
2291 if( x->is_If() && x->req() > 1 &&
2292 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2293 Node *iff = x;
2294 Node *bol = iff->in(1);
2295 // The iff might be some random subclass of If or bol might be Con-Top
2296 if (!bol->is_Bool()) return false;
2297 assert( bol->req() > 1, "" );
2298 return (bol->in(1)->Opcode() == Op_FastUnlock);
2299 }
2300 // probably not necessary to check for these
2301 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj())
2302 return false;
2303 }
2304 return false;
2305 }
2306
2307 //=============================================================================
2308 //---------------------------State---------------------------------------------
2309 State::State(void) {
2310 #ifdef ASSERT
2311 _id = 0;
2312 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2313 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2314 //memset(_cost, -1, sizeof(_cost));
2315 //memset(_rule, -1, sizeof(_rule));
2316 #endif
2317 memset(_valid, 0, sizeof(_valid));
2318 }
2319
2320 #ifdef ASSERT
2321 State::~State() {
2322 _id = 99;
2323 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2324 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2325 memset(_cost, -3, sizeof(_cost));
2326 memset(_rule, -3, sizeof(_rule));
2327 }
2328 #endif
2329
2330 #ifndef PRODUCT
2331 //---------------------------dump----------------------------------------------
2332 void State::dump() {
2333 tty->print("\n");
2334 dump(0);
2335 }
2336
2337 void State::dump(int depth) {
2338 for( int j = 0; j < depth; j++ )
2339 tty->print(" ");
2340 tty->print("--N: ");
2341 _leaf->dump();
2342 uint i;
2343 for( i = 0; i < _LAST_MACH_OPER; i++ )
2344 // Check for valid entry
2345 if( valid(i) ) {
2346 for( int j = 0; j < depth; j++ )
2347 tty->print(" ");
2348 assert(_cost[i] != max_juint, "cost must be a valid value");
2349 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2350 tty->print_cr("%s %d %s",
2351 ruleName[i], _cost[i], ruleName[_rule[i]] );
2352 }
2353 tty->print_cr("");
2354
2355 for( i=0; i<2; i++ )
2356 if( _kids[i] )
2357 _kids[i]->dump(depth+1);
2358 }
2359 #endif