1 //
2 // Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source_hpp %{
239 // Must be visible to the DFA in dfa_x86_32.cpp
240 extern bool is_operand_hi32_zero(Node* n);
241 %}
242
243 source %{
244 #define RELOC_IMM32 Assembler::imm_operand
245 #define RELOC_DISP32 Assembler::disp32_operand
246
247 #define __ _masm.
248
249 // How to find the high register of a Long pair, given the low register
250 #define HIGH_FROM_LOW(x) ((x)+2)
251
252 // These masks are used to provide 128-bit aligned bitmasks to the XMM
253 // instructions, to allow sign-masking or sign-bit flipping. They allow
254 // fast versions of NegF/NegD and AbsF/AbsD.
255
256 // Note: 'double' and 'long long' have 32-bits alignment on x86.
257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
259 // of 128-bits operands for SSE instructions.
260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
261 // Store the value to a 128-bits operand.
262 operand[0] = lo;
263 operand[1] = hi;
264 return operand;
265 }
266
267 // Buffer for 128-bits masks used by SSE instructions.
268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
269
270 // Static initialization during VM startup.
271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
275
276 // Offset hacking within calls.
277 static int pre_call_FPU_size() {
278 if (Compile::current()->in_24_bit_fp_mode())
279 return 6; // fldcw
280 return 0;
281 }
282
283 static int preserve_SP_size() {
284 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
285 }
286
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
292 if (_method_handle_invoke)
293 offset += preserve_SP_size();
294 return offset;
295 }
296
297 int MachCallDynamicJavaNode::ret_addr_offset() {
298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
299 }
300
301 static int sizeof_FFree_Float_Stack_All = -1;
302
303 int MachCallRuntimeNode::ret_addr_offset() {
304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
306 }
307
308 // Indicate if the safepoint node needs the polling page as an input.
309 // Since x86 does have absolute addressing, it doesn't.
310 bool SafePointNode::needs_polling_address_input() {
311 return false;
312 }
313
314 //
315 // Compute padding required for nodes which need alignment
316 //
317
318 // The address of the call instruction needs to be 4-byte aligned to
319 // ensure that it does not span a cache line so that it can be patched.
320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
321 current_offset += pre_call_FPU_size(); // skip fldcw, if any
322 current_offset += 1; // skip call opcode byte
323 return round_to(current_offset, alignment_required()) - current_offset;
324 }
325
326 // The address of the call instruction needs to be 4-byte aligned to
327 // ensure that it does not span a cache line so that it can be patched.
328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
329 current_offset += pre_call_FPU_size(); // skip fldcw, if any
330 current_offset += preserve_SP_size(); // skip mov rbp, rsp
331 current_offset += 1; // skip call opcode byte
332 return round_to(current_offset, alignment_required()) - current_offset;
333 }
334
335 // The address of the call instruction needs to be 4-byte aligned to
336 // ensure that it does not span a cache line so that it can be patched.
337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset;
342 }
343
344 #ifndef PRODUCT
345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
346 st->print("INT3");
347 }
348 #endif
349
350 // EMIT_RM()
351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
353 cbuf.insts()->emit_int8(c);
354 }
355
356 // EMIT_CC()
357 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
358 unsigned char c = (unsigned char)( f1 | f2 );
359 cbuf.insts()->emit_int8(c);
360 }
361
362 // EMIT_OPCODE()
363 void emit_opcode(CodeBuffer &cbuf, int code) {
364 cbuf.insts()->emit_int8((unsigned char) code);
365 }
366
367 // EMIT_OPCODE() w/ relocation information
368 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
369 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
370 emit_opcode(cbuf, code);
371 }
372
373 // EMIT_D8()
374 void emit_d8(CodeBuffer &cbuf, int d8) {
375 cbuf.insts()->emit_int8((unsigned char) d8);
376 }
377
378 // EMIT_D16()
379 void emit_d16(CodeBuffer &cbuf, int d16) {
380 cbuf.insts()->emit_int16(d16);
381 }
382
383 // EMIT_D32()
384 void emit_d32(CodeBuffer &cbuf, int d32) {
385 cbuf.insts()->emit_int32(d32);
386 }
387
388 // emit 32 bit value and construct relocation entry from relocInfo::relocType
389 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
390 int format) {
391 cbuf.relocate(cbuf.insts_mark(), reloc, format);
392 cbuf.insts()->emit_int32(d32);
393 }
394
395 // emit 32 bit value and construct relocation entry from RelocationHolder
396 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
397 int format) {
398 #ifdef ASSERT
399 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
400 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
401 }
402 #endif
403 cbuf.relocate(cbuf.insts_mark(), rspec, format);
404 cbuf.insts()->emit_int32(d32);
405 }
406
407 // Access stack slot for load or store
408 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
409 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
410 if( -128 <= disp && disp <= 127 ) {
411 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
412 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
413 emit_d8 (cbuf, disp); // Displacement // R/M byte
414 } else {
415 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
416 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
417 emit_d32(cbuf, disp); // Displacement // R/M byte
418 }
419 }
420
421 // eRegI ereg, memory mem) %{ // emit_reg_mem
422 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
423 // There is no index & no scale, use form without SIB byte
424 if ((index == 0x4) &&
425 (scale == 0) && (base != ESP_enc)) {
426 // If no displacement, mode is 0x0; unless base is [EBP]
427 if ( (displace == 0) && (base != EBP_enc) ) {
428 emit_rm(cbuf, 0x0, reg_encoding, base);
429 }
430 else { // If 8-bit displacement, mode 0x1
431 if ((displace >= -128) && (displace <= 127)
432 && !(displace_is_oop) ) {
433 emit_rm(cbuf, 0x1, reg_encoding, base);
434 emit_d8(cbuf, displace);
435 }
436 else { // If 32-bit displacement
437 if (base == -1) { // Special flag for absolute address
438 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
439 // (manual lies; no SIB needed here)
440 if ( displace_is_oop ) {
441 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
442 } else {
443 emit_d32 (cbuf, displace);
444 }
445 }
446 else { // Normal base + offset
447 emit_rm(cbuf, 0x2, reg_encoding, base);
448 if ( displace_is_oop ) {
449 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
450 } else {
451 emit_d32 (cbuf, displace);
452 }
453 }
454 }
455 }
456 }
457 else { // Else, encode with the SIB byte
458 // If no displacement, mode is 0x0; unless base is [EBP]
459 if (displace == 0 && (base != EBP_enc)) { // If no displacement
460 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
461 emit_rm(cbuf, scale, index, base);
462 }
463 else { // If 8-bit displacement, mode 0x1
464 if ((displace >= -128) && (displace <= 127)
465 && !(displace_is_oop) ) {
466 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
467 emit_rm(cbuf, scale, index, base);
468 emit_d8(cbuf, displace);
469 }
470 else { // If 32-bit displacement
471 if (base == 0x04 ) {
472 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
473 emit_rm(cbuf, scale, index, 0x04);
474 } else {
475 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
476 emit_rm(cbuf, scale, index, base);
477 }
478 if ( displace_is_oop ) {
479 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
480 } else {
481 emit_d32 (cbuf, displace);
482 }
483 }
484 }
485 }
486 }
487
488
489 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
490 if( dst_encoding == src_encoding ) {
491 // reg-reg copy, use an empty encoding
492 } else {
493 emit_opcode( cbuf, 0x8B );
494 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
495 }
496 }
497
498 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
499 if( dst_encoding == src_encoding ) {
500 // reg-reg copy, use an empty encoding
501 } else {
502 MacroAssembler _masm(&cbuf);
503
504 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
505 }
506 }
507
508
509 //=============================================================================
510 const bool Matcher::constant_table_absolute_addressing = true;
511 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
512
513 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
514 // Empty encoding
515 }
516
517 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
518 return 0;
519 }
520
521 #ifndef PRODUCT
522 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
523 st->print("# MachConstantBaseNode (empty encoding)");
524 }
525 #endif
526
527
528 //=============================================================================
529 #ifndef PRODUCT
530 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
531 Compile* C = ra_->C;
532 if( C->in_24_bit_fp_mode() ) {
533 st->print("FLDCW 24 bit fpu control word");
534 st->print_cr(""); st->print("\t");
535 }
536
537 int framesize = C->frame_slots() << LogBytesPerInt;
538 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
539 // Remove two words for return addr and rbp,
540 framesize -= 2*wordSize;
541
542 // Calls to C2R adapters often do not accept exceptional returns.
543 // We require that their callers must bang for them. But be careful, because
544 // some VM calls (such as call site linkage) can use several kilobytes of
545 // stack. But the stack safety zone should account for that.
546 // See bugs 4446381, 4468289, 4497237.
547 if (C->need_stack_bang(framesize)) {
548 st->print_cr("# stack bang"); st->print("\t");
549 }
550 st->print_cr("PUSHL EBP"); st->print("\t");
551
552 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
553 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
554 st->print_cr(""); st->print("\t");
555 framesize -= wordSize;
556 }
557
558 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
559 if (framesize) {
560 st->print("SUB ESP,%d\t# Create frame",framesize);
561 }
562 } else {
563 st->print("SUB ESP,%d\t# Create frame",framesize);
564 }
565 }
566 #endif
567
568
569 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
570 Compile* C = ra_->C;
571
572 if (UseSSE >= 2 && VerifyFPU) {
573 MacroAssembler masm(&cbuf);
574 masm.verify_FPU(0, "FPU stack must be clean on entry");
575 }
576
577 // WARNING: Initial instruction MUST be 5 bytes or longer so that
578 // NativeJump::patch_verified_entry will be able to patch out the entry
579 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
580 // depth is ok at 5 bytes, the frame allocation can be either 3 or
581 // 6 bytes. So if we don't do the fldcw or the push then we must
582 // use the 6 byte frame allocation even if we have no frame. :-(
583 // If method sets FPU control word do it now
584 if( C->in_24_bit_fp_mode() ) {
585 MacroAssembler masm(&cbuf);
586 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
587 }
588
589 int framesize = C->frame_slots() << LogBytesPerInt;
590 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
591 // Remove two words for return addr and rbp,
592 framesize -= 2*wordSize;
593
594 // Calls to C2R adapters often do not accept exceptional returns.
595 // We require that their callers must bang for them. But be careful, because
596 // some VM calls (such as call site linkage) can use several kilobytes of
597 // stack. But the stack safety zone should account for that.
598 // See bugs 4446381, 4468289, 4497237.
599 if (C->need_stack_bang(framesize)) {
600 MacroAssembler masm(&cbuf);
601 masm.generate_stack_overflow_check(framesize);
602 }
603
604 // We always push rbp, so that on return to interpreter rbp, will be
605 // restored correctly and we can correct the stack.
606 emit_opcode(cbuf, 0x50 | EBP_enc);
607
608 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
609 emit_opcode(cbuf, 0x68); // push 0xbadb100d
610 emit_d32(cbuf, 0xbadb100d);
611 framesize -= wordSize;
612 }
613
614 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
615 if (framesize) {
616 emit_opcode(cbuf, 0x83); // sub SP,#framesize
617 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
618 emit_d8(cbuf, framesize);
619 }
620 } else {
621 emit_opcode(cbuf, 0x81); // sub SP,#framesize
622 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
623 emit_d32(cbuf, framesize);
624 }
625 C->set_frame_complete(cbuf.insts_size());
626
627 #ifdef ASSERT
628 if (VerifyStackAtCalls) {
629 Label L;
630 MacroAssembler masm(&cbuf);
631 masm.push(rax);
632 masm.mov(rax, rsp);
633 masm.andptr(rax, StackAlignmentInBytes-1);
634 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
635 masm.pop(rax);
636 masm.jcc(Assembler::equal, L);
637 masm.stop("Stack is not properly aligned!");
638 masm.bind(L);
639 }
640 #endif
641
642 }
643
644 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
645 return MachNode::size(ra_); // too many variables; just compute it the hard way
646 }
647
648 int MachPrologNode::reloc() const {
649 return 0; // a large enough number
650 }
651
652 //=============================================================================
653 #ifndef PRODUCT
654 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
655 Compile *C = ra_->C;
656 int framesize = C->frame_slots() << LogBytesPerInt;
657 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
658 // Remove two words for return addr and rbp,
659 framesize -= 2*wordSize;
660
661 if( C->in_24_bit_fp_mode() ) {
662 st->print("FLDCW standard control word");
663 st->cr(); st->print("\t");
664 }
665 if( framesize ) {
666 st->print("ADD ESP,%d\t# Destroy frame",framesize);
667 st->cr(); st->print("\t");
668 }
669 st->print_cr("POPL EBP"); st->print("\t");
670 if( do_polling() && C->is_method_compilation() ) {
671 st->print("TEST PollPage,EAX\t! Poll Safepoint");
672 st->cr(); st->print("\t");
673 }
674 }
675 #endif
676
677 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
678 Compile *C = ra_->C;
679
680 // If method set FPU control word, restore to standard control word
681 if( C->in_24_bit_fp_mode() ) {
682 MacroAssembler masm(&cbuf);
683 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
684 }
685
686 int framesize = C->frame_slots() << LogBytesPerInt;
687 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
688 // Remove two words for return addr and rbp,
689 framesize -= 2*wordSize;
690
691 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
692
693 if( framesize >= 128 ) {
694 emit_opcode(cbuf, 0x81); // add SP, #framesize
695 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
696 emit_d32(cbuf, framesize);
697 }
698 else if( framesize ) {
699 emit_opcode(cbuf, 0x83); // add SP, #framesize
700 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
701 emit_d8(cbuf, framesize);
702 }
703
704 emit_opcode(cbuf, 0x58 | EBP_enc);
705
706 if( do_polling() && C->is_method_compilation() ) {
707 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
708 emit_opcode(cbuf,0x85);
709 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
710 emit_d32(cbuf, (intptr_t)os::get_polling_page());
711 }
712 }
713
714 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
715 Compile *C = ra_->C;
716 // If method set FPU control word, restore to standard control word
717 int size = C->in_24_bit_fp_mode() ? 6 : 0;
718 if( do_polling() && C->is_method_compilation() ) size += 6;
719
720 int framesize = C->frame_slots() << LogBytesPerInt;
721 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
722 // Remove two words for return addr and rbp,
723 framesize -= 2*wordSize;
724
725 size++; // popl rbp,
726
727 if( framesize >= 128 ) {
728 size += 6;
729 } else {
730 size += framesize ? 3 : 0;
731 }
732 return size;
733 }
734
735 int MachEpilogNode::reloc() const {
736 return 0; // a large enough number
737 }
738
739 const Pipeline * MachEpilogNode::pipeline() const {
740 return MachNode::pipeline_class();
741 }
742
743 int MachEpilogNode::safepoint_offset() const { return 0; }
744
745 //=============================================================================
746
747 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
748 static enum RC rc_class( OptoReg::Name reg ) {
749
750 if( !OptoReg::is_valid(reg) ) return rc_bad;
751 if (OptoReg::is_stack(reg)) return rc_stack;
752
753 VMReg r = OptoReg::as_VMReg(reg);
754 if (r->is_Register()) return rc_int;
755 if (r->is_FloatRegister()) {
756 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
757 return rc_float;
758 }
759 assert(r->is_XMMRegister(), "must be");
760 return rc_xmm;
761 }
762
763 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
764 int opcode, const char *op_str, int size, outputStream* st ) {
765 if( cbuf ) {
766 emit_opcode (*cbuf, opcode );
767 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
768 #ifndef PRODUCT
769 } else if( !do_size ) {
770 if( size != 0 ) st->print("\n\t");
771 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
772 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
773 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
774 } else { // FLD, FST, PUSH, POP
775 st->print("%s [ESP + #%d]",op_str,offset);
776 }
777 #endif
778 }
779 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
780 return size+3+offset_size;
781 }
782
783 // Helper for XMM registers. Extra opcode bits, limited syntax.
784 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
785 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
786 if( cbuf ) {
787 if( reg_lo+1 == reg_hi ) { // double move?
788 if( is_load && !UseXmmLoadAndClearUpper )
789 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
790 else
791 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
792 } else {
793 emit_opcode(*cbuf, 0xF3 );
794 }
795 emit_opcode(*cbuf, 0x0F );
796 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
797 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
798 else
799 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
800 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
801 #ifndef PRODUCT
802 } else if( !do_size ) {
803 if( size != 0 ) st->print("\n\t");
804 if( reg_lo+1 == reg_hi ) { // double move?
805 if( is_load ) st->print("%s %s,[ESP + #%d]",
806 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
807 Matcher::regName[reg_lo], offset);
808 else st->print("MOVSD [ESP + #%d],%s",
809 offset, Matcher::regName[reg_lo]);
810 } else {
811 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
812 Matcher::regName[reg_lo], offset);
813 else st->print("MOVSS [ESP + #%d],%s",
814 offset, Matcher::regName[reg_lo]);
815 }
816 #endif
817 }
818 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
819 return size+5+offset_size;
820 }
821
822
823 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
824 int src_hi, int dst_hi, int size, outputStream* st ) {
825 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
826 if( cbuf ) {
827 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
828 emit_opcode(*cbuf, 0x66 );
829 }
830 emit_opcode(*cbuf, 0x0F );
831 emit_opcode(*cbuf, 0x28 );
832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
833 #ifndef PRODUCT
834 } else if( !do_size ) {
835 if( size != 0 ) st->print("\n\t");
836 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
837 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
838 } else {
839 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
840 }
841 #endif
842 }
843 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
844 } else {
845 if( cbuf ) {
846 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
847 emit_opcode(*cbuf, 0x0F );
848 emit_opcode(*cbuf, 0x10 );
849 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
850 #ifndef PRODUCT
851 } else if( !do_size ) {
852 if( size != 0 ) st->print("\n\t");
853 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
854 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
855 } else {
856 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
857 }
858 #endif
859 }
860 return size+4;
861 }
862 }
863
864 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
865 int src_hi, int dst_hi, int size, outputStream* st ) {
866 // 32-bit
867 if (cbuf) {
868 emit_opcode(*cbuf, 0x66);
869 emit_opcode(*cbuf, 0x0F);
870 emit_opcode(*cbuf, 0x6E);
871 emit_rm(*cbuf, 0x3, Matcher::_regEncode[dst_lo] & 7, Matcher::_regEncode[src_lo] & 7);
872 #ifndef PRODUCT
873 } else if (!do_size) {
874 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
875 #endif
876 }
877 return 4;
878 }
879
880
881 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
882 int src_hi, int dst_hi, int size, outputStream* st ) {
883 // 32-bit
884 if (cbuf) {
885 emit_opcode(*cbuf, 0x66);
886 emit_opcode(*cbuf, 0x0F);
887 emit_opcode(*cbuf, 0x7E);
888 emit_rm(*cbuf, 0x3, Matcher::_regEncode[src_lo] & 7, Matcher::_regEncode[dst_lo] & 7);
889 #ifndef PRODUCT
890 } else if (!do_size) {
891 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
892 #endif
893 }
894 return 4;
895 }
896
897 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
898 if( cbuf ) {
899 emit_opcode(*cbuf, 0x8B );
900 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
901 #ifndef PRODUCT
902 } else if( !do_size ) {
903 if( size != 0 ) st->print("\n\t");
904 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
905 #endif
906 }
907 return size+2;
908 }
909
910 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
911 int offset, int size, outputStream* st ) {
912 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
913 if( cbuf ) {
914 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
915 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
916 #ifndef PRODUCT
917 } else if( !do_size ) {
918 if( size != 0 ) st->print("\n\t");
919 st->print("FLD %s",Matcher::regName[src_lo]);
920 #endif
921 }
922 size += 2;
923 }
924
925 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
926 const char *op_str;
927 int op;
928 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
929 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
930 op = 0xDD;
931 } else { // 32-bit store
932 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
933 op = 0xD9;
934 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
935 }
936
937 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
938 }
939
940 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
941 // Get registers to move
942 OptoReg::Name src_second = ra_->get_reg_second(in(1));
943 OptoReg::Name src_first = ra_->get_reg_first(in(1));
944 OptoReg::Name dst_second = ra_->get_reg_second(this );
945 OptoReg::Name dst_first = ra_->get_reg_first(this );
946
947 enum RC src_second_rc = rc_class(src_second);
948 enum RC src_first_rc = rc_class(src_first);
949 enum RC dst_second_rc = rc_class(dst_second);
950 enum RC dst_first_rc = rc_class(dst_first);
951
952 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
953
954 // Generate spill code!
955 int size = 0;
956
957 if( src_first == dst_first && src_second == dst_second )
958 return size; // Self copy, no move
959
960 // --------------------------------------
961 // Check for mem-mem move. push/pop to move.
962 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
963 if( src_second == dst_first ) { // overlapping stack copy ranges
964 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
965 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
966 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
967 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
968 }
969 // move low bits
970 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
971 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
972 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
973 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
974 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
975 }
976 return size;
977 }
978
979 // --------------------------------------
980 // Check for integer reg-reg copy
981 if( src_first_rc == rc_int && dst_first_rc == rc_int )
982 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
983
984 // Check for integer store
985 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
986 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
987
988 // Check for integer load
989 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
990 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
991
992 // Check for integer reg-xmm reg copy
993 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
994 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
995 "no 64 bit integer-float reg moves" );
996 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
997 }
998 // --------------------------------------
999 // Check for float reg-reg copy
1000 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1001 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1002 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1003 if( cbuf ) {
1004
1005 // Note the mucking with the register encode to compensate for the 0/1
1006 // indexing issue mentioned in a comment in the reg_def sections
1007 // for FPR registers many lines above here.
1008
1009 if( src_first != FPR1L_num ) {
1010 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1011 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1012 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1013 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1014 } else {
1015 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1016 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1017 }
1018 #ifndef PRODUCT
1019 } else if( !do_size ) {
1020 if( size != 0 ) st->print("\n\t");
1021 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1022 else st->print( "FST %s", Matcher::regName[dst_first]);
1023 #endif
1024 }
1025 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1026 }
1027
1028 // Check for float store
1029 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1030 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1031 }
1032
1033 // Check for float load
1034 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1035 int offset = ra_->reg2offset(src_first);
1036 const char *op_str;
1037 int op;
1038 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1039 op_str = "FLD_D";
1040 op = 0xDD;
1041 } else { // 32-bit load
1042 op_str = "FLD_S";
1043 op = 0xD9;
1044 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1045 }
1046 if( cbuf ) {
1047 emit_opcode (*cbuf, op );
1048 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1049 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1050 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1051 #ifndef PRODUCT
1052 } else if( !do_size ) {
1053 if( size != 0 ) st->print("\n\t");
1054 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1055 #endif
1056 }
1057 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1058 return size + 3+offset_size+2;
1059 }
1060
1061 // Check for xmm reg-reg copy
1062 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1063 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1064 (src_first+1 == src_second && dst_first+1 == dst_second),
1065 "no non-adjacent float-moves" );
1066 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1067 }
1068
1069 // Check for xmm reg-integer reg copy
1070 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1071 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1072 "no 64 bit float-integer reg moves" );
1073 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1074 }
1075
1076 // Check for xmm store
1077 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1078 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1079 }
1080
1081 // Check for float xmm load
1082 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1083 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1084 }
1085
1086 // Copy from float reg to xmm reg
1087 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1088 // copy to the top of stack from floating point reg
1089 // and use LEA to preserve flags
1090 if( cbuf ) {
1091 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1092 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1093 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1094 emit_d8(*cbuf,0xF8);
1095 #ifndef PRODUCT
1096 } else if( !do_size ) {
1097 if( size != 0 ) st->print("\n\t");
1098 st->print("LEA ESP,[ESP-8]");
1099 #endif
1100 }
1101 size += 4;
1102
1103 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1104
1105 // Copy from the temp memory to the xmm reg.
1106 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1107
1108 if( cbuf ) {
1109 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1110 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1111 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1112 emit_d8(*cbuf,0x08);
1113 #ifndef PRODUCT
1114 } else if( !do_size ) {
1115 if( size != 0 ) st->print("\n\t");
1116 st->print("LEA ESP,[ESP+8]");
1117 #endif
1118 }
1119 size += 4;
1120 return size;
1121 }
1122
1123 assert( size > 0, "missed a case" );
1124
1125 // --------------------------------------------------------------------
1126 // Check for second bits still needing moving.
1127 if( src_second == dst_second )
1128 return size; // Self copy; no move
1129 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1130
1131 // Check for second word int-int move
1132 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1133 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1134
1135 // Check for second word integer store
1136 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1137 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1138
1139 // Check for second word integer load
1140 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1141 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1142
1143
1144 Unimplemented();
1145 }
1146
1147 #ifndef PRODUCT
1148 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1149 implementation( NULL, ra_, false, st );
1150 }
1151 #endif
1152
1153 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1154 implementation( &cbuf, ra_, false, NULL );
1155 }
1156
1157 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1158 return implementation( NULL, ra_, true, NULL );
1159 }
1160
1161 //=============================================================================
1162 #ifndef PRODUCT
1163 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1164 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1165 }
1166 #endif
1167
1168 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1169 MacroAssembler _masm(&cbuf);
1170 __ nop(_count);
1171 }
1172
1173 uint MachNopNode::size(PhaseRegAlloc *) const {
1174 return _count;
1175 }
1176
1177
1178 //=============================================================================
1179 #ifndef PRODUCT
1180 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1181 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1182 int reg = ra_->get_reg_first(this);
1183 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1184 }
1185 #endif
1186
1187 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1188 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1189 int reg = ra_->get_encode(this);
1190 if( offset >= 128 ) {
1191 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1192 emit_rm(cbuf, 0x2, reg, 0x04);
1193 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1194 emit_d32(cbuf, offset);
1195 }
1196 else {
1197 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1198 emit_rm(cbuf, 0x1, reg, 0x04);
1199 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1200 emit_d8(cbuf, offset);
1201 }
1202 }
1203
1204 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1205 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1206 if( offset >= 128 ) {
1207 return 7;
1208 }
1209 else {
1210 return 4;
1211 }
1212 }
1213
1214 //=============================================================================
1215
1216 // emit call stub, compiled java to interpreter
1217 void emit_java_to_interp(CodeBuffer &cbuf ) {
1218 // Stub is fixed up when the corresponding call is converted from calling
1219 // compiled code to calling interpreted code.
1220 // mov rbx,0
1221 // jmp -1
1222
1223 address mark = cbuf.insts_mark(); // get mark within main instrs section
1224
1225 // Note that the code buffer's insts_mark is always relative to insts.
1226 // That's why we must use the macroassembler to generate a stub.
1227 MacroAssembler _masm(&cbuf);
1228
1229 address base =
1230 __ start_a_stub(Compile::MAX_stubs_size);
1231 if (base == NULL) return; // CodeBuffer::expand failed
1232 // static stub relocation stores the instruction address of the call
1233 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1234 // static stub relocation also tags the methodOop in the code-stream.
1235 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1236 // This is recognized as unresolved by relocs/nativeInst/ic code
1237 __ jump(RuntimeAddress(__ pc()));
1238
1239 __ end_a_stub();
1240 // Update current stubs pointer and restore insts_end.
1241 }
1242 // size of call stub, compiled java to interpretor
1243 uint size_java_to_interp() {
1244 return 10; // movl; jmp
1245 }
1246 // relocation entries for call stub, compiled java to interpretor
1247 uint reloc_java_to_interp() {
1248 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1249 }
1250
1251 //=============================================================================
1252 #ifndef PRODUCT
1253 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1254 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1255 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1256 st->print_cr("\tNOP");
1257 st->print_cr("\tNOP");
1258 if( !OptoBreakpoint )
1259 st->print_cr("\tNOP");
1260 }
1261 #endif
1262
1263 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1264 MacroAssembler masm(&cbuf);
1265 #ifdef ASSERT
1266 uint insts_size = cbuf.insts_size();
1267 #endif
1268 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1269 masm.jump_cc(Assembler::notEqual,
1270 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1271 /* WARNING these NOPs are critical so that verified entry point is properly
1272 aligned for patching by NativeJump::patch_verified_entry() */
1273 int nops_cnt = 2;
1274 if( !OptoBreakpoint ) // Leave space for int3
1275 nops_cnt += 1;
1276 masm.nop(nops_cnt);
1277
1278 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1279 }
1280
1281 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1282 return OptoBreakpoint ? 11 : 12;
1283 }
1284
1285
1286 //=============================================================================
1287 uint size_exception_handler() {
1288 // NativeCall instruction size is the same as NativeJump.
1289 // exception handler starts out as jump and can be patched to
1290 // a call be deoptimization. (4932387)
1291 // Note that this value is also credited (in output.cpp) to
1292 // the size of the code section.
1293 return NativeJump::instruction_size;
1294 }
1295
1296 // Emit exception handler code. Stuff framesize into a register
1297 // and call a VM stub routine.
1298 int emit_exception_handler(CodeBuffer& cbuf) {
1299
1300 // Note that the code buffer's insts_mark is always relative to insts.
1301 // That's why we must use the macroassembler to generate a handler.
1302 MacroAssembler _masm(&cbuf);
1303 address base =
1304 __ start_a_stub(size_exception_handler());
1305 if (base == NULL) return 0; // CodeBuffer::expand failed
1306 int offset = __ offset();
1307 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1308 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1309 __ end_a_stub();
1310 return offset;
1311 }
1312
1313 uint size_deopt_handler() {
1314 // NativeCall instruction size is the same as NativeJump.
1315 // exception handler starts out as jump and can be patched to
1316 // a call be deoptimization. (4932387)
1317 // Note that this value is also credited (in output.cpp) to
1318 // the size of the code section.
1319 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1320 }
1321
1322 // Emit deopt handler code.
1323 int emit_deopt_handler(CodeBuffer& cbuf) {
1324
1325 // Note that the code buffer's insts_mark is always relative to insts.
1326 // That's why we must use the macroassembler to generate a handler.
1327 MacroAssembler _masm(&cbuf);
1328 address base =
1329 __ start_a_stub(size_exception_handler());
1330 if (base == NULL) return 0; // CodeBuffer::expand failed
1331 int offset = __ offset();
1332 InternalAddress here(__ pc());
1333 __ pushptr(here.addr());
1334
1335 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1336 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1337 __ end_a_stub();
1338 return offset;
1339 }
1340
1341
1342 const bool Matcher::match_rule_supported(int opcode) {
1343 if (!has_match_rule(opcode))
1344 return false;
1345
1346 return true; // Per default match rules are supported.
1347 }
1348
1349 int Matcher::regnum_to_fpu_offset(int regnum) {
1350 return regnum - 32; // The FP registers are in the second chunk
1351 }
1352
1353 // This is UltraSparc specific, true just means we have fast l2f conversion
1354 const bool Matcher::convL2FSupported(void) {
1355 return true;
1356 }
1357
1358 // Vector width in bytes
1359 const uint Matcher::vector_width_in_bytes(void) {
1360 return UseSSE >= 2 ? 8 : 0;
1361 }
1362
1363 // Vector ideal reg
1364 const uint Matcher::vector_ideal_reg(void) {
1365 return Op_RegD;
1366 }
1367
1368 // Is this branch offset short enough that a short branch can be used?
1369 //
1370 // NOTE: If the platform does not provide any short branch variants, then
1371 // this method should return false for offset 0.
1372 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1373 // The passed offset is relative to address of the branch.
1374 // On 86 a branch displacement is calculated relative to address
1375 // of a next instruction.
1376 offset -= br_size;
1377
1378 // the short version of jmpConUCF2 contains multiple branches,
1379 // making the reach slightly less
1380 if (rule == jmpConUCF2_rule)
1381 return (-126 <= offset && offset <= 125);
1382 return (-128 <= offset && offset <= 127);
1383 }
1384
1385 const bool Matcher::isSimpleConstant64(jlong value) {
1386 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1387 return false;
1388 }
1389
1390 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1391 const bool Matcher::init_array_count_is_in_bytes = false;
1392
1393 // Threshold size for cleararray.
1394 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1395
1396 // Should the Matcher clone shifts on addressing modes, expecting them to
1397 // be subsumed into complex addressing expressions or compute them into
1398 // registers? True for Intel but false for most RISCs
1399 const bool Matcher::clone_shift_expressions = true;
1400
1401 // Do we need to mask the count passed to shift instructions or does
1402 // the cpu only look at the lower 5/6 bits anyway?
1403 const bool Matcher::need_masked_shift_count = false;
1404
1405 bool Matcher::narrow_oop_use_complex_address() {
1406 ShouldNotCallThis();
1407 return true;
1408 }
1409
1410
1411 // Is it better to copy float constants, or load them directly from memory?
1412 // Intel can load a float constant from a direct address, requiring no
1413 // extra registers. Most RISCs will have to materialize an address into a
1414 // register first, so they would do better to copy the constant from stack.
1415 const bool Matcher::rematerialize_float_constants = true;
1416
1417 // If CPU can load and store mis-aligned doubles directly then no fixup is
1418 // needed. Else we split the double into 2 integer pieces and move it
1419 // piece-by-piece. Only happens when passing doubles into C code as the
1420 // Java calling convention forces doubles to be aligned.
1421 const bool Matcher::misaligned_doubles_ok = true;
1422
1423
1424 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1425 // Get the memory operand from the node
1426 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1427 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1428 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1429 uint opcnt = 1; // First operand
1430 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1431 while( idx >= skipped+num_edges ) {
1432 skipped += num_edges;
1433 opcnt++; // Bump operand count
1434 assert( opcnt < numopnds, "Accessing non-existent operand" );
1435 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1436 }
1437
1438 MachOper *memory = node->_opnds[opcnt];
1439 MachOper *new_memory = NULL;
1440 switch (memory->opcode()) {
1441 case DIRECT:
1442 case INDOFFSET32X:
1443 // No transformation necessary.
1444 return;
1445 case INDIRECT:
1446 new_memory = new (C) indirect_win95_safeOper( );
1447 break;
1448 case INDOFFSET8:
1449 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1450 break;
1451 case INDOFFSET32:
1452 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1453 break;
1454 case INDINDEXOFFSET:
1455 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1456 break;
1457 case INDINDEXSCALE:
1458 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1459 break;
1460 case INDINDEXSCALEOFFSET:
1461 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1462 break;
1463 case LOAD_LONG_INDIRECT:
1464 case LOAD_LONG_INDOFFSET32:
1465 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1466 return;
1467 default:
1468 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1469 return;
1470 }
1471 node->_opnds[opcnt] = new_memory;
1472 }
1473
1474 // Advertise here if the CPU requires explicit rounding operations
1475 // to implement the UseStrictFP mode.
1476 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1477
1478 // Are floats conerted to double when stored to stack during deoptimization?
1479 // On x32 it is stored with convertion only when FPU is used for floats.
1480 bool Matcher::float_in_double() { return (UseSSE == 0); }
1481
1482 // Do ints take an entire long register or just half?
1483 const bool Matcher::int_in_long = false;
1484
1485 // Return whether or not this register is ever used as an argument. This
1486 // function is used on startup to build the trampoline stubs in generateOptoStub.
1487 // Registers not mentioned will be killed by the VM call in the trampoline, and
1488 // arguments in those registers not be available to the callee.
1489 bool Matcher::can_be_java_arg( int reg ) {
1490 if( reg == ECX_num || reg == EDX_num ) return true;
1491 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1492 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1493 return false;
1494 }
1495
1496 bool Matcher::is_spillable_arg( int reg ) {
1497 return can_be_java_arg(reg);
1498 }
1499
1500 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1501 // Use hardware integer DIV instruction when
1502 // it is faster than a code which use multiply.
1503 // Only when constant divisor fits into 32 bit
1504 // (min_jint is excluded to get only correct
1505 // positive 32 bit values from negative).
1506 return VM_Version::has_fast_idiv() &&
1507 (divisor == (int)divisor && divisor != min_jint);
1508 }
1509
1510 // Register for DIVI projection of divmodI
1511 RegMask Matcher::divI_proj_mask() {
1512 return EAX_REG_mask;
1513 }
1514
1515 // Register for MODI projection of divmodI
1516 RegMask Matcher::modI_proj_mask() {
1517 return EDX_REG_mask;
1518 }
1519
1520 // Register for DIVL projection of divmodL
1521 RegMask Matcher::divL_proj_mask() {
1522 ShouldNotReachHere();
1523 return RegMask();
1524 }
1525
1526 // Register for MODL projection of divmodL
1527 RegMask Matcher::modL_proj_mask() {
1528 ShouldNotReachHere();
1529 return RegMask();
1530 }
1531
1532 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1533 return EBP_REG_mask;
1534 }
1535
1536 // Returns true if the high 32 bits of the value is known to be zero.
1537 bool is_operand_hi32_zero(Node* n) {
1538 int opc = n->Opcode();
1539 if (opc == Op_LoadUI2L) {
1540 return true;
1541 }
1542 if (opc == Op_AndL) {
1543 Node* o2 = n->in(2);
1544 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1545 return true;
1546 }
1547 }
1548 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1549 return true;
1550 }
1551 return false;
1552 }
1553
1554 %}
1555
1556 //----------ENCODING BLOCK-----------------------------------------------------
1557 // This block specifies the encoding classes used by the compiler to output
1558 // byte streams. Encoding classes generate functions which are called by
1559 // Machine Instruction Nodes in order to generate the bit encoding of the
1560 // instruction. Operands specify their base encoding interface with the
1561 // interface keyword. There are currently supported four interfaces,
1562 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1563 // operand to generate a function which returns its register number when
1564 // queried. CONST_INTER causes an operand to generate a function which
1565 // returns the value of the constant when queried. MEMORY_INTER causes an
1566 // operand to generate four functions which return the Base Register, the
1567 // Index Register, the Scale Value, and the Offset Value of the operand when
1568 // queried. COND_INTER causes an operand to generate six functions which
1569 // return the encoding code (ie - encoding bits for the instruction)
1570 // associated with each basic boolean condition for a conditional instruction.
1571 // Instructions specify two basic values for encoding. They use the
1572 // ins_encode keyword to specify their encoding class (which must be one of
1573 // the class names specified in the encoding block), and they use the
1574 // opcode keyword to specify, in order, their primary, secondary, and
1575 // tertiary opcode. Only the opcode sections which a particular instruction
1576 // needs for encoding need to be specified.
1577 encode %{
1578 // Build emit functions for each basic byte or larger field in the intel
1579 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1580 // code in the enc_class source block. Emit functions will live in the
1581 // main source block for now. In future, we can generalize this by
1582 // adding a syntax that specifies the sizes of fields in an order,
1583 // so that the adlc can build the emit functions automagically
1584
1585 // Emit primary opcode
1586 enc_class OpcP %{
1587 emit_opcode(cbuf, $primary);
1588 %}
1589
1590 // Emit secondary opcode
1591 enc_class OpcS %{
1592 emit_opcode(cbuf, $secondary);
1593 %}
1594
1595 // Emit opcode directly
1596 enc_class Opcode(immI d8) %{
1597 emit_opcode(cbuf, $d8$$constant);
1598 %}
1599
1600 enc_class SizePrefix %{
1601 emit_opcode(cbuf,0x66);
1602 %}
1603
1604 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1605 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1606 %}
1607
1608 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1609 emit_opcode(cbuf,$opcode$$constant);
1610 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1611 %}
1612
1613 enc_class mov_r32_imm0( eRegI dst ) %{
1614 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1615 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1616 %}
1617
1618 enc_class cdq_enc %{
1619 // Full implementation of Java idiv and irem; checks for
1620 // special case as described in JVM spec., p.243 & p.271.
1621 //
1622 // normal case special case
1623 //
1624 // input : rax,: dividend min_int
1625 // reg: divisor -1
1626 //
1627 // output: rax,: quotient (= rax, idiv reg) min_int
1628 // rdx: remainder (= rax, irem reg) 0
1629 //
1630 // Code sequnce:
1631 //
1632 // 81 F8 00 00 00 80 cmp rax,80000000h
1633 // 0F 85 0B 00 00 00 jne normal_case
1634 // 33 D2 xor rdx,edx
1635 // 83 F9 FF cmp rcx,0FFh
1636 // 0F 84 03 00 00 00 je done
1637 // normal_case:
1638 // 99 cdq
1639 // F7 F9 idiv rax,ecx
1640 // done:
1641 //
1642 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1643 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1644 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1645 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1646 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1647 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1648 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1649 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1650 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1651 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1652 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1653 // normal_case:
1654 emit_opcode(cbuf,0x99); // cdq
1655 // idiv (note: must be emitted by the user of this rule)
1656 // normal:
1657 %}
1658
1659 // Dense encoding for older common ops
1660 enc_class Opc_plus(immI opcode, eRegI reg) %{
1661 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1662 %}
1663
1664
1665 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1666 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1667 // Check for 8-bit immediate, and set sign extend bit in opcode
1668 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1669 emit_opcode(cbuf, $primary | 0x02);
1670 }
1671 else { // If 32-bit immediate
1672 emit_opcode(cbuf, $primary);
1673 }
1674 %}
1675
1676 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1677 // Emit primary opcode and set sign-extend bit
1678 // Check for 8-bit immediate, and set sign extend bit in opcode
1679 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1680 emit_opcode(cbuf, $primary | 0x02); }
1681 else { // If 32-bit immediate
1682 emit_opcode(cbuf, $primary);
1683 }
1684 // Emit r/m byte with secondary opcode, after primary opcode.
1685 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1686 %}
1687
1688 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1689 // Check for 8-bit immediate, and set sign extend bit in opcode
1690 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1691 $$$emit8$imm$$constant;
1692 }
1693 else { // If 32-bit immediate
1694 // Output immediate
1695 $$$emit32$imm$$constant;
1696 }
1697 %}
1698
1699 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1700 // Emit primary opcode and set sign-extend bit
1701 // Check for 8-bit immediate, and set sign extend bit in opcode
1702 int con = (int)$imm$$constant; // Throw away top bits
1703 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1704 // Emit r/m byte with secondary opcode, after primary opcode.
1705 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1706 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1707 else emit_d32(cbuf,con);
1708 %}
1709
1710 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1711 // Emit primary opcode and set sign-extend bit
1712 // Check for 8-bit immediate, and set sign extend bit in opcode
1713 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1714 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1715 // Emit r/m byte with tertiary opcode, after primary opcode.
1716 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1717 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1718 else emit_d32(cbuf,con);
1719 %}
1720
1721 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1722 emit_cc(cbuf, $secondary, $dst$$reg );
1723 %}
1724
1725 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1726 int destlo = $dst$$reg;
1727 int desthi = HIGH_FROM_LOW(destlo);
1728 // bswap lo
1729 emit_opcode(cbuf, 0x0F);
1730 emit_cc(cbuf, 0xC8, destlo);
1731 // bswap hi
1732 emit_opcode(cbuf, 0x0F);
1733 emit_cc(cbuf, 0xC8, desthi);
1734 // xchg lo and hi
1735 emit_opcode(cbuf, 0x87);
1736 emit_rm(cbuf, 0x3, destlo, desthi);
1737 %}
1738
1739 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1740 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1741 %}
1742
1743 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1744 $$$emit8$primary;
1745 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1746 %}
1747
1748 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1749 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1750 emit_d8(cbuf, op >> 8 );
1751 emit_d8(cbuf, op & 255);
1752 %}
1753
1754 // emulate a CMOV with a conditional branch around a MOV
1755 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1756 // Invert sense of branch from sense of CMOV
1757 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1758 emit_d8( cbuf, $brOffs$$constant );
1759 %}
1760
1761 enc_class enc_PartialSubtypeCheck( ) %{
1762 Register Redi = as_Register(EDI_enc); // result register
1763 Register Reax = as_Register(EAX_enc); // super class
1764 Register Recx = as_Register(ECX_enc); // killed
1765 Register Resi = as_Register(ESI_enc); // sub class
1766 Label miss;
1767
1768 MacroAssembler _masm(&cbuf);
1769 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1770 NULL, &miss,
1771 /*set_cond_codes:*/ true);
1772 if ($primary) {
1773 __ xorptr(Redi, Redi);
1774 }
1775 __ bind(miss);
1776 %}
1777
1778 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1779 MacroAssembler masm(&cbuf);
1780 int start = masm.offset();
1781 if (UseSSE >= 2) {
1782 if (VerifyFPU) {
1783 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1784 }
1785 } else {
1786 // External c_calling_convention expects the FPU stack to be 'clean'.
1787 // Compiled code leaves it dirty. Do cleanup now.
1788 masm.empty_FPU_stack();
1789 }
1790 if (sizeof_FFree_Float_Stack_All == -1) {
1791 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1792 } else {
1793 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1794 }
1795 %}
1796
1797 enc_class Verify_FPU_For_Leaf %{
1798 if( VerifyFPU ) {
1799 MacroAssembler masm(&cbuf);
1800 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1801 }
1802 %}
1803
1804 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1805 // This is the instruction starting address for relocation info.
1806 cbuf.set_insts_mark();
1807 $$$emit8$primary;
1808 // CALL directly to the runtime
1809 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1810 runtime_call_Relocation::spec(), RELOC_IMM32 );
1811
1812 if (UseSSE >= 2) {
1813 MacroAssembler _masm(&cbuf);
1814 BasicType rt = tf()->return_type();
1815
1816 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1817 // A C runtime call where the return value is unused. In SSE2+
1818 // mode the result needs to be removed from the FPU stack. It's
1819 // likely that this function call could be removed by the
1820 // optimizer if the C function is a pure function.
1821 __ ffree(0);
1822 } else if (rt == T_FLOAT) {
1823 __ lea(rsp, Address(rsp, -4));
1824 __ fstp_s(Address(rsp, 0));
1825 __ movflt(xmm0, Address(rsp, 0));
1826 __ lea(rsp, Address(rsp, 4));
1827 } else if (rt == T_DOUBLE) {
1828 __ lea(rsp, Address(rsp, -8));
1829 __ fstp_d(Address(rsp, 0));
1830 __ movdbl(xmm0, Address(rsp, 0));
1831 __ lea(rsp, Address(rsp, 8));
1832 }
1833 }
1834 %}
1835
1836
1837 enc_class pre_call_FPU %{
1838 // If method sets FPU control word restore it here
1839 debug_only(int off0 = cbuf.insts_size());
1840 if( Compile::current()->in_24_bit_fp_mode() ) {
1841 MacroAssembler masm(&cbuf);
1842 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1843 }
1844 debug_only(int off1 = cbuf.insts_size());
1845 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1846 %}
1847
1848 enc_class post_call_FPU %{
1849 // If method sets FPU control word do it here also
1850 if( Compile::current()->in_24_bit_fp_mode() ) {
1851 MacroAssembler masm(&cbuf);
1852 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1853 }
1854 %}
1855
1856 enc_class preserve_SP %{
1857 debug_only(int off0 = cbuf.insts_size());
1858 MacroAssembler _masm(&cbuf);
1859 // RBP is preserved across all calls, even compiled calls.
1860 // Use it to preserve RSP in places where the callee might change the SP.
1861 __ movptr(rbp_mh_SP_save, rsp);
1862 debug_only(int off1 = cbuf.insts_size());
1863 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
1864 %}
1865
1866 enc_class restore_SP %{
1867 MacroAssembler _masm(&cbuf);
1868 __ movptr(rsp, rbp_mh_SP_save);
1869 %}
1870
1871 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1872 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1873 // who we intended to call.
1874 cbuf.set_insts_mark();
1875 $$$emit8$primary;
1876 if ( !_method ) {
1877 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1878 runtime_call_Relocation::spec(), RELOC_IMM32 );
1879 } else if(_optimized_virtual) {
1880 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1881 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1882 } else {
1883 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1884 static_call_Relocation::spec(), RELOC_IMM32 );
1885 }
1886 if( _method ) { // Emit stub for static call
1887 emit_java_to_interp(cbuf);
1888 }
1889 %}
1890
1891 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1892 // !!!!!
1893 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1894 // emit_call_dynamic_prologue( cbuf );
1895 cbuf.set_insts_mark();
1896 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1897 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1898 address virtual_call_oop_addr = cbuf.insts_mark();
1899 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1900 // who we intended to call.
1901 cbuf.set_insts_mark();
1902 $$$emit8$primary;
1903 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1904 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1905 %}
1906
1907 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1908 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1909 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1910
1911 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1912 cbuf.set_insts_mark();
1913 $$$emit8$primary;
1914 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1915 emit_d8(cbuf, disp); // Displacement
1916
1917 %}
1918
1919 enc_class Xor_Reg (eRegI dst) %{
1920 emit_opcode(cbuf, 0x33);
1921 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1922 %}
1923
1924 // Following encoding is no longer used, but may be restored if calling
1925 // convention changes significantly.
1926 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1927 //
1928 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1929 // // int ic_reg = Matcher::inline_cache_reg();
1930 // // int ic_encode = Matcher::_regEncode[ic_reg];
1931 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1932 // // int imo_encode = Matcher::_regEncode[imo_reg];
1933 //
1934 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1935 // // // so we load it immediately before the call
1936 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1937 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1938 //
1939 // // xor rbp,ebp
1940 // emit_opcode(cbuf, 0x33);
1941 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1942 //
1943 // // CALL to interpreter.
1944 // cbuf.set_insts_mark();
1945 // $$$emit8$primary;
1946 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1947 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1948 // %}
1949
1950 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1951 $$$emit8$primary;
1952 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1953 $$$emit8$shift$$constant;
1954 %}
1955
1956 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1957 // Load immediate does not have a zero or sign extended version
1958 // for 8-bit immediates
1959 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1960 $$$emit32$src$$constant;
1961 %}
1962
1963 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1964 // Load immediate does not have a zero or sign extended version
1965 // for 8-bit immediates
1966 emit_opcode(cbuf, $primary + $dst$$reg);
1967 $$$emit32$src$$constant;
1968 %}
1969
1970 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1971 // Load immediate does not have a zero or sign extended version
1972 // for 8-bit immediates
1973 int dst_enc = $dst$$reg;
1974 int src_con = $src$$constant & 0x0FFFFFFFFL;
1975 if (src_con == 0) {
1976 // xor dst, dst
1977 emit_opcode(cbuf, 0x33);
1978 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1979 } else {
1980 emit_opcode(cbuf, $primary + dst_enc);
1981 emit_d32(cbuf, src_con);
1982 }
1983 %}
1984
1985 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1986 // Load immediate does not have a zero or sign extended version
1987 // for 8-bit immediates
1988 int dst_enc = $dst$$reg + 2;
1989 int src_con = ((julong)($src$$constant)) >> 32;
1990 if (src_con == 0) {
1991 // xor dst, dst
1992 emit_opcode(cbuf, 0x33);
1993 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1994 } else {
1995 emit_opcode(cbuf, $primary + dst_enc);
1996 emit_d32(cbuf, src_con);
1997 }
1998 %}
1999
2000
2001 enc_class MovI2X_reg(regX dst, eRegI src) %{
2002 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2003 emit_opcode(cbuf, 0x0F );
2004 emit_opcode(cbuf, 0x6E );
2005 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2006 %}
2007
2008 enc_class MovX2I_reg(eRegI dst, regX src) %{
2009 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2010 emit_opcode(cbuf, 0x0F );
2011 emit_opcode(cbuf, 0x7E );
2012 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2013 %}
2014
2015 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
2016 { // MOVD $dst,$src.lo
2017 emit_opcode(cbuf,0x66);
2018 emit_opcode(cbuf,0x0F);
2019 emit_opcode(cbuf,0x6E);
2020 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2021 }
2022 { // MOVD $tmp,$src.hi
2023 emit_opcode(cbuf,0x66);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x6E);
2026 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2027 }
2028 { // PUNPCKLDQ $dst,$tmp
2029 emit_opcode(cbuf,0x66);
2030 emit_opcode(cbuf,0x0F);
2031 emit_opcode(cbuf,0x62);
2032 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2033 }
2034 %}
2035
2036 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2037 { // MOVD $dst.lo,$src
2038 emit_opcode(cbuf,0x66);
2039 emit_opcode(cbuf,0x0F);
2040 emit_opcode(cbuf,0x7E);
2041 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2042 }
2043 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2044 emit_opcode(cbuf,0xF2);
2045 emit_opcode(cbuf,0x0F);
2046 emit_opcode(cbuf,0x70);
2047 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2048 emit_d8(cbuf, 0x4E);
2049 }
2050 { // MOVD $dst.hi,$tmp
2051 emit_opcode(cbuf,0x66);
2052 emit_opcode(cbuf,0x0F);
2053 emit_opcode(cbuf,0x7E);
2054 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2055 }
2056 %}
2057
2058
2059 // Encode a reg-reg copy. If it is useless, then empty encoding.
2060 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2061 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2062 %}
2063
2064 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2065 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2066 %}
2067
2068 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2069 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2070 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2071 %}
2072
2073 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2074 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2075 %}
2076
2077 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2078 $$$emit8$primary;
2079 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2080 %}
2081
2082 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2083 $$$emit8$secondary;
2084 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2085 %}
2086
2087 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2088 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2089 %}
2090
2091 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2092 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2093 %}
2094
2095 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2096 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2097 %}
2098
2099 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2100 // Output immediate
2101 $$$emit32$src$$constant;
2102 %}
2103
2104 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2105 // Output Float immediate bits
2106 jfloat jf = $src$$constant;
2107 int jf_as_bits = jint_cast( jf );
2108 emit_d32(cbuf, jf_as_bits);
2109 %}
2110
2111 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2112 // Output Float immediate bits
2113 jfloat jf = $src$$constant;
2114 int jf_as_bits = jint_cast( jf );
2115 emit_d32(cbuf, jf_as_bits);
2116 %}
2117
2118 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2119 // Output immediate
2120 $$$emit16$src$$constant;
2121 %}
2122
2123 enc_class Con_d32(immI src) %{
2124 emit_d32(cbuf,$src$$constant);
2125 %}
2126
2127 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2128 // Output immediate memory reference
2129 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2130 emit_d32(cbuf, 0x00);
2131 %}
2132
2133 enc_class lock_prefix( ) %{
2134 if( os::is_MP() )
2135 emit_opcode(cbuf,0xF0); // [Lock]
2136 %}
2137
2138 // Cmp-xchg long value.
2139 // Note: we need to swap rbx, and rcx before and after the
2140 // cmpxchg8 instruction because the instruction uses
2141 // rcx as the high order word of the new value to store but
2142 // our register encoding uses rbx,.
2143 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2144
2145 // XCHG rbx,ecx
2146 emit_opcode(cbuf,0x87);
2147 emit_opcode(cbuf,0xD9);
2148 // [Lock]
2149 if( os::is_MP() )
2150 emit_opcode(cbuf,0xF0);
2151 // CMPXCHG8 [Eptr]
2152 emit_opcode(cbuf,0x0F);
2153 emit_opcode(cbuf,0xC7);
2154 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2155 // XCHG rbx,ecx
2156 emit_opcode(cbuf,0x87);
2157 emit_opcode(cbuf,0xD9);
2158 %}
2159
2160 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2161 // [Lock]
2162 if( os::is_MP() )
2163 emit_opcode(cbuf,0xF0);
2164
2165 // CMPXCHG [Eptr]
2166 emit_opcode(cbuf,0x0F);
2167 emit_opcode(cbuf,0xB1);
2168 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2169 %}
2170
2171 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2172 int res_encoding = $res$$reg;
2173
2174 // MOV res,0
2175 emit_opcode( cbuf, 0xB8 + res_encoding);
2176 emit_d32( cbuf, 0 );
2177 // JNE,s fail
2178 emit_opcode(cbuf,0x75);
2179 emit_d8(cbuf, 5 );
2180 // MOV res,1
2181 emit_opcode( cbuf, 0xB8 + res_encoding);
2182 emit_d32( cbuf, 1 );
2183 // fail:
2184 %}
2185
2186 enc_class set_instruction_start( ) %{
2187 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2188 %}
2189
2190 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2191 int reg_encoding = $ereg$$reg;
2192 int base = $mem$$base;
2193 int index = $mem$$index;
2194 int scale = $mem$$scale;
2195 int displace = $mem$$disp;
2196 bool disp_is_oop = $mem->disp_is_oop();
2197 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2198 %}
2199
2200 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2201 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2202 int base = $mem$$base;
2203 int index = $mem$$index;
2204 int scale = $mem$$scale;
2205 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2206 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2207 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2208 %}
2209
2210 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2211 int r1, r2;
2212 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2213 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2214 emit_opcode(cbuf,0x0F);
2215 emit_opcode(cbuf,$tertiary);
2216 emit_rm(cbuf, 0x3, r1, r2);
2217 emit_d8(cbuf,$cnt$$constant);
2218 emit_d8(cbuf,$primary);
2219 emit_rm(cbuf, 0x3, $secondary, r1);
2220 emit_d8(cbuf,$cnt$$constant);
2221 %}
2222
2223 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2224 emit_opcode( cbuf, 0x8B ); // Move
2225 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2226 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2227 emit_d8(cbuf,$primary);
2228 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2229 emit_d8(cbuf,$cnt$$constant-32);
2230 }
2231 emit_d8(cbuf,$primary);
2232 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2233 emit_d8(cbuf,31);
2234 %}
2235
2236 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2237 int r1, r2;
2238 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2239 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2240
2241 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2242 emit_rm(cbuf, 0x3, r1, r2);
2243 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2244 emit_opcode(cbuf,$primary);
2245 emit_rm(cbuf, 0x3, $secondary, r1);
2246 emit_d8(cbuf,$cnt$$constant-32);
2247 }
2248 emit_opcode(cbuf,0x33); // XOR r2,r2
2249 emit_rm(cbuf, 0x3, r2, r2);
2250 %}
2251
2252 // Clone of RegMem but accepts an extra parameter to access each
2253 // half of a double in memory; it never needs relocation info.
2254 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2255 emit_opcode(cbuf,$opcode$$constant);
2256 int reg_encoding = $rm_reg$$reg;
2257 int base = $mem$$base;
2258 int index = $mem$$index;
2259 int scale = $mem$$scale;
2260 int displace = $mem$$disp + $disp_for_half$$constant;
2261 bool disp_is_oop = false;
2262 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2263 %}
2264
2265 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2266 //
2267 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2268 // and it never needs relocation information.
2269 // Frequently used to move data between FPU's Stack Top and memory.
2270 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2271 int rm_byte_opcode = $rm_opcode$$constant;
2272 int base = $mem$$base;
2273 int index = $mem$$index;
2274 int scale = $mem$$scale;
2275 int displace = $mem$$disp;
2276 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2277 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2278 %}
2279
2280 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2281 int rm_byte_opcode = $rm_opcode$$constant;
2282 int base = $mem$$base;
2283 int index = $mem$$index;
2284 int scale = $mem$$scale;
2285 int displace = $mem$$disp;
2286 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2287 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2288 %}
2289
2290 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2291 int reg_encoding = $dst$$reg;
2292 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2293 int index = 0x04; // 0x04 indicates no index
2294 int scale = 0x00; // 0x00 indicates no scale
2295 int displace = $src1$$constant; // 0x00 indicates no displacement
2296 bool disp_is_oop = false;
2297 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2298 %}
2299
2300 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2301 // Compare dst,src
2302 emit_opcode(cbuf,0x3B);
2303 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2304 // jmp dst < src around move
2305 emit_opcode(cbuf,0x7C);
2306 emit_d8(cbuf,2);
2307 // move dst,src
2308 emit_opcode(cbuf,0x8B);
2309 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2310 %}
2311
2312 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2313 // Compare dst,src
2314 emit_opcode(cbuf,0x3B);
2315 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2316 // jmp dst > src around move
2317 emit_opcode(cbuf,0x7F);
2318 emit_d8(cbuf,2);
2319 // move dst,src
2320 emit_opcode(cbuf,0x8B);
2321 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2322 %}
2323
2324 enc_class enc_FP_store(memory mem, regD src) %{
2325 // If src is FPR1, we can just FST to store it.
2326 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2327 int reg_encoding = 0x2; // Just store
2328 int base = $mem$$base;
2329 int index = $mem$$index;
2330 int scale = $mem$$scale;
2331 int displace = $mem$$disp;
2332 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2333 if( $src$$reg != FPR1L_enc ) {
2334 reg_encoding = 0x3; // Store & pop
2335 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2336 emit_d8( cbuf, 0xC0-1+$src$$reg );
2337 }
2338 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2339 emit_opcode(cbuf,$primary);
2340 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2341 %}
2342
2343 enc_class neg_reg(eRegI dst) %{
2344 // NEG $dst
2345 emit_opcode(cbuf,0xF7);
2346 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2347 %}
2348
2349 enc_class setLT_reg(eCXRegI dst) %{
2350 // SETLT $dst
2351 emit_opcode(cbuf,0x0F);
2352 emit_opcode(cbuf,0x9C);
2353 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2354 %}
2355
2356 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2357 int tmpReg = $tmp$$reg;
2358
2359 // SUB $p,$q
2360 emit_opcode(cbuf,0x2B);
2361 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2362 // SBB $tmp,$tmp
2363 emit_opcode(cbuf,0x1B);
2364 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2365 // AND $tmp,$y
2366 emit_opcode(cbuf,0x23);
2367 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2368 // ADD $p,$tmp
2369 emit_opcode(cbuf,0x03);
2370 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2371 %}
2372
2373 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2374 int tmpReg = $tmp$$reg;
2375
2376 // SUB $p,$q
2377 emit_opcode(cbuf,0x2B);
2378 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2379 // SBB $tmp,$tmp
2380 emit_opcode(cbuf,0x1B);
2381 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2382 // AND $tmp,$y
2383 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2384 emit_opcode(cbuf,0x23);
2385 int reg_encoding = tmpReg;
2386 int base = $mem$$base;
2387 int index = $mem$$index;
2388 int scale = $mem$$scale;
2389 int displace = $mem$$disp;
2390 bool disp_is_oop = $mem->disp_is_oop();
2391 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2392 // ADD $p,$tmp
2393 emit_opcode(cbuf,0x03);
2394 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2395 %}
2396
2397 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2398 // TEST shift,32
2399 emit_opcode(cbuf,0xF7);
2400 emit_rm(cbuf, 0x3, 0, ECX_enc);
2401 emit_d32(cbuf,0x20);
2402 // JEQ,s small
2403 emit_opcode(cbuf, 0x74);
2404 emit_d8(cbuf, 0x04);
2405 // MOV $dst.hi,$dst.lo
2406 emit_opcode( cbuf, 0x8B );
2407 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2408 // CLR $dst.lo
2409 emit_opcode(cbuf, 0x33);
2410 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2411 // small:
2412 // SHLD $dst.hi,$dst.lo,$shift
2413 emit_opcode(cbuf,0x0F);
2414 emit_opcode(cbuf,0xA5);
2415 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2416 // SHL $dst.lo,$shift"
2417 emit_opcode(cbuf,0xD3);
2418 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2419 %}
2420
2421 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2422 // TEST shift,32
2423 emit_opcode(cbuf,0xF7);
2424 emit_rm(cbuf, 0x3, 0, ECX_enc);
2425 emit_d32(cbuf,0x20);
2426 // JEQ,s small
2427 emit_opcode(cbuf, 0x74);
2428 emit_d8(cbuf, 0x04);
2429 // MOV $dst.lo,$dst.hi
2430 emit_opcode( cbuf, 0x8B );
2431 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2432 // CLR $dst.hi
2433 emit_opcode(cbuf, 0x33);
2434 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2435 // small:
2436 // SHRD $dst.lo,$dst.hi,$shift
2437 emit_opcode(cbuf,0x0F);
2438 emit_opcode(cbuf,0xAD);
2439 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2440 // SHR $dst.hi,$shift"
2441 emit_opcode(cbuf,0xD3);
2442 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2443 %}
2444
2445 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2446 // TEST shift,32
2447 emit_opcode(cbuf,0xF7);
2448 emit_rm(cbuf, 0x3, 0, ECX_enc);
2449 emit_d32(cbuf,0x20);
2450 // JEQ,s small
2451 emit_opcode(cbuf, 0x74);
2452 emit_d8(cbuf, 0x05);
2453 // MOV $dst.lo,$dst.hi
2454 emit_opcode( cbuf, 0x8B );
2455 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2456 // SAR $dst.hi,31
2457 emit_opcode(cbuf, 0xC1);
2458 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2459 emit_d8(cbuf, 0x1F );
2460 // small:
2461 // SHRD $dst.lo,$dst.hi,$shift
2462 emit_opcode(cbuf,0x0F);
2463 emit_opcode(cbuf,0xAD);
2464 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2465 // SAR $dst.hi,$shift"
2466 emit_opcode(cbuf,0xD3);
2467 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2468 %}
2469
2470
2471 // ----------------- Encodings for floating point unit -----------------
2472 // May leave result in FPU-TOS or FPU reg depending on opcodes
2473 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2474 $$$emit8$primary;
2475 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2476 %}
2477
2478 // Pop argument in FPR0 with FSTP ST(0)
2479 enc_class PopFPU() %{
2480 emit_opcode( cbuf, 0xDD );
2481 emit_d8( cbuf, 0xD8 );
2482 %}
2483
2484 // !!!!! equivalent to Pop_Reg_F
2485 enc_class Pop_Reg_D( regD dst ) %{
2486 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2487 emit_d8( cbuf, 0xD8+$dst$$reg );
2488 %}
2489
2490 enc_class Push_Reg_D( regD dst ) %{
2491 emit_opcode( cbuf, 0xD9 );
2492 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2493 %}
2494
2495 enc_class strictfp_bias1( regD dst ) %{
2496 emit_opcode( cbuf, 0xDB ); // FLD m80real
2497 emit_opcode( cbuf, 0x2D );
2498 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2499 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2500 emit_opcode( cbuf, 0xC8+$dst$$reg );
2501 %}
2502
2503 enc_class strictfp_bias2( regD dst ) %{
2504 emit_opcode( cbuf, 0xDB ); // FLD m80real
2505 emit_opcode( cbuf, 0x2D );
2506 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2507 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2508 emit_opcode( cbuf, 0xC8+$dst$$reg );
2509 %}
2510
2511 // Special case for moving an integer register to a stack slot.
2512 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2513 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2514 %}
2515
2516 // Special case for moving a register to a stack slot.
2517 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2518 // Opcode already emitted
2519 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2520 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2521 emit_d32(cbuf, $dst$$disp); // Displacement
2522 %}
2523
2524 // Push the integer in stackSlot 'src' onto FP-stack
2525 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2526 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2527 %}
2528
2529 // Push the float in stackSlot 'src' onto FP-stack
2530 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2531 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2532 %}
2533
2534 // Push the double in stackSlot 'src' onto FP-stack
2535 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2536 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2537 %}
2538
2539 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2540 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2541 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2542 %}
2543
2544 // Same as Pop_Mem_F except for opcode
2545 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2546 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2547 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2548 %}
2549
2550 enc_class Pop_Reg_F( regF dst ) %{
2551 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2552 emit_d8( cbuf, 0xD8+$dst$$reg );
2553 %}
2554
2555 enc_class Push_Reg_F( regF dst ) %{
2556 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2557 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2558 %}
2559
2560 // Push FPU's float to a stack-slot, and pop FPU-stack
2561 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2562 int pop = 0x02;
2563 if ($src$$reg != FPR1L_enc) {
2564 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2565 emit_d8( cbuf, 0xC0-1+$src$$reg );
2566 pop = 0x03;
2567 }
2568 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2569 %}
2570
2571 // Push FPU's double to a stack-slot, and pop FPU-stack
2572 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2573 int pop = 0x02;
2574 if ($src$$reg != FPR1L_enc) {
2575 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2576 emit_d8( cbuf, 0xC0-1+$src$$reg );
2577 pop = 0x03;
2578 }
2579 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2580 %}
2581
2582 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2583 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2584 int pop = 0xD0 - 1; // -1 since we skip FLD
2585 if ($src$$reg != FPR1L_enc) {
2586 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2587 emit_d8( cbuf, 0xC0-1+$src$$reg );
2588 pop = 0xD8;
2589 }
2590 emit_opcode( cbuf, 0xDD );
2591 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2592 %}
2593
2594
2595 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2596 MacroAssembler masm(&cbuf);
2597 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2598 masm.fmul( $src2$$reg+0); // value at TOS
2599 masm.fadd( $src$$reg+0); // value at TOS
2600 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2601 %}
2602
2603
2604 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2605 // load dst in FPR0
2606 emit_opcode( cbuf, 0xD9 );
2607 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2608 if ($src$$reg != FPR1L_enc) {
2609 // fincstp
2610 emit_opcode (cbuf, 0xD9);
2611 emit_opcode (cbuf, 0xF7);
2612 // swap src with FPR1:
2613 // FXCH FPR1 with src
2614 emit_opcode(cbuf, 0xD9);
2615 emit_d8(cbuf, 0xC8-1+$src$$reg );
2616 // fdecstp
2617 emit_opcode (cbuf, 0xD9);
2618 emit_opcode (cbuf, 0xF6);
2619 }
2620 %}
2621
2622 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2623 // Allocate a word
2624 emit_opcode(cbuf,0x83); // SUB ESP,8
2625 emit_opcode(cbuf,0xEC);
2626 emit_d8(cbuf,0x08);
2627
2628 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2629 emit_opcode (cbuf, 0x0F );
2630 emit_opcode (cbuf, 0x11 );
2631 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2632
2633 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2634 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2635
2636 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2637 emit_opcode (cbuf, 0x0F );
2638 emit_opcode (cbuf, 0x11 );
2639 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2640
2641 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2642 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2643
2644 %}
2645
2646 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2647 // Allocate a word
2648 emit_opcode(cbuf,0x83); // SUB ESP,4
2649 emit_opcode(cbuf,0xEC);
2650 emit_d8(cbuf,0x04);
2651
2652 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2653 emit_opcode (cbuf, 0x0F );
2654 emit_opcode (cbuf, 0x11 );
2655 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2656
2657 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2658 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2659
2660 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2661 emit_opcode (cbuf, 0x0F );
2662 emit_opcode (cbuf, 0x11 );
2663 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2664
2665 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2666 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2667
2668 %}
2669
2670 enc_class Push_ResultXD(regXD dst) %{
2671 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2672
2673 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2674 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2675 emit_opcode (cbuf, 0x0F );
2676 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2677 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2678
2679 emit_opcode(cbuf,0x83); // ADD ESP,8
2680 emit_opcode(cbuf,0xC4);
2681 emit_d8(cbuf,0x08);
2682 %}
2683
2684 enc_class Push_ResultX(regX dst, immI d8) %{
2685 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2686
2687 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2688 emit_opcode (cbuf, 0x0F );
2689 emit_opcode (cbuf, 0x10 );
2690 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2691
2692 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2693 emit_opcode(cbuf,0xC4);
2694 emit_d8(cbuf,$d8$$constant);
2695 %}
2696
2697 enc_class Push_SrcXD(regXD src) %{
2698 // Allocate a word
2699 emit_opcode(cbuf,0x83); // SUB ESP,8
2700 emit_opcode(cbuf,0xEC);
2701 emit_d8(cbuf,0x08);
2702
2703 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2704 emit_opcode (cbuf, 0x0F );
2705 emit_opcode (cbuf, 0x11 );
2706 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2707
2708 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2709 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2710 %}
2711
2712 enc_class push_stack_temp_qword() %{
2713 emit_opcode(cbuf,0x83); // SUB ESP,8
2714 emit_opcode(cbuf,0xEC);
2715 emit_d8 (cbuf,0x08);
2716 %}
2717
2718 enc_class pop_stack_temp_qword() %{
2719 emit_opcode(cbuf,0x83); // ADD ESP,8
2720 emit_opcode(cbuf,0xC4);
2721 emit_d8 (cbuf,0x08);
2722 %}
2723
2724 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2725 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2726 emit_opcode (cbuf, 0x0F );
2727 emit_opcode (cbuf, 0x11 );
2728 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2729
2730 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2731 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2732 %}
2733
2734 // Compute X^Y using Intel's fast hardware instructions, if possible.
2735 // Otherwise return a NaN.
2736 enc_class pow_exp_core_encoding %{
2737 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2738 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2739 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2740 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2741 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2742 emit_opcode(cbuf,0x1C);
2743 emit_d8(cbuf,0x24);
2744 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2745 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2746 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2747 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2748 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2749 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2750 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2751 emit_d32(cbuf,0xFFFFF800);
2752 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2753 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2754 emit_d32(cbuf,1023);
2755 emit_opcode(cbuf,0x8B); // mov rbx,eax
2756 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2757 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2758 emit_rm(cbuf,0x3,0x4,EAX_enc);
2759 emit_d8(cbuf,20);
2760 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2761 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2762 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2763 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2764 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2765 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2766 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2767 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2768 emit_d32(cbuf,0);
2769 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2770 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2771 %}
2772
2773 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2774 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2775
2776 enc_class Push_Result_Mod_D( regD src) %{
2777 if ($src$$reg != FPR1L_enc) {
2778 // fincstp
2779 emit_opcode (cbuf, 0xD9);
2780 emit_opcode (cbuf, 0xF7);
2781 // FXCH FPR1 with src
2782 emit_opcode(cbuf, 0xD9);
2783 emit_d8(cbuf, 0xC8-1+$src$$reg );
2784 // fdecstp
2785 emit_opcode (cbuf, 0xD9);
2786 emit_opcode (cbuf, 0xF6);
2787 }
2788 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2789 // // FSTP FPR$dst$$reg
2790 // emit_opcode( cbuf, 0xDD );
2791 // emit_d8( cbuf, 0xD8+$dst$$reg );
2792 %}
2793
2794 enc_class fnstsw_sahf_skip_parity() %{
2795 // fnstsw ax
2796 emit_opcode( cbuf, 0xDF );
2797 emit_opcode( cbuf, 0xE0 );
2798 // sahf
2799 emit_opcode( cbuf, 0x9E );
2800 // jnp ::skip
2801 emit_opcode( cbuf, 0x7B );
2802 emit_opcode( cbuf, 0x05 );
2803 %}
2804
2805 enc_class emitModD() %{
2806 // fprem must be iterative
2807 // :: loop
2808 // fprem
2809 emit_opcode( cbuf, 0xD9 );
2810 emit_opcode( cbuf, 0xF8 );
2811 // wait
2812 emit_opcode( cbuf, 0x9b );
2813 // fnstsw ax
2814 emit_opcode( cbuf, 0xDF );
2815 emit_opcode( cbuf, 0xE0 );
2816 // sahf
2817 emit_opcode( cbuf, 0x9E );
2818 // jp ::loop
2819 emit_opcode( cbuf, 0x0F );
2820 emit_opcode( cbuf, 0x8A );
2821 emit_opcode( cbuf, 0xF4 );
2822 emit_opcode( cbuf, 0xFF );
2823 emit_opcode( cbuf, 0xFF );
2824 emit_opcode( cbuf, 0xFF );
2825 %}
2826
2827 enc_class fpu_flags() %{
2828 // fnstsw_ax
2829 emit_opcode( cbuf, 0xDF);
2830 emit_opcode( cbuf, 0xE0);
2831 // test ax,0x0400
2832 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2833 emit_opcode( cbuf, 0xA9 );
2834 emit_d16 ( cbuf, 0x0400 );
2835 // // // This sequence works, but stalls for 12-16 cycles on PPro
2836 // // test rax,0x0400
2837 // emit_opcode( cbuf, 0xA9 );
2838 // emit_d32 ( cbuf, 0x00000400 );
2839 //
2840 // jz exit (no unordered comparison)
2841 emit_opcode( cbuf, 0x74 );
2842 emit_d8 ( cbuf, 0x02 );
2843 // mov ah,1 - treat as LT case (set carry flag)
2844 emit_opcode( cbuf, 0xB4 );
2845 emit_d8 ( cbuf, 0x01 );
2846 // sahf
2847 emit_opcode( cbuf, 0x9E);
2848 %}
2849
2850 enc_class cmpF_P6_fixup() %{
2851 // Fixup the integer flags in case comparison involved a NaN
2852 //
2853 // JNP exit (no unordered comparison, P-flag is set by NaN)
2854 emit_opcode( cbuf, 0x7B );
2855 emit_d8 ( cbuf, 0x03 );
2856 // MOV AH,1 - treat as LT case (set carry flag)
2857 emit_opcode( cbuf, 0xB4 );
2858 emit_d8 ( cbuf, 0x01 );
2859 // SAHF
2860 emit_opcode( cbuf, 0x9E);
2861 // NOP // target for branch to avoid branch to branch
2862 emit_opcode( cbuf, 0x90);
2863 %}
2864
2865 // fnstsw_ax();
2866 // sahf();
2867 // movl(dst, nan_result);
2868 // jcc(Assembler::parity, exit);
2869 // movl(dst, less_result);
2870 // jcc(Assembler::below, exit);
2871 // movl(dst, equal_result);
2872 // jcc(Assembler::equal, exit);
2873 // movl(dst, greater_result);
2874
2875 // less_result = 1;
2876 // greater_result = -1;
2877 // equal_result = 0;
2878 // nan_result = -1;
2879
2880 enc_class CmpF_Result(eRegI dst) %{
2881 // fnstsw_ax();
2882 emit_opcode( cbuf, 0xDF);
2883 emit_opcode( cbuf, 0xE0);
2884 // sahf
2885 emit_opcode( cbuf, 0x9E);
2886 // movl(dst, nan_result);
2887 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2888 emit_d32( cbuf, -1 );
2889 // jcc(Assembler::parity, exit);
2890 emit_opcode( cbuf, 0x7A );
2891 emit_d8 ( cbuf, 0x13 );
2892 // movl(dst, less_result);
2893 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2894 emit_d32( cbuf, -1 );
2895 // jcc(Assembler::below, exit);
2896 emit_opcode( cbuf, 0x72 );
2897 emit_d8 ( cbuf, 0x0C );
2898 // movl(dst, equal_result);
2899 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2900 emit_d32( cbuf, 0 );
2901 // jcc(Assembler::equal, exit);
2902 emit_opcode( cbuf, 0x74 );
2903 emit_d8 ( cbuf, 0x05 );
2904 // movl(dst, greater_result);
2905 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2906 emit_d32( cbuf, 1 );
2907 %}
2908
2909
2910 // XMM version of CmpF_Result. Because the XMM compare
2911 // instructions set the EFLAGS directly. It becomes simpler than
2912 // the float version above.
2913 enc_class CmpX_Result(eRegI dst) %{
2914 MacroAssembler _masm(&cbuf);
2915 Label nan, inc, done;
2916
2917 __ jccb(Assembler::parity, nan);
2918 __ jccb(Assembler::equal, done);
2919 __ jccb(Assembler::above, inc);
2920 __ bind(nan);
2921 __ decrement(as_Register($dst$$reg)); // NO L qqq
2922 __ jmpb(done);
2923 __ bind(inc);
2924 __ increment(as_Register($dst$$reg)); // NO L qqq
2925 __ bind(done);
2926 %}
2927
2928 // Compare the longs and set flags
2929 // BROKEN! Do Not use as-is
2930 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2931 // CMP $src1.hi,$src2.hi
2932 emit_opcode( cbuf, 0x3B );
2933 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2934 // JNE,s done
2935 emit_opcode(cbuf,0x75);
2936 emit_d8(cbuf, 2 );
2937 // CMP $src1.lo,$src2.lo
2938 emit_opcode( cbuf, 0x3B );
2939 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2940 // done:
2941 %}
2942
2943 enc_class convert_int_long( regL dst, eRegI src ) %{
2944 // mov $dst.lo,$src
2945 int dst_encoding = $dst$$reg;
2946 int src_encoding = $src$$reg;
2947 encode_Copy( cbuf, dst_encoding , src_encoding );
2948 // mov $dst.hi,$src
2949 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2950 // sar $dst.hi,31
2951 emit_opcode( cbuf, 0xC1 );
2952 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2953 emit_d8(cbuf, 0x1F );
2954 %}
2955
2956 enc_class convert_long_double( eRegL src ) %{
2957 // push $src.hi
2958 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2959 // push $src.lo
2960 emit_opcode(cbuf, 0x50+$src$$reg );
2961 // fild 64-bits at [SP]
2962 emit_opcode(cbuf,0xdf);
2963 emit_d8(cbuf, 0x6C);
2964 emit_d8(cbuf, 0x24);
2965 emit_d8(cbuf, 0x00);
2966 // pop stack
2967 emit_opcode(cbuf, 0x83); // add SP, #8
2968 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2969 emit_d8(cbuf, 0x8);
2970 %}
2971
2972 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2973 // IMUL EDX:EAX,$src1
2974 emit_opcode( cbuf, 0xF7 );
2975 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2976 // SAR EDX,$cnt-32
2977 int shift_count = ((int)$cnt$$constant) - 32;
2978 if (shift_count > 0) {
2979 emit_opcode(cbuf, 0xC1);
2980 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2981 emit_d8(cbuf, shift_count);
2982 }
2983 %}
2984
2985 // this version doesn't have add sp, 8
2986 enc_class convert_long_double2( eRegL src ) %{
2987 // push $src.hi
2988 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2989 // push $src.lo
2990 emit_opcode(cbuf, 0x50+$src$$reg );
2991 // fild 64-bits at [SP]
2992 emit_opcode(cbuf,0xdf);
2993 emit_d8(cbuf, 0x6C);
2994 emit_d8(cbuf, 0x24);
2995 emit_d8(cbuf, 0x00);
2996 %}
2997
2998 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2999 // Basic idea: long = (long)int * (long)int
3000 // IMUL EDX:EAX, src
3001 emit_opcode( cbuf, 0xF7 );
3002 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
3003 %}
3004
3005 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
3006 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
3007 // MUL EDX:EAX, src
3008 emit_opcode( cbuf, 0xF7 );
3009 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
3010 %}
3011
3012 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
3013 // Basic idea: lo(result) = lo(x_lo * y_lo)
3014 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
3015 // MOV $tmp,$src.lo
3016 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
3017 // IMUL $tmp,EDX
3018 emit_opcode( cbuf, 0x0F );
3019 emit_opcode( cbuf, 0xAF );
3020 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3021 // MOV EDX,$src.hi
3022 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3023 // IMUL EDX,EAX
3024 emit_opcode( cbuf, 0x0F );
3025 emit_opcode( cbuf, 0xAF );
3026 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3027 // ADD $tmp,EDX
3028 emit_opcode( cbuf, 0x03 );
3029 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3030 // MUL EDX:EAX,$src.lo
3031 emit_opcode( cbuf, 0xF7 );
3032 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3033 // ADD EDX,ESI
3034 emit_opcode( cbuf, 0x03 );
3035 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3036 %}
3037
3038 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3039 // Basic idea: lo(result) = lo(src * y_lo)
3040 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3041 // IMUL $tmp,EDX,$src
3042 emit_opcode( cbuf, 0x6B );
3043 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3044 emit_d8( cbuf, (int)$src$$constant );
3045 // MOV EDX,$src
3046 emit_opcode(cbuf, 0xB8 + EDX_enc);
3047 emit_d32( cbuf, (int)$src$$constant );
3048 // MUL EDX:EAX,EDX
3049 emit_opcode( cbuf, 0xF7 );
3050 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3051 // ADD EDX,ESI
3052 emit_opcode( cbuf, 0x03 );
3053 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3054 %}
3055
3056 enc_class long_div( eRegL src1, eRegL src2 ) %{
3057 // PUSH src1.hi
3058 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3059 // PUSH src1.lo
3060 emit_opcode(cbuf, 0x50+$src1$$reg );
3061 // PUSH src2.hi
3062 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3063 // PUSH src2.lo
3064 emit_opcode(cbuf, 0x50+$src2$$reg );
3065 // CALL directly to the runtime
3066 cbuf.set_insts_mark();
3067 emit_opcode(cbuf,0xE8); // Call into runtime
3068 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3069 // Restore stack
3070 emit_opcode(cbuf, 0x83); // add SP, #framesize
3071 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3072 emit_d8(cbuf, 4*4);
3073 %}
3074
3075 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3076 // PUSH src1.hi
3077 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3078 // PUSH src1.lo
3079 emit_opcode(cbuf, 0x50+$src1$$reg );
3080 // PUSH src2.hi
3081 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3082 // PUSH src2.lo
3083 emit_opcode(cbuf, 0x50+$src2$$reg );
3084 // CALL directly to the runtime
3085 cbuf.set_insts_mark();
3086 emit_opcode(cbuf,0xE8); // Call into runtime
3087 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3088 // Restore stack
3089 emit_opcode(cbuf, 0x83); // add SP, #framesize
3090 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3091 emit_d8(cbuf, 4*4);
3092 %}
3093
3094 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3095 // MOV $tmp,$src.lo
3096 emit_opcode(cbuf, 0x8B);
3097 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3098 // OR $tmp,$src.hi
3099 emit_opcode(cbuf, 0x0B);
3100 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3101 %}
3102
3103 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3104 // CMP $src1.lo,$src2.lo
3105 emit_opcode( cbuf, 0x3B );
3106 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3107 // JNE,s skip
3108 emit_cc(cbuf, 0x70, 0x5);
3109 emit_d8(cbuf,2);
3110 // CMP $src1.hi,$src2.hi
3111 emit_opcode( cbuf, 0x3B );
3112 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3113 %}
3114
3115 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3116 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3117 emit_opcode( cbuf, 0x3B );
3118 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3119 // MOV $tmp,$src1.hi
3120 emit_opcode( cbuf, 0x8B );
3121 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3122 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3123 emit_opcode( cbuf, 0x1B );
3124 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3125 %}
3126
3127 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3128 // XOR $tmp,$tmp
3129 emit_opcode(cbuf,0x33); // XOR
3130 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3131 // CMP $tmp,$src.lo
3132 emit_opcode( cbuf, 0x3B );
3133 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3134 // SBB $tmp,$src.hi
3135 emit_opcode( cbuf, 0x1B );
3136 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3137 %}
3138
3139 // Sniff, sniff... smells like Gnu Superoptimizer
3140 enc_class neg_long( eRegL dst ) %{
3141 emit_opcode(cbuf,0xF7); // NEG hi
3142 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3143 emit_opcode(cbuf,0xF7); // NEG lo
3144 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3145 emit_opcode(cbuf,0x83); // SBB hi,0
3146 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3147 emit_d8 (cbuf,0 );
3148 %}
3149
3150 enc_class movq_ld(regXD dst, memory mem) %{
3151 MacroAssembler _masm(&cbuf);
3152 __ movq($dst$$XMMRegister, $mem$$Address);
3153 %}
3154
3155 enc_class movq_st(memory mem, regXD src) %{
3156 MacroAssembler _masm(&cbuf);
3157 __ movq($mem$$Address, $src$$XMMRegister);
3158 %}
3159
3160 enc_class pshufd_8x8(regX dst, regX src) %{
3161 MacroAssembler _masm(&cbuf);
3162
3163 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3164 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3165 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3166 %}
3167
3168 enc_class pshufd_4x16(regX dst, regX src) %{
3169 MacroAssembler _masm(&cbuf);
3170
3171 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3172 %}
3173
3174 enc_class pshufd(regXD dst, regXD src, int mode) %{
3175 MacroAssembler _masm(&cbuf);
3176
3177 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3178 %}
3179
3180 enc_class pxor(regXD dst, regXD src) %{
3181 MacroAssembler _masm(&cbuf);
3182
3183 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3184 %}
3185
3186 enc_class mov_i2x(regXD dst, eRegI src) %{
3187 MacroAssembler _masm(&cbuf);
3188
3189 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3190 %}
3191
3192
3193 // Because the transitions from emitted code to the runtime
3194 // monitorenter/exit helper stubs are so slow it's critical that
3195 // we inline both the stack-locking fast-path and the inflated fast path.
3196 //
3197 // See also: cmpFastLock and cmpFastUnlock.
3198 //
3199 // What follows is a specialized inline transliteration of the code
3200 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3201 // another option would be to emit TrySlowEnter and TrySlowExit methods
3202 // at startup-time. These methods would accept arguments as
3203 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3204 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3205 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3206 // In practice, however, the # of lock sites is bounded and is usually small.
3207 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3208 // if the processor uses simple bimodal branch predictors keyed by EIP
3209 // Since the helper routines would be called from multiple synchronization
3210 // sites.
3211 //
3212 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3213 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3214 // to those specialized methods. That'd give us a mostly platform-independent
3215 // implementation that the JITs could optimize and inline at their pleasure.
3216 // Done correctly, the only time we'd need to cross to native could would be
3217 // to park() or unpark() threads. We'd also need a few more unsafe operators
3218 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3219 // (b) explicit barriers or fence operations.
3220 //
3221 // TODO:
3222 //
3223 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3224 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3225 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3226 // the lock operators would typically be faster than reifying Self.
3227 //
3228 // * Ideally I'd define the primitives as:
3229 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3230 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3231 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3232 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3233 // Furthermore the register assignments are overconstrained, possibly resulting in
3234 // sub-optimal code near the synchronization site.
3235 //
3236 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3237 // Alternately, use a better sp-proximity test.
3238 //
3239 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3240 // Either one is sufficient to uniquely identify a thread.
3241 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3242 //
3243 // * Intrinsify notify() and notifyAll() for the common cases where the
3244 // object is locked by the calling thread but the waitlist is empty.
3245 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3246 //
3247 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3248 // But beware of excessive branch density on AMD Opterons.
3249 //
3250 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3251 // or failure of the fast-path. If the fast-path fails then we pass
3252 // control to the slow-path, typically in C. In Fast_Lock and
3253 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3254 // will emit a conditional branch immediately after the node.
3255 // So we have branches to branches and lots of ICC.ZF games.
3256 // Instead, it might be better to have C2 pass a "FailureLabel"
3257 // into Fast_Lock and Fast_Unlock. In the case of success, control
3258 // will drop through the node. ICC.ZF is undefined at exit.
3259 // In the case of failure, the node will branch directly to the
3260 // FailureLabel
3261
3262
3263 // obj: object to lock
3264 // box: on-stack box address (displaced header location) - KILLED
3265 // rax,: tmp -- KILLED
3266 // scr: tmp -- KILLED
3267 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3268
3269 Register objReg = as_Register($obj$$reg);
3270 Register boxReg = as_Register($box$$reg);
3271 Register tmpReg = as_Register($tmp$$reg);
3272 Register scrReg = as_Register($scr$$reg);
3273
3274 // Ensure the register assignents are disjoint
3275 guarantee (objReg != boxReg, "") ;
3276 guarantee (objReg != tmpReg, "") ;
3277 guarantee (objReg != scrReg, "") ;
3278 guarantee (boxReg != tmpReg, "") ;
3279 guarantee (boxReg != scrReg, "") ;
3280 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3281
3282 MacroAssembler masm(&cbuf);
3283
3284 if (_counters != NULL) {
3285 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3286 }
3287 if (EmitSync & 1) {
3288 // set box->dhw = unused_mark (3)
3289 // Force all sync thru slow-path: slow_enter() and slow_exit()
3290 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3291 masm.cmpptr (rsp, (int32_t)0) ;
3292 } else
3293 if (EmitSync & 2) {
3294 Label DONE_LABEL ;
3295 if (UseBiasedLocking) {
3296 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3297 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3298 }
3299
3300 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3301 masm.orptr (tmpReg, 0x1);
3302 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3303 if (os::is_MP()) { masm.lock(); }
3304 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3305 masm.jcc(Assembler::equal, DONE_LABEL);
3306 // Recursive locking
3307 masm.subptr(tmpReg, rsp);
3308 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3309 masm.movptr(Address(boxReg, 0), tmpReg);
3310 masm.bind(DONE_LABEL) ;
3311 } else {
3312 // Possible cases that we'll encounter in fast_lock
3313 // ------------------------------------------------
3314 // * Inflated
3315 // -- unlocked
3316 // -- Locked
3317 // = by self
3318 // = by other
3319 // * biased
3320 // -- by Self
3321 // -- by other
3322 // * neutral
3323 // * stack-locked
3324 // -- by self
3325 // = sp-proximity test hits
3326 // = sp-proximity test generates false-negative
3327 // -- by other
3328 //
3329
3330 Label IsInflated, DONE_LABEL, PopDone ;
3331
3332 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3333 // order to reduce the number of conditional branches in the most common cases.
3334 // Beware -- there's a subtle invariant that fetch of the markword
3335 // at [FETCH], below, will never observe a biased encoding (*101b).
3336 // If this invariant is not held we risk exclusion (safety) failure.
3337 if (UseBiasedLocking && !UseOptoBiasInlining) {
3338 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3339 }
3340
3341 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3342 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3343 masm.jccb (Assembler::notZero, IsInflated) ;
3344
3345 // Attempt stack-locking ...
3346 masm.orptr (tmpReg, 0x1);
3347 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3348 if (os::is_MP()) { masm.lock(); }
3349 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3350 if (_counters != NULL) {
3351 masm.cond_inc32(Assembler::equal,
3352 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3353 }
3354 masm.jccb (Assembler::equal, DONE_LABEL);
3355
3356 // Recursive locking
3357 masm.subptr(tmpReg, rsp);
3358 masm.andptr(tmpReg, 0xFFFFF003 );
3359 masm.movptr(Address(boxReg, 0), tmpReg);
3360 if (_counters != NULL) {
3361 masm.cond_inc32(Assembler::equal,
3362 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3363 }
3364 masm.jmp (DONE_LABEL) ;
3365
3366 masm.bind (IsInflated) ;
3367
3368 // The object is inflated.
3369 //
3370 // TODO-FIXME: eliminate the ugly use of manifest constants:
3371 // Use markOopDesc::monitor_value instead of "2".
3372 // use markOop::unused_mark() instead of "3".
3373 // The tmpReg value is an objectMonitor reference ORed with
3374 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3375 // objectmonitor pointer by masking off the "2" bit or we can just
3376 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3377 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3378 //
3379 // I use the latter as it avoids AGI stalls.
3380 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3381 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3382 //
3383 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3384
3385 // boxReg refers to the on-stack BasicLock in the current frame.
3386 // We'd like to write:
3387 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3388 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3389 // additional latency as we have another ST in the store buffer that must drain.
3390
3391 if (EmitSync & 8192) {
3392 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3393 masm.get_thread (scrReg) ;
3394 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3395 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3396 if (os::is_MP()) { masm.lock(); }
3397 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3398 } else
3399 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3400 masm.movptr(scrReg, boxReg) ;
3401 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3402
3403 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3404 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3405 // prefetchw [eax + Offset(_owner)-2]
3406 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3407 }
3408
3409 if ((EmitSync & 64) == 0) {
3410 // Optimistic form: consider XORL tmpReg,tmpReg
3411 masm.movptr(tmpReg, NULL_WORD) ;
3412 } else {
3413 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3414 // Test-And-CAS instead of CAS
3415 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3416 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3417 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3418 }
3419
3420 // Appears unlocked - try to swing _owner from null to non-null.
3421 // Ideally, I'd manifest "Self" with get_thread and then attempt
3422 // to CAS the register containing Self into m->Owner.
3423 // But we don't have enough registers, so instead we can either try to CAS
3424 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3425 // we later store "Self" into m->Owner. Transiently storing a stack address
3426 // (rsp or the address of the box) into m->owner is harmless.
3427 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3428 if (os::is_MP()) { masm.lock(); }
3429 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3430 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3431 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3432 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3433 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3434 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3435
3436 // If the CAS fails we can either retry or pass control to the slow-path.
3437 // We use the latter tactic.
3438 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3439 // If the CAS was successful ...
3440 // Self has acquired the lock
3441 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3442 // Intentional fall-through into DONE_LABEL ...
3443 } else {
3444 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3445 masm.movptr(boxReg, tmpReg) ;
3446
3447 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3448 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3449 // prefetchw [eax + Offset(_owner)-2]
3450 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3451 }
3452
3453 if ((EmitSync & 64) == 0) {
3454 // Optimistic form
3455 masm.xorptr (tmpReg, tmpReg) ;
3456 } else {
3457 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3458 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3459 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3460 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3461 }
3462
3463 // Appears unlocked - try to swing _owner from null to non-null.
3464 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3465 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3466 masm.get_thread (scrReg) ;
3467 if (os::is_MP()) { masm.lock(); }
3468 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3469
3470 // If the CAS fails we can either retry or pass control to the slow-path.
3471 // We use the latter tactic.
3472 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3473 // If the CAS was successful ...
3474 // Self has acquired the lock
3475 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3476 // Intentional fall-through into DONE_LABEL ...
3477 }
3478
3479 // DONE_LABEL is a hot target - we'd really like to place it at the
3480 // start of cache line by padding with NOPs.
3481 // See the AMD and Intel software optimization manuals for the
3482 // most efficient "long" NOP encodings.
3483 // Unfortunately none of our alignment mechanisms suffice.
3484 masm.bind(DONE_LABEL);
3485
3486 // Avoid branch-to-branch on AMD processors
3487 // This appears to be superstition.
3488 if (EmitSync & 32) masm.nop() ;
3489
3490
3491 // At DONE_LABEL the icc ZFlag is set as follows ...
3492 // Fast_Unlock uses the same protocol.
3493 // ZFlag == 1 -> Success
3494 // ZFlag == 0 -> Failure - force control through the slow-path
3495 }
3496 %}
3497
3498 // obj: object to unlock
3499 // box: box address (displaced header location), killed. Must be EAX.
3500 // rbx,: killed tmp; cannot be obj nor box.
3501 //
3502 // Some commentary on balanced locking:
3503 //
3504 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3505 // Methods that don't have provably balanced locking are forced to run in the
3506 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3507 // The interpreter provides two properties:
3508 // I1: At return-time the interpreter automatically and quietly unlocks any
3509 // objects acquired the current activation (frame). Recall that the
3510 // interpreter maintains an on-stack list of locks currently held by
3511 // a frame.
3512 // I2: If a method attempts to unlock an object that is not held by the
3513 // the frame the interpreter throws IMSX.
3514 //
3515 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3516 // B() doesn't have provably balanced locking so it runs in the interpreter.
3517 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3518 // is still locked by A().
3519 //
3520 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3521 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3522 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3523 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3524
3525 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3526
3527 Register objReg = as_Register($obj$$reg);
3528 Register boxReg = as_Register($box$$reg);
3529 Register tmpReg = as_Register($tmp$$reg);
3530
3531 guarantee (objReg != boxReg, "") ;
3532 guarantee (objReg != tmpReg, "") ;
3533 guarantee (boxReg != tmpReg, "") ;
3534 guarantee (boxReg == as_Register(EAX_enc), "") ;
3535 MacroAssembler masm(&cbuf);
3536
3537 if (EmitSync & 4) {
3538 // Disable - inhibit all inlining. Force control through the slow-path
3539 masm.cmpptr (rsp, 0) ;
3540 } else
3541 if (EmitSync & 8) {
3542 Label DONE_LABEL ;
3543 if (UseBiasedLocking) {
3544 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3545 }
3546 // classic stack-locking code ...
3547 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3548 masm.testptr(tmpReg, tmpReg) ;
3549 masm.jcc (Assembler::zero, DONE_LABEL) ;
3550 if (os::is_MP()) { masm.lock(); }
3551 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3552 masm.bind(DONE_LABEL);
3553 } else {
3554 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3555
3556 // Critically, the biased locking test must have precedence over
3557 // and appear before the (box->dhw == 0) recursive stack-lock test.
3558 if (UseBiasedLocking && !UseOptoBiasInlining) {
3559 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3560 }
3561
3562 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3563 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3564 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3565
3566 masm.testptr(tmpReg, 0x02) ; // Inflated?
3567 masm.jccb (Assembler::zero, Stacked) ;
3568
3569 masm.bind (Inflated) ;
3570 // It's inflated.
3571 // Despite our balanced locking property we still check that m->_owner == Self
3572 // as java routines or native JNI code called by this thread might
3573 // have released the lock.
3574 // Refer to the comments in synchronizer.cpp for how we might encode extra
3575 // state in _succ so we can avoid fetching EntryList|cxq.
3576 //
3577 // I'd like to add more cases in fast_lock() and fast_unlock() --
3578 // such as recursive enter and exit -- but we have to be wary of
3579 // I$ bloat, T$ effects and BP$ effects.
3580 //
3581 // If there's no contention try a 1-0 exit. That is, exit without
3582 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3583 // we detect and recover from the race that the 1-0 exit admits.
3584 //
3585 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3586 // before it STs null into _owner, releasing the lock. Updates
3587 // to data protected by the critical section must be visible before
3588 // we drop the lock (and thus before any other thread could acquire
3589 // the lock and observe the fields protected by the lock).
3590 // IA32's memory-model is SPO, so STs are ordered with respect to
3591 // each other and there's no need for an explicit barrier (fence).
3592 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3593
3594 masm.get_thread (boxReg) ;
3595 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3596 // prefetchw [ebx + Offset(_owner)-2]
3597 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3598 }
3599
3600 // Note that we could employ various encoding schemes to reduce
3601 // the number of loads below (currently 4) to just 2 or 3.
3602 // Refer to the comments in synchronizer.cpp.
3603 // In practice the chain of fetches doesn't seem to impact performance, however.
3604 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3605 // Attempt to reduce branch density - AMD's branch predictor.
3606 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3607 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3608 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3609 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3610 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3611 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3612 masm.jmpb (DONE_LABEL) ;
3613 } else {
3614 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3615 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3616 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3617 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3618 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3619 masm.jccb (Assembler::notZero, CheckSucc) ;
3620 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3621 masm.jmpb (DONE_LABEL) ;
3622 }
3623
3624 // The Following code fragment (EmitSync & 65536) improves the performance of
3625 // contended applications and contended synchronization microbenchmarks.
3626 // Unfortunately the emission of the code - even though not executed - causes regressions
3627 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3628 // with an equal number of never-executed NOPs results in the same regression.
3629 // We leave it off by default.
3630
3631 if ((EmitSync & 65536) != 0) {
3632 Label LSuccess, LGoSlowPath ;
3633
3634 masm.bind (CheckSucc) ;
3635
3636 // Optional pre-test ... it's safe to elide this
3637 if ((EmitSync & 16) == 0) {
3638 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3639 masm.jccb (Assembler::zero, LGoSlowPath) ;
3640 }
3641
3642 // We have a classic Dekker-style idiom:
3643 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3644 // There are a number of ways to implement the barrier:
3645 // (1) lock:andl &m->_owner, 0
3646 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3647 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3648 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3649 // (2) If supported, an explicit MFENCE is appealing.
3650 // In older IA32 processors MFENCE is slower than lock:add or xchg
3651 // particularly if the write-buffer is full as might be the case if
3652 // if stores closely precede the fence or fence-equivalent instruction.
3653 // In more modern implementations MFENCE appears faster, however.
3654 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3655 // The $lines underlying the top-of-stack should be in M-state.
3656 // The locked add instruction is serializing, of course.
3657 // (4) Use xchg, which is serializing
3658 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3659 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3660 // The integer condition codes will tell us if succ was 0.
3661 // Since _succ and _owner should reside in the same $line and
3662 // we just stored into _owner, it's likely that the $line
3663 // remains in M-state for the lock:orl.
3664 //
3665 // We currently use (3), although it's likely that switching to (2)
3666 // is correct for the future.
3667
3668 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3669 if (os::is_MP()) {
3670 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3671 masm.mfence();
3672 } else {
3673 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3674 }
3675 }
3676 // Ratify _succ remains non-null
3677 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3678 masm.jccb (Assembler::notZero, LSuccess) ;
3679
3680 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3681 if (os::is_MP()) { masm.lock(); }
3682 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3683 masm.jccb (Assembler::notEqual, LSuccess) ;
3684 // Since we're low on registers we installed rsp as a placeholding in _owner.
3685 // Now install Self over rsp. This is safe as we're transitioning from
3686 // non-null to non=null
3687 masm.get_thread (boxReg) ;
3688 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3689 // Intentional fall-through into LGoSlowPath ...
3690
3691 masm.bind (LGoSlowPath) ;
3692 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3693 masm.jmpb (DONE_LABEL) ;
3694
3695 masm.bind (LSuccess) ;
3696 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3697 masm.jmpb (DONE_LABEL) ;
3698 }
3699
3700 masm.bind (Stacked) ;
3701 // It's not inflated and it's not recursively stack-locked and it's not biased.
3702 // It must be stack-locked.
3703 // Try to reset the header to displaced header.
3704 // The "box" value on the stack is stable, so we can reload
3705 // and be assured we observe the same value as above.
3706 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3707 if (os::is_MP()) { masm.lock(); }
3708 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3709 // Intention fall-thru into DONE_LABEL
3710
3711
3712 // DONE_LABEL is a hot target - we'd really like to place it at the
3713 // start of cache line by padding with NOPs.
3714 // See the AMD and Intel software optimization manuals for the
3715 // most efficient "long" NOP encodings.
3716 // Unfortunately none of our alignment mechanisms suffice.
3717 if ((EmitSync & 65536) == 0) {
3718 masm.bind (CheckSucc) ;
3719 }
3720 masm.bind(DONE_LABEL);
3721
3722 // Avoid branch to branch on AMD processors
3723 if (EmitSync & 32768) { masm.nop() ; }
3724 }
3725 %}
3726
3727
3728 enc_class enc_pop_rdx() %{
3729 emit_opcode(cbuf,0x5A);
3730 %}
3731
3732 enc_class enc_rethrow() %{
3733 cbuf.set_insts_mark();
3734 emit_opcode(cbuf, 0xE9); // jmp entry
3735 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3736 runtime_call_Relocation::spec(), RELOC_IMM32 );
3737 %}
3738
3739
3740 // Convert a double to an int. Java semantics require we do complex
3741 // manglelations in the corner cases. So we set the rounding mode to
3742 // 'zero', store the darned double down as an int, and reset the
3743 // rounding mode to 'nearest'. The hardware throws an exception which
3744 // patches up the correct value directly to the stack.
3745 enc_class D2I_encoding( regD src ) %{
3746 // Flip to round-to-zero mode. We attempted to allow invalid-op
3747 // exceptions here, so that a NAN or other corner-case value will
3748 // thrown an exception (but normal values get converted at full speed).
3749 // However, I2C adapters and other float-stack manglers leave pending
3750 // invalid-op exceptions hanging. We would have to clear them before
3751 // enabling them and that is more expensive than just testing for the
3752 // invalid value Intel stores down in the corner cases.
3753 emit_opcode(cbuf,0xD9); // FLDCW trunc
3754 emit_opcode(cbuf,0x2D);
3755 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3756 // Allocate a word
3757 emit_opcode(cbuf,0x83); // SUB ESP,4
3758 emit_opcode(cbuf,0xEC);
3759 emit_d8(cbuf,0x04);
3760 // Encoding assumes a double has been pushed into FPR0.
3761 // Store down the double as an int, popping the FPU stack
3762 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3763 emit_opcode(cbuf,0x1C);
3764 emit_d8(cbuf,0x24);
3765 // Restore the rounding mode; mask the exception
3766 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3767 emit_opcode(cbuf,0x2D);
3768 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3769 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3770 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3771
3772 // Load the converted int; adjust CPU stack
3773 emit_opcode(cbuf,0x58); // POP EAX
3774 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3775 emit_d32 (cbuf,0x80000000); // 0x80000000
3776 emit_opcode(cbuf,0x75); // JNE around_slow_call
3777 emit_d8 (cbuf,0x07); // Size of slow_call
3778 // Push src onto stack slow-path
3779 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3780 emit_d8 (cbuf,0xC0-1+$src$$reg );
3781 // CALL directly to the runtime
3782 cbuf.set_insts_mark();
3783 emit_opcode(cbuf,0xE8); // Call into runtime
3784 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3785 // Carry on here...
3786 %}
3787
3788 enc_class D2L_encoding( regD src ) %{
3789 emit_opcode(cbuf,0xD9); // FLDCW trunc
3790 emit_opcode(cbuf,0x2D);
3791 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3792 // Allocate a word
3793 emit_opcode(cbuf,0x83); // SUB ESP,8
3794 emit_opcode(cbuf,0xEC);
3795 emit_d8(cbuf,0x08);
3796 // Encoding assumes a double has been pushed into FPR0.
3797 // Store down the double as a long, popping the FPU stack
3798 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3799 emit_opcode(cbuf,0x3C);
3800 emit_d8(cbuf,0x24);
3801 // Restore the rounding mode; mask the exception
3802 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3803 emit_opcode(cbuf,0x2D);
3804 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3805 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3806 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3807
3808 // Load the converted int; adjust CPU stack
3809 emit_opcode(cbuf,0x58); // POP EAX
3810 emit_opcode(cbuf,0x5A); // POP EDX
3811 emit_opcode(cbuf,0x81); // CMP EDX,imm
3812 emit_d8 (cbuf,0xFA); // rdx
3813 emit_d32 (cbuf,0x80000000); // 0x80000000
3814 emit_opcode(cbuf,0x75); // JNE around_slow_call
3815 emit_d8 (cbuf,0x07+4); // Size of slow_call
3816 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3817 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3818 emit_opcode(cbuf,0x75); // JNE around_slow_call
3819 emit_d8 (cbuf,0x07); // Size of slow_call
3820 // Push src onto stack slow-path
3821 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3822 emit_d8 (cbuf,0xC0-1+$src$$reg );
3823 // CALL directly to the runtime
3824 cbuf.set_insts_mark();
3825 emit_opcode(cbuf,0xE8); // Call into runtime
3826 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3827 // Carry on here...
3828 %}
3829
3830 enc_class X2L_encoding( regX src ) %{
3831 // Allocate a word
3832 emit_opcode(cbuf,0x83); // SUB ESP,8
3833 emit_opcode(cbuf,0xEC);
3834 emit_d8(cbuf,0x08);
3835
3836 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3837 emit_opcode (cbuf, 0x0F );
3838 emit_opcode (cbuf, 0x11 );
3839 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3840
3841 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3842 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3843
3844 emit_opcode(cbuf,0xD9); // FLDCW trunc
3845 emit_opcode(cbuf,0x2D);
3846 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3847
3848 // Encoding assumes a double has been pushed into FPR0.
3849 // Store down the double as a long, popping the FPU stack
3850 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3851 emit_opcode(cbuf,0x3C);
3852 emit_d8(cbuf,0x24);
3853
3854 // Restore the rounding mode; mask the exception
3855 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3856 emit_opcode(cbuf,0x2D);
3857 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3858 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3859 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3860
3861 // Load the converted int; adjust CPU stack
3862 emit_opcode(cbuf,0x58); // POP EAX
3863
3864 emit_opcode(cbuf,0x5A); // POP EDX
3865
3866 emit_opcode(cbuf,0x81); // CMP EDX,imm
3867 emit_d8 (cbuf,0xFA); // rdx
3868 emit_d32 (cbuf,0x80000000);// 0x80000000
3869
3870 emit_opcode(cbuf,0x75); // JNE around_slow_call
3871 emit_d8 (cbuf,0x13+4); // Size of slow_call
3872
3873 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3874 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3875
3876 emit_opcode(cbuf,0x75); // JNE around_slow_call
3877 emit_d8 (cbuf,0x13); // Size of slow_call
3878
3879 // Allocate a word
3880 emit_opcode(cbuf,0x83); // SUB ESP,4
3881 emit_opcode(cbuf,0xEC);
3882 emit_d8(cbuf,0x04);
3883
3884 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3885 emit_opcode (cbuf, 0x0F );
3886 emit_opcode (cbuf, 0x11 );
3887 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3888
3889 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3890 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3891
3892 emit_opcode(cbuf,0x83); // ADD ESP,4
3893 emit_opcode(cbuf,0xC4);
3894 emit_d8(cbuf,0x04);
3895
3896 // CALL directly to the runtime
3897 cbuf.set_insts_mark();
3898 emit_opcode(cbuf,0xE8); // Call into runtime
3899 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3900 // Carry on here...
3901 %}
3902
3903 enc_class XD2L_encoding( regXD src ) %{
3904 // Allocate a word
3905 emit_opcode(cbuf,0x83); // SUB ESP,8
3906 emit_opcode(cbuf,0xEC);
3907 emit_d8(cbuf,0x08);
3908
3909 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3910 emit_opcode (cbuf, 0x0F );
3911 emit_opcode (cbuf, 0x11 );
3912 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3913
3914 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
3915 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3916
3917 emit_opcode(cbuf,0xD9); // FLDCW trunc
3918 emit_opcode(cbuf,0x2D);
3919 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3920
3921 // Encoding assumes a double has been pushed into FPR0.
3922 // Store down the double as a long, popping the FPU stack
3923 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3924 emit_opcode(cbuf,0x3C);
3925 emit_d8(cbuf,0x24);
3926
3927 // Restore the rounding mode; mask the exception
3928 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3929 emit_opcode(cbuf,0x2D);
3930 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3931 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3932 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3933
3934 // Load the converted int; adjust CPU stack
3935 emit_opcode(cbuf,0x58); // POP EAX
3936
3937 emit_opcode(cbuf,0x5A); // POP EDX
3938
3939 emit_opcode(cbuf,0x81); // CMP EDX,imm
3940 emit_d8 (cbuf,0xFA); // rdx
3941 emit_d32 (cbuf,0x80000000); // 0x80000000
3942
3943 emit_opcode(cbuf,0x75); // JNE around_slow_call
3944 emit_d8 (cbuf,0x13+4); // Size of slow_call
3945
3946 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3947 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3948
3949 emit_opcode(cbuf,0x75); // JNE around_slow_call
3950 emit_d8 (cbuf,0x13); // Size of slow_call
3951
3952 // Push src onto stack slow-path
3953 // Allocate a word
3954 emit_opcode(cbuf,0x83); // SUB ESP,8
3955 emit_opcode(cbuf,0xEC);
3956 emit_d8(cbuf,0x08);
3957
3958 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
3959 emit_opcode (cbuf, 0x0F );
3960 emit_opcode (cbuf, 0x11 );
3961 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3962
3963 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
3964 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3965
3966 emit_opcode(cbuf,0x83); // ADD ESP,8
3967 emit_opcode(cbuf,0xC4);
3968 emit_d8(cbuf,0x08);
3969
3970 // CALL directly to the runtime
3971 cbuf.set_insts_mark();
3972 emit_opcode(cbuf,0xE8); // Call into runtime
3973 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3974 // Carry on here...
3975 %}
3976
3977 enc_class D2X_encoding( regX dst, regD src ) %{
3978 // Allocate a word
3979 emit_opcode(cbuf,0x83); // SUB ESP,4
3980 emit_opcode(cbuf,0xEC);
3981 emit_d8(cbuf,0x04);
3982 int pop = 0x02;
3983 if ($src$$reg != FPR1L_enc) {
3984 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
3985 emit_d8( cbuf, 0xC0-1+$src$$reg );
3986 pop = 0x03;
3987 }
3988 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
3989
3990 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
3991 emit_opcode (cbuf, 0x0F );
3992 emit_opcode (cbuf, 0x10 );
3993 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
3994
3995 emit_opcode(cbuf,0x83); // ADD ESP,4
3996 emit_opcode(cbuf,0xC4);
3997 emit_d8(cbuf,0x04);
3998 // Carry on here...
3999 %}
4000
4001 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4002 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4003
4004 // Compare the result to see if we need to go to the slow path
4005 emit_opcode(cbuf,0x81); // CMP dst,imm
4006 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4007 emit_d32 (cbuf,0x80000000); // 0x80000000
4008
4009 emit_opcode(cbuf,0x75); // JNE around_slow_call
4010 emit_d8 (cbuf,0x13); // Size of slow_call
4011 // Store xmm to a temp memory
4012 // location and push it onto stack.
4013
4014 emit_opcode(cbuf,0x83); // SUB ESP,4
4015 emit_opcode(cbuf,0xEC);
4016 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4017
4018 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4019 emit_opcode (cbuf, 0x0F );
4020 emit_opcode (cbuf, 0x11 );
4021 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4022
4023 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4024 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4025
4026 emit_opcode(cbuf,0x83); // ADD ESP,4
4027 emit_opcode(cbuf,0xC4);
4028 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4029
4030 // CALL directly to the runtime
4031 cbuf.set_insts_mark();
4032 emit_opcode(cbuf,0xE8); // Call into runtime
4033 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4034
4035 // Carry on here...
4036 %}
4037
4038 enc_class X2D_encoding( regD dst, regX src ) %{
4039 // Allocate a word
4040 emit_opcode(cbuf,0x83); // SUB ESP,4
4041 emit_opcode(cbuf,0xEC);
4042 emit_d8(cbuf,0x04);
4043
4044 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4045 emit_opcode (cbuf, 0x0F );
4046 emit_opcode (cbuf, 0x11 );
4047 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4048
4049 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4050 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4051
4052 emit_opcode(cbuf,0x83); // ADD ESP,4
4053 emit_opcode(cbuf,0xC4);
4054 emit_d8(cbuf,0x04);
4055
4056 // Carry on here...
4057 %}
4058
4059 enc_class AbsXF_encoding(regX dst) %{
4060 address signmask_address=(address)float_signmask_pool;
4061 // andpd:\tANDPS $dst,[signconst]
4062 emit_opcode(cbuf, 0x0F);
4063 emit_opcode(cbuf, 0x54);
4064 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4065 emit_d32(cbuf, (int)signmask_address);
4066 %}
4067
4068 enc_class AbsXD_encoding(regXD dst) %{
4069 address signmask_address=(address)double_signmask_pool;
4070 // andpd:\tANDPD $dst,[signconst]
4071 emit_opcode(cbuf, 0x66);
4072 emit_opcode(cbuf, 0x0F);
4073 emit_opcode(cbuf, 0x54);
4074 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4075 emit_d32(cbuf, (int)signmask_address);
4076 %}
4077
4078 enc_class NegXF_encoding(regX dst) %{
4079 address signmask_address=(address)float_signflip_pool;
4080 // andpd:\tXORPS $dst,[signconst]
4081 emit_opcode(cbuf, 0x0F);
4082 emit_opcode(cbuf, 0x57);
4083 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4084 emit_d32(cbuf, (int)signmask_address);
4085 %}
4086
4087 enc_class NegXD_encoding(regXD dst) %{
4088 address signmask_address=(address)double_signflip_pool;
4089 // andpd:\tXORPD $dst,[signconst]
4090 emit_opcode(cbuf, 0x66);
4091 emit_opcode(cbuf, 0x0F);
4092 emit_opcode(cbuf, 0x57);
4093 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4094 emit_d32(cbuf, (int)signmask_address);
4095 %}
4096
4097 enc_class FMul_ST_reg( eRegF src1 ) %{
4098 // Operand was loaded from memory into fp ST (stack top)
4099 // FMUL ST,$src /* D8 C8+i */
4100 emit_opcode(cbuf, 0xD8);
4101 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4102 %}
4103
4104 enc_class FAdd_ST_reg( eRegF src2 ) %{
4105 // FADDP ST,src2 /* D8 C0+i */
4106 emit_opcode(cbuf, 0xD8);
4107 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4108 //could use FADDP src2,fpST /* DE C0+i */
4109 %}
4110
4111 enc_class FAddP_reg_ST( eRegF src2 ) %{
4112 // FADDP src2,ST /* DE C0+i */
4113 emit_opcode(cbuf, 0xDE);
4114 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4115 %}
4116
4117 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4118 // Operand has been loaded into fp ST (stack top)
4119 // FSUB ST,$src1
4120 emit_opcode(cbuf, 0xD8);
4121 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4122
4123 // FDIV
4124 emit_opcode(cbuf, 0xD8);
4125 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4126 %}
4127
4128 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4129 // Operand was loaded from memory into fp ST (stack top)
4130 // FADD ST,$src /* D8 C0+i */
4131 emit_opcode(cbuf, 0xD8);
4132 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4133
4134 // FMUL ST,src2 /* D8 C*+i */
4135 emit_opcode(cbuf, 0xD8);
4136 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4137 %}
4138
4139
4140 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4141 // Operand was loaded from memory into fp ST (stack top)
4142 // FADD ST,$src /* D8 C0+i */
4143 emit_opcode(cbuf, 0xD8);
4144 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4145
4146 // FMULP src2,ST /* DE C8+i */
4147 emit_opcode(cbuf, 0xDE);
4148 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4149 %}
4150
4151 // Atomically load the volatile long
4152 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4153 emit_opcode(cbuf,0xDF);
4154 int rm_byte_opcode = 0x05;
4155 int base = $mem$$base;
4156 int index = $mem$$index;
4157 int scale = $mem$$scale;
4158 int displace = $mem$$disp;
4159 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4160 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4161 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4162 %}
4163
4164 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4165 { // Atomic long load
4166 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4167 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4168 emit_opcode(cbuf,0x0F);
4169 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4170 int base = $mem$$base;
4171 int index = $mem$$index;
4172 int scale = $mem$$scale;
4173 int displace = $mem$$disp;
4174 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4175 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4176 }
4177 { // MOVSD $dst,$tmp ! atomic long store
4178 emit_opcode(cbuf,0xF2);
4179 emit_opcode(cbuf,0x0F);
4180 emit_opcode(cbuf,0x11);
4181 int base = $dst$$base;
4182 int index = $dst$$index;
4183 int scale = $dst$$scale;
4184 int displace = $dst$$disp;
4185 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4186 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4187 }
4188 %}
4189
4190 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4191 { // Atomic long load
4192 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4193 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4194 emit_opcode(cbuf,0x0F);
4195 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4196 int base = $mem$$base;
4197 int index = $mem$$index;
4198 int scale = $mem$$scale;
4199 int displace = $mem$$disp;
4200 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4201 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4202 }
4203 { // MOVD $dst.lo,$tmp
4204 emit_opcode(cbuf,0x66);
4205 emit_opcode(cbuf,0x0F);
4206 emit_opcode(cbuf,0x7E);
4207 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4208 }
4209 { // PSRLQ $tmp,32
4210 emit_opcode(cbuf,0x66);
4211 emit_opcode(cbuf,0x0F);
4212 emit_opcode(cbuf,0x73);
4213 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4214 emit_d8(cbuf, 0x20);
4215 }
4216 { // MOVD $dst.hi,$tmp
4217 emit_opcode(cbuf,0x66);
4218 emit_opcode(cbuf,0x0F);
4219 emit_opcode(cbuf,0x7E);
4220 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4221 }
4222 %}
4223
4224 // Volatile Store Long. Must be atomic, so move it into
4225 // the FP TOS and then do a 64-bit FIST. Has to probe the
4226 // target address before the store (for null-ptr checks)
4227 // so the memory operand is used twice in the encoding.
4228 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4229 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4230 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
4231 emit_opcode(cbuf,0xDF);
4232 int rm_byte_opcode = 0x07;
4233 int base = $mem$$base;
4234 int index = $mem$$index;
4235 int scale = $mem$$scale;
4236 int displace = $mem$$disp;
4237 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4238 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4239 %}
4240
4241 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4242 { // Atomic long load
4243 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4244 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4245 emit_opcode(cbuf,0x0F);
4246 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4247 int base = $src$$base;
4248 int index = $src$$index;
4249 int scale = $src$$scale;
4250 int displace = $src$$disp;
4251 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4252 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4253 }
4254 cbuf.set_insts_mark(); // Mark start of MOVSD in case $mem has an oop
4255 { // MOVSD $mem,$tmp ! atomic long store
4256 emit_opcode(cbuf,0xF2);
4257 emit_opcode(cbuf,0x0F);
4258 emit_opcode(cbuf,0x11);
4259 int base = $mem$$base;
4260 int index = $mem$$index;
4261 int scale = $mem$$scale;
4262 int displace = $mem$$disp;
4263 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4264 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4265 }
4266 %}
4267
4268 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4269 { // MOVD $tmp,$src.lo
4270 emit_opcode(cbuf,0x66);
4271 emit_opcode(cbuf,0x0F);
4272 emit_opcode(cbuf,0x6E);
4273 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4274 }
4275 { // MOVD $tmp2,$src.hi
4276 emit_opcode(cbuf,0x66);
4277 emit_opcode(cbuf,0x0F);
4278 emit_opcode(cbuf,0x6E);
4279 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4280 }
4281 { // PUNPCKLDQ $tmp,$tmp2
4282 emit_opcode(cbuf,0x66);
4283 emit_opcode(cbuf,0x0F);
4284 emit_opcode(cbuf,0x62);
4285 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4286 }
4287 cbuf.set_insts_mark(); // Mark start of MOVSD in case $mem has an oop
4288 { // MOVSD $mem,$tmp ! atomic long store
4289 emit_opcode(cbuf,0xF2);
4290 emit_opcode(cbuf,0x0F);
4291 emit_opcode(cbuf,0x11);
4292 int base = $mem$$base;
4293 int index = $mem$$index;
4294 int scale = $mem$$scale;
4295 int displace = $mem$$disp;
4296 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4297 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4298 }
4299 %}
4300
4301 // Safepoint Poll. This polls the safepoint page, and causes an
4302 // exception if it is not readable. Unfortunately, it kills the condition code
4303 // in the process
4304 // We current use TESTL [spp],EDI
4305 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4306
4307 enc_class Safepoint_Poll() %{
4308 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
4309 emit_opcode(cbuf,0x85);
4310 emit_rm (cbuf, 0x0, 0x7, 0x5);
4311 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4312 %}
4313 %}
4314
4315
4316 //----------FRAME--------------------------------------------------------------
4317 // Definition of frame structure and management information.
4318 //
4319 // S T A C K L A Y O U T Allocators stack-slot number
4320 // | (to get allocators register number
4321 // G Owned by | | v add OptoReg::stack0())
4322 // r CALLER | |
4323 // o | +--------+ pad to even-align allocators stack-slot
4324 // w V | pad0 | numbers; owned by CALLER
4325 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4326 // h ^ | in | 5
4327 // | | args | 4 Holes in incoming args owned by SELF
4328 // | | | | 3
4329 // | | +--------+
4330 // V | | old out| Empty on Intel, window on Sparc
4331 // | old |preserve| Must be even aligned.
4332 // | SP-+--------+----> Matcher::_old_SP, even aligned
4333 // | | in | 3 area for Intel ret address
4334 // Owned by |preserve| Empty on Sparc.
4335 // SELF +--------+
4336 // | | pad2 | 2 pad to align old SP
4337 // | +--------+ 1
4338 // | | locks | 0
4339 // | +--------+----> OptoReg::stack0(), even aligned
4340 // | | pad1 | 11 pad to align new SP
4341 // | +--------+
4342 // | | | 10
4343 // | | spills | 9 spills
4344 // V | | 8 (pad0 slot for callee)
4345 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4346 // ^ | out | 7
4347 // | | args | 6 Holes in outgoing args owned by CALLEE
4348 // Owned by +--------+
4349 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4350 // | new |preserve| Must be even-aligned.
4351 // | SP-+--------+----> Matcher::_new_SP, even aligned
4352 // | | |
4353 //
4354 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4355 // known from SELF's arguments and the Java calling convention.
4356 // Region 6-7 is determined per call site.
4357 // Note 2: If the calling convention leaves holes in the incoming argument
4358 // area, those holes are owned by SELF. Holes in the outgoing area
4359 // are owned by the CALLEE. Holes should not be nessecary in the
4360 // incoming area, as the Java calling convention is completely under
4361 // the control of the AD file. Doubles can be sorted and packed to
4362 // avoid holes. Holes in the outgoing arguments may be nessecary for
4363 // varargs C calling conventions.
4364 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4365 // even aligned with pad0 as needed.
4366 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4367 // region 6-11 is even aligned; it may be padded out more so that
4368 // the region from SP to FP meets the minimum stack alignment.
4369
4370 frame %{
4371 // What direction does stack grow in (assumed to be same for C & Java)
4372 stack_direction(TOWARDS_LOW);
4373
4374 // These three registers define part of the calling convention
4375 // between compiled code and the interpreter.
4376 inline_cache_reg(EAX); // Inline Cache Register
4377 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4378
4379 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4380 cisc_spilling_operand_name(indOffset32);
4381
4382 // Number of stack slots consumed by locking an object
4383 sync_stack_slots(1);
4384
4385 // Compiled code's Frame Pointer
4386 frame_pointer(ESP);
4387 // Interpreter stores its frame pointer in a register which is
4388 // stored to the stack by I2CAdaptors.
4389 // I2CAdaptors convert from interpreted java to compiled java.
4390 interpreter_frame_pointer(EBP);
4391
4392 // Stack alignment requirement
4393 // Alignment size in bytes (128-bit -> 16 bytes)
4394 stack_alignment(StackAlignmentInBytes);
4395
4396 // Number of stack slots between incoming argument block and the start of
4397 // a new frame. The PROLOG must add this many slots to the stack. The
4398 // EPILOG must remove this many slots. Intel needs one slot for
4399 // return address and one for rbp, (must save rbp)
4400 in_preserve_stack_slots(2+VerifyStackAtCalls);
4401
4402 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4403 // for calls to C. Supports the var-args backing area for register parms.
4404 varargs_C_out_slots_killed(0);
4405
4406 // The after-PROLOG location of the return address. Location of
4407 // return address specifies a type (REG or STACK) and a number
4408 // representing the register number (i.e. - use a register name) or
4409 // stack slot.
4410 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4411 // Otherwise, it is above the locks and verification slot and alignment word
4412 return_addr(STACK - 1 +
4413 round_to(1+VerifyStackAtCalls+
4414 Compile::current()->fixed_slots(),
4415 (StackAlignmentInBytes/wordSize)));
4416
4417 // Body of function which returns an integer array locating
4418 // arguments either in registers or in stack slots. Passed an array
4419 // of ideal registers called "sig" and a "length" count. Stack-slot
4420 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4421 // arguments for a CALLEE. Incoming stack arguments are
4422 // automatically biased by the preserve_stack_slots field above.
4423 calling_convention %{
4424 // No difference between ingoing/outgoing just pass false
4425 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4426 %}
4427
4428
4429 // Body of function which returns an integer array locating
4430 // arguments either in registers or in stack slots. Passed an array
4431 // of ideal registers called "sig" and a "length" count. Stack-slot
4432 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4433 // arguments for a CALLEE. Incoming stack arguments are
4434 // automatically biased by the preserve_stack_slots field above.
4435 c_calling_convention %{
4436 // This is obviously always outgoing
4437 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4438 %}
4439
4440 // Location of C & interpreter return values
4441 c_return_value %{
4442 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4443 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4444 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4445
4446 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4447 // that C functions return float and double results in XMM0.
4448 if( ideal_reg == Op_RegD && UseSSE>=2 )
4449 return OptoRegPair(XMM0b_num,XMM0a_num);
4450 if( ideal_reg == Op_RegF && UseSSE>=2 )
4451 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4452
4453 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4454 %}
4455
4456 // Location of return values
4457 return_value %{
4458 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4459 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4460 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4461 if( ideal_reg == Op_RegD && UseSSE>=2 )
4462 return OptoRegPair(XMM0b_num,XMM0a_num);
4463 if( ideal_reg == Op_RegF && UseSSE>=1 )
4464 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4465 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4466 %}
4467
4468 %}
4469
4470 //----------ATTRIBUTES---------------------------------------------------------
4471 //----------Operand Attributes-------------------------------------------------
4472 op_attrib op_cost(0); // Required cost attribute
4473
4474 //----------Instruction Attributes---------------------------------------------
4475 ins_attrib ins_cost(100); // Required cost attribute
4476 ins_attrib ins_size(8); // Required size attribute (in bits)
4477 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4478 // non-matching short branch variant of some
4479 // long branch?
4480 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4481 // specifies the alignment that some part of the instruction (not
4482 // necessarily the start) requires. If > 1, a compute_padding()
4483 // function must be provided for the instruction
4484
4485 //----------OPERANDS-----------------------------------------------------------
4486 // Operand definitions must precede instruction definitions for correct parsing
4487 // in the ADLC because operands constitute user defined types which are used in
4488 // instruction definitions.
4489
4490 //----------Simple Operands----------------------------------------------------
4491 // Immediate Operands
4492 // Integer Immediate
4493 operand immI() %{
4494 match(ConI);
4495
4496 op_cost(10);
4497 format %{ %}
4498 interface(CONST_INTER);
4499 %}
4500
4501 // Constant for test vs zero
4502 operand immI0() %{
4503 predicate(n->get_int() == 0);
4504 match(ConI);
4505
4506 op_cost(0);
4507 format %{ %}
4508 interface(CONST_INTER);
4509 %}
4510
4511 // Constant for increment
4512 operand immI1() %{
4513 predicate(n->get_int() == 1);
4514 match(ConI);
4515
4516 op_cost(0);
4517 format %{ %}
4518 interface(CONST_INTER);
4519 %}
4520
4521 // Constant for decrement
4522 operand immI_M1() %{
4523 predicate(n->get_int() == -1);
4524 match(ConI);
4525
4526 op_cost(0);
4527 format %{ %}
4528 interface(CONST_INTER);
4529 %}
4530
4531 // Valid scale values for addressing modes
4532 operand immI2() %{
4533 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4534 match(ConI);
4535
4536 format %{ %}
4537 interface(CONST_INTER);
4538 %}
4539
4540 operand immI8() %{
4541 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4542 match(ConI);
4543
4544 op_cost(5);
4545 format %{ %}
4546 interface(CONST_INTER);
4547 %}
4548
4549 operand immI16() %{
4550 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4551 match(ConI);
4552
4553 op_cost(10);
4554 format %{ %}
4555 interface(CONST_INTER);
4556 %}
4557
4558 // Constant for long shifts
4559 operand immI_32() %{
4560 predicate( n->get_int() == 32 );
4561 match(ConI);
4562
4563 op_cost(0);
4564 format %{ %}
4565 interface(CONST_INTER);
4566 %}
4567
4568 operand immI_1_31() %{
4569 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4570 match(ConI);
4571
4572 op_cost(0);
4573 format %{ %}
4574 interface(CONST_INTER);
4575 %}
4576
4577 operand immI_32_63() %{
4578 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4579 match(ConI);
4580 op_cost(0);
4581
4582 format %{ %}
4583 interface(CONST_INTER);
4584 %}
4585
4586 operand immI_1() %{
4587 predicate( n->get_int() == 1 );
4588 match(ConI);
4589
4590 op_cost(0);
4591 format %{ %}
4592 interface(CONST_INTER);
4593 %}
4594
4595 operand immI_2() %{
4596 predicate( n->get_int() == 2 );
4597 match(ConI);
4598
4599 op_cost(0);
4600 format %{ %}
4601 interface(CONST_INTER);
4602 %}
4603
4604 operand immI_3() %{
4605 predicate( n->get_int() == 3 );
4606 match(ConI);
4607
4608 op_cost(0);
4609 format %{ %}
4610 interface(CONST_INTER);
4611 %}
4612
4613 // Pointer Immediate
4614 operand immP() %{
4615 match(ConP);
4616
4617 op_cost(10);
4618 format %{ %}
4619 interface(CONST_INTER);
4620 %}
4621
4622 // NULL Pointer Immediate
4623 operand immP0() %{
4624 predicate( n->get_ptr() == 0 );
4625 match(ConP);
4626 op_cost(0);
4627
4628 format %{ %}
4629 interface(CONST_INTER);
4630 %}
4631
4632 // Long Immediate
4633 operand immL() %{
4634 match(ConL);
4635
4636 op_cost(20);
4637 format %{ %}
4638 interface(CONST_INTER);
4639 %}
4640
4641 // Long Immediate zero
4642 operand immL0() %{
4643 predicate( n->get_long() == 0L );
4644 match(ConL);
4645 op_cost(0);
4646
4647 format %{ %}
4648 interface(CONST_INTER);
4649 %}
4650
4651 // Long Immediate zero
4652 operand immL_M1() %{
4653 predicate( n->get_long() == -1L );
4654 match(ConL);
4655 op_cost(0);
4656
4657 format %{ %}
4658 interface(CONST_INTER);
4659 %}
4660
4661 // Long immediate from 0 to 127.
4662 // Used for a shorter form of long mul by 10.
4663 operand immL_127() %{
4664 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4665 match(ConL);
4666 op_cost(0);
4667
4668 format %{ %}
4669 interface(CONST_INTER);
4670 %}
4671
4672 // Long Immediate: low 32-bit mask
4673 operand immL_32bits() %{
4674 predicate(n->get_long() == 0xFFFFFFFFL);
4675 match(ConL);
4676 op_cost(0);
4677
4678 format %{ %}
4679 interface(CONST_INTER);
4680 %}
4681
4682 // Long Immediate: low 32-bit mask
4683 operand immL32() %{
4684 predicate(n->get_long() == (int)(n->get_long()));
4685 match(ConL);
4686 op_cost(20);
4687
4688 format %{ %}
4689 interface(CONST_INTER);
4690 %}
4691
4692 //Double Immediate zero
4693 operand immD0() %{
4694 // Do additional (and counter-intuitive) test against NaN to work around VC++
4695 // bug that generates code such that NaNs compare equal to 0.0
4696 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4697 match(ConD);
4698
4699 op_cost(5);
4700 format %{ %}
4701 interface(CONST_INTER);
4702 %}
4703
4704 // Double Immediate one
4705 operand immD1() %{
4706 predicate( UseSSE<=1 && n->getd() == 1.0 );
4707 match(ConD);
4708
4709 op_cost(5);
4710 format %{ %}
4711 interface(CONST_INTER);
4712 %}
4713
4714 // Double Immediate
4715 operand immD() %{
4716 predicate(UseSSE<=1);
4717 match(ConD);
4718
4719 op_cost(5);
4720 format %{ %}
4721 interface(CONST_INTER);
4722 %}
4723
4724 operand immXD() %{
4725 predicate(UseSSE>=2);
4726 match(ConD);
4727
4728 op_cost(5);
4729 format %{ %}
4730 interface(CONST_INTER);
4731 %}
4732
4733 // Double Immediate zero
4734 operand immXD0() %{
4735 // Do additional (and counter-intuitive) test against NaN to work around VC++
4736 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4737 // compare equal to -0.0.
4738 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4739 match(ConD);
4740
4741 format %{ %}
4742 interface(CONST_INTER);
4743 %}
4744
4745 // Float Immediate zero
4746 operand immF0() %{
4747 predicate(UseSSE == 0 && n->getf() == 0.0F);
4748 match(ConF);
4749
4750 op_cost(5);
4751 format %{ %}
4752 interface(CONST_INTER);
4753 %}
4754
4755 // Float Immediate one
4756 operand immF1() %{
4757 predicate(UseSSE == 0 && n->getf() == 1.0F);
4758 match(ConF);
4759
4760 op_cost(5);
4761 format %{ %}
4762 interface(CONST_INTER);
4763 %}
4764
4765 // Float Immediate
4766 operand immF() %{
4767 predicate( UseSSE == 0 );
4768 match(ConF);
4769
4770 op_cost(5);
4771 format %{ %}
4772 interface(CONST_INTER);
4773 %}
4774
4775 // Float Immediate
4776 operand immXF() %{
4777 predicate(UseSSE >= 1);
4778 match(ConF);
4779
4780 op_cost(5);
4781 format %{ %}
4782 interface(CONST_INTER);
4783 %}
4784
4785 // Float Immediate zero. Zero and not -0.0
4786 operand immXF0() %{
4787 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4788 match(ConF);
4789
4790 op_cost(5);
4791 format %{ %}
4792 interface(CONST_INTER);
4793 %}
4794
4795 // Immediates for special shifts (sign extend)
4796
4797 // Constants for increment
4798 operand immI_16() %{
4799 predicate( n->get_int() == 16 );
4800 match(ConI);
4801
4802 format %{ %}
4803 interface(CONST_INTER);
4804 %}
4805
4806 operand immI_24() %{
4807 predicate( n->get_int() == 24 );
4808 match(ConI);
4809
4810 format %{ %}
4811 interface(CONST_INTER);
4812 %}
4813
4814 // Constant for byte-wide masking
4815 operand immI_255() %{
4816 predicate( n->get_int() == 255 );
4817 match(ConI);
4818
4819 format %{ %}
4820 interface(CONST_INTER);
4821 %}
4822
4823 // Constant for short-wide masking
4824 operand immI_65535() %{
4825 predicate(n->get_int() == 65535);
4826 match(ConI);
4827
4828 format %{ %}
4829 interface(CONST_INTER);
4830 %}
4831
4832 // Register Operands
4833 // Integer Register
4834 operand eRegI() %{
4835 constraint(ALLOC_IN_RC(e_reg));
4836 match(RegI);
4837 match(xRegI);
4838 match(eAXRegI);
4839 match(eBXRegI);
4840 match(eCXRegI);
4841 match(eDXRegI);
4842 match(eDIRegI);
4843 match(eSIRegI);
4844
4845 format %{ %}
4846 interface(REG_INTER);
4847 %}
4848
4849 // Subset of Integer Register
4850 operand xRegI(eRegI reg) %{
4851 constraint(ALLOC_IN_RC(x_reg));
4852 match(reg);
4853 match(eAXRegI);
4854 match(eBXRegI);
4855 match(eCXRegI);
4856 match(eDXRegI);
4857
4858 format %{ %}
4859 interface(REG_INTER);
4860 %}
4861
4862 // Special Registers
4863 operand eAXRegI(xRegI reg) %{
4864 constraint(ALLOC_IN_RC(eax_reg));
4865 match(reg);
4866 match(eRegI);
4867
4868 format %{ "EAX" %}
4869 interface(REG_INTER);
4870 %}
4871
4872 // Special Registers
4873 operand eBXRegI(xRegI reg) %{
4874 constraint(ALLOC_IN_RC(ebx_reg));
4875 match(reg);
4876 match(eRegI);
4877
4878 format %{ "EBX" %}
4879 interface(REG_INTER);
4880 %}
4881
4882 operand eCXRegI(xRegI reg) %{
4883 constraint(ALLOC_IN_RC(ecx_reg));
4884 match(reg);
4885 match(eRegI);
4886
4887 format %{ "ECX" %}
4888 interface(REG_INTER);
4889 %}
4890
4891 operand eDXRegI(xRegI reg) %{
4892 constraint(ALLOC_IN_RC(edx_reg));
4893 match(reg);
4894 match(eRegI);
4895
4896 format %{ "EDX" %}
4897 interface(REG_INTER);
4898 %}
4899
4900 operand eDIRegI(xRegI reg) %{
4901 constraint(ALLOC_IN_RC(edi_reg));
4902 match(reg);
4903 match(eRegI);
4904
4905 format %{ "EDI" %}
4906 interface(REG_INTER);
4907 %}
4908
4909 operand naxRegI() %{
4910 constraint(ALLOC_IN_RC(nax_reg));
4911 match(RegI);
4912 match(eCXRegI);
4913 match(eDXRegI);
4914 match(eSIRegI);
4915 match(eDIRegI);
4916
4917 format %{ %}
4918 interface(REG_INTER);
4919 %}
4920
4921 operand nadxRegI() %{
4922 constraint(ALLOC_IN_RC(nadx_reg));
4923 match(RegI);
4924 match(eBXRegI);
4925 match(eCXRegI);
4926 match(eSIRegI);
4927 match(eDIRegI);
4928
4929 format %{ %}
4930 interface(REG_INTER);
4931 %}
4932
4933 operand ncxRegI() %{
4934 constraint(ALLOC_IN_RC(ncx_reg));
4935 match(RegI);
4936 match(eAXRegI);
4937 match(eDXRegI);
4938 match(eSIRegI);
4939 match(eDIRegI);
4940
4941 format %{ %}
4942 interface(REG_INTER);
4943 %}
4944
4945 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4946 // //
4947 operand eSIRegI(xRegI reg) %{
4948 constraint(ALLOC_IN_RC(esi_reg));
4949 match(reg);
4950 match(eRegI);
4951
4952 format %{ "ESI" %}
4953 interface(REG_INTER);
4954 %}
4955
4956 // Pointer Register
4957 operand anyRegP() %{
4958 constraint(ALLOC_IN_RC(any_reg));
4959 match(RegP);
4960 match(eAXRegP);
4961 match(eBXRegP);
4962 match(eCXRegP);
4963 match(eDIRegP);
4964 match(eRegP);
4965
4966 format %{ %}
4967 interface(REG_INTER);
4968 %}
4969
4970 operand eRegP() %{
4971 constraint(ALLOC_IN_RC(e_reg));
4972 match(RegP);
4973 match(eAXRegP);
4974 match(eBXRegP);
4975 match(eCXRegP);
4976 match(eDIRegP);
4977
4978 format %{ %}
4979 interface(REG_INTER);
4980 %}
4981
4982 // On windows95, EBP is not safe to use for implicit null tests.
4983 operand eRegP_no_EBP() %{
4984 constraint(ALLOC_IN_RC(e_reg_no_rbp));
4985 match(RegP);
4986 match(eAXRegP);
4987 match(eBXRegP);
4988 match(eCXRegP);
4989 match(eDIRegP);
4990
4991 op_cost(100);
4992 format %{ %}
4993 interface(REG_INTER);
4994 %}
4995
4996 operand naxRegP() %{
4997 constraint(ALLOC_IN_RC(nax_reg));
4998 match(RegP);
4999 match(eBXRegP);
5000 match(eDXRegP);
5001 match(eCXRegP);
5002 match(eSIRegP);
5003 match(eDIRegP);
5004
5005 format %{ %}
5006 interface(REG_INTER);
5007 %}
5008
5009 operand nabxRegP() %{
5010 constraint(ALLOC_IN_RC(nabx_reg));
5011 match(RegP);
5012 match(eCXRegP);
5013 match(eDXRegP);
5014 match(eSIRegP);
5015 match(eDIRegP);
5016
5017 format %{ %}
5018 interface(REG_INTER);
5019 %}
5020
5021 operand pRegP() %{
5022 constraint(ALLOC_IN_RC(p_reg));
5023 match(RegP);
5024 match(eBXRegP);
5025 match(eDXRegP);
5026 match(eSIRegP);
5027 match(eDIRegP);
5028
5029 format %{ %}
5030 interface(REG_INTER);
5031 %}
5032
5033 // Special Registers
5034 // Return a pointer value
5035 operand eAXRegP(eRegP reg) %{
5036 constraint(ALLOC_IN_RC(eax_reg));
5037 match(reg);
5038 format %{ "EAX" %}
5039 interface(REG_INTER);
5040 %}
5041
5042 // Used in AtomicAdd
5043 operand eBXRegP(eRegP reg) %{
5044 constraint(ALLOC_IN_RC(ebx_reg));
5045 match(reg);
5046 format %{ "EBX" %}
5047 interface(REG_INTER);
5048 %}
5049
5050 // Tail-call (interprocedural jump) to interpreter
5051 operand eCXRegP(eRegP reg) %{
5052 constraint(ALLOC_IN_RC(ecx_reg));
5053 match(reg);
5054 format %{ "ECX" %}
5055 interface(REG_INTER);
5056 %}
5057
5058 operand eSIRegP(eRegP reg) %{
5059 constraint(ALLOC_IN_RC(esi_reg));
5060 match(reg);
5061 format %{ "ESI" %}
5062 interface(REG_INTER);
5063 %}
5064
5065 // Used in rep stosw
5066 operand eDIRegP(eRegP reg) %{
5067 constraint(ALLOC_IN_RC(edi_reg));
5068 match(reg);
5069 format %{ "EDI" %}
5070 interface(REG_INTER);
5071 %}
5072
5073 operand eBPRegP() %{
5074 constraint(ALLOC_IN_RC(ebp_reg));
5075 match(RegP);
5076 format %{ "EBP" %}
5077 interface(REG_INTER);
5078 %}
5079
5080 operand eRegL() %{
5081 constraint(ALLOC_IN_RC(long_reg));
5082 match(RegL);
5083 match(eADXRegL);
5084
5085 format %{ %}
5086 interface(REG_INTER);
5087 %}
5088
5089 operand eADXRegL( eRegL reg ) %{
5090 constraint(ALLOC_IN_RC(eadx_reg));
5091 match(reg);
5092
5093 format %{ "EDX:EAX" %}
5094 interface(REG_INTER);
5095 %}
5096
5097 operand eBCXRegL( eRegL reg ) %{
5098 constraint(ALLOC_IN_RC(ebcx_reg));
5099 match(reg);
5100
5101 format %{ "EBX:ECX" %}
5102 interface(REG_INTER);
5103 %}
5104
5105 // Special case for integer high multiply
5106 operand eADXRegL_low_only() %{
5107 constraint(ALLOC_IN_RC(eadx_reg));
5108 match(RegL);
5109
5110 format %{ "EAX" %}
5111 interface(REG_INTER);
5112 %}
5113
5114 // Flags register, used as output of compare instructions
5115 operand eFlagsReg() %{
5116 constraint(ALLOC_IN_RC(int_flags));
5117 match(RegFlags);
5118
5119 format %{ "EFLAGS" %}
5120 interface(REG_INTER);
5121 %}
5122
5123 // Flags register, used as output of FLOATING POINT compare instructions
5124 operand eFlagsRegU() %{
5125 constraint(ALLOC_IN_RC(int_flags));
5126 match(RegFlags);
5127
5128 format %{ "EFLAGS_U" %}
5129 interface(REG_INTER);
5130 %}
5131
5132 operand eFlagsRegUCF() %{
5133 constraint(ALLOC_IN_RC(int_flags));
5134 match(RegFlags);
5135 predicate(false);
5136
5137 format %{ "EFLAGS_U_CF" %}
5138 interface(REG_INTER);
5139 %}
5140
5141 // Condition Code Register used by long compare
5142 operand flagsReg_long_LTGE() %{
5143 constraint(ALLOC_IN_RC(int_flags));
5144 match(RegFlags);
5145 format %{ "FLAGS_LTGE" %}
5146 interface(REG_INTER);
5147 %}
5148 operand flagsReg_long_EQNE() %{
5149 constraint(ALLOC_IN_RC(int_flags));
5150 match(RegFlags);
5151 format %{ "FLAGS_EQNE" %}
5152 interface(REG_INTER);
5153 %}
5154 operand flagsReg_long_LEGT() %{
5155 constraint(ALLOC_IN_RC(int_flags));
5156 match(RegFlags);
5157 format %{ "FLAGS_LEGT" %}
5158 interface(REG_INTER);
5159 %}
5160
5161 // Float register operands
5162 operand regD() %{
5163 predicate( UseSSE < 2 );
5164 constraint(ALLOC_IN_RC(dbl_reg));
5165 match(RegD);
5166 match(regDPR1);
5167 match(regDPR2);
5168 format %{ %}
5169 interface(REG_INTER);
5170 %}
5171
5172 operand regDPR1(regD reg) %{
5173 predicate( UseSSE < 2 );
5174 constraint(ALLOC_IN_RC(dbl_reg0));
5175 match(reg);
5176 format %{ "FPR1" %}
5177 interface(REG_INTER);
5178 %}
5179
5180 operand regDPR2(regD reg) %{
5181 predicate( UseSSE < 2 );
5182 constraint(ALLOC_IN_RC(dbl_reg1));
5183 match(reg);
5184 format %{ "FPR2" %}
5185 interface(REG_INTER);
5186 %}
5187
5188 operand regnotDPR1(regD reg) %{
5189 predicate( UseSSE < 2 );
5190 constraint(ALLOC_IN_RC(dbl_notreg0));
5191 match(reg);
5192 format %{ %}
5193 interface(REG_INTER);
5194 %}
5195
5196 // XMM Double register operands
5197 operand regXD() %{
5198 predicate( UseSSE>=2 );
5199 constraint(ALLOC_IN_RC(xdb_reg));
5200 match(RegD);
5201 match(regXD6);
5202 match(regXD7);
5203 format %{ %}
5204 interface(REG_INTER);
5205 %}
5206
5207 // XMM6 double register operands
5208 operand regXD6(regXD reg) %{
5209 predicate( UseSSE>=2 );
5210 constraint(ALLOC_IN_RC(xdb_reg6));
5211 match(reg);
5212 format %{ "XMM6" %}
5213 interface(REG_INTER);
5214 %}
5215
5216 // XMM7 double register operands
5217 operand regXD7(regXD reg) %{
5218 predicate( UseSSE>=2 );
5219 constraint(ALLOC_IN_RC(xdb_reg7));
5220 match(reg);
5221 format %{ "XMM7" %}
5222 interface(REG_INTER);
5223 %}
5224
5225 // Float register operands
5226 operand regF() %{
5227 predicate( UseSSE < 2 );
5228 constraint(ALLOC_IN_RC(flt_reg));
5229 match(RegF);
5230 match(regFPR1);
5231 format %{ %}
5232 interface(REG_INTER);
5233 %}
5234
5235 // Float register operands
5236 operand regFPR1(regF reg) %{
5237 predicate( UseSSE < 2 );
5238 constraint(ALLOC_IN_RC(flt_reg0));
5239 match(reg);
5240 format %{ "FPR1" %}
5241 interface(REG_INTER);
5242 %}
5243
5244 // XMM register operands
5245 operand regX() %{
5246 predicate( UseSSE>=1 );
5247 constraint(ALLOC_IN_RC(xmm_reg));
5248 match(RegF);
5249 format %{ %}
5250 interface(REG_INTER);
5251 %}
5252
5253
5254 //----------Memory Operands----------------------------------------------------
5255 // Direct Memory Operand
5256 operand direct(immP addr) %{
5257 match(addr);
5258
5259 format %{ "[$addr]" %}
5260 interface(MEMORY_INTER) %{
5261 base(0xFFFFFFFF);
5262 index(0x4);
5263 scale(0x0);
5264 disp($addr);
5265 %}
5266 %}
5267
5268 // Indirect Memory Operand
5269 operand indirect(eRegP reg) %{
5270 constraint(ALLOC_IN_RC(e_reg));
5271 match(reg);
5272
5273 format %{ "[$reg]" %}
5274 interface(MEMORY_INTER) %{
5275 base($reg);
5276 index(0x4);
5277 scale(0x0);
5278 disp(0x0);
5279 %}
5280 %}
5281
5282 // Indirect Memory Plus Short Offset Operand
5283 operand indOffset8(eRegP reg, immI8 off) %{
5284 match(AddP reg off);
5285
5286 format %{ "[$reg + $off]" %}
5287 interface(MEMORY_INTER) %{
5288 base($reg);
5289 index(0x4);
5290 scale(0x0);
5291 disp($off);
5292 %}
5293 %}
5294
5295 // Indirect Memory Plus Long Offset Operand
5296 operand indOffset32(eRegP reg, immI off) %{
5297 match(AddP reg off);
5298
5299 format %{ "[$reg + $off]" %}
5300 interface(MEMORY_INTER) %{
5301 base($reg);
5302 index(0x4);
5303 scale(0x0);
5304 disp($off);
5305 %}
5306 %}
5307
5308 // Indirect Memory Plus Long Offset Operand
5309 operand indOffset32X(eRegI reg, immP off) %{
5310 match(AddP off reg);
5311
5312 format %{ "[$reg + $off]" %}
5313 interface(MEMORY_INTER) %{
5314 base($reg);
5315 index(0x4);
5316 scale(0x0);
5317 disp($off);
5318 %}
5319 %}
5320
5321 // Indirect Memory Plus Index Register Plus Offset Operand
5322 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5323 match(AddP (AddP reg ireg) off);
5324
5325 op_cost(10);
5326 format %{"[$reg + $off + $ireg]" %}
5327 interface(MEMORY_INTER) %{
5328 base($reg);
5329 index($ireg);
5330 scale(0x0);
5331 disp($off);
5332 %}
5333 %}
5334
5335 // Indirect Memory Plus Index Register Plus Offset Operand
5336 operand indIndex(eRegP reg, eRegI ireg) %{
5337 match(AddP reg ireg);
5338
5339 op_cost(10);
5340 format %{"[$reg + $ireg]" %}
5341 interface(MEMORY_INTER) %{
5342 base($reg);
5343 index($ireg);
5344 scale(0x0);
5345 disp(0x0);
5346 %}
5347 %}
5348
5349 // // -------------------------------------------------------------------------
5350 // // 486 architecture doesn't support "scale * index + offset" with out a base
5351 // // -------------------------------------------------------------------------
5352 // // Scaled Memory Operands
5353 // // Indirect Memory Times Scale Plus Offset Operand
5354 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5355 // match(AddP off (LShiftI ireg scale));
5356 //
5357 // op_cost(10);
5358 // format %{"[$off + $ireg << $scale]" %}
5359 // interface(MEMORY_INTER) %{
5360 // base(0x4);
5361 // index($ireg);
5362 // scale($scale);
5363 // disp($off);
5364 // %}
5365 // %}
5366
5367 // Indirect Memory Times Scale Plus Index Register
5368 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5369 match(AddP reg (LShiftI ireg scale));
5370
5371 op_cost(10);
5372 format %{"[$reg + $ireg << $scale]" %}
5373 interface(MEMORY_INTER) %{
5374 base($reg);
5375 index($ireg);
5376 scale($scale);
5377 disp(0x0);
5378 %}
5379 %}
5380
5381 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5382 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5383 match(AddP (AddP reg (LShiftI ireg scale)) off);
5384
5385 op_cost(10);
5386 format %{"[$reg + $off + $ireg << $scale]" %}
5387 interface(MEMORY_INTER) %{
5388 base($reg);
5389 index($ireg);
5390 scale($scale);
5391 disp($off);
5392 %}
5393 %}
5394
5395 //----------Load Long Memory Operands------------------------------------------
5396 // The load-long idiom will use it's address expression again after loading
5397 // the first word of the long. If the load-long destination overlaps with
5398 // registers used in the addressing expression, the 2nd half will be loaded
5399 // from a clobbered address. Fix this by requiring that load-long use
5400 // address registers that do not overlap with the load-long target.
5401
5402 // load-long support
5403 operand load_long_RegP() %{
5404 constraint(ALLOC_IN_RC(esi_reg));
5405 match(RegP);
5406 match(eSIRegP);
5407 op_cost(100);
5408 format %{ %}
5409 interface(REG_INTER);
5410 %}
5411
5412 // Indirect Memory Operand Long
5413 operand load_long_indirect(load_long_RegP reg) %{
5414 constraint(ALLOC_IN_RC(esi_reg));
5415 match(reg);
5416
5417 format %{ "[$reg]" %}
5418 interface(MEMORY_INTER) %{
5419 base($reg);
5420 index(0x4);
5421 scale(0x0);
5422 disp(0x0);
5423 %}
5424 %}
5425
5426 // Indirect Memory Plus Long Offset Operand
5427 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5428 match(AddP reg off);
5429
5430 format %{ "[$reg + $off]" %}
5431 interface(MEMORY_INTER) %{
5432 base($reg);
5433 index(0x4);
5434 scale(0x0);
5435 disp($off);
5436 %}
5437 %}
5438
5439 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5440
5441
5442 //----------Special Memory Operands--------------------------------------------
5443 // Stack Slot Operand - This operand is used for loading and storing temporary
5444 // values on the stack where a match requires a value to
5445 // flow through memory.
5446 operand stackSlotP(sRegP reg) %{
5447 constraint(ALLOC_IN_RC(stack_slots));
5448 // No match rule because this operand is only generated in matching
5449 format %{ "[$reg]" %}
5450 interface(MEMORY_INTER) %{
5451 base(0x4); // ESP
5452 index(0x4); // No Index
5453 scale(0x0); // No Scale
5454 disp($reg); // Stack Offset
5455 %}
5456 %}
5457
5458 operand stackSlotI(sRegI reg) %{
5459 constraint(ALLOC_IN_RC(stack_slots));
5460 // No match rule because this operand is only generated in matching
5461 format %{ "[$reg]" %}
5462 interface(MEMORY_INTER) %{
5463 base(0x4); // ESP
5464 index(0x4); // No Index
5465 scale(0x0); // No Scale
5466 disp($reg); // Stack Offset
5467 %}
5468 %}
5469
5470 operand stackSlotF(sRegF reg) %{
5471 constraint(ALLOC_IN_RC(stack_slots));
5472 // No match rule because this operand is only generated in matching
5473 format %{ "[$reg]" %}
5474 interface(MEMORY_INTER) %{
5475 base(0x4); // ESP
5476 index(0x4); // No Index
5477 scale(0x0); // No Scale
5478 disp($reg); // Stack Offset
5479 %}
5480 %}
5481
5482 operand stackSlotD(sRegD reg) %{
5483 constraint(ALLOC_IN_RC(stack_slots));
5484 // No match rule because this operand is only generated in matching
5485 format %{ "[$reg]" %}
5486 interface(MEMORY_INTER) %{
5487 base(0x4); // ESP
5488 index(0x4); // No Index
5489 scale(0x0); // No Scale
5490 disp($reg); // Stack Offset
5491 %}
5492 %}
5493
5494 operand stackSlotL(sRegL reg) %{
5495 constraint(ALLOC_IN_RC(stack_slots));
5496 // No match rule because this operand is only generated in matching
5497 format %{ "[$reg]" %}
5498 interface(MEMORY_INTER) %{
5499 base(0x4); // ESP
5500 index(0x4); // No Index
5501 scale(0x0); // No Scale
5502 disp($reg); // Stack Offset
5503 %}
5504 %}
5505
5506 //----------Memory Operands - Win95 Implicit Null Variants----------------
5507 // Indirect Memory Operand
5508 operand indirect_win95_safe(eRegP_no_EBP reg)
5509 %{
5510 constraint(ALLOC_IN_RC(e_reg));
5511 match(reg);
5512
5513 op_cost(100);
5514 format %{ "[$reg]" %}
5515 interface(MEMORY_INTER) %{
5516 base($reg);
5517 index(0x4);
5518 scale(0x0);
5519 disp(0x0);
5520 %}
5521 %}
5522
5523 // Indirect Memory Plus Short Offset Operand
5524 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5525 %{
5526 match(AddP reg off);
5527
5528 op_cost(100);
5529 format %{ "[$reg + $off]" %}
5530 interface(MEMORY_INTER) %{
5531 base($reg);
5532 index(0x4);
5533 scale(0x0);
5534 disp($off);
5535 %}
5536 %}
5537
5538 // Indirect Memory Plus Long Offset Operand
5539 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5540 %{
5541 match(AddP reg off);
5542
5543 op_cost(100);
5544 format %{ "[$reg + $off]" %}
5545 interface(MEMORY_INTER) %{
5546 base($reg);
5547 index(0x4);
5548 scale(0x0);
5549 disp($off);
5550 %}
5551 %}
5552
5553 // Indirect Memory Plus Index Register Plus Offset Operand
5554 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5555 %{
5556 match(AddP (AddP reg ireg) off);
5557
5558 op_cost(100);
5559 format %{"[$reg + $off + $ireg]" %}
5560 interface(MEMORY_INTER) %{
5561 base($reg);
5562 index($ireg);
5563 scale(0x0);
5564 disp($off);
5565 %}
5566 %}
5567
5568 // Indirect Memory Times Scale Plus Index Register
5569 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5570 %{
5571 match(AddP reg (LShiftI ireg scale));
5572
5573 op_cost(100);
5574 format %{"[$reg + $ireg << $scale]" %}
5575 interface(MEMORY_INTER) %{
5576 base($reg);
5577 index($ireg);
5578 scale($scale);
5579 disp(0x0);
5580 %}
5581 %}
5582
5583 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5584 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5585 %{
5586 match(AddP (AddP reg (LShiftI ireg scale)) off);
5587
5588 op_cost(100);
5589 format %{"[$reg + $off + $ireg << $scale]" %}
5590 interface(MEMORY_INTER) %{
5591 base($reg);
5592 index($ireg);
5593 scale($scale);
5594 disp($off);
5595 %}
5596 %}
5597
5598 //----------Conditional Branch Operands----------------------------------------
5599 // Comparison Op - This is the operation of the comparison, and is limited to
5600 // the following set of codes:
5601 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5602 //
5603 // Other attributes of the comparison, such as unsignedness, are specified
5604 // by the comparison instruction that sets a condition code flags register.
5605 // That result is represented by a flags operand whose subtype is appropriate
5606 // to the unsignedness (etc.) of the comparison.
5607 //
5608 // Later, the instruction which matches both the Comparison Op (a Bool) and
5609 // the flags (produced by the Cmp) specifies the coding of the comparison op
5610 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5611
5612 // Comparision Code
5613 operand cmpOp() %{
5614 match(Bool);
5615
5616 format %{ "" %}
5617 interface(COND_INTER) %{
5618 equal(0x4, "e");
5619 not_equal(0x5, "ne");
5620 less(0xC, "l");
5621 greater_equal(0xD, "ge");
5622 less_equal(0xE, "le");
5623 greater(0xF, "g");
5624 %}
5625 %}
5626
5627 // Comparison Code, unsigned compare. Used by FP also, with
5628 // C2 (unordered) turned into GT or LT already. The other bits
5629 // C0 and C3 are turned into Carry & Zero flags.
5630 operand cmpOpU() %{
5631 match(Bool);
5632
5633 format %{ "" %}
5634 interface(COND_INTER) %{
5635 equal(0x4, "e");
5636 not_equal(0x5, "ne");
5637 less(0x2, "b");
5638 greater_equal(0x3, "nb");
5639 less_equal(0x6, "be");
5640 greater(0x7, "nbe");
5641 %}
5642 %}
5643
5644 // Floating comparisons that don't require any fixup for the unordered case
5645 operand cmpOpUCF() %{
5646 match(Bool);
5647 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5648 n->as_Bool()->_test._test == BoolTest::ge ||
5649 n->as_Bool()->_test._test == BoolTest::le ||
5650 n->as_Bool()->_test._test == BoolTest::gt);
5651 format %{ "" %}
5652 interface(COND_INTER) %{
5653 equal(0x4, "e");
5654 not_equal(0x5, "ne");
5655 less(0x2, "b");
5656 greater_equal(0x3, "nb");
5657 less_equal(0x6, "be");
5658 greater(0x7, "nbe");
5659 %}
5660 %}
5661
5662
5663 // Floating comparisons that can be fixed up with extra conditional jumps
5664 operand cmpOpUCF2() %{
5665 match(Bool);
5666 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5667 n->as_Bool()->_test._test == BoolTest::eq);
5668 format %{ "" %}
5669 interface(COND_INTER) %{
5670 equal(0x4, "e");
5671 not_equal(0x5, "ne");
5672 less(0x2, "b");
5673 greater_equal(0x3, "nb");
5674 less_equal(0x6, "be");
5675 greater(0x7, "nbe");
5676 %}
5677 %}
5678
5679 // Comparison Code for FP conditional move
5680 operand cmpOp_fcmov() %{
5681 match(Bool);
5682
5683 format %{ "" %}
5684 interface(COND_INTER) %{
5685 equal (0x0C8);
5686 not_equal (0x1C8);
5687 less (0x0C0);
5688 greater_equal(0x1C0);
5689 less_equal (0x0D0);
5690 greater (0x1D0);
5691 %}
5692 %}
5693
5694 // Comparision Code used in long compares
5695 operand cmpOp_commute() %{
5696 match(Bool);
5697
5698 format %{ "" %}
5699 interface(COND_INTER) %{
5700 equal(0x4, "e");
5701 not_equal(0x5, "ne");
5702 less(0xF, "g");
5703 greater_equal(0xE, "le");
5704 less_equal(0xD, "ge");
5705 greater(0xC, "l");
5706 %}
5707 %}
5708
5709 //----------OPERAND CLASSES----------------------------------------------------
5710 // Operand Classes are groups of operands that are used as to simplify
5711 // instruction definitions by not requiring the AD writer to specify separate
5712 // instructions for every form of operand when the instruction accepts
5713 // multiple operand types with the same basic encoding and format. The classic
5714 // case of this is memory operands.
5715
5716 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5717 indIndex, indIndexScale, indIndexScaleOffset);
5718
5719 // Long memory operations are encoded in 2 instructions and a +4 offset.
5720 // This means some kind of offset is always required and you cannot use
5721 // an oop as the offset (done when working on static globals).
5722 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5723 indIndex, indIndexScale, indIndexScaleOffset);
5724
5725
5726 //----------PIPELINE-----------------------------------------------------------
5727 // Rules which define the behavior of the target architectures pipeline.
5728 pipeline %{
5729
5730 //----------ATTRIBUTES---------------------------------------------------------
5731 attributes %{
5732 variable_size_instructions; // Fixed size instructions
5733 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5734 instruction_unit_size = 1; // An instruction is 1 bytes long
5735 instruction_fetch_unit_size = 16; // The processor fetches one line
5736 instruction_fetch_units = 1; // of 16 bytes
5737
5738 // List of nop instructions
5739 nops( MachNop );
5740 %}
5741
5742 //----------RESOURCES----------------------------------------------------------
5743 // Resources are the functional units available to the machine
5744
5745 // Generic P2/P3 pipeline
5746 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5747 // 3 instructions decoded per cycle.
5748 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5749 // 2 ALU op, only ALU0 handles mul/div instructions.
5750 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5751 MS0, MS1, MEM = MS0 | MS1,
5752 BR, FPU,
5753 ALU0, ALU1, ALU = ALU0 | ALU1 );
5754
5755 //----------PIPELINE DESCRIPTION-----------------------------------------------
5756 // Pipeline Description specifies the stages in the machine's pipeline
5757
5758 // Generic P2/P3 pipeline
5759 pipe_desc(S0, S1, S2, S3, S4, S5);
5760
5761 //----------PIPELINE CLASSES---------------------------------------------------
5762 // Pipeline Classes describe the stages in which input and output are
5763 // referenced by the hardware pipeline.
5764
5765 // Naming convention: ialu or fpu
5766 // Then: _reg
5767 // Then: _reg if there is a 2nd register
5768 // Then: _long if it's a pair of instructions implementing a long
5769 // Then: _fat if it requires the big decoder
5770 // Or: _mem if it requires the big decoder and a memory unit.
5771
5772 // Integer ALU reg operation
5773 pipe_class ialu_reg(eRegI dst) %{
5774 single_instruction;
5775 dst : S4(write);
5776 dst : S3(read);
5777 DECODE : S0; // any decoder
5778 ALU : S3; // any alu
5779 %}
5780
5781 // Long ALU reg operation
5782 pipe_class ialu_reg_long(eRegL dst) %{
5783 instruction_count(2);
5784 dst : S4(write);
5785 dst : S3(read);
5786 DECODE : S0(2); // any 2 decoders
5787 ALU : S3(2); // both alus
5788 %}
5789
5790 // Integer ALU reg operation using big decoder
5791 pipe_class ialu_reg_fat(eRegI dst) %{
5792 single_instruction;
5793 dst : S4(write);
5794 dst : S3(read);
5795 D0 : S0; // big decoder only
5796 ALU : S3; // any alu
5797 %}
5798
5799 // Long ALU reg operation using big decoder
5800 pipe_class ialu_reg_long_fat(eRegL dst) %{
5801 instruction_count(2);
5802 dst : S4(write);
5803 dst : S3(read);
5804 D0 : S0(2); // big decoder only; twice
5805 ALU : S3(2); // any 2 alus
5806 %}
5807
5808 // Integer ALU reg-reg operation
5809 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5810 single_instruction;
5811 dst : S4(write);
5812 src : S3(read);
5813 DECODE : S0; // any decoder
5814 ALU : S3; // any alu
5815 %}
5816
5817 // Long ALU reg-reg operation
5818 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5819 instruction_count(2);
5820 dst : S4(write);
5821 src : S3(read);
5822 DECODE : S0(2); // any 2 decoders
5823 ALU : S3(2); // both alus
5824 %}
5825
5826 // Integer ALU reg-reg operation
5827 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5828 single_instruction;
5829 dst : S4(write);
5830 src : S3(read);
5831 D0 : S0; // big decoder only
5832 ALU : S3; // any alu
5833 %}
5834
5835 // Long ALU reg-reg operation
5836 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5837 instruction_count(2);
5838 dst : S4(write);
5839 src : S3(read);
5840 D0 : S0(2); // big decoder only; twice
5841 ALU : S3(2); // both alus
5842 %}
5843
5844 // Integer ALU reg-mem operation
5845 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5846 single_instruction;
5847 dst : S5(write);
5848 mem : S3(read);
5849 D0 : S0; // big decoder only
5850 ALU : S4; // any alu
5851 MEM : S3; // any mem
5852 %}
5853
5854 // Long ALU reg-mem operation
5855 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5856 instruction_count(2);
5857 dst : S5(write);
5858 mem : S3(read);
5859 D0 : S0(2); // big decoder only; twice
5860 ALU : S4(2); // any 2 alus
5861 MEM : S3(2); // both mems
5862 %}
5863
5864 // Integer mem operation (prefetch)
5865 pipe_class ialu_mem(memory mem)
5866 %{
5867 single_instruction;
5868 mem : S3(read);
5869 D0 : S0; // big decoder only
5870 MEM : S3; // any mem
5871 %}
5872
5873 // Integer Store to Memory
5874 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5875 single_instruction;
5876 mem : S3(read);
5877 src : S5(read);
5878 D0 : S0; // big decoder only
5879 ALU : S4; // any alu
5880 MEM : S3;
5881 %}
5882
5883 // Long Store to Memory
5884 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5885 instruction_count(2);
5886 mem : S3(read);
5887 src : S5(read);
5888 D0 : S0(2); // big decoder only; twice
5889 ALU : S4(2); // any 2 alus
5890 MEM : S3(2); // Both mems
5891 %}
5892
5893 // Integer Store to Memory
5894 pipe_class ialu_mem_imm(memory mem) %{
5895 single_instruction;
5896 mem : S3(read);
5897 D0 : S0; // big decoder only
5898 ALU : S4; // any alu
5899 MEM : S3;
5900 %}
5901
5902 // Integer ALU0 reg-reg operation
5903 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5904 single_instruction;
5905 dst : S4(write);
5906 src : S3(read);
5907 D0 : S0; // Big decoder only
5908 ALU0 : S3; // only alu0
5909 %}
5910
5911 // Integer ALU0 reg-mem operation
5912 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5913 single_instruction;
5914 dst : S5(write);
5915 mem : S3(read);
5916 D0 : S0; // big decoder only
5917 ALU0 : S4; // ALU0 only
5918 MEM : S3; // any mem
5919 %}
5920
5921 // Integer ALU reg-reg operation
5922 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
5923 single_instruction;
5924 cr : S4(write);
5925 src1 : S3(read);
5926 src2 : S3(read);
5927 DECODE : S0; // any decoder
5928 ALU : S3; // any alu
5929 %}
5930
5931 // Integer ALU reg-imm operation
5932 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
5933 single_instruction;
5934 cr : S4(write);
5935 src1 : S3(read);
5936 DECODE : S0; // any decoder
5937 ALU : S3; // any alu
5938 %}
5939
5940 // Integer ALU reg-mem operation
5941 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
5942 single_instruction;
5943 cr : S4(write);
5944 src1 : S3(read);
5945 src2 : S3(read);
5946 D0 : S0; // big decoder only
5947 ALU : S4; // any alu
5948 MEM : S3;
5949 %}
5950
5951 // Conditional move reg-reg
5952 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
5953 instruction_count(4);
5954 y : S4(read);
5955 q : S3(read);
5956 p : S3(read);
5957 DECODE : S0(4); // any decoder
5958 %}
5959
5960 // Conditional move reg-reg
5961 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
5962 single_instruction;
5963 dst : S4(write);
5964 src : S3(read);
5965 cr : S3(read);
5966 DECODE : S0; // any decoder
5967 %}
5968
5969 // Conditional move reg-mem
5970 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
5971 single_instruction;
5972 dst : S4(write);
5973 src : S3(read);
5974 cr : S3(read);
5975 DECODE : S0; // any decoder
5976 MEM : S3;
5977 %}
5978
5979 // Conditional move reg-reg long
5980 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5981 single_instruction;
5982 dst : S4(write);
5983 src : S3(read);
5984 cr : S3(read);
5985 DECODE : S0(2); // any 2 decoders
5986 %}
5987
5988 // Conditional move double reg-reg
5989 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
5990 single_instruction;
5991 dst : S4(write);
5992 src : S3(read);
5993 cr : S3(read);
5994 DECODE : S0; // any decoder
5995 %}
5996
5997 // Float reg-reg operation
5998 pipe_class fpu_reg(regD dst) %{
5999 instruction_count(2);
6000 dst : S3(read);
6001 DECODE : S0(2); // any 2 decoders
6002 FPU : S3;
6003 %}
6004
6005 // Float reg-reg operation
6006 pipe_class fpu_reg_reg(regD dst, regD src) %{
6007 instruction_count(2);
6008 dst : S4(write);
6009 src : S3(read);
6010 DECODE : S0(2); // any 2 decoders
6011 FPU : S3;
6012 %}
6013
6014 // Float reg-reg operation
6015 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6016 instruction_count(3);
6017 dst : S4(write);
6018 src1 : S3(read);
6019 src2 : S3(read);
6020 DECODE : S0(3); // any 3 decoders
6021 FPU : S3(2);
6022 %}
6023
6024 // Float reg-reg operation
6025 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6026 instruction_count(4);
6027 dst : S4(write);
6028 src1 : S3(read);
6029 src2 : S3(read);
6030 src3 : S3(read);
6031 DECODE : S0(4); // any 3 decoders
6032 FPU : S3(2);
6033 %}
6034
6035 // Float reg-reg operation
6036 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6037 instruction_count(4);
6038 dst : S4(write);
6039 src1 : S3(read);
6040 src2 : S3(read);
6041 src3 : S3(read);
6042 DECODE : S1(3); // any 3 decoders
6043 D0 : S0; // Big decoder only
6044 FPU : S3(2);
6045 MEM : S3;
6046 %}
6047
6048 // Float reg-mem operation
6049 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6050 instruction_count(2);
6051 dst : S5(write);
6052 mem : S3(read);
6053 D0 : S0; // big decoder only
6054 DECODE : S1; // any decoder for FPU POP
6055 FPU : S4;
6056 MEM : S3; // any mem
6057 %}
6058
6059 // Float reg-mem operation
6060 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6061 instruction_count(3);
6062 dst : S5(write);
6063 src1 : S3(read);
6064 mem : S3(read);
6065 D0 : S0; // big decoder only
6066 DECODE : S1(2); // any decoder for FPU POP
6067 FPU : S4;
6068 MEM : S3; // any mem
6069 %}
6070
6071 // Float mem-reg operation
6072 pipe_class fpu_mem_reg(memory mem, regD src) %{
6073 instruction_count(2);
6074 src : S5(read);
6075 mem : S3(read);
6076 DECODE : S0; // any decoder for FPU PUSH
6077 D0 : S1; // big decoder only
6078 FPU : S4;
6079 MEM : S3; // any mem
6080 %}
6081
6082 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6083 instruction_count(3);
6084 src1 : S3(read);
6085 src2 : S3(read);
6086 mem : S3(read);
6087 DECODE : S0(2); // any decoder for FPU PUSH
6088 D0 : S1; // big decoder only
6089 FPU : S4;
6090 MEM : S3; // any mem
6091 %}
6092
6093 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6094 instruction_count(3);
6095 src1 : S3(read);
6096 src2 : S3(read);
6097 mem : S4(read);
6098 DECODE : S0; // any decoder for FPU PUSH
6099 D0 : S0(2); // big decoder only
6100 FPU : S4;
6101 MEM : S3(2); // any mem
6102 %}
6103
6104 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6105 instruction_count(2);
6106 src1 : S3(read);
6107 dst : S4(read);
6108 D0 : S0(2); // big decoder only
6109 MEM : S3(2); // any mem
6110 %}
6111
6112 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6113 instruction_count(3);
6114 src1 : S3(read);
6115 src2 : S3(read);
6116 dst : S4(read);
6117 D0 : S0(3); // big decoder only
6118 FPU : S4;
6119 MEM : S3(3); // any mem
6120 %}
6121
6122 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6123 instruction_count(3);
6124 src1 : S4(read);
6125 mem : S4(read);
6126 DECODE : S0; // any decoder for FPU PUSH
6127 D0 : S0(2); // big decoder only
6128 FPU : S4;
6129 MEM : S3(2); // any mem
6130 %}
6131
6132 // Float load constant
6133 pipe_class fpu_reg_con(regD dst) %{
6134 instruction_count(2);
6135 dst : S5(write);
6136 D0 : S0; // big decoder only for the load
6137 DECODE : S1; // any decoder for FPU POP
6138 FPU : S4;
6139 MEM : S3; // any mem
6140 %}
6141
6142 // Float load constant
6143 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6144 instruction_count(3);
6145 dst : S5(write);
6146 src : S3(read);
6147 D0 : S0; // big decoder only for the load
6148 DECODE : S1(2); // any decoder for FPU POP
6149 FPU : S4;
6150 MEM : S3; // any mem
6151 %}
6152
6153 // UnConditional branch
6154 pipe_class pipe_jmp( label labl ) %{
6155 single_instruction;
6156 BR : S3;
6157 %}
6158
6159 // Conditional branch
6160 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6161 single_instruction;
6162 cr : S1(read);
6163 BR : S3;
6164 %}
6165
6166 // Allocation idiom
6167 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6168 instruction_count(1); force_serialization;
6169 fixed_latency(6);
6170 heap_ptr : S3(read);
6171 DECODE : S0(3);
6172 D0 : S2;
6173 MEM : S3;
6174 ALU : S3(2);
6175 dst : S5(write);
6176 BR : S5;
6177 %}
6178
6179 // Generic big/slow expanded idiom
6180 pipe_class pipe_slow( ) %{
6181 instruction_count(10); multiple_bundles; force_serialization;
6182 fixed_latency(100);
6183 D0 : S0(2);
6184 MEM : S3(2);
6185 %}
6186
6187 // The real do-nothing guy
6188 pipe_class empty( ) %{
6189 instruction_count(0);
6190 %}
6191
6192 // Define the class for the Nop node
6193 define %{
6194 MachNop = empty;
6195 %}
6196
6197 %}
6198
6199 //----------INSTRUCTIONS-------------------------------------------------------
6200 //
6201 // match -- States which machine-independent subtree may be replaced
6202 // by this instruction.
6203 // ins_cost -- The estimated cost of this instruction is used by instruction
6204 // selection to identify a minimum cost tree of machine
6205 // instructions that matches a tree of machine-independent
6206 // instructions.
6207 // format -- A string providing the disassembly for this instruction.
6208 // The value of an instruction's operand may be inserted
6209 // by referring to it with a '$' prefix.
6210 // opcode -- Three instruction opcodes may be provided. These are referred
6211 // to within an encode class as $primary, $secondary, and $tertiary
6212 // respectively. The primary opcode is commonly used to
6213 // indicate the type of machine instruction, while secondary
6214 // and tertiary are often used for prefix options or addressing
6215 // modes.
6216 // ins_encode -- A list of encode classes with parameters. The encode class
6217 // name must have been defined in an 'enc_class' specification
6218 // in the encode section of the architecture description.
6219
6220 //----------BSWAP-Instruction--------------------------------------------------
6221 instruct bytes_reverse_int(eRegI dst) %{
6222 match(Set dst (ReverseBytesI dst));
6223
6224 format %{ "BSWAP $dst" %}
6225 opcode(0x0F, 0xC8);
6226 ins_encode( OpcP, OpcSReg(dst) );
6227 ins_pipe( ialu_reg );
6228 %}
6229
6230 instruct bytes_reverse_long(eRegL dst) %{
6231 match(Set dst (ReverseBytesL dst));
6232
6233 format %{ "BSWAP $dst.lo\n\t"
6234 "BSWAP $dst.hi\n\t"
6235 "XCHG $dst.lo $dst.hi" %}
6236
6237 ins_cost(125);
6238 ins_encode( bswap_long_bytes(dst) );
6239 ins_pipe( ialu_reg_reg);
6240 %}
6241
6242 instruct bytes_reverse_unsigned_short(eRegI dst) %{
6243 match(Set dst (ReverseBytesUS dst));
6244
6245 format %{ "BSWAP $dst\n\t"
6246 "SHR $dst,16\n\t" %}
6247 ins_encode %{
6248 __ bswapl($dst$$Register);
6249 __ shrl($dst$$Register, 16);
6250 %}
6251 ins_pipe( ialu_reg );
6252 %}
6253
6254 instruct bytes_reverse_short(eRegI dst) %{
6255 match(Set dst (ReverseBytesS dst));
6256
6257 format %{ "BSWAP $dst\n\t"
6258 "SAR $dst,16\n\t" %}
6259 ins_encode %{
6260 __ bswapl($dst$$Register);
6261 __ sarl($dst$$Register, 16);
6262 %}
6263 ins_pipe( ialu_reg );
6264 %}
6265
6266
6267 //---------- Zeros Count Instructions ------------------------------------------
6268
6269 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6270 predicate(UseCountLeadingZerosInstruction);
6271 match(Set dst (CountLeadingZerosI src));
6272 effect(KILL cr);
6273
6274 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6275 ins_encode %{
6276 __ lzcntl($dst$$Register, $src$$Register);
6277 %}
6278 ins_pipe(ialu_reg);
6279 %}
6280
6281 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6282 predicate(!UseCountLeadingZerosInstruction);
6283 match(Set dst (CountLeadingZerosI src));
6284 effect(KILL cr);
6285
6286 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6287 "JNZ skip\n\t"
6288 "MOV $dst, -1\n"
6289 "skip:\n\t"
6290 "NEG $dst\n\t"
6291 "ADD $dst, 31" %}
6292 ins_encode %{
6293 Register Rdst = $dst$$Register;
6294 Register Rsrc = $src$$Register;
6295 Label skip;
6296 __ bsrl(Rdst, Rsrc);
6297 __ jccb(Assembler::notZero, skip);
6298 __ movl(Rdst, -1);
6299 __ bind(skip);
6300 __ negl(Rdst);
6301 __ addl(Rdst, BitsPerInt - 1);
6302 %}
6303 ins_pipe(ialu_reg);
6304 %}
6305
6306 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6307 predicate(UseCountLeadingZerosInstruction);
6308 match(Set dst (CountLeadingZerosL src));
6309 effect(TEMP dst, KILL cr);
6310
6311 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6312 "JNC done\n\t"
6313 "LZCNT $dst, $src.lo\n\t"
6314 "ADD $dst, 32\n"
6315 "done:" %}
6316 ins_encode %{
6317 Register Rdst = $dst$$Register;
6318 Register Rsrc = $src$$Register;
6319 Label done;
6320 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6321 __ jccb(Assembler::carryClear, done);
6322 __ lzcntl(Rdst, Rsrc);
6323 __ addl(Rdst, BitsPerInt);
6324 __ bind(done);
6325 %}
6326 ins_pipe(ialu_reg);
6327 %}
6328
6329 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6330 predicate(!UseCountLeadingZerosInstruction);
6331 match(Set dst (CountLeadingZerosL src));
6332 effect(TEMP dst, KILL cr);
6333
6334 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6335 "JZ msw_is_zero\n\t"
6336 "ADD $dst, 32\n\t"
6337 "JMP not_zero\n"
6338 "msw_is_zero:\n\t"
6339 "BSR $dst, $src.lo\n\t"
6340 "JNZ not_zero\n\t"
6341 "MOV $dst, -1\n"
6342 "not_zero:\n\t"
6343 "NEG $dst\n\t"
6344 "ADD $dst, 63\n" %}
6345 ins_encode %{
6346 Register Rdst = $dst$$Register;
6347 Register Rsrc = $src$$Register;
6348 Label msw_is_zero;
6349 Label not_zero;
6350 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6351 __ jccb(Assembler::zero, msw_is_zero);
6352 __ addl(Rdst, BitsPerInt);
6353 __ jmpb(not_zero);
6354 __ bind(msw_is_zero);
6355 __ bsrl(Rdst, Rsrc);
6356 __ jccb(Assembler::notZero, not_zero);
6357 __ movl(Rdst, -1);
6358 __ bind(not_zero);
6359 __ negl(Rdst);
6360 __ addl(Rdst, BitsPerLong - 1);
6361 %}
6362 ins_pipe(ialu_reg);
6363 %}
6364
6365 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6366 match(Set dst (CountTrailingZerosI src));
6367 effect(KILL cr);
6368
6369 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6370 "JNZ done\n\t"
6371 "MOV $dst, 32\n"
6372 "done:" %}
6373 ins_encode %{
6374 Register Rdst = $dst$$Register;
6375 Label done;
6376 __ bsfl(Rdst, $src$$Register);
6377 __ jccb(Assembler::notZero, done);
6378 __ movl(Rdst, BitsPerInt);
6379 __ bind(done);
6380 %}
6381 ins_pipe(ialu_reg);
6382 %}
6383
6384 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6385 match(Set dst (CountTrailingZerosL src));
6386 effect(TEMP dst, KILL cr);
6387
6388 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6389 "JNZ done\n\t"
6390 "BSF $dst, $src.hi\n\t"
6391 "JNZ msw_not_zero\n\t"
6392 "MOV $dst, 32\n"
6393 "msw_not_zero:\n\t"
6394 "ADD $dst, 32\n"
6395 "done:" %}
6396 ins_encode %{
6397 Register Rdst = $dst$$Register;
6398 Register Rsrc = $src$$Register;
6399 Label msw_not_zero;
6400 Label done;
6401 __ bsfl(Rdst, Rsrc);
6402 __ jccb(Assembler::notZero, done);
6403 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6404 __ jccb(Assembler::notZero, msw_not_zero);
6405 __ movl(Rdst, BitsPerInt);
6406 __ bind(msw_not_zero);
6407 __ addl(Rdst, BitsPerInt);
6408 __ bind(done);
6409 %}
6410 ins_pipe(ialu_reg);
6411 %}
6412
6413
6414 //---------- Population Count Instructions -------------------------------------
6415
6416 instruct popCountI(eRegI dst, eRegI src) %{
6417 predicate(UsePopCountInstruction);
6418 match(Set dst (PopCountI src));
6419
6420 format %{ "POPCNT $dst, $src" %}
6421 ins_encode %{
6422 __ popcntl($dst$$Register, $src$$Register);
6423 %}
6424 ins_pipe(ialu_reg);
6425 %}
6426
6427 instruct popCountI_mem(eRegI dst, memory mem) %{
6428 predicate(UsePopCountInstruction);
6429 match(Set dst (PopCountI (LoadI mem)));
6430
6431 format %{ "POPCNT $dst, $mem" %}
6432 ins_encode %{
6433 __ popcntl($dst$$Register, $mem$$Address);
6434 %}
6435 ins_pipe(ialu_reg);
6436 %}
6437
6438 // Note: Long.bitCount(long) returns an int.
6439 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6440 predicate(UsePopCountInstruction);
6441 match(Set dst (PopCountL src));
6442 effect(KILL cr, TEMP tmp, TEMP dst);
6443
6444 format %{ "POPCNT $dst, $src.lo\n\t"
6445 "POPCNT $tmp, $src.hi\n\t"
6446 "ADD $dst, $tmp" %}
6447 ins_encode %{
6448 __ popcntl($dst$$Register, $src$$Register);
6449 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6450 __ addl($dst$$Register, $tmp$$Register);
6451 %}
6452 ins_pipe(ialu_reg);
6453 %}
6454
6455 // Note: Long.bitCount(long) returns an int.
6456 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6457 predicate(UsePopCountInstruction);
6458 match(Set dst (PopCountL (LoadL mem)));
6459 effect(KILL cr, TEMP tmp, TEMP dst);
6460
6461 format %{ "POPCNT $dst, $mem\n\t"
6462 "POPCNT $tmp, $mem+4\n\t"
6463 "ADD $dst, $tmp" %}
6464 ins_encode %{
6465 //__ popcntl($dst$$Register, $mem$$Address$$first);
6466 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6467 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6468 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6469 __ addl($dst$$Register, $tmp$$Register);
6470 %}
6471 ins_pipe(ialu_reg);
6472 %}
6473
6474
6475 //----------Load/Store/Move Instructions---------------------------------------
6476 //----------Load Instructions--------------------------------------------------
6477 // Load Byte (8bit signed)
6478 instruct loadB(xRegI dst, memory mem) %{
6479 match(Set dst (LoadB mem));
6480
6481 ins_cost(125);
6482 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6483
6484 ins_encode %{
6485 __ movsbl($dst$$Register, $mem$$Address);
6486 %}
6487
6488 ins_pipe(ialu_reg_mem);
6489 %}
6490
6491 // Load Byte (8bit signed) into Long Register
6492 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6493 match(Set dst (ConvI2L (LoadB mem)));
6494 effect(KILL cr);
6495
6496 ins_cost(375);
6497 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6498 "MOV $dst.hi,$dst.lo\n\t"
6499 "SAR $dst.hi,7" %}
6500
6501 ins_encode %{
6502 __ movsbl($dst$$Register, $mem$$Address);
6503 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6504 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6505 %}
6506
6507 ins_pipe(ialu_reg_mem);
6508 %}
6509
6510 // Load Unsigned Byte (8bit UNsigned)
6511 instruct loadUB(xRegI dst, memory mem) %{
6512 match(Set dst (LoadUB mem));
6513
6514 ins_cost(125);
6515 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6516
6517 ins_encode %{
6518 __ movzbl($dst$$Register, $mem$$Address);
6519 %}
6520
6521 ins_pipe(ialu_reg_mem);
6522 %}
6523
6524 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6525 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6526 match(Set dst (ConvI2L (LoadUB mem)));
6527 effect(KILL cr);
6528
6529 ins_cost(250);
6530 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6531 "XOR $dst.hi,$dst.hi" %}
6532
6533 ins_encode %{
6534 Register Rdst = $dst$$Register;
6535 __ movzbl(Rdst, $mem$$Address);
6536 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6537 %}
6538
6539 ins_pipe(ialu_reg_mem);
6540 %}
6541
6542 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
6543 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
6544 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6545 effect(KILL cr);
6546
6547 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
6548 "XOR $dst.hi,$dst.hi\n\t"
6549 "AND $dst.lo,$mask" %}
6550 ins_encode %{
6551 Register Rdst = $dst$$Register;
6552 __ movzbl(Rdst, $mem$$Address);
6553 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6554 __ andl(Rdst, $mask$$constant);
6555 %}
6556 ins_pipe(ialu_reg_mem);
6557 %}
6558
6559 // Load Short (16bit signed)
6560 instruct loadS(eRegI dst, memory mem) %{
6561 match(Set dst (LoadS mem));
6562
6563 ins_cost(125);
6564 format %{ "MOVSX $dst,$mem\t# short" %}
6565
6566 ins_encode %{
6567 __ movswl($dst$$Register, $mem$$Address);
6568 %}
6569
6570 ins_pipe(ialu_reg_mem);
6571 %}
6572
6573 // Load Short (16 bit signed) to Byte (8 bit signed)
6574 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6575 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6576
6577 ins_cost(125);
6578 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6579 ins_encode %{
6580 __ movsbl($dst$$Register, $mem$$Address);
6581 %}
6582 ins_pipe(ialu_reg_mem);
6583 %}
6584
6585 // Load Short (16bit signed) into Long Register
6586 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6587 match(Set dst (ConvI2L (LoadS mem)));
6588 effect(KILL cr);
6589
6590 ins_cost(375);
6591 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6592 "MOV $dst.hi,$dst.lo\n\t"
6593 "SAR $dst.hi,15" %}
6594
6595 ins_encode %{
6596 __ movswl($dst$$Register, $mem$$Address);
6597 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6598 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6599 %}
6600
6601 ins_pipe(ialu_reg_mem);
6602 %}
6603
6604 // Load Unsigned Short/Char (16bit unsigned)
6605 instruct loadUS(eRegI dst, memory mem) %{
6606 match(Set dst (LoadUS mem));
6607
6608 ins_cost(125);
6609 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6610
6611 ins_encode %{
6612 __ movzwl($dst$$Register, $mem$$Address);
6613 %}
6614
6615 ins_pipe(ialu_reg_mem);
6616 %}
6617
6618 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6619 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6620 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6621
6622 ins_cost(125);
6623 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6624 ins_encode %{
6625 __ movsbl($dst$$Register, $mem$$Address);
6626 %}
6627 ins_pipe(ialu_reg_mem);
6628 %}
6629
6630 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6631 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6632 match(Set dst (ConvI2L (LoadUS mem)));
6633 effect(KILL cr);
6634
6635 ins_cost(250);
6636 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6637 "XOR $dst.hi,$dst.hi" %}
6638
6639 ins_encode %{
6640 __ movzwl($dst$$Register, $mem$$Address);
6641 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6642 %}
6643
6644 ins_pipe(ialu_reg_mem);
6645 %}
6646
6647 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6648 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6649 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6650 effect(KILL cr);
6651
6652 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6653 "XOR $dst.hi,$dst.hi" %}
6654 ins_encode %{
6655 Register Rdst = $dst$$Register;
6656 __ movzbl(Rdst, $mem$$Address);
6657 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6658 %}
6659 ins_pipe(ialu_reg_mem);
6660 %}
6661
6662 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6663 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6664 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6665 effect(KILL cr);
6666
6667 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6668 "XOR $dst.hi,$dst.hi\n\t"
6669 "AND $dst.lo,$mask" %}
6670 ins_encode %{
6671 Register Rdst = $dst$$Register;
6672 __ movzwl(Rdst, $mem$$Address);
6673 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6674 __ andl(Rdst, $mask$$constant);
6675 %}
6676 ins_pipe(ialu_reg_mem);
6677 %}
6678
6679 // Load Integer
6680 instruct loadI(eRegI dst, memory mem) %{
6681 match(Set dst (LoadI mem));
6682
6683 ins_cost(125);
6684 format %{ "MOV $dst,$mem\t# int" %}
6685
6686 ins_encode %{
6687 __ movl($dst$$Register, $mem$$Address);
6688 %}
6689
6690 ins_pipe(ialu_reg_mem);
6691 %}
6692
6693 // Load Integer (32 bit signed) to Byte (8 bit signed)
6694 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6695 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6696
6697 ins_cost(125);
6698 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6699 ins_encode %{
6700 __ movsbl($dst$$Register, $mem$$Address);
6701 %}
6702 ins_pipe(ialu_reg_mem);
6703 %}
6704
6705 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6706 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6707 match(Set dst (AndI (LoadI mem) mask));
6708
6709 ins_cost(125);
6710 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6711 ins_encode %{
6712 __ movzbl($dst$$Register, $mem$$Address);
6713 %}
6714 ins_pipe(ialu_reg_mem);
6715 %}
6716
6717 // Load Integer (32 bit signed) to Short (16 bit signed)
6718 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6719 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6720
6721 ins_cost(125);
6722 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6723 ins_encode %{
6724 __ movswl($dst$$Register, $mem$$Address);
6725 %}
6726 ins_pipe(ialu_reg_mem);
6727 %}
6728
6729 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6730 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6731 match(Set dst (AndI (LoadI mem) mask));
6732
6733 ins_cost(125);
6734 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6735 ins_encode %{
6736 __ movzwl($dst$$Register, $mem$$Address);
6737 %}
6738 ins_pipe(ialu_reg_mem);
6739 %}
6740
6741 // Load Integer into Long Register
6742 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6743 match(Set dst (ConvI2L (LoadI mem)));
6744 effect(KILL cr);
6745
6746 ins_cost(375);
6747 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6748 "MOV $dst.hi,$dst.lo\n\t"
6749 "SAR $dst.hi,31" %}
6750
6751 ins_encode %{
6752 __ movl($dst$$Register, $mem$$Address);
6753 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6754 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6755 %}
6756
6757 ins_pipe(ialu_reg_mem);
6758 %}
6759
6760 // Load Integer with mask 0xFF into Long Register
6761 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6762 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6763 effect(KILL cr);
6764
6765 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6766 "XOR $dst.hi,$dst.hi" %}
6767 ins_encode %{
6768 Register Rdst = $dst$$Register;
6769 __ movzbl(Rdst, $mem$$Address);
6770 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6771 %}
6772 ins_pipe(ialu_reg_mem);
6773 %}
6774
6775 // Load Integer with mask 0xFFFF into Long Register
6776 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6777 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6778 effect(KILL cr);
6779
6780 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6781 "XOR $dst.hi,$dst.hi" %}
6782 ins_encode %{
6783 Register Rdst = $dst$$Register;
6784 __ movzwl(Rdst, $mem$$Address);
6785 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6786 %}
6787 ins_pipe(ialu_reg_mem);
6788 %}
6789
6790 // Load Integer with 32-bit mask into Long Register
6791 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6792 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6793 effect(KILL cr);
6794
6795 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6796 "XOR $dst.hi,$dst.hi\n\t"
6797 "AND $dst.lo,$mask" %}
6798 ins_encode %{
6799 Register Rdst = $dst$$Register;
6800 __ movl(Rdst, $mem$$Address);
6801 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6802 __ andl(Rdst, $mask$$constant);
6803 %}
6804 ins_pipe(ialu_reg_mem);
6805 %}
6806
6807 // Load Unsigned Integer into Long Register
6808 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6809 match(Set dst (LoadUI2L mem));
6810 effect(KILL cr);
6811
6812 ins_cost(250);
6813 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6814 "XOR $dst.hi,$dst.hi" %}
6815
6816 ins_encode %{
6817 __ movl($dst$$Register, $mem$$Address);
6818 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6819 %}
6820
6821 ins_pipe(ialu_reg_mem);
6822 %}
6823
6824 // Load Long. Cannot clobber address while loading, so restrict address
6825 // register to ESI
6826 instruct loadL(eRegL dst, load_long_memory mem) %{
6827 predicate(!((LoadLNode*)n)->require_atomic_access());
6828 match(Set dst (LoadL mem));
6829
6830 ins_cost(250);
6831 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6832 "MOV $dst.hi,$mem+4" %}
6833
6834 ins_encode %{
6835 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6836 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6837 __ movl($dst$$Register, Amemlo);
6838 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6839 %}
6840
6841 ins_pipe(ialu_reg_long_mem);
6842 %}
6843
6844 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6845 // then store it down to the stack and reload on the int
6846 // side.
6847 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6848 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6849 match(Set dst (LoadL mem));
6850
6851 ins_cost(200);
6852 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6853 "FISTp $dst" %}
6854 ins_encode(enc_loadL_volatile(mem,dst));
6855 ins_pipe( fpu_reg_mem );
6856 %}
6857
6858 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6859 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6860 match(Set dst (LoadL mem));
6861 effect(TEMP tmp);
6862 ins_cost(180);
6863 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6864 "MOVSD $dst,$tmp" %}
6865 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6866 ins_pipe( pipe_slow );
6867 %}
6868
6869 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6870 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6871 match(Set dst (LoadL mem));
6872 effect(TEMP tmp);
6873 ins_cost(160);
6874 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6875 "MOVD $dst.lo,$tmp\n\t"
6876 "PSRLQ $tmp,32\n\t"
6877 "MOVD $dst.hi,$tmp" %}
6878 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6879 ins_pipe( pipe_slow );
6880 %}
6881
6882 // Load Range
6883 instruct loadRange(eRegI dst, memory mem) %{
6884 match(Set dst (LoadRange mem));
6885
6886 ins_cost(125);
6887 format %{ "MOV $dst,$mem" %}
6888 opcode(0x8B);
6889 ins_encode( OpcP, RegMem(dst,mem));
6890 ins_pipe( ialu_reg_mem );
6891 %}
6892
6893
6894 // Load Pointer
6895 instruct loadP(eRegP dst, memory mem) %{
6896 match(Set dst (LoadP mem));
6897
6898 ins_cost(125);
6899 format %{ "MOV $dst,$mem" %}
6900 opcode(0x8B);
6901 ins_encode( OpcP, RegMem(dst,mem));
6902 ins_pipe( ialu_reg_mem );
6903 %}
6904
6905 // Load Klass Pointer
6906 instruct loadKlass(eRegP dst, memory mem) %{
6907 match(Set dst (LoadKlass mem));
6908
6909 ins_cost(125);
6910 format %{ "MOV $dst,$mem" %}
6911 opcode(0x8B);
6912 ins_encode( OpcP, RegMem(dst,mem));
6913 ins_pipe( ialu_reg_mem );
6914 %}
6915
6916 // Load Double
6917 instruct loadD(regD dst, memory mem) %{
6918 predicate(UseSSE<=1);
6919 match(Set dst (LoadD mem));
6920
6921 ins_cost(150);
6922 format %{ "FLD_D ST,$mem\n\t"
6923 "FSTP $dst" %}
6924 opcode(0xDD); /* DD /0 */
6925 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6926 Pop_Reg_D(dst) );
6927 ins_pipe( fpu_reg_mem );
6928 %}
6929
6930 // Load Double to XMM
6931 instruct loadXD(regXD dst, memory mem) %{
6932 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6933 match(Set dst (LoadD mem));
6934 ins_cost(145);
6935 format %{ "MOVSD $dst,$mem" %}
6936 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6937 ins_pipe( pipe_slow );
6938 %}
6939
6940 instruct loadXD_partial(regXD dst, memory mem) %{
6941 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6942 match(Set dst (LoadD mem));
6943 ins_cost(145);
6944 format %{ "MOVLPD $dst,$mem" %}
6945 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6946 ins_pipe( pipe_slow );
6947 %}
6948
6949 // Load to XMM register (single-precision floating point)
6950 // MOVSS instruction
6951 instruct loadX(regX dst, memory mem) %{
6952 predicate(UseSSE>=1);
6953 match(Set dst (LoadF mem));
6954 ins_cost(145);
6955 format %{ "MOVSS $dst,$mem" %}
6956 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6957 ins_pipe( pipe_slow );
6958 %}
6959
6960 // Load Float
6961 instruct loadF(regF dst, memory mem) %{
6962 predicate(UseSSE==0);
6963 match(Set dst (LoadF mem));
6964
6965 ins_cost(150);
6966 format %{ "FLD_S ST,$mem\n\t"
6967 "FSTP $dst" %}
6968 opcode(0xD9); /* D9 /0 */
6969 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6970 Pop_Reg_F(dst) );
6971 ins_pipe( fpu_reg_mem );
6972 %}
6973
6974 // Load Aligned Packed Byte to XMM register
6975 instruct loadA8B(regXD dst, memory mem) %{
6976 predicate(UseSSE>=1);
6977 match(Set dst (Load8B mem));
6978 ins_cost(125);
6979 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6980 ins_encode( movq_ld(dst, mem));
6981 ins_pipe( pipe_slow );
6982 %}
6983
6984 // Load Aligned Packed Short to XMM register
6985 instruct loadA4S(regXD dst, memory mem) %{
6986 predicate(UseSSE>=1);
6987 match(Set dst (Load4S mem));
6988 ins_cost(125);
6989 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6990 ins_encode( movq_ld(dst, mem));
6991 ins_pipe( pipe_slow );
6992 %}
6993
6994 // Load Aligned Packed Char to XMM register
6995 instruct loadA4C(regXD dst, memory mem) %{
6996 predicate(UseSSE>=1);
6997 match(Set dst (Load4C mem));
6998 ins_cost(125);
6999 format %{ "MOVQ $dst,$mem\t! packed4C" %}
7000 ins_encode( movq_ld(dst, mem));
7001 ins_pipe( pipe_slow );
7002 %}
7003
7004 // Load Aligned Packed Integer to XMM register
7005 instruct load2IU(regXD dst, memory mem) %{
7006 predicate(UseSSE>=1);
7007 match(Set dst (Load2I mem));
7008 ins_cost(125);
7009 format %{ "MOVQ $dst,$mem\t! packed2I" %}
7010 ins_encode( movq_ld(dst, mem));
7011 ins_pipe( pipe_slow );
7012 %}
7013
7014 // Load Aligned Packed Single to XMM
7015 instruct loadA2F(regXD dst, memory mem) %{
7016 predicate(UseSSE>=1);
7017 match(Set dst (Load2F mem));
7018 ins_cost(145);
7019 format %{ "MOVQ $dst,$mem\t! packed2F" %}
7020 ins_encode( movq_ld(dst, mem));
7021 ins_pipe( pipe_slow );
7022 %}
7023
7024 // Load Effective Address
7025 instruct leaP8(eRegP dst, indOffset8 mem) %{
7026 match(Set dst mem);
7027
7028 ins_cost(110);
7029 format %{ "LEA $dst,$mem" %}
7030 opcode(0x8D);
7031 ins_encode( OpcP, RegMem(dst,mem));
7032 ins_pipe( ialu_reg_reg_fat );
7033 %}
7034
7035 instruct leaP32(eRegP dst, indOffset32 mem) %{
7036 match(Set dst mem);
7037
7038 ins_cost(110);
7039 format %{ "LEA $dst,$mem" %}
7040 opcode(0x8D);
7041 ins_encode( OpcP, RegMem(dst,mem));
7042 ins_pipe( ialu_reg_reg_fat );
7043 %}
7044
7045 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
7046 match(Set dst mem);
7047
7048 ins_cost(110);
7049 format %{ "LEA $dst,$mem" %}
7050 opcode(0x8D);
7051 ins_encode( OpcP, RegMem(dst,mem));
7052 ins_pipe( ialu_reg_reg_fat );
7053 %}
7054
7055 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7056 match(Set dst mem);
7057
7058 ins_cost(110);
7059 format %{ "LEA $dst,$mem" %}
7060 opcode(0x8D);
7061 ins_encode( OpcP, RegMem(dst,mem));
7062 ins_pipe( ialu_reg_reg_fat );
7063 %}
7064
7065 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7066 match(Set dst mem);
7067
7068 ins_cost(110);
7069 format %{ "LEA $dst,$mem" %}
7070 opcode(0x8D);
7071 ins_encode( OpcP, RegMem(dst,mem));
7072 ins_pipe( ialu_reg_reg_fat );
7073 %}
7074
7075 // Load Constant
7076 instruct loadConI(eRegI dst, immI src) %{
7077 match(Set dst src);
7078
7079 format %{ "MOV $dst,$src" %}
7080 ins_encode( LdImmI(dst, src) );
7081 ins_pipe( ialu_reg_fat );
7082 %}
7083
7084 // Load Constant zero
7085 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7086 match(Set dst src);
7087 effect(KILL cr);
7088
7089 ins_cost(50);
7090 format %{ "XOR $dst,$dst" %}
7091 opcode(0x33); /* + rd */
7092 ins_encode( OpcP, RegReg( dst, dst ) );
7093 ins_pipe( ialu_reg );
7094 %}
7095
7096 instruct loadConP(eRegP dst, immP src) %{
7097 match(Set dst src);
7098
7099 format %{ "MOV $dst,$src" %}
7100 opcode(0xB8); /* + rd */
7101 ins_encode( LdImmP(dst, src) );
7102 ins_pipe( ialu_reg_fat );
7103 %}
7104
7105 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7106 match(Set dst src);
7107 effect(KILL cr);
7108 ins_cost(200);
7109 format %{ "MOV $dst.lo,$src.lo\n\t"
7110 "MOV $dst.hi,$src.hi" %}
7111 opcode(0xB8);
7112 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7113 ins_pipe( ialu_reg_long_fat );
7114 %}
7115
7116 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7117 match(Set dst src);
7118 effect(KILL cr);
7119 ins_cost(150);
7120 format %{ "XOR $dst.lo,$dst.lo\n\t"
7121 "XOR $dst.hi,$dst.hi" %}
7122 opcode(0x33,0x33);
7123 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7124 ins_pipe( ialu_reg_long );
7125 %}
7126
7127 // The instruction usage is guarded by predicate in operand immF().
7128 instruct loadConF(regF dst, immF con) %{
7129 match(Set dst con);
7130 ins_cost(125);
7131 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
7132 "FSTP $dst" %}
7133 ins_encode %{
7134 __ fld_s($constantaddress($con));
7135 __ fstp_d($dst$$reg);
7136 %}
7137 ins_pipe(fpu_reg_con);
7138 %}
7139
7140 // The instruction usage is guarded by predicate in operand immF0().
7141 instruct loadConF0(regF dst, immF0 con) %{
7142 match(Set dst con);
7143 ins_cost(125);
7144 format %{ "FLDZ ST\n\t"
7145 "FSTP $dst" %}
7146 ins_encode %{
7147 __ fldz();
7148 __ fstp_d($dst$$reg);
7149 %}
7150 ins_pipe(fpu_reg_con);
7151 %}
7152
7153 // The instruction usage is guarded by predicate in operand immF1().
7154 instruct loadConF1(regF dst, immF1 con) %{
7155 match(Set dst con);
7156 ins_cost(125);
7157 format %{ "FLD1 ST\n\t"
7158 "FSTP $dst" %}
7159 ins_encode %{
7160 __ fld1();
7161 __ fstp_d($dst$$reg);
7162 %}
7163 ins_pipe(fpu_reg_con);
7164 %}
7165
7166 // The instruction usage is guarded by predicate in operand immXF().
7167 instruct loadConX(regX dst, immXF con) %{
7168 match(Set dst con);
7169 ins_cost(125);
7170 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
7171 ins_encode %{
7172 __ movflt($dst$$XMMRegister, $constantaddress($con));
7173 %}
7174 ins_pipe(pipe_slow);
7175 %}
7176
7177 // The instruction usage is guarded by predicate in operand immXF0().
7178 instruct loadConX0(regX dst, immXF0 src) %{
7179 match(Set dst src);
7180 ins_cost(100);
7181 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7182 ins_encode %{
7183 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
7184 %}
7185 ins_pipe(pipe_slow);
7186 %}
7187
7188 // The instruction usage is guarded by predicate in operand immD().
7189 instruct loadConD(regD dst, immD con) %{
7190 match(Set dst con);
7191 ins_cost(125);
7192
7193 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
7194 "FSTP $dst" %}
7195 ins_encode %{
7196 __ fld_d($constantaddress($con));
7197 __ fstp_d($dst$$reg);
7198 %}
7199 ins_pipe(fpu_reg_con);
7200 %}
7201
7202 // The instruction usage is guarded by predicate in operand immD0().
7203 instruct loadConD0(regD dst, immD0 con) %{
7204 match(Set dst con);
7205 ins_cost(125);
7206
7207 format %{ "FLDZ ST\n\t"
7208 "FSTP $dst" %}
7209 ins_encode %{
7210 __ fldz();
7211 __ fstp_d($dst$$reg);
7212 %}
7213 ins_pipe(fpu_reg_con);
7214 %}
7215
7216 // The instruction usage is guarded by predicate in operand immD1().
7217 instruct loadConD1(regD dst, immD1 con) %{
7218 match(Set dst con);
7219 ins_cost(125);
7220
7221 format %{ "FLD1 ST\n\t"
7222 "FSTP $dst" %}
7223 ins_encode %{
7224 __ fld1();
7225 __ fstp_d($dst$$reg);
7226 %}
7227 ins_pipe(fpu_reg_con);
7228 %}
7229
7230 // The instruction usage is guarded by predicate in operand immXD().
7231 instruct loadConXD(regXD dst, immXD con) %{
7232 match(Set dst con);
7233 ins_cost(125);
7234 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
7235 ins_encode %{
7236 __ movdbl($dst$$XMMRegister, $constantaddress($con));
7237 %}
7238 ins_pipe(pipe_slow);
7239 %}
7240
7241 // The instruction usage is guarded by predicate in operand immXD0().
7242 instruct loadConXD0(regXD dst, immXD0 src) %{
7243 match(Set dst src);
7244 ins_cost(100);
7245 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7246 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7247 ins_pipe( pipe_slow );
7248 %}
7249
7250 // Load Stack Slot
7251 instruct loadSSI(eRegI dst, stackSlotI src) %{
7252 match(Set dst src);
7253 ins_cost(125);
7254
7255 format %{ "MOV $dst,$src" %}
7256 opcode(0x8B);
7257 ins_encode( OpcP, RegMem(dst,src));
7258 ins_pipe( ialu_reg_mem );
7259 %}
7260
7261 instruct loadSSL(eRegL dst, stackSlotL src) %{
7262 match(Set dst src);
7263
7264 ins_cost(200);
7265 format %{ "MOV $dst,$src.lo\n\t"
7266 "MOV $dst+4,$src.hi" %}
7267 opcode(0x8B, 0x8B);
7268 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7269 ins_pipe( ialu_mem_long_reg );
7270 %}
7271
7272 // Load Stack Slot
7273 instruct loadSSP(eRegP dst, stackSlotP src) %{
7274 match(Set dst src);
7275 ins_cost(125);
7276
7277 format %{ "MOV $dst,$src" %}
7278 opcode(0x8B);
7279 ins_encode( OpcP, RegMem(dst,src));
7280 ins_pipe( ialu_reg_mem );
7281 %}
7282
7283 // Load Stack Slot
7284 instruct loadSSF(regF dst, stackSlotF src) %{
7285 match(Set dst src);
7286 ins_cost(125);
7287
7288 format %{ "FLD_S $src\n\t"
7289 "FSTP $dst" %}
7290 opcode(0xD9); /* D9 /0, FLD m32real */
7291 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7292 Pop_Reg_F(dst) );
7293 ins_pipe( fpu_reg_mem );
7294 %}
7295
7296 // Load Stack Slot
7297 instruct loadSSD(regD dst, stackSlotD src) %{
7298 match(Set dst src);
7299 ins_cost(125);
7300
7301 format %{ "FLD_D $src\n\t"
7302 "FSTP $dst" %}
7303 opcode(0xDD); /* DD /0, FLD m64real */
7304 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7305 Pop_Reg_D(dst) );
7306 ins_pipe( fpu_reg_mem );
7307 %}
7308
7309 // Prefetch instructions.
7310 // Must be safe to execute with invalid address (cannot fault).
7311
7312 instruct prefetchr0( memory mem ) %{
7313 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7314 match(PrefetchRead mem);
7315 ins_cost(0);
7316 size(0);
7317 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7318 ins_encode();
7319 ins_pipe(empty);
7320 %}
7321
7322 instruct prefetchr( memory mem ) %{
7323 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
7324 match(PrefetchRead mem);
7325 ins_cost(100);
7326
7327 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7328 ins_encode %{
7329 __ prefetchr($mem$$Address);
7330 %}
7331 ins_pipe(ialu_mem);
7332 %}
7333
7334 instruct prefetchrNTA( memory mem ) %{
7335 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7336 match(PrefetchRead mem);
7337 ins_cost(100);
7338
7339 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7340 ins_encode %{
7341 __ prefetchnta($mem$$Address);
7342 %}
7343 ins_pipe(ialu_mem);
7344 %}
7345
7346 instruct prefetchrT0( memory mem ) %{
7347 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7348 match(PrefetchRead mem);
7349 ins_cost(100);
7350
7351 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7352 ins_encode %{
7353 __ prefetcht0($mem$$Address);
7354 %}
7355 ins_pipe(ialu_mem);
7356 %}
7357
7358 instruct prefetchrT2( memory mem ) %{
7359 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7360 match(PrefetchRead mem);
7361 ins_cost(100);
7362
7363 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7364 ins_encode %{
7365 __ prefetcht2($mem$$Address);
7366 %}
7367 ins_pipe(ialu_mem);
7368 %}
7369
7370 instruct prefetchw0( memory mem ) %{
7371 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7372 match(PrefetchWrite mem);
7373 ins_cost(0);
7374 size(0);
7375 format %{ "Prefetch (non-SSE is empty encoding)" %}
7376 ins_encode();
7377 ins_pipe(empty);
7378 %}
7379
7380 instruct prefetchw( memory mem ) %{
7381 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
7382 match( PrefetchWrite mem );
7383 ins_cost(100);
7384
7385 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7386 ins_encode %{
7387 __ prefetchw($mem$$Address);
7388 %}
7389 ins_pipe(ialu_mem);
7390 %}
7391
7392 instruct prefetchwNTA( memory mem ) %{
7393 predicate(UseSSE>=1);
7394 match(PrefetchWrite mem);
7395 ins_cost(100);
7396
7397 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7398 ins_encode %{
7399 __ prefetchnta($mem$$Address);
7400 %}
7401 ins_pipe(ialu_mem);
7402 %}
7403
7404 // Prefetch instructions for allocation.
7405
7406 instruct prefetchAlloc0( memory mem ) %{
7407 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
7408 match(PrefetchAllocation mem);
7409 ins_cost(0);
7410 size(0);
7411 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
7412 ins_encode();
7413 ins_pipe(empty);
7414 %}
7415
7416 instruct prefetchAlloc( memory mem ) %{
7417 predicate(AllocatePrefetchInstr==3);
7418 match( PrefetchAllocation mem );
7419 ins_cost(100);
7420
7421 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
7422 ins_encode %{
7423 __ prefetchw($mem$$Address);
7424 %}
7425 ins_pipe(ialu_mem);
7426 %}
7427
7428 instruct prefetchAllocNTA( memory mem ) %{
7429 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7430 match(PrefetchAllocation mem);
7431 ins_cost(100);
7432
7433 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
7434 ins_encode %{
7435 __ prefetchnta($mem$$Address);
7436 %}
7437 ins_pipe(ialu_mem);
7438 %}
7439
7440 instruct prefetchAllocT0( memory mem ) %{
7441 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7442 match(PrefetchAllocation mem);
7443 ins_cost(100);
7444
7445 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
7446 ins_encode %{
7447 __ prefetcht0($mem$$Address);
7448 %}
7449 ins_pipe(ialu_mem);
7450 %}
7451
7452 instruct prefetchAllocT2( memory mem ) %{
7453 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7454 match(PrefetchAllocation mem);
7455 ins_cost(100);
7456
7457 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
7458 ins_encode %{
7459 __ prefetcht2($mem$$Address);
7460 %}
7461 ins_pipe(ialu_mem);
7462 %}
7463
7464 //----------Store Instructions-------------------------------------------------
7465
7466 // Store Byte
7467 instruct storeB(memory mem, xRegI src) %{
7468 match(Set mem (StoreB mem src));
7469
7470 ins_cost(125);
7471 format %{ "MOV8 $mem,$src" %}
7472 opcode(0x88);
7473 ins_encode( OpcP, RegMem( src, mem ) );
7474 ins_pipe( ialu_mem_reg );
7475 %}
7476
7477 // Store Char/Short
7478 instruct storeC(memory mem, eRegI src) %{
7479 match(Set mem (StoreC mem src));
7480
7481 ins_cost(125);
7482 format %{ "MOV16 $mem,$src" %}
7483 opcode(0x89, 0x66);
7484 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7485 ins_pipe( ialu_mem_reg );
7486 %}
7487
7488 // Store Integer
7489 instruct storeI(memory mem, eRegI src) %{
7490 match(Set mem (StoreI mem src));
7491
7492 ins_cost(125);
7493 format %{ "MOV $mem,$src" %}
7494 opcode(0x89);
7495 ins_encode( OpcP, RegMem( src, mem ) );
7496 ins_pipe( ialu_mem_reg );
7497 %}
7498
7499 // Store Long
7500 instruct storeL(long_memory mem, eRegL src) %{
7501 predicate(!((StoreLNode*)n)->require_atomic_access());
7502 match(Set mem (StoreL mem src));
7503
7504 ins_cost(200);
7505 format %{ "MOV $mem,$src.lo\n\t"
7506 "MOV $mem+4,$src.hi" %}
7507 opcode(0x89, 0x89);
7508 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7509 ins_pipe( ialu_mem_long_reg );
7510 %}
7511
7512 // Store Long to Integer
7513 instruct storeL2I(memory mem, eRegL src) %{
7514 match(Set mem (StoreI mem (ConvL2I src)));
7515
7516 format %{ "MOV $mem,$src.lo\t# long -> int" %}
7517 ins_encode %{
7518 __ movl($mem$$Address, $src$$Register);
7519 %}
7520 ins_pipe(ialu_mem_reg);
7521 %}
7522
7523 // Volatile Store Long. Must be atomic, so move it into
7524 // the FP TOS and then do a 64-bit FIST. Has to probe the
7525 // target address before the store (for null-ptr checks)
7526 // so the memory operand is used twice in the encoding.
7527 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7528 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7529 match(Set mem (StoreL mem src));
7530 effect( KILL cr );
7531 ins_cost(400);
7532 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7533 "FILD $src\n\t"
7534 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7535 opcode(0x3B);
7536 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7537 ins_pipe( fpu_reg_mem );
7538 %}
7539
7540 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7541 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7542 match(Set mem (StoreL mem src));
7543 effect( TEMP tmp, KILL cr );
7544 ins_cost(380);
7545 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7546 "MOVSD $tmp,$src\n\t"
7547 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7548 opcode(0x3B);
7549 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7550 ins_pipe( pipe_slow );
7551 %}
7552
7553 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7554 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7555 match(Set mem (StoreL mem src));
7556 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7557 ins_cost(360);
7558 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7559 "MOVD $tmp,$src.lo\n\t"
7560 "MOVD $tmp2,$src.hi\n\t"
7561 "PUNPCKLDQ $tmp,$tmp2\n\t"
7562 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7563 opcode(0x3B);
7564 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7565 ins_pipe( pipe_slow );
7566 %}
7567
7568 // Store Pointer; for storing unknown oops and raw pointers
7569 instruct storeP(memory mem, anyRegP src) %{
7570 match(Set mem (StoreP mem src));
7571
7572 ins_cost(125);
7573 format %{ "MOV $mem,$src" %}
7574 opcode(0x89);
7575 ins_encode( OpcP, RegMem( src, mem ) );
7576 ins_pipe( ialu_mem_reg );
7577 %}
7578
7579 // Store Integer Immediate
7580 instruct storeImmI(memory mem, immI src) %{
7581 match(Set mem (StoreI mem src));
7582
7583 ins_cost(150);
7584 format %{ "MOV $mem,$src" %}
7585 opcode(0xC7); /* C7 /0 */
7586 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7587 ins_pipe( ialu_mem_imm );
7588 %}
7589
7590 // Store Short/Char Immediate
7591 instruct storeImmI16(memory mem, immI16 src) %{
7592 predicate(UseStoreImmI16);
7593 match(Set mem (StoreC mem src));
7594
7595 ins_cost(150);
7596 format %{ "MOV16 $mem,$src" %}
7597 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7598 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7599 ins_pipe( ialu_mem_imm );
7600 %}
7601
7602 // Store Pointer Immediate; null pointers or constant oops that do not
7603 // need card-mark barriers.
7604 instruct storeImmP(memory mem, immP src) %{
7605 match(Set mem (StoreP mem src));
7606
7607 ins_cost(150);
7608 format %{ "MOV $mem,$src" %}
7609 opcode(0xC7); /* C7 /0 */
7610 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7611 ins_pipe( ialu_mem_imm );
7612 %}
7613
7614 // Store Byte Immediate
7615 instruct storeImmB(memory mem, immI8 src) %{
7616 match(Set mem (StoreB mem src));
7617
7618 ins_cost(150);
7619 format %{ "MOV8 $mem,$src" %}
7620 opcode(0xC6); /* C6 /0 */
7621 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7622 ins_pipe( ialu_mem_imm );
7623 %}
7624
7625 // Store Aligned Packed Byte XMM register to memory
7626 instruct storeA8B(memory mem, regXD src) %{
7627 predicate(UseSSE>=1);
7628 match(Set mem (Store8B mem src));
7629 ins_cost(145);
7630 format %{ "MOVQ $mem,$src\t! packed8B" %}
7631 ins_encode( movq_st(mem, src));
7632 ins_pipe( pipe_slow );
7633 %}
7634
7635 // Store Aligned Packed Char/Short XMM register to memory
7636 instruct storeA4C(memory mem, regXD src) %{
7637 predicate(UseSSE>=1);
7638 match(Set mem (Store4C mem src));
7639 ins_cost(145);
7640 format %{ "MOVQ $mem,$src\t! packed4C" %}
7641 ins_encode( movq_st(mem, src));
7642 ins_pipe( pipe_slow );
7643 %}
7644
7645 // Store Aligned Packed Integer XMM register to memory
7646 instruct storeA2I(memory mem, regXD src) %{
7647 predicate(UseSSE>=1);
7648 match(Set mem (Store2I mem src));
7649 ins_cost(145);
7650 format %{ "MOVQ $mem,$src\t! packed2I" %}
7651 ins_encode( movq_st(mem, src));
7652 ins_pipe( pipe_slow );
7653 %}
7654
7655 // Store CMS card-mark Immediate
7656 instruct storeImmCM(memory mem, immI8 src) %{
7657 match(Set mem (StoreCM mem src));
7658
7659 ins_cost(150);
7660 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7661 opcode(0xC6); /* C6 /0 */
7662 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7663 ins_pipe( ialu_mem_imm );
7664 %}
7665
7666 // Store Double
7667 instruct storeD( memory mem, regDPR1 src) %{
7668 predicate(UseSSE<=1);
7669 match(Set mem (StoreD mem src));
7670
7671 ins_cost(100);
7672 format %{ "FST_D $mem,$src" %}
7673 opcode(0xDD); /* DD /2 */
7674 ins_encode( enc_FP_store(mem,src) );
7675 ins_pipe( fpu_mem_reg );
7676 %}
7677
7678 // Store double does rounding on x86
7679 instruct storeD_rounded( memory mem, regDPR1 src) %{
7680 predicate(UseSSE<=1);
7681 match(Set mem (StoreD mem (RoundDouble src)));
7682
7683 ins_cost(100);
7684 format %{ "FST_D $mem,$src\t# round" %}
7685 opcode(0xDD); /* DD /2 */
7686 ins_encode( enc_FP_store(mem,src) );
7687 ins_pipe( fpu_mem_reg );
7688 %}
7689
7690 // Store XMM register to memory (double-precision floating points)
7691 // MOVSD instruction
7692 instruct storeXD(memory mem, regXD src) %{
7693 predicate(UseSSE>=2);
7694 match(Set mem (StoreD mem src));
7695 ins_cost(95);
7696 format %{ "MOVSD $mem,$src" %}
7697 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7698 ins_pipe( pipe_slow );
7699 %}
7700
7701 // Store XMM register to memory (single-precision floating point)
7702 // MOVSS instruction
7703 instruct storeX(memory mem, regX src) %{
7704 predicate(UseSSE>=1);
7705 match(Set mem (StoreF mem src));
7706 ins_cost(95);
7707 format %{ "MOVSS $mem,$src" %}
7708 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7709 ins_pipe( pipe_slow );
7710 %}
7711
7712 // Store Aligned Packed Single Float XMM register to memory
7713 instruct storeA2F(memory mem, regXD src) %{
7714 predicate(UseSSE>=1);
7715 match(Set mem (Store2F mem src));
7716 ins_cost(145);
7717 format %{ "MOVQ $mem,$src\t! packed2F" %}
7718 ins_encode( movq_st(mem, src));
7719 ins_pipe( pipe_slow );
7720 %}
7721
7722 // Store Float
7723 instruct storeF( memory mem, regFPR1 src) %{
7724 predicate(UseSSE==0);
7725 match(Set mem (StoreF mem src));
7726
7727 ins_cost(100);
7728 format %{ "FST_S $mem,$src" %}
7729 opcode(0xD9); /* D9 /2 */
7730 ins_encode( enc_FP_store(mem,src) );
7731 ins_pipe( fpu_mem_reg );
7732 %}
7733
7734 // Store Float does rounding on x86
7735 instruct storeF_rounded( memory mem, regFPR1 src) %{
7736 predicate(UseSSE==0);
7737 match(Set mem (StoreF mem (RoundFloat src)));
7738
7739 ins_cost(100);
7740 format %{ "FST_S $mem,$src\t# round" %}
7741 opcode(0xD9); /* D9 /2 */
7742 ins_encode( enc_FP_store(mem,src) );
7743 ins_pipe( fpu_mem_reg );
7744 %}
7745
7746 // Store Float does rounding on x86
7747 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7748 predicate(UseSSE<=1);
7749 match(Set mem (StoreF mem (ConvD2F src)));
7750
7751 ins_cost(100);
7752 format %{ "FST_S $mem,$src\t# D-round" %}
7753 opcode(0xD9); /* D9 /2 */
7754 ins_encode( enc_FP_store(mem,src) );
7755 ins_pipe( fpu_mem_reg );
7756 %}
7757
7758 // Store immediate Float value (it is faster than store from FPU register)
7759 // The instruction usage is guarded by predicate in operand immF().
7760 instruct storeF_imm( memory mem, immF src) %{
7761 match(Set mem (StoreF mem src));
7762
7763 ins_cost(50);
7764 format %{ "MOV $mem,$src\t# store float" %}
7765 opcode(0xC7); /* C7 /0 */
7766 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7767 ins_pipe( ialu_mem_imm );
7768 %}
7769
7770 // Store immediate Float value (it is faster than store from XMM register)
7771 // The instruction usage is guarded by predicate in operand immXF().
7772 instruct storeX_imm( memory mem, immXF src) %{
7773 match(Set mem (StoreF mem src));
7774
7775 ins_cost(50);
7776 format %{ "MOV $mem,$src\t# store float" %}
7777 opcode(0xC7); /* C7 /0 */
7778 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7779 ins_pipe( ialu_mem_imm );
7780 %}
7781
7782 // Store Integer to stack slot
7783 instruct storeSSI(stackSlotI dst, eRegI src) %{
7784 match(Set dst src);
7785
7786 ins_cost(100);
7787 format %{ "MOV $dst,$src" %}
7788 opcode(0x89);
7789 ins_encode( OpcPRegSS( dst, src ) );
7790 ins_pipe( ialu_mem_reg );
7791 %}
7792
7793 // Store Integer to stack slot
7794 instruct storeSSP(stackSlotP dst, eRegP src) %{
7795 match(Set dst src);
7796
7797 ins_cost(100);
7798 format %{ "MOV $dst,$src" %}
7799 opcode(0x89);
7800 ins_encode( OpcPRegSS( dst, src ) );
7801 ins_pipe( ialu_mem_reg );
7802 %}
7803
7804 // Store Long to stack slot
7805 instruct storeSSL(stackSlotL dst, eRegL src) %{
7806 match(Set dst src);
7807
7808 ins_cost(200);
7809 format %{ "MOV $dst,$src.lo\n\t"
7810 "MOV $dst+4,$src.hi" %}
7811 opcode(0x89, 0x89);
7812 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7813 ins_pipe( ialu_mem_long_reg );
7814 %}
7815
7816 //----------MemBar Instructions-----------------------------------------------
7817 // Memory barrier flavors
7818
7819 instruct membar_acquire() %{
7820 match(MemBarAcquire);
7821 ins_cost(400);
7822
7823 size(0);
7824 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7825 ins_encode();
7826 ins_pipe(empty);
7827 %}
7828
7829 instruct membar_acquire_lock() %{
7830 match(MemBarAcquireLock);
7831 ins_cost(0);
7832
7833 size(0);
7834 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7835 ins_encode( );
7836 ins_pipe(empty);
7837 %}
7838
7839 instruct membar_release() %{
7840 match(MemBarRelease);
7841 ins_cost(400);
7842
7843 size(0);
7844 format %{ "MEMBAR-release ! (empty encoding)" %}
7845 ins_encode( );
7846 ins_pipe(empty);
7847 %}
7848
7849 instruct membar_release_lock() %{
7850 match(MemBarReleaseLock);
7851 ins_cost(0);
7852
7853 size(0);
7854 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7855 ins_encode( );
7856 ins_pipe(empty);
7857 %}
7858
7859 instruct membar_volatile(eFlagsReg cr) %{
7860 match(MemBarVolatile);
7861 effect(KILL cr);
7862 ins_cost(400);
7863
7864 format %{
7865 $$template
7866 if (os::is_MP()) {
7867 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7868 } else {
7869 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7870 }
7871 %}
7872 ins_encode %{
7873 __ membar(Assembler::StoreLoad);
7874 %}
7875 ins_pipe(pipe_slow);
7876 %}
7877
7878 instruct unnecessary_membar_volatile() %{
7879 match(MemBarVolatile);
7880 predicate(Matcher::post_store_load_barrier(n));
7881 ins_cost(0);
7882
7883 size(0);
7884 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7885 ins_encode( );
7886 ins_pipe(empty);
7887 %}
7888
7889 //----------Move Instructions--------------------------------------------------
7890 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7891 match(Set dst (CastX2P src));
7892 format %{ "# X2P $dst, $src" %}
7893 ins_encode( /*empty encoding*/ );
7894 ins_cost(0);
7895 ins_pipe(empty);
7896 %}
7897
7898 instruct castP2X(eRegI dst, eRegP src ) %{
7899 match(Set dst (CastP2X src));
7900 ins_cost(50);
7901 format %{ "MOV $dst, $src\t# CastP2X" %}
7902 ins_encode( enc_Copy( dst, src) );
7903 ins_pipe( ialu_reg_reg );
7904 %}
7905
7906 //----------Conditional Move---------------------------------------------------
7907 // Conditional move
7908 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7909 predicate(VM_Version::supports_cmov() );
7910 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7911 ins_cost(200);
7912 format %{ "CMOV$cop $dst,$src" %}
7913 opcode(0x0F,0x40);
7914 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7915 ins_pipe( pipe_cmov_reg );
7916 %}
7917
7918 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7919 predicate(VM_Version::supports_cmov() );
7920 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7921 ins_cost(200);
7922 format %{ "CMOV$cop $dst,$src" %}
7923 opcode(0x0F,0x40);
7924 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7925 ins_pipe( pipe_cmov_reg );
7926 %}
7927
7928 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7929 predicate(VM_Version::supports_cmov() );
7930 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7931 ins_cost(200);
7932 expand %{
7933 cmovI_regU(cop, cr, dst, src);
7934 %}
7935 %}
7936
7937 // Conditional move
7938 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7939 predicate(VM_Version::supports_cmov() );
7940 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7941 ins_cost(250);
7942 format %{ "CMOV$cop $dst,$src" %}
7943 opcode(0x0F,0x40);
7944 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7945 ins_pipe( pipe_cmov_mem );
7946 %}
7947
7948 // Conditional move
7949 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7950 predicate(VM_Version::supports_cmov() );
7951 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7952 ins_cost(250);
7953 format %{ "CMOV$cop $dst,$src" %}
7954 opcode(0x0F,0x40);
7955 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7956 ins_pipe( pipe_cmov_mem );
7957 %}
7958
7959 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7960 predicate(VM_Version::supports_cmov() );
7961 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7962 ins_cost(250);
7963 expand %{
7964 cmovI_memU(cop, cr, dst, src);
7965 %}
7966 %}
7967
7968 // Conditional move
7969 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7970 predicate(VM_Version::supports_cmov() );
7971 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7972 ins_cost(200);
7973 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7974 opcode(0x0F,0x40);
7975 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7976 ins_pipe( pipe_cmov_reg );
7977 %}
7978
7979 // Conditional move (non-P6 version)
7980 // Note: a CMoveP is generated for stubs and native wrappers
7981 // regardless of whether we are on a P6, so we
7982 // emulate a cmov here
7983 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7984 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7985 ins_cost(300);
7986 format %{ "Jn$cop skip\n\t"
7987 "MOV $dst,$src\t# pointer\n"
7988 "skip:" %}
7989 opcode(0x8b);
7990 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7991 ins_pipe( pipe_cmov_reg );
7992 %}
7993
7994 // Conditional move
7995 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7996 predicate(VM_Version::supports_cmov() );
7997 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7998 ins_cost(200);
7999 format %{ "CMOV$cop $dst,$src\t# ptr" %}
8000 opcode(0x0F,0x40);
8001 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
8002 ins_pipe( pipe_cmov_reg );
8003 %}
8004
8005 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
8006 predicate(VM_Version::supports_cmov() );
8007 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
8008 ins_cost(200);
8009 expand %{
8010 cmovP_regU(cop, cr, dst, src);
8011 %}
8012 %}
8013
8014 // DISABLED: Requires the ADLC to emit a bottom_type call that
8015 // correctly meets the two pointer arguments; one is an incoming
8016 // register but the other is a memory operand. ALSO appears to
8017 // be buggy with implicit null checks.
8018 //
8019 //// Conditional move
8020 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
8021 // predicate(VM_Version::supports_cmov() );
8022 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8023 // ins_cost(250);
8024 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8025 // opcode(0x0F,0x40);
8026 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8027 // ins_pipe( pipe_cmov_mem );
8028 //%}
8029 //
8030 //// Conditional move
8031 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
8032 // predicate(VM_Version::supports_cmov() );
8033 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8034 // ins_cost(250);
8035 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8036 // opcode(0x0F,0x40);
8037 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8038 // ins_pipe( pipe_cmov_mem );
8039 //%}
8040
8041 // Conditional move
8042 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
8043 predicate(UseSSE<=1);
8044 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8045 ins_cost(200);
8046 format %{ "FCMOV$cop $dst,$src\t# double" %}
8047 opcode(0xDA);
8048 ins_encode( enc_cmov_d(cop,src) );
8049 ins_pipe( pipe_cmovD_reg );
8050 %}
8051
8052 // Conditional move
8053 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
8054 predicate(UseSSE==0);
8055 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8056 ins_cost(200);
8057 format %{ "FCMOV$cop $dst,$src\t# float" %}
8058 opcode(0xDA);
8059 ins_encode( enc_cmov_d(cop,src) );
8060 ins_pipe( pipe_cmovD_reg );
8061 %}
8062
8063 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8064 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
8065 predicate(UseSSE<=1);
8066 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8067 ins_cost(200);
8068 format %{ "Jn$cop skip\n\t"
8069 "MOV $dst,$src\t# double\n"
8070 "skip:" %}
8071 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8072 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
8073 ins_pipe( pipe_cmovD_reg );
8074 %}
8075
8076 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8077 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
8078 predicate(UseSSE==0);
8079 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8080 ins_cost(200);
8081 format %{ "Jn$cop skip\n\t"
8082 "MOV $dst,$src\t# float\n"
8083 "skip:" %}
8084 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8085 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
8086 ins_pipe( pipe_cmovD_reg );
8087 %}
8088
8089 // No CMOVE with SSE/SSE2
8090 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
8091 predicate (UseSSE>=1);
8092 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8093 ins_cost(200);
8094 format %{ "Jn$cop skip\n\t"
8095 "MOVSS $dst,$src\t# float\n"
8096 "skip:" %}
8097 ins_encode %{
8098 Label skip;
8099 // Invert sense of branch from sense of CMOV
8100 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8101 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8102 __ bind(skip);
8103 %}
8104 ins_pipe( pipe_slow );
8105 %}
8106
8107 // No CMOVE with SSE/SSE2
8108 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
8109 predicate (UseSSE>=2);
8110 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8111 ins_cost(200);
8112 format %{ "Jn$cop skip\n\t"
8113 "MOVSD $dst,$src\t# float\n"
8114 "skip:" %}
8115 ins_encode %{
8116 Label skip;
8117 // Invert sense of branch from sense of CMOV
8118 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8119 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8120 __ bind(skip);
8121 %}
8122 ins_pipe( pipe_slow );
8123 %}
8124
8125 // unsigned version
8126 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
8127 predicate (UseSSE>=1);
8128 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8129 ins_cost(200);
8130 format %{ "Jn$cop skip\n\t"
8131 "MOVSS $dst,$src\t# float\n"
8132 "skip:" %}
8133 ins_encode %{
8134 Label skip;
8135 // Invert sense of branch from sense of CMOV
8136 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8137 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8138 __ bind(skip);
8139 %}
8140 ins_pipe( pipe_slow );
8141 %}
8142
8143 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
8144 predicate (UseSSE>=1);
8145 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8146 ins_cost(200);
8147 expand %{
8148 fcmovX_regU(cop, cr, dst, src);
8149 %}
8150 %}
8151
8152 // unsigned version
8153 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
8154 predicate (UseSSE>=2);
8155 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8156 ins_cost(200);
8157 format %{ "Jn$cop skip\n\t"
8158 "MOVSD $dst,$src\t# float\n"
8159 "skip:" %}
8160 ins_encode %{
8161 Label skip;
8162 // Invert sense of branch from sense of CMOV
8163 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8164 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8165 __ bind(skip);
8166 %}
8167 ins_pipe( pipe_slow );
8168 %}
8169
8170 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8171 predicate (UseSSE>=2);
8172 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8173 ins_cost(200);
8174 expand %{
8175 fcmovXD_regU(cop, cr, dst, src);
8176 %}
8177 %}
8178
8179 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8180 predicate(VM_Version::supports_cmov() );
8181 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8182 ins_cost(200);
8183 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8184 "CMOV$cop $dst.hi,$src.hi" %}
8185 opcode(0x0F,0x40);
8186 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8187 ins_pipe( pipe_cmov_reg_long );
8188 %}
8189
8190 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8191 predicate(VM_Version::supports_cmov() );
8192 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8193 ins_cost(200);
8194 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8195 "CMOV$cop $dst.hi,$src.hi" %}
8196 opcode(0x0F,0x40);
8197 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8198 ins_pipe( pipe_cmov_reg_long );
8199 %}
8200
8201 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8202 predicate(VM_Version::supports_cmov() );
8203 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8204 ins_cost(200);
8205 expand %{
8206 cmovL_regU(cop, cr, dst, src);
8207 %}
8208 %}
8209
8210 //----------Arithmetic Instructions--------------------------------------------
8211 //----------Addition Instructions----------------------------------------------
8212 // Integer Addition Instructions
8213 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8214 match(Set dst (AddI dst src));
8215 effect(KILL cr);
8216
8217 size(2);
8218 format %{ "ADD $dst,$src" %}
8219 opcode(0x03);
8220 ins_encode( OpcP, RegReg( dst, src) );
8221 ins_pipe( ialu_reg_reg );
8222 %}
8223
8224 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8225 match(Set dst (AddI dst src));
8226 effect(KILL cr);
8227
8228 format %{ "ADD $dst,$src" %}
8229 opcode(0x81, 0x00); /* /0 id */
8230 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8231 ins_pipe( ialu_reg );
8232 %}
8233
8234 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8235 predicate(UseIncDec);
8236 match(Set dst (AddI dst src));
8237 effect(KILL cr);
8238
8239 size(1);
8240 format %{ "INC $dst" %}
8241 opcode(0x40); /* */
8242 ins_encode( Opc_plus( primary, dst ) );
8243 ins_pipe( ialu_reg );
8244 %}
8245
8246 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8247 match(Set dst (AddI src0 src1));
8248 ins_cost(110);
8249
8250 format %{ "LEA $dst,[$src0 + $src1]" %}
8251 opcode(0x8D); /* 0x8D /r */
8252 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8253 ins_pipe( ialu_reg_reg );
8254 %}
8255
8256 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8257 match(Set dst (AddP src0 src1));
8258 ins_cost(110);
8259
8260 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8261 opcode(0x8D); /* 0x8D /r */
8262 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8263 ins_pipe( ialu_reg_reg );
8264 %}
8265
8266 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8267 predicate(UseIncDec);
8268 match(Set dst (AddI dst src));
8269 effect(KILL cr);
8270
8271 size(1);
8272 format %{ "DEC $dst" %}
8273 opcode(0x48); /* */
8274 ins_encode( Opc_plus( primary, dst ) );
8275 ins_pipe( ialu_reg );
8276 %}
8277
8278 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8279 match(Set dst (AddP dst src));
8280 effect(KILL cr);
8281
8282 size(2);
8283 format %{ "ADD $dst,$src" %}
8284 opcode(0x03);
8285 ins_encode( OpcP, RegReg( dst, src) );
8286 ins_pipe( ialu_reg_reg );
8287 %}
8288
8289 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8290 match(Set dst (AddP dst src));
8291 effect(KILL cr);
8292
8293 format %{ "ADD $dst,$src" %}
8294 opcode(0x81,0x00); /* Opcode 81 /0 id */
8295 // ins_encode( RegImm( dst, src) );
8296 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8297 ins_pipe( ialu_reg );
8298 %}
8299
8300 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8301 match(Set dst (AddI dst (LoadI src)));
8302 effect(KILL cr);
8303
8304 ins_cost(125);
8305 format %{ "ADD $dst,$src" %}
8306 opcode(0x03);
8307 ins_encode( OpcP, RegMem( dst, src) );
8308 ins_pipe( ialu_reg_mem );
8309 %}
8310
8311 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8312 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8313 effect(KILL cr);
8314
8315 ins_cost(150);
8316 format %{ "ADD $dst,$src" %}
8317 opcode(0x01); /* Opcode 01 /r */
8318 ins_encode( OpcP, RegMem( src, dst ) );
8319 ins_pipe( ialu_mem_reg );
8320 %}
8321
8322 // Add Memory with Immediate
8323 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8324 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8325 effect(KILL cr);
8326
8327 ins_cost(125);
8328 format %{ "ADD $dst,$src" %}
8329 opcode(0x81); /* Opcode 81 /0 id */
8330 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8331 ins_pipe( ialu_mem_imm );
8332 %}
8333
8334 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8335 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8336 effect(KILL cr);
8337
8338 ins_cost(125);
8339 format %{ "INC $dst" %}
8340 opcode(0xFF); /* Opcode FF /0 */
8341 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8342 ins_pipe( ialu_mem_imm );
8343 %}
8344
8345 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8346 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8347 effect(KILL cr);
8348
8349 ins_cost(125);
8350 format %{ "DEC $dst" %}
8351 opcode(0xFF); /* Opcode FF /1 */
8352 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8353 ins_pipe( ialu_mem_imm );
8354 %}
8355
8356
8357 instruct checkCastPP( eRegP dst ) %{
8358 match(Set dst (CheckCastPP dst));
8359
8360 size(0);
8361 format %{ "#checkcastPP of $dst" %}
8362 ins_encode( /*empty encoding*/ );
8363 ins_pipe( empty );
8364 %}
8365
8366 instruct castPP( eRegP dst ) %{
8367 match(Set dst (CastPP dst));
8368 format %{ "#castPP of $dst" %}
8369 ins_encode( /*empty encoding*/ );
8370 ins_pipe( empty );
8371 %}
8372
8373 instruct castII( eRegI dst ) %{
8374 match(Set dst (CastII dst));
8375 format %{ "#castII of $dst" %}
8376 ins_encode( /*empty encoding*/ );
8377 ins_cost(0);
8378 ins_pipe( empty );
8379 %}
8380
8381
8382 // Load-locked - same as a regular pointer load when used with compare-swap
8383 instruct loadPLocked(eRegP dst, memory mem) %{
8384 match(Set dst (LoadPLocked mem));
8385
8386 ins_cost(125);
8387 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8388 opcode(0x8B);
8389 ins_encode( OpcP, RegMem(dst,mem));
8390 ins_pipe( ialu_reg_mem );
8391 %}
8392
8393 // LoadLong-locked - same as a volatile long load when used with compare-swap
8394 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8395 predicate(UseSSE<=1);
8396 match(Set dst (LoadLLocked mem));
8397
8398 ins_cost(200);
8399 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8400 "FISTp $dst" %}
8401 ins_encode(enc_loadL_volatile(mem,dst));
8402 ins_pipe( fpu_reg_mem );
8403 %}
8404
8405 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8406 predicate(UseSSE>=2);
8407 match(Set dst (LoadLLocked mem));
8408 effect(TEMP tmp);
8409 ins_cost(180);
8410 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8411 "MOVSD $dst,$tmp" %}
8412 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8413 ins_pipe( pipe_slow );
8414 %}
8415
8416 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8417 predicate(UseSSE>=2);
8418 match(Set dst (LoadLLocked mem));
8419 effect(TEMP tmp);
8420 ins_cost(160);
8421 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8422 "MOVD $dst.lo,$tmp\n\t"
8423 "PSRLQ $tmp,32\n\t"
8424 "MOVD $dst.hi,$tmp" %}
8425 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8426 ins_pipe( pipe_slow );
8427 %}
8428
8429 // Conditional-store of the updated heap-top.
8430 // Used during allocation of the shared heap.
8431 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8432 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8433 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8434 // EAX is killed if there is contention, but then it's also unused.
8435 // In the common case of no contention, EAX holds the new oop address.
8436 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8437 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8438 ins_pipe( pipe_cmpxchg );
8439 %}
8440
8441 // Conditional-store of an int value.
8442 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8443 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8444 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8445 effect(KILL oldval);
8446 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8447 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8448 ins_pipe( pipe_cmpxchg );
8449 %}
8450
8451 // Conditional-store of a long value.
8452 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8453 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8454 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8455 effect(KILL oldval);
8456 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8457 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8458 "XCHG EBX,ECX"
8459 %}
8460 ins_encode %{
8461 // Note: we need to swap rbx, and rcx before and after the
8462 // cmpxchg8 instruction because the instruction uses
8463 // rcx as the high order word of the new value to store but
8464 // our register encoding uses rbx.
8465 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8466 if( os::is_MP() )
8467 __ lock();
8468 __ cmpxchg8($mem$$Address);
8469 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8470 %}
8471 ins_pipe( pipe_cmpxchg );
8472 %}
8473
8474 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8475
8476 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8477 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8478 effect(KILL cr, KILL oldval);
8479 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8480 "MOV $res,0\n\t"
8481 "JNE,s fail\n\t"
8482 "MOV $res,1\n"
8483 "fail:" %}
8484 ins_encode( enc_cmpxchg8(mem_ptr),
8485 enc_flags_ne_to_boolean(res) );
8486 ins_pipe( pipe_cmpxchg );
8487 %}
8488
8489 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8490 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8491 effect(KILL cr, KILL oldval);
8492 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8493 "MOV $res,0\n\t"
8494 "JNE,s fail\n\t"
8495 "MOV $res,1\n"
8496 "fail:" %}
8497 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8498 ins_pipe( pipe_cmpxchg );
8499 %}
8500
8501 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8502 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8503 effect(KILL cr, KILL oldval);
8504 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8505 "MOV $res,0\n\t"
8506 "JNE,s fail\n\t"
8507 "MOV $res,1\n"
8508 "fail:" %}
8509 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8510 ins_pipe( pipe_cmpxchg );
8511 %}
8512
8513 //----------Subtraction Instructions-------------------------------------------
8514 // Integer Subtraction Instructions
8515 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8516 match(Set dst (SubI dst src));
8517 effect(KILL cr);
8518
8519 size(2);
8520 format %{ "SUB $dst,$src" %}
8521 opcode(0x2B);
8522 ins_encode( OpcP, RegReg( dst, src) );
8523 ins_pipe( ialu_reg_reg );
8524 %}
8525
8526 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8527 match(Set dst (SubI dst src));
8528 effect(KILL cr);
8529
8530 format %{ "SUB $dst,$src" %}
8531 opcode(0x81,0x05); /* Opcode 81 /5 */
8532 // ins_encode( RegImm( dst, src) );
8533 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8534 ins_pipe( ialu_reg );
8535 %}
8536
8537 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8538 match(Set dst (SubI dst (LoadI src)));
8539 effect(KILL cr);
8540
8541 ins_cost(125);
8542 format %{ "SUB $dst,$src" %}
8543 opcode(0x2B);
8544 ins_encode( OpcP, RegMem( dst, src) );
8545 ins_pipe( ialu_reg_mem );
8546 %}
8547
8548 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8549 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8550 effect(KILL cr);
8551
8552 ins_cost(150);
8553 format %{ "SUB $dst,$src" %}
8554 opcode(0x29); /* Opcode 29 /r */
8555 ins_encode( OpcP, RegMem( src, dst ) );
8556 ins_pipe( ialu_mem_reg );
8557 %}
8558
8559 // Subtract from a pointer
8560 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8561 match(Set dst (AddP dst (SubI zero src)));
8562 effect(KILL cr);
8563
8564 size(2);
8565 format %{ "SUB $dst,$src" %}
8566 opcode(0x2B);
8567 ins_encode( OpcP, RegReg( dst, src) );
8568 ins_pipe( ialu_reg_reg );
8569 %}
8570
8571 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8572 match(Set dst (SubI zero dst));
8573 effect(KILL cr);
8574
8575 size(2);
8576 format %{ "NEG $dst" %}
8577 opcode(0xF7,0x03); // Opcode F7 /3
8578 ins_encode( OpcP, RegOpc( dst ) );
8579 ins_pipe( ialu_reg );
8580 %}
8581
8582
8583 //----------Multiplication/Division Instructions-------------------------------
8584 // Integer Multiplication Instructions
8585 // Multiply Register
8586 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8587 match(Set dst (MulI dst src));
8588 effect(KILL cr);
8589
8590 size(3);
8591 ins_cost(300);
8592 format %{ "IMUL $dst,$src" %}
8593 opcode(0xAF, 0x0F);
8594 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8595 ins_pipe( ialu_reg_reg_alu0 );
8596 %}
8597
8598 // Multiply 32-bit Immediate
8599 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8600 match(Set dst (MulI src imm));
8601 effect(KILL cr);
8602
8603 ins_cost(300);
8604 format %{ "IMUL $dst,$src,$imm" %}
8605 opcode(0x69); /* 69 /r id */
8606 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8607 ins_pipe( ialu_reg_reg_alu0 );
8608 %}
8609
8610 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8611 match(Set dst src);
8612 effect(KILL cr);
8613
8614 // Note that this is artificially increased to make it more expensive than loadConL
8615 ins_cost(250);
8616 format %{ "MOV EAX,$src\t// low word only" %}
8617 opcode(0xB8);
8618 ins_encode( LdImmL_Lo(dst, src) );
8619 ins_pipe( ialu_reg_fat );
8620 %}
8621
8622 // Multiply by 32-bit Immediate, taking the shifted high order results
8623 // (special case for shift by 32)
8624 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8625 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8626 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8627 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8628 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8629 effect(USE src1, KILL cr);
8630
8631 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8632 ins_cost(0*100 + 1*400 - 150);
8633 format %{ "IMUL EDX:EAX,$src1" %}
8634 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8635 ins_pipe( pipe_slow );
8636 %}
8637
8638 // Multiply by 32-bit Immediate, taking the shifted high order results
8639 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8640 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8641 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8642 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8643 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8644 effect(USE src1, KILL cr);
8645
8646 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8647 ins_cost(1*100 + 1*400 - 150);
8648 format %{ "IMUL EDX:EAX,$src1\n\t"
8649 "SAR EDX,$cnt-32" %}
8650 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8651 ins_pipe( pipe_slow );
8652 %}
8653
8654 // Multiply Memory 32-bit Immediate
8655 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8656 match(Set dst (MulI (LoadI src) imm));
8657 effect(KILL cr);
8658
8659 ins_cost(300);
8660 format %{ "IMUL $dst,$src,$imm" %}
8661 opcode(0x69); /* 69 /r id */
8662 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8663 ins_pipe( ialu_reg_mem_alu0 );
8664 %}
8665
8666 // Multiply Memory
8667 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8668 match(Set dst (MulI dst (LoadI src)));
8669 effect(KILL cr);
8670
8671 ins_cost(350);
8672 format %{ "IMUL $dst,$src" %}
8673 opcode(0xAF, 0x0F);
8674 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8675 ins_pipe( ialu_reg_mem_alu0 );
8676 %}
8677
8678 // Multiply Register Int to Long
8679 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8680 // Basic Idea: long = (long)int * (long)int
8681 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8682 effect(DEF dst, USE src, USE src1, KILL flags);
8683
8684 ins_cost(300);
8685 format %{ "IMUL $dst,$src1" %}
8686
8687 ins_encode( long_int_multiply( dst, src1 ) );
8688 ins_pipe( ialu_reg_reg_alu0 );
8689 %}
8690
8691 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8692 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8693 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8694 effect(KILL flags);
8695
8696 ins_cost(300);
8697 format %{ "MUL $dst,$src1" %}
8698
8699 ins_encode( long_uint_multiply(dst, src1) );
8700 ins_pipe( ialu_reg_reg_alu0 );
8701 %}
8702
8703 // Multiply Register Long
8704 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8705 match(Set dst (MulL dst src));
8706 effect(KILL cr, TEMP tmp);
8707 ins_cost(4*100+3*400);
8708 // Basic idea: lo(result) = lo(x_lo * y_lo)
8709 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8710 format %{ "MOV $tmp,$src.lo\n\t"
8711 "IMUL $tmp,EDX\n\t"
8712 "MOV EDX,$src.hi\n\t"
8713 "IMUL EDX,EAX\n\t"
8714 "ADD $tmp,EDX\n\t"
8715 "MUL EDX:EAX,$src.lo\n\t"
8716 "ADD EDX,$tmp" %}
8717 ins_encode( long_multiply( dst, src, tmp ) );
8718 ins_pipe( pipe_slow );
8719 %}
8720
8721 // Multiply Register Long where the left operand's high 32 bits are zero
8722 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8723 predicate(is_operand_hi32_zero(n->in(1)));
8724 match(Set dst (MulL dst src));
8725 effect(KILL cr, TEMP tmp);
8726 ins_cost(2*100+2*400);
8727 // Basic idea: lo(result) = lo(x_lo * y_lo)
8728 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8729 format %{ "MOV $tmp,$src.hi\n\t"
8730 "IMUL $tmp,EAX\n\t"
8731 "MUL EDX:EAX,$src.lo\n\t"
8732 "ADD EDX,$tmp" %}
8733 ins_encode %{
8734 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8735 __ imull($tmp$$Register, rax);
8736 __ mull($src$$Register);
8737 __ addl(rdx, $tmp$$Register);
8738 %}
8739 ins_pipe( pipe_slow );
8740 %}
8741
8742 // Multiply Register Long where the right operand's high 32 bits are zero
8743 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8744 predicate(is_operand_hi32_zero(n->in(2)));
8745 match(Set dst (MulL dst src));
8746 effect(KILL cr, TEMP tmp);
8747 ins_cost(2*100+2*400);
8748 // Basic idea: lo(result) = lo(x_lo * y_lo)
8749 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8750 format %{ "MOV $tmp,$src.lo\n\t"
8751 "IMUL $tmp,EDX\n\t"
8752 "MUL EDX:EAX,$src.lo\n\t"
8753 "ADD EDX,$tmp" %}
8754 ins_encode %{
8755 __ movl($tmp$$Register, $src$$Register);
8756 __ imull($tmp$$Register, rdx);
8757 __ mull($src$$Register);
8758 __ addl(rdx, $tmp$$Register);
8759 %}
8760 ins_pipe( pipe_slow );
8761 %}
8762
8763 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8764 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8765 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8766 match(Set dst (MulL dst src));
8767 effect(KILL cr);
8768 ins_cost(1*400);
8769 // Basic idea: lo(result) = lo(x_lo * y_lo)
8770 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8771 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8772 ins_encode %{
8773 __ mull($src$$Register);
8774 %}
8775 ins_pipe( pipe_slow );
8776 %}
8777
8778 // Multiply Register Long by small constant
8779 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8780 match(Set dst (MulL dst src));
8781 effect(KILL cr, TEMP tmp);
8782 ins_cost(2*100+2*400);
8783 size(12);
8784 // Basic idea: lo(result) = lo(src * EAX)
8785 // hi(result) = hi(src * EAX) + lo(src * EDX)
8786 format %{ "IMUL $tmp,EDX,$src\n\t"
8787 "MOV EDX,$src\n\t"
8788 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8789 "ADD EDX,$tmp" %}
8790 ins_encode( long_multiply_con( dst, src, tmp ) );
8791 ins_pipe( pipe_slow );
8792 %}
8793
8794 // Integer DIV with Register
8795 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8796 match(Set rax (DivI rax div));
8797 effect(KILL rdx, KILL cr);
8798 size(26);
8799 ins_cost(30*100+10*100);
8800 format %{ "CMP EAX,0x80000000\n\t"
8801 "JNE,s normal\n\t"
8802 "XOR EDX,EDX\n\t"
8803 "CMP ECX,-1\n\t"
8804 "JE,s done\n"
8805 "normal: CDQ\n\t"
8806 "IDIV $div\n\t"
8807 "done:" %}
8808 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8809 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8810 ins_pipe( ialu_reg_reg_alu0 );
8811 %}
8812
8813 // Divide Register Long
8814 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8815 match(Set dst (DivL src1 src2));
8816 effect( KILL cr, KILL cx, KILL bx );
8817 ins_cost(10000);
8818 format %{ "PUSH $src1.hi\n\t"
8819 "PUSH $src1.lo\n\t"
8820 "PUSH $src2.hi\n\t"
8821 "PUSH $src2.lo\n\t"
8822 "CALL SharedRuntime::ldiv\n\t"
8823 "ADD ESP,16" %}
8824 ins_encode( long_div(src1,src2) );
8825 ins_pipe( pipe_slow );
8826 %}
8827
8828 // Integer DIVMOD with Register, both quotient and mod results
8829 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8830 match(DivModI rax div);
8831 effect(KILL cr);
8832 size(26);
8833 ins_cost(30*100+10*100);
8834 format %{ "CMP EAX,0x80000000\n\t"
8835 "JNE,s normal\n\t"
8836 "XOR EDX,EDX\n\t"
8837 "CMP ECX,-1\n\t"
8838 "JE,s done\n"
8839 "normal: CDQ\n\t"
8840 "IDIV $div\n\t"
8841 "done:" %}
8842 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8843 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8844 ins_pipe( pipe_slow );
8845 %}
8846
8847 // Integer MOD with Register
8848 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8849 match(Set rdx (ModI rax div));
8850 effect(KILL rax, KILL cr);
8851
8852 size(26);
8853 ins_cost(300);
8854 format %{ "CDQ\n\t"
8855 "IDIV $div" %}
8856 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8857 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8858 ins_pipe( ialu_reg_reg_alu0 );
8859 %}
8860
8861 // Remainder Register Long
8862 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8863 match(Set dst (ModL src1 src2));
8864 effect( KILL cr, KILL cx, KILL bx );
8865 ins_cost(10000);
8866 format %{ "PUSH $src1.hi\n\t"
8867 "PUSH $src1.lo\n\t"
8868 "PUSH $src2.hi\n\t"
8869 "PUSH $src2.lo\n\t"
8870 "CALL SharedRuntime::lrem\n\t"
8871 "ADD ESP,16" %}
8872 ins_encode( long_mod(src1,src2) );
8873 ins_pipe( pipe_slow );
8874 %}
8875
8876 // Divide Register Long (no special case since divisor != -1)
8877 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8878 match(Set dst (DivL dst imm));
8879 effect( TEMP tmp, TEMP tmp2, KILL cr );
8880 ins_cost(1000);
8881 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8882 "XOR $tmp2,$tmp2\n\t"
8883 "CMP $tmp,EDX\n\t"
8884 "JA,s fast\n\t"
8885 "MOV $tmp2,EAX\n\t"
8886 "MOV EAX,EDX\n\t"
8887 "MOV EDX,0\n\t"
8888 "JLE,s pos\n\t"
8889 "LNEG EAX : $tmp2\n\t"
8890 "DIV $tmp # unsigned division\n\t"
8891 "XCHG EAX,$tmp2\n\t"
8892 "DIV $tmp\n\t"
8893 "LNEG $tmp2 : EAX\n\t"
8894 "JMP,s done\n"
8895 "pos:\n\t"
8896 "DIV $tmp\n\t"
8897 "XCHG EAX,$tmp2\n"
8898 "fast:\n\t"
8899 "DIV $tmp\n"
8900 "done:\n\t"
8901 "MOV EDX,$tmp2\n\t"
8902 "NEG EDX:EAX # if $imm < 0" %}
8903 ins_encode %{
8904 int con = (int)$imm$$constant;
8905 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8906 int pcon = (con > 0) ? con : -con;
8907 Label Lfast, Lpos, Ldone;
8908
8909 __ movl($tmp$$Register, pcon);
8910 __ xorl($tmp2$$Register,$tmp2$$Register);
8911 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8912 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8913
8914 __ movl($tmp2$$Register, $dst$$Register); // save
8915 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8916 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8917 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8918
8919 // Negative dividend.
8920 // convert value to positive to use unsigned division
8921 __ lneg($dst$$Register, $tmp2$$Register);
8922 __ divl($tmp$$Register);
8923 __ xchgl($dst$$Register, $tmp2$$Register);
8924 __ divl($tmp$$Register);
8925 // revert result back to negative
8926 __ lneg($tmp2$$Register, $dst$$Register);
8927 __ jmpb(Ldone);
8928
8929 __ bind(Lpos);
8930 __ divl($tmp$$Register); // Use unsigned division
8931 __ xchgl($dst$$Register, $tmp2$$Register);
8932 // Fallthrow for final divide, tmp2 has 32 bit hi result
8933
8934 __ bind(Lfast);
8935 // fast path: src is positive
8936 __ divl($tmp$$Register); // Use unsigned division
8937
8938 __ bind(Ldone);
8939 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8940 if (con < 0) {
8941 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8942 }
8943 %}
8944 ins_pipe( pipe_slow );
8945 %}
8946
8947 // Remainder Register Long (remainder fit into 32 bits)
8948 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{
8949 match(Set dst (ModL dst imm));
8950 effect( TEMP tmp, TEMP tmp2, KILL cr );
8951 ins_cost(1000);
8952 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8953 "CMP $tmp,EDX\n\t"
8954 "JA,s fast\n\t"
8955 "MOV $tmp2,EAX\n\t"
8956 "MOV EAX,EDX\n\t"
8957 "MOV EDX,0\n\t"
8958 "JLE,s pos\n\t"
8959 "LNEG EAX : $tmp2\n\t"
8960 "DIV $tmp # unsigned division\n\t"
8961 "MOV EAX,$tmp2\n\t"
8962 "DIV $tmp\n\t"
8963 "NEG EDX\n\t"
8964 "JMP,s done\n"
8965 "pos:\n\t"
8966 "DIV $tmp\n\t"
8967 "MOV EAX,$tmp2\n"
8968 "fast:\n\t"
8969 "DIV $tmp\n"
8970 "done:\n\t"
8971 "MOV EAX,EDX\n\t"
8972 "SAR EDX,31\n\t" %}
8973 ins_encode %{
8974 int con = (int)$imm$$constant;
8975 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8976 int pcon = (con > 0) ? con : -con;
8977 Label Lfast, Lpos, Ldone;
8978
8979 __ movl($tmp$$Register, pcon);
8980 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8981 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8982
8983 __ movl($tmp2$$Register, $dst$$Register); // save
8984 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8985 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8986 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8987
8988 // Negative dividend.
8989 // convert value to positive to use unsigned division
8990 __ lneg($dst$$Register, $tmp2$$Register);
8991 __ divl($tmp$$Register);
8992 __ movl($dst$$Register, $tmp2$$Register);
8993 __ divl($tmp$$Register);
8994 // revert remainder back to negative
8995 __ negl(HIGH_FROM_LOW($dst$$Register));
8996 __ jmpb(Ldone);
8997
8998 __ bind(Lpos);
8999 __ divl($tmp$$Register);
9000 __ movl($dst$$Register, $tmp2$$Register);
9001
9002 __ bind(Lfast);
9003 // fast path: src is positive
9004 __ divl($tmp$$Register);
9005
9006 __ bind(Ldone);
9007 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
9008 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
9009
9010 %}
9011 ins_pipe( pipe_slow );
9012 %}
9013
9014 // Integer Shift Instructions
9015 // Shift Left by one
9016 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9017 match(Set dst (LShiftI dst shift));
9018 effect(KILL cr);
9019
9020 size(2);
9021 format %{ "SHL $dst,$shift" %}
9022 opcode(0xD1, 0x4); /* D1 /4 */
9023 ins_encode( OpcP, RegOpc( dst ) );
9024 ins_pipe( ialu_reg );
9025 %}
9026
9027 // Shift Left by 8-bit immediate
9028 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9029 match(Set dst (LShiftI dst shift));
9030 effect(KILL cr);
9031
9032 size(3);
9033 format %{ "SHL $dst,$shift" %}
9034 opcode(0xC1, 0x4); /* C1 /4 ib */
9035 ins_encode( RegOpcImm( dst, shift) );
9036 ins_pipe( ialu_reg );
9037 %}
9038
9039 // Shift Left by variable
9040 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9041 match(Set dst (LShiftI dst shift));
9042 effect(KILL cr);
9043
9044 size(2);
9045 format %{ "SHL $dst,$shift" %}
9046 opcode(0xD3, 0x4); /* D3 /4 */
9047 ins_encode( OpcP, RegOpc( dst ) );
9048 ins_pipe( ialu_reg_reg );
9049 %}
9050
9051 // Arithmetic shift right by one
9052 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9053 match(Set dst (RShiftI dst shift));
9054 effect(KILL cr);
9055
9056 size(2);
9057 format %{ "SAR $dst,$shift" %}
9058 opcode(0xD1, 0x7); /* D1 /7 */
9059 ins_encode( OpcP, RegOpc( dst ) );
9060 ins_pipe( ialu_reg );
9061 %}
9062
9063 // Arithmetic shift right by one
9064 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
9065 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9066 effect(KILL cr);
9067 format %{ "SAR $dst,$shift" %}
9068 opcode(0xD1, 0x7); /* D1 /7 */
9069 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
9070 ins_pipe( ialu_mem_imm );
9071 %}
9072
9073 // Arithmetic Shift Right by 8-bit immediate
9074 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9075 match(Set dst (RShiftI dst shift));
9076 effect(KILL cr);
9077
9078 size(3);
9079 format %{ "SAR $dst,$shift" %}
9080 opcode(0xC1, 0x7); /* C1 /7 ib */
9081 ins_encode( RegOpcImm( dst, shift ) );
9082 ins_pipe( ialu_mem_imm );
9083 %}
9084
9085 // Arithmetic Shift Right by 8-bit immediate
9086 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
9087 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9088 effect(KILL cr);
9089
9090 format %{ "SAR $dst,$shift" %}
9091 opcode(0xC1, 0x7); /* C1 /7 ib */
9092 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
9093 ins_pipe( ialu_mem_imm );
9094 %}
9095
9096 // Arithmetic Shift Right by variable
9097 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9098 match(Set dst (RShiftI dst shift));
9099 effect(KILL cr);
9100
9101 size(2);
9102 format %{ "SAR $dst,$shift" %}
9103 opcode(0xD3, 0x7); /* D3 /7 */
9104 ins_encode( OpcP, RegOpc( dst ) );
9105 ins_pipe( ialu_reg_reg );
9106 %}
9107
9108 // Logical shift right by one
9109 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9110 match(Set dst (URShiftI dst shift));
9111 effect(KILL cr);
9112
9113 size(2);
9114 format %{ "SHR $dst,$shift" %}
9115 opcode(0xD1, 0x5); /* D1 /5 */
9116 ins_encode( OpcP, RegOpc( dst ) );
9117 ins_pipe( ialu_reg );
9118 %}
9119
9120 // Logical Shift Right by 8-bit immediate
9121 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
9122 match(Set dst (URShiftI dst shift));
9123 effect(KILL cr);
9124
9125 size(3);
9126 format %{ "SHR $dst,$shift" %}
9127 opcode(0xC1, 0x5); /* C1 /5 ib */
9128 ins_encode( RegOpcImm( dst, shift) );
9129 ins_pipe( ialu_reg );
9130 %}
9131
9132
9133 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9134 // This idiom is used by the compiler for the i2b bytecode.
9135 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
9136 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9137
9138 size(3);
9139 format %{ "MOVSX $dst,$src :8" %}
9140 ins_encode %{
9141 __ movsbl($dst$$Register, $src$$Register);
9142 %}
9143 ins_pipe(ialu_reg_reg);
9144 %}
9145
9146 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9147 // This idiom is used by the compiler the i2s bytecode.
9148 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
9149 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9150
9151 size(3);
9152 format %{ "MOVSX $dst,$src :16" %}
9153 ins_encode %{
9154 __ movswl($dst$$Register, $src$$Register);
9155 %}
9156 ins_pipe(ialu_reg_reg);
9157 %}
9158
9159
9160 // Logical Shift Right by variable
9161 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9162 match(Set dst (URShiftI dst shift));
9163 effect(KILL cr);
9164
9165 size(2);
9166 format %{ "SHR $dst,$shift" %}
9167 opcode(0xD3, 0x5); /* D3 /5 */
9168 ins_encode( OpcP, RegOpc( dst ) );
9169 ins_pipe( ialu_reg_reg );
9170 %}
9171
9172
9173 //----------Logical Instructions-----------------------------------------------
9174 //----------Integer Logical Instructions---------------------------------------
9175 // And Instructions
9176 // And Register with Register
9177 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9178 match(Set dst (AndI dst src));
9179 effect(KILL cr);
9180
9181 size(2);
9182 format %{ "AND $dst,$src" %}
9183 opcode(0x23);
9184 ins_encode( OpcP, RegReg( dst, src) );
9185 ins_pipe( ialu_reg_reg );
9186 %}
9187
9188 // And Register with Immediate
9189 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9190 match(Set dst (AndI dst src));
9191 effect(KILL cr);
9192
9193 format %{ "AND $dst,$src" %}
9194 opcode(0x81,0x04); /* Opcode 81 /4 */
9195 // ins_encode( RegImm( dst, src) );
9196 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9197 ins_pipe( ialu_reg );
9198 %}
9199
9200 // And Register with Memory
9201 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9202 match(Set dst (AndI dst (LoadI src)));
9203 effect(KILL cr);
9204
9205 ins_cost(125);
9206 format %{ "AND $dst,$src" %}
9207 opcode(0x23);
9208 ins_encode( OpcP, RegMem( dst, src) );
9209 ins_pipe( ialu_reg_mem );
9210 %}
9211
9212 // And Memory with Register
9213 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9214 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9215 effect(KILL cr);
9216
9217 ins_cost(150);
9218 format %{ "AND $dst,$src" %}
9219 opcode(0x21); /* Opcode 21 /r */
9220 ins_encode( OpcP, RegMem( src, dst ) );
9221 ins_pipe( ialu_mem_reg );
9222 %}
9223
9224 // And Memory with Immediate
9225 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9226 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9227 effect(KILL cr);
9228
9229 ins_cost(125);
9230 format %{ "AND $dst,$src" %}
9231 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9232 // ins_encode( MemImm( dst, src) );
9233 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9234 ins_pipe( ialu_mem_imm );
9235 %}
9236
9237 // Or Instructions
9238 // Or Register with Register
9239 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9240 match(Set dst (OrI dst src));
9241 effect(KILL cr);
9242
9243 size(2);
9244 format %{ "OR $dst,$src" %}
9245 opcode(0x0B);
9246 ins_encode( OpcP, RegReg( dst, src) );
9247 ins_pipe( ialu_reg_reg );
9248 %}
9249
9250 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
9251 match(Set dst (OrI dst (CastP2X src)));
9252 effect(KILL cr);
9253
9254 size(2);
9255 format %{ "OR $dst,$src" %}
9256 opcode(0x0B);
9257 ins_encode( OpcP, RegReg( dst, src) );
9258 ins_pipe( ialu_reg_reg );
9259 %}
9260
9261
9262 // Or Register with Immediate
9263 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9264 match(Set dst (OrI dst src));
9265 effect(KILL cr);
9266
9267 format %{ "OR $dst,$src" %}
9268 opcode(0x81,0x01); /* Opcode 81 /1 id */
9269 // ins_encode( RegImm( dst, src) );
9270 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9271 ins_pipe( ialu_reg );
9272 %}
9273
9274 // Or Register with Memory
9275 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9276 match(Set dst (OrI dst (LoadI src)));
9277 effect(KILL cr);
9278
9279 ins_cost(125);
9280 format %{ "OR $dst,$src" %}
9281 opcode(0x0B);
9282 ins_encode( OpcP, RegMem( dst, src) );
9283 ins_pipe( ialu_reg_mem );
9284 %}
9285
9286 // Or Memory with Register
9287 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9288 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9289 effect(KILL cr);
9290
9291 ins_cost(150);
9292 format %{ "OR $dst,$src" %}
9293 opcode(0x09); /* Opcode 09 /r */
9294 ins_encode( OpcP, RegMem( src, dst ) );
9295 ins_pipe( ialu_mem_reg );
9296 %}
9297
9298 // Or Memory with Immediate
9299 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9300 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9301 effect(KILL cr);
9302
9303 ins_cost(125);
9304 format %{ "OR $dst,$src" %}
9305 opcode(0x81,0x1); /* Opcode 81 /1 id */
9306 // ins_encode( MemImm( dst, src) );
9307 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9308 ins_pipe( ialu_mem_imm );
9309 %}
9310
9311 // ROL/ROR
9312 // ROL expand
9313 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9314 effect(USE_DEF dst, USE shift, KILL cr);
9315
9316 format %{ "ROL $dst, $shift" %}
9317 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9318 ins_encode( OpcP, RegOpc( dst ));
9319 ins_pipe( ialu_reg );
9320 %}
9321
9322 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9323 effect(USE_DEF dst, USE shift, KILL cr);
9324
9325 format %{ "ROL $dst, $shift" %}
9326 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
9327 ins_encode( RegOpcImm(dst, shift) );
9328 ins_pipe(ialu_reg);
9329 %}
9330
9331 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
9332 effect(USE_DEF dst, USE shift, KILL cr);
9333
9334 format %{ "ROL $dst, $shift" %}
9335 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9336 ins_encode(OpcP, RegOpc(dst));
9337 ins_pipe( ialu_reg_reg );
9338 %}
9339 // end of ROL expand
9340
9341 // ROL 32bit by one once
9342 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
9343 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9344
9345 expand %{
9346 rolI_eReg_imm1(dst, lshift, cr);
9347 %}
9348 %}
9349
9350 // ROL 32bit var by imm8 once
9351 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
9352 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9353 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9354
9355 expand %{
9356 rolI_eReg_imm8(dst, lshift, cr);
9357 %}
9358 %}
9359
9360 // ROL 32bit var by var once
9361 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9362 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9363
9364 expand %{
9365 rolI_eReg_CL(dst, shift, cr);
9366 %}
9367 %}
9368
9369 // ROL 32bit var by var once
9370 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9371 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9372
9373 expand %{
9374 rolI_eReg_CL(dst, shift, cr);
9375 %}
9376 %}
9377
9378 // ROR expand
9379 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9380 effect(USE_DEF dst, USE shift, KILL cr);
9381
9382 format %{ "ROR $dst, $shift" %}
9383 opcode(0xD1,0x1); /* Opcode D1 /1 */
9384 ins_encode( OpcP, RegOpc( dst ) );
9385 ins_pipe( ialu_reg );
9386 %}
9387
9388 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9389 effect (USE_DEF dst, USE shift, KILL cr);
9390
9391 format %{ "ROR $dst, $shift" %}
9392 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9393 ins_encode( RegOpcImm(dst, shift) );
9394 ins_pipe( ialu_reg );
9395 %}
9396
9397 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9398 effect(USE_DEF dst, USE shift, KILL cr);
9399
9400 format %{ "ROR $dst, $shift" %}
9401 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9402 ins_encode(OpcP, RegOpc(dst));
9403 ins_pipe( ialu_reg_reg );
9404 %}
9405 // end of ROR expand
9406
9407 // ROR right once
9408 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9409 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9410
9411 expand %{
9412 rorI_eReg_imm1(dst, rshift, cr);
9413 %}
9414 %}
9415
9416 // ROR 32bit by immI8 once
9417 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9418 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9419 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9420
9421 expand %{
9422 rorI_eReg_imm8(dst, rshift, cr);
9423 %}
9424 %}
9425
9426 // ROR 32bit var by var once
9427 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9428 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9429
9430 expand %{
9431 rorI_eReg_CL(dst, shift, cr);
9432 %}
9433 %}
9434
9435 // ROR 32bit var by var once
9436 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9437 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9438
9439 expand %{
9440 rorI_eReg_CL(dst, shift, cr);
9441 %}
9442 %}
9443
9444 // Xor Instructions
9445 // Xor Register with Register
9446 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9447 match(Set dst (XorI dst src));
9448 effect(KILL cr);
9449
9450 size(2);
9451 format %{ "XOR $dst,$src" %}
9452 opcode(0x33);
9453 ins_encode( OpcP, RegReg( dst, src) );
9454 ins_pipe( ialu_reg_reg );
9455 %}
9456
9457 // Xor Register with Immediate -1
9458 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9459 match(Set dst (XorI dst imm));
9460
9461 size(2);
9462 format %{ "NOT $dst" %}
9463 ins_encode %{
9464 __ notl($dst$$Register);
9465 %}
9466 ins_pipe( ialu_reg );
9467 %}
9468
9469 // Xor Register with Immediate
9470 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9471 match(Set dst (XorI dst src));
9472 effect(KILL cr);
9473
9474 format %{ "XOR $dst,$src" %}
9475 opcode(0x81,0x06); /* Opcode 81 /6 id */
9476 // ins_encode( RegImm( dst, src) );
9477 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9478 ins_pipe( ialu_reg );
9479 %}
9480
9481 // Xor Register with Memory
9482 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9483 match(Set dst (XorI dst (LoadI src)));
9484 effect(KILL cr);
9485
9486 ins_cost(125);
9487 format %{ "XOR $dst,$src" %}
9488 opcode(0x33);
9489 ins_encode( OpcP, RegMem(dst, src) );
9490 ins_pipe( ialu_reg_mem );
9491 %}
9492
9493 // Xor Memory with Register
9494 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9495 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9496 effect(KILL cr);
9497
9498 ins_cost(150);
9499 format %{ "XOR $dst,$src" %}
9500 opcode(0x31); /* Opcode 31 /r */
9501 ins_encode( OpcP, RegMem( src, dst ) );
9502 ins_pipe( ialu_mem_reg );
9503 %}
9504
9505 // Xor Memory with Immediate
9506 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9507 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9508 effect(KILL cr);
9509
9510 ins_cost(125);
9511 format %{ "XOR $dst,$src" %}
9512 opcode(0x81,0x6); /* Opcode 81 /6 id */
9513 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9514 ins_pipe( ialu_mem_imm );
9515 %}
9516
9517 //----------Convert Int to Boolean---------------------------------------------
9518
9519 instruct movI_nocopy(eRegI dst, eRegI src) %{
9520 effect( DEF dst, USE src );
9521 format %{ "MOV $dst,$src" %}
9522 ins_encode( enc_Copy( dst, src) );
9523 ins_pipe( ialu_reg_reg );
9524 %}
9525
9526 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9527 effect( USE_DEF dst, USE src, KILL cr );
9528
9529 size(4);
9530 format %{ "NEG $dst\n\t"
9531 "ADC $dst,$src" %}
9532 ins_encode( neg_reg(dst),
9533 OpcRegReg(0x13,dst,src) );
9534 ins_pipe( ialu_reg_reg_long );
9535 %}
9536
9537 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9538 match(Set dst (Conv2B src));
9539
9540 expand %{
9541 movI_nocopy(dst,src);
9542 ci2b(dst,src,cr);
9543 %}
9544 %}
9545
9546 instruct movP_nocopy(eRegI dst, eRegP src) %{
9547 effect( DEF dst, USE src );
9548 format %{ "MOV $dst,$src" %}
9549 ins_encode( enc_Copy( dst, src) );
9550 ins_pipe( ialu_reg_reg );
9551 %}
9552
9553 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9554 effect( USE_DEF dst, USE src, KILL cr );
9555 format %{ "NEG $dst\n\t"
9556 "ADC $dst,$src" %}
9557 ins_encode( neg_reg(dst),
9558 OpcRegReg(0x13,dst,src) );
9559 ins_pipe( ialu_reg_reg_long );
9560 %}
9561
9562 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9563 match(Set dst (Conv2B src));
9564
9565 expand %{
9566 movP_nocopy(dst,src);
9567 cp2b(dst,src,cr);
9568 %}
9569 %}
9570
9571 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9572 match(Set dst (CmpLTMask p q));
9573 effect( KILL cr );
9574 ins_cost(400);
9575
9576 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9577 format %{ "XOR $dst,$dst\n\t"
9578 "CMP $p,$q\n\t"
9579 "SETlt $dst\n\t"
9580 "NEG $dst" %}
9581 ins_encode( OpcRegReg(0x33,dst,dst),
9582 OpcRegReg(0x3B,p,q),
9583 setLT_reg(dst), neg_reg(dst) );
9584 ins_pipe( pipe_slow );
9585 %}
9586
9587 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9588 match(Set dst (CmpLTMask dst zero));
9589 effect( DEF dst, KILL cr );
9590 ins_cost(100);
9591
9592 format %{ "SAR $dst,31" %}
9593 opcode(0xC1, 0x7); /* C1 /7 ib */
9594 ins_encode( RegOpcImm( dst, 0x1F ) );
9595 ins_pipe( ialu_reg );
9596 %}
9597
9598
9599 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9600 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9601 effect( KILL tmp, KILL cr );
9602 ins_cost(400);
9603 // annoyingly, $tmp has no edges so you cant ask for it in
9604 // any format or encoding
9605 format %{ "SUB $p,$q\n\t"
9606 "SBB ECX,ECX\n\t"
9607 "AND ECX,$y\n\t"
9608 "ADD $p,ECX" %}
9609 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9610 ins_pipe( pipe_cmplt );
9611 %}
9612
9613 /* If I enable this, I encourage spilling in the inner loop of compress.
9614 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9615 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9616 effect( USE_KILL tmp, KILL cr );
9617 ins_cost(400);
9618
9619 format %{ "SUB $p,$q\n\t"
9620 "SBB ECX,ECX\n\t"
9621 "AND ECX,$y\n\t"
9622 "ADD $p,ECX" %}
9623 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9624 %}
9625 */
9626
9627 //----------Long Instructions------------------------------------------------
9628 // Add Long Register with Register
9629 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9630 match(Set dst (AddL dst src));
9631 effect(KILL cr);
9632 ins_cost(200);
9633 format %{ "ADD $dst.lo,$src.lo\n\t"
9634 "ADC $dst.hi,$src.hi" %}
9635 opcode(0x03, 0x13);
9636 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9637 ins_pipe( ialu_reg_reg_long );
9638 %}
9639
9640 // Add Long Register with Immediate
9641 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9642 match(Set dst (AddL dst src));
9643 effect(KILL cr);
9644 format %{ "ADD $dst.lo,$src.lo\n\t"
9645 "ADC $dst.hi,$src.hi" %}
9646 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9647 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9648 ins_pipe( ialu_reg_long );
9649 %}
9650
9651 // Add Long Register with Memory
9652 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9653 match(Set dst (AddL dst (LoadL mem)));
9654 effect(KILL cr);
9655 ins_cost(125);
9656 format %{ "ADD $dst.lo,$mem\n\t"
9657 "ADC $dst.hi,$mem+4" %}
9658 opcode(0x03, 0x13);
9659 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9660 ins_pipe( ialu_reg_long_mem );
9661 %}
9662
9663 // Subtract Long Register with Register.
9664 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9665 match(Set dst (SubL dst src));
9666 effect(KILL cr);
9667 ins_cost(200);
9668 format %{ "SUB $dst.lo,$src.lo\n\t"
9669 "SBB $dst.hi,$src.hi" %}
9670 opcode(0x2B, 0x1B);
9671 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9672 ins_pipe( ialu_reg_reg_long );
9673 %}
9674
9675 // Subtract Long Register with Immediate
9676 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9677 match(Set dst (SubL dst src));
9678 effect(KILL cr);
9679 format %{ "SUB $dst.lo,$src.lo\n\t"
9680 "SBB $dst.hi,$src.hi" %}
9681 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9682 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9683 ins_pipe( ialu_reg_long );
9684 %}
9685
9686 // Subtract Long Register with Memory
9687 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9688 match(Set dst (SubL dst (LoadL mem)));
9689 effect(KILL cr);
9690 ins_cost(125);
9691 format %{ "SUB $dst.lo,$mem\n\t"
9692 "SBB $dst.hi,$mem+4" %}
9693 opcode(0x2B, 0x1B);
9694 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9695 ins_pipe( ialu_reg_long_mem );
9696 %}
9697
9698 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9699 match(Set dst (SubL zero dst));
9700 effect(KILL cr);
9701 ins_cost(300);
9702 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9703 ins_encode( neg_long(dst) );
9704 ins_pipe( ialu_reg_reg_long );
9705 %}
9706
9707 // And Long Register with Register
9708 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9709 match(Set dst (AndL dst src));
9710 effect(KILL cr);
9711 format %{ "AND $dst.lo,$src.lo\n\t"
9712 "AND $dst.hi,$src.hi" %}
9713 opcode(0x23,0x23);
9714 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9715 ins_pipe( ialu_reg_reg_long );
9716 %}
9717
9718 // And Long Register with Immediate
9719 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9720 match(Set dst (AndL dst src));
9721 effect(KILL cr);
9722 format %{ "AND $dst.lo,$src.lo\n\t"
9723 "AND $dst.hi,$src.hi" %}
9724 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9725 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9726 ins_pipe( ialu_reg_long );
9727 %}
9728
9729 // And Long Register with Memory
9730 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9731 match(Set dst (AndL dst (LoadL mem)));
9732 effect(KILL cr);
9733 ins_cost(125);
9734 format %{ "AND $dst.lo,$mem\n\t"
9735 "AND $dst.hi,$mem+4" %}
9736 opcode(0x23, 0x23);
9737 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9738 ins_pipe( ialu_reg_long_mem );
9739 %}
9740
9741 // Or Long Register with Register
9742 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9743 match(Set dst (OrL dst src));
9744 effect(KILL cr);
9745 format %{ "OR $dst.lo,$src.lo\n\t"
9746 "OR $dst.hi,$src.hi" %}
9747 opcode(0x0B,0x0B);
9748 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9749 ins_pipe( ialu_reg_reg_long );
9750 %}
9751
9752 // Or Long Register with Immediate
9753 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9754 match(Set dst (OrL dst src));
9755 effect(KILL cr);
9756 format %{ "OR $dst.lo,$src.lo\n\t"
9757 "OR $dst.hi,$src.hi" %}
9758 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9759 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9760 ins_pipe( ialu_reg_long );
9761 %}
9762
9763 // Or Long Register with Memory
9764 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9765 match(Set dst (OrL dst (LoadL mem)));
9766 effect(KILL cr);
9767 ins_cost(125);
9768 format %{ "OR $dst.lo,$mem\n\t"
9769 "OR $dst.hi,$mem+4" %}
9770 opcode(0x0B,0x0B);
9771 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9772 ins_pipe( ialu_reg_long_mem );
9773 %}
9774
9775 // Xor Long Register with Register
9776 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9777 match(Set dst (XorL dst src));
9778 effect(KILL cr);
9779 format %{ "XOR $dst.lo,$src.lo\n\t"
9780 "XOR $dst.hi,$src.hi" %}
9781 opcode(0x33,0x33);
9782 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9783 ins_pipe( ialu_reg_reg_long );
9784 %}
9785
9786 // Xor Long Register with Immediate -1
9787 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9788 match(Set dst (XorL dst imm));
9789 format %{ "NOT $dst.lo\n\t"
9790 "NOT $dst.hi" %}
9791 ins_encode %{
9792 __ notl($dst$$Register);
9793 __ notl(HIGH_FROM_LOW($dst$$Register));
9794 %}
9795 ins_pipe( ialu_reg_long );
9796 %}
9797
9798 // Xor Long Register with Immediate
9799 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9800 match(Set dst (XorL dst src));
9801 effect(KILL cr);
9802 format %{ "XOR $dst.lo,$src.lo\n\t"
9803 "XOR $dst.hi,$src.hi" %}
9804 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9805 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9806 ins_pipe( ialu_reg_long );
9807 %}
9808
9809 // Xor Long Register with Memory
9810 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9811 match(Set dst (XorL dst (LoadL mem)));
9812 effect(KILL cr);
9813 ins_cost(125);
9814 format %{ "XOR $dst.lo,$mem\n\t"
9815 "XOR $dst.hi,$mem+4" %}
9816 opcode(0x33,0x33);
9817 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9818 ins_pipe( ialu_reg_long_mem );
9819 %}
9820
9821 // Shift Left Long by 1
9822 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9823 predicate(UseNewLongLShift);
9824 match(Set dst (LShiftL dst cnt));
9825 effect(KILL cr);
9826 ins_cost(100);
9827 format %{ "ADD $dst.lo,$dst.lo\n\t"
9828 "ADC $dst.hi,$dst.hi" %}
9829 ins_encode %{
9830 __ addl($dst$$Register,$dst$$Register);
9831 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9832 %}
9833 ins_pipe( ialu_reg_long );
9834 %}
9835
9836 // Shift Left Long by 2
9837 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9838 predicate(UseNewLongLShift);
9839 match(Set dst (LShiftL dst cnt));
9840 effect(KILL cr);
9841 ins_cost(100);
9842 format %{ "ADD $dst.lo,$dst.lo\n\t"
9843 "ADC $dst.hi,$dst.hi\n\t"
9844 "ADD $dst.lo,$dst.lo\n\t"
9845 "ADC $dst.hi,$dst.hi" %}
9846 ins_encode %{
9847 __ addl($dst$$Register,$dst$$Register);
9848 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9849 __ addl($dst$$Register,$dst$$Register);
9850 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9851 %}
9852 ins_pipe( ialu_reg_long );
9853 %}
9854
9855 // Shift Left Long by 3
9856 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9857 predicate(UseNewLongLShift);
9858 match(Set dst (LShiftL dst cnt));
9859 effect(KILL cr);
9860 ins_cost(100);
9861 format %{ "ADD $dst.lo,$dst.lo\n\t"
9862 "ADC $dst.hi,$dst.hi\n\t"
9863 "ADD $dst.lo,$dst.lo\n\t"
9864 "ADC $dst.hi,$dst.hi\n\t"
9865 "ADD $dst.lo,$dst.lo\n\t"
9866 "ADC $dst.hi,$dst.hi" %}
9867 ins_encode %{
9868 __ addl($dst$$Register,$dst$$Register);
9869 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9870 __ addl($dst$$Register,$dst$$Register);
9871 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9872 __ addl($dst$$Register,$dst$$Register);
9873 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9874 %}
9875 ins_pipe( ialu_reg_long );
9876 %}
9877
9878 // Shift Left Long by 1-31
9879 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9880 match(Set dst (LShiftL dst cnt));
9881 effect(KILL cr);
9882 ins_cost(200);
9883 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9884 "SHL $dst.lo,$cnt" %}
9885 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9886 ins_encode( move_long_small_shift(dst,cnt) );
9887 ins_pipe( ialu_reg_long );
9888 %}
9889
9890 // Shift Left Long by 32-63
9891 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9892 match(Set dst (LShiftL dst cnt));
9893 effect(KILL cr);
9894 ins_cost(300);
9895 format %{ "MOV $dst.hi,$dst.lo\n"
9896 "\tSHL $dst.hi,$cnt-32\n"
9897 "\tXOR $dst.lo,$dst.lo" %}
9898 opcode(0xC1, 0x4); /* C1 /4 ib */
9899 ins_encode( move_long_big_shift_clr(dst,cnt) );
9900 ins_pipe( ialu_reg_long );
9901 %}
9902
9903 // Shift Left Long by variable
9904 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9905 match(Set dst (LShiftL dst shift));
9906 effect(KILL cr);
9907 ins_cost(500+200);
9908 size(17);
9909 format %{ "TEST $shift,32\n\t"
9910 "JEQ,s small\n\t"
9911 "MOV $dst.hi,$dst.lo\n\t"
9912 "XOR $dst.lo,$dst.lo\n"
9913 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9914 "SHL $dst.lo,$shift" %}
9915 ins_encode( shift_left_long( dst, shift ) );
9916 ins_pipe( pipe_slow );
9917 %}
9918
9919 // Shift Right Long by 1-31
9920 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9921 match(Set dst (URShiftL dst cnt));
9922 effect(KILL cr);
9923 ins_cost(200);
9924 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9925 "SHR $dst.hi,$cnt" %}
9926 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9927 ins_encode( move_long_small_shift(dst,cnt) );
9928 ins_pipe( ialu_reg_long );
9929 %}
9930
9931 // Shift Right Long by 32-63
9932 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9933 match(Set dst (URShiftL dst cnt));
9934 effect(KILL cr);
9935 ins_cost(300);
9936 format %{ "MOV $dst.lo,$dst.hi\n"
9937 "\tSHR $dst.lo,$cnt-32\n"
9938 "\tXOR $dst.hi,$dst.hi" %}
9939 opcode(0xC1, 0x5); /* C1 /5 ib */
9940 ins_encode( move_long_big_shift_clr(dst,cnt) );
9941 ins_pipe( ialu_reg_long );
9942 %}
9943
9944 // Shift Right Long by variable
9945 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9946 match(Set dst (URShiftL dst shift));
9947 effect(KILL cr);
9948 ins_cost(600);
9949 size(17);
9950 format %{ "TEST $shift,32\n\t"
9951 "JEQ,s small\n\t"
9952 "MOV $dst.lo,$dst.hi\n\t"
9953 "XOR $dst.hi,$dst.hi\n"
9954 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9955 "SHR $dst.hi,$shift" %}
9956 ins_encode( shift_right_long( dst, shift ) );
9957 ins_pipe( pipe_slow );
9958 %}
9959
9960 // Shift Right Long by 1-31
9961 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9962 match(Set dst (RShiftL dst cnt));
9963 effect(KILL cr);
9964 ins_cost(200);
9965 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9966 "SAR $dst.hi,$cnt" %}
9967 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9968 ins_encode( move_long_small_shift(dst,cnt) );
9969 ins_pipe( ialu_reg_long );
9970 %}
9971
9972 // Shift Right Long by 32-63
9973 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9974 match(Set dst (RShiftL dst cnt));
9975 effect(KILL cr);
9976 ins_cost(300);
9977 format %{ "MOV $dst.lo,$dst.hi\n"
9978 "\tSAR $dst.lo,$cnt-32\n"
9979 "\tSAR $dst.hi,31" %}
9980 opcode(0xC1, 0x7); /* C1 /7 ib */
9981 ins_encode( move_long_big_shift_sign(dst,cnt) );
9982 ins_pipe( ialu_reg_long );
9983 %}
9984
9985 // Shift Right arithmetic Long by variable
9986 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9987 match(Set dst (RShiftL dst shift));
9988 effect(KILL cr);
9989 ins_cost(600);
9990 size(18);
9991 format %{ "TEST $shift,32\n\t"
9992 "JEQ,s small\n\t"
9993 "MOV $dst.lo,$dst.hi\n\t"
9994 "SAR $dst.hi,31\n"
9995 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9996 "SAR $dst.hi,$shift" %}
9997 ins_encode( shift_right_arith_long( dst, shift ) );
9998 ins_pipe( pipe_slow );
9999 %}
10000
10001
10002 //----------Double Instructions------------------------------------------------
10003 // Double Math
10004
10005 // Compare & branch
10006
10007 // P6 version of float compare, sets condition codes in EFLAGS
10008 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
10009 predicate(VM_Version::supports_cmov() && UseSSE <=1);
10010 match(Set cr (CmpD src1 src2));
10011 effect(KILL rax);
10012 ins_cost(150);
10013 format %{ "FLD $src1\n\t"
10014 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10015 "JNP exit\n\t"
10016 "MOV ah,1 // saw a NaN, set CF\n\t"
10017 "SAHF\n"
10018 "exit:\tNOP // avoid branch to branch" %}
10019 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10020 ins_encode( Push_Reg_D(src1),
10021 OpcP, RegOpc(src2),
10022 cmpF_P6_fixup );
10023 ins_pipe( pipe_slow );
10024 %}
10025
10026 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
10027 predicate(VM_Version::supports_cmov() && UseSSE <=1);
10028 match(Set cr (CmpD src1 src2));
10029 ins_cost(150);
10030 format %{ "FLD $src1\n\t"
10031 "FUCOMIP ST,$src2 // P6 instruction" %}
10032 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10033 ins_encode( Push_Reg_D(src1),
10034 OpcP, RegOpc(src2));
10035 ins_pipe( pipe_slow );
10036 %}
10037
10038 // Compare & branch
10039 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
10040 predicate(UseSSE<=1);
10041 match(Set cr (CmpD src1 src2));
10042 effect(KILL rax);
10043 ins_cost(200);
10044 format %{ "FLD $src1\n\t"
10045 "FCOMp $src2\n\t"
10046 "FNSTSW AX\n\t"
10047 "TEST AX,0x400\n\t"
10048 "JZ,s flags\n\t"
10049 "MOV AH,1\t# unordered treat as LT\n"
10050 "flags:\tSAHF" %}
10051 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10052 ins_encode( Push_Reg_D(src1),
10053 OpcP, RegOpc(src2),
10054 fpu_flags);
10055 ins_pipe( pipe_slow );
10056 %}
10057
10058 // Compare vs zero into -1,0,1
10059 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
10060 predicate(UseSSE<=1);
10061 match(Set dst (CmpD3 src1 zero));
10062 effect(KILL cr, KILL rax);
10063 ins_cost(280);
10064 format %{ "FTSTD $dst,$src1" %}
10065 opcode(0xE4, 0xD9);
10066 ins_encode( Push_Reg_D(src1),
10067 OpcS, OpcP, PopFPU,
10068 CmpF_Result(dst));
10069 ins_pipe( pipe_slow );
10070 %}
10071
10072 // Compare into -1,0,1
10073 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
10074 predicate(UseSSE<=1);
10075 match(Set dst (CmpD3 src1 src2));
10076 effect(KILL cr, KILL rax);
10077 ins_cost(300);
10078 format %{ "FCMPD $dst,$src1,$src2" %}
10079 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10080 ins_encode( Push_Reg_D(src1),
10081 OpcP, RegOpc(src2),
10082 CmpF_Result(dst));
10083 ins_pipe( pipe_slow );
10084 %}
10085
10086 // float compare and set condition codes in EFLAGS by XMM regs
10087 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
10088 predicate(UseSSE>=2);
10089 match(Set cr (CmpD dst src));
10090 effect(KILL rax);
10091 ins_cost(125);
10092 format %{ "COMISD $dst,$src\n"
10093 "\tJNP exit\n"
10094 "\tMOV ah,1 // saw a NaN, set CF\n"
10095 "\tSAHF\n"
10096 "exit:\tNOP // avoid branch to branch" %}
10097 opcode(0x66, 0x0F, 0x2F);
10098 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
10099 ins_pipe( pipe_slow );
10100 %}
10101
10102 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
10103 predicate(UseSSE>=2);
10104 match(Set cr (CmpD dst src));
10105 ins_cost(100);
10106 format %{ "COMISD $dst,$src" %}
10107 opcode(0x66, 0x0F, 0x2F);
10108 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10109 ins_pipe( pipe_slow );
10110 %}
10111
10112 // float compare and set condition codes in EFLAGS by XMM regs
10113 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
10114 predicate(UseSSE>=2);
10115 match(Set cr (CmpD dst (LoadD src)));
10116 effect(KILL rax);
10117 ins_cost(145);
10118 format %{ "COMISD $dst,$src\n"
10119 "\tJNP exit\n"
10120 "\tMOV ah,1 // saw a NaN, set CF\n"
10121 "\tSAHF\n"
10122 "exit:\tNOP // avoid branch to branch" %}
10123 opcode(0x66, 0x0F, 0x2F);
10124 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
10125 ins_pipe( pipe_slow );
10126 %}
10127
10128 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
10129 predicate(UseSSE>=2);
10130 match(Set cr (CmpD dst (LoadD src)));
10131 ins_cost(100);
10132 format %{ "COMISD $dst,$src" %}
10133 opcode(0x66, 0x0F, 0x2F);
10134 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
10135 ins_pipe( pipe_slow );
10136 %}
10137
10138 // Compare into -1,0,1 in XMM
10139 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
10140 predicate(UseSSE>=2);
10141 match(Set dst (CmpD3 src1 src2));
10142 effect(KILL cr);
10143 ins_cost(255);
10144 format %{ "XOR $dst,$dst\n"
10145 "\tCOMISD $src1,$src2\n"
10146 "\tJP,s nan\n"
10147 "\tJEQ,s exit\n"
10148 "\tJA,s inc\n"
10149 "nan:\tDEC $dst\n"
10150 "\tJMP,s exit\n"
10151 "inc:\tINC $dst\n"
10152 "exit:"
10153 %}
10154 opcode(0x66, 0x0F, 0x2F);
10155 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
10156 CmpX_Result(dst));
10157 ins_pipe( pipe_slow );
10158 %}
10159
10160 // Compare into -1,0,1 in XMM and memory
10161 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
10162 predicate(UseSSE>=2);
10163 match(Set dst (CmpD3 src1 (LoadD mem)));
10164 effect(KILL cr);
10165 ins_cost(275);
10166 format %{ "COMISD $src1,$mem\n"
10167 "\tMOV $dst,0\t\t# do not blow flags\n"
10168 "\tJP,s nan\n"
10169 "\tJEQ,s exit\n"
10170 "\tJA,s inc\n"
10171 "nan:\tDEC $dst\n"
10172 "\tJMP,s exit\n"
10173 "inc:\tINC $dst\n"
10174 "exit:"
10175 %}
10176 opcode(0x66, 0x0F, 0x2F);
10177 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
10178 LdImmI(dst,0x0), CmpX_Result(dst));
10179 ins_pipe( pipe_slow );
10180 %}
10181
10182
10183 instruct subD_reg(regD dst, regD src) %{
10184 predicate (UseSSE <=1);
10185 match(Set dst (SubD dst src));
10186
10187 format %{ "FLD $src\n\t"
10188 "DSUBp $dst,ST" %}
10189 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10190 ins_cost(150);
10191 ins_encode( Push_Reg_D(src),
10192 OpcP, RegOpc(dst) );
10193 ins_pipe( fpu_reg_reg );
10194 %}
10195
10196 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10197 predicate (UseSSE <=1);
10198 match(Set dst (RoundDouble (SubD src1 src2)));
10199 ins_cost(250);
10200
10201 format %{ "FLD $src2\n\t"
10202 "DSUB ST,$src1\n\t"
10203 "FSTP_D $dst\t# D-round" %}
10204 opcode(0xD8, 0x5);
10205 ins_encode( Push_Reg_D(src2),
10206 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10207 ins_pipe( fpu_mem_reg_reg );
10208 %}
10209
10210
10211 instruct subD_reg_mem(regD dst, memory src) %{
10212 predicate (UseSSE <=1);
10213 match(Set dst (SubD dst (LoadD src)));
10214 ins_cost(150);
10215
10216 format %{ "FLD $src\n\t"
10217 "DSUBp $dst,ST" %}
10218 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10219 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10220 OpcP, RegOpc(dst) );
10221 ins_pipe( fpu_reg_mem );
10222 %}
10223
10224 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
10225 predicate (UseSSE<=1);
10226 match(Set dst (AbsD src));
10227 ins_cost(100);
10228 format %{ "FABS" %}
10229 opcode(0xE1, 0xD9);
10230 ins_encode( OpcS, OpcP );
10231 ins_pipe( fpu_reg_reg );
10232 %}
10233
10234 instruct absXD_reg( regXD dst ) %{
10235 predicate(UseSSE>=2);
10236 match(Set dst (AbsD dst));
10237 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
10238 ins_encode( AbsXD_encoding(dst));
10239 ins_pipe( pipe_slow );
10240 %}
10241
10242 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
10243 predicate(UseSSE<=1);
10244 match(Set dst (NegD src));
10245 ins_cost(100);
10246 format %{ "FCHS" %}
10247 opcode(0xE0, 0xD9);
10248 ins_encode( OpcS, OpcP );
10249 ins_pipe( fpu_reg_reg );
10250 %}
10251
10252 instruct negXD_reg( regXD dst ) %{
10253 predicate(UseSSE>=2);
10254 match(Set dst (NegD dst));
10255 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
10256 ins_encode %{
10257 __ xorpd($dst$$XMMRegister,
10258 ExternalAddress((address)double_signflip_pool));
10259 %}
10260 ins_pipe( pipe_slow );
10261 %}
10262
10263 instruct addD_reg(regD dst, regD src) %{
10264 predicate(UseSSE<=1);
10265 match(Set dst (AddD dst src));
10266 format %{ "FLD $src\n\t"
10267 "DADD $dst,ST" %}
10268 size(4);
10269 ins_cost(150);
10270 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10271 ins_encode( Push_Reg_D(src),
10272 OpcP, RegOpc(dst) );
10273 ins_pipe( fpu_reg_reg );
10274 %}
10275
10276
10277 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10278 predicate(UseSSE<=1);
10279 match(Set dst (RoundDouble (AddD src1 src2)));
10280 ins_cost(250);
10281
10282 format %{ "FLD $src2\n\t"
10283 "DADD ST,$src1\n\t"
10284 "FSTP_D $dst\t# D-round" %}
10285 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
10286 ins_encode( Push_Reg_D(src2),
10287 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10288 ins_pipe( fpu_mem_reg_reg );
10289 %}
10290
10291
10292 instruct addD_reg_mem(regD dst, memory src) %{
10293 predicate(UseSSE<=1);
10294 match(Set dst (AddD dst (LoadD src)));
10295 ins_cost(150);
10296
10297 format %{ "FLD $src\n\t"
10298 "DADDp $dst,ST" %}
10299 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10300 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10301 OpcP, RegOpc(dst) );
10302 ins_pipe( fpu_reg_mem );
10303 %}
10304
10305 // add-to-memory
10306 instruct addD_mem_reg(memory dst, regD src) %{
10307 predicate(UseSSE<=1);
10308 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
10309 ins_cost(150);
10310
10311 format %{ "FLD_D $dst\n\t"
10312 "DADD ST,$src\n\t"
10313 "FST_D $dst" %}
10314 opcode(0xDD, 0x0);
10315 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10316 Opcode(0xD8), RegOpc(src),
10317 set_instruction_start,
10318 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10319 ins_pipe( fpu_reg_mem );
10320 %}
10321
10322 instruct addD_reg_imm1(regD dst, immD1 con) %{
10323 predicate(UseSSE<=1);
10324 match(Set dst (AddD dst con));
10325 ins_cost(125);
10326 format %{ "FLD1\n\t"
10327 "DADDp $dst,ST" %}
10328 ins_encode %{
10329 __ fld1();
10330 __ faddp($dst$$reg);
10331 %}
10332 ins_pipe(fpu_reg);
10333 %}
10334
10335 instruct addD_reg_imm(regD dst, immD con) %{
10336 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10337 match(Set dst (AddD dst con));
10338 ins_cost(200);
10339 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
10340 "DADDp $dst,ST" %}
10341 ins_encode %{
10342 __ fld_d($constantaddress($con));
10343 __ faddp($dst$$reg);
10344 %}
10345 ins_pipe(fpu_reg_mem);
10346 %}
10347
10348 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
10349 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10350 match(Set dst (RoundDouble (AddD src con)));
10351 ins_cost(200);
10352 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
10353 "DADD ST,$src\n\t"
10354 "FSTP_D $dst\t# D-round" %}
10355 ins_encode %{
10356 __ fld_d($constantaddress($con));
10357 __ fadd($src$$reg);
10358 __ fstp_d(Address(rsp, $dst$$disp));
10359 %}
10360 ins_pipe(fpu_mem_reg_con);
10361 %}
10362
10363 // Add two double precision floating point values in xmm
10364 instruct addXD_reg(regXD dst, regXD src) %{
10365 predicate(UseSSE>=2);
10366 match(Set dst (AddD dst src));
10367 format %{ "ADDSD $dst,$src" %}
10368 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10369 ins_pipe( pipe_slow );
10370 %}
10371
10372 instruct addXD_imm(regXD dst, immXD con) %{
10373 predicate(UseSSE>=2);
10374 match(Set dst (AddD dst con));
10375 format %{ "ADDSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
10376 ins_encode %{
10377 __ addsd($dst$$XMMRegister, $constantaddress($con));
10378 %}
10379 ins_pipe(pipe_slow);
10380 %}
10381
10382 instruct addXD_mem(regXD dst, memory mem) %{
10383 predicate(UseSSE>=2);
10384 match(Set dst (AddD dst (LoadD mem)));
10385 format %{ "ADDSD $dst,$mem" %}
10386 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10387 ins_pipe( pipe_slow );
10388 %}
10389
10390 // Sub two double precision floating point values in xmm
10391 instruct subXD_reg(regXD dst, regXD src) %{
10392 predicate(UseSSE>=2);
10393 match(Set dst (SubD dst src));
10394 format %{ "SUBSD $dst,$src" %}
10395 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10396 ins_pipe( pipe_slow );
10397 %}
10398
10399 instruct subXD_imm(regXD dst, immXD con) %{
10400 predicate(UseSSE>=2);
10401 match(Set dst (SubD dst con));
10402 format %{ "SUBSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
10403 ins_encode %{
10404 __ subsd($dst$$XMMRegister, $constantaddress($con));
10405 %}
10406 ins_pipe(pipe_slow);
10407 %}
10408
10409 instruct subXD_mem(regXD dst, memory mem) %{
10410 predicate(UseSSE>=2);
10411 match(Set dst (SubD dst (LoadD mem)));
10412 format %{ "SUBSD $dst,$mem" %}
10413 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10414 ins_pipe( pipe_slow );
10415 %}
10416
10417 // Mul two double precision floating point values in xmm
10418 instruct mulXD_reg(regXD dst, regXD src) %{
10419 predicate(UseSSE>=2);
10420 match(Set dst (MulD dst src));
10421 format %{ "MULSD $dst,$src" %}
10422 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10423 ins_pipe( pipe_slow );
10424 %}
10425
10426 instruct mulXD_imm(regXD dst, immXD con) %{
10427 predicate(UseSSE>=2);
10428 match(Set dst (MulD dst con));
10429 format %{ "MULSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
10430 ins_encode %{
10431 __ mulsd($dst$$XMMRegister, $constantaddress($con));
10432 %}
10433 ins_pipe(pipe_slow);
10434 %}
10435
10436 instruct mulXD_mem(regXD dst, memory mem) %{
10437 predicate(UseSSE>=2);
10438 match(Set dst (MulD dst (LoadD mem)));
10439 format %{ "MULSD $dst,$mem" %}
10440 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10441 ins_pipe( pipe_slow );
10442 %}
10443
10444 // Div two double precision floating point values in xmm
10445 instruct divXD_reg(regXD dst, regXD src) %{
10446 predicate(UseSSE>=2);
10447 match(Set dst (DivD dst src));
10448 format %{ "DIVSD $dst,$src" %}
10449 opcode(0xF2, 0x0F, 0x5E);
10450 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10451 ins_pipe( pipe_slow );
10452 %}
10453
10454 instruct divXD_imm(regXD dst, immXD con) %{
10455 predicate(UseSSE>=2);
10456 match(Set dst (DivD dst con));
10457 format %{ "DIVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
10458 ins_encode %{
10459 __ divsd($dst$$XMMRegister, $constantaddress($con));
10460 %}
10461 ins_pipe(pipe_slow);
10462 %}
10463
10464 instruct divXD_mem(regXD dst, memory mem) %{
10465 predicate(UseSSE>=2);
10466 match(Set dst (DivD dst (LoadD mem)));
10467 format %{ "DIVSD $dst,$mem" %}
10468 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10469 ins_pipe( pipe_slow );
10470 %}
10471
10472
10473 instruct mulD_reg(regD dst, regD src) %{
10474 predicate(UseSSE<=1);
10475 match(Set dst (MulD dst src));
10476 format %{ "FLD $src\n\t"
10477 "DMULp $dst,ST" %}
10478 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10479 ins_cost(150);
10480 ins_encode( Push_Reg_D(src),
10481 OpcP, RegOpc(dst) );
10482 ins_pipe( fpu_reg_reg );
10483 %}
10484
10485 // Strict FP instruction biases argument before multiply then
10486 // biases result to avoid double rounding of subnormals.
10487 //
10488 // scale arg1 by multiplying arg1 by 2^(-15360)
10489 // load arg2
10490 // multiply scaled arg1 by arg2
10491 // rescale product by 2^(15360)
10492 //
10493 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10494 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10495 match(Set dst (MulD dst src));
10496 ins_cost(1); // Select this instruction for all strict FP double multiplies
10497
10498 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10499 "DMULp $dst,ST\n\t"
10500 "FLD $src\n\t"
10501 "DMULp $dst,ST\n\t"
10502 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10503 "DMULp $dst,ST\n\t" %}
10504 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10505 ins_encode( strictfp_bias1(dst),
10506 Push_Reg_D(src),
10507 OpcP, RegOpc(dst),
10508 strictfp_bias2(dst) );
10509 ins_pipe( fpu_reg_reg );
10510 %}
10511
10512 instruct mulD_reg_imm(regD dst, immD con) %{
10513 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10514 match(Set dst (MulD dst con));
10515 ins_cost(200);
10516 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
10517 "DMULp $dst,ST" %}
10518 ins_encode %{
10519 __ fld_d($constantaddress($con));
10520 __ fmulp($dst$$reg);
10521 %}
10522 ins_pipe(fpu_reg_mem);
10523 %}
10524
10525
10526 instruct mulD_reg_mem(regD dst, memory src) %{
10527 predicate( UseSSE<=1 );
10528 match(Set dst (MulD dst (LoadD src)));
10529 ins_cost(200);
10530 format %{ "FLD_D $src\n\t"
10531 "DMULp $dst,ST" %}
10532 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10533 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10534 OpcP, RegOpc(dst) );
10535 ins_pipe( fpu_reg_mem );
10536 %}
10537
10538 //
10539 // Cisc-alternate to reg-reg multiply
10540 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10541 predicate( UseSSE<=1 );
10542 match(Set dst (MulD src (LoadD mem)));
10543 ins_cost(250);
10544 format %{ "FLD_D $mem\n\t"
10545 "DMUL ST,$src\n\t"
10546 "FSTP_D $dst" %}
10547 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10548 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10549 OpcReg_F(src),
10550 Pop_Reg_D(dst) );
10551 ins_pipe( fpu_reg_reg_mem );
10552 %}
10553
10554
10555 // MACRO3 -- addD a mulD
10556 // This instruction is a '2-address' instruction in that the result goes
10557 // back to src2. This eliminates a move from the macro; possibly the
10558 // register allocator will have to add it back (and maybe not).
10559 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10560 predicate( UseSSE<=1 );
10561 match(Set src2 (AddD (MulD src0 src1) src2));
10562 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10563 "DMUL ST,$src1\n\t"
10564 "DADDp $src2,ST" %}
10565 ins_cost(250);
10566 opcode(0xDD); /* LoadD DD /0 */
10567 ins_encode( Push_Reg_F(src0),
10568 FMul_ST_reg(src1),
10569 FAddP_reg_ST(src2) );
10570 ins_pipe( fpu_reg_reg_reg );
10571 %}
10572
10573
10574 // MACRO3 -- subD a mulD
10575 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10576 predicate( UseSSE<=1 );
10577 match(Set src2 (SubD (MulD src0 src1) src2));
10578 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10579 "DMUL ST,$src1\n\t"
10580 "DSUBRp $src2,ST" %}
10581 ins_cost(250);
10582 ins_encode( Push_Reg_F(src0),
10583 FMul_ST_reg(src1),
10584 Opcode(0xDE), Opc_plus(0xE0,src2));
10585 ins_pipe( fpu_reg_reg_reg );
10586 %}
10587
10588
10589 instruct divD_reg(regD dst, regD src) %{
10590 predicate( UseSSE<=1 );
10591 match(Set dst (DivD dst src));
10592
10593 format %{ "FLD $src\n\t"
10594 "FDIVp $dst,ST" %}
10595 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10596 ins_cost(150);
10597 ins_encode( Push_Reg_D(src),
10598 OpcP, RegOpc(dst) );
10599 ins_pipe( fpu_reg_reg );
10600 %}
10601
10602 // Strict FP instruction biases argument before division then
10603 // biases result, to avoid double rounding of subnormals.
10604 //
10605 // scale dividend by multiplying dividend by 2^(-15360)
10606 // load divisor
10607 // divide scaled dividend by divisor
10608 // rescale quotient by 2^(15360)
10609 //
10610 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10611 predicate (UseSSE<=1);
10612 match(Set dst (DivD dst src));
10613 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10614 ins_cost(01);
10615
10616 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10617 "DMULp $dst,ST\n\t"
10618 "FLD $src\n\t"
10619 "FDIVp $dst,ST\n\t"
10620 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10621 "DMULp $dst,ST\n\t" %}
10622 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10623 ins_encode( strictfp_bias1(dst),
10624 Push_Reg_D(src),
10625 OpcP, RegOpc(dst),
10626 strictfp_bias2(dst) );
10627 ins_pipe( fpu_reg_reg );
10628 %}
10629
10630 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10631 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10632 match(Set dst (RoundDouble (DivD src1 src2)));
10633
10634 format %{ "FLD $src1\n\t"
10635 "FDIV ST,$src2\n\t"
10636 "FSTP_D $dst\t# D-round" %}
10637 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10638 ins_encode( Push_Reg_D(src1),
10639 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10640 ins_pipe( fpu_mem_reg_reg );
10641 %}
10642
10643
10644 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10645 predicate(UseSSE<=1);
10646 match(Set dst (ModD dst src));
10647 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10648
10649 format %{ "DMOD $dst,$src" %}
10650 ins_cost(250);
10651 ins_encode(Push_Reg_Mod_D(dst, src),
10652 emitModD(),
10653 Push_Result_Mod_D(src),
10654 Pop_Reg_D(dst));
10655 ins_pipe( pipe_slow );
10656 %}
10657
10658 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10659 predicate(UseSSE>=2);
10660 match(Set dst (ModD src0 src1));
10661 effect(KILL rax, KILL cr);
10662
10663 format %{ "SUB ESP,8\t # DMOD\n"
10664 "\tMOVSD [ESP+0],$src1\n"
10665 "\tFLD_D [ESP+0]\n"
10666 "\tMOVSD [ESP+0],$src0\n"
10667 "\tFLD_D [ESP+0]\n"
10668 "loop:\tFPREM\n"
10669 "\tFWAIT\n"
10670 "\tFNSTSW AX\n"
10671 "\tSAHF\n"
10672 "\tJP loop\n"
10673 "\tFSTP_D [ESP+0]\n"
10674 "\tMOVSD $dst,[ESP+0]\n"
10675 "\tADD ESP,8\n"
10676 "\tFSTP ST0\t # Restore FPU Stack"
10677 %}
10678 ins_cost(250);
10679 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10680 ins_pipe( pipe_slow );
10681 %}
10682
10683 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10684 predicate (UseSSE<=1);
10685 match(Set dst (SinD src));
10686 ins_cost(1800);
10687 format %{ "DSIN $dst" %}
10688 opcode(0xD9, 0xFE);
10689 ins_encode( OpcP, OpcS );
10690 ins_pipe( pipe_slow );
10691 %}
10692
10693 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10694 predicate (UseSSE>=2);
10695 match(Set dst (SinD dst));
10696 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10697 ins_cost(1800);
10698 format %{ "DSIN $dst" %}
10699 opcode(0xD9, 0xFE);
10700 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10701 ins_pipe( pipe_slow );
10702 %}
10703
10704 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10705 predicate (UseSSE<=1);
10706 match(Set dst (CosD src));
10707 ins_cost(1800);
10708 format %{ "DCOS $dst" %}
10709 opcode(0xD9, 0xFF);
10710 ins_encode( OpcP, OpcS );
10711 ins_pipe( pipe_slow );
10712 %}
10713
10714 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10715 predicate (UseSSE>=2);
10716 match(Set dst (CosD dst));
10717 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10718 ins_cost(1800);
10719 format %{ "DCOS $dst" %}
10720 opcode(0xD9, 0xFF);
10721 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10722 ins_pipe( pipe_slow );
10723 %}
10724
10725 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10726 predicate (UseSSE<=1);
10727 match(Set dst(TanD src));
10728 format %{ "DTAN $dst" %}
10729 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10730 Opcode(0xDD), Opcode(0xD8)); // fstp st
10731 ins_pipe( pipe_slow );
10732 %}
10733
10734 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10735 predicate (UseSSE>=2);
10736 match(Set dst(TanD dst));
10737 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10738 format %{ "DTAN $dst" %}
10739 ins_encode( Push_SrcXD(dst),
10740 Opcode(0xD9), Opcode(0xF2), // fptan
10741 Opcode(0xDD), Opcode(0xD8), // fstp st
10742 Push_ResultXD(dst) );
10743 ins_pipe( pipe_slow );
10744 %}
10745
10746 instruct atanD_reg(regD dst, regD src) %{
10747 predicate (UseSSE<=1);
10748 match(Set dst(AtanD dst src));
10749 format %{ "DATA $dst,$src" %}
10750 opcode(0xD9, 0xF3);
10751 ins_encode( Push_Reg_D(src),
10752 OpcP, OpcS, RegOpc(dst) );
10753 ins_pipe( pipe_slow );
10754 %}
10755
10756 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10757 predicate (UseSSE>=2);
10758 match(Set dst(AtanD dst src));
10759 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10760 format %{ "DATA $dst,$src" %}
10761 opcode(0xD9, 0xF3);
10762 ins_encode( Push_SrcXD(src),
10763 OpcP, OpcS, Push_ResultXD(dst) );
10764 ins_pipe( pipe_slow );
10765 %}
10766
10767 instruct sqrtD_reg(regD dst, regD src) %{
10768 predicate (UseSSE<=1);
10769 match(Set dst (SqrtD src));
10770 format %{ "DSQRT $dst,$src" %}
10771 opcode(0xFA, 0xD9);
10772 ins_encode( Push_Reg_D(src),
10773 OpcS, OpcP, Pop_Reg_D(dst) );
10774 ins_pipe( pipe_slow );
10775 %}
10776
10777 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10778 predicate (UseSSE<=1);
10779 match(Set Y (PowD X Y)); // Raise X to the Yth power
10780 effect(KILL rax, KILL rbx, KILL rcx);
10781 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10782 "FLD_D $X\n\t"
10783 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10784
10785 "FDUP \t\t\t# Q Q\n\t"
10786 "FRNDINT\t\t\t# int(Q) Q\n\t"
10787 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10788 "FISTP dword [ESP]\n\t"
10789 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10790 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10791 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10792 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10793 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10794 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10795 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10796 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10797 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10798 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10799 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10800 "MOV [ESP+0],0\n\t"
10801 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10802
10803 "ADD ESP,8"
10804 %}
10805 ins_encode( push_stack_temp_qword,
10806 Push_Reg_D(X),
10807 Opcode(0xD9), Opcode(0xF1), // fyl2x
10808 pow_exp_core_encoding,
10809 pop_stack_temp_qword);
10810 ins_pipe( pipe_slow );
10811 %}
10812
10813 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10814 predicate (UseSSE>=2);
10815 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10816 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10817 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10818 "MOVSD [ESP],$src1\n\t"
10819 "FLD FPR1,$src1\n\t"
10820 "MOVSD [ESP],$src0\n\t"
10821 "FLD FPR1,$src0\n\t"
10822 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10823
10824 "FDUP \t\t\t# Q Q\n\t"
10825 "FRNDINT\t\t\t# int(Q) Q\n\t"
10826 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10827 "FISTP dword [ESP]\n\t"
10828 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10829 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10830 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10831 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10832 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10833 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10834 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10835 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10836 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10837 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10838 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10839 "MOV [ESP+0],0\n\t"
10840 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10841
10842 "FST_D [ESP]\n\t"
10843 "MOVSD $dst,[ESP]\n\t"
10844 "ADD ESP,8"
10845 %}
10846 ins_encode( push_stack_temp_qword,
10847 push_xmm_to_fpr1(src1),
10848 push_xmm_to_fpr1(src0),
10849 Opcode(0xD9), Opcode(0xF1), // fyl2x
10850 pow_exp_core_encoding,
10851 Push_ResultXD(dst) );
10852 ins_pipe( pipe_slow );
10853 %}
10854
10855
10856 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10857 predicate (UseSSE<=1);
10858 match(Set dpr1 (ExpD dpr1));
10859 effect(KILL rax, KILL rbx, KILL rcx);
10860 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10861 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10862 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10863
10864 "FDUP \t\t\t# Q Q\n\t"
10865 "FRNDINT\t\t\t# int(Q) Q\n\t"
10866 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10867 "FISTP dword [ESP]\n\t"
10868 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10869 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10870 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10871 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10872 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10873 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10874 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10875 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10876 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10877 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10878 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10879 "MOV [ESP+0],0\n\t"
10880 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10881
10882 "ADD ESP,8"
10883 %}
10884 ins_encode( push_stack_temp_qword,
10885 Opcode(0xD9), Opcode(0xEA), // fldl2e
10886 Opcode(0xDE), Opcode(0xC9), // fmulp
10887 pow_exp_core_encoding,
10888 pop_stack_temp_qword);
10889 ins_pipe( pipe_slow );
10890 %}
10891
10892 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10893 predicate (UseSSE>=2);
10894 match(Set dst (ExpD src));
10895 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10896 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10897 "MOVSD [ESP],$src\n\t"
10898 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10899 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10900
10901 "FDUP \t\t\t# Q Q\n\t"
10902 "FRNDINT\t\t\t# int(Q) Q\n\t"
10903 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10904 "FISTP dword [ESP]\n\t"
10905 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10906 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10907 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10908 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10909 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10910 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10911 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10912 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10913 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10914 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10915 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10916 "MOV [ESP+0],0\n\t"
10917 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10918
10919 "FST_D [ESP]\n\t"
10920 "MOVSD $dst,[ESP]\n\t"
10921 "ADD ESP,8"
10922 %}
10923 ins_encode( Push_SrcXD(src),
10924 Opcode(0xD9), Opcode(0xEA), // fldl2e
10925 Opcode(0xDE), Opcode(0xC9), // fmulp
10926 pow_exp_core_encoding,
10927 Push_ResultXD(dst) );
10928 ins_pipe( pipe_slow );
10929 %}
10930
10931
10932
10933 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10934 predicate (UseSSE<=1);
10935 // The source Double operand on FPU stack
10936 match(Set dst (Log10D src));
10937 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10938 // fxch ; swap ST(0) with ST(1)
10939 // fyl2x ; compute log_10(2) * log_2(x)
10940 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10941 "FXCH \n\t"
10942 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10943 %}
10944 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10945 Opcode(0xD9), Opcode(0xC9), // fxch
10946 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10947
10948 ins_pipe( pipe_slow );
10949 %}
10950
10951 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10952 predicate (UseSSE>=2);
10953 effect(KILL cr);
10954 match(Set dst (Log10D src));
10955 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10956 // fyl2x ; compute log_10(2) * log_2(x)
10957 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10958 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10959 %}
10960 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10961 Push_SrcXD(src),
10962 Opcode(0xD9), Opcode(0xF1), // fyl2x
10963 Push_ResultXD(dst));
10964
10965 ins_pipe( pipe_slow );
10966 %}
10967
10968 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10969 predicate (UseSSE<=1);
10970 // The source Double operand on FPU stack
10971 match(Set dst (LogD src));
10972 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10973 // fxch ; swap ST(0) with ST(1)
10974 // fyl2x ; compute log_e(2) * log_2(x)
10975 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10976 "FXCH \n\t"
10977 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10978 %}
10979 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10980 Opcode(0xD9), Opcode(0xC9), // fxch
10981 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10982
10983 ins_pipe( pipe_slow );
10984 %}
10985
10986 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10987 predicate (UseSSE>=2);
10988 effect(KILL cr);
10989 // The source and result Double operands in XMM registers
10990 match(Set dst (LogD src));
10991 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10992 // fyl2x ; compute log_e(2) * log_2(x)
10993 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10994 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10995 %}
10996 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10997 Push_SrcXD(src),
10998 Opcode(0xD9), Opcode(0xF1), // fyl2x
10999 Push_ResultXD(dst));
11000 ins_pipe( pipe_slow );
11001 %}
11002
11003 //-------------Float Instructions-------------------------------
11004 // Float Math
11005
11006 // Code for float compare:
11007 // fcompp();
11008 // fwait(); fnstsw_ax();
11009 // sahf();
11010 // movl(dst, unordered_result);
11011 // jcc(Assembler::parity, exit);
11012 // movl(dst, less_result);
11013 // jcc(Assembler::below, exit);
11014 // movl(dst, equal_result);
11015 // jcc(Assembler::equal, exit);
11016 // movl(dst, greater_result);
11017 // exit:
11018
11019 // P6 version of float compare, sets condition codes in EFLAGS
11020 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
11021 predicate(VM_Version::supports_cmov() && UseSSE == 0);
11022 match(Set cr (CmpF src1 src2));
11023 effect(KILL rax);
11024 ins_cost(150);
11025 format %{ "FLD $src1\n\t"
11026 "FUCOMIP ST,$src2 // P6 instruction\n\t"
11027 "JNP exit\n\t"
11028 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
11029 "SAHF\n"
11030 "exit:\tNOP // avoid branch to branch" %}
11031 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
11032 ins_encode( Push_Reg_D(src1),
11033 OpcP, RegOpc(src2),
11034 cmpF_P6_fixup );
11035 ins_pipe( pipe_slow );
11036 %}
11037
11038 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
11039 predicate(VM_Version::supports_cmov() && UseSSE == 0);
11040 match(Set cr (CmpF src1 src2));
11041 ins_cost(100);
11042 format %{ "FLD $src1\n\t"
11043 "FUCOMIP ST,$src2 // P6 instruction" %}
11044 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
11045 ins_encode( Push_Reg_D(src1),
11046 OpcP, RegOpc(src2));
11047 ins_pipe( pipe_slow );
11048 %}
11049
11050
11051 // Compare & branch
11052 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
11053 predicate(UseSSE == 0);
11054 match(Set cr (CmpF src1 src2));
11055 effect(KILL rax);
11056 ins_cost(200);
11057 format %{ "FLD $src1\n\t"
11058 "FCOMp $src2\n\t"
11059 "FNSTSW AX\n\t"
11060 "TEST AX,0x400\n\t"
11061 "JZ,s flags\n\t"
11062 "MOV AH,1\t# unordered treat as LT\n"
11063 "flags:\tSAHF" %}
11064 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
11065 ins_encode( Push_Reg_D(src1),
11066 OpcP, RegOpc(src2),
11067 fpu_flags);
11068 ins_pipe( pipe_slow );
11069 %}
11070
11071 // Compare vs zero into -1,0,1
11072 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
11073 predicate(UseSSE == 0);
11074 match(Set dst (CmpF3 src1 zero));
11075 effect(KILL cr, KILL rax);
11076 ins_cost(280);
11077 format %{ "FTSTF $dst,$src1" %}
11078 opcode(0xE4, 0xD9);
11079 ins_encode( Push_Reg_D(src1),
11080 OpcS, OpcP, PopFPU,
11081 CmpF_Result(dst));
11082 ins_pipe( pipe_slow );
11083 %}
11084
11085 // Compare into -1,0,1
11086 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11087 predicate(UseSSE == 0);
11088 match(Set dst (CmpF3 src1 src2));
11089 effect(KILL cr, KILL rax);
11090 ins_cost(300);
11091 format %{ "FCMPF $dst,$src1,$src2" %}
11092 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
11093 ins_encode( Push_Reg_D(src1),
11094 OpcP, RegOpc(src2),
11095 CmpF_Result(dst));
11096 ins_pipe( pipe_slow );
11097 %}
11098
11099 // float compare and set condition codes in EFLAGS by XMM regs
11100 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
11101 predicate(UseSSE>=1);
11102 match(Set cr (CmpF dst src));
11103 effect(KILL rax);
11104 ins_cost(145);
11105 format %{ "COMISS $dst,$src\n"
11106 "\tJNP exit\n"
11107 "\tMOV ah,1 // saw a NaN, set CF\n"
11108 "\tSAHF\n"
11109 "exit:\tNOP // avoid branch to branch" %}
11110 opcode(0x0F, 0x2F);
11111 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
11112 ins_pipe( pipe_slow );
11113 %}
11114
11115 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
11116 predicate(UseSSE>=1);
11117 match(Set cr (CmpF dst src));
11118 ins_cost(100);
11119 format %{ "COMISS $dst,$src" %}
11120 opcode(0x0F, 0x2F);
11121 ins_encode(OpcP, OpcS, RegReg(dst, src));
11122 ins_pipe( pipe_slow );
11123 %}
11124
11125 // float compare and set condition codes in EFLAGS by XMM regs
11126 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
11127 predicate(UseSSE>=1);
11128 match(Set cr (CmpF dst (LoadF src)));
11129 effect(KILL rax);
11130 ins_cost(165);
11131 format %{ "COMISS $dst,$src\n"
11132 "\tJNP exit\n"
11133 "\tMOV ah,1 // saw a NaN, set CF\n"
11134 "\tSAHF\n"
11135 "exit:\tNOP // avoid branch to branch" %}
11136 opcode(0x0F, 0x2F);
11137 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
11138 ins_pipe( pipe_slow );
11139 %}
11140
11141 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
11142 predicate(UseSSE>=1);
11143 match(Set cr (CmpF dst (LoadF src)));
11144 ins_cost(100);
11145 format %{ "COMISS $dst,$src" %}
11146 opcode(0x0F, 0x2F);
11147 ins_encode(OpcP, OpcS, RegMem(dst, src));
11148 ins_pipe( pipe_slow );
11149 %}
11150
11151 // Compare into -1,0,1 in XMM
11152 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
11153 predicate(UseSSE>=1);
11154 match(Set dst (CmpF3 src1 src2));
11155 effect(KILL cr);
11156 ins_cost(255);
11157 format %{ "XOR $dst,$dst\n"
11158 "\tCOMISS $src1,$src2\n"
11159 "\tJP,s nan\n"
11160 "\tJEQ,s exit\n"
11161 "\tJA,s inc\n"
11162 "nan:\tDEC $dst\n"
11163 "\tJMP,s exit\n"
11164 "inc:\tINC $dst\n"
11165 "exit:"
11166 %}
11167 opcode(0x0F, 0x2F);
11168 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
11169 ins_pipe( pipe_slow );
11170 %}
11171
11172 // Compare into -1,0,1 in XMM and memory
11173 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
11174 predicate(UseSSE>=1);
11175 match(Set dst (CmpF3 src1 (LoadF mem)));
11176 effect(KILL cr);
11177 ins_cost(275);
11178 format %{ "COMISS $src1,$mem\n"
11179 "\tMOV $dst,0\t\t# do not blow flags\n"
11180 "\tJP,s nan\n"
11181 "\tJEQ,s exit\n"
11182 "\tJA,s inc\n"
11183 "nan:\tDEC $dst\n"
11184 "\tJMP,s exit\n"
11185 "inc:\tINC $dst\n"
11186 "exit:"
11187 %}
11188 opcode(0x0F, 0x2F);
11189 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
11190 ins_pipe( pipe_slow );
11191 %}
11192
11193 // Spill to obtain 24-bit precision
11194 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
11195 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11196 match(Set dst (SubF src1 src2));
11197
11198 format %{ "FSUB $dst,$src1 - $src2" %}
11199 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
11200 ins_encode( Push_Reg_F(src1),
11201 OpcReg_F(src2),
11202 Pop_Mem_F(dst) );
11203 ins_pipe( fpu_mem_reg_reg );
11204 %}
11205 //
11206 // This instruction does not round to 24-bits
11207 instruct subF_reg(regF dst, regF src) %{
11208 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11209 match(Set dst (SubF dst src));
11210
11211 format %{ "FSUB $dst,$src" %}
11212 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
11213 ins_encode( Push_Reg_F(src),
11214 OpcP, RegOpc(dst) );
11215 ins_pipe( fpu_reg_reg );
11216 %}
11217
11218 // Spill to obtain 24-bit precision
11219 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
11220 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11221 match(Set dst (AddF src1 src2));
11222
11223 format %{ "FADD $dst,$src1,$src2" %}
11224 opcode(0xD8, 0x0); /* D8 C0+i */
11225 ins_encode( Push_Reg_F(src2),
11226 OpcReg_F(src1),
11227 Pop_Mem_F(dst) );
11228 ins_pipe( fpu_mem_reg_reg );
11229 %}
11230 //
11231 // This instruction does not round to 24-bits
11232 instruct addF_reg(regF dst, regF src) %{
11233 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11234 match(Set dst (AddF dst src));
11235
11236 format %{ "FLD $src\n\t"
11237 "FADDp $dst,ST" %}
11238 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
11239 ins_encode( Push_Reg_F(src),
11240 OpcP, RegOpc(dst) );
11241 ins_pipe( fpu_reg_reg );
11242 %}
11243
11244 // Add two single precision floating point values in xmm
11245 instruct addX_reg(regX dst, regX src) %{
11246 predicate(UseSSE>=1);
11247 match(Set dst (AddF dst src));
11248 format %{ "ADDSS $dst,$src" %}
11249 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
11250 ins_pipe( pipe_slow );
11251 %}
11252
11253 instruct addX_imm(regX dst, immXF con) %{
11254 predicate(UseSSE>=1);
11255 match(Set dst (AddF dst con));
11256 format %{ "ADDSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
11257 ins_encode %{
11258 __ addss($dst$$XMMRegister, $constantaddress($con));
11259 %}
11260 ins_pipe(pipe_slow);
11261 %}
11262
11263 instruct addX_mem(regX dst, memory mem) %{
11264 predicate(UseSSE>=1);
11265 match(Set dst (AddF dst (LoadF mem)));
11266 format %{ "ADDSS $dst,$mem" %}
11267 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
11268 ins_pipe( pipe_slow );
11269 %}
11270
11271 // Subtract two single precision floating point values in xmm
11272 instruct subX_reg(regX dst, regX src) %{
11273 predicate(UseSSE>=1);
11274 match(Set dst (SubF dst src));
11275 format %{ "SUBSS $dst,$src" %}
11276 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
11277 ins_pipe( pipe_slow );
11278 %}
11279
11280 instruct subX_imm(regX dst, immXF con) %{
11281 predicate(UseSSE>=1);
11282 match(Set dst (SubF dst con));
11283 format %{ "SUBSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
11284 ins_encode %{
11285 __ subss($dst$$XMMRegister, $constantaddress($con));
11286 %}
11287 ins_pipe(pipe_slow);
11288 %}
11289
11290 instruct subX_mem(regX dst, memory mem) %{
11291 predicate(UseSSE>=1);
11292 match(Set dst (SubF dst (LoadF mem)));
11293 format %{ "SUBSS $dst,$mem" %}
11294 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
11295 ins_pipe( pipe_slow );
11296 %}
11297
11298 // Multiply two single precision floating point values in xmm
11299 instruct mulX_reg(regX dst, regX src) %{
11300 predicate(UseSSE>=1);
11301 match(Set dst (MulF dst src));
11302 format %{ "MULSS $dst,$src" %}
11303 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
11304 ins_pipe( pipe_slow );
11305 %}
11306
11307 instruct mulX_imm(regX dst, immXF con) %{
11308 predicate(UseSSE>=1);
11309 match(Set dst (MulF dst con));
11310 format %{ "MULSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
11311 ins_encode %{
11312 __ mulss($dst$$XMMRegister, $constantaddress($con));
11313 %}
11314 ins_pipe(pipe_slow);
11315 %}
11316
11317 instruct mulX_mem(regX dst, memory mem) %{
11318 predicate(UseSSE>=1);
11319 match(Set dst (MulF dst (LoadF mem)));
11320 format %{ "MULSS $dst,$mem" %}
11321 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
11322 ins_pipe( pipe_slow );
11323 %}
11324
11325 // Divide two single precision floating point values in xmm
11326 instruct divX_reg(regX dst, regX src) %{
11327 predicate(UseSSE>=1);
11328 match(Set dst (DivF dst src));
11329 format %{ "DIVSS $dst,$src" %}
11330 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
11331 ins_pipe( pipe_slow );
11332 %}
11333
11334 instruct divX_imm(regX dst, immXF con) %{
11335 predicate(UseSSE>=1);
11336 match(Set dst (DivF dst con));
11337 format %{ "DIVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
11338 ins_encode %{
11339 __ divss($dst$$XMMRegister, $constantaddress($con));
11340 %}
11341 ins_pipe(pipe_slow);
11342 %}
11343
11344 instruct divX_mem(regX dst, memory mem) %{
11345 predicate(UseSSE>=1);
11346 match(Set dst (DivF dst (LoadF mem)));
11347 format %{ "DIVSS $dst,$mem" %}
11348 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
11349 ins_pipe( pipe_slow );
11350 %}
11351
11352 // Get the square root of a single precision floating point values in xmm
11353 instruct sqrtX_reg(regX dst, regX src) %{
11354 predicate(UseSSE>=1);
11355 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
11356 format %{ "SQRTSS $dst,$src" %}
11357 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11358 ins_pipe( pipe_slow );
11359 %}
11360
11361 instruct sqrtX_mem(regX dst, memory mem) %{
11362 predicate(UseSSE>=1);
11363 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
11364 format %{ "SQRTSS $dst,$mem" %}
11365 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11366 ins_pipe( pipe_slow );
11367 %}
11368
11369 // Get the square root of a double precision floating point values in xmm
11370 instruct sqrtXD_reg(regXD dst, regXD src) %{
11371 predicate(UseSSE>=2);
11372 match(Set dst (SqrtD src));
11373 format %{ "SQRTSD $dst,$src" %}
11374 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11375 ins_pipe( pipe_slow );
11376 %}
11377
11378 instruct sqrtXD_mem(regXD dst, memory mem) %{
11379 predicate(UseSSE>=2);
11380 match(Set dst (SqrtD (LoadD mem)));
11381 format %{ "SQRTSD $dst,$mem" %}
11382 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11383 ins_pipe( pipe_slow );
11384 %}
11385
11386 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11387 predicate(UseSSE==0);
11388 match(Set dst (AbsF src));
11389 ins_cost(100);
11390 format %{ "FABS" %}
11391 opcode(0xE1, 0xD9);
11392 ins_encode( OpcS, OpcP );
11393 ins_pipe( fpu_reg_reg );
11394 %}
11395
11396 instruct absX_reg(regX dst ) %{
11397 predicate(UseSSE>=1);
11398 match(Set dst (AbsF dst));
11399 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11400 ins_encode( AbsXF_encoding(dst));
11401 ins_pipe( pipe_slow );
11402 %}
11403
11404 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11405 predicate(UseSSE==0);
11406 match(Set dst (NegF src));
11407 ins_cost(100);
11408 format %{ "FCHS" %}
11409 opcode(0xE0, 0xD9);
11410 ins_encode( OpcS, OpcP );
11411 ins_pipe( fpu_reg_reg );
11412 %}
11413
11414 instruct negX_reg( regX dst ) %{
11415 predicate(UseSSE>=1);
11416 match(Set dst (NegF dst));
11417 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11418 ins_encode( NegXF_encoding(dst));
11419 ins_pipe( pipe_slow );
11420 %}
11421
11422 // Cisc-alternate to addF_reg
11423 // Spill to obtain 24-bit precision
11424 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11425 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11426 match(Set dst (AddF src1 (LoadF src2)));
11427
11428 format %{ "FLD $src2\n\t"
11429 "FADD ST,$src1\n\t"
11430 "FSTP_S $dst" %}
11431 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11432 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11433 OpcReg_F(src1),
11434 Pop_Mem_F(dst) );
11435 ins_pipe( fpu_mem_reg_mem );
11436 %}
11437 //
11438 // Cisc-alternate to addF_reg
11439 // This instruction does not round to 24-bits
11440 instruct addF_reg_mem(regF dst, memory src) %{
11441 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11442 match(Set dst (AddF dst (LoadF src)));
11443
11444 format %{ "FADD $dst,$src" %}
11445 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11446 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11447 OpcP, RegOpc(dst) );
11448 ins_pipe( fpu_reg_mem );
11449 %}
11450
11451 // // Following two instructions for _222_mpegaudio
11452 // Spill to obtain 24-bit precision
11453 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11454 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11455 match(Set dst (AddF src1 src2));
11456
11457 format %{ "FADD $dst,$src1,$src2" %}
11458 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11459 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11460 OpcReg_F(src2),
11461 Pop_Mem_F(dst) );
11462 ins_pipe( fpu_mem_reg_mem );
11463 %}
11464
11465 // Cisc-spill variant
11466 // Spill to obtain 24-bit precision
11467 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11468 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11469 match(Set dst (AddF src1 (LoadF src2)));
11470
11471 format %{ "FADD $dst,$src1,$src2 cisc" %}
11472 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11473 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11474 set_instruction_start,
11475 OpcP, RMopc_Mem(secondary,src1),
11476 Pop_Mem_F(dst) );
11477 ins_pipe( fpu_mem_mem_mem );
11478 %}
11479
11480 // Spill to obtain 24-bit precision
11481 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11482 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11483 match(Set dst (AddF src1 src2));
11484
11485 format %{ "FADD $dst,$src1,$src2" %}
11486 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11487 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11488 set_instruction_start,
11489 OpcP, RMopc_Mem(secondary,src1),
11490 Pop_Mem_F(dst) );
11491 ins_pipe( fpu_mem_mem_mem );
11492 %}
11493
11494
11495 // Spill to obtain 24-bit precision
11496 instruct addF24_reg_imm(stackSlotF dst, regF src, immF con) %{
11497 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11498 match(Set dst (AddF src con));
11499 format %{ "FLD $src\n\t"
11500 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11501 "FSTP_S $dst" %}
11502 ins_encode %{
11503 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11504 __ fadd_s($constantaddress($con));
11505 __ fstp_s(Address(rsp, $dst$$disp));
11506 %}
11507 ins_pipe(fpu_mem_reg_con);
11508 %}
11509 //
11510 // This instruction does not round to 24-bits
11511 instruct addF_reg_imm(regF dst, regF src, immF con) %{
11512 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11513 match(Set dst (AddF src con));
11514 format %{ "FLD $src\n\t"
11515 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11516 "FSTP $dst" %}
11517 ins_encode %{
11518 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11519 __ fadd_s($constantaddress($con));
11520 __ fstp_d($dst$$reg);
11521 %}
11522 ins_pipe(fpu_reg_reg_con);
11523 %}
11524
11525 // Spill to obtain 24-bit precision
11526 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11527 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11528 match(Set dst (MulF src1 src2));
11529
11530 format %{ "FLD $src1\n\t"
11531 "FMUL $src2\n\t"
11532 "FSTP_S $dst" %}
11533 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11534 ins_encode( Push_Reg_F(src1),
11535 OpcReg_F(src2),
11536 Pop_Mem_F(dst) );
11537 ins_pipe( fpu_mem_reg_reg );
11538 %}
11539 //
11540 // This instruction does not round to 24-bits
11541 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11542 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11543 match(Set dst (MulF src1 src2));
11544
11545 format %{ "FLD $src1\n\t"
11546 "FMUL $src2\n\t"
11547 "FSTP_S $dst" %}
11548 opcode(0xD8, 0x1); /* D8 C8+i */
11549 ins_encode( Push_Reg_F(src2),
11550 OpcReg_F(src1),
11551 Pop_Reg_F(dst) );
11552 ins_pipe( fpu_reg_reg_reg );
11553 %}
11554
11555
11556 // Spill to obtain 24-bit precision
11557 // Cisc-alternate to reg-reg multiply
11558 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11559 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11560 match(Set dst (MulF src1 (LoadF src2)));
11561
11562 format %{ "FLD_S $src2\n\t"
11563 "FMUL $src1\n\t"
11564 "FSTP_S $dst" %}
11565 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11566 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11567 OpcReg_F(src1),
11568 Pop_Mem_F(dst) );
11569 ins_pipe( fpu_mem_reg_mem );
11570 %}
11571 //
11572 // This instruction does not round to 24-bits
11573 // Cisc-alternate to reg-reg multiply
11574 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11575 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11576 match(Set dst (MulF src1 (LoadF src2)));
11577
11578 format %{ "FMUL $dst,$src1,$src2" %}
11579 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11580 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11581 OpcReg_F(src1),
11582 Pop_Reg_F(dst) );
11583 ins_pipe( fpu_reg_reg_mem );
11584 %}
11585
11586 // Spill to obtain 24-bit precision
11587 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11588 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11589 match(Set dst (MulF src1 src2));
11590
11591 format %{ "FMUL $dst,$src1,$src2" %}
11592 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11593 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11594 set_instruction_start,
11595 OpcP, RMopc_Mem(secondary,src1),
11596 Pop_Mem_F(dst) );
11597 ins_pipe( fpu_mem_mem_mem );
11598 %}
11599
11600 // Spill to obtain 24-bit precision
11601 instruct mulF24_reg_imm(stackSlotF dst, regF src, immF con) %{
11602 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11603 match(Set dst (MulF src con));
11604
11605 format %{ "FLD $src\n\t"
11606 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11607 "FSTP_S $dst" %}
11608 ins_encode %{
11609 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11610 __ fmul_s($constantaddress($con));
11611 __ fstp_s(Address(rsp, $dst$$disp));
11612 %}
11613 ins_pipe(fpu_mem_reg_con);
11614 %}
11615 //
11616 // This instruction does not round to 24-bits
11617 instruct mulF_reg_imm(regF dst, regF src, immF con) %{
11618 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11619 match(Set dst (MulF src con));
11620
11621 format %{ "FLD $src\n\t"
11622 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
11623 "FSTP $dst" %}
11624 ins_encode %{
11625 __ fld_s($src$$reg - 1); // FLD ST(i-1)
11626 __ fmul_s($constantaddress($con));
11627 __ fstp_d($dst$$reg);
11628 %}
11629 ins_pipe(fpu_reg_reg_con);
11630 %}
11631
11632
11633 //
11634 // MACRO1 -- subsume unshared load into mulF
11635 // This instruction does not round to 24-bits
11636 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11637 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11638 match(Set dst (MulF (LoadF mem1) src));
11639
11640 format %{ "FLD $mem1 ===MACRO1===\n\t"
11641 "FMUL ST,$src\n\t"
11642 "FSTP $dst" %}
11643 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11644 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11645 OpcReg_F(src),
11646 Pop_Reg_F(dst) );
11647 ins_pipe( fpu_reg_reg_mem );
11648 %}
11649 //
11650 // MACRO2 -- addF a mulF which subsumed an unshared load
11651 // This instruction does not round to 24-bits
11652 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11653 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11654 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11655 ins_cost(95);
11656
11657 format %{ "FLD $mem1 ===MACRO2===\n\t"
11658 "FMUL ST,$src1 subsume mulF left load\n\t"
11659 "FADD ST,$src2\n\t"
11660 "FSTP $dst" %}
11661 opcode(0xD9); /* LoadF D9 /0 */
11662 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11663 FMul_ST_reg(src1),
11664 FAdd_ST_reg(src2),
11665 Pop_Reg_F(dst) );
11666 ins_pipe( fpu_reg_mem_reg_reg );
11667 %}
11668
11669 // MACRO3 -- addF a mulF
11670 // This instruction does not round to 24-bits. It is a '2-address'
11671 // instruction in that the result goes back to src2. This eliminates
11672 // a move from the macro; possibly the register allocator will have
11673 // to add it back (and maybe not).
11674 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11675 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11676 match(Set src2 (AddF (MulF src0 src1) src2));
11677
11678 format %{ "FLD $src0 ===MACRO3===\n\t"
11679 "FMUL ST,$src1\n\t"
11680 "FADDP $src2,ST" %}
11681 opcode(0xD9); /* LoadF D9 /0 */
11682 ins_encode( Push_Reg_F(src0),
11683 FMul_ST_reg(src1),
11684 FAddP_reg_ST(src2) );
11685 ins_pipe( fpu_reg_reg_reg );
11686 %}
11687
11688 // MACRO4 -- divF subF
11689 // This instruction does not round to 24-bits
11690 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11691 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11692 match(Set dst (DivF (SubF src2 src1) src3));
11693
11694 format %{ "FLD $src2 ===MACRO4===\n\t"
11695 "FSUB ST,$src1\n\t"
11696 "FDIV ST,$src3\n\t"
11697 "FSTP $dst" %}
11698 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11699 ins_encode( Push_Reg_F(src2),
11700 subF_divF_encode(src1,src3),
11701 Pop_Reg_F(dst) );
11702 ins_pipe( fpu_reg_reg_reg_reg );
11703 %}
11704
11705 // Spill to obtain 24-bit precision
11706 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11707 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11708 match(Set dst (DivF src1 src2));
11709
11710 format %{ "FDIV $dst,$src1,$src2" %}
11711 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11712 ins_encode( Push_Reg_F(src1),
11713 OpcReg_F(src2),
11714 Pop_Mem_F(dst) );
11715 ins_pipe( fpu_mem_reg_reg );
11716 %}
11717 //
11718 // This instruction does not round to 24-bits
11719 instruct divF_reg(regF dst, regF src) %{
11720 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11721 match(Set dst (DivF dst src));
11722
11723 format %{ "FDIV $dst,$src" %}
11724 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11725 ins_encode( Push_Reg_F(src),
11726 OpcP, RegOpc(dst) );
11727 ins_pipe( fpu_reg_reg );
11728 %}
11729
11730
11731 // Spill to obtain 24-bit precision
11732 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11733 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11734 match(Set dst (ModF src1 src2));
11735 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11736
11737 format %{ "FMOD $dst,$src1,$src2" %}
11738 ins_encode( Push_Reg_Mod_D(src1, src2),
11739 emitModD(),
11740 Push_Result_Mod_D(src2),
11741 Pop_Mem_F(dst));
11742 ins_pipe( pipe_slow );
11743 %}
11744 //
11745 // This instruction does not round to 24-bits
11746 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11747 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11748 match(Set dst (ModF dst src));
11749 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11750
11751 format %{ "FMOD $dst,$src" %}
11752 ins_encode(Push_Reg_Mod_D(dst, src),
11753 emitModD(),
11754 Push_Result_Mod_D(src),
11755 Pop_Reg_F(dst));
11756 ins_pipe( pipe_slow );
11757 %}
11758
11759 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11760 predicate(UseSSE>=1);
11761 match(Set dst (ModF src0 src1));
11762 effect(KILL rax, KILL cr);
11763 format %{ "SUB ESP,4\t # FMOD\n"
11764 "\tMOVSS [ESP+0],$src1\n"
11765 "\tFLD_S [ESP+0]\n"
11766 "\tMOVSS [ESP+0],$src0\n"
11767 "\tFLD_S [ESP+0]\n"
11768 "loop:\tFPREM\n"
11769 "\tFWAIT\n"
11770 "\tFNSTSW AX\n"
11771 "\tSAHF\n"
11772 "\tJP loop\n"
11773 "\tFSTP_S [ESP+0]\n"
11774 "\tMOVSS $dst,[ESP+0]\n"
11775 "\tADD ESP,4\n"
11776 "\tFSTP ST0\t # Restore FPU Stack"
11777 %}
11778 ins_cost(250);
11779 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11780 ins_pipe( pipe_slow );
11781 %}
11782
11783
11784 //----------Arithmetic Conversion Instructions---------------------------------
11785 // The conversions operations are all Alpha sorted. Please keep it that way!
11786
11787 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11788 predicate(UseSSE==0);
11789 match(Set dst (RoundFloat src));
11790 ins_cost(125);
11791 format %{ "FST_S $dst,$src\t# F-round" %}
11792 ins_encode( Pop_Mem_Reg_F(dst, src) );
11793 ins_pipe( fpu_mem_reg );
11794 %}
11795
11796 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11797 predicate(UseSSE<=1);
11798 match(Set dst (RoundDouble src));
11799 ins_cost(125);
11800 format %{ "FST_D $dst,$src\t# D-round" %}
11801 ins_encode( Pop_Mem_Reg_D(dst, src) );
11802 ins_pipe( fpu_mem_reg );
11803 %}
11804
11805 // Force rounding to 24-bit precision and 6-bit exponent
11806 instruct convD2F_reg(stackSlotF dst, regD src) %{
11807 predicate(UseSSE==0);
11808 match(Set dst (ConvD2F src));
11809 format %{ "FST_S $dst,$src\t# F-round" %}
11810 expand %{
11811 roundFloat_mem_reg(dst,src);
11812 %}
11813 %}
11814
11815 // Force rounding to 24-bit precision and 6-bit exponent
11816 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11817 predicate(UseSSE==1);
11818 match(Set dst (ConvD2F src));
11819 effect( KILL cr );
11820 format %{ "SUB ESP,4\n\t"
11821 "FST_S [ESP],$src\t# F-round\n\t"
11822 "MOVSS $dst,[ESP]\n\t"
11823 "ADD ESP,4" %}
11824 ins_encode( D2X_encoding(dst, src) );
11825 ins_pipe( pipe_slow );
11826 %}
11827
11828 // Force rounding double precision to single precision
11829 instruct convXD2X_reg(regX dst, regXD src) %{
11830 predicate(UseSSE>=2);
11831 match(Set dst (ConvD2F src));
11832 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11833 opcode(0xF2, 0x0F, 0x5A);
11834 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11835 ins_pipe( pipe_slow );
11836 %}
11837
11838 instruct convF2D_reg_reg(regD dst, regF src) %{
11839 predicate(UseSSE==0);
11840 match(Set dst (ConvF2D src));
11841 format %{ "FST_S $dst,$src\t# D-round" %}
11842 ins_encode( Pop_Reg_Reg_D(dst, src));
11843 ins_pipe( fpu_reg_reg );
11844 %}
11845
11846 instruct convF2D_reg(stackSlotD dst, regF src) %{
11847 predicate(UseSSE==1);
11848 match(Set dst (ConvF2D src));
11849 format %{ "FST_D $dst,$src\t# D-round" %}
11850 expand %{
11851 roundDouble_mem_reg(dst,src);
11852 %}
11853 %}
11854
11855 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11856 predicate(UseSSE==1);
11857 match(Set dst (ConvF2D src));
11858 effect( KILL cr );
11859 format %{ "SUB ESP,4\n\t"
11860 "MOVSS [ESP] $src\n\t"
11861 "FLD_S [ESP]\n\t"
11862 "ADD ESP,4\n\t"
11863 "FSTP $dst\t# D-round" %}
11864 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11865 ins_pipe( pipe_slow );
11866 %}
11867
11868 instruct convX2XD_reg(regXD dst, regX src) %{
11869 predicate(UseSSE>=2);
11870 match(Set dst (ConvF2D src));
11871 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11872 opcode(0xF3, 0x0F, 0x5A);
11873 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11874 ins_pipe( pipe_slow );
11875 %}
11876
11877 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11878 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11879 predicate(UseSSE<=1);
11880 match(Set dst (ConvD2I src));
11881 effect( KILL tmp, KILL cr );
11882 format %{ "FLD $src\t# Convert double to int \n\t"
11883 "FLDCW trunc mode\n\t"
11884 "SUB ESP,4\n\t"
11885 "FISTp [ESP + #0]\n\t"
11886 "FLDCW std/24-bit mode\n\t"
11887 "POP EAX\n\t"
11888 "CMP EAX,0x80000000\n\t"
11889 "JNE,s fast\n\t"
11890 "FLD_D $src\n\t"
11891 "CALL d2i_wrapper\n"
11892 "fast:" %}
11893 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11894 ins_pipe( pipe_slow );
11895 %}
11896
11897 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11898 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11899 predicate(UseSSE>=2);
11900 match(Set dst (ConvD2I src));
11901 effect( KILL tmp, KILL cr );
11902 format %{ "CVTTSD2SI $dst, $src\n\t"
11903 "CMP $dst,0x80000000\n\t"
11904 "JNE,s fast\n\t"
11905 "SUB ESP, 8\n\t"
11906 "MOVSD [ESP], $src\n\t"
11907 "FLD_D [ESP]\n\t"
11908 "ADD ESP, 8\n\t"
11909 "CALL d2i_wrapper\n"
11910 "fast:" %}
11911 opcode(0x1); // double-precision conversion
11912 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11913 ins_pipe( pipe_slow );
11914 %}
11915
11916 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11917 predicate(UseSSE<=1);
11918 match(Set dst (ConvD2L src));
11919 effect( KILL cr );
11920 format %{ "FLD $src\t# Convert double to long\n\t"
11921 "FLDCW trunc mode\n\t"
11922 "SUB ESP,8\n\t"
11923 "FISTp [ESP + #0]\n\t"
11924 "FLDCW std/24-bit mode\n\t"
11925 "POP EAX\n\t"
11926 "POP EDX\n\t"
11927 "CMP EDX,0x80000000\n\t"
11928 "JNE,s fast\n\t"
11929 "TEST EAX,EAX\n\t"
11930 "JNE,s fast\n\t"
11931 "FLD $src\n\t"
11932 "CALL d2l_wrapper\n"
11933 "fast:" %}
11934 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11935 ins_pipe( pipe_slow );
11936 %}
11937
11938 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11939 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11940 predicate (UseSSE>=2);
11941 match(Set dst (ConvD2L src));
11942 effect( KILL cr );
11943 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11944 "MOVSD [ESP],$src\n\t"
11945 "FLD_D [ESP]\n\t"
11946 "FLDCW trunc mode\n\t"
11947 "FISTp [ESP + #0]\n\t"
11948 "FLDCW std/24-bit mode\n\t"
11949 "POP EAX\n\t"
11950 "POP EDX\n\t"
11951 "CMP EDX,0x80000000\n\t"
11952 "JNE,s fast\n\t"
11953 "TEST EAX,EAX\n\t"
11954 "JNE,s fast\n\t"
11955 "SUB ESP,8\n\t"
11956 "MOVSD [ESP],$src\n\t"
11957 "FLD_D [ESP]\n\t"
11958 "CALL d2l_wrapper\n"
11959 "fast:" %}
11960 ins_encode( XD2L_encoding(src) );
11961 ins_pipe( pipe_slow );
11962 %}
11963
11964 // Convert a double to an int. Java semantics require we do complex
11965 // manglations in the corner cases. So we set the rounding mode to
11966 // 'zero', store the darned double down as an int, and reset the
11967 // rounding mode to 'nearest'. The hardware stores a flag value down
11968 // if we would overflow or converted a NAN; we check for this and
11969 // and go the slow path if needed.
11970 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11971 predicate(UseSSE==0);
11972 match(Set dst (ConvF2I src));
11973 effect( KILL tmp, KILL cr );
11974 format %{ "FLD $src\t# Convert float to int \n\t"
11975 "FLDCW trunc mode\n\t"
11976 "SUB ESP,4\n\t"
11977 "FISTp [ESP + #0]\n\t"
11978 "FLDCW std/24-bit mode\n\t"
11979 "POP EAX\n\t"
11980 "CMP EAX,0x80000000\n\t"
11981 "JNE,s fast\n\t"
11982 "FLD $src\n\t"
11983 "CALL d2i_wrapper\n"
11984 "fast:" %}
11985 // D2I_encoding works for F2I
11986 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11987 ins_pipe( pipe_slow );
11988 %}
11989
11990 // Convert a float in xmm to an int reg.
11991 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11992 predicate(UseSSE>=1);
11993 match(Set dst (ConvF2I src));
11994 effect( KILL tmp, KILL cr );
11995 format %{ "CVTTSS2SI $dst, $src\n\t"
11996 "CMP $dst,0x80000000\n\t"
11997 "JNE,s fast\n\t"
11998 "SUB ESP, 4\n\t"
11999 "MOVSS [ESP], $src\n\t"
12000 "FLD [ESP]\n\t"
12001 "ADD ESP, 4\n\t"
12002 "CALL d2i_wrapper\n"
12003 "fast:" %}
12004 opcode(0x0); // single-precision conversion
12005 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
12006 ins_pipe( pipe_slow );
12007 %}
12008
12009 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
12010 predicate(UseSSE==0);
12011 match(Set dst (ConvF2L src));
12012 effect( KILL cr );
12013 format %{ "FLD $src\t# Convert float to long\n\t"
12014 "FLDCW trunc mode\n\t"
12015 "SUB ESP,8\n\t"
12016 "FISTp [ESP + #0]\n\t"
12017 "FLDCW std/24-bit mode\n\t"
12018 "POP EAX\n\t"
12019 "POP EDX\n\t"
12020 "CMP EDX,0x80000000\n\t"
12021 "JNE,s fast\n\t"
12022 "TEST EAX,EAX\n\t"
12023 "JNE,s fast\n\t"
12024 "FLD $src\n\t"
12025 "CALL d2l_wrapper\n"
12026 "fast:" %}
12027 // D2L_encoding works for F2L
12028 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
12029 ins_pipe( pipe_slow );
12030 %}
12031
12032 // XMM lacks a float/double->long conversion, so use the old FPU stack.
12033 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
12034 predicate (UseSSE>=1);
12035 match(Set dst (ConvF2L src));
12036 effect( KILL cr );
12037 format %{ "SUB ESP,8\t# Convert float to long\n\t"
12038 "MOVSS [ESP],$src\n\t"
12039 "FLD_S [ESP]\n\t"
12040 "FLDCW trunc mode\n\t"
12041 "FISTp [ESP + #0]\n\t"
12042 "FLDCW std/24-bit mode\n\t"
12043 "POP EAX\n\t"
12044 "POP EDX\n\t"
12045 "CMP EDX,0x80000000\n\t"
12046 "JNE,s fast\n\t"
12047 "TEST EAX,EAX\n\t"
12048 "JNE,s fast\n\t"
12049 "SUB ESP,4\t# Convert float to long\n\t"
12050 "MOVSS [ESP],$src\n\t"
12051 "FLD_S [ESP]\n\t"
12052 "ADD ESP,4\n\t"
12053 "CALL d2l_wrapper\n"
12054 "fast:" %}
12055 ins_encode( X2L_encoding(src) );
12056 ins_pipe( pipe_slow );
12057 %}
12058
12059 instruct convI2D_reg(regD dst, stackSlotI src) %{
12060 predicate( UseSSE<=1 );
12061 match(Set dst (ConvI2D src));
12062 format %{ "FILD $src\n\t"
12063 "FSTP $dst" %}
12064 opcode(0xDB, 0x0); /* DB /0 */
12065 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
12066 ins_pipe( fpu_reg_mem );
12067 %}
12068
12069 instruct convI2XD_reg(regXD dst, eRegI src) %{
12070 predicate( UseSSE>=2 && !UseXmmI2D );
12071 match(Set dst (ConvI2D src));
12072 format %{ "CVTSI2SD $dst,$src" %}
12073 opcode(0xF2, 0x0F, 0x2A);
12074 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
12075 ins_pipe( pipe_slow );
12076 %}
12077
12078 instruct convI2XD_mem(regXD dst, memory mem) %{
12079 predicate( UseSSE>=2 );
12080 match(Set dst (ConvI2D (LoadI mem)));
12081 format %{ "CVTSI2SD $dst,$mem" %}
12082 opcode(0xF2, 0x0F, 0x2A);
12083 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
12084 ins_pipe( pipe_slow );
12085 %}
12086
12087 instruct convXI2XD_reg(regXD dst, eRegI src)
12088 %{
12089 predicate( UseSSE>=2 && UseXmmI2D );
12090 match(Set dst (ConvI2D src));
12091
12092 format %{ "MOVD $dst,$src\n\t"
12093 "CVTDQ2PD $dst,$dst\t# i2d" %}
12094 ins_encode %{
12095 __ movdl($dst$$XMMRegister, $src$$Register);
12096 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
12097 %}
12098 ins_pipe(pipe_slow); // XXX
12099 %}
12100
12101 instruct convI2D_mem(regD dst, memory mem) %{
12102 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
12103 match(Set dst (ConvI2D (LoadI mem)));
12104 format %{ "FILD $mem\n\t"
12105 "FSTP $dst" %}
12106 opcode(0xDB); /* DB /0 */
12107 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12108 Pop_Reg_D(dst));
12109 ins_pipe( fpu_reg_mem );
12110 %}
12111
12112 // Convert a byte to a float; no rounding step needed.
12113 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
12114 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
12115 match(Set dst (ConvI2F src));
12116 format %{ "FILD $src\n\t"
12117 "FSTP $dst" %}
12118
12119 opcode(0xDB, 0x0); /* DB /0 */
12120 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
12121 ins_pipe( fpu_reg_mem );
12122 %}
12123
12124 // In 24-bit mode, force exponent rounding by storing back out
12125 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
12126 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
12127 match(Set dst (ConvI2F src));
12128 ins_cost(200);
12129 format %{ "FILD $src\n\t"
12130 "FSTP_S $dst" %}
12131 opcode(0xDB, 0x0); /* DB /0 */
12132 ins_encode( Push_Mem_I(src),
12133 Pop_Mem_F(dst));
12134 ins_pipe( fpu_mem_mem );
12135 %}
12136
12137 // In 24-bit mode, force exponent rounding by storing back out
12138 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
12139 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
12140 match(Set dst (ConvI2F (LoadI mem)));
12141 ins_cost(200);
12142 format %{ "FILD $mem\n\t"
12143 "FSTP_S $dst" %}
12144 opcode(0xDB); /* DB /0 */
12145 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12146 Pop_Mem_F(dst));
12147 ins_pipe( fpu_mem_mem );
12148 %}
12149
12150 // This instruction does not round to 24-bits
12151 instruct convI2F_reg(regF dst, stackSlotI src) %{
12152 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
12153 match(Set dst (ConvI2F src));
12154 format %{ "FILD $src\n\t"
12155 "FSTP $dst" %}
12156 opcode(0xDB, 0x0); /* DB /0 */
12157 ins_encode( Push_Mem_I(src),
12158 Pop_Reg_F(dst));
12159 ins_pipe( fpu_reg_mem );
12160 %}
12161
12162 // This instruction does not round to 24-bits
12163 instruct convI2F_mem(regF dst, memory mem) %{
12164 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
12165 match(Set dst (ConvI2F (LoadI mem)));
12166 format %{ "FILD $mem\n\t"
12167 "FSTP $dst" %}
12168 opcode(0xDB); /* DB /0 */
12169 ins_encode( OpcP, RMopc_Mem(0x00,mem),
12170 Pop_Reg_F(dst));
12171 ins_pipe( fpu_reg_mem );
12172 %}
12173
12174 // Convert an int to a float in xmm; no rounding step needed.
12175 instruct convI2X_reg(regX dst, eRegI src) %{
12176 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
12177 match(Set dst (ConvI2F src));
12178 format %{ "CVTSI2SS $dst, $src" %}
12179
12180 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
12181 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
12182 ins_pipe( pipe_slow );
12183 %}
12184
12185 instruct convXI2X_reg(regX dst, eRegI src)
12186 %{
12187 predicate( UseSSE>=2 && UseXmmI2F );
12188 match(Set dst (ConvI2F src));
12189
12190 format %{ "MOVD $dst,$src\n\t"
12191 "CVTDQ2PS $dst,$dst\t# i2f" %}
12192 ins_encode %{
12193 __ movdl($dst$$XMMRegister, $src$$Register);
12194 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
12195 %}
12196 ins_pipe(pipe_slow); // XXX
12197 %}
12198
12199 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
12200 match(Set dst (ConvI2L src));
12201 effect(KILL cr);
12202 ins_cost(375);
12203 format %{ "MOV $dst.lo,$src\n\t"
12204 "MOV $dst.hi,$src\n\t"
12205 "SAR $dst.hi,31" %}
12206 ins_encode(convert_int_long(dst,src));
12207 ins_pipe( ialu_reg_reg_long );
12208 %}
12209
12210 // Zero-extend convert int to long
12211 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
12212 match(Set dst (AndL (ConvI2L src) mask) );
12213 effect( KILL flags );
12214 ins_cost(250);
12215 format %{ "MOV $dst.lo,$src\n\t"
12216 "XOR $dst.hi,$dst.hi" %}
12217 opcode(0x33); // XOR
12218 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12219 ins_pipe( ialu_reg_reg_long );
12220 %}
12221
12222 // Zero-extend long
12223 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
12224 match(Set dst (AndL src mask) );
12225 effect( KILL flags );
12226 ins_cost(250);
12227 format %{ "MOV $dst.lo,$src.lo\n\t"
12228 "XOR $dst.hi,$dst.hi\n\t" %}
12229 opcode(0x33); // XOR
12230 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12231 ins_pipe( ialu_reg_reg_long );
12232 %}
12233
12234 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
12235 predicate (UseSSE<=1);
12236 match(Set dst (ConvL2D src));
12237 effect( KILL cr );
12238 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12239 "PUSH $src.lo\n\t"
12240 "FILD ST,[ESP + #0]\n\t"
12241 "ADD ESP,8\n\t"
12242 "FSTP_D $dst\t# D-round" %}
12243 opcode(0xDF, 0x5); /* DF /5 */
12244 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
12245 ins_pipe( pipe_slow );
12246 %}
12247
12248 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
12249 predicate (UseSSE>=2);
12250 match(Set dst (ConvL2D src));
12251 effect( KILL cr );
12252 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12253 "PUSH $src.lo\n\t"
12254 "FILD_D [ESP]\n\t"
12255 "FSTP_D [ESP]\n\t"
12256 "MOVSD $dst,[ESP]\n\t"
12257 "ADD ESP,8" %}
12258 opcode(0xDF, 0x5); /* DF /5 */
12259 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
12260 ins_pipe( pipe_slow );
12261 %}
12262
12263 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
12264 predicate (UseSSE>=1);
12265 match(Set dst (ConvL2F src));
12266 effect( KILL cr );
12267 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12268 "PUSH $src.lo\n\t"
12269 "FILD_D [ESP]\n\t"
12270 "FSTP_S [ESP]\n\t"
12271 "MOVSS $dst,[ESP]\n\t"
12272 "ADD ESP,8" %}
12273 opcode(0xDF, 0x5); /* DF /5 */
12274 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
12275 ins_pipe( pipe_slow );
12276 %}
12277
12278 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
12279 match(Set dst (ConvL2F src));
12280 effect( KILL cr );
12281 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12282 "PUSH $src.lo\n\t"
12283 "FILD ST,[ESP + #0]\n\t"
12284 "ADD ESP,8\n\t"
12285 "FSTP_S $dst\t# F-round" %}
12286 opcode(0xDF, 0x5); /* DF /5 */
12287 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
12288 ins_pipe( pipe_slow );
12289 %}
12290
12291 instruct convL2I_reg( eRegI dst, eRegL src ) %{
12292 match(Set dst (ConvL2I src));
12293 effect( DEF dst, USE src );
12294 format %{ "MOV $dst,$src.lo" %}
12295 ins_encode(enc_CopyL_Lo(dst,src));
12296 ins_pipe( ialu_reg_reg );
12297 %}
12298
12299
12300 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
12301 match(Set dst (MoveF2I src));
12302 effect( DEF dst, USE src );
12303 ins_cost(100);
12304 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
12305 opcode(0x8B);
12306 ins_encode( OpcP, RegMem(dst,src));
12307 ins_pipe( ialu_reg_mem );
12308 %}
12309
12310 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12311 predicate(UseSSE==0);
12312 match(Set dst (MoveF2I src));
12313 effect( DEF dst, USE src );
12314
12315 ins_cost(125);
12316 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
12317 ins_encode( Pop_Mem_Reg_F(dst, src) );
12318 ins_pipe( fpu_mem_reg );
12319 %}
12320
12321 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
12322 predicate(UseSSE>=1);
12323 match(Set dst (MoveF2I src));
12324 effect( DEF dst, USE src );
12325
12326 ins_cost(95);
12327 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
12328 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
12329 ins_pipe( pipe_slow );
12330 %}
12331
12332 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
12333 predicate(UseSSE>=2);
12334 match(Set dst (MoveF2I src));
12335 effect( DEF dst, USE src );
12336 ins_cost(85);
12337 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
12338 ins_encode( MovX2I_reg(dst, src));
12339 ins_pipe( pipe_slow );
12340 %}
12341
12342 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12343 match(Set dst (MoveI2F src));
12344 effect( DEF dst, USE src );
12345
12346 ins_cost(100);
12347 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12348 opcode(0x89);
12349 ins_encode( OpcPRegSS( dst, src ) );
12350 ins_pipe( ialu_mem_reg );
12351 %}
12352
12353
12354 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12355 predicate(UseSSE==0);
12356 match(Set dst (MoveI2F src));
12357 effect(DEF dst, USE src);
12358
12359 ins_cost(125);
12360 format %{ "FLD_S $src\n\t"
12361 "FSTP $dst\t# MoveI2F_stack_reg" %}
12362 opcode(0xD9); /* D9 /0, FLD m32real */
12363 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12364 Pop_Reg_F(dst) );
12365 ins_pipe( fpu_reg_mem );
12366 %}
12367
12368 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12369 predicate(UseSSE>=1);
12370 match(Set dst (MoveI2F src));
12371 effect( DEF dst, USE src );
12372
12373 ins_cost(95);
12374 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12375 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12376 ins_pipe( pipe_slow );
12377 %}
12378
12379 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12380 predicate(UseSSE>=2);
12381 match(Set dst (MoveI2F src));
12382 effect( DEF dst, USE src );
12383
12384 ins_cost(85);
12385 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12386 ins_encode( MovI2X_reg(dst, src) );
12387 ins_pipe( pipe_slow );
12388 %}
12389
12390 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12391 match(Set dst (MoveD2L src));
12392 effect(DEF dst, USE src);
12393
12394 ins_cost(250);
12395 format %{ "MOV $dst.lo,$src\n\t"
12396 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12397 opcode(0x8B, 0x8B);
12398 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12399 ins_pipe( ialu_mem_long_reg );
12400 %}
12401
12402 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12403 predicate(UseSSE<=1);
12404 match(Set dst (MoveD2L src));
12405 effect(DEF dst, USE src);
12406
12407 ins_cost(125);
12408 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12409 ins_encode( Pop_Mem_Reg_D(dst, src) );
12410 ins_pipe( fpu_mem_reg );
12411 %}
12412
12413 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12414 predicate(UseSSE>=2);
12415 match(Set dst (MoveD2L src));
12416 effect(DEF dst, USE src);
12417 ins_cost(95);
12418
12419 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12420 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12421 ins_pipe( pipe_slow );
12422 %}
12423
12424 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12425 predicate(UseSSE>=2);
12426 match(Set dst (MoveD2L src));
12427 effect(DEF dst, USE src, TEMP tmp);
12428 ins_cost(85);
12429 format %{ "MOVD $dst.lo,$src\n\t"
12430 "PSHUFLW $tmp,$src,0x4E\n\t"
12431 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12432 ins_encode( MovXD2L_reg(dst, src, tmp) );
12433 ins_pipe( pipe_slow );
12434 %}
12435
12436 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12437 match(Set dst (MoveL2D src));
12438 effect(DEF dst, USE src);
12439
12440 ins_cost(200);
12441 format %{ "MOV $dst,$src.lo\n\t"
12442 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12443 opcode(0x89, 0x89);
12444 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12445 ins_pipe( ialu_mem_long_reg );
12446 %}
12447
12448
12449 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12450 predicate(UseSSE<=1);
12451 match(Set dst (MoveL2D src));
12452 effect(DEF dst, USE src);
12453 ins_cost(125);
12454
12455 format %{ "FLD_D $src\n\t"
12456 "FSTP $dst\t# MoveL2D_stack_reg" %}
12457 opcode(0xDD); /* DD /0, FLD m64real */
12458 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12459 Pop_Reg_D(dst) );
12460 ins_pipe( fpu_reg_mem );
12461 %}
12462
12463
12464 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12465 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12466 match(Set dst (MoveL2D src));
12467 effect(DEF dst, USE src);
12468
12469 ins_cost(95);
12470 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12471 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12472 ins_pipe( pipe_slow );
12473 %}
12474
12475 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12476 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12477 match(Set dst (MoveL2D src));
12478 effect(DEF dst, USE src);
12479
12480 ins_cost(95);
12481 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12482 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12483 ins_pipe( pipe_slow );
12484 %}
12485
12486 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12487 predicate(UseSSE>=2);
12488 match(Set dst (MoveL2D src));
12489 effect(TEMP dst, USE src, TEMP tmp);
12490 ins_cost(85);
12491 format %{ "MOVD $dst,$src.lo\n\t"
12492 "MOVD $tmp,$src.hi\n\t"
12493 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12494 ins_encode( MovL2XD_reg(dst, src, tmp) );
12495 ins_pipe( pipe_slow );
12496 %}
12497
12498 // Replicate scalar to packed byte (1 byte) values in xmm
12499 instruct Repl8B_reg(regXD dst, regXD src) %{
12500 predicate(UseSSE>=2);
12501 match(Set dst (Replicate8B src));
12502 format %{ "MOVDQA $dst,$src\n\t"
12503 "PUNPCKLBW $dst,$dst\n\t"
12504 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12505 ins_encode( pshufd_8x8(dst, src));
12506 ins_pipe( pipe_slow );
12507 %}
12508
12509 // Replicate scalar to packed byte (1 byte) values in xmm
12510 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12511 predicate(UseSSE>=2);
12512 match(Set dst (Replicate8B src));
12513 format %{ "MOVD $dst,$src\n\t"
12514 "PUNPCKLBW $dst,$dst\n\t"
12515 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12516 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12517 ins_pipe( pipe_slow );
12518 %}
12519
12520 // Replicate scalar zero to packed byte (1 byte) values in xmm
12521 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12522 predicate(UseSSE>=2);
12523 match(Set dst (Replicate8B zero));
12524 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12525 ins_encode( pxor(dst, dst));
12526 ins_pipe( fpu_reg_reg );
12527 %}
12528
12529 // Replicate scalar to packed shore (2 byte) values in xmm
12530 instruct Repl4S_reg(regXD dst, regXD src) %{
12531 predicate(UseSSE>=2);
12532 match(Set dst (Replicate4S src));
12533 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12534 ins_encode( pshufd_4x16(dst, src));
12535 ins_pipe( fpu_reg_reg );
12536 %}
12537
12538 // Replicate scalar to packed shore (2 byte) values in xmm
12539 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12540 predicate(UseSSE>=2);
12541 match(Set dst (Replicate4S src));
12542 format %{ "MOVD $dst,$src\n\t"
12543 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12544 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12545 ins_pipe( fpu_reg_reg );
12546 %}
12547
12548 // Replicate scalar zero to packed short (2 byte) values in xmm
12549 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12550 predicate(UseSSE>=2);
12551 match(Set dst (Replicate4S zero));
12552 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12553 ins_encode( pxor(dst, dst));
12554 ins_pipe( fpu_reg_reg );
12555 %}
12556
12557 // Replicate scalar to packed char (2 byte) values in xmm
12558 instruct Repl4C_reg(regXD dst, regXD src) %{
12559 predicate(UseSSE>=2);
12560 match(Set dst (Replicate4C src));
12561 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12562 ins_encode( pshufd_4x16(dst, src));
12563 ins_pipe( fpu_reg_reg );
12564 %}
12565
12566 // Replicate scalar to packed char (2 byte) values in xmm
12567 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12568 predicate(UseSSE>=2);
12569 match(Set dst (Replicate4C src));
12570 format %{ "MOVD $dst,$src\n\t"
12571 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12572 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12573 ins_pipe( fpu_reg_reg );
12574 %}
12575
12576 // Replicate scalar zero to packed char (2 byte) values in xmm
12577 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12578 predicate(UseSSE>=2);
12579 match(Set dst (Replicate4C zero));
12580 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12581 ins_encode( pxor(dst, dst));
12582 ins_pipe( fpu_reg_reg );
12583 %}
12584
12585 // Replicate scalar to packed integer (4 byte) values in xmm
12586 instruct Repl2I_reg(regXD dst, regXD src) %{
12587 predicate(UseSSE>=2);
12588 match(Set dst (Replicate2I src));
12589 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12590 ins_encode( pshufd(dst, src, 0x00));
12591 ins_pipe( fpu_reg_reg );
12592 %}
12593
12594 // Replicate scalar to packed integer (4 byte) values in xmm
12595 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12596 predicate(UseSSE>=2);
12597 match(Set dst (Replicate2I src));
12598 format %{ "MOVD $dst,$src\n\t"
12599 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12600 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12601 ins_pipe( fpu_reg_reg );
12602 %}
12603
12604 // Replicate scalar zero to packed integer (2 byte) values in xmm
12605 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12606 predicate(UseSSE>=2);
12607 match(Set dst (Replicate2I zero));
12608 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12609 ins_encode( pxor(dst, dst));
12610 ins_pipe( fpu_reg_reg );
12611 %}
12612
12613 // Replicate scalar to packed single precision floating point values in xmm
12614 instruct Repl2F_reg(regXD dst, regXD src) %{
12615 predicate(UseSSE>=2);
12616 match(Set dst (Replicate2F src));
12617 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12618 ins_encode( pshufd(dst, src, 0xe0));
12619 ins_pipe( fpu_reg_reg );
12620 %}
12621
12622 // Replicate scalar to packed single precision floating point values in xmm
12623 instruct Repl2F_regX(regXD dst, regX src) %{
12624 predicate(UseSSE>=2);
12625 match(Set dst (Replicate2F src));
12626 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12627 ins_encode( pshufd(dst, src, 0xe0));
12628 ins_pipe( fpu_reg_reg );
12629 %}
12630
12631 // Replicate scalar to packed single precision floating point values in xmm
12632 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12633 predicate(UseSSE>=2);
12634 match(Set dst (Replicate2F zero));
12635 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12636 ins_encode( pxor(dst, dst));
12637 ins_pipe( fpu_reg_reg );
12638 %}
12639
12640 // =======================================================================
12641 // fast clearing of an array
12642 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12643 match(Set dummy (ClearArray cnt base));
12644 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12645 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12646 "XOR EAX,EAX\n\t"
12647 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12648 opcode(0,0x4);
12649 ins_encode( Opcode(0xD1), RegOpc(ECX),
12650 OpcRegReg(0x33,EAX,EAX),
12651 Opcode(0xF3), Opcode(0xAB) );
12652 ins_pipe( pipe_slow );
12653 %}
12654
12655 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
12656 eAXRegI result, regXD tmp1, eFlagsReg cr) %{
12657 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12658 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12659
12660 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12661 ins_encode %{
12662 __ string_compare($str1$$Register, $str2$$Register,
12663 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12664 $tmp1$$XMMRegister);
12665 %}
12666 ins_pipe( pipe_slow );
12667 %}
12668
12669 // fast string equals
12670 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
12671 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
12672 match(Set result (StrEquals (Binary str1 str2) cnt));
12673 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12674
12675 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12676 ins_encode %{
12677 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12678 $cnt$$Register, $result$$Register, $tmp3$$Register,
12679 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12680 %}
12681 ins_pipe( pipe_slow );
12682 %}
12683
12684 // fast search of substring with known size.
12685 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
12686 eBXRegI result, regXD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
12687 predicate(UseSSE42Intrinsics);
12688 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12689 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12690
12691 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
12692 ins_encode %{
12693 int icnt2 = (int)$int_cnt2$$constant;
12694 if (icnt2 >= 8) {
12695 // IndexOf for constant substrings with size >= 8 elements
12696 // which don't need to be loaded through stack.
12697 __ string_indexofC8($str1$$Register, $str2$$Register,
12698 $cnt1$$Register, $cnt2$$Register,
12699 icnt2, $result$$Register,
12700 $vec$$XMMRegister, $tmp$$Register);
12701 } else {
12702 // Small strings are loaded through stack if they cross page boundary.
12703 __ string_indexof($str1$$Register, $str2$$Register,
12704 $cnt1$$Register, $cnt2$$Register,
12705 icnt2, $result$$Register,
12706 $vec$$XMMRegister, $tmp$$Register);
12707 }
12708 %}
12709 ins_pipe( pipe_slow );
12710 %}
12711
12712 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12713 eBXRegI result, regXD vec, eCXRegI tmp, eFlagsReg cr) %{
12714 predicate(UseSSE42Intrinsics);
12715 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12716 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12717
12718 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12719 ins_encode %{
12720 __ string_indexof($str1$$Register, $str2$$Register,
12721 $cnt1$$Register, $cnt2$$Register,
12722 (-1), $result$$Register,
12723 $vec$$XMMRegister, $tmp$$Register);
12724 %}
12725 ins_pipe( pipe_slow );
12726 %}
12727
12728 // fast array equals
12729 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12730 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12731 %{
12732 match(Set result (AryEq ary1 ary2));
12733 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12734 //ins_cost(300);
12735
12736 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12737 ins_encode %{
12738 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12739 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12740 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12741 %}
12742 ins_pipe( pipe_slow );
12743 %}
12744
12745 //----------Control Flow Instructions------------------------------------------
12746 // Signed compare Instructions
12747 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12748 match(Set cr (CmpI op1 op2));
12749 effect( DEF cr, USE op1, USE op2 );
12750 format %{ "CMP $op1,$op2" %}
12751 opcode(0x3B); /* Opcode 3B /r */
12752 ins_encode( OpcP, RegReg( op1, op2) );
12753 ins_pipe( ialu_cr_reg_reg );
12754 %}
12755
12756 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12757 match(Set cr (CmpI op1 op2));
12758 effect( DEF cr, USE op1 );
12759 format %{ "CMP $op1,$op2" %}
12760 opcode(0x81,0x07); /* Opcode 81 /7 */
12761 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12762 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12763 ins_pipe( ialu_cr_reg_imm );
12764 %}
12765
12766 // Cisc-spilled version of cmpI_eReg
12767 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12768 match(Set cr (CmpI op1 (LoadI op2)));
12769
12770 format %{ "CMP $op1,$op2" %}
12771 ins_cost(500);
12772 opcode(0x3B); /* Opcode 3B /r */
12773 ins_encode( OpcP, RegMem( op1, op2) );
12774 ins_pipe( ialu_cr_reg_mem );
12775 %}
12776
12777 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12778 match(Set cr (CmpI src zero));
12779 effect( DEF cr, USE src );
12780
12781 format %{ "TEST $src,$src" %}
12782 opcode(0x85);
12783 ins_encode( OpcP, RegReg( src, src ) );
12784 ins_pipe( ialu_cr_reg_imm );
12785 %}
12786
12787 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12788 match(Set cr (CmpI (AndI src con) zero));
12789
12790 format %{ "TEST $src,$con" %}
12791 opcode(0xF7,0x00);
12792 ins_encode( OpcP, RegOpc(src), Con32(con) );
12793 ins_pipe( ialu_cr_reg_imm );
12794 %}
12795
12796 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12797 match(Set cr (CmpI (AndI src mem) zero));
12798
12799 format %{ "TEST $src,$mem" %}
12800 opcode(0x85);
12801 ins_encode( OpcP, RegMem( src, mem ) );
12802 ins_pipe( ialu_cr_reg_mem );
12803 %}
12804
12805 // Unsigned compare Instructions; really, same as signed except they
12806 // produce an eFlagsRegU instead of eFlagsReg.
12807 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12808 match(Set cr (CmpU op1 op2));
12809
12810 format %{ "CMPu $op1,$op2" %}
12811 opcode(0x3B); /* Opcode 3B /r */
12812 ins_encode( OpcP, RegReg( op1, op2) );
12813 ins_pipe( ialu_cr_reg_reg );
12814 %}
12815
12816 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12817 match(Set cr (CmpU op1 op2));
12818
12819 format %{ "CMPu $op1,$op2" %}
12820 opcode(0x81,0x07); /* Opcode 81 /7 */
12821 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12822 ins_pipe( ialu_cr_reg_imm );
12823 %}
12824
12825 // // Cisc-spilled version of cmpU_eReg
12826 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12827 match(Set cr (CmpU op1 (LoadI op2)));
12828
12829 format %{ "CMPu $op1,$op2" %}
12830 ins_cost(500);
12831 opcode(0x3B); /* Opcode 3B /r */
12832 ins_encode( OpcP, RegMem( op1, op2) );
12833 ins_pipe( ialu_cr_reg_mem );
12834 %}
12835
12836 // // Cisc-spilled version of cmpU_eReg
12837 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12838 // match(Set cr (CmpU (LoadI op1) op2));
12839 //
12840 // format %{ "CMPu $op1,$op2" %}
12841 // ins_cost(500);
12842 // opcode(0x39); /* Opcode 39 /r */
12843 // ins_encode( OpcP, RegMem( op1, op2) );
12844 //%}
12845
12846 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12847 match(Set cr (CmpU src zero));
12848
12849 format %{ "TESTu $src,$src" %}
12850 opcode(0x85);
12851 ins_encode( OpcP, RegReg( src, src ) );
12852 ins_pipe( ialu_cr_reg_imm );
12853 %}
12854
12855 // Unsigned pointer compare Instructions
12856 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12857 match(Set cr (CmpP op1 op2));
12858
12859 format %{ "CMPu $op1,$op2" %}
12860 opcode(0x3B); /* Opcode 3B /r */
12861 ins_encode( OpcP, RegReg( op1, op2) );
12862 ins_pipe( ialu_cr_reg_reg );
12863 %}
12864
12865 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12866 match(Set cr (CmpP op1 op2));
12867
12868 format %{ "CMPu $op1,$op2" %}
12869 opcode(0x81,0x07); /* Opcode 81 /7 */
12870 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12871 ins_pipe( ialu_cr_reg_imm );
12872 %}
12873
12874 // // Cisc-spilled version of cmpP_eReg
12875 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12876 match(Set cr (CmpP op1 (LoadP op2)));
12877
12878 format %{ "CMPu $op1,$op2" %}
12879 ins_cost(500);
12880 opcode(0x3B); /* Opcode 3B /r */
12881 ins_encode( OpcP, RegMem( op1, op2) );
12882 ins_pipe( ialu_cr_reg_mem );
12883 %}
12884
12885 // // Cisc-spilled version of cmpP_eReg
12886 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12887 // match(Set cr (CmpP (LoadP op1) op2));
12888 //
12889 // format %{ "CMPu $op1,$op2" %}
12890 // ins_cost(500);
12891 // opcode(0x39); /* Opcode 39 /r */
12892 // ins_encode( OpcP, RegMem( op1, op2) );
12893 //%}
12894
12895 // Compare raw pointer (used in out-of-heap check).
12896 // Only works because non-oop pointers must be raw pointers
12897 // and raw pointers have no anti-dependencies.
12898 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12899 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12900 match(Set cr (CmpP op1 (LoadP op2)));
12901
12902 format %{ "CMPu $op1,$op2" %}
12903 opcode(0x3B); /* Opcode 3B /r */
12904 ins_encode( OpcP, RegMem( op1, op2) );
12905 ins_pipe( ialu_cr_reg_mem );
12906 %}
12907
12908 //
12909 // This will generate a signed flags result. This should be ok
12910 // since any compare to a zero should be eq/neq.
12911 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12912 match(Set cr (CmpP src zero));
12913
12914 format %{ "TEST $src,$src" %}
12915 opcode(0x85);
12916 ins_encode( OpcP, RegReg( src, src ) );
12917 ins_pipe( ialu_cr_reg_imm );
12918 %}
12919
12920 // Cisc-spilled version of testP_reg
12921 // This will generate a signed flags result. This should be ok
12922 // since any compare to a zero should be eq/neq.
12923 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12924 match(Set cr (CmpP (LoadP op) zero));
12925
12926 format %{ "TEST $op,0xFFFFFFFF" %}
12927 ins_cost(500);
12928 opcode(0xF7); /* Opcode F7 /0 */
12929 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12930 ins_pipe( ialu_cr_reg_imm );
12931 %}
12932
12933 // Yanked all unsigned pointer compare operations.
12934 // Pointer compares are done with CmpP which is already unsigned.
12935
12936 //----------Max and Min--------------------------------------------------------
12937 // Min Instructions
12938 ////
12939 // *** Min and Max using the conditional move are slower than the
12940 // *** branch version on a Pentium III.
12941 // // Conditional move for min
12942 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12943 // effect( USE_DEF op2, USE op1, USE cr );
12944 // format %{ "CMOVlt $op2,$op1\t! min" %}
12945 // opcode(0x4C,0x0F);
12946 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12947 // ins_pipe( pipe_cmov_reg );
12948 //%}
12949 //
12950 //// Min Register with Register (P6 version)
12951 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12952 // predicate(VM_Version::supports_cmov() );
12953 // match(Set op2 (MinI op1 op2));
12954 // ins_cost(200);
12955 // expand %{
12956 // eFlagsReg cr;
12957 // compI_eReg(cr,op1,op2);
12958 // cmovI_reg_lt(op2,op1,cr);
12959 // %}
12960 //%}
12961
12962 // Min Register with Register (generic version)
12963 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12964 match(Set dst (MinI dst src));
12965 effect(KILL flags);
12966 ins_cost(300);
12967
12968 format %{ "MIN $dst,$src" %}
12969 opcode(0xCC);
12970 ins_encode( min_enc(dst,src) );
12971 ins_pipe( pipe_slow );
12972 %}
12973
12974 // Max Register with Register
12975 // *** Min and Max using the conditional move are slower than the
12976 // *** branch version on a Pentium III.
12977 // // Conditional move for max
12978 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12979 // effect( USE_DEF op2, USE op1, USE cr );
12980 // format %{ "CMOVgt $op2,$op1\t! max" %}
12981 // opcode(0x4F,0x0F);
12982 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12983 // ins_pipe( pipe_cmov_reg );
12984 //%}
12985 //
12986 // // Max Register with Register (P6 version)
12987 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12988 // predicate(VM_Version::supports_cmov() );
12989 // match(Set op2 (MaxI op1 op2));
12990 // ins_cost(200);
12991 // expand %{
12992 // eFlagsReg cr;
12993 // compI_eReg(cr,op1,op2);
12994 // cmovI_reg_gt(op2,op1,cr);
12995 // %}
12996 //%}
12997
12998 // Max Register with Register (generic version)
12999 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
13000 match(Set dst (MaxI dst src));
13001 effect(KILL flags);
13002 ins_cost(300);
13003
13004 format %{ "MAX $dst,$src" %}
13005 opcode(0xCC);
13006 ins_encode( max_enc(dst,src) );
13007 ins_pipe( pipe_slow );
13008 %}
13009
13010 // ============================================================================
13011 // Counted Loop limit node which represents exact final iterator value.
13012 // Note: the resulting value should fit into integer range since
13013 // counted loops have limit check on overflow.
13014 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
13015 match(Set limit (LoopLimit (Binary init limit) stride));
13016 effect(TEMP limit_hi, TEMP tmp, KILL flags);
13017 ins_cost(300);
13018
13019 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
13020 ins_encode %{
13021 int strd = (int)$stride$$constant;
13022 assert(strd != 1 && strd != -1, "sanity");
13023 int m1 = (strd > 0) ? 1 : -1;
13024 // Convert limit to long (EAX:EDX)
13025 __ cdql();
13026 // Convert init to long (init:tmp)
13027 __ movl($tmp$$Register, $init$$Register);
13028 __ sarl($tmp$$Register, 31);
13029 // $limit - $init
13030 __ subl($limit$$Register, $init$$Register);
13031 __ sbbl($limit_hi$$Register, $tmp$$Register);
13032 // + ($stride - 1)
13033 if (strd > 0) {
13034 __ addl($limit$$Register, (strd - 1));
13035 __ adcl($limit_hi$$Register, 0);
13036 __ movl($tmp$$Register, strd);
13037 } else {
13038 __ addl($limit$$Register, (strd + 1));
13039 __ adcl($limit_hi$$Register, -1);
13040 __ lneg($limit_hi$$Register, $limit$$Register);
13041 __ movl($tmp$$Register, -strd);
13042 }
13043 // signed devision: (EAX:EDX) / pos_stride
13044 __ idivl($tmp$$Register);
13045 if (strd < 0) {
13046 // restore sign
13047 __ negl($tmp$$Register);
13048 }
13049 // (EAX) * stride
13050 __ mull($tmp$$Register);
13051 // + init (ignore upper bits)
13052 __ addl($limit$$Register, $init$$Register);
13053 %}
13054 ins_pipe( pipe_slow );
13055 %}
13056
13057 // ============================================================================
13058 // Branch Instructions
13059 // Jump Table
13060 instruct jumpXtnd(eRegI switch_val) %{
13061 match(Jump switch_val);
13062 ins_cost(350);
13063 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
13064 ins_encode %{
13065 // Jump to Address(table_base + switch_reg)
13066 Address index(noreg, $switch_val$$Register, Address::times_1);
13067 __ jump(ArrayAddress($constantaddress, index));
13068 %}
13069 ins_pipe(pipe_jmp);
13070 %}
13071
13072 // Jump Direct - Label defines a relative address from JMP+1
13073 instruct jmpDir(label labl) %{
13074 match(Goto);
13075 effect(USE labl);
13076
13077 ins_cost(300);
13078 format %{ "JMP $labl" %}
13079 size(5);
13080 ins_encode %{
13081 Label* L = $labl$$label;
13082 __ jmp(*L, false); // Always long jump
13083 %}
13084 ins_pipe( pipe_jmp );
13085 %}
13086
13087 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13088 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
13089 match(If cop cr);
13090 effect(USE labl);
13091
13092 ins_cost(300);
13093 format %{ "J$cop $labl" %}
13094 size(6);
13095 ins_encode %{
13096 Label* L = $labl$$label;
13097 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13098 %}
13099 ins_pipe( pipe_jcc );
13100 %}
13101
13102 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13103 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
13104 match(CountedLoopEnd cop cr);
13105 effect(USE labl);
13106
13107 ins_cost(300);
13108 format %{ "J$cop $labl\t# Loop end" %}
13109 size(6);
13110 ins_encode %{
13111 Label* L = $labl$$label;
13112 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13113 %}
13114 ins_pipe( pipe_jcc );
13115 %}
13116
13117 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13118 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13119 match(CountedLoopEnd cop cmp);
13120 effect(USE labl);
13121
13122 ins_cost(300);
13123 format %{ "J$cop,u $labl\t# Loop end" %}
13124 size(6);
13125 ins_encode %{
13126 Label* L = $labl$$label;
13127 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13128 %}
13129 ins_pipe( pipe_jcc );
13130 %}
13131
13132 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13133 match(CountedLoopEnd cop cmp);
13134 effect(USE labl);
13135
13136 ins_cost(200);
13137 format %{ "J$cop,u $labl\t# Loop end" %}
13138 size(6);
13139 ins_encode %{
13140 Label* L = $labl$$label;
13141 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13142 %}
13143 ins_pipe( pipe_jcc );
13144 %}
13145
13146 // Jump Direct Conditional - using unsigned comparison
13147 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13148 match(If cop cmp);
13149 effect(USE labl);
13150
13151 ins_cost(300);
13152 format %{ "J$cop,u $labl" %}
13153 size(6);
13154 ins_encode %{
13155 Label* L = $labl$$label;
13156 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13157 %}
13158 ins_pipe(pipe_jcc);
13159 %}
13160
13161 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13162 match(If cop cmp);
13163 effect(USE labl);
13164
13165 ins_cost(200);
13166 format %{ "J$cop,u $labl" %}
13167 size(6);
13168 ins_encode %{
13169 Label* L = $labl$$label;
13170 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13171 %}
13172 ins_pipe(pipe_jcc);
13173 %}
13174
13175 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13176 match(If cop cmp);
13177 effect(USE labl);
13178
13179 ins_cost(200);
13180 format %{ $$template
13181 if ($cop$$cmpcode == Assembler::notEqual) {
13182 $$emit$$"JP,u $labl\n\t"
13183 $$emit$$"J$cop,u $labl"
13184 } else {
13185 $$emit$$"JP,u done\n\t"
13186 $$emit$$"J$cop,u $labl\n\t"
13187 $$emit$$"done:"
13188 }
13189 %}
13190 ins_encode %{
13191 Label* l = $labl$$label;
13192 if ($cop$$cmpcode == Assembler::notEqual) {
13193 __ jcc(Assembler::parity, *l, false);
13194 __ jcc(Assembler::notEqual, *l, false);
13195 } else if ($cop$$cmpcode == Assembler::equal) {
13196 Label done;
13197 __ jccb(Assembler::parity, done);
13198 __ jcc(Assembler::equal, *l, false);
13199 __ bind(done);
13200 } else {
13201 ShouldNotReachHere();
13202 }
13203 %}
13204 ins_pipe(pipe_jcc);
13205 %}
13206
13207 // ============================================================================
13208 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
13209 // array for an instance of the superklass. Set a hidden internal cache on a
13210 // hit (cache is checked with exposed code in gen_subtype_check()). Return
13211 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
13212 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
13213 match(Set result (PartialSubtypeCheck sub super));
13214 effect( KILL rcx, KILL cr );
13215
13216 ins_cost(1100); // slightly larger than the next version
13217 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13218 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13219 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13220 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13221 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
13222 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
13223 "XOR $result,$result\t\t Hit: EDI zero\n\t"
13224 "miss:\t" %}
13225
13226 opcode(0x1); // Force a XOR of EDI
13227 ins_encode( enc_PartialSubtypeCheck() );
13228 ins_pipe( pipe_slow );
13229 %}
13230
13231 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
13232 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
13233 effect( KILL rcx, KILL result );
13234
13235 ins_cost(1000);
13236 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
13237 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
13238 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
13239 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
13240 "JNE,s miss\t\t# Missed: flags NZ\n\t"
13241 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
13242 "miss:\t" %}
13243
13244 opcode(0x0); // No need to XOR EDI
13245 ins_encode( enc_PartialSubtypeCheck() );
13246 ins_pipe( pipe_slow );
13247 %}
13248
13249 // ============================================================================
13250 // Branch Instructions -- short offset versions
13251 //
13252 // These instructions are used to replace jumps of a long offset (the default
13253 // match) with jumps of a shorter offset. These instructions are all tagged
13254 // with the ins_short_branch attribute, which causes the ADLC to suppress the
13255 // match rules in general matching. Instead, the ADLC generates a conversion
13256 // method in the MachNode which can be used to do in-place replacement of the
13257 // long variant with the shorter variant. The compiler will determine if a
13258 // branch can be taken by the is_short_branch_offset() predicate in the machine
13259 // specific code section of the file.
13260
13261 // Jump Direct - Label defines a relative address from JMP+1
13262 instruct jmpDir_short(label labl) %{
13263 match(Goto);
13264 effect(USE labl);
13265
13266 ins_cost(300);
13267 format %{ "JMP,s $labl" %}
13268 size(2);
13269 ins_encode %{
13270 Label* L = $labl$$label;
13271 __ jmpb(*L);
13272 %}
13273 ins_pipe( pipe_jmp );
13274 ins_short_branch(1);
13275 %}
13276
13277 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13278 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
13279 match(If cop cr);
13280 effect(USE labl);
13281
13282 ins_cost(300);
13283 format %{ "J$cop,s $labl" %}
13284 size(2);
13285 ins_encode %{
13286 Label* L = $labl$$label;
13287 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13288 %}
13289 ins_pipe( pipe_jcc );
13290 ins_short_branch(1);
13291 %}
13292
13293 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13294 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
13295 match(CountedLoopEnd cop cr);
13296 effect(USE labl);
13297
13298 ins_cost(300);
13299 format %{ "J$cop,s $labl\t# Loop end" %}
13300 size(2);
13301 ins_encode %{
13302 Label* L = $labl$$label;
13303 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13304 %}
13305 ins_pipe( pipe_jcc );
13306 ins_short_branch(1);
13307 %}
13308
13309 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13310 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13311 match(CountedLoopEnd cop cmp);
13312 effect(USE labl);
13313
13314 ins_cost(300);
13315 format %{ "J$cop,us $labl\t# Loop end" %}
13316 size(2);
13317 ins_encode %{
13318 Label* L = $labl$$label;
13319 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13320 %}
13321 ins_pipe( pipe_jcc );
13322 ins_short_branch(1);
13323 %}
13324
13325 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13326 match(CountedLoopEnd cop cmp);
13327 effect(USE labl);
13328
13329 ins_cost(300);
13330 format %{ "J$cop,us $labl\t# Loop end" %}
13331 size(2);
13332 ins_encode %{
13333 Label* L = $labl$$label;
13334 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13335 %}
13336 ins_pipe( pipe_jcc );
13337 ins_short_branch(1);
13338 %}
13339
13340 // Jump Direct Conditional - using unsigned comparison
13341 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13342 match(If cop cmp);
13343 effect(USE labl);
13344
13345 ins_cost(300);
13346 format %{ "J$cop,us $labl" %}
13347 size(2);
13348 ins_encode %{
13349 Label* L = $labl$$label;
13350 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13351 %}
13352 ins_pipe( pipe_jcc );
13353 ins_short_branch(1);
13354 %}
13355
13356 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13357 match(If cop cmp);
13358 effect(USE labl);
13359
13360 ins_cost(300);
13361 format %{ "J$cop,us $labl" %}
13362 size(2);
13363 ins_encode %{
13364 Label* L = $labl$$label;
13365 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13366 %}
13367 ins_pipe( pipe_jcc );
13368 ins_short_branch(1);
13369 %}
13370
13371 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13372 match(If cop cmp);
13373 effect(USE labl);
13374
13375 ins_cost(300);
13376 format %{ $$template
13377 if ($cop$$cmpcode == Assembler::notEqual) {
13378 $$emit$$"JP,u,s $labl\n\t"
13379 $$emit$$"J$cop,u,s $labl"
13380 } else {
13381 $$emit$$"JP,u,s done\n\t"
13382 $$emit$$"J$cop,u,s $labl\n\t"
13383 $$emit$$"done:"
13384 }
13385 %}
13386 size(4);
13387 ins_encode %{
13388 Label* l = $labl$$label;
13389 if ($cop$$cmpcode == Assembler::notEqual) {
13390 __ jccb(Assembler::parity, *l);
13391 __ jccb(Assembler::notEqual, *l);
13392 } else if ($cop$$cmpcode == Assembler::equal) {
13393 Label done;
13394 __ jccb(Assembler::parity, done);
13395 __ jccb(Assembler::equal, *l);
13396 __ bind(done);
13397 } else {
13398 ShouldNotReachHere();
13399 }
13400 %}
13401 ins_pipe(pipe_jcc);
13402 ins_short_branch(1);
13403 %}
13404
13405 // ============================================================================
13406 // Long Compare
13407 //
13408 // Currently we hold longs in 2 registers. Comparing such values efficiently
13409 // is tricky. The flavor of compare used depends on whether we are testing
13410 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13411 // The GE test is the negated LT test. The LE test can be had by commuting
13412 // the operands (yielding a GE test) and then negating; negate again for the
13413 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13414 // NE test is negated from that.
13415
13416 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13417 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13418 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13419 // are collapsed internally in the ADLC's dfa-gen code. The match for
13420 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13421 // foo match ends up with the wrong leaf. One fix is to not match both
13422 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13423 // both forms beat the trinary form of long-compare and both are very useful
13424 // on Intel which has so few registers.
13425
13426 // Manifest a CmpL result in an integer register. Very painful.
13427 // This is the test to avoid.
13428 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13429 match(Set dst (CmpL3 src1 src2));
13430 effect( KILL flags );
13431 ins_cost(1000);
13432 format %{ "XOR $dst,$dst\n\t"
13433 "CMP $src1.hi,$src2.hi\n\t"
13434 "JLT,s m_one\n\t"
13435 "JGT,s p_one\n\t"
13436 "CMP $src1.lo,$src2.lo\n\t"
13437 "JB,s m_one\n\t"
13438 "JEQ,s done\n"
13439 "p_one:\tINC $dst\n\t"
13440 "JMP,s done\n"
13441 "m_one:\tDEC $dst\n"
13442 "done:" %}
13443 ins_encode %{
13444 Label p_one, m_one, done;
13445 __ xorptr($dst$$Register, $dst$$Register);
13446 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13447 __ jccb(Assembler::less, m_one);
13448 __ jccb(Assembler::greater, p_one);
13449 __ cmpl($src1$$Register, $src2$$Register);
13450 __ jccb(Assembler::below, m_one);
13451 __ jccb(Assembler::equal, done);
13452 __ bind(p_one);
13453 __ incrementl($dst$$Register);
13454 __ jmpb(done);
13455 __ bind(m_one);
13456 __ decrementl($dst$$Register);
13457 __ bind(done);
13458 %}
13459 ins_pipe( pipe_slow );
13460 %}
13461
13462 //======
13463 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13464 // compares. Can be used for LE or GT compares by reversing arguments.
13465 // NOT GOOD FOR EQ/NE tests.
13466 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13467 match( Set flags (CmpL src zero ));
13468 ins_cost(100);
13469 format %{ "TEST $src.hi,$src.hi" %}
13470 opcode(0x85);
13471 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13472 ins_pipe( ialu_cr_reg_reg );
13473 %}
13474
13475 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13476 // compares. Can be used for LE or GT compares by reversing arguments.
13477 // NOT GOOD FOR EQ/NE tests.
13478 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13479 match( Set flags (CmpL src1 src2 ));
13480 effect( TEMP tmp );
13481 ins_cost(300);
13482 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13483 "MOV $tmp,$src1.hi\n\t"
13484 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13485 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13486 ins_pipe( ialu_cr_reg_reg );
13487 %}
13488
13489 // Long compares reg < zero/req OR reg >= zero/req.
13490 // Just a wrapper for a normal branch, plus the predicate test.
13491 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13492 match(If cmp flags);
13493 effect(USE labl);
13494 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13495 expand %{
13496 jmpCon(cmp,flags,labl); // JLT or JGE...
13497 %}
13498 %}
13499
13500 // Compare 2 longs and CMOVE longs.
13501 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13502 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13503 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13504 ins_cost(400);
13505 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13506 "CMOV$cmp $dst.hi,$src.hi" %}
13507 opcode(0x0F,0x40);
13508 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13509 ins_pipe( pipe_cmov_reg_long );
13510 %}
13511
13512 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13513 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13514 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13515 ins_cost(500);
13516 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13517 "CMOV$cmp $dst.hi,$src.hi" %}
13518 opcode(0x0F,0x40);
13519 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13520 ins_pipe( pipe_cmov_reg_long );
13521 %}
13522
13523 // Compare 2 longs and CMOVE ints.
13524 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13525 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13526 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13527 ins_cost(200);
13528 format %{ "CMOV$cmp $dst,$src" %}
13529 opcode(0x0F,0x40);
13530 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13531 ins_pipe( pipe_cmov_reg );
13532 %}
13533
13534 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13535 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13536 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13537 ins_cost(250);
13538 format %{ "CMOV$cmp $dst,$src" %}
13539 opcode(0x0F,0x40);
13540 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13541 ins_pipe( pipe_cmov_mem );
13542 %}
13543
13544 // Compare 2 longs and CMOVE ints.
13545 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13546 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13547 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13548 ins_cost(200);
13549 format %{ "CMOV$cmp $dst,$src" %}
13550 opcode(0x0F,0x40);
13551 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13552 ins_pipe( pipe_cmov_reg );
13553 %}
13554
13555 // Compare 2 longs and CMOVE doubles
13556 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13557 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13558 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13559 ins_cost(200);
13560 expand %{
13561 fcmovD_regS(cmp,flags,dst,src);
13562 %}
13563 %}
13564
13565 // Compare 2 longs and CMOVE doubles
13566 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13567 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13568 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13569 ins_cost(200);
13570 expand %{
13571 fcmovXD_regS(cmp,flags,dst,src);
13572 %}
13573 %}
13574
13575 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13576 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13577 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13578 ins_cost(200);
13579 expand %{
13580 fcmovF_regS(cmp,flags,dst,src);
13581 %}
13582 %}
13583
13584 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13585 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13586 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13587 ins_cost(200);
13588 expand %{
13589 fcmovX_regS(cmp,flags,dst,src);
13590 %}
13591 %}
13592
13593 //======
13594 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13595 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13596 match( Set flags (CmpL src zero ));
13597 effect(TEMP tmp);
13598 ins_cost(200);
13599 format %{ "MOV $tmp,$src.lo\n\t"
13600 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13601 ins_encode( long_cmp_flags0( src, tmp ) );
13602 ins_pipe( ialu_reg_reg_long );
13603 %}
13604
13605 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13606 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13607 match( Set flags (CmpL src1 src2 ));
13608 ins_cost(200+300);
13609 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13610 "JNE,s skip\n\t"
13611 "CMP $src1.hi,$src2.hi\n\t"
13612 "skip:\t" %}
13613 ins_encode( long_cmp_flags1( src1, src2 ) );
13614 ins_pipe( ialu_cr_reg_reg );
13615 %}
13616
13617 // Long compare reg == zero/reg OR reg != zero/reg
13618 // Just a wrapper for a normal branch, plus the predicate test.
13619 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13620 match(If cmp flags);
13621 effect(USE labl);
13622 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13623 expand %{
13624 jmpCon(cmp,flags,labl); // JEQ or JNE...
13625 %}
13626 %}
13627
13628 // Compare 2 longs and CMOVE longs.
13629 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13630 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13631 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13632 ins_cost(400);
13633 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13634 "CMOV$cmp $dst.hi,$src.hi" %}
13635 opcode(0x0F,0x40);
13636 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13637 ins_pipe( pipe_cmov_reg_long );
13638 %}
13639
13640 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13641 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13642 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13643 ins_cost(500);
13644 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13645 "CMOV$cmp $dst.hi,$src.hi" %}
13646 opcode(0x0F,0x40);
13647 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13648 ins_pipe( pipe_cmov_reg_long );
13649 %}
13650
13651 // Compare 2 longs and CMOVE ints.
13652 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13653 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13654 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13655 ins_cost(200);
13656 format %{ "CMOV$cmp $dst,$src" %}
13657 opcode(0x0F,0x40);
13658 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13659 ins_pipe( pipe_cmov_reg );
13660 %}
13661
13662 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13663 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13664 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13665 ins_cost(250);
13666 format %{ "CMOV$cmp $dst,$src" %}
13667 opcode(0x0F,0x40);
13668 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13669 ins_pipe( pipe_cmov_mem );
13670 %}
13671
13672 // Compare 2 longs and CMOVE ints.
13673 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13674 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13675 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13676 ins_cost(200);
13677 format %{ "CMOV$cmp $dst,$src" %}
13678 opcode(0x0F,0x40);
13679 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13680 ins_pipe( pipe_cmov_reg );
13681 %}
13682
13683 // Compare 2 longs and CMOVE doubles
13684 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13685 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13686 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13687 ins_cost(200);
13688 expand %{
13689 fcmovD_regS(cmp,flags,dst,src);
13690 %}
13691 %}
13692
13693 // Compare 2 longs and CMOVE doubles
13694 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13695 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13696 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13697 ins_cost(200);
13698 expand %{
13699 fcmovXD_regS(cmp,flags,dst,src);
13700 %}
13701 %}
13702
13703 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13704 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13705 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13706 ins_cost(200);
13707 expand %{
13708 fcmovF_regS(cmp,flags,dst,src);
13709 %}
13710 %}
13711
13712 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13713 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13714 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13715 ins_cost(200);
13716 expand %{
13717 fcmovX_regS(cmp,flags,dst,src);
13718 %}
13719 %}
13720
13721 //======
13722 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13723 // Same as cmpL_reg_flags_LEGT except must negate src
13724 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13725 match( Set flags (CmpL src zero ));
13726 effect( TEMP tmp );
13727 ins_cost(300);
13728 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13729 "CMP $tmp,$src.lo\n\t"
13730 "SBB $tmp,$src.hi\n\t" %}
13731 ins_encode( long_cmp_flags3(src, tmp) );
13732 ins_pipe( ialu_reg_reg_long );
13733 %}
13734
13735 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13736 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13737 // requires a commuted test to get the same result.
13738 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13739 match( Set flags (CmpL src1 src2 ));
13740 effect( TEMP tmp );
13741 ins_cost(300);
13742 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13743 "MOV $tmp,$src2.hi\n\t"
13744 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13745 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13746 ins_pipe( ialu_cr_reg_reg );
13747 %}
13748
13749 // Long compares reg < zero/req OR reg >= zero/req.
13750 // Just a wrapper for a normal branch, plus the predicate test
13751 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13752 match(If cmp flags);
13753 effect(USE labl);
13754 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13755 ins_cost(300);
13756 expand %{
13757 jmpCon(cmp,flags,labl); // JGT or JLE...
13758 %}
13759 %}
13760
13761 // Compare 2 longs and CMOVE longs.
13762 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13763 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13764 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13765 ins_cost(400);
13766 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13767 "CMOV$cmp $dst.hi,$src.hi" %}
13768 opcode(0x0F,0x40);
13769 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13770 ins_pipe( pipe_cmov_reg_long );
13771 %}
13772
13773 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13774 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13775 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13776 ins_cost(500);
13777 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13778 "CMOV$cmp $dst.hi,$src.hi+4" %}
13779 opcode(0x0F,0x40);
13780 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13781 ins_pipe( pipe_cmov_reg_long );
13782 %}
13783
13784 // Compare 2 longs and CMOVE ints.
13785 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13786 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13787 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13788 ins_cost(200);
13789 format %{ "CMOV$cmp $dst,$src" %}
13790 opcode(0x0F,0x40);
13791 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13792 ins_pipe( pipe_cmov_reg );
13793 %}
13794
13795 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13796 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13797 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13798 ins_cost(250);
13799 format %{ "CMOV$cmp $dst,$src" %}
13800 opcode(0x0F,0x40);
13801 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13802 ins_pipe( pipe_cmov_mem );
13803 %}
13804
13805 // Compare 2 longs and CMOVE ptrs.
13806 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13807 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13808 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13809 ins_cost(200);
13810 format %{ "CMOV$cmp $dst,$src" %}
13811 opcode(0x0F,0x40);
13812 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13813 ins_pipe( pipe_cmov_reg );
13814 %}
13815
13816 // Compare 2 longs and CMOVE doubles
13817 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13818 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13819 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13820 ins_cost(200);
13821 expand %{
13822 fcmovD_regS(cmp,flags,dst,src);
13823 %}
13824 %}
13825
13826 // Compare 2 longs and CMOVE doubles
13827 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13828 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13829 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13830 ins_cost(200);
13831 expand %{
13832 fcmovXD_regS(cmp,flags,dst,src);
13833 %}
13834 %}
13835
13836 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13837 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13838 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13839 ins_cost(200);
13840 expand %{
13841 fcmovF_regS(cmp,flags,dst,src);
13842 %}
13843 %}
13844
13845
13846 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13847 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13848 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13849 ins_cost(200);
13850 expand %{
13851 fcmovX_regS(cmp,flags,dst,src);
13852 %}
13853 %}
13854
13855
13856 // ============================================================================
13857 // Procedure Call/Return Instructions
13858 // Call Java Static Instruction
13859 // Note: If this code changes, the corresponding ret_addr_offset() and
13860 // compute_padding() functions will have to be adjusted.
13861 instruct CallStaticJavaDirect(method meth) %{
13862 match(CallStaticJava);
13863 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13864 effect(USE meth);
13865
13866 ins_cost(300);
13867 format %{ "CALL,static " %}
13868 opcode(0xE8); /* E8 cd */
13869 ins_encode( pre_call_FPU,
13870 Java_Static_Call( meth ),
13871 call_epilog,
13872 post_call_FPU );
13873 ins_pipe( pipe_slow );
13874 ins_alignment(4);
13875 %}
13876
13877 // Call Java Static Instruction (method handle version)
13878 // Note: If this code changes, the corresponding ret_addr_offset() and
13879 // compute_padding() functions will have to be adjusted.
13880 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13881 match(CallStaticJava);
13882 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13883 effect(USE meth);
13884 // EBP is saved by all callees (for interpreter stack correction).
13885 // We use it here for a similar purpose, in {preserve,restore}_SP.
13886
13887 ins_cost(300);
13888 format %{ "CALL,static/MethodHandle " %}
13889 opcode(0xE8); /* E8 cd */
13890 ins_encode( pre_call_FPU,
13891 preserve_SP,
13892 Java_Static_Call( meth ),
13893 restore_SP,
13894 call_epilog,
13895 post_call_FPU );
13896 ins_pipe( pipe_slow );
13897 ins_alignment(4);
13898 %}
13899
13900 // Call Java Dynamic Instruction
13901 // Note: If this code changes, the corresponding ret_addr_offset() and
13902 // compute_padding() functions will have to be adjusted.
13903 instruct CallDynamicJavaDirect(method meth) %{
13904 match(CallDynamicJava);
13905 effect(USE meth);
13906
13907 ins_cost(300);
13908 format %{ "MOV EAX,(oop)-1\n\t"
13909 "CALL,dynamic" %}
13910 opcode(0xE8); /* E8 cd */
13911 ins_encode( pre_call_FPU,
13912 Java_Dynamic_Call( meth ),
13913 call_epilog,
13914 post_call_FPU );
13915 ins_pipe( pipe_slow );
13916 ins_alignment(4);
13917 %}
13918
13919 // Call Runtime Instruction
13920 instruct CallRuntimeDirect(method meth) %{
13921 match(CallRuntime );
13922 effect(USE meth);
13923
13924 ins_cost(300);
13925 format %{ "CALL,runtime " %}
13926 opcode(0xE8); /* E8 cd */
13927 // Use FFREEs to clear entries in float stack
13928 ins_encode( pre_call_FPU,
13929 FFree_Float_Stack_All,
13930 Java_To_Runtime( meth ),
13931 post_call_FPU );
13932 ins_pipe( pipe_slow );
13933 %}
13934
13935 // Call runtime without safepoint
13936 instruct CallLeafDirect(method meth) %{
13937 match(CallLeaf);
13938 effect(USE meth);
13939
13940 ins_cost(300);
13941 format %{ "CALL_LEAF,runtime " %}
13942 opcode(0xE8); /* E8 cd */
13943 ins_encode( pre_call_FPU,
13944 FFree_Float_Stack_All,
13945 Java_To_Runtime( meth ),
13946 Verify_FPU_For_Leaf, post_call_FPU );
13947 ins_pipe( pipe_slow );
13948 %}
13949
13950 instruct CallLeafNoFPDirect(method meth) %{
13951 match(CallLeafNoFP);
13952 effect(USE meth);
13953
13954 ins_cost(300);
13955 format %{ "CALL_LEAF_NOFP,runtime " %}
13956 opcode(0xE8); /* E8 cd */
13957 ins_encode(Java_To_Runtime(meth));
13958 ins_pipe( pipe_slow );
13959 %}
13960
13961
13962 // Return Instruction
13963 // Remove the return address & jump to it.
13964 instruct Ret() %{
13965 match(Return);
13966 format %{ "RET" %}
13967 opcode(0xC3);
13968 ins_encode(OpcP);
13969 ins_pipe( pipe_jmp );
13970 %}
13971
13972 // Tail Call; Jump from runtime stub to Java code.
13973 // Also known as an 'interprocedural jump'.
13974 // Target of jump will eventually return to caller.
13975 // TailJump below removes the return address.
13976 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13977 match(TailCall jump_target method_oop );
13978 ins_cost(300);
13979 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13980 opcode(0xFF, 0x4); /* Opcode FF /4 */
13981 ins_encode( OpcP, RegOpc(jump_target) );
13982 ins_pipe( pipe_jmp );
13983 %}
13984
13985
13986 // Tail Jump; remove the return address; jump to target.
13987 // TailCall above leaves the return address around.
13988 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13989 match( TailJump jump_target ex_oop );
13990 ins_cost(300);
13991 format %{ "POP EDX\t# pop return address into dummy\n\t"
13992 "JMP $jump_target " %}
13993 opcode(0xFF, 0x4); /* Opcode FF /4 */
13994 ins_encode( enc_pop_rdx,
13995 OpcP, RegOpc(jump_target) );
13996 ins_pipe( pipe_jmp );
13997 %}
13998
13999 // Create exception oop: created by stack-crawling runtime code.
14000 // Created exception is now available to this handler, and is setup
14001 // just prior to jumping to this handler. No code emitted.
14002 instruct CreateException( eAXRegP ex_oop )
14003 %{
14004 match(Set ex_oop (CreateEx));
14005
14006 size(0);
14007 // use the following format syntax
14008 format %{ "# exception oop is in EAX; no code emitted" %}
14009 ins_encode();
14010 ins_pipe( empty );
14011 %}
14012
14013
14014 // Rethrow exception:
14015 // The exception oop will come in the first argument position.
14016 // Then JUMP (not call) to the rethrow stub code.
14017 instruct RethrowException()
14018 %{
14019 match(Rethrow);
14020
14021 // use the following format syntax
14022 format %{ "JMP rethrow_stub" %}
14023 ins_encode(enc_rethrow);
14024 ins_pipe( pipe_jmp );
14025 %}
14026
14027 // inlined locking and unlocking
14028
14029
14030 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
14031 match( Set cr (FastLock object box) );
14032 effect( TEMP tmp, TEMP scr );
14033 ins_cost(300);
14034 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
14035 ins_encode( Fast_Lock(object,box,tmp,scr) );
14036 ins_pipe( pipe_slow );
14037 %}
14038
14039 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
14040 match( Set cr (FastUnlock object box) );
14041 effect( TEMP tmp );
14042 ins_cost(300);
14043 format %{ "FASTUNLOCK $object, $box, $tmp" %}
14044 ins_encode( Fast_Unlock(object,box,tmp) );
14045 ins_pipe( pipe_slow );
14046 %}
14047
14048
14049
14050 // ============================================================================
14051 // Safepoint Instruction
14052 instruct safePoint_poll(eFlagsReg cr) %{
14053 match(SafePoint);
14054 effect(KILL cr);
14055
14056 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
14057 // On SPARC that might be acceptable as we can generate the address with
14058 // just a sethi, saving an or. By polling at offset 0 we can end up
14059 // putting additional pressure on the index-0 in the D$. Because of
14060 // alignment (just like the situation at hand) the lower indices tend
14061 // to see more traffic. It'd be better to change the polling address
14062 // to offset 0 of the last $line in the polling page.
14063
14064 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
14065 ins_cost(125);
14066 size(6) ;
14067 ins_encode( Safepoint_Poll() );
14068 ins_pipe( ialu_reg_mem );
14069 %}
14070
14071 //----------PEEPHOLE RULES-----------------------------------------------------
14072 // These must follow all instruction definitions as they use the names
14073 // defined in the instructions definitions.
14074 //
14075 // peepmatch ( root_instr_name [preceding_instruction]* );
14076 //
14077 // peepconstraint %{
14078 // (instruction_number.operand_name relational_op instruction_number.operand_name
14079 // [, ...] );
14080 // // instruction numbers are zero-based using left to right order in peepmatch
14081 //
14082 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
14083 // // provide an instruction_number.operand_name for each operand that appears
14084 // // in the replacement instruction's match rule
14085 //
14086 // ---------VM FLAGS---------------------------------------------------------
14087 //
14088 // All peephole optimizations can be turned off using -XX:-OptoPeephole
14089 //
14090 // Each peephole rule is given an identifying number starting with zero and
14091 // increasing by one in the order seen by the parser. An individual peephole
14092 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
14093 // on the command-line.
14094 //
14095 // ---------CURRENT LIMITATIONS----------------------------------------------
14096 //
14097 // Only match adjacent instructions in same basic block
14098 // Only equality constraints
14099 // Only constraints between operands, not (0.dest_reg == EAX_enc)
14100 // Only one replacement instruction
14101 //
14102 // ---------EXAMPLE----------------------------------------------------------
14103 //
14104 // // pertinent parts of existing instructions in architecture description
14105 // instruct movI(eRegI dst, eRegI src) %{
14106 // match(Set dst (CopyI src));
14107 // %}
14108 //
14109 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
14110 // match(Set dst (AddI dst src));
14111 // effect(KILL cr);
14112 // %}
14113 //
14114 // // Change (inc mov) to lea
14115 // peephole %{
14116 // // increment preceeded by register-register move
14117 // peepmatch ( incI_eReg movI );
14118 // // require that the destination register of the increment
14119 // // match the destination register of the move
14120 // peepconstraint ( 0.dst == 1.dst );
14121 // // construct a replacement instruction that sets
14122 // // the destination to ( move's source register + one )
14123 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14124 // %}
14125 //
14126 // Implementation no longer uses movX instructions since
14127 // machine-independent system no longer uses CopyX nodes.
14128 //
14129 // peephole %{
14130 // peepmatch ( incI_eReg movI );
14131 // peepconstraint ( 0.dst == 1.dst );
14132 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14133 // %}
14134 //
14135 // peephole %{
14136 // peepmatch ( decI_eReg movI );
14137 // peepconstraint ( 0.dst == 1.dst );
14138 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14139 // %}
14140 //
14141 // peephole %{
14142 // peepmatch ( addI_eReg_imm movI );
14143 // peepconstraint ( 0.dst == 1.dst );
14144 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
14145 // %}
14146 //
14147 // peephole %{
14148 // peepmatch ( addP_eReg_imm movP );
14149 // peepconstraint ( 0.dst == 1.dst );
14150 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
14151 // %}
14152
14153 // // Change load of spilled value to only a spill
14154 // instruct storeI(memory mem, eRegI src) %{
14155 // match(Set mem (StoreI mem src));
14156 // %}
14157 //
14158 // instruct loadI(eRegI dst, memory mem) %{
14159 // match(Set dst (LoadI mem));
14160 // %}
14161 //
14162 peephole %{
14163 peepmatch ( loadI storeI );
14164 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
14165 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
14166 %}
14167
14168 //----------SMARTSPILL RULES---------------------------------------------------
14169 // These must follow all instruction definitions as they use the names
14170 // defined in the instructions definitions.