2056 reg == XMM4_num || reg == XMM4_H_num ||
2057 reg == XMM5_num || reg == XMM5_H_num ||
2058 reg == XMM6_num || reg == XMM6_H_num ||
2059 reg == XMM7_num || reg == XMM7_H_num;
2060 }
2061
2062 bool Matcher::is_spillable_arg(int reg)
2063 {
2064 return can_be_java_arg(reg);
2065 }
2066
2067 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2068 // In 64 bit mode a code which use multiply when
2069 // devisor is constant is faster than hardware
2070 // DIV instruction (it uses MulHiL).
2071 return false;
2072 }
2073
2074 // Register for DIVI projection of divmodI
2075 RegMask Matcher::divI_proj_mask() {
2076 return INT_RAX_REG_mask;
2077 }
2078
2079 // Register for MODI projection of divmodI
2080 RegMask Matcher::modI_proj_mask() {
2081 return INT_RDX_REG_mask;
2082 }
2083
2084 // Register for DIVL projection of divmodL
2085 RegMask Matcher::divL_proj_mask() {
2086 return LONG_RAX_REG_mask;
2087 }
2088
2089 // Register for MODL projection of divmodL
2090 RegMask Matcher::modL_proj_mask() {
2091 return LONG_RDX_REG_mask;
2092 }
2093
2094 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2095 return PTR_RBP_REG_mask;
2096 }
2097
2098 static Address build_address(int b, int i, int s, int d) {
2099 Register index = as_Register(i);
2100 Address::ScaleFactor scale = (Address::ScaleFactor)s;
2101 if (index == rsp) {
2102 index = noreg;
2103 scale = Address::no_scale;
2104 }
2105 Address addr(as_Register(b), index, scale, d);
2106 return addr;
2107 }
2108
2109 %}
2110
2111 //----------ENCODING BLOCK-----------------------------------------------------
2112 // This block specifies the encoding classes used by the compiler to
2113 // output byte streams. Encoding classes are parameterized macros
2114 // used by Machine Instruction Nodes in order to generate the bit
2115 // encoding of the instruction. Operands specify their base encoding
|
2056 reg == XMM4_num || reg == XMM4_H_num ||
2057 reg == XMM5_num || reg == XMM5_H_num ||
2058 reg == XMM6_num || reg == XMM6_H_num ||
2059 reg == XMM7_num || reg == XMM7_H_num;
2060 }
2061
2062 bool Matcher::is_spillable_arg(int reg)
2063 {
2064 return can_be_java_arg(reg);
2065 }
2066
2067 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2068 // In 64 bit mode a code which use multiply when
2069 // devisor is constant is faster than hardware
2070 // DIV instruction (it uses MulHiL).
2071 return false;
2072 }
2073
2074 // Register for DIVI projection of divmodI
2075 RegMask Matcher::divI_proj_mask() {
2076 return INT_RAX_REG_mask();
2077 }
2078
2079 // Register for MODI projection of divmodI
2080 RegMask Matcher::modI_proj_mask() {
2081 return INT_RDX_REG_mask();
2082 }
2083
2084 // Register for DIVL projection of divmodL
2085 RegMask Matcher::divL_proj_mask() {
2086 return LONG_RAX_REG_mask();
2087 }
2088
2089 // Register for MODL projection of divmodL
2090 RegMask Matcher::modL_proj_mask() {
2091 return LONG_RDX_REG_mask();
2092 }
2093
2094 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2095 return PTR_RBP_REG_mask();
2096 }
2097
2098 static Address build_address(int b, int i, int s, int d) {
2099 Register index = as_Register(i);
2100 Address::ScaleFactor scale = (Address::ScaleFactor)s;
2101 if (index == rsp) {
2102 index = noreg;
2103 scale = Address::no_scale;
2104 }
2105 Address addr(as_Register(b), index, scale, d);
2106 return addr;
2107 }
2108
2109 %}
2110
2111 //----------ENCODING BLOCK-----------------------------------------------------
2112 // This block specifies the encoding classes used by the compiler to
2113 // output byte streams. Encoding classes are parameterized macros
2114 // used by Machine Instruction Nodes in order to generate the bit
2115 // encoding of the instruction. Operands specify their base encoding
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