1 /*
2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp"
30 #include "ci/ciInstance.hpp"
31 #include "runtime/sharedRuntime.hpp"
32
33 Register LIR_OprDesc::as_register() const {
34 return FrameMap::cpu_rnr2reg(cpu_regnr());
35 }
36
37 Register LIR_OprDesc::as_register_lo() const {
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
39 }
40
41 Register LIR_OprDesc::as_register_hi() const {
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
43 }
44
45 #if defined(X86)
46
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
48 return FrameMap::nr2xmmreg(xmm_regnr());
49 }
50
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
55
56 #endif // X86
57
58 #if defined(SPARC) || defined(PPC)
59
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
63
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
67
68 #endif
69
70 #ifdef ARM
71
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
75
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
79
80 #endif
81
82
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
84
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case objectTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
91 return LIR_OprFact::oopConst(NULL);
92 } else {
93 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
94 }
95 }
96 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
97 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
98 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
99 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
100 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
101 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
102 }
103 }
104
105
106 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
107 switch (type->tag()) {
108 case objectTag: return LIR_OprFact::oopConst(NULL);
109 case addressTag:return LIR_OprFact::addressConst(0);
110 case intTag: return LIR_OprFact::intConst(0);
111 case floatTag: return LIR_OprFact::floatConst(0.0);
112 case longTag: return LIR_OprFact::longConst(0);
113 case doubleTag: return LIR_OprFact::doubleConst(0.0);
114 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
115 }
116 return illegalOpr;
117 }
118
119
120
121 //---------------------------------------------------
122
123
124 LIR_Address::Scale LIR_Address::scale(BasicType type) {
125 int elem_size = type2aelembytes(type);
126 switch (elem_size) {
127 case 1: return LIR_Address::times_1;
128 case 2: return LIR_Address::times_2;
129 case 4: return LIR_Address::times_4;
130 case 8: return LIR_Address::times_8;
131 }
132 ShouldNotReachHere();
133 return LIR_Address::times_1;
134 }
135
136
137 #ifndef PRODUCT
138 void LIR_Address::verify() const {
139 #if defined(SPARC) || defined(PPC)
140 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
141 assert(disp() == 0 || index()->is_illegal(), "can't have both");
142 #endif
143 #ifdef ARM
144 assert(disp() == 0 || index()->is_illegal(), "can't have both");
145 // Note: offsets higher than 4096 must not be rejected here. They can
146 // be handled by the back-end or will be rejected if not.
147 #endif
148 #ifdef _LP64
149 assert(base()->is_cpu_register(), "wrong base operand");
150 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
151 assert(base()->type() == T_OBJECT || base()->type() == T_LONG,
152 "wrong type for addresses");
153 #else
154 assert(base()->is_single_cpu(), "wrong base operand");
155 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
156 assert(base()->type() == T_OBJECT || base()->type() == T_INT,
157 "wrong type for addresses");
158 #endif
159 }
160 #endif
161
162
163 //---------------------------------------------------
164
165 char LIR_OprDesc::type_char(BasicType t) {
166 switch (t) {
167 case T_ARRAY:
168 t = T_OBJECT;
169 case T_BOOLEAN:
170 case T_CHAR:
171 case T_FLOAT:
172 case T_DOUBLE:
173 case T_BYTE:
174 case T_SHORT:
175 case T_INT:
176 case T_LONG:
177 case T_OBJECT:
178 case T_ADDRESS:
179 case T_VOID:
180 return ::type2char(t);
181
182 case T_ILLEGAL:
183 return '?';
184
185 default:
186 ShouldNotReachHere();
187 return '?';
188 }
189 }
190
191 #ifndef PRODUCT
192 void LIR_OprDesc::validate_type() const {
193
194 #ifdef ASSERT
195 if (!is_pointer() && !is_illegal()) {
196 switch (as_BasicType(type_field())) {
197 case T_LONG:
198 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
199 size_field() == double_size, "must match");
200 break;
201 case T_FLOAT:
202 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
203 assert((kind_field() == fpu_register || kind_field() == stack_value
204 ARM_ONLY(|| kind_field() == cpu_register)
205 PPC_ONLY(|| kind_field() == cpu_register) ) &&
206 size_field() == single_size, "must match");
207 break;
208 case T_DOUBLE:
209 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
210 assert((kind_field() == fpu_register || kind_field() == stack_value
211 ARM_ONLY(|| kind_field() == cpu_register)
212 PPC_ONLY(|| kind_field() == cpu_register) ) &&
213 size_field() == double_size, "must match");
214 break;
215 case T_BOOLEAN:
216 case T_CHAR:
217 case T_BYTE:
218 case T_SHORT:
219 case T_INT:
220 case T_ADDRESS:
221 case T_OBJECT:
222 case T_ARRAY:
223 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
224 size_field() == single_size, "must match");
225 break;
226
227 case T_ILLEGAL:
228 // XXX TKR also means unknown right now
229 // assert(is_illegal(), "must match");
230 break;
231
232 default:
233 ShouldNotReachHere();
234 }
235 }
236 #endif
237
238 }
239 #endif // PRODUCT
240
241
242 bool LIR_OprDesc::is_oop() const {
243 if (is_pointer()) {
244 return pointer()->is_oop_pointer();
245 } else {
246 OprType t= type_field();
247 assert(t != unknown_type, "not set");
248 return t == object_type;
249 }
250 }
251
252
253
254 void LIR_Op2::verify() const {
255 #ifdef ASSERT
256 switch (code()) {
257 case lir_cmove:
258 break;
259
260 default:
261 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
262 "can't produce oops from arith");
263 }
264
265 if (TwoOperandLIRForm) {
266 switch (code()) {
267 case lir_add:
268 case lir_sub:
269 case lir_mul:
270 case lir_mul_strictfp:
271 case lir_div:
272 case lir_div_strictfp:
273 case lir_rem:
274 case lir_logic_and:
275 case lir_logic_or:
276 case lir_logic_xor:
277 case lir_shl:
278 case lir_shr:
279 assert(in_opr1() == result_opr(), "opr1 and result must match");
280 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
281 break;
282
283 // special handling for lir_ushr because of write barriers
284 case lir_ushr:
285 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
286 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
287 break;
288
289 }
290 }
291 #endif
292 }
293
294
295 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
296 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
297 , _cond(cond)
298 , _type(type)
299 , _label(block->label())
300 , _block(block)
301 , _ublock(NULL)
302 , _stub(NULL) {
303 }
304
305 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
306 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
307 , _cond(cond)
308 , _type(type)
309 , _label(stub->entry())
310 , _block(NULL)
311 , _ublock(NULL)
312 , _stub(stub) {
313 }
314
315 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
316 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
317 , _cond(cond)
318 , _type(type)
319 , _label(block->label())
320 , _block(block)
321 , _ublock(ublock)
322 , _stub(NULL)
323 {
324 }
325
326 void LIR_OpBranch::change_block(BlockBegin* b) {
327 assert(_block != NULL, "must have old block");
328 assert(_block->label() == label(), "must be equal");
329
330 _block = b;
331 _label = b->label();
332 }
333
334 void LIR_OpBranch::change_ublock(BlockBegin* b) {
335 assert(_ublock != NULL, "must have old block");
336 _ublock = b;
337 }
338
339 void LIR_OpBranch::negate_cond() {
340 switch (_cond) {
341 case lir_cond_equal: _cond = lir_cond_notEqual; break;
342 case lir_cond_notEqual: _cond = lir_cond_equal; break;
343 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
344 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
345 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
346 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
347 default: ShouldNotReachHere();
348 }
349 }
350
351
352 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
353 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
354 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
355 CodeStub* stub)
356
357 : LIR_Op(code, result, NULL)
358 , _object(object)
359 , _array(LIR_OprFact::illegalOpr)
360 , _klass(klass)
361 , _tmp1(tmp1)
362 , _tmp2(tmp2)
363 , _tmp3(tmp3)
364 , _fast_check(fast_check)
365 , _stub(stub)
366 , _info_for_patch(info_for_patch)
367 , _info_for_exception(info_for_exception)
368 , _profiled_method(NULL)
369 , _profiled_bci(-1)
370 , _should_profile(false)
371 {
372 if (code == lir_checkcast) {
373 assert(info_for_exception != NULL, "checkcast throws exceptions");
374 } else if (code == lir_instanceof) {
375 assert(info_for_exception == NULL, "instanceof throws no exceptions");
376 } else {
377 ShouldNotReachHere();
378 }
379 }
380
381
382
383 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
384 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
385 , _object(object)
386 , _array(array)
387 , _klass(NULL)
388 , _tmp1(tmp1)
389 , _tmp2(tmp2)
390 , _tmp3(tmp3)
391 , _fast_check(false)
392 , _stub(NULL)
393 , _info_for_patch(NULL)
394 , _info_for_exception(info_for_exception)
395 , _profiled_method(NULL)
396 , _profiled_bci(-1)
397 , _should_profile(false)
398 {
399 if (code == lir_store_check) {
400 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
401 assert(info_for_exception != NULL, "store_check throws exceptions");
402 } else {
403 ShouldNotReachHere();
404 }
405 }
406
407
408 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
409 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
410 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
411 , _tmp(tmp)
412 , _src(src)
413 , _src_pos(src_pos)
414 , _dst(dst)
415 , _dst_pos(dst_pos)
416 , _flags(flags)
417 , _expected_type(expected_type)
418 , _length(length) {
419 _stub = new ArrayCopyStub(this);
420 }
421
422
423 //-------------------verify--------------------------
424
425 void LIR_Op1::verify() const {
426 switch(code()) {
427 case lir_move:
428 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
429 break;
430 case lir_null_check:
431 assert(in_opr()->is_register(), "must be");
432 break;
433 case lir_return:
434 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
435 break;
436 }
437 }
438
439 void LIR_OpRTCall::verify() const {
440 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
441 }
442
443 //-------------------visits--------------------------
444
445 // complete rework of LIR instruction visitor.
446 // The virtual calls for each instruction type is replaced by a big
447 // switch that adds the operands for each instruction
448
449 void LIR_OpVisitState::visit(LIR_Op* op) {
450 // copy information from the LIR_Op
451 reset();
452 set_op(op);
453
454 switch (op->code()) {
455
456 // LIR_Op0
457 case lir_word_align: // result and info always invalid
458 case lir_backwardbranch_target: // result and info always invalid
459 case lir_build_frame: // result and info always invalid
460 case lir_fpop_raw: // result and info always invalid
461 case lir_24bit_FPU: // result and info always invalid
462 case lir_reset_FPU: // result and info always invalid
463 case lir_breakpoint: // result and info always invalid
464 case lir_membar: // result and info always invalid
465 case lir_membar_acquire: // result and info always invalid
466 case lir_membar_release: // result and info always invalid
467 case lir_membar_loadload: // result and info always invalid
468 case lir_membar_storestore: // result and info always invalid
469 case lir_membar_loadstore: // result and info always invalid
470 case lir_membar_storeload: // result and info always invalid
471 {
472 assert(op->as_Op0() != NULL, "must be");
473 assert(op->_info == NULL, "info not used by this instruction");
474 assert(op->_result->is_illegal(), "not used");
475 break;
476 }
477
478 case lir_nop: // may have info, result always invalid
479 case lir_std_entry: // may have result, info always invalid
480 case lir_osr_entry: // may have result, info always invalid
481 case lir_get_thread: // may have result, info always invalid
482 {
483 assert(op->as_Op0() != NULL, "must be");
484 if (op->_info != NULL) do_info(op->_info);
485 if (op->_result->is_valid()) do_output(op->_result);
486 break;
487 }
488
489
490 // LIR_OpLabel
491 case lir_label: // result and info always invalid
492 {
493 assert(op->as_OpLabel() != NULL, "must be");
494 assert(op->_info == NULL, "info not used by this instruction");
495 assert(op->_result->is_illegal(), "not used");
496 break;
497 }
498
499
500 // LIR_Op1
501 case lir_fxch: // input always valid, result and info always invalid
502 case lir_fld: // input always valid, result and info always invalid
503 case lir_ffree: // input always valid, result and info always invalid
504 case lir_push: // input always valid, result and info always invalid
505 case lir_pop: // input always valid, result and info always invalid
506 case lir_return: // input always valid, result and info always invalid
507 case lir_leal: // input and result always valid, info always invalid
508 case lir_neg: // input and result always valid, info always invalid
509 case lir_monaddr: // input and result always valid, info always invalid
510 case lir_null_check: // input and info always valid, result always invalid
511 case lir_move: // input and result always valid, may have info
512 case lir_pack64: // input and result always valid
513 case lir_unpack64: // input and result always valid
514 case lir_prefetchr: // input always valid, result and info always invalid
515 case lir_prefetchw: // input always valid, result and info always invalid
516 {
517 assert(op->as_Op1() != NULL, "must be");
518 LIR_Op1* op1 = (LIR_Op1*)op;
519
520 if (op1->_info) do_info(op1->_info);
521 if (op1->_opr->is_valid()) do_input(op1->_opr);
522 if (op1->_result->is_valid()) do_output(op1->_result);
523
524 break;
525 }
526
527 case lir_safepoint:
528 {
529 assert(op->as_Op1() != NULL, "must be");
530 LIR_Op1* op1 = (LIR_Op1*)op;
531
532 assert(op1->_info != NULL, ""); do_info(op1->_info);
533 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
534 assert(op1->_result->is_illegal(), "safepoint does not produce value");
535
536 break;
537 }
538
539 // LIR_OpConvert;
540 case lir_convert: // input and result always valid, info always invalid
541 {
542 assert(op->as_OpConvert() != NULL, "must be");
543 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
544
545 assert(opConvert->_info == NULL, "must be");
546 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
547 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
548 #ifdef PPC
549 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
550 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
551 #endif
552 do_stub(opConvert->_stub);
553
554 break;
555 }
556
557 // LIR_OpBranch;
558 case lir_branch: // may have info, input and result register always invalid
559 case lir_cond_float_branch: // may have info, input and result register always invalid
560 {
561 assert(op->as_OpBranch() != NULL, "must be");
562 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
563
564 if (opBranch->_info != NULL) do_info(opBranch->_info);
565 assert(opBranch->_result->is_illegal(), "not used");
566 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
567
568 break;
569 }
570
571
572 // LIR_OpAllocObj
573 case lir_alloc_object:
574 {
575 assert(op->as_OpAllocObj() != NULL, "must be");
576 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
577
578 if (opAllocObj->_info) do_info(opAllocObj->_info);
579 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
580 do_temp(opAllocObj->_opr);
581 }
582 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
583 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
584 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
585 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
586 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
587 do_stub(opAllocObj->_stub);
588 break;
589 }
590
591
592 // LIR_OpRoundFP;
593 case lir_roundfp: {
594 assert(op->as_OpRoundFP() != NULL, "must be");
595 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
596
597 assert(op->_info == NULL, "info not used by this instruction");
598 assert(opRoundFP->_tmp->is_illegal(), "not used");
599 do_input(opRoundFP->_opr);
600 do_output(opRoundFP->_result);
601
602 break;
603 }
604
605
606 // LIR_Op2
607 case lir_cmp:
608 case lir_cmp_l2i:
609 case lir_ucmp_fd2i:
610 case lir_cmp_fd2i:
611 case lir_add:
612 case lir_sub:
613 case lir_mul:
614 case lir_div:
615 case lir_rem:
616 case lir_sqrt:
617 case lir_abs:
618 case lir_logic_and:
619 case lir_logic_or:
620 case lir_logic_xor:
621 case lir_shl:
622 case lir_shr:
623 case lir_ushr:
624 {
625 assert(op->as_Op2() != NULL, "must be");
626 LIR_Op2* op2 = (LIR_Op2*)op;
627 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
628 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
629
630 if (op2->_info) do_info(op2->_info);
631 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
632 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
633 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
634 if (op2->_result->is_valid()) do_output(op2->_result);
635
636 break;
637 }
638
639 // special handling for cmove: right input operand must not be equal
640 // to the result operand, otherwise the backend fails
641 case lir_cmove:
642 {
643 assert(op->as_Op2() != NULL, "must be");
644 LIR_Op2* op2 = (LIR_Op2*)op;
645
646 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
647 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
648 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
649
650 do_input(op2->_opr1);
651 do_input(op2->_opr2);
652 do_temp(op2->_opr2);
653 do_output(op2->_result);
654
655 break;
656 }
657
658 // vspecial handling for strict operations: register input operands
659 // as temp to guarantee that they do not overlap with other
660 // registers
661 case lir_mul_strictfp:
662 case lir_div_strictfp:
663 {
664 assert(op->as_Op2() != NULL, "must be");
665 LIR_Op2* op2 = (LIR_Op2*)op;
666
667 assert(op2->_info == NULL, "not used");
668 assert(op2->_opr1->is_valid(), "used");
669 assert(op2->_opr2->is_valid(), "used");
670 assert(op2->_result->is_valid(), "used");
671 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
672 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
673
674 do_input(op2->_opr1); do_temp(op2->_opr1);
675 do_input(op2->_opr2); do_temp(op2->_opr2);
676 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
677 do_output(op2->_result);
678
679 break;
680 }
681
682 case lir_throw: {
683 assert(op->as_Op2() != NULL, "must be");
684 LIR_Op2* op2 = (LIR_Op2*)op;
685
686 if (op2->_info) do_info(op2->_info);
687 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
688 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
689 assert(op2->_result->is_illegal(), "no result");
690 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
691 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
692
693 break;
694 }
695
696 case lir_unwind: {
697 assert(op->as_Op1() != NULL, "must be");
698 LIR_Op1* op1 = (LIR_Op1*)op;
699
700 assert(op1->_info == NULL, "no info");
701 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
702 assert(op1->_result->is_illegal(), "no result");
703
704 break;
705 }
706
707
708 case lir_tan:
709 case lir_sin:
710 case lir_cos:
711 case lir_log:
712 case lir_log10:
713 case lir_exp: {
714 assert(op->as_Op2() != NULL, "must be");
715 LIR_Op2* op2 = (LIR_Op2*)op;
716
717 // On x86 tan/sin/cos need two temporary fpu stack slots and
718 // log/log10 need one so handle opr2 and tmp as temp inputs.
719 // Register input operand as temp to guarantee that it doesn't
720 // overlap with the input.
721 assert(op2->_info == NULL, "not used");
722 assert(op2->_tmp5->is_illegal(), "not used");
723 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
724 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
725 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
726 assert(op2->_opr1->is_valid(), "used");
727 do_input(op2->_opr1); do_temp(op2->_opr1);
728
729 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
730 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
731 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
732 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
733 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
734 if (op2->_result->is_valid()) do_output(op2->_result);
735
736 break;
737 }
738
739 case lir_pow: {
740 assert(op->as_Op2() != NULL, "must be");
741 LIR_Op2* op2 = (LIR_Op2*)op;
742
743 // On x86 pow needs two temporary fpu stack slots: tmp1 and
744 // tmp2. Register input operands as temps to guarantee that it
745 // doesn't overlap with the temporary slots.
746 assert(op2->_info == NULL, "not used");
747 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
748 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
749 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
750 assert(op2->_result->is_valid(), "used");
751
752 do_input(op2->_opr1); do_temp(op2->_opr1);
753 do_input(op2->_opr2); do_temp(op2->_opr2);
754 do_temp(op2->_tmp1);
755 do_temp(op2->_tmp2);
756 do_temp(op2->_tmp3);
757 do_temp(op2->_tmp4);
758 do_temp(op2->_tmp5);
759 do_output(op2->_result);
760
761 break;
762 }
763
764 // LIR_Op3
765 case lir_idiv:
766 case lir_irem: {
767 assert(op->as_Op3() != NULL, "must be");
768 LIR_Op3* op3= (LIR_Op3*)op;
769
770 if (op3->_info) do_info(op3->_info);
771 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
772
773 // second operand is input and temp, so ensure that second operand
774 // and third operand get not the same register
775 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
776 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
777 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
778
779 if (op3->_result->is_valid()) do_output(op3->_result);
780
781 break;
782 }
783
784
785 // LIR_OpJavaCall
786 case lir_static_call:
787 case lir_optvirtual_call:
788 case lir_icvirtual_call:
789 case lir_virtual_call:
790 case lir_dynamic_call: {
791 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
792 assert(opJavaCall != NULL, "must be");
793
794 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
795
796 // only visit register parameters
797 int n = opJavaCall->_arguments->length();
798 for (int i = 0; i < n; i++) {
799 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
800 do_input(*opJavaCall->_arguments->adr_at(i));
801 }
802 }
803
804 if (opJavaCall->_info) do_info(opJavaCall->_info);
805 if (opJavaCall->is_method_handle_invoke()) {
806 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
807 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
808 }
809 do_call();
810 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
811
812 break;
813 }
814
815
816 // LIR_OpRTCall
817 case lir_rtcall: {
818 assert(op->as_OpRTCall() != NULL, "must be");
819 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
820
821 // only visit register parameters
822 int n = opRTCall->_arguments->length();
823 for (int i = 0; i < n; i++) {
824 if (!opRTCall->_arguments->at(i)->is_pointer()) {
825 do_input(*opRTCall->_arguments->adr_at(i));
826 }
827 }
828 if (opRTCall->_info) do_info(opRTCall->_info);
829 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
830 do_call();
831 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
832
833 break;
834 }
835
836
837 // LIR_OpArrayCopy
838 case lir_arraycopy: {
839 assert(op->as_OpArrayCopy() != NULL, "must be");
840 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
841
842 assert(opArrayCopy->_result->is_illegal(), "unused");
843 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
844 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
845 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
846 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
847 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
848 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
849 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
850
851 // the implementation of arraycopy always has a call into the runtime
852 do_call();
853
854 break;
855 }
856
857
858 // LIR_OpLock
859 case lir_lock:
860 case lir_unlock: {
861 assert(op->as_OpLock() != NULL, "must be");
862 LIR_OpLock* opLock = (LIR_OpLock*)op;
863
864 if (opLock->_info) do_info(opLock->_info);
865
866 // TODO: check if these operands really have to be temp
867 // (or if input is sufficient). This may have influence on the oop map!
868 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
869 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
870 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
871
872 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
873 assert(opLock->_result->is_illegal(), "unused");
874
875 do_stub(opLock->_stub);
876
877 break;
878 }
879
880
881 // LIR_OpDelay
882 case lir_delay_slot: {
883 assert(op->as_OpDelay() != NULL, "must be");
884 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
885
886 visit(opDelay->delay_op());
887 break;
888 }
889
890 // LIR_OpTypeCheck
891 case lir_instanceof:
892 case lir_checkcast:
893 case lir_store_check: {
894 assert(op->as_OpTypeCheck() != NULL, "must be");
895 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
896
897 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
898 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
899 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
900 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
901 do_temp(opTypeCheck->_object);
902 }
903 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
904 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
905 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
906 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
907 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
908 do_stub(opTypeCheck->_stub);
909 break;
910 }
911
912 // LIR_OpCompareAndSwap
913 case lir_cas_long:
914 case lir_cas_obj:
915 case lir_cas_int: {
916 assert(op->as_OpCompareAndSwap() != NULL, "must be");
917 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
918
919 assert(opCompareAndSwap->_addr->is_valid(), "used");
920 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
921 assert(opCompareAndSwap->_new_value->is_valid(), "used");
922 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
923 do_input(opCompareAndSwap->_addr);
924 do_temp(opCompareAndSwap->_addr);
925 do_input(opCompareAndSwap->_cmp_value);
926 do_temp(opCompareAndSwap->_cmp_value);
927 do_input(opCompareAndSwap->_new_value);
928 do_temp(opCompareAndSwap->_new_value);
929 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
930 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
931 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
932
933 break;
934 }
935
936
937 // LIR_OpAllocArray;
938 case lir_alloc_array: {
939 assert(op->as_OpAllocArray() != NULL, "must be");
940 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
941
942 if (opAllocArray->_info) do_info(opAllocArray->_info);
943 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
944 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
945 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
946 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
947 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
948 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
949 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
950 do_stub(opAllocArray->_stub);
951 break;
952 }
953
954 // LIR_OpProfileCall:
955 case lir_profile_call: {
956 assert(op->as_OpProfileCall() != NULL, "must be");
957 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
958
959 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
960 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
961 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
962 break;
963 }
964 default:
965 ShouldNotReachHere();
966 }
967 }
968
969
970 void LIR_OpVisitState::do_stub(CodeStub* stub) {
971 if (stub != NULL) {
972 stub->visit(this);
973 }
974 }
975
976 XHandlers* LIR_OpVisitState::all_xhandler() {
977 XHandlers* result = NULL;
978
979 int i;
980 for (i = 0; i < info_count(); i++) {
981 if (info_at(i)->exception_handlers() != NULL) {
982 result = info_at(i)->exception_handlers();
983 break;
984 }
985 }
986
987 #ifdef ASSERT
988 for (i = 0; i < info_count(); i++) {
989 assert(info_at(i)->exception_handlers() == NULL ||
990 info_at(i)->exception_handlers() == result,
991 "only one xhandler list allowed per LIR-operation");
992 }
993 #endif
994
995 if (result != NULL) {
996 return result;
997 } else {
998 return new XHandlers();
999 }
1000
1001 return result;
1002 }
1003
1004
1005 #ifdef ASSERT
1006 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1007 visit(op);
1008
1009 return opr_count(inputMode) == 0 &&
1010 opr_count(outputMode) == 0 &&
1011 opr_count(tempMode) == 0 &&
1012 info_count() == 0 &&
1013 !has_call() &&
1014 !has_slow_case();
1015 }
1016 #endif
1017
1018 //---------------------------------------------------
1019
1020
1021 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1022 masm->emit_call(this);
1023 }
1024
1025 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1026 masm->emit_rtcall(this);
1027 }
1028
1029 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1030 masm->emit_opLabel(this);
1031 }
1032
1033 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1034 masm->emit_arraycopy(this);
1035 masm->emit_code_stub(stub());
1036 }
1037
1038 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1039 masm->emit_op0(this);
1040 }
1041
1042 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1043 masm->emit_op1(this);
1044 }
1045
1046 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1047 masm->emit_alloc_obj(this);
1048 masm->emit_code_stub(stub());
1049 }
1050
1051 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1052 masm->emit_opBranch(this);
1053 if (stub()) {
1054 masm->emit_code_stub(stub());
1055 }
1056 }
1057
1058 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1059 masm->emit_opConvert(this);
1060 if (stub() != NULL) {
1061 masm->emit_code_stub(stub());
1062 }
1063 }
1064
1065 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1066 masm->emit_op2(this);
1067 }
1068
1069 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1070 masm->emit_alloc_array(this);
1071 masm->emit_code_stub(stub());
1072 }
1073
1074 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1075 masm->emit_opTypeCheck(this);
1076 if (stub()) {
1077 masm->emit_code_stub(stub());
1078 }
1079 }
1080
1081 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1082 masm->emit_compare_and_swap(this);
1083 }
1084
1085 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1086 masm->emit_op3(this);
1087 }
1088
1089 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1090 masm->emit_lock(this);
1091 if (stub()) {
1092 masm->emit_code_stub(stub());
1093 }
1094 }
1095
1096
1097 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1098 masm->emit_delay(this);
1099 }
1100
1101 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1102 masm->emit_profile_call(this);
1103 }
1104
1105 // LIR_List
1106 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1107 : _operations(8)
1108 , _compilation(compilation)
1109 #ifndef PRODUCT
1110 , _block(block)
1111 #endif
1112 #ifdef ASSERT
1113 , _file(NULL)
1114 , _line(0)
1115 #endif
1116 { }
1117
1118
1119 #ifdef ASSERT
1120 void LIR_List::set_file_and_line(const char * file, int line) {
1121 const char * f = strrchr(file, '/');
1122 if (f == NULL) f = strrchr(file, '\\');
1123 if (f == NULL) {
1124 f = file;
1125 } else {
1126 f++;
1127 }
1128 _file = f;
1129 _line = line;
1130 }
1131 #endif
1132
1133
1134 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1135 assert(this == buffer->lir_list(), "wrong lir list");
1136 const int n = _operations.length();
1137
1138 if (buffer->number_of_ops() > 0) {
1139 // increase size of instructions list
1140 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1141 // insert ops from buffer into instructions list
1142 int op_index = buffer->number_of_ops() - 1;
1143 int ip_index = buffer->number_of_insertion_points() - 1;
1144 int from_index = n - 1;
1145 int to_index = _operations.length() - 1;
1146 for (; ip_index >= 0; ip_index --) {
1147 int index = buffer->index_at(ip_index);
1148 // make room after insertion point
1149 while (index < from_index) {
1150 _operations.at_put(to_index --, _operations.at(from_index --));
1151 }
1152 // insert ops from buffer
1153 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1154 _operations.at_put(to_index --, buffer->op_at(op_index --));
1155 }
1156 }
1157 }
1158
1159 buffer->finish();
1160 }
1161
1162
1163 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1164 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1165 }
1166
1167
1168 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1169 append(new LIR_Op1(
1170 lir_move,
1171 LIR_OprFact::address(addr),
1172 src,
1173 addr->type(),
1174 patch_code,
1175 info));
1176 }
1177
1178
1179 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1180 append(new LIR_Op1(
1181 lir_move,
1182 LIR_OprFact::address(address),
1183 dst,
1184 address->type(),
1185 patch_code,
1186 info, lir_move_volatile));
1187 }
1188
1189 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1190 append(new LIR_Op1(
1191 lir_move,
1192 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1193 dst,
1194 type,
1195 patch_code,
1196 info, lir_move_volatile));
1197 }
1198
1199
1200 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1201 append(new LIR_Op1(
1202 is_store ? lir_prefetchw : lir_prefetchr,
1203 LIR_OprFact::address(addr)));
1204 }
1205
1206
1207 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1208 append(new LIR_Op1(
1209 lir_move,
1210 LIR_OprFact::intConst(v),
1211 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1212 type,
1213 patch_code,
1214 info));
1215 }
1216
1217
1218 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1219 append(new LIR_Op1(
1220 lir_move,
1221 LIR_OprFact::oopConst(o),
1222 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1223 type,
1224 patch_code,
1225 info));
1226 }
1227
1228
1229 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1230 append(new LIR_Op1(
1231 lir_move,
1232 src,
1233 LIR_OprFact::address(addr),
1234 addr->type(),
1235 patch_code,
1236 info));
1237 }
1238
1239
1240 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1241 append(new LIR_Op1(
1242 lir_move,
1243 src,
1244 LIR_OprFact::address(addr),
1245 addr->type(),
1246 patch_code,
1247 info,
1248 lir_move_volatile));
1249 }
1250
1251 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1252 append(new LIR_Op1(
1253 lir_move,
1254 src,
1255 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1256 type,
1257 patch_code,
1258 info, lir_move_volatile));
1259 }
1260
1261
1262 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1263 append(new LIR_Op3(
1264 lir_idiv,
1265 left,
1266 right,
1267 tmp,
1268 res,
1269 info));
1270 }
1271
1272
1273 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1274 append(new LIR_Op3(
1275 lir_idiv,
1276 left,
1277 LIR_OprFact::intConst(right),
1278 tmp,
1279 res,
1280 info));
1281 }
1282
1283
1284 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1285 append(new LIR_Op3(
1286 lir_irem,
1287 left,
1288 right,
1289 tmp,
1290 res,
1291 info));
1292 }
1293
1294
1295 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1296 append(new LIR_Op3(
1297 lir_irem,
1298 left,
1299 LIR_OprFact::intConst(right),
1300 tmp,
1301 res,
1302 info));
1303 }
1304
1305
1306 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1307 append(new LIR_Op2(
1308 lir_cmp,
1309 condition,
1310 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1311 LIR_OprFact::intConst(c),
1312 info));
1313 }
1314
1315
1316 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1317 append(new LIR_Op2(
1318 lir_cmp,
1319 condition,
1320 reg,
1321 LIR_OprFact::address(addr),
1322 info));
1323 }
1324
1325 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1326 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1327 append(new LIR_OpAllocObj(
1328 klass,
1329 dst,
1330 t1,
1331 t2,
1332 t3,
1333 t4,
1334 header_size,
1335 object_size,
1336 init_check,
1337 stub));
1338 }
1339
1340 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1341 append(new LIR_OpAllocArray(
1342 klass,
1343 len,
1344 dst,
1345 t1,
1346 t2,
1347 t3,
1348 t4,
1349 type,
1350 stub));
1351 }
1352
1353 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1354 append(new LIR_Op2(
1355 lir_shl,
1356 value,
1357 count,
1358 dst,
1359 tmp));
1360 }
1361
1362 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1363 append(new LIR_Op2(
1364 lir_shr,
1365 value,
1366 count,
1367 dst,
1368 tmp));
1369 }
1370
1371
1372 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1373 append(new LIR_Op2(
1374 lir_ushr,
1375 value,
1376 count,
1377 dst,
1378 tmp));
1379 }
1380
1381 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1382 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1383 left,
1384 right,
1385 dst));
1386 }
1387
1388 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1389 append(new LIR_OpLock(
1390 lir_lock,
1391 hdr,
1392 obj,
1393 lock,
1394 scratch,
1395 stub,
1396 info));
1397 }
1398
1399 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1400 append(new LIR_OpLock(
1401 lir_unlock,
1402 hdr,
1403 obj,
1404 lock,
1405 scratch,
1406 stub,
1407 NULL));
1408 }
1409
1410
1411 void check_LIR() {
1412 // cannot do the proper checking as PRODUCT and other modes return different results
1413 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1414 }
1415
1416
1417
1418 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1419 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1420 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1421 ciMethod* profiled_method, int profiled_bci) {
1422 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1423 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1424 if (profiled_method != NULL) {
1425 c->set_profiled_method(profiled_method);
1426 c->set_profiled_bci(profiled_bci);
1427 c->set_should_profile(true);
1428 }
1429 append(c);
1430 }
1431
1432 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1433 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1434 if (profiled_method != NULL) {
1435 c->set_profiled_method(profiled_method);
1436 c->set_profiled_bci(profiled_bci);
1437 c->set_should_profile(true);
1438 }
1439 append(c);
1440 }
1441
1442
1443 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1444 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1445 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1446 if (profiled_method != NULL) {
1447 c->set_profiled_method(profiled_method);
1448 c->set_profiled_bci(profiled_bci);
1449 c->set_should_profile(true);
1450 }
1451 append(c);
1452 }
1453
1454
1455 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1456 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1457 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1458 }
1459
1460 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1461 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1462 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1463 }
1464
1465 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1466 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1467 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1468 }
1469
1470
1471 #ifdef PRODUCT
1472
1473 void print_LIR(BlockList* blocks) {
1474 }
1475
1476 #else
1477 // LIR_OprDesc
1478 void LIR_OprDesc::print() const {
1479 print(tty);
1480 }
1481
1482 void LIR_OprDesc::print(outputStream* out) const {
1483 if (is_illegal()) {
1484 return;
1485 }
1486
1487 out->print("[");
1488 if (is_pointer()) {
1489 pointer()->print_value_on(out);
1490 } else if (is_single_stack()) {
1491 out->print("stack:%d", single_stack_ix());
1492 } else if (is_double_stack()) {
1493 out->print("dbl_stack:%d",double_stack_ix());
1494 } else if (is_virtual()) {
1495 out->print("R%d", vreg_number());
1496 } else if (is_single_cpu()) {
1497 out->print(as_register()->name());
1498 } else if (is_double_cpu()) {
1499 out->print(as_register_hi()->name());
1500 out->print(as_register_lo()->name());
1501 #if defined(X86)
1502 } else if (is_single_xmm()) {
1503 out->print(as_xmm_float_reg()->name());
1504 } else if (is_double_xmm()) {
1505 out->print(as_xmm_double_reg()->name());
1506 } else if (is_single_fpu()) {
1507 out->print("fpu%d", fpu_regnr());
1508 } else if (is_double_fpu()) {
1509 out->print("fpu%d", fpu_regnrLo());
1510 #elif defined(ARM)
1511 } else if (is_single_fpu()) {
1512 out->print("s%d", fpu_regnr());
1513 } else if (is_double_fpu()) {
1514 out->print("d%d", fpu_regnrLo() >> 1);
1515 #else
1516 } else if (is_single_fpu()) {
1517 out->print(as_float_reg()->name());
1518 } else if (is_double_fpu()) {
1519 out->print(as_double_reg()->name());
1520 #endif
1521
1522 } else if (is_illegal()) {
1523 out->print("-");
1524 } else {
1525 out->print("Unknown Operand");
1526 }
1527 if (!is_illegal()) {
1528 out->print("|%c", type_char());
1529 }
1530 if (is_register() && is_last_use()) {
1531 out->print("(last_use)");
1532 }
1533 out->print("]");
1534 }
1535
1536
1537 // LIR_Address
1538 void LIR_Const::print_value_on(outputStream* out) const {
1539 switch (type()) {
1540 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1541 case T_INT: out->print("int:%d", as_jint()); break;
1542 case T_LONG: out->print("lng:%lld", as_jlong()); break;
1543 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1544 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1545 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break;
1546 default: out->print("%3d:0x%x",type(), as_jdouble()); break;
1547 }
1548 }
1549
1550 // LIR_Address
1551 void LIR_Address::print_value_on(outputStream* out) const {
1552 out->print("Base:"); _base->print(out);
1553 if (!_index->is_illegal()) {
1554 out->print(" Index:"); _index->print(out);
1555 switch (scale()) {
1556 case times_1: break;
1557 case times_2: out->print(" * 2"); break;
1558 case times_4: out->print(" * 4"); break;
1559 case times_8: out->print(" * 8"); break;
1560 }
1561 }
1562 out->print(" Disp: %d", _disp);
1563 }
1564
1565 // debug output of block header without InstructionPrinter
1566 // (because phi functions are not necessary for LIR)
1567 static void print_block(BlockBegin* x) {
1568 // print block id
1569 BlockEnd* end = x->end();
1570 tty->print("B%d ", x->block_id());
1571
1572 // print flags
1573 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1574 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1575 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1576 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1577 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1578 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1579 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1580
1581 // print block bci range
1582 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1583
1584 // print predecessors and successors
1585 if (x->number_of_preds() > 0) {
1586 tty->print("preds: ");
1587 for (int i = 0; i < x->number_of_preds(); i ++) {
1588 tty->print("B%d ", x->pred_at(i)->block_id());
1589 }
1590 }
1591
1592 if (x->number_of_sux() > 0) {
1593 tty->print("sux: ");
1594 for (int i = 0; i < x->number_of_sux(); i ++) {
1595 tty->print("B%d ", x->sux_at(i)->block_id());
1596 }
1597 }
1598
1599 // print exception handlers
1600 if (x->number_of_exception_handlers() > 0) {
1601 tty->print("xhandler: ");
1602 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1603 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1604 }
1605 }
1606
1607 tty->cr();
1608 }
1609
1610 void print_LIR(BlockList* blocks) {
1611 tty->print_cr("LIR:");
1612 int i;
1613 for (i = 0; i < blocks->length(); i++) {
1614 BlockBegin* bb = blocks->at(i);
1615 print_block(bb);
1616 tty->print("__id_Instruction___________________________________________"); tty->cr();
1617 bb->lir()->print_instructions();
1618 }
1619 }
1620
1621 void LIR_List::print_instructions() {
1622 for (int i = 0; i < _operations.length(); i++) {
1623 _operations.at(i)->print(); tty->cr();
1624 }
1625 tty->cr();
1626 }
1627
1628 // LIR_Ops printing routines
1629 // LIR_Op
1630 void LIR_Op::print_on(outputStream* out) const {
1631 if (id() != -1 || PrintCFGToFile) {
1632 out->print("%4d ", id());
1633 } else {
1634 out->print(" ");
1635 }
1636 out->print(name()); out->print(" ");
1637 print_instr(out);
1638 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1639 #ifdef ASSERT
1640 if (Verbose && _file != NULL) {
1641 out->print(" (%s:%d)", _file, _line);
1642 }
1643 #endif
1644 }
1645
1646 const char * LIR_Op::name() const {
1647 const char* s = NULL;
1648 switch(code()) {
1649 // LIR_Op0
1650 case lir_membar: s = "membar"; break;
1651 case lir_membar_acquire: s = "membar_acquire"; break;
1652 case lir_membar_release: s = "membar_release"; break;
1653 case lir_membar_loadload: s = "membar_loadload"; break;
1654 case lir_membar_storestore: s = "membar_storestore"; break;
1655 case lir_membar_loadstore: s = "membar_loadstore"; break;
1656 case lir_membar_storeload: s = "membar_storeload"; break;
1657 case lir_word_align: s = "word_align"; break;
1658 case lir_label: s = "label"; break;
1659 case lir_nop: s = "nop"; break;
1660 case lir_backwardbranch_target: s = "backbranch"; break;
1661 case lir_std_entry: s = "std_entry"; break;
1662 case lir_osr_entry: s = "osr_entry"; break;
1663 case lir_build_frame: s = "build_frm"; break;
1664 case lir_fpop_raw: s = "fpop_raw"; break;
1665 case lir_24bit_FPU: s = "24bit_FPU"; break;
1666 case lir_reset_FPU: s = "reset_FPU"; break;
1667 case lir_breakpoint: s = "breakpoint"; break;
1668 case lir_get_thread: s = "get_thread"; break;
1669 // LIR_Op1
1670 case lir_fxch: s = "fxch"; break;
1671 case lir_fld: s = "fld"; break;
1672 case lir_ffree: s = "ffree"; break;
1673 case lir_push: s = "push"; break;
1674 case lir_pop: s = "pop"; break;
1675 case lir_null_check: s = "null_check"; break;
1676 case lir_return: s = "return"; break;
1677 case lir_safepoint: s = "safepoint"; break;
1678 case lir_neg: s = "neg"; break;
1679 case lir_leal: s = "leal"; break;
1680 case lir_branch: s = "branch"; break;
1681 case lir_cond_float_branch: s = "flt_cond_br"; break;
1682 case lir_move: s = "move"; break;
1683 case lir_roundfp: s = "roundfp"; break;
1684 case lir_rtcall: s = "rtcall"; break;
1685 case lir_throw: s = "throw"; break;
1686 case lir_unwind: s = "unwind"; break;
1687 case lir_convert: s = "convert"; break;
1688 case lir_alloc_object: s = "alloc_obj"; break;
1689 case lir_monaddr: s = "mon_addr"; break;
1690 case lir_pack64: s = "pack64"; break;
1691 case lir_unpack64: s = "unpack64"; break;
1692 // LIR_Op2
1693 case lir_cmp: s = "cmp"; break;
1694 case lir_cmp_l2i: s = "cmp_l2i"; break;
1695 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1696 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1697 case lir_cmove: s = "cmove"; break;
1698 case lir_add: s = "add"; break;
1699 case lir_sub: s = "sub"; break;
1700 case lir_mul: s = "mul"; break;
1701 case lir_mul_strictfp: s = "mul_strictfp"; break;
1702 case lir_div: s = "div"; break;
1703 case lir_div_strictfp: s = "div_strictfp"; break;
1704 case lir_rem: s = "rem"; break;
1705 case lir_abs: s = "abs"; break;
1706 case lir_sqrt: s = "sqrt"; break;
1707 case lir_sin: s = "sin"; break;
1708 case lir_cos: s = "cos"; break;
1709 case lir_tan: s = "tan"; break;
1710 case lir_log: s = "log"; break;
1711 case lir_log10: s = "log10"; break;
1712 case lir_exp: s = "exp"; break;
1713 case lir_pow: s = "pow"; break;
1714 case lir_logic_and: s = "logic_and"; break;
1715 case lir_logic_or: s = "logic_or"; break;
1716 case lir_logic_xor: s = "logic_xor"; break;
1717 case lir_shl: s = "shift_left"; break;
1718 case lir_shr: s = "shift_right"; break;
1719 case lir_ushr: s = "ushift_right"; break;
1720 case lir_alloc_array: s = "alloc_array"; break;
1721 // LIR_Op3
1722 case lir_idiv: s = "idiv"; break;
1723 case lir_irem: s = "irem"; break;
1724 // LIR_OpJavaCall
1725 case lir_static_call: s = "static"; break;
1726 case lir_optvirtual_call: s = "optvirtual"; break;
1727 case lir_icvirtual_call: s = "icvirtual"; break;
1728 case lir_virtual_call: s = "virtual"; break;
1729 case lir_dynamic_call: s = "dynamic"; break;
1730 // LIR_OpArrayCopy
1731 case lir_arraycopy: s = "arraycopy"; break;
1732 // LIR_OpLock
1733 case lir_lock: s = "lock"; break;
1734 case lir_unlock: s = "unlock"; break;
1735 // LIR_OpDelay
1736 case lir_delay_slot: s = "delay"; break;
1737 // LIR_OpTypeCheck
1738 case lir_instanceof: s = "instanceof"; break;
1739 case lir_checkcast: s = "checkcast"; break;
1740 case lir_store_check: s = "store_check"; break;
1741 // LIR_OpCompareAndSwap
1742 case lir_cas_long: s = "cas_long"; break;
1743 case lir_cas_obj: s = "cas_obj"; break;
1744 case lir_cas_int: s = "cas_int"; break;
1745 // LIR_OpProfileCall
1746 case lir_profile_call: s = "profile_call"; break;
1747 case lir_none: ShouldNotReachHere();break;
1748 default: s = "illegal_op"; break;
1749 }
1750 return s;
1751 }
1752
1753 // LIR_OpJavaCall
1754 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1755 out->print("call: ");
1756 out->print("[addr: 0x%x]", address());
1757 if (receiver()->is_valid()) {
1758 out->print(" [recv: "); receiver()->print(out); out->print("]");
1759 }
1760 if (result_opr()->is_valid()) {
1761 out->print(" [result: "); result_opr()->print(out); out->print("]");
1762 }
1763 }
1764
1765 // LIR_OpLabel
1766 void LIR_OpLabel::print_instr(outputStream* out) const {
1767 out->print("[label:0x%x]", _label);
1768 }
1769
1770 // LIR_OpArrayCopy
1771 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1772 src()->print(out); out->print(" ");
1773 src_pos()->print(out); out->print(" ");
1774 dst()->print(out); out->print(" ");
1775 dst_pos()->print(out); out->print(" ");
1776 length()->print(out); out->print(" ");
1777 tmp()->print(out); out->print(" ");
1778 }
1779
1780 // LIR_OpCompareAndSwap
1781 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1782 addr()->print(out); out->print(" ");
1783 cmp_value()->print(out); out->print(" ");
1784 new_value()->print(out); out->print(" ");
1785 tmp1()->print(out); out->print(" ");
1786 tmp2()->print(out); out->print(" ");
1787
1788 }
1789
1790 // LIR_Op0
1791 void LIR_Op0::print_instr(outputStream* out) const {
1792 result_opr()->print(out);
1793 }
1794
1795 // LIR_Op1
1796 const char * LIR_Op1::name() const {
1797 if (code() == lir_move) {
1798 switch (move_kind()) {
1799 case lir_move_normal:
1800 return "move";
1801 case lir_move_unaligned:
1802 return "unaligned move";
1803 case lir_move_volatile:
1804 return "volatile_move";
1805 case lir_move_wide:
1806 return "wide_move";
1807 default:
1808 ShouldNotReachHere();
1809 return "illegal_op";
1810 }
1811 } else {
1812 return LIR_Op::name();
1813 }
1814 }
1815
1816
1817 void LIR_Op1::print_instr(outputStream* out) const {
1818 _opr->print(out); out->print(" ");
1819 result_opr()->print(out); out->print(" ");
1820 print_patch_code(out, patch_code());
1821 }
1822
1823
1824 // LIR_Op1
1825 void LIR_OpRTCall::print_instr(outputStream* out) const {
1826 intx a = (intx)addr();
1827 out->print(Runtime1::name_for_address(addr()));
1828 out->print(" ");
1829 tmp()->print(out);
1830 }
1831
1832 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1833 switch(code) {
1834 case lir_patch_none: break;
1835 case lir_patch_low: out->print("[patch_low]"); break;
1836 case lir_patch_high: out->print("[patch_high]"); break;
1837 case lir_patch_normal: out->print("[patch_normal]"); break;
1838 default: ShouldNotReachHere();
1839 }
1840 }
1841
1842 // LIR_OpBranch
1843 void LIR_OpBranch::print_instr(outputStream* out) const {
1844 print_condition(out, cond()); out->print(" ");
1845 if (block() != NULL) {
1846 out->print("[B%d] ", block()->block_id());
1847 } else if (stub() != NULL) {
1848 out->print("[");
1849 stub()->print_name(out);
1850 out->print(": 0x%x]", stub());
1851 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1852 } else {
1853 out->print("[label:0x%x] ", label());
1854 }
1855 if (ublock() != NULL) {
1856 out->print("unordered: [B%d] ", ublock()->block_id());
1857 }
1858 }
1859
1860 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1861 switch(cond) {
1862 case lir_cond_equal: out->print("[EQ]"); break;
1863 case lir_cond_notEqual: out->print("[NE]"); break;
1864 case lir_cond_less: out->print("[LT]"); break;
1865 case lir_cond_lessEqual: out->print("[LE]"); break;
1866 case lir_cond_greaterEqual: out->print("[GE]"); break;
1867 case lir_cond_greater: out->print("[GT]"); break;
1868 case lir_cond_belowEqual: out->print("[BE]"); break;
1869 case lir_cond_aboveEqual: out->print("[AE]"); break;
1870 case lir_cond_always: out->print("[AL]"); break;
1871 default: out->print("[%d]",cond); break;
1872 }
1873 }
1874
1875 // LIR_OpConvert
1876 void LIR_OpConvert::print_instr(outputStream* out) const {
1877 print_bytecode(out, bytecode());
1878 in_opr()->print(out); out->print(" ");
1879 result_opr()->print(out); out->print(" ");
1880 #ifdef PPC
1881 if(tmp1()->is_valid()) {
1882 tmp1()->print(out); out->print(" ");
1883 tmp2()->print(out); out->print(" ");
1884 }
1885 #endif
1886 }
1887
1888 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1889 switch(code) {
1890 case Bytecodes::_d2f: out->print("[d2f] "); break;
1891 case Bytecodes::_d2i: out->print("[d2i] "); break;
1892 case Bytecodes::_d2l: out->print("[d2l] "); break;
1893 case Bytecodes::_f2d: out->print("[f2d] "); break;
1894 case Bytecodes::_f2i: out->print("[f2i] "); break;
1895 case Bytecodes::_f2l: out->print("[f2l] "); break;
1896 case Bytecodes::_i2b: out->print("[i2b] "); break;
1897 case Bytecodes::_i2c: out->print("[i2c] "); break;
1898 case Bytecodes::_i2d: out->print("[i2d] "); break;
1899 case Bytecodes::_i2f: out->print("[i2f] "); break;
1900 case Bytecodes::_i2l: out->print("[i2l] "); break;
1901 case Bytecodes::_i2s: out->print("[i2s] "); break;
1902 case Bytecodes::_l2i: out->print("[l2i] "); break;
1903 case Bytecodes::_l2f: out->print("[l2f] "); break;
1904 case Bytecodes::_l2d: out->print("[l2d] "); break;
1905 default:
1906 out->print("[?%d]",code);
1907 break;
1908 }
1909 }
1910
1911 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1912 klass()->print(out); out->print(" ");
1913 obj()->print(out); out->print(" ");
1914 tmp1()->print(out); out->print(" ");
1915 tmp2()->print(out); out->print(" ");
1916 tmp3()->print(out); out->print(" ");
1917 tmp4()->print(out); out->print(" ");
1918 out->print("[hdr:%d]", header_size()); out->print(" ");
1919 out->print("[obj:%d]", object_size()); out->print(" ");
1920 out->print("[lbl:0x%x]", stub()->entry());
1921 }
1922
1923 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1924 _opr->print(out); out->print(" ");
1925 tmp()->print(out); out->print(" ");
1926 result_opr()->print(out); out->print(" ");
1927 }
1928
1929 // LIR_Op2
1930 void LIR_Op2::print_instr(outputStream* out) const {
1931 if (code() == lir_cmove) {
1932 print_condition(out, condition()); out->print(" ");
1933 }
1934 in_opr1()->print(out); out->print(" ");
1935 in_opr2()->print(out); out->print(" ");
1936 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
1937 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
1938 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
1939 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
1940 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
1941 result_opr()->print(out);
1942 }
1943
1944 void LIR_OpAllocArray::print_instr(outputStream* out) const {
1945 klass()->print(out); out->print(" ");
1946 len()->print(out); out->print(" ");
1947 obj()->print(out); out->print(" ");
1948 tmp1()->print(out); out->print(" ");
1949 tmp2()->print(out); out->print(" ");
1950 tmp3()->print(out); out->print(" ");
1951 tmp4()->print(out); out->print(" ");
1952 out->print("[type:0x%x]", type()); out->print(" ");
1953 out->print("[label:0x%x]", stub()->entry());
1954 }
1955
1956
1957 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
1958 object()->print(out); out->print(" ");
1959 if (code() == lir_store_check) {
1960 array()->print(out); out->print(" ");
1961 }
1962 if (code() != lir_store_check) {
1963 klass()->print_name_on(out); out->print(" ");
1964 if (fast_check()) out->print("fast_check ");
1965 }
1966 tmp1()->print(out); out->print(" ");
1967 tmp2()->print(out); out->print(" ");
1968 tmp3()->print(out); out->print(" ");
1969 result_opr()->print(out); out->print(" ");
1970 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
1971 }
1972
1973
1974 // LIR_Op3
1975 void LIR_Op3::print_instr(outputStream* out) const {
1976 in_opr1()->print(out); out->print(" ");
1977 in_opr2()->print(out); out->print(" ");
1978 in_opr3()->print(out); out->print(" ");
1979 result_opr()->print(out);
1980 }
1981
1982
1983 void LIR_OpLock::print_instr(outputStream* out) const {
1984 hdr_opr()->print(out); out->print(" ");
1985 obj_opr()->print(out); out->print(" ");
1986 lock_opr()->print(out); out->print(" ");
1987 if (_scratch->is_valid()) {
1988 _scratch->print(out); out->print(" ");
1989 }
1990 out->print("[lbl:0x%x]", stub()->entry());
1991 }
1992
1993
1994 void LIR_OpDelay::print_instr(outputStream* out) const {
1995 _op->print_on(out);
1996 }
1997
1998
1999 // LIR_OpProfileCall
2000 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2001 profiled_method()->name()->print_symbol_on(out);
2002 out->print(".");
2003 profiled_method()->holder()->name()->print_symbol_on(out);
2004 out->print(" @ %d ", profiled_bci());
2005 mdo()->print(out); out->print(" ");
2006 recv()->print(out); out->print(" ");
2007 tmp1()->print(out); out->print(" ");
2008 }
2009
2010 #endif // PRODUCT
2011
2012 // Implementation of LIR_InsertionBuffer
2013
2014 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2015 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2016
2017 int i = number_of_insertion_points() - 1;
2018 if (i < 0 || index_at(i) < index) {
2019 append_new(index, 1);
2020 } else {
2021 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2022 assert(count_at(i) > 0, "check");
2023 set_count_at(i, count_at(i) + 1);
2024 }
2025 _ops.push(op);
2026
2027 DEBUG_ONLY(verify());
2028 }
2029
2030 #ifdef ASSERT
2031 void LIR_InsertionBuffer::verify() {
2032 int sum = 0;
2033 int prev_idx = -1;
2034
2035 for (int i = 0; i < number_of_insertion_points(); i++) {
2036 assert(prev_idx < index_at(i), "index must be ordered ascending");
2037 sum += count_at(i);
2038 }
2039 assert(sum == number_of_ops(), "wrong total sum");
2040 }
2041 #endif