src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

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rev 4136 : 7153771: array bound check elimination for c1
Summary: when possible optimize out array bound checks, inserting predicates when needed.
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3345   assert_different_registers(rs, rd, rd->successor());
3346   __ srlx(rs, 32, rd);
3347   __ srl (rs,  0, rd->successor());
3348 }
3349 
3350 
3351 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3352   LIR_Address* addr = addr_opr->as_address_ptr();
3353   assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
3354 
3355   __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3356 }
3357 
3358 
3359 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3360   assert(result_reg->is_register(), "check");
3361   __ mov(G2_thread, result_reg->as_register());
3362 }
3363 
3364 









































3365 void LIR_Assembler::peephole(LIR_List* lir) {
3366   LIR_OpList* inst = lir->instructions_list();
3367   for (int i = 0; i < inst->length(); i++) {
3368     LIR_Op* op = inst->at(i);
3369     switch (op->code()) {
3370       case lir_cond_float_branch:
3371       case lir_branch: {
3372         LIR_OpBranch* branch = op->as_OpBranch();
3373         assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3374         LIR_Op* delay_op = NULL;
3375         // we'd like to be able to pull following instructions into
3376         // this slot but we don't know enough to do it safely yet so
3377         // only optimize block to block control flow.
3378         if (LIRFillDelaySlots && branch->block()) {
3379           LIR_Op* prev = inst->at(i - 1);
3380           if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3381             // swap previous instruction into delay slot
3382             inst->at_put(i - 1, op);
3383             inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3384 #ifndef PRODUCT




3345   assert_different_registers(rs, rd, rd->successor());
3346   __ srlx(rs, 32, rd);
3347   __ srl (rs,  0, rd->successor());
3348 }
3349 
3350 
3351 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3352   LIR_Address* addr = addr_opr->as_address_ptr();
3353   assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
3354 
3355   __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3356 }
3357 
3358 
3359 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3360   assert(result_reg->is_register(), "check");
3361   __ mov(G2_thread, result_reg->as_register());
3362 }
3363 
3364 
3365 #ifndef PRODUCT
3366 
3367 // emit run-time assertion
3368 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3369   assert(op->code() == lir_assert, "must be");
3370 
3371   if (op->in_opr1()->is_valid()) {
3372     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3373     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3374   } else {
3375     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3376     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3377   }
3378 
3379   Label ok;
3380   if (op->condition() != lir_cond_always) {
3381     Assembler::Condition acond;
3382     switch (op->condition()) {
3383       case lir_cond_equal:        acond = Assembler::equal;                break;
3384       case lir_cond_notEqual:     acond = Assembler::notEqual;             break;
3385       case lir_cond_less:         acond = Assembler::less;                 break;
3386       case lir_cond_lessEqual:    acond = Assembler::lessEqual;            break;
3387       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;         break;
3388       case lir_cond_greater:      acond = Assembler::greater;              break;
3389       case lir_cond_aboveEqual:   acond = Assembler::greaterEqualUnsigned; break;
3390       case lir_cond_belowEqual:   acond = Assembler::lessEqualUnsigned;    break;
3391       default:                         ShouldNotReachHere();
3392     };
3393     __ br(acond, false, Assembler::pt, ok);
3394     __ delayed()->nop();
3395   }
3396   if (op->halt()) {
3397     const char* str = __ code_string(op->msg());
3398     delete op->msg();
3399     __ stop(str);
3400   } else {
3401     breakpoint();
3402   }
3403   __ bind(ok);
3404 }
3405 #endif
3406 void LIR_Assembler::peephole(LIR_List* lir) {
3407   LIR_OpList* inst = lir->instructions_list();
3408   for (int i = 0; i < inst->length(); i++) {
3409     LIR_Op* op = inst->at(i);
3410     switch (op->code()) {
3411       case lir_cond_float_branch:
3412       case lir_branch: {
3413         LIR_OpBranch* branch = op->as_OpBranch();
3414         assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3415         LIR_Op* delay_op = NULL;
3416         // we'd like to be able to pull following instructions into
3417         // this slot but we don't know enough to do it safely yet so
3418         // only optimize block to block control flow.
3419         if (LIRFillDelaySlots && branch->block()) {
3420           LIR_Op* prev = inst->at(i - 1);
3421           if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3422             // swap previous instruction into delay slot
3423             inst->at_put(i - 1, op);
3424             inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3425 #ifndef PRODUCT