1 /*
   2  * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
  27 
  28 class BiasedLockingCounters;
  29 
  30 // Contains all the definitions needed for x86 assembly code generation.
  31 
  32 // Calling convention
  33 class Argument VALUE_OBJ_CLASS_SPEC {
  34  public:
  35   enum {
  36 #ifdef _LP64
  37 #ifdef _WIN64
  38     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  39     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  40 #else
  41     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  42     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  43 #endif // _WIN64
  44     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  45     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  46 #else
  47     n_register_parameters = 0   // 0 registers used to pass arguments
  48 #endif // _LP64
  49   };
  50 };
  51 
  52 
  53 #ifdef _LP64
  54 // Symbolically name the register arguments used by the c calling convention.
  55 // Windows is different from linux/solaris. So much for standards...
  56 
  57 #ifdef _WIN64
  58 
  59 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  60 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  61 REGISTER_DECLARATION(Register, c_rarg2, r8);
  62 REGISTER_DECLARATION(Register, c_rarg3, r9);
  63 
  64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  68 
  69 #else
  70 
  71 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  72 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  73 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  74 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  75 REGISTER_DECLARATION(Register, c_rarg4, r8);
  76 REGISTER_DECLARATION(Register, c_rarg5, r9);
  77 
  78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  86 
  87 #endif // _WIN64
  88 
  89 // Symbolically name the register arguments used by the Java calling convention.
  90 // We have control over the convention for java so we can do what we please.
  91 // What pleases us is to offset the java calling convention so that when
  92 // we call a suitable jni method the arguments are lined up and we don't
  93 // have to do little shuffling. A suitable jni method is non-static and a
  94 // small number of arguments (two fewer args on windows)
  95 //
  96 //        |-------------------------------------------------------|
  97 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
  98 //        |-------------------------------------------------------|
  99 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 100 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 101 //        |-------------------------------------------------------|
 102 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 103 //        |-------------------------------------------------------|
 104 
 105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 108 // Windows runs out of register args here
 109 #ifdef _WIN64
 110 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 111 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 112 #else
 113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 115 #endif /* _WIN64 */
 116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 117 
 118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 126 
 127 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 128 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 129 
 130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 132 
 133 #else
 134 // rscratch1 will apear in 32bit code that is dead but of course must compile
 135 // Using noreg ensures if the dead code is incorrectly live and executed it
 136 // will cause an assertion failure
 137 #define rscratch1 noreg
 138 #define rscratch2 noreg
 139 
 140 #endif // _LP64
 141 
 142 // JSR 292 fixed register usages:
 143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
 144 
 145 // Address is an abstraction used to represent a memory location
 146 // using any of the amd64 addressing modes with one object.
 147 //
 148 // Note: A register location is represented via a Register, not
 149 //       via an address for efficiency & simplicity reasons.
 150 
 151 class ArrayAddress;
 152 
 153 class Address VALUE_OBJ_CLASS_SPEC {
 154  public:
 155   enum ScaleFactor {
 156     no_scale = -1,
 157     times_1  =  0,
 158     times_2  =  1,
 159     times_4  =  2,
 160     times_8  =  3,
 161     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 162   };
 163   static ScaleFactor times(int size) {
 164     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 165     if (size == 8)  return times_8;
 166     if (size == 4)  return times_4;
 167     if (size == 2)  return times_2;
 168     return times_1;
 169   }
 170   static int scale_size(ScaleFactor scale) {
 171     assert(scale != no_scale, "");
 172     assert(((1 << (int)times_1) == 1 &&
 173             (1 << (int)times_2) == 2 &&
 174             (1 << (int)times_4) == 4 &&
 175             (1 << (int)times_8) == 8), "");
 176     return (1 << (int)scale);
 177   }
 178 
 179  private:
 180   Register         _base;
 181   Register         _index;
 182   ScaleFactor      _scale;
 183   int              _disp;
 184   RelocationHolder _rspec;
 185 
 186   // Easily misused constructors make them private
 187   // %%% can we make these go away?
 188   NOT_LP64(Address(address loc, RelocationHolder spec);)
 189   Address(int disp, address loc, relocInfo::relocType rtype);
 190   Address(int disp, address loc, RelocationHolder spec);
 191 
 192  public:
 193 
 194  int disp() { return _disp; }
 195   // creation
 196   Address()
 197     : _base(noreg),
 198       _index(noreg),
 199       _scale(no_scale),
 200       _disp(0) {
 201   }
 202 
 203   // No default displacement otherwise Register can be implicitly
 204   // converted to 0(Register) which is quite a different animal.
 205 
 206   Address(Register base, int disp)
 207     : _base(base),
 208       _index(noreg),
 209       _scale(no_scale),
 210       _disp(disp) {
 211   }
 212 
 213   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 214     : _base (base),
 215       _index(index),
 216       _scale(scale),
 217       _disp (disp) {
 218     assert(!index->is_valid() == (scale == Address::no_scale),
 219            "inconsistent address");
 220   }
 221 
 222   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 223     : _base (base),
 224       _index(index.register_or_noreg()),
 225       _scale(scale),
 226       _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
 227     if (!index.is_register())  scale = Address::no_scale;
 228     assert(!_index->is_valid() == (scale == Address::no_scale),
 229            "inconsistent address");
 230   }
 231 
 232   Address plus_disp(int disp) const {
 233     Address a = (*this);
 234     a._disp += disp;
 235     return a;
 236   }
 237   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 238     Address a = (*this);
 239     a._disp += disp.constant_or_zero() * scale_size(scale);
 240     if (disp.is_register()) {
 241       assert(!a.index()->is_valid(), "competing indexes");
 242       a._index = disp.as_register();
 243       a._scale = scale;
 244     }
 245     return a;
 246   }
 247   bool is_same_address(Address a) const {
 248     // disregard _rspec
 249     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 250   }
 251 
 252   // The following two overloads are used in connection with the
 253   // ByteSize type (see sizes.hpp).  They simplify the use of
 254   // ByteSize'd arguments in assembly code. Note that their equivalent
 255   // for the optimized build are the member functions with int disp
 256   // argument since ByteSize is mapped to an int type in that case.
 257   //
 258   // Note: DO NOT introduce similar overloaded functions for WordSize
 259   // arguments as in the optimized mode, both ByteSize and WordSize
 260   // are mapped to the same type and thus the compiler cannot make a
 261   // distinction anymore (=> compiler errors).
 262 
 263 #ifdef ASSERT
 264   Address(Register base, ByteSize disp)
 265     : _base(base),
 266       _index(noreg),
 267       _scale(no_scale),
 268       _disp(in_bytes(disp)) {
 269   }
 270 
 271   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 272     : _base(base),
 273       _index(index),
 274       _scale(scale),
 275       _disp(in_bytes(disp)) {
 276     assert(!index->is_valid() == (scale == Address::no_scale),
 277            "inconsistent address");
 278   }
 279 
 280   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 281     : _base (base),
 282       _index(index.register_or_noreg()),
 283       _scale(scale),
 284       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
 285     if (!index.is_register())  scale = Address::no_scale;
 286     assert(!_index->is_valid() == (scale == Address::no_scale),
 287            "inconsistent address");
 288   }
 289 
 290 #endif // ASSERT
 291 
 292   // accessors
 293   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 294   Register    base()             const { return _base;  }
 295   Register    index()            const { return _index; }
 296   ScaleFactor scale()            const { return _scale; }
 297   int         disp()             const { return _disp;  }
 298 
 299   // Convert the raw encoding form into the form expected by the constructor for
 300   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 301   // that to noreg for the Address constructor.
 302   static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
 303 
 304   static Address make_array(ArrayAddress);
 305 
 306  private:
 307   bool base_needs_rex() const {
 308     return _base != noreg && _base->encoding() >= 8;
 309   }
 310 
 311   bool index_needs_rex() const {
 312     return _index != noreg &&_index->encoding() >= 8;
 313   }
 314 
 315   relocInfo::relocType reloc() const { return _rspec.type(); }
 316 
 317   friend class Assembler;
 318   friend class MacroAssembler;
 319   friend class LIR_Assembler; // base/index/scale/disp
 320 };
 321 
 322 //
 323 // AddressLiteral has been split out from Address because operands of this type
 324 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 325 // the few instructions that need to deal with address literals are unique and the
 326 // MacroAssembler does not have to implement every instruction in the Assembler
 327 // in order to search for address literals that may need special handling depending
 328 // on the instruction and the platform. As small step on the way to merging i486/amd64
 329 // directories.
 330 //
 331 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
 332   friend class ArrayAddress;
 333   RelocationHolder _rspec;
 334   // Typically we use AddressLiterals we want to use their rval
 335   // However in some situations we want the lval (effect address) of the item.
 336   // We provide a special factory for making those lvals.
 337   bool _is_lval;
 338 
 339   // If the target is far we'll need to load the ea of this to
 340   // a register to reach it. Otherwise if near we can do rip
 341   // relative addressing.
 342 
 343   address          _target;
 344 
 345  protected:
 346   // creation
 347   AddressLiteral()
 348     : _is_lval(false),
 349       _target(NULL)
 350   {}
 351 
 352   public:
 353 
 354 
 355   AddressLiteral(address target, relocInfo::relocType rtype);
 356 
 357   AddressLiteral(address target, RelocationHolder const& rspec)
 358     : _rspec(rspec),
 359       _is_lval(false),
 360       _target(target)
 361   {}
 362 
 363   AddressLiteral addr() {
 364     AddressLiteral ret = *this;
 365     ret._is_lval = true;
 366     return ret;
 367   }
 368 
 369 
 370  private:
 371 
 372   address target() { return _target; }
 373   bool is_lval() { return _is_lval; }
 374 
 375   relocInfo::relocType reloc() const { return _rspec.type(); }
 376   const RelocationHolder& rspec() const { return _rspec; }
 377 
 378   friend class Assembler;
 379   friend class MacroAssembler;
 380   friend class Address;
 381   friend class LIR_Assembler;
 382 };
 383 
 384 // Convience classes
 385 class RuntimeAddress: public AddressLiteral {
 386 
 387   public:
 388 
 389   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 390 
 391 };
 392 
 393 class OopAddress: public AddressLiteral {
 394 
 395   public:
 396 
 397   OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
 398 
 399 };
 400 
 401 class ExternalAddress: public AddressLiteral {
 402  private:
 403   static relocInfo::relocType reloc_for_target(address target) {
 404     // Sometimes ExternalAddress is used for values which aren't
 405     // exactly addresses, like the card table base.
 406     // external_word_type can't be used for values in the first page
 407     // so just skip the reloc in that case.
 408     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 409   }
 410 
 411  public:
 412 
 413   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 414 
 415 };
 416 
 417 class InternalAddress: public AddressLiteral {
 418 
 419   public:
 420 
 421   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 422 
 423 };
 424 
 425 // x86 can do array addressing as a single operation since disp can be an absolute
 426 // address amd64 can't. We create a class that expresses the concept but does extra
 427 // magic on amd64 to get the final result
 428 
 429 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
 430   private:
 431 
 432   AddressLiteral _base;
 433   Address        _index;
 434 
 435   public:
 436 
 437   ArrayAddress() {};
 438   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 439   AddressLiteral base() { return _base; }
 440   Address index() { return _index; }
 441 
 442 };
 443 
 444 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
 445 
 446 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 447 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 448 // is what you get. The Assembler is generating code into a CodeBuffer.
 449 
 450 class Assembler : public AbstractAssembler  {
 451   friend class AbstractAssembler; // for the non-virtual hack
 452   friend class LIR_Assembler; // as_Address()
 453   friend class StubGenerator;
 454 
 455  public:
 456   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 457     zero          = 0x4,
 458     notZero       = 0x5,
 459     equal         = 0x4,
 460     notEqual      = 0x5,
 461     less          = 0xc,
 462     lessEqual     = 0xe,
 463     greater       = 0xf,
 464     greaterEqual  = 0xd,
 465     below         = 0x2,
 466     belowEqual    = 0x6,
 467     above         = 0x7,
 468     aboveEqual    = 0x3,
 469     overflow      = 0x0,
 470     noOverflow    = 0x1,
 471     carrySet      = 0x2,
 472     carryClear    = 0x3,
 473     negative      = 0x8,
 474     positive      = 0x9,
 475     parity        = 0xa,
 476     noParity      = 0xb
 477   };
 478 
 479   enum Prefix {
 480     // segment overrides
 481     CS_segment = 0x2e,
 482     SS_segment = 0x36,
 483     DS_segment = 0x3e,
 484     ES_segment = 0x26,
 485     FS_segment = 0x64,
 486     GS_segment = 0x65,
 487 
 488     REX        = 0x40,
 489 
 490     REX_B      = 0x41,
 491     REX_X      = 0x42,
 492     REX_XB     = 0x43,
 493     REX_R      = 0x44,
 494     REX_RB     = 0x45,
 495     REX_RX     = 0x46,
 496     REX_RXB    = 0x47,
 497 
 498     REX_W      = 0x48,
 499 
 500     REX_WB     = 0x49,
 501     REX_WX     = 0x4A,
 502     REX_WXB    = 0x4B,
 503     REX_WR     = 0x4C,
 504     REX_WRB    = 0x4D,
 505     REX_WRX    = 0x4E,
 506     REX_WRXB   = 0x4F,
 507 
 508     VEX_3bytes = 0xC4,
 509     VEX_2bytes = 0xC5
 510   };
 511 
 512   enum VexPrefix {
 513     VEX_B = 0x20,
 514     VEX_X = 0x40,
 515     VEX_R = 0x80,
 516     VEX_W = 0x80
 517   };
 518 
 519   enum VexSimdPrefix {
 520     VEX_SIMD_NONE = 0x0,
 521     VEX_SIMD_66   = 0x1,
 522     VEX_SIMD_F3   = 0x2,
 523     VEX_SIMD_F2   = 0x3
 524   };
 525 
 526   enum VexOpcode {
 527     VEX_OPCODE_NONE  = 0x0,
 528     VEX_OPCODE_0F    = 0x1,
 529     VEX_OPCODE_0F_38 = 0x2,
 530     VEX_OPCODE_0F_3A = 0x3
 531   };
 532 
 533   enum WhichOperand {
 534     // input to locate_operand, and format code for relocations
 535     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 536     disp32_operand = 1,          // embedded 32-bit displacement or address
 537     call32_operand = 2,          // embedded 32-bit self-relative displacement
 538 #ifndef _LP64
 539     _WhichOperand_limit = 3
 540 #else
 541      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 542     _WhichOperand_limit = 4
 543 #endif
 544   };
 545 
 546 
 547 
 548   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 549   // of instructions are freely declared without the need for wrapping them an ifdef.
 550   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 551   // In the .cpp file the implementations are wrapped so that they are dropped out
 552   // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
 553   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 554   //
 555   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 556   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 557 
 558 private:
 559 
 560 
 561   // 64bit prefixes
 562   int prefix_and_encode(int reg_enc, bool byteinst = false);
 563   int prefixq_and_encode(int reg_enc);
 564 
 565   int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
 566   int prefixq_and_encode(int dst_enc, int src_enc);
 567 
 568   void prefix(Register reg);
 569   void prefix(Address adr);
 570   void prefixq(Address adr);
 571 
 572   void prefix(Address adr, Register reg,  bool byteinst = false);
 573   void prefix(Address adr, XMMRegister reg);
 574   void prefixq(Address adr, Register reg);
 575   void prefixq(Address adr, XMMRegister reg);
 576 
 577   void prefetch_prefix(Address src);
 578 
 579   void rex_prefix(Address adr, XMMRegister xreg,
 580                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 581   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 582                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 583 
 584   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
 585                   int nds_enc, VexSimdPrefix pre, VexOpcode opc,
 586                   bool vector256);
 587 
 588   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 589                   VexSimdPrefix pre, VexOpcode opc,
 590                   bool vex_w, bool vector256);
 591 
 592   void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
 593                   VexSimdPrefix pre, bool vector256 = false) {
 594      vex_prefix(src, nds->encoding(), dst->encoding(),
 595                 pre, VEX_OPCODE_0F, false, vector256);
 596   }
 597 
 598   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 599                              VexSimdPrefix pre, VexOpcode opc,
 600                              bool vex_w, bool vector256);
 601 
 602   int  vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
 603                              VexSimdPrefix pre, bool vector256 = false) {
 604      return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
 605                                   pre, VEX_OPCODE_0F, false, vector256);
 606   }
 607 
 608   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
 609                    VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
 610                    bool rex_w = false, bool vector256 = false);
 611 
 612   void simd_prefix(XMMRegister dst, Address src,
 613                    VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
 614     simd_prefix(dst, xnoreg, src, pre, opc);
 615   }
 616   void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
 617     simd_prefix(src, dst, pre);
 618   }
 619   void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
 620                      VexSimdPrefix pre) {
 621     bool rex_w = true;
 622     simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
 623   }
 624 
 625 
 626   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
 627                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
 628                              bool rex_w = false, bool vector256 = false);
 629 
 630   int simd_prefix_and_encode(XMMRegister dst, XMMRegister src,
 631                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
 632     return simd_prefix_and_encode(dst, xnoreg, src, pre, opc);
 633   }
 634 
 635   // Move/convert 32-bit integer value.
 636   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
 637                              VexSimdPrefix pre) {
 638     // It is OK to cast from Register to XMMRegister to pass argument here
 639     // since only encoding is used in simd_prefix_and_encode() and number of
 640     // Gen and Xmm registers are the same.
 641     return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre);
 642   }
 643   int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) {
 644     return simd_prefix_and_encode(dst, xnoreg, src, pre);
 645   }
 646   int simd_prefix_and_encode(Register dst, XMMRegister src,
 647                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
 648     return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc);
 649   }
 650 
 651   // Move/convert 64-bit integer value.
 652   int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
 653                                VexSimdPrefix pre) {
 654     bool rex_w = true;
 655     return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w);
 656   }
 657   int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) {
 658     return simd_prefix_and_encode_q(dst, xnoreg, src, pre);
 659   }
 660   int simd_prefix_and_encode_q(Register dst, XMMRegister src,
 661                              VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
 662     bool rex_w = true;
 663     return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w);
 664   }
 665 
 666   // Helper functions for groups of instructions
 667   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 668 
 669   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 670   // Force generation of a 4 byte immediate value even if it fits into 8bit
 671   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 672   // only 32bit??
 673   void emit_arith(int op1, int op2, Register dst, jobject obj);
 674   void emit_arith(int op1, int op2, Register dst, Register src);
 675 
 676   void emit_operand(Register reg,
 677                     Register base, Register index, Address::ScaleFactor scale,
 678                     int disp,
 679                     RelocationHolder const& rspec,
 680                     int rip_relative_correction = 0);
 681 
 682   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 683 
 684   // operands that only take the original 32bit registers
 685   void emit_operand32(Register reg, Address adr);
 686 
 687   void emit_operand(XMMRegister reg,
 688                     Register base, Register index, Address::ScaleFactor scale,
 689                     int disp,
 690                     RelocationHolder const& rspec);
 691 
 692   void emit_operand(XMMRegister reg, Address adr);
 693 
 694   void emit_operand(MMXRegister reg, Address adr);
 695 
 696   // workaround gcc (3.2.1-7) bug
 697   void emit_operand(Address adr, MMXRegister reg);
 698 
 699 
 700   // Immediate-to-memory forms
 701   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 702 
 703   void emit_farith(int b1, int b2, int i);
 704 
 705 
 706  protected:
 707   #ifdef ASSERT
 708   void check_relocation(RelocationHolder const& rspec, int format);
 709   #endif
 710 
 711   inline void emit_long64(jlong x);
 712 
 713   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 714   void emit_data(jint data, RelocationHolder const& rspec, int format);
 715   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 716   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 717 
 718   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 719 
 720   // These are all easily abused and hence protected
 721 
 722   // 32BIT ONLY SECTION
 723 #ifndef _LP64
 724   // Make these disappear in 64bit mode since they would never be correct
 725   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 726   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 727 
 728   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 729   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 730 
 731   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 732 #else
 733   // 64BIT ONLY SECTION
 734   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 735 
 736   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 737   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 738 
 739   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 740   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 741 #endif // _LP64
 742 
 743   // These are unique in that we are ensured by the caller that the 32bit
 744   // relative in these instructions will always be able to reach the potentially
 745   // 64bit address described by entry. Since they can take a 64bit address they
 746   // don't have the 32 suffix like the other instructions in this class.
 747 
 748   void call_literal(address entry, RelocationHolder const& rspec);
 749   void jmp_literal(address entry, RelocationHolder const& rspec);
 750 
 751   // Avoid using directly section
 752   // Instructions in this section are actually usable by anyone without danger
 753   // of failure but have performance issues that are addressed my enhanced
 754   // instructions which will do the proper thing base on the particular cpu.
 755   // We protect them because we don't trust you...
 756 
 757   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 758   // could cause a partial flag stall since they don't set CF flag.
 759   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 760   // which call inc() & dec() or add() & sub() in accordance with
 761   // the product flag UseIncDec value.
 762 
 763   void decl(Register dst);
 764   void decl(Address dst);
 765   void decq(Register dst);
 766   void decq(Address dst);
 767 
 768   void incl(Register dst);
 769   void incl(Address dst);
 770   void incq(Register dst);
 771   void incq(Address dst);
 772 
 773   // New cpus require use of movsd and movss to avoid partial register stall
 774   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 775   // The selection is done in MacroAssembler::movdbl() and movflt().
 776 
 777   // Move Scalar Single-Precision Floating-Point Values
 778   void movss(XMMRegister dst, Address src);
 779   void movss(XMMRegister dst, XMMRegister src);
 780   void movss(Address dst, XMMRegister src);
 781 
 782   // Move Scalar Double-Precision Floating-Point Values
 783   void movsd(XMMRegister dst, Address src);
 784   void movsd(XMMRegister dst, XMMRegister src);
 785   void movsd(Address dst, XMMRegister src);
 786   void movlpd(XMMRegister dst, Address src);
 787 
 788   // New cpus require use of movaps and movapd to avoid partial register stall
 789   // when moving between registers.
 790   void movaps(XMMRegister dst, XMMRegister src);
 791   void movapd(XMMRegister dst, XMMRegister src);
 792 
 793   // End avoid using directly
 794 
 795 
 796   // Instruction prefixes
 797   void prefix(Prefix p);
 798 
 799   public:
 800 
 801   // Creation
 802   Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
 803 
 804   // Decoding
 805   static address locate_operand(address inst, WhichOperand which);
 806   static address locate_next_instruction(address inst);
 807 
 808   // Utilities
 809   static bool is_polling_page_far() NOT_LP64({ return false;});
 810 
 811   // Generic instructions
 812   // Does 32bit or 64bit as needed for the platform. In some sense these
 813   // belong in macro assembler but there is no need for both varieties to exist
 814 
 815   void lea(Register dst, Address src);
 816 
 817   void mov(Register dst, Register src);
 818 
 819   void pusha();
 820   void popa();
 821 
 822   void pushf();
 823   void popf();
 824 
 825   void push(int32_t imm32);
 826 
 827   void push(Register src);
 828 
 829   void pop(Register dst);
 830 
 831   // These are dummies to prevent surprise implicit conversions to Register
 832   void push(void* v);
 833   void pop(void* v);
 834 
 835   // These do register sized moves/scans
 836   void rep_mov();
 837   void rep_set();
 838   void repne_scan();
 839 #ifdef _LP64
 840   void repne_scanl();
 841 #endif
 842 
 843   // Vanilla instructions in lexical order
 844 
 845   void adcl(Address dst, int32_t imm32);
 846   void adcl(Address dst, Register src);
 847   void adcl(Register dst, int32_t imm32);
 848   void adcl(Register dst, Address src);
 849   void adcl(Register dst, Register src);
 850 
 851   void adcq(Register dst, int32_t imm32);
 852   void adcq(Register dst, Address src);
 853   void adcq(Register dst, Register src);
 854 
 855   void addl(Address dst, int32_t imm32);
 856   void addl(Address dst, Register src);
 857   void addl(Register dst, int32_t imm32);
 858   void addl(Register dst, Address src);
 859   void addl(Register dst, Register src);
 860 
 861   void addq(Address dst, int32_t imm32);
 862   void addq(Address dst, Register src);
 863   void addq(Register dst, int32_t imm32);
 864   void addq(Register dst, Address src);
 865   void addq(Register dst, Register src);
 866 
 867   void addr_nop_4();
 868   void addr_nop_5();
 869   void addr_nop_7();
 870   void addr_nop_8();
 871 
 872   // Add Scalar Double-Precision Floating-Point Values
 873   void addsd(XMMRegister dst, Address src);
 874   void addsd(XMMRegister dst, XMMRegister src);
 875 
 876   // Add Scalar Single-Precision Floating-Point Values
 877   void addss(XMMRegister dst, Address src);
 878   void addss(XMMRegister dst, XMMRegister src);
 879 
 880   void andl(Address  dst, int32_t imm32);
 881   void andl(Register dst, int32_t imm32);
 882   void andl(Register dst, Address src);
 883   void andl(Register dst, Register src);
 884 
 885   void andq(Address  dst, int32_t imm32);
 886   void andq(Register dst, int32_t imm32);
 887   void andq(Register dst, Address src);
 888   void andq(Register dst, Register src);
 889 
 890   // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
 891   void andpd(XMMRegister dst, XMMRegister src);
 892 
 893   // Bitwise Logical AND of Packed Single-Precision Floating-Point Values
 894   void andps(XMMRegister dst, XMMRegister src);
 895 
 896   void bsfl(Register dst, Register src);
 897   void bsrl(Register dst, Register src);
 898 
 899 #ifdef _LP64
 900   void bsfq(Register dst, Register src);
 901   void bsrq(Register dst, Register src);
 902 #endif
 903 
 904   void bswapl(Register reg);
 905 
 906   void bswapq(Register reg);
 907 
 908   void call(Label& L, relocInfo::relocType rtype);
 909   void call(Register reg);  // push pc; pc <- reg
 910   void call(Address adr);   // push pc; pc <- adr
 911 
 912   void cdql();
 913 
 914   void cdqq();
 915 
 916   void cld() { emit_byte(0xfc); }
 917 
 918   void clflush(Address adr);
 919 
 920   void cmovl(Condition cc, Register dst, Register src);
 921   void cmovl(Condition cc, Register dst, Address src);
 922 
 923   void cmovq(Condition cc, Register dst, Register src);
 924   void cmovq(Condition cc, Register dst, Address src);
 925 
 926 
 927   void cmpb(Address dst, int imm8);
 928 
 929   void cmpl(Address dst, int32_t imm32);
 930 
 931   void cmpl(Register dst, int32_t imm32);
 932   void cmpl(Register dst, Register src);
 933   void cmpl(Register dst, Address src);
 934 
 935   void cmpq(Address dst, int32_t imm32);
 936   void cmpq(Address dst, Register src);
 937 
 938   void cmpq(Register dst, int32_t imm32);
 939   void cmpq(Register dst, Register src);
 940   void cmpq(Register dst, Address src);
 941 
 942   // these are dummies used to catch attempting to convert NULL to Register
 943   void cmpl(Register dst, void* junk); // dummy
 944   void cmpq(Register dst, void* junk); // dummy
 945 
 946   void cmpw(Address dst, int imm16);
 947 
 948   void cmpxchg8 (Address adr);
 949 
 950   void cmpxchgl(Register reg, Address adr);
 951 
 952   void cmpxchgq(Register reg, Address adr);
 953 
 954   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
 955   void comisd(XMMRegister dst, Address src);
 956   void comisd(XMMRegister dst, XMMRegister src);
 957 
 958   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
 959   void comiss(XMMRegister dst, Address src);
 960   void comiss(XMMRegister dst, XMMRegister src);
 961 
 962   // Identify processor type and features
 963   void cpuid() {
 964     emit_byte(0x0F);
 965     emit_byte(0xA2);
 966   }
 967 
 968   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
 969   void cvtsd2ss(XMMRegister dst, XMMRegister src);
 970   void cvtsd2ss(XMMRegister dst, Address src);
 971 
 972   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
 973   void cvtsi2sdl(XMMRegister dst, Register src);
 974   void cvtsi2sdl(XMMRegister dst, Address src);
 975   void cvtsi2sdq(XMMRegister dst, Register src);
 976   void cvtsi2sdq(XMMRegister dst, Address src);
 977 
 978   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
 979   void cvtsi2ssl(XMMRegister dst, Register src);
 980   void cvtsi2ssl(XMMRegister dst, Address src);
 981   void cvtsi2ssq(XMMRegister dst, Register src);
 982   void cvtsi2ssq(XMMRegister dst, Address src);
 983 
 984   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
 985   void cvtdq2pd(XMMRegister dst, XMMRegister src);
 986 
 987   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
 988   void cvtdq2ps(XMMRegister dst, XMMRegister src);
 989 
 990   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
 991   void cvtss2sd(XMMRegister dst, XMMRegister src);
 992   void cvtss2sd(XMMRegister dst, Address src);
 993 
 994   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
 995   void cvttsd2sil(Register dst, Address src);
 996   void cvttsd2sil(Register dst, XMMRegister src);
 997   void cvttsd2siq(Register dst, XMMRegister src);
 998 
 999   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1000   void cvttss2sil(Register dst, XMMRegister src);
1001   void cvttss2siq(Register dst, XMMRegister src);
1002 
1003   // Divide Scalar Double-Precision Floating-Point Values
1004   void divsd(XMMRegister dst, Address src);
1005   void divsd(XMMRegister dst, XMMRegister src);
1006 
1007   // Divide Scalar Single-Precision Floating-Point Values
1008   void divss(XMMRegister dst, Address src);
1009   void divss(XMMRegister dst, XMMRegister src);
1010 
1011   void emms();
1012 
1013   void fabs();
1014 
1015   void fadd(int i);
1016 
1017   void fadd_d(Address src);
1018   void fadd_s(Address src);
1019 
1020   // "Alternate" versions of x87 instructions place result down in FPU
1021   // stack instead of on TOS
1022 
1023   void fadda(int i); // "alternate" fadd
1024   void faddp(int i = 1);
1025 
1026   void fchs();
1027 
1028   void fcom(int i);
1029 
1030   void fcomp(int i = 1);
1031   void fcomp_d(Address src);
1032   void fcomp_s(Address src);
1033 
1034   void fcompp();
1035 
1036   void fcos();
1037 
1038   void fdecstp();
1039 
1040   void fdiv(int i);
1041   void fdiv_d(Address src);
1042   void fdivr_s(Address src);
1043   void fdiva(int i);  // "alternate" fdiv
1044   void fdivp(int i = 1);
1045 
1046   void fdivr(int i);
1047   void fdivr_d(Address src);
1048   void fdiv_s(Address src);
1049 
1050   void fdivra(int i); // "alternate" reversed fdiv
1051 
1052   void fdivrp(int i = 1);
1053 
1054   void ffree(int i = 0);
1055 
1056   void fild_d(Address adr);
1057   void fild_s(Address adr);
1058 
1059   void fincstp();
1060 
1061   void finit();
1062 
1063   void fist_s (Address adr);
1064   void fistp_d(Address adr);
1065   void fistp_s(Address adr);
1066 
1067   void fld1();
1068 
1069   void fld_d(Address adr);
1070   void fld_s(Address adr);
1071   void fld_s(int index);
1072   void fld_x(Address adr);  // extended-precision (80-bit) format
1073 
1074   void fldcw(Address src);
1075 
1076   void fldenv(Address src);
1077 
1078   void fldlg2();
1079 
1080   void fldln2();
1081 
1082   void fldz();
1083 
1084   void flog();
1085   void flog10();
1086 
1087   void fmul(int i);
1088 
1089   void fmul_d(Address src);
1090   void fmul_s(Address src);
1091 
1092   void fmula(int i);  // "alternate" fmul
1093 
1094   void fmulp(int i = 1);
1095 
1096   void fnsave(Address dst);
1097 
1098   void fnstcw(Address src);
1099 
1100   void fnstsw_ax();
1101 
1102   void fprem();
1103   void fprem1();
1104 
1105   void frstor(Address src);
1106 
1107   void fsin();
1108 
1109   void fsqrt();
1110 
1111   void fst_d(Address adr);
1112   void fst_s(Address adr);
1113 
1114   void fstp_d(Address adr);
1115   void fstp_d(int index);
1116   void fstp_s(Address adr);
1117   void fstp_x(Address adr); // extended-precision (80-bit) format
1118 
1119   void fsub(int i);
1120   void fsub_d(Address src);
1121   void fsub_s(Address src);
1122 
1123   void fsuba(int i);  // "alternate" fsub
1124 
1125   void fsubp(int i = 1);
1126 
1127   void fsubr(int i);
1128   void fsubr_d(Address src);
1129   void fsubr_s(Address src);
1130 
1131   void fsubra(int i); // "alternate" reversed fsub
1132 
1133   void fsubrp(int i = 1);
1134 
1135   void ftan();
1136 
1137   void ftst();
1138 
1139   void fucomi(int i = 1);
1140   void fucomip(int i = 1);
1141 
1142   void fwait();
1143 
1144   void fxch(int i = 1);
1145 
1146   void fxrstor(Address src);
1147 
1148   void fxsave(Address dst);
1149 
1150   void fyl2x();
1151   void frndint();
1152   void f2xm1();
1153   void fldl2e();
1154 
1155   void hlt();
1156 
1157   void idivl(Register src);
1158   void divl(Register src); // Unsigned division
1159 
1160   void idivq(Register src);
1161 
1162   void imull(Register dst, Register src);
1163   void imull(Register dst, Register src, int value);
1164 
1165   void imulq(Register dst, Register src);
1166   void imulq(Register dst, Register src, int value);
1167 
1168 
1169   // jcc is the generic conditional branch generator to run-
1170   // time routines, jcc is used for branches to labels. jcc
1171   // takes a branch opcode (cc) and a label (L) and generates
1172   // either a backward branch or a forward branch and links it
1173   // to the label fixup chain. Usage:
1174   //
1175   // Label L;      // unbound label
1176   // jcc(cc, L);   // forward branch to unbound label
1177   // bind(L);      // bind label to the current pc
1178   // jcc(cc, L);   // backward branch to bound label
1179   // bind(L);      // illegal: a label may be bound only once
1180   //
1181   // Note: The same Label can be used for forward and backward branches
1182   // but it may be bound only once.
1183 
1184   void jcc(Condition cc, Label& L, bool maybe_short = true);
1185 
1186   // Conditional jump to a 8-bit offset to L.
1187   // WARNING: be very careful using this for forward jumps.  If the label is
1188   // not bound within an 8-bit offset of this instruction, a run-time error
1189   // will occur.
1190   void jccb(Condition cc, Label& L);
1191 
1192   void jmp(Address entry);    // pc <- entry
1193 
1194   // Label operations & relative jumps (PPUM Appendix D)
1195   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1196 
1197   void jmp(Register entry); // pc <- entry
1198 
1199   // Unconditional 8-bit offset jump to L.
1200   // WARNING: be very careful using this for forward jumps.  If the label is
1201   // not bound within an 8-bit offset of this instruction, a run-time error
1202   // will occur.
1203   void jmpb(Label& L);
1204 
1205   void ldmxcsr( Address src );
1206 
1207   void leal(Register dst, Address src);
1208 
1209   void leaq(Register dst, Address src);
1210 
1211   void lfence() {
1212     emit_byte(0x0F);
1213     emit_byte(0xAE);
1214     emit_byte(0xE8);
1215   }
1216 
1217   void lock();
1218 
1219   void lzcntl(Register dst, Register src);
1220 
1221 #ifdef _LP64
1222   void lzcntq(Register dst, Register src);
1223 #endif
1224 
1225   enum Membar_mask_bits {
1226     StoreStore = 1 << 3,
1227     LoadStore  = 1 << 2,
1228     StoreLoad  = 1 << 1,
1229     LoadLoad   = 1 << 0
1230   };
1231 
1232   // Serializes memory and blows flags
1233   void membar(Membar_mask_bits order_constraint) {
1234     if (os::is_MP()) {
1235       // We only have to handle StoreLoad
1236       if (order_constraint & StoreLoad) {
1237         // All usable chips support "locked" instructions which suffice
1238         // as barriers, and are much faster than the alternative of
1239         // using cpuid instruction. We use here a locked add [esp],0.
1240         // This is conveniently otherwise a no-op except for blowing
1241         // flags.
1242         // Any change to this code may need to revisit other places in
1243         // the code where this idiom is used, in particular the
1244         // orderAccess code.
1245         lock();
1246         addl(Address(rsp, 0), 0);// Assert the lock# signal here
1247       }
1248     }
1249   }
1250 
1251   void mfence();
1252 
1253   // Moves
1254 
1255   void mov64(Register dst, int64_t imm64);
1256 
1257   void movb(Address dst, Register src);
1258   void movb(Address dst, int imm8);
1259   void movb(Register dst, Address src);
1260 
1261   void movdl(XMMRegister dst, Register src);
1262   void movdl(Register dst, XMMRegister src);
1263   void movdl(XMMRegister dst, Address src);
1264 
1265   // Move Double Quadword
1266   void movdq(XMMRegister dst, Register src);
1267   void movdq(Register dst, XMMRegister src);
1268 
1269   // Move Aligned Double Quadword
1270   void movdqa(XMMRegister dst, XMMRegister src);
1271 
1272   // Move Unaligned Double Quadword
1273   void movdqu(Address     dst, XMMRegister src);
1274   void movdqu(XMMRegister dst, Address src);
1275   void movdqu(XMMRegister dst, XMMRegister src);
1276 
1277   void movl(Register dst, int32_t imm32);
1278   void movl(Address dst, int32_t imm32);
1279   void movl(Register dst, Register src);
1280   void movl(Register dst, Address src);
1281   void movl(Address dst, Register src);
1282 
1283   // These dummies prevent using movl from converting a zero (like NULL) into Register
1284   // by giving the compiler two choices it can't resolve
1285 
1286   void movl(Address  dst, void* junk);
1287   void movl(Register dst, void* junk);
1288 
1289 #ifdef _LP64
1290   void movq(Register dst, Register src);
1291   void movq(Register dst, Address src);
1292   void movq(Address  dst, Register src);
1293 #endif
1294 
1295   void movq(Address     dst, MMXRegister src );
1296   void movq(MMXRegister dst, Address src );
1297 
1298 #ifdef _LP64
1299   // These dummies prevent using movq from converting a zero (like NULL) into Register
1300   // by giving the compiler two choices it can't resolve
1301 
1302   void movq(Address  dst, void* dummy);
1303   void movq(Register dst, void* dummy);
1304 #endif
1305 
1306   // Move Quadword
1307   void movq(Address     dst, XMMRegister src);
1308   void movq(XMMRegister dst, Address src);
1309 
1310   void movsbl(Register dst, Address src);
1311   void movsbl(Register dst, Register src);
1312 
1313 #ifdef _LP64
1314   void movsbq(Register dst, Address src);
1315   void movsbq(Register dst, Register src);
1316 
1317   // Move signed 32bit immediate to 64bit extending sign
1318   void movslq(Address  dst, int32_t imm64);
1319   void movslq(Register dst, int32_t imm64);
1320 
1321   void movslq(Register dst, Address src);
1322   void movslq(Register dst, Register src);
1323   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1324 #endif
1325 
1326   void movswl(Register dst, Address src);
1327   void movswl(Register dst, Register src);
1328 
1329 #ifdef _LP64
1330   void movswq(Register dst, Address src);
1331   void movswq(Register dst, Register src);
1332 #endif
1333 
1334   void movw(Address dst, int imm16);
1335   void movw(Register dst, Address src);
1336   void movw(Address dst, Register src);
1337 
1338   void movzbl(Register dst, Address src);
1339   void movzbl(Register dst, Register src);
1340 
1341 #ifdef _LP64
1342   void movzbq(Register dst, Address src);
1343   void movzbq(Register dst, Register src);
1344 #endif
1345 
1346   void movzwl(Register dst, Address src);
1347   void movzwl(Register dst, Register src);
1348 
1349 #ifdef _LP64
1350   void movzwq(Register dst, Address src);
1351   void movzwq(Register dst, Register src);
1352 #endif
1353 
1354   void mull(Address src);
1355   void mull(Register src);
1356 
1357   // Multiply Scalar Double-Precision Floating-Point Values
1358   void mulsd(XMMRegister dst, Address src);
1359   void mulsd(XMMRegister dst, XMMRegister src);
1360 
1361   // Multiply Scalar Single-Precision Floating-Point Values
1362   void mulss(XMMRegister dst, Address src);
1363   void mulss(XMMRegister dst, XMMRegister src);
1364 
1365   void negl(Register dst);
1366 
1367 #ifdef _LP64
1368   void negq(Register dst);
1369 #endif
1370 
1371   void nop(int i = 1);
1372 
1373   void notl(Register dst);
1374 
1375 #ifdef _LP64
1376   void notq(Register dst);
1377 #endif
1378 
1379   void orl(Address dst, int32_t imm32);
1380   void orl(Register dst, int32_t imm32);
1381   void orl(Register dst, Address src);
1382   void orl(Register dst, Register src);
1383 
1384   void orq(Address dst, int32_t imm32);
1385   void orq(Register dst, int32_t imm32);
1386   void orq(Register dst, Address src);
1387   void orq(Register dst, Register src);
1388 
1389   // Pack with unsigned saturation
1390   void packuswb(XMMRegister dst, XMMRegister src);
1391   void packuswb(XMMRegister dst, Address src);
1392 
1393   // SSE4.2 string instructions
1394   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1395   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1396 
1397   // SSE4.1 packed move
1398   void pmovzxbw(XMMRegister dst, XMMRegister src);
1399   void pmovzxbw(XMMRegister dst, Address src);
1400 
1401 #ifndef _LP64 // no 32bit push/pop on amd64
1402   void popl(Address dst);
1403 #endif
1404 
1405 #ifdef _LP64
1406   void popq(Address dst);
1407 #endif
1408 
1409   void popcntl(Register dst, Address src);
1410   void popcntl(Register dst, Register src);
1411 
1412 #ifdef _LP64
1413   void popcntq(Register dst, Address src);
1414   void popcntq(Register dst, Register src);
1415 #endif
1416 
1417   // Prefetches (SSE, SSE2, 3DNOW only)
1418 
1419   void prefetchnta(Address src);
1420   void prefetchr(Address src);
1421   void prefetcht0(Address src);
1422   void prefetcht1(Address src);
1423   void prefetcht2(Address src);
1424   void prefetchw(Address src);
1425 
1426   // POR - Bitwise logical OR
1427   void por(XMMRegister dst, XMMRegister src);
1428   void por(XMMRegister dst, Address src);
1429 
1430   // Shuffle Packed Doublewords
1431   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1432   void pshufd(XMMRegister dst, Address src,     int mode);
1433 
1434   // Shuffle Packed Low Words
1435   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1436   void pshuflw(XMMRegister dst, Address src,     int mode);
1437 
1438   // Shift Right by bits Logical Quadword Immediate
1439   void psrlq(XMMRegister dst, int shift);
1440 
1441   // Shift Right by bytes Logical DoubleQuadword Immediate
1442   void psrldq(XMMRegister dst, int shift);
1443 
1444   // Logical Compare Double Quadword
1445   void ptest(XMMRegister dst, XMMRegister src);
1446   void ptest(XMMRegister dst, Address src);
1447 
1448   // Interleave Low Bytes
1449   void punpcklbw(XMMRegister dst, XMMRegister src);
1450   void punpcklbw(XMMRegister dst, Address src);
1451 
1452   // Interleave Low Doublewords
1453   void punpckldq(XMMRegister dst, XMMRegister src);
1454   void punpckldq(XMMRegister dst, Address src);
1455 
1456 #ifndef _LP64 // no 32bit push/pop on amd64
1457   void pushl(Address src);
1458 #endif
1459 
1460   void pushq(Address src);
1461 
1462   // Xor Packed Byte Integer Values
1463   void pxor(XMMRegister dst, Address src);
1464   void pxor(XMMRegister dst, XMMRegister src);
1465 
1466   void rcll(Register dst, int imm8);
1467 
1468   void rclq(Register dst, int imm8);
1469 
1470   void ret(int imm16);
1471 
1472   void sahf();
1473 
1474   void sarl(Register dst, int imm8);
1475   void sarl(Register dst);
1476 
1477   void sarq(Register dst, int imm8);
1478   void sarq(Register dst);
1479 
1480   void sbbl(Address dst, int32_t imm32);
1481   void sbbl(Register dst, int32_t imm32);
1482   void sbbl(Register dst, Address src);
1483   void sbbl(Register dst, Register src);
1484 
1485   void sbbq(Address dst, int32_t imm32);
1486   void sbbq(Register dst, int32_t imm32);
1487   void sbbq(Register dst, Address src);
1488   void sbbq(Register dst, Register src);
1489 
1490   void setb(Condition cc, Register dst);
1491 
1492   void shldl(Register dst, Register src);
1493 
1494   void shll(Register dst, int imm8);
1495   void shll(Register dst);
1496 
1497   void shlq(Register dst, int imm8);
1498   void shlq(Register dst);
1499 
1500   void shrdl(Register dst, Register src);
1501 
1502   void shrl(Register dst, int imm8);
1503   void shrl(Register dst);
1504 
1505   void shrq(Register dst, int imm8);
1506   void shrq(Register dst);
1507 
1508   void smovl(); // QQQ generic?
1509 
1510   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1511   void sqrtsd(XMMRegister dst, Address src);
1512   void sqrtsd(XMMRegister dst, XMMRegister src);
1513 
1514   // Compute Square Root of Scalar Single-Precision Floating-Point Value
1515   void sqrtss(XMMRegister dst, Address src);
1516   void sqrtss(XMMRegister dst, XMMRegister src);
1517 
1518   void std() { emit_byte(0xfd); }
1519 
1520   void stmxcsr( Address dst );
1521 
1522   void subl(Address dst, int32_t imm32);
1523   void subl(Address dst, Register src);
1524   void subl(Register dst, int32_t imm32);
1525   void subl(Register dst, Address src);
1526   void subl(Register dst, Register src);
1527 
1528   void subq(Address dst, int32_t imm32);
1529   void subq(Address dst, Register src);
1530   void subq(Register dst, int32_t imm32);
1531   void subq(Register dst, Address src);
1532   void subq(Register dst, Register src);
1533 
1534   // Force generation of a 4 byte immediate value even if it fits into 8bit
1535   void subl_imm32(Register dst, int32_t imm32);
1536   void subq_imm32(Register dst, int32_t imm32);
1537 
1538   // Subtract Scalar Double-Precision Floating-Point Values
1539   void subsd(XMMRegister dst, Address src);
1540   void subsd(XMMRegister dst, XMMRegister src);
1541 
1542   // Subtract Scalar Single-Precision Floating-Point Values
1543   void subss(XMMRegister dst, Address src);
1544   void subss(XMMRegister dst, XMMRegister src);
1545 
1546   void testb(Register dst, int imm8);
1547 
1548   void testl(Register dst, int32_t imm32);
1549   void testl(Register dst, Register src);
1550   void testl(Register dst, Address src);
1551 
1552   void testq(Register dst, int32_t imm32);
1553   void testq(Register dst, Register src);
1554 
1555 
1556   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1557   void ucomisd(XMMRegister dst, Address src);
1558   void ucomisd(XMMRegister dst, XMMRegister src);
1559 
1560   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1561   void ucomiss(XMMRegister dst, Address src);
1562   void ucomiss(XMMRegister dst, XMMRegister src);
1563 
1564   void xaddl(Address dst, Register src);
1565 
1566   void xaddq(Address dst, Register src);
1567 
1568   void xchgl(Register reg, Address adr);
1569   void xchgl(Register dst, Register src);
1570 
1571   void xchgq(Register reg, Address adr);
1572   void xchgq(Register dst, Register src);
1573 
1574   // Get Value of Extended Control Register
1575   void xgetbv() {
1576     emit_byte(0x0F);
1577     emit_byte(0x01);
1578     emit_byte(0xD0);
1579   }
1580 
1581   void xorl(Register dst, int32_t imm32);
1582   void xorl(Register dst, Address src);
1583   void xorl(Register dst, Register src);
1584 
1585   void xorq(Register dst, Address src);
1586   void xorq(Register dst, Register src);
1587 
1588   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1589   void xorpd(XMMRegister dst, XMMRegister src);
1590 
1591   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1592   void xorps(XMMRegister dst, XMMRegister src);
1593 
1594   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1595 
1596   // AVX 3-operands instructions (encoded with VEX prefix)
1597   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1598   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1599   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1600   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1601   void vandpd(XMMRegister dst, XMMRegister nds, Address src);
1602   void vandps(XMMRegister dst, XMMRegister nds, Address src);
1603   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1604   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1605   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1606   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1607   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1608   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1609   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1610   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1611   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1612   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1613   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1614   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1615   void vxorpd(XMMRegister dst, XMMRegister nds, Address src);
1616   void vxorps(XMMRegister dst, XMMRegister nds, Address src);
1617 
1618 
1619  protected:
1620   // Next instructions require address alignment 16 bytes SSE mode.
1621   // They should be called only from corresponding MacroAssembler instructions.
1622   void andpd(XMMRegister dst, Address src);
1623   void andps(XMMRegister dst, Address src);
1624   void xorpd(XMMRegister dst, Address src);
1625   void xorps(XMMRegister dst, Address src);
1626 
1627 };
1628 
1629 
1630 // MacroAssembler extends Assembler by frequently used macros.
1631 //
1632 // Instructions for which a 'better' code sequence exists depending
1633 // on arguments should also go in here.
1634 
1635 class MacroAssembler: public Assembler {
1636   friend class LIR_Assembler;
1637   friend class Runtime1;      // as_Address()
1638 
1639  protected:
1640 
1641   Address as_Address(AddressLiteral adr);
1642   Address as_Address(ArrayAddress adr);
1643 
1644   // Support for VM calls
1645   //
1646   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1647   // may customize this version by overriding it for its purposes (e.g., to save/restore
1648   // additional registers when doing a VM call).
1649 #ifdef CC_INTERP
1650   // c++ interpreter never wants to use interp_masm version of call_VM
1651   #define VIRTUAL
1652 #else
1653   #define VIRTUAL virtual
1654 #endif
1655 
1656   VIRTUAL void call_VM_leaf_base(
1657     address entry_point,               // the entry point
1658     int     number_of_arguments        // the number of arguments to pop after the call
1659   );
1660 
1661   // This is the base routine called by the different versions of call_VM. The interpreter
1662   // may customize this version by overriding it for its purposes (e.g., to save/restore
1663   // additional registers when doing a VM call).
1664   //
1665   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1666   // returns the register which contains the thread upon return. If a thread register has been
1667   // specified, the return value will correspond to that register. If no last_java_sp is specified
1668   // (noreg) than rsp will be used instead.
1669   VIRTUAL void call_VM_base(           // returns the register containing the thread upon return
1670     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
1671     Register java_thread,              // the thread if computed before     ; use noreg otherwise
1672     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
1673     address  entry_point,              // the entry point
1674     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
1675     bool     check_exceptions          // whether to check for pending exceptions after return
1676   );
1677 
1678   // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1679   // The implementation is only non-empty for the InterpreterMacroAssembler,
1680   // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1681   virtual void check_and_handle_popframe(Register java_thread);
1682   virtual void check_and_handle_earlyret(Register java_thread);
1683 
1684   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1685 
1686   // helpers for FPU flag access
1687   // tmp is a temporary register, if none is available use noreg
1688   void save_rax   (Register tmp);
1689   void restore_rax(Register tmp);
1690 
1691  public:
1692   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1693 
1694   // Support for NULL-checks
1695   //
1696   // Generates code that causes a NULL OS exception if the content of reg is NULL.
1697   // If the accessed location is M[reg + offset] and the offset is known, provide the
1698   // offset. No explicit code generation is needed if the offset is within a certain
1699   // range (0 <= offset <= page_size).
1700 
1701   void null_check(Register reg, int offset = -1);
1702   static bool needs_explicit_null_check(intptr_t offset);
1703 
1704   // Required platform-specific helpers for Label::patch_instructions.
1705   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1706   void pd_patch_instruction(address branch, address target);
1707 #ifndef PRODUCT
1708   static void pd_print_patched_instruction(address branch);
1709 #endif
1710 
1711   // The following 4 methods return the offset of the appropriate move instruction
1712 
1713   // Support for fast byte/short loading with zero extension (depending on particular CPU)
1714   int load_unsigned_byte(Register dst, Address src);
1715   int load_unsigned_short(Register dst, Address src);
1716 
1717   // Support for fast byte/short loading with sign extension (depending on particular CPU)
1718   int load_signed_byte(Register dst, Address src);
1719   int load_signed_short(Register dst, Address src);
1720 
1721   // Support for sign-extension (hi:lo = extend_sign(lo))
1722   void extend_sign(Register hi, Register lo);
1723 
1724   // Load and store values by size and signed-ness
1725   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
1726   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
1727 
1728   // Support for inc/dec with optimal instruction selection depending on value
1729 
1730   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1731   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1732 
1733   void decrementl(Address dst, int value = 1);
1734   void decrementl(Register reg, int value = 1);
1735 
1736   void decrementq(Register reg, int value = 1);
1737   void decrementq(Address dst, int value = 1);
1738 
1739   void incrementl(Address dst, int value = 1);
1740   void incrementl(Register reg, int value = 1);
1741 
1742   void incrementq(Register reg, int value = 1);
1743   void incrementq(Address dst, int value = 1);
1744 
1745 
1746   // Support optimal SSE move instructions.
1747   void movflt(XMMRegister dst, XMMRegister src) {
1748     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1749     else                       { movss (dst, src); return; }
1750   }
1751   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1752   void movflt(XMMRegister dst, AddressLiteral src);
1753   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1754 
1755   void movdbl(XMMRegister dst, XMMRegister src) {
1756     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1757     else                       { movsd (dst, src); return; }
1758   }
1759 
1760   void movdbl(XMMRegister dst, AddressLiteral src);
1761 
1762   void movdbl(XMMRegister dst, Address src) {
1763     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1764     else                         { movlpd(dst, src); return; }
1765   }
1766   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1767 
1768   void incrementl(AddressLiteral dst);
1769   void incrementl(ArrayAddress dst);
1770 
1771   // Alignment
1772   void align(int modulus);
1773 
1774   // A 5 byte nop that is safe for patching (see patch_verified_entry)
1775   void fat_nop();
1776 
1777   // Stack frame creation/removal
1778   void enter();
1779   void leave();
1780 
1781   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1782   // The pointer will be loaded into the thread register.
1783   void get_thread(Register thread);
1784 
1785 
1786   // Support for VM calls
1787   //
1788   // It is imperative that all calls into the VM are handled via the call_VM macros.
1789   // They make sure that the stack linkage is setup correctly. call_VM's correspond
1790   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1791 
1792 
1793   void call_VM(Register oop_result,
1794                address entry_point,
1795                bool check_exceptions = true);
1796   void call_VM(Register oop_result,
1797                address entry_point,
1798                Register arg_1,
1799                bool check_exceptions = true);
1800   void call_VM(Register oop_result,
1801                address entry_point,
1802                Register arg_1, Register arg_2,
1803                bool check_exceptions = true);
1804   void call_VM(Register oop_result,
1805                address entry_point,
1806                Register arg_1, Register arg_2, Register arg_3,
1807                bool check_exceptions = true);
1808 
1809   // Overloadings with last_Java_sp
1810   void call_VM(Register oop_result,
1811                Register last_java_sp,
1812                address entry_point,
1813                int number_of_arguments = 0,
1814                bool check_exceptions = true);
1815   void call_VM(Register oop_result,
1816                Register last_java_sp,
1817                address entry_point,
1818                Register arg_1, bool
1819                check_exceptions = true);
1820   void call_VM(Register oop_result,
1821                Register last_java_sp,
1822                address entry_point,
1823                Register arg_1, Register arg_2,
1824                bool check_exceptions = true);
1825   void call_VM(Register oop_result,
1826                Register last_java_sp,
1827                address entry_point,
1828                Register arg_1, Register arg_2, Register arg_3,
1829                bool check_exceptions = true);
1830 
1831   // These always tightly bind to MacroAssembler::call_VM_base
1832   // bypassing the virtual implementation
1833   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1834   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1835   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1836   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1837   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
1838 
1839   void call_VM_leaf(address entry_point,
1840                     int number_of_arguments = 0);
1841   void call_VM_leaf(address entry_point,
1842                     Register arg_1);
1843   void call_VM_leaf(address entry_point,
1844                     Register arg_1, Register arg_2);
1845   void call_VM_leaf(address entry_point,
1846                     Register arg_1, Register arg_2, Register arg_3);
1847 
1848   // These always tightly bind to MacroAssembler::call_VM_leaf_base
1849   // bypassing the virtual implementation
1850   void super_call_VM_leaf(address entry_point);
1851   void super_call_VM_leaf(address entry_point, Register arg_1);
1852   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
1853   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
1854   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
1855 
1856   // last Java Frame (fills frame anchor)
1857   void set_last_Java_frame(Register thread,
1858                            Register last_java_sp,
1859                            Register last_java_fp,
1860                            address last_java_pc);
1861 
1862   // thread in the default location (r15_thread on 64bit)
1863   void set_last_Java_frame(Register last_java_sp,
1864                            Register last_java_fp,
1865                            address last_java_pc);
1866 
1867   void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1868 
1869   // thread in the default location (r15_thread on 64bit)
1870   void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1871 
1872   // Stores
1873   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
1874   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
1875 
1876 #ifndef SERIALGC
1877 
1878   void g1_write_barrier_pre(Register obj,
1879                             Register pre_val,
1880                             Register thread,
1881                             Register tmp,
1882                             bool tosca_live,
1883                             bool expand_call);
1884 
1885   void g1_write_barrier_post(Register store_addr,
1886                              Register new_val,
1887                              Register thread,
1888                              Register tmp,
1889                              Register tmp2);
1890 
1891 #endif // SERIALGC
1892 
1893   // split store_check(Register obj) to enhance instruction interleaving
1894   void store_check_part_1(Register obj);
1895   void store_check_part_2(Register obj);
1896 
1897   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1898   void c2bool(Register x);
1899 
1900   // C++ bool manipulation
1901 
1902   void movbool(Register dst, Address src);
1903   void movbool(Address dst, bool boolconst);
1904   void movbool(Address dst, Register src);
1905   void testbool(Register dst);
1906 
1907   // oop manipulations
1908   void load_klass(Register dst, Register src);
1909   void store_klass(Register dst, Register src);
1910 
1911   void load_heap_oop(Register dst, Address src);
1912   void load_heap_oop_not_null(Register dst, Address src);
1913   void store_heap_oop(Address dst, Register src);
1914 
1915   // Used for storing NULL. All other oop constants should be
1916   // stored using routines that take a jobject.
1917   void store_heap_oop_null(Address dst);
1918 
1919   void load_prototype_header(Register dst, Register src);
1920 
1921 #ifdef _LP64
1922   void store_klass_gap(Register dst, Register src);
1923 
1924   // This dummy is to prevent a call to store_heap_oop from
1925   // converting a zero (like NULL) into a Register by giving
1926   // the compiler two choices it can't resolve
1927 
1928   void store_heap_oop(Address dst, void* dummy);
1929 
1930   void encode_heap_oop(Register r);
1931   void decode_heap_oop(Register r);
1932   void encode_heap_oop_not_null(Register r);
1933   void decode_heap_oop_not_null(Register r);
1934   void encode_heap_oop_not_null(Register dst, Register src);
1935   void decode_heap_oop_not_null(Register dst, Register src);
1936 
1937   void set_narrow_oop(Register dst, jobject obj);
1938   void set_narrow_oop(Address dst, jobject obj);
1939   void cmp_narrow_oop(Register dst, jobject obj);
1940   void cmp_narrow_oop(Address dst, jobject obj);
1941 
1942   // if heap base register is used - reinit it with the correct value
1943   void reinit_heapbase();
1944 
1945   DEBUG_ONLY(void verify_heapbase(const char* msg);)
1946 
1947 #endif // _LP64
1948 
1949   // Int division/remainder for Java
1950   // (as idivl, but checks for special case as described in JVM spec.)
1951   // returns idivl instruction offset for implicit exception handling
1952   int corrected_idivl(Register reg);
1953 
1954   // Long division/remainder for Java
1955   // (as idivq, but checks for special case as described in JVM spec.)
1956   // returns idivq instruction offset for implicit exception handling
1957   int corrected_idivq(Register reg);
1958 
1959   void int3();
1960 
1961   // Long operation macros for a 32bit cpu
1962   // Long negation for Java
1963   void lneg(Register hi, Register lo);
1964 
1965   // Long multiplication for Java
1966   // (destroys contents of eax, ebx, ecx and edx)
1967   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1968 
1969   // Long shifts for Java
1970   // (semantics as described in JVM spec.)
1971   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
1972   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
1973 
1974   // Long compare for Java
1975   // (semantics as described in JVM spec.)
1976   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1977 
1978 
1979   // misc
1980 
1981   // Sign extension
1982   void sign_extend_short(Register reg);
1983   void sign_extend_byte(Register reg);
1984 
1985   // Division by power of 2, rounding towards 0
1986   void division_with_shift(Register reg, int shift_value);
1987 
1988   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1989   //
1990   // CF (corresponds to C0) if x < y
1991   // PF (corresponds to C2) if unordered
1992   // ZF (corresponds to C3) if x = y
1993   //
1994   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1995   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1996   void fcmp(Register tmp);
1997   // Variant of the above which allows y to be further down the stack
1998   // and which only pops x and y if specified. If pop_right is
1999   // specified then pop_left must also be specified.
2000   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
2001 
2002   // Floating-point comparison for Java
2003   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
2004   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
2005   // (semantics as described in JVM spec.)
2006   void fcmp2int(Register dst, bool unordered_is_less);
2007   // Variant of the above which allows y to be further down the stack
2008   // and which only pops x and y if specified. If pop_right is
2009   // specified then pop_left must also be specified.
2010   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
2011 
2012   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
2013   // tmp is a temporary register, if none is available use noreg
2014   void fremr(Register tmp);
2015 
2016 
2017   // same as fcmp2int, but using SSE2
2018   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
2019   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
2020 
2021   // Inlined sin/cos generator for Java; must not use CPU instruction
2022   // directly on Intel as it does not have high enough precision
2023   // outside of the range [-pi/4, pi/4]. Extra argument indicate the
2024   // number of FPU stack slots in use; all but the topmost will
2025   // require saving if a slow case is necessary. Assumes argument is
2026   // on FP TOS; result is on FP TOS.  No cpu registers are changed by
2027   // this code.
2028   void trigfunc(char trig, int num_fpu_regs_in_use = 1);
2029 
2030   // branch to L if FPU flag C2 is set/not set
2031   // tmp is a temporary register, if none is available use noreg
2032   void jC2 (Register tmp, Label& L);
2033   void jnC2(Register tmp, Label& L);
2034 
2035   // Pop ST (ffree & fincstp combined)
2036   void fpop();
2037 
2038   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2039   void push_fTOS();
2040 
2041   // pops double TOS element from CPU stack and pushes on FPU stack
2042   void pop_fTOS();
2043 
2044   void empty_FPU_stack();
2045 
2046   void push_IU_state();
2047   void pop_IU_state();
2048 
2049   void push_FPU_state();
2050   void pop_FPU_state();
2051 
2052   void push_CPU_state();
2053   void pop_CPU_state();
2054 
2055   // Round up to a power of two
2056   void round_to(Register reg, int modulus);
2057 
2058   // Callee saved registers handling
2059   void push_callee_saved_registers();
2060   void pop_callee_saved_registers();
2061 
2062   // allocation
2063   void eden_allocate(
2064     Register obj,                      // result: pointer to object after successful allocation
2065     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
2066     int      con_size_in_bytes,        // object size in bytes if   known at compile time
2067     Register t1,                       // temp register
2068     Label&   slow_case                 // continuation point if fast allocation fails
2069   );
2070   void tlab_allocate(
2071     Register obj,                      // result: pointer to object after successful allocation
2072     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
2073     int      con_size_in_bytes,        // object size in bytes if   known at compile time
2074     Register t1,                       // temp register
2075     Register t2,                       // temp register
2076     Label&   slow_case                 // continuation point if fast allocation fails
2077   );
2078   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
2079   void incr_allocated_bytes(Register thread,
2080                             Register var_size_in_bytes, int con_size_in_bytes,
2081                             Register t1 = noreg);
2082 
2083   // interface method calling
2084   void lookup_interface_method(Register recv_klass,
2085                                Register intf_klass,
2086                                RegisterOrConstant itable_index,
2087                                Register method_result,
2088                                Register scan_temp,
2089                                Label& no_such_interface);
2090 
2091   // Test sub_klass against super_klass, with fast and slow paths.
2092 
2093   // The fast path produces a tri-state answer: yes / no / maybe-slow.
2094   // One of the three labels can be NULL, meaning take the fall-through.
2095   // If super_check_offset is -1, the value is loaded up from super_klass.
2096   // No registers are killed, except temp_reg.
2097   void check_klass_subtype_fast_path(Register sub_klass,
2098                                      Register super_klass,
2099                                      Register temp_reg,
2100                                      Label* L_success,
2101                                      Label* L_failure,
2102                                      Label* L_slow_path,
2103                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
2104 
2105   // The rest of the type check; must be wired to a corresponding fast path.
2106   // It does not repeat the fast path logic, so don't use it standalone.
2107   // The temp_reg and temp2_reg can be noreg, if no temps are available.
2108   // Updates the sub's secondary super cache as necessary.
2109   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
2110   void check_klass_subtype_slow_path(Register sub_klass,
2111                                      Register super_klass,
2112                                      Register temp_reg,
2113                                      Register temp2_reg,
2114                                      Label* L_success,
2115                                      Label* L_failure,
2116                                      bool set_cond_codes = false);
2117 
2118   // Simplified, combined version, good for typical uses.
2119   // Falls through on failure.
2120   void check_klass_subtype(Register sub_klass,
2121                            Register super_klass,
2122                            Register temp_reg,
2123                            Label& L_success);
2124 
2125   // method handles (JSR 292)
2126   void check_method_handle_type(Register mtype_reg, Register mh_reg,
2127                                 Register temp_reg,
2128                                 Label& wrong_method_type);
2129   void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
2130                                   Register temp_reg);
2131   void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
2132   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
2133 
2134 
2135   //----
2136   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
2137 
2138   // Debugging
2139 
2140   // only if +VerifyOops
2141   void verify_oop(Register reg, const char* s = "broken oop");
2142   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
2143 
2144   // only if +VerifyFPU
2145   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2146 
2147   // prints msg, dumps registers and stops execution
2148   void stop(const char* msg);
2149 
2150   // prints msg and continues
2151   void warn(const char* msg);
2152 
2153   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
2154   static void debug64(char* msg, int64_t pc, int64_t regs[]);
2155 
2156   void os_breakpoint();
2157 
2158   void untested()                                { stop("untested"); }
2159 
2160   void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
2161 
2162   void should_not_reach_here()                   { stop("should not reach here"); }
2163 
2164   void print_CPU_state();
2165 
2166   // Stack overflow checking
2167   void bang_stack_with_offset(int offset) {
2168     // stack grows down, caller passes positive offset
2169     assert(offset > 0, "must bang with negative offset");
2170     movl(Address(rsp, (-offset)), rax);
2171   }
2172 
2173   // Writes to stack successive pages until offset reached to check for
2174   // stack overflow + shadow pages.  Also, clobbers tmp
2175   void bang_stack_size(Register size, Register tmp);
2176 
2177   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2178                                                 Register tmp,
2179                                                 int offset);
2180 
2181   // Support for serializing memory accesses between threads
2182   void serialize_memory(Register thread, Register tmp);
2183 
2184   void verify_tlab();
2185 
2186   // Biased locking support
2187   // lock_reg and obj_reg must be loaded up with the appropriate values.
2188   // swap_reg must be rax, and is killed.
2189   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
2190   // be killed; if not supplied, push/pop will be used internally to
2191   // allocate a temporary (inefficient, avoid if possible).
2192   // Optional slow case is for implementations (interpreter and C1) which branch to
2193   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
2194   // Returns offset of first potentially-faulting instruction for null
2195   // check info (currently consumed only by C1). If
2196   // swap_reg_contains_mark is true then returns -1 as it is assumed
2197   // the calling code has already passed any potential faults.
2198   int biased_locking_enter(Register lock_reg, Register obj_reg,
2199                            Register swap_reg, Register tmp_reg,
2200                            bool swap_reg_contains_mark,
2201                            Label& done, Label* slow_case = NULL,
2202                            BiasedLockingCounters* counters = NULL);
2203   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
2204 
2205 
2206   Condition negate_condition(Condition cond);
2207 
2208   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
2209   // operands. In general the names are modified to avoid hiding the instruction in Assembler
2210   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
2211   // here in MacroAssembler. The major exception to this rule is call
2212 
2213   // Arithmetics
2214 
2215 
2216   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
2217   void addptr(Address dst, Register src);
2218 
2219   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
2220   void addptr(Register dst, int32_t src);
2221   void addptr(Register dst, Register src);
2222   void addptr(Register dst, RegisterOrConstant src) {
2223     if (src.is_constant()) addptr(dst, (int) src.as_constant());
2224     else                   addptr(dst,       src.as_register());
2225   }
2226 
2227   void andptr(Register dst, int32_t src);
2228   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
2229 
2230   void cmp8(AddressLiteral src1, int imm);
2231 
2232   // renamed to drag out the casting of address to int32_t/intptr_t
2233   void cmp32(Register src1, int32_t imm);
2234 
2235   void cmp32(AddressLiteral src1, int32_t imm);
2236   // compare reg - mem, or reg - &mem
2237   void cmp32(Register src1, AddressLiteral src2);
2238 
2239   void cmp32(Register src1, Address src2);
2240 
2241 #ifndef _LP64
2242   void cmpoop(Address dst, jobject obj);
2243   void cmpoop(Register dst, jobject obj);
2244 #endif // _LP64
2245 
2246   // NOTE src2 must be the lval. This is NOT an mem-mem compare
2247   void cmpptr(Address src1, AddressLiteral src2);
2248 
2249   void cmpptr(Register src1, AddressLiteral src2);
2250 
2251   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2252   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2253   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2254 
2255   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2256   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2257 
2258   // cmp64 to avoild hiding cmpq
2259   void cmp64(Register src1, AddressLiteral src);
2260 
2261   void cmpxchgptr(Register reg, Address adr);
2262 
2263   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2264 
2265 
2266   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2267 
2268 
2269   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2270 
2271   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2272 
2273   void shlptr(Register dst, int32_t shift);
2274   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2275 
2276   void shrptr(Register dst, int32_t shift);
2277   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2278 
2279   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2280   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2281 
2282   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2283 
2284   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2285   void subptr(Register dst, int32_t src);
2286   // Force generation of a 4 byte immediate value even if it fits into 8bit
2287   void subptr_imm32(Register dst, int32_t src);
2288   void subptr(Register dst, Register src);
2289   void subptr(Register dst, RegisterOrConstant src) {
2290     if (src.is_constant()) subptr(dst, (int) src.as_constant());
2291     else                   subptr(dst,       src.as_register());
2292   }
2293 
2294   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2295   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2296 
2297   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2298   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2299 
2300   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2301 
2302 
2303 
2304   // Helper functions for statistics gathering.
2305   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2306   void cond_inc32(Condition cond, AddressLiteral counter_addr);
2307   // Unconditional atomic increment.
2308   void atomic_incl(AddressLiteral counter_addr);
2309 
2310   void lea(Register dst, AddressLiteral adr);
2311   void lea(Address dst, AddressLiteral adr);
2312   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2313 
2314   void leal32(Register dst, Address src) { leal(dst, src); }
2315 
2316   // Import other testl() methods from the parent class or else
2317   // they will be hidden by the following overriding declaration.
2318   using Assembler::testl;
2319   void testl(Register dst, AddressLiteral src);
2320 
2321   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2322   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2323   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2324 
2325   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2326   void testptr(Register src1, Register src2);
2327 
2328   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2329   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2330 
2331   // Calls
2332 
2333   void call(Label& L, relocInfo::relocType rtype);
2334   void call(Register entry);
2335 
2336   // NOTE: this call tranfers to the effective address of entry NOT
2337   // the address contained by entry. This is because this is more natural
2338   // for jumps/calls.
2339   void call(AddressLiteral entry);
2340 
2341   // Jumps
2342 
2343   // NOTE: these jumps tranfer to the effective address of dst NOT
2344   // the address contained by dst. This is because this is more natural
2345   // for jumps/calls.
2346   void jump(AddressLiteral dst);
2347   void jump_cc(Condition cc, AddressLiteral dst);
2348 
2349   // 32bit can do a case table jump in one instruction but we no longer allow the base
2350   // to be installed in the Address class. This jump will tranfers to the address
2351   // contained in the location described by entry (not the address of entry)
2352   void jump(ArrayAddress entry);
2353 
2354   // Floating
2355 
2356   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2357   void andpd(XMMRegister dst, AddressLiteral src);
2358 
2359   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
2360   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
2361   void andps(XMMRegister dst, AddressLiteral src);
2362 
2363   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
2364   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2365   void comiss(XMMRegister dst, AddressLiteral src);
2366 
2367   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
2368   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2369   void comisd(XMMRegister dst, AddressLiteral src);
2370 
2371   void fadd_s(Address src)        { Assembler::fadd_s(src); }
2372   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
2373 
2374   void fldcw(Address src) { Assembler::fldcw(src); }
2375   void fldcw(AddressLiteral src);
2376 
2377   void fld_s(int index)   { Assembler::fld_s(index); }
2378   void fld_s(Address src) { Assembler::fld_s(src); }
2379   void fld_s(AddressLiteral src);
2380 
2381   void fld_d(Address src) { Assembler::fld_d(src); }
2382   void fld_d(AddressLiteral src);
2383 
2384   void fld_x(Address src) { Assembler::fld_x(src); }
2385   void fld_x(AddressLiteral src);
2386 
2387   void fmul_s(Address src)        { Assembler::fmul_s(src); }
2388   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
2389 
2390   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2391   void ldmxcsr(AddressLiteral src);
2392 
2393   // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
2394   // all corner cases and may result in NaN and require fallback to a
2395   // runtime call.
2396   void fast_pow();
2397   void fast_exp();
2398   void increase_precision();
2399   void restore_precision();
2400 
2401   // computes exp(x). Fallback to runtime call included.
2402   void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
2403   // computes pow(x,y). Fallback to runtime call included.
2404   void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
2405 
2406 private:
2407 
2408   // call runtime as a fallback for trig functions and pow/exp.
2409   void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
2410 
2411   // computes 2^(Ylog2X); Ylog2X in ST(0)
2412   void pow_exp_core_encoding();
2413 
2414   // computes pow(x,y) or exp(x). Fallback to runtime call included.
2415   void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
2416 
2417   // these are private because users should be doing movflt/movdbl
2418 
2419   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
2420   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2421   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
2422   void movss(XMMRegister dst, AddressLiteral src);
2423 
2424   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
2425   void movlpd(XMMRegister dst, AddressLiteral src);
2426 
2427 public:
2428 
2429   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
2430   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
2431   void addsd(XMMRegister dst, AddressLiteral src);
2432 
2433   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
2434   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
2435   void addss(XMMRegister dst, AddressLiteral src);
2436 
2437   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
2438   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
2439   void divsd(XMMRegister dst, AddressLiteral src);
2440 
2441   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
2442   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
2443   void divss(XMMRegister dst, AddressLiteral src);
2444 
2445   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2446   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
2447   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
2448   void movsd(XMMRegister dst, AddressLiteral src);
2449 
2450   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
2451   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
2452   void mulsd(XMMRegister dst, AddressLiteral src);
2453 
2454   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
2455   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
2456   void mulss(XMMRegister dst, AddressLiteral src);
2457 
2458   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
2459   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
2460   void sqrtsd(XMMRegister dst, AddressLiteral src);
2461 
2462   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
2463   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
2464   void sqrtss(XMMRegister dst, AddressLiteral src);
2465 
2466   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
2467   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
2468   void subsd(XMMRegister dst, AddressLiteral src);
2469 
2470   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
2471   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
2472   void subss(XMMRegister dst, AddressLiteral src);
2473 
2474   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2475   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
2476   void ucomiss(XMMRegister dst, AddressLiteral src);
2477 
2478   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2479   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
2480   void ucomisd(XMMRegister dst, AddressLiteral src);
2481 
2482   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2483   void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2484   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
2485   void xorpd(XMMRegister dst, AddressLiteral src);
2486 
2487   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2488   void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2489   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
2490   void xorps(XMMRegister dst, AddressLiteral src);
2491 
2492   // AVX 3-operands instructions
2493 
2494   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
2495   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
2496   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2497 
2498   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
2499   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
2500   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2501 
2502   void vandpd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vandpd(dst, nds, src); }
2503   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2504 
2505   void vandps(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vandps(dst, nds, src); }
2506   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2507 
2508   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
2509   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
2510   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2511 
2512   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
2513   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
2514   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2515 
2516   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
2517   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
2518   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2519 
2520   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
2521   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
2522   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2523 
2524   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
2525   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
2526   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2527 
2528   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
2529   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
2530   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2531 
2532   void vxorpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorpd(dst, nds, src); }
2533   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2534 
2535   void vxorps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorps(dst, nds, src); }
2536   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2537 
2538 
2539   // Data
2540 
2541   void cmov32( Condition cc, Register dst, Address  src);
2542   void cmov32( Condition cc, Register dst, Register src);
2543 
2544   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2545 
2546   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2547   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2548 
2549   void movoop(Register dst, jobject obj);
2550   void movoop(Address dst, jobject obj);
2551 
2552   void movptr(ArrayAddress dst, Register src);
2553   // can this do an lea?
2554   void movptr(Register dst, ArrayAddress src);
2555 
2556   void movptr(Register dst, Address src);
2557 
2558   void movptr(Register dst, AddressLiteral src);
2559 
2560   void movptr(Register dst, intptr_t src);
2561   void movptr(Register dst, Register src);
2562   void movptr(Address dst, intptr_t src);
2563 
2564   void movptr(Address dst, Register src);
2565 
2566   void movptr(Register dst, RegisterOrConstant src) {
2567     if (src.is_constant()) movptr(dst, src.as_constant());
2568     else                   movptr(dst, src.as_register());
2569   }
2570 
2571 #ifdef _LP64
2572   // Generally the next two are only used for moving NULL
2573   // Although there are situations in initializing the mark word where
2574   // they could be used. They are dangerous.
2575 
2576   // They only exist on LP64 so that int32_t and intptr_t are not the same
2577   // and we have ambiguous declarations.
2578 
2579   void movptr(Address dst, int32_t imm32);
2580   void movptr(Register dst, int32_t imm32);
2581 #endif // _LP64
2582 
2583   // to avoid hiding movl
2584   void mov32(AddressLiteral dst, Register src);
2585   void mov32(Register dst, AddressLiteral src);
2586 
2587   // to avoid hiding movb
2588   void movbyte(ArrayAddress dst, int src);
2589 
2590   // Can push value or effective address
2591   void pushptr(AddressLiteral src);
2592 
2593   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2594   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2595 
2596   void pushoop(jobject obj);
2597 
2598   // sign extend as need a l to ptr sized element
2599   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2600   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2601 
2602   // C2 compiled method's prolog code.
2603   void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b);
2604 
2605   // IndexOf strings.
2606   // Small strings are loaded through stack if they cross page boundary.
2607   void string_indexof(Register str1, Register str2,
2608                       Register cnt1, Register cnt2,
2609                       int int_cnt2,  Register result,
2610                       XMMRegister vec, Register tmp);
2611 
2612   // IndexOf for constant substrings with size >= 8 elements
2613   // which don't need to be loaded through stack.
2614   void string_indexofC8(Register str1, Register str2,
2615                       Register cnt1, Register cnt2,
2616                       int int_cnt2,  Register result,
2617                       XMMRegister vec, Register tmp);
2618 
2619     // Smallest code: we don't need to load through stack,
2620     // check string tail.
2621 
2622   // Compare strings.
2623   void string_compare(Register str1, Register str2,
2624                       Register cnt1, Register cnt2, Register result,
2625                       XMMRegister vec1);
2626 
2627   // Compare char[] arrays.
2628   void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2629                           Register limit, Register result, Register chr,
2630                           XMMRegister vec1, XMMRegister vec2);
2631 
2632   // Fill primitive arrays
2633   void generate_fill(BasicType t, bool aligned,
2634                      Register to, Register value, Register count,
2635                      Register rtmp, XMMRegister xtmp);
2636 
2637 #undef VIRTUAL
2638 
2639 };
2640 
2641 /**
2642  * class SkipIfEqual:
2643  *
2644  * Instantiating this class will result in assembly code being output that will
2645  * jump around any code emitted between the creation of the instance and it's
2646  * automatic destruction at the end of a scope block, depending on the value of
2647  * the flag passed to the constructor, which will be checked at run-time.
2648  */
2649 class SkipIfEqual {
2650  private:
2651   MacroAssembler* _masm;
2652   Label _label;
2653 
2654  public:
2655    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2656    ~SkipIfEqual();
2657 };
2658 
2659 #ifdef ASSERT
2660 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2661 #endif
2662 
2663 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP