hotspot Sdiff src/cpu/sparc/vm

src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
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src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

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rev 5240 : 8023657: New type profiling points: arguments to call
Summary: x86 interpreter and c1 type profiling for arguments at calls
Reviewed-by:

3083     } else {
3084       __ load_klass(recv, recv);
3085       Label update_done;
3086       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
3087       // Receiver did not match any saved receiver and there is no empty row for it.
3088       // Increment total counter to indicate polymorphic case.
3089       __ ld_ptr(counter_addr, tmp1);
3090       __ add(tmp1, DataLayout::counter_increment, tmp1);
3091       __ st_ptr(tmp1, counter_addr);
3092 
3093       __ bind(update_done);
3094     }
3095   } else {
3096     // Static call
3097     __ ld_ptr(counter_addr, tmp1);
3098     __ add(tmp1, DataLayout::counter_increment, tmp1);
3099     __ st_ptr(tmp1, counter_addr);
3100   }
3101 }
3102 




3103 void LIR_Assembler::align_backward_branch_target() {
3104   __ align(OptoLoopAlignment);
3105 }
3106 
3107 
3108 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
3109   // make sure we are expecting a delay
3110   // this has the side effect of clearing the delay state
3111   // so we can use _masm instead of _masm->delayed() to do the
3112   // code generation.
3113   __ delayed();
3114 
3115   // make sure we only emit one instruction
3116   int offset = code_offset();
3117   op->delay_op()->emit_code(this);
3118 #ifdef ASSERT
3119   if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3120     op->delay_op()->print();
3121   }
3122   assert(code_offset() - offset == NativeInstruction::nop_instruction_size,

3083     } else {
3084       __ load_klass(recv, recv);
3085       Label update_done;
3086       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
3087       // Receiver did not match any saved receiver and there is no empty row for it.
3088       // Increment total counter to indicate polymorphic case.
3089       __ ld_ptr(counter_addr, tmp1);
3090       __ add(tmp1, DataLayout::counter_increment, tmp1);
3091       __ st_ptr(tmp1, counter_addr);
3092 
3093       __ bind(update_done);
3094     }
3095   } else {
3096     // Static call
3097     __ ld_ptr(counter_addr, tmp1);
3098     __ add(tmp1, DataLayout::counter_increment, tmp1);
3099     __ st_ptr(tmp1, counter_addr);
3100   }
3101 }
3102 
3103 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3104   fatal("Type profiling not implemented on this platform");
3105 }
3106 
3107 void LIR_Assembler::align_backward_branch_target() {
3108   __ align(OptoLoopAlignment);
3109 }
3110 
3111 
3112 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
3113   // make sure we are expecting a delay
3114   // this has the side effect of clearing the delay state
3115   // so we can use _masm instead of _masm->delayed() to do the
3116   // code generation.
3117   __ delayed();
3118 
3119   // make sure we only emit one instruction
3120   int offset = code_offset();
3121   op->delay_op()->emit_code(this);
3122 #ifdef ASSERT
3123   if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
3124     op->delay_op()->print();
3125   }
3126   assert(code_offset() - offset == NativeInstruction::nop_instruction_size,

src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp
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