1 // 2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 // or visit www.oracle.com if you need additional information or have any 21 // questions. 22 // 23 // 24 25 // SPARC Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 register %{ 32 //----------Architecture Description Register Definitions---------------------- 33 // General Registers 34 // "reg_def" name ( register save type, C convention save type, 35 // ideal register type, encoding, vm name ); 36 // Register Save Types: 37 // 38 // NS = No-Save: The register allocator assumes that these registers 39 // can be used without saving upon entry to the method, & 40 // that they do not need to be saved at call sites. 41 // 42 // SOC = Save-On-Call: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, 44 // but that they must be saved at call sites. 45 // 46 // SOE = Save-On-Entry: The register allocator assumes that these registers 47 // must be saved before using them upon entry to the 48 // method, but they do not need to be saved at call 49 // sites. 50 // 51 // AS = Always-Save: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, & that they must be saved at call sites. 54 // 55 // Ideal Register Type is used to determine how to save & restore a 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58 // 59 // The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62 // ---------------------------- 63 // Integer/Long Registers 64 // ---------------------------- 65 66 // Need to expose the hi/lo aspect of 64-bit registers 67 // This register set is used for both the 64-bit build and 68 // the 32-bit build with 1-register longs. 69 70 // Global Registers 0-7 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88 // Output Registers 0-7 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106 // Local Registers 0-7 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124 // Input Registers 0-7 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142 // ---------------------------- 143 // Float/Double Registers 144 // ---------------------------- 145 146 // Float Registers 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180 // Double Registers 181 // The rules of ADL require that double registers be defined in pairs. 182 // Each pair must be two 32-bit values, but not necessarily a pair of 183 // single float registers. In each pair, ADLC-assigned register numbers 184 // must be adjacent, with the lower number even. Finally, when the 185 // CPU stores such a register pair to memory, the word associated with 186 // the lower ADLC-assigned number must be stored to the lower address. 187 188 // These definitions specify the actual bit encodings of the sparc 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190 // wants 0-63, so we have to convert every time we want to use fp regs 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192 // 255 is a flag meaning "don't go here". 193 // I believe we can't handle callee-save doubles D32 and up until 194 // the place in the sparc stack crawler that asserts on the 255 is 195 // fixed up. 196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230 // ---------------------------- 231 // Special Registers 232 // Condition Codes Flag Registers 233 // I tried to break out ICC and XCC but it's not very pretty. 234 // Every Sparc instruction which defs/kills one also kills the other. 235 // Hence every compare instruction which defs one kind of flags ends 236 // up needing a kill of the other. 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244 // ---------------------------- 245 // Specify the enum values for the registers. These enums are only used by the 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed 247 // for visibility to the rest of the vm. The order of this enum influences the 248 // register allocator so having the freedom to set this order and not be stuck 249 // with the order that is natural for the rest of the vm is worth it. 250 alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256 // Note that a register is not allocatable unless it is also mentioned 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259 alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277 //----------Architecture Description Register Classes-------------------------- 278 // Several register classes are automatically defined based upon information in 279 // this architecture description. 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283 // 284 285 // G0 is not included in integer class since it has special meaning. 286 reg_class g0_reg(R_G0); 287 288 // ---------------------------- 289 // Integer Register Classes 290 // ---------------------------- 291 // Exclusions from i_reg: 292 // R_G0: hardwired zero 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294 // R_G6: reserved by Solaris ABI to tools 295 // R_G7: reserved by Solaris ABI to libthread 296 // R_O7: Used as a temp in many encodings 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299 // Class for all integer registers, except the G registers. This is used for 300 // encodings which use G registers as temps. The regular inputs to such 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302 // will not put an input into a temp register. 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305 reg_class g1_regI(R_G1); 306 reg_class g3_regI(R_G3); 307 reg_class g4_regI(R_G4); 308 reg_class o0_regI(R_O0); 309 reg_class o7_regI(R_O7); 310 311 // ---------------------------- 312 // Pointer Register Classes 313 // ---------------------------- 314 #ifdef _LP64 315 // 64-bit build means 64-bit pointers means hi/lo pairs 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 320 // Lock encodings use G3 and G4 internally 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 325 // Special class for storeP instructions, which can store SP or RPC to TLS. 326 // It is also used for memory addressing, allowing direct TLS addressing. 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register 332 // We use it to save R_G2 across calls out of Java. 333 reg_class l7_regP(R_L7H,R_L7); 334 335 // Other special pointer regs 336 reg_class g1_regP(R_G1H,R_G1); 337 reg_class g2_regP(R_G2H,R_G2); 338 reg_class g3_regP(R_G3H,R_G3); 339 reg_class g4_regP(R_G4H,R_G4); 340 reg_class g5_regP(R_G5H,R_G5); 341 reg_class i0_regP(R_I0H,R_I0); 342 reg_class o0_regP(R_O0H,R_O0); 343 reg_class o1_regP(R_O1H,R_O1); 344 reg_class o2_regP(R_O2H,R_O2); 345 reg_class o7_regP(R_O7H,R_O7); 346 347 #else // _LP64 348 // 32-bit build means 32-bit pointers means 1 register. 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 353 // Lock encodings use G3 and G4 internally 354 reg_class lock_ptr_reg(R_G1, R_G5, 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 358 // Special class for storeP instructions, which can store SP or RPC to TLS. 359 // It is also used for memory addressing, allowing direct TLS addressing. 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register 365 // We use it to save R_G2 across calls out of Java. 366 reg_class l7_regP(R_L7); 367 368 // Other special pointer regs 369 reg_class g1_regP(R_G1); 370 reg_class g2_regP(R_G2); 371 reg_class g3_regP(R_G3); 372 reg_class g4_regP(R_G4); 373 reg_class g5_regP(R_G5); 374 reg_class i0_regP(R_I0); 375 reg_class o0_regP(R_O0); 376 reg_class o1_regP(R_O1); 377 reg_class o2_regP(R_O2); 378 reg_class o7_regP(R_O7); 379 #endif // _LP64 380 381 382 // ---------------------------- 383 // Long Register Classes 384 // ---------------------------- 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 389 #ifdef _LP64 390 // 64-bit, longs in 1 register: use all 64-bit integer registers 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 394 #endif // _LP64 395 ); 396 397 reg_class g1_regL(R_G1H,R_G1); 398 reg_class g3_regL(R_G3H,R_G3); 399 reg_class o2_regL(R_O2H,R_O2); 400 reg_class o7_regL(R_O7H,R_O7); 401 402 // ---------------------------- 403 // Special Class for Condition Code Flags Register 404 reg_class int_flags(CCR); 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 406 reg_class float_flag0(FCC0); 407 408 409 // ---------------------------- 410 // Float Point Register Classes 411 // ---------------------------- 412 // Skip F30/F31, they are reserved for mem-mem copies 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 414 415 // Paired floating point registers--they show up in the same order as the floats, 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 419 /* Use extra V9 double registers; this AD file does not support V8 */ 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 422 ); 423 424 // Paired floating point registers--they show up in the same order as the floats, 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 426 // This class is usable for mis-aligned loads as happen in I2C adapters. 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 429 %} 430 431 //----------DEFINITION BLOCK--------------------------------------------------- 432 // Define name --> value mappings to inform the ADLC of an integer valued name 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] 434 // Format: 435 // int_def <name> ( <int_value>, <expression>); 436 // Generated Code in ad_<arch>.hpp 437 // #define <name> (<expression>) 438 // // value == <int_value> 439 // Generated code in ad_<arch>.cpp adlc_verification() 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 441 // 442 definitions %{ 443 // The default cost (of an ALU instruction). 444 int_def DEFAULT_COST ( 100, 100); 445 int_def HUGE_COST (1000000, 1000000); 446 447 // Memory refs are twice as expensive as run-of-the-mill. 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 449 450 // Branches are even more expensive. 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); 453 %} 454 455 456 //----------SOURCE BLOCK------------------------------------------------------- 457 // This is a block of C++ code which provides values, functions, and 458 // definitions necessary in the rest of the architecture description 459 source_hpp %{ 460 // Must be visible to the DFA in dfa_sparc.cpp 461 extern bool can_branch_register( Node *bol, Node *cmp ); 462 463 extern bool use_block_zeroing(Node* count); 464 465 // Macros to extract hi & lo halves from a long pair. 466 // G0 is not part of any long pair, so assert on that. 467 // Prevents accidentally using G1 instead of G0. 468 #define LONG_HI_REG(x) (x) 469 #define LONG_LO_REG(x) (x) 470 471 %} 472 473 source %{ 474 #define __ _masm. 475 476 // tertiary op of a LoadP or StoreP encoding 477 #define REGP_OP true 478 479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 481 static Register reg_to_register_object(int register_encoding); 482 483 // Used by the DFA in dfa_sparc.cpp. 484 // Check for being able to use a V9 branch-on-register. Requires a 485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 486 // extended. Doesn't work following an integer ADD, for example, because of 487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On 488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 489 // replace them with zero, which could become sign-extension in a different OS 490 // release. There's no obvious reason why an interrupt will ever fill these 491 // bits with non-zero junk (the registers are reloaded with standard LD 492 // instructions which either zero-fill or sign-fill). 493 bool can_branch_register( Node *bol, Node *cmp ) { 494 if( !BranchOnRegister ) return false; 495 #ifdef _LP64 496 if( cmp->Opcode() == Op_CmpP ) 497 return true; // No problems with pointer compares 498 #endif 499 if( cmp->Opcode() == Op_CmpL ) 500 return true; // No problems with long compares 501 502 if( !SparcV9RegsHiBitsZero ) return false; 503 if( bol->as_Bool()->_test._test != BoolTest::ne && 504 bol->as_Bool()->_test._test != BoolTest::eq ) 505 return false; 506 507 // Check for comparing against a 'safe' value. Any operation which 508 // clears out the high word is safe. Thus, loads and certain shifts 509 // are safe, as are non-negative constants. Any operation which 510 // preserves zero bits in the high word is safe as long as each of its 511 // inputs are safe. Thus, phis and bitwise booleans are safe if their 512 // inputs are safe. At present, the only important case to recognize 513 // seems to be loads. Constants should fold away, and shifts & 514 // logicals can use the 'cc' forms. 515 Node *x = cmp->in(1); 516 if( x->is_Load() ) return true; 517 if( x->is_Phi() ) { 518 for( uint i = 1; i < x->req(); i++ ) 519 if( !x->in(i)->is_Load() ) 520 return false; 521 return true; 522 } 523 return false; 524 } 525 526 bool use_block_zeroing(Node* count) { 527 // Use BIS for zeroing if count is not constant 528 // or it is >= BlockZeroingLowLimit. 529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); 530 } 531 532 // **************************************************************************** 533 534 // REQUIRED FUNCTIONALITY 535 536 // !!!!! Special hack to get all type of calls to specify the byte offset 537 // from the start of the call to the point where the return address 538 // will point. 539 // The "return address" is the address of the call instruction, plus 8. 540 541 int MachCallStaticJavaNode::ret_addr_offset() { 542 int offset = NativeCall::instruction_size; // call; delay slot 543 if (_method_handle_invoke) 544 offset += 4; // restore SP 545 return offset; 546 } 547 548 int MachCallDynamicJavaNode::ret_addr_offset() { 549 int vtable_index = this->_vtable_index; 550 if (vtable_index < 0) { 551 // must be invalid_vtable_index, not nonvirtual_vtable_index 552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 553 return (NativeMovConstReg::instruction_size + 554 NativeCall::instruction_size); // sethi; setlo; call; delay slot 555 } else { 556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 559 int klass_load_size; 560 if (UseCompressedClassPointers) { 561 assert(Universe::heap() != NULL, "java heap should be initialized"); 562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 563 } else { 564 klass_load_size = 1*BytesPerInstWord; 565 } 566 if (Assembler::is_simm13(v_off)) { 567 return klass_load_size + 568 (2*BytesPerInstWord + // ld_ptr, ld_ptr 569 NativeCall::instruction_size); // call; delay slot 570 } else { 571 return klass_load_size + 572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 573 NativeCall::instruction_size); // call; delay slot 574 } 575 } 576 } 577 578 int MachCallRuntimeNode::ret_addr_offset() { 579 #ifdef _LP64 580 if (MacroAssembler::is_far_target(entry_point())) { 581 return NativeFarCall::instruction_size; 582 } else { 583 return NativeCall::instruction_size; 584 } 585 #else 586 return NativeCall::instruction_size; // call; delay slot 587 #endif 588 } 589 590 // Indicate if the safepoint node needs the polling page as an input. 591 // Since Sparc does not have absolute addressing, it does. 592 bool SafePointNode::needs_polling_address_input() { 593 return true; 594 } 595 596 // emit an interrupt that is caught by the debugger (for debugging compiler) 597 void emit_break(CodeBuffer &cbuf) { 598 MacroAssembler _masm(&cbuf); 599 __ breakpoint_trap(); 600 } 601 602 #ifndef PRODUCT 603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 604 st->print("TA"); 605 } 606 #endif 607 608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 609 emit_break(cbuf); 610 } 611 612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 613 return MachNode::size(ra_); 614 } 615 616 // Traceable jump 617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 618 MacroAssembler _masm(&cbuf); 619 Register rdest = reg_to_register_object(jump_target); 620 __ JMP(rdest, 0); 621 __ delayed()->nop(); 622 } 623 624 // Traceable jump and set exception pc 625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 626 MacroAssembler _masm(&cbuf); 627 Register rdest = reg_to_register_object(jump_target); 628 __ JMP(rdest, 0); 629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 630 } 631 632 void emit_nop(CodeBuffer &cbuf) { 633 MacroAssembler _masm(&cbuf); 634 __ nop(); 635 } 636 637 void emit_illtrap(CodeBuffer &cbuf) { 638 MacroAssembler _masm(&cbuf); 639 __ illtrap(0); 640 } 641 642 643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 644 assert(n->rule() != loadUB_rule, ""); 645 646 intptr_t offset = 0; 647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 648 const Node* addr = n->get_base_and_disp(offset, adr_type); 649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 650 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 651 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 652 atype = atype->add_offset(offset); 653 assert(disp32 == offset, "wrong disp32"); 654 return atype->_offset; 655 } 656 657 658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 659 assert(n->rule() != loadUB_rule, ""); 660 661 intptr_t offset = 0; 662 Node* addr = n->in(2); 663 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 665 Node* a = addr->in(2/*AddPNode::Address*/); 666 Node* o = addr->in(3/*AddPNode::Offset*/); 667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 668 atype = a->bottom_type()->is_ptr()->add_offset(offset); 669 assert(atype->isa_oop_ptr(), "still an oop"); 670 } 671 offset = atype->is_ptr()->_offset; 672 if (offset != Type::OffsetBot) offset += disp32; 673 return offset; 674 } 675 676 static inline jdouble replicate_immI(int con, int count, int width) { 677 // Load a constant replicated "count" times with width "width" 678 assert(count*width == 8 && width <= 4, "sanity"); 679 int bit_width = width * 8; 680 jlong val = con; 681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits 682 for (int i = 0; i < count - 1; i++) { 683 val |= (val << bit_width); 684 } 685 jdouble dval = *((jdouble*) &val); // coerce to double type 686 return dval; 687 } 688 689 static inline jdouble replicate_immF(float con) { 690 // Replicate float con 2 times and pack into vector. 691 int val = *((int*)&con); 692 jlong lval = val; 693 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 694 jdouble dval = *((jdouble*) &lval); // coerce to double type 695 return dval; 696 } 697 698 // Standard Sparc opcode form2 field breakdown 699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 700 f0 &= (1<<19)-1; // Mask displacement to 19 bits 701 int op = (f30 << 30) | 702 (f29 << 29) | 703 (f25 << 25) | 704 (f22 << 22) | 705 (f20 << 20) | 706 (f19 << 19) | 707 (f0 << 0); 708 cbuf.insts()->emit_int32(op); 709 } 710 711 // Standard Sparc opcode form2 field breakdown 712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 713 f0 >>= 10; // Drop 10 bits 714 f0 &= (1<<22)-1; // Mask displacement to 22 bits 715 int op = (f30 << 30) | 716 (f25 << 25) | 717 (f22 << 22) | 718 (f0 << 0); 719 cbuf.insts()->emit_int32(op); 720 } 721 722 // Standard Sparc opcode form3 field breakdown 723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 724 int op = (f30 << 30) | 725 (f25 << 25) | 726 (f19 << 19) | 727 (f14 << 14) | 728 (f5 << 5) | 729 (f0 << 0); 730 cbuf.insts()->emit_int32(op); 731 } 732 733 // Standard Sparc opcode form3 field breakdown 734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 735 simm13 &= (1<<13)-1; // Mask to 13 bits 736 int op = (f30 << 30) | 737 (f25 << 25) | 738 (f19 << 19) | 739 (f14 << 14) | 740 (1 << 13) | // bit to indicate immediate-mode 741 (simm13<<0); 742 cbuf.insts()->emit_int32(op); 743 } 744 745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 746 simm10 &= (1<<10)-1; // Mask to 10 bits 747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 748 } 749 750 #ifdef ASSERT 751 // Helper function for VerifyOops in emit_form3_mem_reg 752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 753 warning("VerifyOops encountered unexpected instruction:"); 754 n->dump(2); 755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 756 } 757 #endif 758 759 760 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, 761 int src1_enc, int disp32, int src2_enc, int dst_enc) { 762 763 #ifdef ASSERT 764 // The following code implements the +VerifyOops feature. 765 // It verifies oop values which are loaded into or stored out of 766 // the current method activation. +VerifyOops complements techniques 767 // like ScavengeALot, because it eagerly inspects oops in transit, 768 // as they enter or leave the stack, as opposed to ScavengeALot, 769 // which inspects oops "at rest", in the stack or heap, at safepoints. 770 // For this reason, +VerifyOops can sometimes detect bugs very close 771 // to their point of creation. It can also serve as a cross-check 772 // on the validity of oop maps, when used toegether with ScavengeALot. 773 774 // It would be good to verify oops at other points, especially 775 // when an oop is used as a base pointer for a load or store. 776 // This is presently difficult, because it is hard to know when 777 // a base address is biased or not. (If we had such information, 778 // it would be easy and useful to make a two-argument version of 779 // verify_oop which unbiases the base, and performs verification.) 780 781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 782 bool is_verified_oop_base = false; 783 bool is_verified_oop_load = false; 784 bool is_verified_oop_store = false; 785 int tmp_enc = -1; 786 if (VerifyOops && src1_enc != R_SP_enc) { 787 // classify the op, mainly for an assert check 788 int st_op = 0, ld_op = 0; 789 switch (primary) { 790 case Assembler::stb_op3: st_op = Op_StoreB; break; 791 case Assembler::sth_op3: st_op = Op_StoreC; break; 792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 793 case Assembler::stw_op3: st_op = Op_StoreI; break; 794 case Assembler::std_op3: st_op = Op_StoreL; break; 795 case Assembler::stf_op3: st_op = Op_StoreF; break; 796 case Assembler::stdf_op3: st_op = Op_StoreD; break; 797 798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; 800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 802 case Assembler::ldx_op3: // may become LoadP or stay LoadI 803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 804 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 805 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 806 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 807 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 809 810 default: ShouldNotReachHere(); 811 } 812 if (tertiary == REGP_OP) { 813 if (st_op == Op_StoreI) st_op = Op_StoreP; 814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 815 else ShouldNotReachHere(); 816 if (st_op) { 817 // a store 818 // inputs are (0:control, 1:memory, 2:address, 3:value) 819 Node* n2 = n->in(3); 820 if (n2 != NULL) { 821 const Type* t = n2->bottom_type(); 822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 823 } 824 } else { 825 // a load 826 const Type* t = n->bottom_type(); 827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 828 } 829 } 830 831 if (ld_op) { 832 // a Load 833 // inputs are (0:control, 1:memory, 2:address) 834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && 846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && 847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && 848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && 849 !(n->rule() == loadUB_rule)) { 850 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 851 } 852 } else if (st_op) { 853 // a Store 854 // inputs are (0:control, 1:memory, 2:address, 3:value) 855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && 861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 862 verify_oops_warning(n, n->ideal_Opcode(), st_op); 863 } 864 } 865 866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 867 Node* addr = n->in(2); 868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 870 if (atype != NULL) { 871 intptr_t offset = get_offset_from_base(n, atype, disp32); 872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 873 if (offset != offset_2) { 874 get_offset_from_base(n, atype, disp32); 875 get_offset_from_base_2(n, atype, disp32); 876 } 877 assert(offset == offset_2, "different offsets"); 878 if (offset == disp32) { 879 // we now know that src1 is a true oop pointer 880 is_verified_oop_base = true; 881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 882 if( primary == Assembler::ldd_op3 ) { 883 is_verified_oop_base = false; // Cannot 'ldd' into O7 884 } else { 885 tmp_enc = dst_enc; 886 dst_enc = R_O7_enc; // Load into O7; preserve source oop 887 assert(src1_enc != dst_enc, ""); 888 } 889 } 890 } 891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 892 || offset == oopDesc::mark_offset_in_bytes())) { 893 // loading the mark should not be allowed either, but 894 // we don't check this since it conflicts with InlineObjectHash 895 // usage of LoadINode to get the mark. We could keep the 896 // check if we create a new LoadMarkNode 897 // but do not verify the object before its header is initialized 898 ShouldNotReachHere(); 899 } 900 } 901 } 902 } 903 } 904 #endif 905 906 uint instr; 907 instr = (Assembler::ldst_op << 30) 908 | (dst_enc << 25) 909 | (primary << 19) 910 | (src1_enc << 14); 911 912 uint index = src2_enc; 913 int disp = disp32; 914 915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { 916 disp += STACK_BIAS; 917 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not 918 if (!Assembler::is_simm13(disp)) { 919 ra->C->record_method_not_compilable("unable to handle large constant offsets"); 920 return; 921 } 922 } 923 924 // We should have a compiler bailout here rather than a guarantee. 925 // Better yet would be some mechanism to handle variable-size matches correctly. 926 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 927 928 if( disp == 0 ) { 929 // use reg-reg form 930 // bit 13 is already zero 931 instr |= index; 932 } else { 933 // use reg-imm form 934 instr |= 0x00002000; // set bit 13 to one 935 instr |= disp & 0x1FFF; 936 } 937 938 cbuf.insts()->emit_int32(instr); 939 940 #ifdef ASSERT 941 { 942 MacroAssembler _masm(&cbuf); 943 if (is_verified_oop_base) { 944 __ verify_oop(reg_to_register_object(src1_enc)); 945 } 946 if (is_verified_oop_store) { 947 __ verify_oop(reg_to_register_object(dst_enc)); 948 } 949 if (tmp_enc != -1) { 950 __ mov(O7, reg_to_register_object(tmp_enc)); 951 } 952 if (is_verified_oop_load) { 953 __ verify_oop(reg_to_register_object(dst_enc)); 954 } 955 } 956 #endif 957 } 958 959 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { 960 // The method which records debug information at every safepoint 961 // expects the call to be the first instruction in the snippet as 962 // it creates a PcDesc structure which tracks the offset of a call 963 // from the start of the codeBlob. This offset is computed as 964 // code_end() - code_begin() of the code which has been emitted 965 // so far. 966 // In this particular case we have skirted around the problem by 967 // putting the "mov" instruction in the delay slot but the problem 968 // may bite us again at some other point and a cleaner/generic 969 // solution using relocations would be needed. 970 MacroAssembler _masm(&cbuf); 971 __ set_inst_mark(); 972 973 // We flush the current window just so that there is a valid stack copy 974 // the fact that the current window becomes active again instantly is 975 // not a problem there is nothing live in it. 976 977 #ifdef ASSERT 978 int startpos = __ offset(); 979 #endif /* ASSERT */ 980 981 __ call((address)entry_point, rtype); 982 983 if (preserve_g2) __ delayed()->mov(G2, L7); 984 else __ delayed()->nop(); 985 986 if (preserve_g2) __ mov(L7, G2); 987 988 #ifdef ASSERT 989 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 990 #ifdef _LP64 991 // Trash argument dump slots. 992 __ set(0xb0b8ac0db0b8ac0d, G1); 993 __ mov(G1, G5); 994 __ stx(G1, SP, STACK_BIAS + 0x80); 995 __ stx(G1, SP, STACK_BIAS + 0x88); 996 __ stx(G1, SP, STACK_BIAS + 0x90); 997 __ stx(G1, SP, STACK_BIAS + 0x98); 998 __ stx(G1, SP, STACK_BIAS + 0xA0); 999 __ stx(G1, SP, STACK_BIAS + 0xA8); 1000 #else // _LP64 1001 // this is also a native call, so smash the first 7 stack locations, 1002 // and the various registers 1003 1004 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 1005 // while [SP+0x44..0x58] are the argument dump slots. 1006 __ set((intptr_t)0xbaadf00d, G1); 1007 __ mov(G1, G5); 1008 __ sllx(G1, 32, G1); 1009 __ or3(G1, G5, G1); 1010 __ mov(G1, G5); 1011 __ stx(G1, SP, 0x40); 1012 __ stx(G1, SP, 0x48); 1013 __ stx(G1, SP, 0x50); 1014 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 1015 #endif // _LP64 1016 } 1017 #endif /*ASSERT*/ 1018 } 1019 1020 //============================================================================= 1021 // REQUIRED FUNCTIONALITY for encoding 1022 void emit_lo(CodeBuffer &cbuf, int val) { } 1023 void emit_hi(CodeBuffer &cbuf, int val) { } 1024 1025 1026 //============================================================================= 1027 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); 1028 1029 int Compile::ConstantTable::calculate_table_base_offset() const { 1030 if (UseRDPCForConstantTableBase) { 1031 // The table base offset might be less but then it fits into 1032 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). 1033 return Assembler::min_simm13(); 1034 } else { 1035 int offset = -(size() / 2); 1036 if (!Assembler::is_simm13(offset)) { 1037 offset = Assembler::min_simm13(); 1038 } 1039 return offset; 1040 } 1041 } 1042 1043 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 1044 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1045 ShouldNotReachHere(); 1046 } 1047 1048 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1049 Compile* C = ra_->C; 1050 Compile::ConstantTable& constant_table = C->constant_table(); 1051 MacroAssembler _masm(&cbuf); 1052 1053 Register r = as_Register(ra_->get_encode(this)); 1054 CodeSection* consts_section = __ code()->consts(); 1055 int consts_size = consts_section->align_at_start(consts_section->size()); 1056 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); 1057 1058 if (UseRDPCForConstantTableBase) { 1059 // For the following RDPC logic to work correctly the consts 1060 // section must be allocated right before the insts section. This 1061 // assert checks for that. The layout and the SECT_* constants 1062 // are defined in src/share/vm/asm/codeBuffer.hpp. 1063 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); 1064 int insts_offset = __ offset(); 1065 1066 // Layout: 1067 // 1068 // |----------- consts section ------------|----------- insts section -----------... 1069 // |------ constant table -----|- padding -|------------------x---- 1070 // \ current PC (RDPC instruction) 1071 // |<------------- consts_size ----------->|<- insts_offset ->| 1072 // \ table base 1073 // The table base offset is later added to the load displacement 1074 // so it has to be negative. 1075 int table_base_offset = -(consts_size + insts_offset); 1076 int disp; 1077 1078 // If the displacement from the current PC to the constant table 1079 // base fits into simm13 we set the constant table base to the 1080 // current PC. 1081 if (Assembler::is_simm13(table_base_offset)) { 1082 constant_table.set_table_base_offset(table_base_offset); 1083 disp = 0; 1084 } else { 1085 // Otherwise we set the constant table base offset to the 1086 // maximum negative displacement of load instructions to keep 1087 // the disp as small as possible: 1088 // 1089 // |<------------- consts_size ----------->|<- insts_offset ->| 1090 // |<--------- min_simm13 --------->|<-------- disp --------->| 1091 // \ table base 1092 table_base_offset = Assembler::min_simm13(); 1093 constant_table.set_table_base_offset(table_base_offset); 1094 disp = (consts_size + insts_offset) + table_base_offset; 1095 } 1096 1097 __ rdpc(r); 1098 1099 if (disp != 0) { 1100 assert(r != O7, "need temporary"); 1101 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); 1102 } 1103 } 1104 else { 1105 // Materialize the constant table base. 1106 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); 1107 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1108 AddressLiteral base(baseaddr, rspec); 1109 __ set(base, r); 1110 } 1111 } 1112 1113 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { 1114 if (UseRDPCForConstantTableBase) { 1115 // This is really the worst case but generally it's only 1 instruction. 1116 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; 1117 } else { 1118 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; 1119 } 1120 } 1121 1122 #ifndef PRODUCT 1123 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1124 char reg[128]; 1125 ra_->dump_register(this, reg); 1126 if (UseRDPCForConstantTableBase) { 1127 st->print("RDPC %s\t! constant table base", reg); 1128 } else { 1129 st->print("SET &constanttable,%s\t! constant table base", reg); 1130 } 1131 } 1132 #endif 1133 1134 1135 //============================================================================= 1136 1137 #ifndef PRODUCT 1138 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1139 Compile* C = ra_->C; 1140 1141 for (int i = 0; i < OptoPrologueNops; i++) { 1142 st->print_cr("NOP"); st->print("\t"); 1143 } 1144 1145 if( VerifyThread ) { 1146 st->print_cr("Verify_Thread"); st->print("\t"); 1147 } 1148 1149 size_t framesize = C->frame_slots() << LogBytesPerInt; 1150 1151 // Calls to C2R adapters often do not accept exceptional returns. 1152 // We require that their callers must bang for them. But be careful, because 1153 // some VM calls (such as call site linkage) can use several kilobytes of 1154 // stack. But the stack safety zone should account for that. 1155 // See bugs 4446381, 4468289, 4497237. 1156 if (C->need_stack_bang(framesize)) { 1157 st->print_cr("! stack bang"); st->print("\t"); 1158 } 1159 1160 if (Assembler::is_simm13(-framesize)) { 1161 st->print ("SAVE R_SP,-%d,R_SP",framesize); 1162 } else { 1163 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); 1164 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); 1165 st->print ("SAVE R_SP,R_G3,R_SP"); 1166 } 1167 1168 } 1169 #endif 1170 1171 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1172 Compile* C = ra_->C; 1173 MacroAssembler _masm(&cbuf); 1174 1175 for (int i = 0; i < OptoPrologueNops; i++) { 1176 __ nop(); 1177 } 1178 1179 __ verify_thread(); 1180 1181 size_t framesize = C->frame_slots() << LogBytesPerInt; 1182 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1183 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1184 1185 // Calls to C2R adapters often do not accept exceptional returns. 1186 // We require that their callers must bang for them. But be careful, because 1187 // some VM calls (such as call site linkage) can use several kilobytes of 1188 // stack. But the stack safety zone should account for that. 1189 // See bugs 4446381, 4468289, 4497237. 1190 if (C->need_stack_bang(framesize)) { 1191 __ generate_stack_overflow_check(framesize); 1192 } 1193 1194 if (Assembler::is_simm13(-framesize)) { 1195 __ save(SP, -framesize, SP); 1196 } else { 1197 __ sethi(-framesize & ~0x3ff, G3); 1198 __ add(G3, -framesize & 0x3ff, G3); 1199 __ save(SP, G3, SP); 1200 } 1201 C->set_frame_complete( __ offset() ); 1202 1203 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { 1204 // NOTE: We set the table base offset here because users might be 1205 // emitted before MachConstantBaseNode. 1206 Compile::ConstantTable& constant_table = C->constant_table(); 1207 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 1208 } 1209 } 1210 1211 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1212 return MachNode::size(ra_); 1213 } 1214 1215 int MachPrologNode::reloc() const { 1216 return 10; // a large enough number 1217 } 1218 1219 //============================================================================= 1220 #ifndef PRODUCT 1221 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1222 Compile* C = ra_->C; 1223 1224 if( do_polling() && ra_->C->is_method_compilation() ) { 1225 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1226 #ifdef _LP64 1227 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1228 #else 1229 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 1230 #endif 1231 } 1232 1233 if( do_polling() ) 1234 st->print("RET\n\t"); 1235 1236 st->print("RESTORE"); 1237 } 1238 #endif 1239 1240 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1241 MacroAssembler _masm(&cbuf); 1242 Compile* C = ra_->C; 1243 1244 __ verify_thread(); 1245 1246 // If this does safepoint polling, then do it here 1247 if( do_polling() && ra_->C->is_method_compilation() ) { 1248 AddressLiteral polling_page(os::get_polling_page()); 1249 __ sethi(polling_page, L0); 1250 __ relocate(relocInfo::poll_return_type); 1251 __ ld_ptr( L0, 0, G0 ); 1252 } 1253 1254 // If this is a return, then stuff the restore in the delay slot 1255 if( do_polling() ) { 1256 __ ret(); 1257 __ delayed()->restore(); 1258 } else { 1259 __ restore(); 1260 } 1261 } 1262 1263 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1264 return MachNode::size(ra_); 1265 } 1266 1267 int MachEpilogNode::reloc() const { 1268 return 16; // a large enough number 1269 } 1270 1271 const Pipeline * MachEpilogNode::pipeline() const { 1272 return MachNode::pipeline_class(); 1273 } 1274 1275 int MachEpilogNode::safepoint_offset() const { 1276 assert( do_polling(), "no return for this epilog node"); 1277 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; 1278 } 1279 1280 //============================================================================= 1281 1282 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1283 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1284 static enum RC rc_class( OptoReg::Name reg ) { 1285 if( !OptoReg::is_valid(reg) ) return rc_bad; 1286 if (OptoReg::is_stack(reg)) return rc_stack; 1287 VMReg r = OptoReg::as_VMReg(reg); 1288 if (r->is_Register()) return rc_int; 1289 assert(r->is_FloatRegister(), "must be"); 1290 return rc_float; 1291 } 1292 1293 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1294 if (cbuf) { 1295 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1296 } 1297 #ifndef PRODUCT 1298 else if (!do_size) { 1299 if (size != 0) st->print("\n\t"); 1300 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1301 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1302 } 1303 #endif 1304 return size+4; 1305 } 1306 1307 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { 1308 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); 1309 #ifndef PRODUCT 1310 else if( !do_size ) { 1311 if( size != 0 ) st->print("\n\t"); 1312 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); 1313 } 1314 #endif 1315 return size+4; 1316 } 1317 1318 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, 1319 PhaseRegAlloc *ra_, 1320 bool do_size, 1321 outputStream* st ) const { 1322 // Get registers to move 1323 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 1324 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 1325 OptoReg::Name dst_second = ra_->get_reg_second(this ); 1326 OptoReg::Name dst_first = ra_->get_reg_first(this ); 1327 1328 enum RC src_second_rc = rc_class(src_second); 1329 enum RC src_first_rc = rc_class(src_first); 1330 enum RC dst_second_rc = rc_class(dst_second); 1331 enum RC dst_first_rc = rc_class(dst_first); 1332 1333 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 1334 1335 // Generate spill code! 1336 int size = 0; 1337 1338 if( src_first == dst_first && src_second == dst_second ) 1339 return size; // Self copy, no move 1340 1341 // -------------------------------------- 1342 // Check for mem-mem move. Load into unused float registers and fall into 1343 // the float-store case. 1344 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1345 int offset = ra_->reg2offset(src_first); 1346 // Further check for aligned-adjacent pair, so we can use a double load 1347 if( (src_first&1)==0 && src_first+1 == src_second ) { 1348 src_second = OptoReg::Name(R_F31_num); 1349 src_second_rc = rc_float; 1350 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); 1351 } else { 1352 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); 1353 } 1354 src_first = OptoReg::Name(R_F30_num); 1355 src_first_rc = rc_float; 1356 } 1357 1358 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1359 int offset = ra_->reg2offset(src_second); 1360 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); 1361 src_second = OptoReg::Name(R_F31_num); 1362 src_second_rc = rc_float; 1363 } 1364 1365 // -------------------------------------- 1366 // Check for float->int copy; requires a trip through memory 1367 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { 1368 int offset = frame::register_save_words*wordSize; 1369 if (cbuf) { 1370 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); 1371 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1372 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1373 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); 1374 } 1375 #ifndef PRODUCT 1376 else if (!do_size) { 1377 if (size != 0) st->print("\n\t"); 1378 st->print( "SUB R_SP,16,R_SP\n"); 1379 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1380 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1381 st->print("\tADD R_SP,16,R_SP\n"); 1382 } 1383 #endif 1384 size += 16; 1385 } 1386 1387 // Check for float->int copy on T4 1388 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { 1389 // Further check for aligned-adjacent pair, so we can use a double move 1390 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) 1391 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); 1392 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); 1393 } 1394 // Check for int->float copy on T4 1395 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { 1396 // Further check for aligned-adjacent pair, so we can use a double move 1397 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) 1398 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); 1399 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); 1400 } 1401 1402 // -------------------------------------- 1403 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1404 // In such cases, I have to do the big-endian swap. For aligned targets, the 1405 // hardware does the flop for me. Doubles are always aligned, so no problem 1406 // there. Misaligned sources only come from native-long-returns (handled 1407 // special below). 1408 #ifndef _LP64 1409 if( src_first_rc == rc_int && // source is already big-endian 1410 src_second_rc != rc_bad && // 64-bit move 1411 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst 1412 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); 1413 // Do the big-endian flop. 1414 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 1415 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 1416 } 1417 #endif 1418 1419 // -------------------------------------- 1420 // Check for integer reg-reg copy 1421 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { 1422 #ifndef _LP64 1423 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case 1424 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1425 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1426 // operand contains the least significant word of the 64-bit value and vice versa. 1427 OptoReg::Name tmp = OptoReg::Name(R_O7_num); 1428 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 1429 // Shift O0 left in-place, zero-extend O1, then OR them into the dst 1430 if( cbuf ) { 1431 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); 1432 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); 1433 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); 1434 #ifndef PRODUCT 1435 } else if( !do_size ) { 1436 if( size != 0 ) st->print("\n\t"); 1437 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 1438 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 1439 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 1440 #endif 1441 } 1442 return size+12; 1443 } 1444 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { 1445 // returning a long value in I0/I1 1446 // a SpillCopy must be able to target a return instruction's reg_class 1447 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1448 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1449 // operand contains the least significant word of the 64-bit value and vice versa. 1450 OptoReg::Name tdest = dst_first; 1451 1452 if (src_first == dst_first) { 1453 tdest = OptoReg::Name(R_O7_num); 1454 size += 4; 1455 } 1456 1457 if( cbuf ) { 1458 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 1459 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 1460 // ShrL_reg_imm6 1461 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); 1462 // ShrR_reg_imm6 src, 0, dst 1463 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); 1464 if (tdest != dst_first) { 1465 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); 1466 } 1467 } 1468 #ifndef PRODUCT 1469 else if( !do_size ) { 1470 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! 1471 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1472 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1473 if (tdest != dst_first) { 1474 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1475 } 1476 } 1477 #endif // PRODUCT 1478 return size+8; 1479 } 1480 #endif // !_LP64 1481 // Else normal reg-reg copy 1482 assert( src_second != dst_first, "smashed second before evacuating it" ); 1483 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); 1484 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); 1485 // This moves an aligned adjacent pair. 1486 // See if we are done. 1487 if( src_first+1 == src_second && dst_first+1 == dst_second ) 1488 return size; 1489 } 1490 1491 // Check for integer store 1492 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { 1493 int offset = ra_->reg2offset(dst_first); 1494 // Further check for aligned-adjacent pair, so we can use a double store 1495 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1496 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); 1497 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); 1498 } 1499 1500 // Check for integer load 1501 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { 1502 int offset = ra_->reg2offset(src_first); 1503 // Further check for aligned-adjacent pair, so we can use a double load 1504 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1505 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); 1506 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1507 } 1508 1509 // Check for float reg-reg copy 1510 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1511 // Further check for aligned-adjacent pair, so we can use a double move 1512 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1513 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); 1514 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); 1515 } 1516 1517 // Check for float store 1518 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1519 int offset = ra_->reg2offset(dst_first); 1520 // Further check for aligned-adjacent pair, so we can use a double store 1521 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1522 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); 1523 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1524 } 1525 1526 // Check for float load 1527 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1528 int offset = ra_->reg2offset(src_first); 1529 // Further check for aligned-adjacent pair, so we can use a double load 1530 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1531 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); 1532 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); 1533 } 1534 1535 // -------------------------------------------------------------------- 1536 // Check for hi bits still needing moving. Only happens for misaligned 1537 // arguments to native calls. 1538 if( src_second == dst_second ) 1539 return size; // Self copy; no move 1540 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1541 1542 #ifndef _LP64 1543 // In the LP64 build, all registers can be moved as aligned/adjacent 1544 // pairs, so there's never any need to move the high bits separately. 1545 // The 32-bit builds have to deal with the 32-bit ABI which can force 1546 // all sorts of silly alignment problems. 1547 1548 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1549 // 32-bits of a 64-bit register, but are needed in low bits of another 1550 // register (else it's a hi-bits-to-hi-bits copy which should have 1551 // happened already as part of a 64-bit move) 1552 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { 1553 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); 1554 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); 1555 // Shift src_second down to dst_second's low bits. 1556 if( cbuf ) { 1557 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1558 #ifndef PRODUCT 1559 } else if( !do_size ) { 1560 if( size != 0 ) st->print("\n\t"); 1561 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); 1562 #endif 1563 } 1564 return size+4; 1565 } 1566 1567 // Check for high word integer store. Must down-shift the hi bits 1568 // into a temp register, then fall into the case of storing int bits. 1569 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { 1570 // Shift src_second down to dst_second's low bits. 1571 if( cbuf ) { 1572 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1573 #ifndef PRODUCT 1574 } else if( !do_size ) { 1575 if( size != 0 ) st->print("\n\t"); 1576 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); 1577 #endif 1578 } 1579 size+=4; 1580 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1581 } 1582 1583 // Check for high word integer load 1584 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1585 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); 1586 1587 // Check for high word integer store 1588 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1589 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); 1590 1591 // Check for high word float store 1592 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) 1593 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); 1594 1595 #endif // !_LP64 1596 1597 Unimplemented(); 1598 } 1599 1600 #ifndef PRODUCT 1601 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1602 implementation( NULL, ra_, false, st ); 1603 } 1604 #endif 1605 1606 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1607 implementation( &cbuf, ra_, false, NULL ); 1608 } 1609 1610 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1611 return implementation( NULL, ra_, true, NULL ); 1612 } 1613 1614 //============================================================================= 1615 #ifndef PRODUCT 1616 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { 1617 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1618 } 1619 #endif 1620 1621 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1622 MacroAssembler _masm(&cbuf); 1623 for(int i = 0; i < _count; i += 1) { 1624 __ nop(); 1625 } 1626 } 1627 1628 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1629 return 4 * _count; 1630 } 1631 1632 1633 //============================================================================= 1634 #ifndef PRODUCT 1635 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1636 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1637 int reg = ra_->get_reg_first(this); 1638 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1639 } 1640 #endif 1641 1642 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1643 MacroAssembler _masm(&cbuf); 1644 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1645 int reg = ra_->get_encode(this); 1646 1647 if (Assembler::is_simm13(offset)) { 1648 __ add(SP, offset, reg_to_register_object(reg)); 1649 } else { 1650 __ set(offset, O7); 1651 __ add(SP, O7, reg_to_register_object(reg)); 1652 } 1653 } 1654 1655 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1656 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1657 assert(ra_ == ra_->C->regalloc(), "sanity"); 1658 return ra_->C->scratch_emit_size(this); 1659 } 1660 1661 //============================================================================= 1662 #ifndef PRODUCT 1663 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1664 st->print_cr("\nUEP:"); 1665 #ifdef _LP64 1666 if (UseCompressedClassPointers) { 1667 assert(Universe::heap() != NULL, "java heap should be initialized"); 1668 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1669 if (Universe::narrow_klass_base() != 0) { 1670 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); 1671 if (Universe::narrow_klass_shift() != 0) { 1672 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1673 } 1674 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1675 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); 1676 } else { 1677 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1678 } 1679 } else { 1680 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1681 } 1682 st->print_cr("\tCMP R_G5,R_G3" ); 1683 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1684 #else // _LP64 1685 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1686 st->print_cr("\tCMP R_G5,R_G3" ); 1687 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1688 #endif // _LP64 1689 } 1690 #endif 1691 1692 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1693 MacroAssembler _masm(&cbuf); 1694 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1695 Register temp_reg = G3; 1696 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1697 1698 // Load klass from receiver 1699 __ load_klass(O0, temp_reg); 1700 // Compare against expected klass 1701 __ cmp(temp_reg, G5_ic_reg); 1702 // Branch to miss code, checks xcc or icc depending 1703 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1704 } 1705 1706 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1707 return MachNode::size(ra_); 1708 } 1709 1710 1711 //============================================================================= 1712 1713 uint size_exception_handler() { 1714 if (TraceJumps) { 1715 return (400); // just a guess 1716 } 1717 return ( NativeJump::instruction_size ); // sethi;jmp;nop 1718 } 1719 1720 uint size_deopt_handler() { 1721 if (TraceJumps) { 1722 return (400); // just a guess 1723 } 1724 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 1725 } 1726 1727 // Emit exception handler code. 1728 int emit_exception_handler(CodeBuffer& cbuf) { 1729 Register temp_reg = G3; 1730 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1731 MacroAssembler _masm(&cbuf); 1732 1733 address base = 1734 __ start_a_stub(size_exception_handler()); 1735 if (base == NULL) return 0; // CodeBuffer::expand failed 1736 1737 int offset = __ offset(); 1738 1739 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1740 __ delayed()->nop(); 1741 1742 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1743 1744 __ end_a_stub(); 1745 1746 return offset; 1747 } 1748 1749 int emit_deopt_handler(CodeBuffer& cbuf) { 1750 // Can't use any of the current frame's registers as we may have deopted 1751 // at a poll and everything (including G3) can be live. 1752 Register temp_reg = L0; 1753 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1754 MacroAssembler _masm(&cbuf); 1755 1756 address base = 1757 __ start_a_stub(size_deopt_handler()); 1758 if (base == NULL) return 0; // CodeBuffer::expand failed 1759 1760 int offset = __ offset(); 1761 __ save_frame(0); 1762 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1763 __ delayed()->restore(); 1764 1765 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1766 1767 __ end_a_stub(); 1768 return offset; 1769 1770 } 1771 1772 // Given a register encoding, produce a Integer Register object 1773 static Register reg_to_register_object(int register_encoding) { 1774 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1775 return as_Register(register_encoding); 1776 } 1777 1778 // Given a register encoding, produce a single-precision Float Register object 1779 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1780 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1781 return as_SingleFloatRegister(register_encoding); 1782 } 1783 1784 // Given a register encoding, produce a double-precision Float Register object 1785 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1786 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1787 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1788 return as_DoubleFloatRegister(register_encoding); 1789 } 1790 1791 const bool Matcher::match_rule_supported(int opcode) { 1792 if (!has_match_rule(opcode)) 1793 return false; 1794 1795 switch (opcode) { 1796 case Op_CountLeadingZerosI: 1797 case Op_CountLeadingZerosL: 1798 case Op_CountTrailingZerosI: 1799 case Op_CountTrailingZerosL: 1800 case Op_PopCountI: 1801 case Op_PopCountL: 1802 if (!UsePopCountInstruction) 1803 return false; 1804 case Op_CompareAndSwapL: 1805 #ifdef _LP64 1806 case Op_CompareAndSwapP: 1807 #endif 1808 if (!VM_Version::supports_cx8()) 1809 return false; 1810 break; 1811 } 1812 1813 return true; // Per default match rules are supported. 1814 } 1815 1816 int Matcher::regnum_to_fpu_offset(int regnum) { 1817 return regnum - 32; // The FP registers are in the second chunk 1818 } 1819 1820 #ifdef ASSERT 1821 address last_rethrow = NULL; // debugging aid for Rethrow encoding 1822 #endif 1823 1824 // Vector width in bytes 1825 const int Matcher::vector_width_in_bytes(BasicType bt) { 1826 assert(MaxVectorSize == 8, ""); 1827 return 8; 1828 } 1829 1830 // Vector ideal reg 1831 const int Matcher::vector_ideal_reg(int size) { 1832 assert(MaxVectorSize == 8, ""); 1833 return Op_RegD; 1834 } 1835 1836 const int Matcher::vector_shift_count_ideal_reg(int size) { 1837 fatal("vector shift is not supported"); 1838 return Node::NotAMachineReg; 1839 } 1840 1841 // Limits on vector size (number of elements) loaded into vector. 1842 const int Matcher::max_vector_size(const BasicType bt) { 1843 assert(is_java_primitive(bt), "only primitive type vectors"); 1844 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1845 } 1846 1847 const int Matcher::min_vector_size(const BasicType bt) { 1848 return max_vector_size(bt); // Same as max. 1849 } 1850 1851 // SPARC doesn't support misaligned vectors store/load. 1852 const bool Matcher::misaligned_vectors_ok() { 1853 return false; 1854 } 1855 1856 // Current (2013) SPARC platforms need to read original key 1857 // to construct decryption expanded key 1858 const bool Matcher::pass_original_key_for_aes() { 1859 return true; 1860 } 1861 1862 // USII supports fxtof through the whole range of number, USIII doesn't 1863 const bool Matcher::convL2FSupported(void) { 1864 return VM_Version::has_fast_fxtof(); 1865 } 1866 1867 // Is this branch offset short enough that a short branch can be used? 1868 // 1869 // NOTE: If the platform does not provide any short branch variants, then 1870 // this method should return false for offset 0. 1871 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1872 // The passed offset is relative to address of the branch. 1873 // Don't need to adjust the offset. 1874 return UseCBCond && Assembler::is_simm12(offset); 1875 } 1876 1877 const bool Matcher::isSimpleConstant64(jlong value) { 1878 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1879 // Depends on optimizations in MacroAssembler::setx. 1880 int hi = (int)(value >> 32); 1881 int lo = (int)(value & ~0); 1882 return (hi == 0) || (hi == -1) || (lo == 0); 1883 } 1884 1885 // No scaling for the parameter the ClearArray node. 1886 const bool Matcher::init_array_count_is_in_bytes = true; 1887 1888 // Threshold size for cleararray. 1889 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1890 1891 // No additional cost for CMOVL. 1892 const int Matcher::long_cmove_cost() { return 0; } 1893 1894 // CMOVF/CMOVD are expensive on T4 and on SPARC64. 1895 const int Matcher::float_cmove_cost() { 1896 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; 1897 } 1898 1899 // Does the CPU require late expand (see block.cpp for description of late expand)? 1900 const bool Matcher::require_postalloc_expand = false; 1901 1902 // Should the Matcher clone shifts on addressing modes, expecting them to 1903 // be subsumed into complex addressing expressions or compute them into 1904 // registers? True for Intel but false for most RISCs 1905 const bool Matcher::clone_shift_expressions = false; 1906 1907 // Do we need to mask the count passed to shift instructions or does 1908 // the cpu only look at the lower 5/6 bits anyway? 1909 const bool Matcher::need_masked_shift_count = false; 1910 1911 bool Matcher::narrow_oop_use_complex_address() { 1912 NOT_LP64(ShouldNotCallThis()); 1913 assert(UseCompressedOops, "only for compressed oops code"); 1914 return false; 1915 } 1916 1917 bool Matcher::narrow_klass_use_complex_address() { 1918 NOT_LP64(ShouldNotCallThis()); 1919 assert(UseCompressedClassPointers, "only for compressed klass code"); 1920 return false; 1921 } 1922 1923 // Is it better to copy float constants, or load them directly from memory? 1924 // Intel can load a float constant from a direct address, requiring no 1925 // extra registers. Most RISCs will have to materialize an address into a 1926 // register first, so they would do better to copy the constant from stack. 1927 const bool Matcher::rematerialize_float_constants = false; 1928 1929 // If CPU can load and store mis-aligned doubles directly then no fixup is 1930 // needed. Else we split the double into 2 integer pieces and move it 1931 // piece-by-piece. Only happens when passing doubles into C code as the 1932 // Java calling convention forces doubles to be aligned. 1933 #ifdef _LP64 1934 const bool Matcher::misaligned_doubles_ok = true; 1935 #else 1936 const bool Matcher::misaligned_doubles_ok = false; 1937 #endif 1938 1939 // No-op on SPARC. 1940 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1941 } 1942 1943 // Advertise here if the CPU requires explicit rounding operations 1944 // to implement the UseStrictFP mode. 1945 const bool Matcher::strict_fp_requires_explicit_rounding = false; 1946 1947 // Are floats conerted to double when stored to stack during deoptimization? 1948 // Sparc does not handle callee-save floats. 1949 bool Matcher::float_in_double() { return false; } 1950 1951 // Do ints take an entire long register or just half? 1952 // Note that we if-def off of _LP64. 1953 // The relevant question is how the int is callee-saved. In _LP64 1954 // the whole long is written but de-opt'ing will have to extract 1955 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1956 #ifdef _LP64 1957 const bool Matcher::int_in_long = true; 1958 #else 1959 const bool Matcher::int_in_long = false; 1960 #endif 1961 1962 // Return whether or not this register is ever used as an argument. This 1963 // function is used on startup to build the trampoline stubs in generateOptoStub. 1964 // Registers not mentioned will be killed by the VM call in the trampoline, and 1965 // arguments in those registers not be available to the callee. 1966 bool Matcher::can_be_java_arg( int reg ) { 1967 // Standard sparc 6 args in registers 1968 if( reg == R_I0_num || 1969 reg == R_I1_num || 1970 reg == R_I2_num || 1971 reg == R_I3_num || 1972 reg == R_I4_num || 1973 reg == R_I5_num ) return true; 1974 #ifdef _LP64 1975 // 64-bit builds can pass 64-bit pointers and longs in 1976 // the high I registers 1977 if( reg == R_I0H_num || 1978 reg == R_I1H_num || 1979 reg == R_I2H_num || 1980 reg == R_I3H_num || 1981 reg == R_I4H_num || 1982 reg == R_I5H_num ) return true; 1983 1984 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1985 return true; 1986 } 1987 1988 #else 1989 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 1990 // Longs cannot be passed in O regs, because O regs become I regs 1991 // after a 'save' and I regs get their high bits chopped off on 1992 // interrupt. 1993 if( reg == R_G1H_num || reg == R_G1_num ) return true; 1994 if( reg == R_G4H_num || reg == R_G4_num ) return true; 1995 #endif 1996 // A few float args in registers 1997 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1998 1999 return false; 2000 } 2001 2002 bool Matcher::is_spillable_arg( int reg ) { 2003 return can_be_java_arg(reg); 2004 } 2005 2006 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 2007 // Use hardware SDIVX instruction when it is 2008 // faster than a code which use multiply. 2009 return VM_Version::has_fast_idiv(); 2010 } 2011 2012 // Register for DIVI projection of divmodI 2013 RegMask Matcher::divI_proj_mask() { 2014 ShouldNotReachHere(); 2015 return RegMask(); 2016 } 2017 2018 // Register for MODI projection of divmodI 2019 RegMask Matcher::modI_proj_mask() { 2020 ShouldNotReachHere(); 2021 return RegMask(); 2022 } 2023 2024 // Register for DIVL projection of divmodL 2025 RegMask Matcher::divL_proj_mask() { 2026 ShouldNotReachHere(); 2027 return RegMask(); 2028 } 2029 2030 // Register for MODL projection of divmodL 2031 RegMask Matcher::modL_proj_mask() { 2032 ShouldNotReachHere(); 2033 return RegMask(); 2034 } 2035 2036 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2037 return L7_REGP_mask(); 2038 } 2039 2040 %} 2041 2042 2043 // The intptr_t operand types, defined by textual substitution. 2044 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 2045 #ifdef _LP64 2046 #define immX immL 2047 #define immX13 immL13 2048 #define immX13m7 immL13m7 2049 #define iRegX iRegL 2050 #define g1RegX g1RegL 2051 #else 2052 #define immX immI 2053 #define immX13 immI13 2054 #define immX13m7 immI13m7 2055 #define iRegX iRegI 2056 #define g1RegX g1RegI 2057 #endif 2058 2059 //----------ENCODING BLOCK----------------------------------------------------- 2060 // This block specifies the encoding classes used by the compiler to output 2061 // byte streams. Encoding classes are parameterized macros used by 2062 // Machine Instruction Nodes in order to generate the bit encoding of the 2063 // instruction. Operands specify their base encoding interface with the 2064 // interface keyword. There are currently supported four interfaces, 2065 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2066 // operand to generate a function which returns its register number when 2067 // queried. CONST_INTER causes an operand to generate a function which 2068 // returns the value of the constant when queried. MEMORY_INTER causes an 2069 // operand to generate four functions which return the Base Register, the 2070 // Index Register, the Scale Value, and the Offset Value of the operand when 2071 // queried. COND_INTER causes an operand to generate six functions which 2072 // return the encoding code (ie - encoding bits for the instruction) 2073 // associated with each basic boolean condition for a conditional instruction. 2074 // 2075 // Instructions specify two basic values for encoding. Again, a function 2076 // is available to check if the constant displacement is an oop. They use the 2077 // ins_encode keyword to specify their encoding classes (which must be 2078 // a sequence of enc_class names, and their parameters, specified in 2079 // the encoding block), and they use the 2080 // opcode keyword to specify, in order, their primary, secondary, and 2081 // tertiary opcode. Only the opcode sections which a particular instruction 2082 // needs for encoding need to be specified. 2083 encode %{ 2084 enc_class enc_untested %{ 2085 #ifdef ASSERT 2086 MacroAssembler _masm(&cbuf); 2087 __ untested("encoding"); 2088 #endif 2089 %} 2090 2091 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 2092 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, 2093 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2094 %} 2095 2096 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 2097 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2098 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2099 %} 2100 2101 enc_class form3_mem_prefetch_read( memory mem ) %{ 2102 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2103 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2104 %} 2105 2106 enc_class form3_mem_prefetch_write( memory mem ) %{ 2107 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2108 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2109 %} 2110 2111 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2112 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2113 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2114 guarantee($mem$$index == R_G0_enc, "double index?"); 2115 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2116 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2117 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2118 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2119 %} 2120 2121 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2122 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2123 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2124 guarantee($mem$$index == R_G0_enc, "double index?"); 2125 // Load long with 2 instructions 2126 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2127 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2128 %} 2129 2130 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2131 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2132 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2133 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2134 %} 2135 2136 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2137 // Encode a reg-reg copy. If it is useless, then empty encoding. 2138 if( $rs2$$reg != $rd$$reg ) 2139 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 2140 %} 2141 2142 // Target lo half of long 2143 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 2144 // Encode a reg-reg copy. If it is useless, then empty encoding. 2145 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 2146 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2147 %} 2148 2149 // Source lo half of long 2150 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2151 // Encode a reg-reg copy. If it is useless, then empty encoding. 2152 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2153 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2154 %} 2155 2156 // Target hi half of long 2157 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2158 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2159 %} 2160 2161 // Source lo half of long, and leave it sign extended. 2162 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2163 // Sign extend low half 2164 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2165 %} 2166 2167 // Source hi half of long, and leave it sign extended. 2168 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2169 // Shift high half to low half 2170 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2171 %} 2172 2173 // Source hi half of long 2174 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2175 // Encode a reg-reg copy. If it is useless, then empty encoding. 2176 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2177 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2178 %} 2179 2180 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2181 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2182 %} 2183 2184 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2185 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2186 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2187 %} 2188 2189 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2190 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2191 // clear if nothing else is happening 2192 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2193 // blt,a,pn done 2194 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2195 // mov dst,-1 in delay slot 2196 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2197 %} 2198 2199 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2200 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2201 %} 2202 2203 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2204 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2205 %} 2206 2207 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2208 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2209 %} 2210 2211 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2212 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2213 %} 2214 2215 enc_class move_return_pc_to_o1() %{ 2216 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2217 %} 2218 2219 #ifdef _LP64 2220 /* %%% merge with enc_to_bool */ 2221 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2222 MacroAssembler _masm(&cbuf); 2223 2224 Register src_reg = reg_to_register_object($src$$reg); 2225 Register dst_reg = reg_to_register_object($dst$$reg); 2226 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2227 %} 2228 #endif 2229 2230 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2231 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2232 MacroAssembler _masm(&cbuf); 2233 2234 Register p_reg = reg_to_register_object($p$$reg); 2235 Register q_reg = reg_to_register_object($q$$reg); 2236 Register y_reg = reg_to_register_object($y$$reg); 2237 Register tmp_reg = reg_to_register_object($tmp$$reg); 2238 2239 __ subcc( p_reg, q_reg, p_reg ); 2240 __ add ( p_reg, y_reg, tmp_reg ); 2241 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2242 %} 2243 2244 enc_class form_d2i_helper(regD src, regF dst) %{ 2245 // fcmp %fcc0,$src,$src 2246 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2247 // branch %fcc0 not-nan, predict taken 2248 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2249 // fdtoi $src,$dst 2250 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2251 // fitos $dst,$dst (if nan) 2252 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2253 // clear $dst (if nan) 2254 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2255 // carry on here... 2256 %} 2257 2258 enc_class form_d2l_helper(regD src, regD dst) %{ 2259 // fcmp %fcc0,$src,$src check for NAN 2260 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2261 // branch %fcc0 not-nan, predict taken 2262 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2263 // fdtox $src,$dst convert in delay slot 2264 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2265 // fxtod $dst,$dst (if nan) 2266 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2267 // clear $dst (if nan) 2268 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2269 // carry on here... 2270 %} 2271 2272 enc_class form_f2i_helper(regF src, regF dst) %{ 2273 // fcmps %fcc0,$src,$src 2274 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2275 // branch %fcc0 not-nan, predict taken 2276 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2277 // fstoi $src,$dst 2278 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2279 // fitos $dst,$dst (if nan) 2280 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2281 // clear $dst (if nan) 2282 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2283 // carry on here... 2284 %} 2285 2286 enc_class form_f2l_helper(regF src, regD dst) %{ 2287 // fcmps %fcc0,$src,$src 2288 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2289 // branch %fcc0 not-nan, predict taken 2290 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2291 // fstox $src,$dst 2292 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2293 // fxtod $dst,$dst (if nan) 2294 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2295 // clear $dst (if nan) 2296 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2297 // carry on here... 2298 %} 2299 2300 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2301 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2302 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2303 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2304 2305 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2306 2307 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2308 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2309 2310 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2311 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2312 %} 2313 2314 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2315 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2316 %} 2317 2318 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2319 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2320 %} 2321 2322 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2323 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2324 %} 2325 2326 enc_class form3_convI2F(regF rs2, regF rd) %{ 2327 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2328 %} 2329 2330 // Encloding class for traceable jumps 2331 enc_class form_jmpl(g3RegP dest) %{ 2332 emit_jmpl(cbuf, $dest$$reg); 2333 %} 2334 2335 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2336 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2337 %} 2338 2339 enc_class form2_nop() %{ 2340 emit_nop(cbuf); 2341 %} 2342 2343 enc_class form2_illtrap() %{ 2344 emit_illtrap(cbuf); 2345 %} 2346 2347 2348 // Compare longs and convert into -1, 0, 1. 2349 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2350 // CMP $src1,$src2 2351 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2352 // blt,a,pn done 2353 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2354 // mov dst,-1 in delay slot 2355 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2356 // bgt,a,pn done 2357 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2358 // mov dst,1 in delay slot 2359 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2360 // CLR $dst 2361 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2362 %} 2363 2364 enc_class enc_PartialSubtypeCheck() %{ 2365 MacroAssembler _masm(&cbuf); 2366 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2367 __ delayed()->nop(); 2368 %} 2369 2370 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ 2371 MacroAssembler _masm(&cbuf); 2372 Label* L = $labl$$label; 2373 Assembler::Predict predict_taken = 2374 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2375 2376 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 2377 __ delayed()->nop(); 2378 %} 2379 2380 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2381 MacroAssembler _masm(&cbuf); 2382 Label* L = $labl$$label; 2383 Assembler::Predict predict_taken = 2384 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2385 2386 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); 2387 __ delayed()->nop(); 2388 %} 2389 2390 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2391 int op = (Assembler::arith_op << 30) | 2392 ($dst$$reg << 25) | 2393 (Assembler::movcc_op3 << 19) | 2394 (1 << 18) | // cc2 bit for 'icc' 2395 ($cmp$$cmpcode << 14) | 2396 (0 << 13) | // select register move 2397 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2398 ($src$$reg << 0); 2399 cbuf.insts()->emit_int32(op); 2400 %} 2401 2402 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2403 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2404 int op = (Assembler::arith_op << 30) | 2405 ($dst$$reg << 25) | 2406 (Assembler::movcc_op3 << 19) | 2407 (1 << 18) | // cc2 bit for 'icc' 2408 ($cmp$$cmpcode << 14) | 2409 (1 << 13) | // select immediate move 2410 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2411 (simm11 << 0); 2412 cbuf.insts()->emit_int32(op); 2413 %} 2414 2415 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2416 int op = (Assembler::arith_op << 30) | 2417 ($dst$$reg << 25) | 2418 (Assembler::movcc_op3 << 19) | 2419 (0 << 18) | // cc2 bit for 'fccX' 2420 ($cmp$$cmpcode << 14) | 2421 (0 << 13) | // select register move 2422 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2423 ($src$$reg << 0); 2424 cbuf.insts()->emit_int32(op); 2425 %} 2426 2427 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2428 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2429 int op = (Assembler::arith_op << 30) | 2430 ($dst$$reg << 25) | 2431 (Assembler::movcc_op3 << 19) | 2432 (0 << 18) | // cc2 bit for 'fccX' 2433 ($cmp$$cmpcode << 14) | 2434 (1 << 13) | // select immediate move 2435 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2436 (simm11 << 0); 2437 cbuf.insts()->emit_int32(op); 2438 %} 2439 2440 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2441 int op = (Assembler::arith_op << 30) | 2442 ($dst$$reg << 25) | 2443 (Assembler::fpop2_op3 << 19) | 2444 (0 << 18) | 2445 ($cmp$$cmpcode << 14) | 2446 (1 << 13) | // select register move 2447 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2448 ($primary << 5) | // select single, double or quad 2449 ($src$$reg << 0); 2450 cbuf.insts()->emit_int32(op); 2451 %} 2452 2453 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2454 int op = (Assembler::arith_op << 30) | 2455 ($dst$$reg << 25) | 2456 (Assembler::fpop2_op3 << 19) | 2457 (0 << 18) | 2458 ($cmp$$cmpcode << 14) | 2459 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2460 ($primary << 5) | // select single, double or quad 2461 ($src$$reg << 0); 2462 cbuf.insts()->emit_int32(op); 2463 %} 2464 2465 // Used by the MIN/MAX encodings. Same as a CMOV, but 2466 // the condition comes from opcode-field instead of an argument. 2467 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2468 int op = (Assembler::arith_op << 30) | 2469 ($dst$$reg << 25) | 2470 (Assembler::movcc_op3 << 19) | 2471 (1 << 18) | // cc2 bit for 'icc' 2472 ($primary << 14) | 2473 (0 << 13) | // select register move 2474 (0 << 11) | // cc1, cc0 bits for 'icc' 2475 ($src$$reg << 0); 2476 cbuf.insts()->emit_int32(op); 2477 %} 2478 2479 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2480 int op = (Assembler::arith_op << 30) | 2481 ($dst$$reg << 25) | 2482 (Assembler::movcc_op3 << 19) | 2483 (6 << 16) | // cc2 bit for 'xcc' 2484 ($primary << 14) | 2485 (0 << 13) | // select register move 2486 (0 << 11) | // cc1, cc0 bits for 'icc' 2487 ($src$$reg << 0); 2488 cbuf.insts()->emit_int32(op); 2489 %} 2490 2491 enc_class Set13( immI13 src, iRegI rd ) %{ 2492 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2493 %} 2494 2495 enc_class SetHi22( immI src, iRegI rd ) %{ 2496 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2497 %} 2498 2499 enc_class Set32( immI src, iRegI rd ) %{ 2500 MacroAssembler _masm(&cbuf); 2501 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2502 %} 2503 2504 enc_class call_epilog %{ 2505 if( VerifyStackAtCalls ) { 2506 MacroAssembler _masm(&cbuf); 2507 int framesize = ra_->C->frame_slots() << LogBytesPerInt; 2508 Register temp_reg = G3; 2509 __ add(SP, framesize, temp_reg); 2510 __ cmp(temp_reg, FP); 2511 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2512 } 2513 %} 2514 2515 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2516 // to G1 so the register allocator will not have to deal with the misaligned register 2517 // pair. 2518 enc_class adjust_long_from_native_call %{ 2519 #ifndef _LP64 2520 if (returns_long()) { 2521 // sllx O0,32,O0 2522 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2523 // srl O1,0,O1 2524 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2525 // or O0,O1,G1 2526 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2527 } 2528 #endif 2529 %} 2530 2531 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2532 // CALL directly to the runtime 2533 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2534 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, 2535 /*preserve_g2=*/true); 2536 %} 2537 2538 enc_class preserve_SP %{ 2539 MacroAssembler _masm(&cbuf); 2540 __ mov(SP, L7_mh_SP_save); 2541 %} 2542 2543 enc_class restore_SP %{ 2544 MacroAssembler _masm(&cbuf); 2545 __ mov(L7_mh_SP_save, SP); 2546 %} 2547 2548 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2549 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2550 // who we intended to call. 2551 if (!_method) { 2552 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); 2553 } else if (_optimized_virtual) { 2554 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); 2555 } else { 2556 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); 2557 } 2558 if (_method) { // Emit stub for static call. 2559 CompiledStaticCall::emit_to_interp_stub(cbuf); 2560 } 2561 %} 2562 2563 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2564 MacroAssembler _masm(&cbuf); 2565 __ set_inst_mark(); 2566 int vtable_index = this->_vtable_index; 2567 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2568 if (vtable_index < 0) { 2569 // must be invalid_vtable_index, not nonvirtual_vtable_index 2570 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 2571 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2572 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2573 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2574 __ ic_call((address)$meth$$method); 2575 } else { 2576 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2577 // Just go thru the vtable 2578 // get receiver klass (receiver already checked for non-null) 2579 // If we end up going thru a c2i adapter interpreter expects method in G5 2580 int off = __ offset(); 2581 __ load_klass(O0, G3_scratch); 2582 int klass_load_size; 2583 if (UseCompressedClassPointers) { 2584 assert(Universe::heap() != NULL, "java heap should be initialized"); 2585 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 2586 } else { 2587 klass_load_size = 1*BytesPerInstWord; 2588 } 2589 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 2590 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 2591 if (Assembler::is_simm13(v_off)) { 2592 __ ld_ptr(G3, v_off, G5_method); 2593 } else { 2594 // Generate 2 instructions 2595 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2596 __ or3(G5_method, v_off & 0x3ff, G5_method); 2597 // ld_ptr, set_hi, set 2598 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2599 "Unexpected instruction size(s)"); 2600 __ ld_ptr(G3, G5_method, G5_method); 2601 } 2602 // NOTE: for vtable dispatches, the vtable entry will never be null. 2603 // However it may very well end up in handle_wrong_method if the 2604 // method is abstract for the particular class. 2605 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); 2606 // jump to target (either compiled code or c2iadapter) 2607 __ jmpl(G3_scratch, G0, O7); 2608 __ delayed()->nop(); 2609 } 2610 %} 2611 2612 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2613 MacroAssembler _masm(&cbuf); 2614 2615 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2616 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2617 // we might be calling a C2I adapter which needs it. 2618 2619 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2620 // Load nmethod 2621 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); 2622 2623 // CALL to compiled java, indirect the contents of G3 2624 __ set_inst_mark(); 2625 __ callr(temp_reg, G0); 2626 __ delayed()->nop(); 2627 %} 2628 2629 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2630 MacroAssembler _masm(&cbuf); 2631 Register Rdividend = reg_to_register_object($src1$$reg); 2632 Register Rdivisor = reg_to_register_object($src2$$reg); 2633 Register Rresult = reg_to_register_object($dst$$reg); 2634 2635 __ sra(Rdivisor, 0, Rdivisor); 2636 __ sra(Rdividend, 0, Rdividend); 2637 __ sdivx(Rdividend, Rdivisor, Rresult); 2638 %} 2639 2640 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2641 MacroAssembler _masm(&cbuf); 2642 2643 Register Rdividend = reg_to_register_object($src1$$reg); 2644 int divisor = $imm$$constant; 2645 Register Rresult = reg_to_register_object($dst$$reg); 2646 2647 __ sra(Rdividend, 0, Rdividend); 2648 __ sdivx(Rdividend, divisor, Rresult); 2649 %} 2650 2651 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2652 MacroAssembler _masm(&cbuf); 2653 Register Rsrc1 = reg_to_register_object($src1$$reg); 2654 Register Rsrc2 = reg_to_register_object($src2$$reg); 2655 Register Rdst = reg_to_register_object($dst$$reg); 2656 2657 __ sra( Rsrc1, 0, Rsrc1 ); 2658 __ sra( Rsrc2, 0, Rsrc2 ); 2659 __ mulx( Rsrc1, Rsrc2, Rdst ); 2660 __ srlx( Rdst, 32, Rdst ); 2661 %} 2662 2663 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2664 MacroAssembler _masm(&cbuf); 2665 Register Rdividend = reg_to_register_object($src1$$reg); 2666 Register Rdivisor = reg_to_register_object($src2$$reg); 2667 Register Rresult = reg_to_register_object($dst$$reg); 2668 Register Rscratch = reg_to_register_object($scratch$$reg); 2669 2670 assert(Rdividend != Rscratch, ""); 2671 assert(Rdivisor != Rscratch, ""); 2672 2673 __ sra(Rdividend, 0, Rdividend); 2674 __ sra(Rdivisor, 0, Rdivisor); 2675 __ sdivx(Rdividend, Rdivisor, Rscratch); 2676 __ mulx(Rscratch, Rdivisor, Rscratch); 2677 __ sub(Rdividend, Rscratch, Rresult); 2678 %} 2679 2680 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2681 MacroAssembler _masm(&cbuf); 2682 2683 Register Rdividend = reg_to_register_object($src1$$reg); 2684 int divisor = $imm$$constant; 2685 Register Rresult = reg_to_register_object($dst$$reg); 2686 Register Rscratch = reg_to_register_object($scratch$$reg); 2687 2688 assert(Rdividend != Rscratch, ""); 2689 2690 __ sra(Rdividend, 0, Rdividend); 2691 __ sdivx(Rdividend, divisor, Rscratch); 2692 __ mulx(Rscratch, divisor, Rscratch); 2693 __ sub(Rdividend, Rscratch, Rresult); 2694 %} 2695 2696 enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2697 MacroAssembler _masm(&cbuf); 2698 2699 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2700 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2701 2702 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2703 %} 2704 2705 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2706 MacroAssembler _masm(&cbuf); 2707 2708 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2709 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2710 2711 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2712 %} 2713 2714 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2715 MacroAssembler _masm(&cbuf); 2716 2717 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2718 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2719 2720 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2721 %} 2722 2723 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2724 MacroAssembler _masm(&cbuf); 2725 2726 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2727 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2728 2729 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2730 %} 2731 2732 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2733 MacroAssembler _masm(&cbuf); 2734 2735 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2736 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2737 2738 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2739 %} 2740 2741 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2742 MacroAssembler _masm(&cbuf); 2743 2744 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2745 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2746 2747 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2748 %} 2749 2750 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2751 MacroAssembler _masm(&cbuf); 2752 2753 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2754 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2755 2756 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2757 %} 2758 2759 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2760 MacroAssembler _masm(&cbuf); 2761 2762 Register Roop = reg_to_register_object($oop$$reg); 2763 Register Rbox = reg_to_register_object($box$$reg); 2764 Register Rscratch = reg_to_register_object($scratch$$reg); 2765 Register Rmark = reg_to_register_object($scratch2$$reg); 2766 2767 assert(Roop != Rscratch, ""); 2768 assert(Roop != Rmark, ""); 2769 assert(Rbox != Rscratch, ""); 2770 assert(Rbox != Rmark, ""); 2771 2772 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2773 %} 2774 2775 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2776 MacroAssembler _masm(&cbuf); 2777 2778 Register Roop = reg_to_register_object($oop$$reg); 2779 Register Rbox = reg_to_register_object($box$$reg); 2780 Register Rscratch = reg_to_register_object($scratch$$reg); 2781 Register Rmark = reg_to_register_object($scratch2$$reg); 2782 2783 assert(Roop != Rscratch, ""); 2784 assert(Roop != Rmark, ""); 2785 assert(Rbox != Rscratch, ""); 2786 assert(Rbox != Rmark, ""); 2787 2788 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2789 %} 2790 2791 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2792 MacroAssembler _masm(&cbuf); 2793 Register Rmem = reg_to_register_object($mem$$reg); 2794 Register Rold = reg_to_register_object($old$$reg); 2795 Register Rnew = reg_to_register_object($new$$reg); 2796 2797 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2798 __ cmp( Rold, Rnew ); 2799 %} 2800 2801 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2802 Register Rmem = reg_to_register_object($mem$$reg); 2803 Register Rold = reg_to_register_object($old$$reg); 2804 Register Rnew = reg_to_register_object($new$$reg); 2805 2806 MacroAssembler _masm(&cbuf); 2807 __ mov(Rnew, O7); 2808 __ casx(Rmem, Rold, O7); 2809 __ cmp( Rold, O7 ); 2810 %} 2811 2812 // raw int cas, used for compareAndSwap 2813 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2814 Register Rmem = reg_to_register_object($mem$$reg); 2815 Register Rold = reg_to_register_object($old$$reg); 2816 Register Rnew = reg_to_register_object($new$$reg); 2817 2818 MacroAssembler _masm(&cbuf); 2819 __ mov(Rnew, O7); 2820 __ cas(Rmem, Rold, O7); 2821 __ cmp( Rold, O7 ); 2822 %} 2823 2824 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2825 Register Rres = reg_to_register_object($res$$reg); 2826 2827 MacroAssembler _masm(&cbuf); 2828 __ mov(1, Rres); 2829 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2830 %} 2831 2832 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2833 Register Rres = reg_to_register_object($res$$reg); 2834 2835 MacroAssembler _masm(&cbuf); 2836 __ mov(1, Rres); 2837 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2838 %} 2839 2840 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2841 MacroAssembler _masm(&cbuf); 2842 Register Rdst = reg_to_register_object($dst$$reg); 2843 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2844 : reg_to_DoubleFloatRegister_object($src1$$reg); 2845 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2846 : reg_to_DoubleFloatRegister_object($src2$$reg); 2847 2848 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2849 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2850 %} 2851 2852 2853 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ 2854 Label Ldone, Lloop; 2855 MacroAssembler _masm(&cbuf); 2856 2857 Register str1_reg = reg_to_register_object($str1$$reg); 2858 Register str2_reg = reg_to_register_object($str2$$reg); 2859 Register cnt1_reg = reg_to_register_object($cnt1$$reg); 2860 Register cnt2_reg = reg_to_register_object($cnt2$$reg); 2861 Register result_reg = reg_to_register_object($result$$reg); 2862 2863 assert(result_reg != str1_reg && 2864 result_reg != str2_reg && 2865 result_reg != cnt1_reg && 2866 result_reg != cnt2_reg , 2867 "need different registers"); 2868 2869 // Compute the minimum of the string lengths(str1_reg) and the 2870 // difference of the string lengths (stack) 2871 2872 // See if the lengths are different, and calculate min in str1_reg. 2873 // Stash diff in O7 in case we need it for a tie-breaker. 2874 Label Lskip; 2875 __ subcc(cnt1_reg, cnt2_reg, O7); 2876 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2877 __ br(Assembler::greater, true, Assembler::pt, Lskip); 2878 // cnt2 is shorter, so use its count: 2879 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2880 __ bind(Lskip); 2881 2882 // reallocate cnt1_reg, cnt2_reg, result_reg 2883 // Note: limit_reg holds the string length pre-scaled by 2 2884 Register limit_reg = cnt1_reg; 2885 Register chr2_reg = cnt2_reg; 2886 Register chr1_reg = result_reg; 2887 // str{12} are the base pointers 2888 2889 // Is the minimum length zero? 2890 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity 2891 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2892 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2893 2894 // Load first characters 2895 __ lduh(str1_reg, 0, chr1_reg); 2896 __ lduh(str2_reg, 0, chr2_reg); 2897 2898 // Compare first characters 2899 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2900 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2901 assert(chr1_reg == result_reg, "result must be pre-placed"); 2902 __ delayed()->nop(); 2903 2904 { 2905 // Check after comparing first character to see if strings are equivalent 2906 Label LSkip2; 2907 // Check if the strings start at same location 2908 __ cmp(str1_reg, str2_reg); 2909 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); 2910 __ delayed()->nop(); 2911 2912 // Check if the length difference is zero (in O7) 2913 __ cmp(G0, O7); 2914 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2915 __ delayed()->mov(G0, result_reg); // result is zero 2916 2917 // Strings might not be equal 2918 __ bind(LSkip2); 2919 } 2920 2921 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 2922 __ signx(limit_reg); 2923 2924 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2925 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2926 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2927 2928 // Shift str1_reg and str2_reg to the end of the arrays, negate limit 2929 __ add(str1_reg, limit_reg, str1_reg); 2930 __ add(str2_reg, limit_reg, str2_reg); 2931 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) 2932 2933 // Compare the rest of the characters 2934 __ lduh(str1_reg, limit_reg, chr1_reg); 2935 __ bind(Lloop); 2936 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2937 __ lduh(str2_reg, limit_reg, chr2_reg); 2938 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2939 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2940 assert(chr1_reg == result_reg, "result must be pre-placed"); 2941 __ delayed()->inccc(limit_reg, sizeof(jchar)); 2942 // annul LDUH if branch is not taken to prevent access past end of string 2943 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 2944 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2945 2946 // If strings are equal up to min length, return the length difference. 2947 __ mov(O7, result_reg); 2948 2949 // Otherwise, return the difference between the first mismatched chars. 2950 __ bind(Ldone); 2951 %} 2952 2953 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ 2954 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; 2955 MacroAssembler _masm(&cbuf); 2956 2957 Register str1_reg = reg_to_register_object($str1$$reg); 2958 Register str2_reg = reg_to_register_object($str2$$reg); 2959 Register cnt_reg = reg_to_register_object($cnt$$reg); 2960 Register tmp1_reg = O7; 2961 Register result_reg = reg_to_register_object($result$$reg); 2962 2963 assert(result_reg != str1_reg && 2964 result_reg != str2_reg && 2965 result_reg != cnt_reg && 2966 result_reg != tmp1_reg , 2967 "need different registers"); 2968 2969 __ cmp(str1_reg, str2_reg); //same char[] ? 2970 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 2971 __ delayed()->add(G0, 1, result_reg); 2972 2973 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); 2974 __ delayed()->add(G0, 1, result_reg); // count == 0 2975 2976 //rename registers 2977 Register limit_reg = cnt_reg; 2978 Register chr1_reg = result_reg; 2979 Register chr2_reg = tmp1_reg; 2980 2981 // We have no guarantee that on 64 bit the higher half of limit_reg is 0 2982 __ signx(limit_reg); 2983 2984 //check for alignment and position the pointers to the ends 2985 __ or3(str1_reg, str2_reg, chr1_reg); 2986 __ andcc(chr1_reg, 0x3, chr1_reg); 2987 // notZero means at least one not 4-byte aligned. 2988 // We could optimize the case when both arrays are not aligned 2989 // but it is not frequent case and it requires additional checks. 2990 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare 2991 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count 2992 2993 // Compare char[] arrays aligned to 4 bytes. 2994 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, 2995 chr1_reg, chr2_reg, Ldone); 2996 __ ba(Ldone); 2997 __ delayed()->add(G0, 1, result_reg); 2998 2999 // char by char compare 3000 __ bind(Lchar); 3001 __ add(str1_reg, limit_reg, str1_reg); 3002 __ add(str2_reg, limit_reg, str2_reg); 3003 __ neg(limit_reg); //negate count 3004 3005 __ lduh(str1_reg, limit_reg, chr1_reg); 3006 // Lchar_loop 3007 __ bind(Lchar_loop); 3008 __ lduh(str2_reg, limit_reg, chr2_reg); 3009 __ cmp(chr1_reg, chr2_reg); 3010 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 3011 __ delayed()->mov(G0, result_reg); //not equal 3012 __ inccc(limit_reg, sizeof(jchar)); 3013 // annul LDUH if branch is not taken to prevent access past end of string 3014 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); 3015 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 3016 3017 __ add(G0, 1, result_reg); //equal 3018 3019 __ bind(Ldone); 3020 %} 3021 3022 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ 3023 Label Lvector, Ldone, Lloop; 3024 MacroAssembler _masm(&cbuf); 3025 3026 Register ary1_reg = reg_to_register_object($ary1$$reg); 3027 Register ary2_reg = reg_to_register_object($ary2$$reg); 3028 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 3029 Register tmp2_reg = O7; 3030 Register result_reg = reg_to_register_object($result$$reg); 3031 3032 int length_offset = arrayOopDesc::length_offset_in_bytes(); 3033 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3034 3035 // return true if the same array 3036 __ cmp(ary1_reg, ary2_reg); 3037 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 3038 __ delayed()->add(G0, 1, result_reg); // equal 3039 3040 __ br_null(ary1_reg, true, Assembler::pn, Ldone); 3041 __ delayed()->mov(G0, result_reg); // not equal 3042 3043 __ br_null(ary2_reg, true, Assembler::pn, Ldone); 3044 __ delayed()->mov(G0, result_reg); // not equal 3045 3046 //load the lengths of arrays 3047 __ ld(Address(ary1_reg, length_offset), tmp1_reg); 3048 __ ld(Address(ary2_reg, length_offset), tmp2_reg); 3049 3050 // return false if the two arrays are not equal length 3051 __ cmp(tmp1_reg, tmp2_reg); 3052 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); 3053 __ delayed()->mov(G0, result_reg); // not equal 3054 3055 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); 3056 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3057 3058 // load array addresses 3059 __ add(ary1_reg, base_offset, ary1_reg); 3060 __ add(ary2_reg, base_offset, ary2_reg); 3061 3062 // renaming registers 3063 Register chr1_reg = result_reg; // for characters in ary1 3064 Register chr2_reg = tmp2_reg; // for characters in ary2 3065 Register limit_reg = tmp1_reg; // length 3066 3067 // set byte count 3068 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); 3069 3070 // Compare char[] arrays aligned to 4 bytes. 3071 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, 3072 chr1_reg, chr2_reg, Ldone); 3073 __ add(G0, 1, result_reg); // equals 3074 3075 __ bind(Ldone); 3076 %} 3077 3078 enc_class enc_rethrow() %{ 3079 cbuf.set_insts_mark(); 3080 Register temp_reg = G3; 3081 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 3082 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3083 MacroAssembler _masm(&cbuf); 3084 #ifdef ASSERT 3085 __ save_frame(0); 3086 AddressLiteral last_rethrow_addrlit(&last_rethrow); 3087 __ sethi(last_rethrow_addrlit, L1); 3088 Address addr(L1, last_rethrow_addrlit.low10()); 3089 __ rdpc(L2); 3090 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3091 __ st_ptr(L2, addr); 3092 __ restore(); 3093 #endif 3094 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 3095 __ delayed()->nop(); 3096 %} 3097 3098 enc_class emit_mem_nop() %{ 3099 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3100 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 3101 %} 3102 3103 enc_class emit_fadd_nop() %{ 3104 // Generates the instruction FMOVS f31,f31 3105 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 3106 %} 3107 3108 enc_class emit_br_nop() %{ 3109 // Generates the instruction BPN,PN . 3110 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 3111 %} 3112 3113 enc_class enc_membar_acquire %{ 3114 MacroAssembler _masm(&cbuf); 3115 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3116 %} 3117 3118 enc_class enc_membar_release %{ 3119 MacroAssembler _masm(&cbuf); 3120 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3121 %} 3122 3123 enc_class enc_membar_volatile %{ 3124 MacroAssembler _masm(&cbuf); 3125 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3126 %} 3127 3128 %} 3129 3130 //----------FRAME-------------------------------------------------------------- 3131 // Definition of frame structure and management information. 3132 // 3133 // S T A C K L A Y O U T Allocators stack-slot number 3134 // | (to get allocators register number 3135 // G Owned by | | v add VMRegImpl::stack0) 3136 // r CALLER | | 3137 // o | +--------+ pad to even-align allocators stack-slot 3138 // w V | pad0 | numbers; owned by CALLER 3139 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3140 // h ^ | in | 5 3141 // | | args | 4 Holes in incoming args owned by SELF 3142 // | | | | 3 3143 // | | +--------+ 3144 // V | | old out| Empty on Intel, window on Sparc 3145 // | old |preserve| Must be even aligned. 3146 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3147 // | | in | 3 area for Intel ret address 3148 // Owned by |preserve| Empty on Sparc. 3149 // SELF +--------+ 3150 // | | pad2 | 2 pad to align old SP 3151 // | +--------+ 1 3152 // | | locks | 0 3153 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3154 // | | pad1 | 11 pad to align new SP 3155 // | +--------+ 3156 // | | | 10 3157 // | | spills | 9 spills 3158 // V | | 8 (pad0 slot for callee) 3159 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 3160 // ^ | out | 7 3161 // | | args | 6 Holes in outgoing args owned by CALLEE 3162 // Owned by +--------+ 3163 // CALLEE | new out| 6 Empty on Intel, window on Sparc 3164 // | new |preserve| Must be even-aligned. 3165 // | SP-+--------+----> Matcher::_new_SP, even aligned 3166 // | | | 3167 // 3168 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3169 // known from SELF's arguments and the Java calling convention. 3170 // Region 6-7 is determined per call site. 3171 // Note 2: If the calling convention leaves holes in the incoming argument 3172 // area, those holes are owned by SELF. Holes in the outgoing area 3173 // are owned by the CALLEE. Holes should not be nessecary in the 3174 // incoming area, as the Java calling convention is completely under 3175 // the control of the AD file. Doubles can be sorted and packed to 3176 // avoid holes. Holes in the outgoing arguments may be nessecary for 3177 // varargs C calling conventions. 3178 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3179 // even aligned with pad0 as needed. 3180 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 3181 // region 6-11 is even aligned; it may be padded out more so that 3182 // the region from SP to FP meets the minimum stack alignment. 3183 3184 frame %{ 3185 // What direction does stack grow in (assumed to be same for native & Java) 3186 stack_direction(TOWARDS_LOW); 3187 3188 // These two registers define part of the calling convention 3189 // between compiled code and the interpreter. 3190 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C 3191 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3192 3193 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3194 cisc_spilling_operand_name(indOffset); 3195 3196 // Number of stack slots consumed by a Monitor enter 3197 #ifdef _LP64 3198 sync_stack_slots(2); 3199 #else 3200 sync_stack_slots(1); 3201 #endif 3202 3203 // Compiled code's Frame Pointer 3204 frame_pointer(R_SP); 3205 3206 // Stack alignment requirement 3207 stack_alignment(StackAlignmentInBytes); 3208 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3209 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3210 3211 // Number of stack slots between incoming argument block and the start of 3212 // a new frame. The PROLOG must add this many slots to the stack. The 3213 // EPILOG must remove this many slots. 3214 in_preserve_stack_slots(0); 3215 3216 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3217 // for calls to C. Supports the var-args backing area for register parms. 3218 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3219 #ifdef _LP64 3220 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3221 varargs_C_out_slots_killed(12); 3222 #else 3223 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3224 varargs_C_out_slots_killed( 7); 3225 #endif 3226 3227 // The after-PROLOG location of the return address. Location of 3228 // return address specifies a type (REG or STACK) and a number 3229 // representing the register number (i.e. - use a register name) or 3230 // stack slot. 3231 return_addr(REG R_I7); // Ret Addr is in register I7 3232 3233 // Body of function which returns an OptoRegs array locating 3234 // arguments either in registers or in stack slots for calling 3235 // java 3236 calling_convention %{ 3237 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3238 3239 %} 3240 3241 // Body of function which returns an OptoRegs array locating 3242 // arguments either in registers or in stack slots for callin 3243 // C. 3244 c_calling_convention %{ 3245 // This is obviously always outgoing 3246 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3247 %} 3248 3249 // Location of native (C/C++) and interpreter return values. This is specified to 3250 // be the same as Java. In the 32-bit VM, long values are actually returned from 3251 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3252 // to and from the register pairs is done by the appropriate call and epilog 3253 // opcodes. This simplifies the register allocator. 3254 c_return_value %{ 3255 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3256 #ifdef _LP64 3257 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3258 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3259 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3260 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3261 #else // !_LP64 3262 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3263 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3264 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3265 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3266 #endif 3267 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3268 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3269 %} 3270 3271 // Location of compiled Java return values. Same as C 3272 return_value %{ 3273 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3274 #ifdef _LP64 3275 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3276 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3277 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3278 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3279 #else // !_LP64 3280 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3281 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3282 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3283 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3284 #endif 3285 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3286 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3287 %} 3288 3289 %} 3290 3291 3292 //----------ATTRIBUTES--------------------------------------------------------- 3293 //----------Operand Attributes------------------------------------------------- 3294 op_attrib op_cost(1); // Required cost attribute 3295 3296 //----------Instruction Attributes--------------------------------------------- 3297 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3298 ins_attrib ins_size(32); // Required size attribute (in bits) 3299 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back 3300 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3301 // non-matching short branch variant of some 3302 // long branch? 3303 3304 //----------OPERANDS----------------------------------------------------------- 3305 // Operand definitions must precede instruction definitions for correct parsing 3306 // in the ADLC because operands constitute user defined types which are used in 3307 // instruction definitions. 3308 3309 //----------Simple Operands---------------------------------------------------- 3310 // Immediate Operands 3311 // Integer Immediate: 32-bit 3312 operand immI() %{ 3313 match(ConI); 3314 3315 op_cost(0); 3316 // formats are generated automatically for constants and base registers 3317 format %{ %} 3318 interface(CONST_INTER); 3319 %} 3320 3321 // Integer Immediate: 8-bit 3322 operand immI8() %{ 3323 predicate(Assembler::is_simm8(n->get_int())); 3324 match(ConI); 3325 op_cost(0); 3326 format %{ %} 3327 interface(CONST_INTER); 3328 %} 3329 3330 // Integer Immediate: 13-bit 3331 operand immI13() %{ 3332 predicate(Assembler::is_simm13(n->get_int())); 3333 match(ConI); 3334 op_cost(0); 3335 3336 format %{ %} 3337 interface(CONST_INTER); 3338 %} 3339 3340 // Integer Immediate: 13-bit minus 7 3341 operand immI13m7() %{ 3342 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3343 match(ConI); 3344 op_cost(0); 3345 3346 format %{ %} 3347 interface(CONST_INTER); 3348 %} 3349 3350 // Integer Immediate: 16-bit 3351 operand immI16() %{ 3352 predicate(Assembler::is_simm16(n->get_int())); 3353 match(ConI); 3354 op_cost(0); 3355 format %{ %} 3356 interface(CONST_INTER); 3357 %} 3358 3359 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) 3360 operand immU12() %{ 3361 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3362 match(ConI); 3363 op_cost(0); 3364 3365 format %{ %} 3366 interface(CONST_INTER); 3367 %} 3368 3369 // Integer Immediate: 6-bit 3370 operand immU6() %{ 3371 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3372 match(ConI); 3373 op_cost(0); 3374 format %{ %} 3375 interface(CONST_INTER); 3376 %} 3377 3378 // Integer Immediate: 11-bit 3379 operand immI11() %{ 3380 predicate(Assembler::is_simm11(n->get_int())); 3381 match(ConI); 3382 op_cost(0); 3383 format %{ %} 3384 interface(CONST_INTER); 3385 %} 3386 3387 // Integer Immediate: 5-bit 3388 operand immI5() %{ 3389 predicate(Assembler::is_simm5(n->get_int())); 3390 match(ConI); 3391 op_cost(0); 3392 format %{ %} 3393 interface(CONST_INTER); 3394 %} 3395 3396 // Int Immediate non-negative 3397 operand immU31() 3398 %{ 3399 predicate(n->get_int() >= 0); 3400 match(ConI); 3401 3402 op_cost(0); 3403 format %{ %} 3404 interface(CONST_INTER); 3405 %} 3406 3407 // Integer Immediate: 0-bit 3408 operand immI0() %{ 3409 predicate(n->get_int() == 0); 3410 match(ConI); 3411 op_cost(0); 3412 3413 format %{ %} 3414 interface(CONST_INTER); 3415 %} 3416 3417 // Integer Immediate: the value 10 3418 operand immI10() %{ 3419 predicate(n->get_int() == 10); 3420 match(ConI); 3421 op_cost(0); 3422 3423 format %{ %} 3424 interface(CONST_INTER); 3425 %} 3426 3427 // Integer Immediate: the values 0-31 3428 operand immU5() %{ 3429 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3430 match(ConI); 3431 op_cost(0); 3432 3433 format %{ %} 3434 interface(CONST_INTER); 3435 %} 3436 3437 // Integer Immediate: the values 1-31 3438 operand immI_1_31() %{ 3439 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3440 match(ConI); 3441 op_cost(0); 3442 3443 format %{ %} 3444 interface(CONST_INTER); 3445 %} 3446 3447 // Integer Immediate: the values 32-63 3448 operand immI_32_63() %{ 3449 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3450 match(ConI); 3451 op_cost(0); 3452 3453 format %{ %} 3454 interface(CONST_INTER); 3455 %} 3456 3457 // Immediates for special shifts (sign extend) 3458 3459 // Integer Immediate: the value 16 3460 operand immI_16() %{ 3461 predicate(n->get_int() == 16); 3462 match(ConI); 3463 op_cost(0); 3464 3465 format %{ %} 3466 interface(CONST_INTER); 3467 %} 3468 3469 // Integer Immediate: the value 24 3470 operand immI_24() %{ 3471 predicate(n->get_int() == 24); 3472 match(ConI); 3473 op_cost(0); 3474 3475 format %{ %} 3476 interface(CONST_INTER); 3477 %} 3478 3479 // Integer Immediate: the value 255 3480 operand immI_255() %{ 3481 predicate( n->get_int() == 255 ); 3482 match(ConI); 3483 op_cost(0); 3484 3485 format %{ %} 3486 interface(CONST_INTER); 3487 %} 3488 3489 // Integer Immediate: the value 65535 3490 operand immI_65535() %{ 3491 predicate(n->get_int() == 65535); 3492 match(ConI); 3493 op_cost(0); 3494 3495 format %{ %} 3496 interface(CONST_INTER); 3497 %} 3498 3499 // Long Immediate: the value FF 3500 operand immL_FF() %{ 3501 predicate( n->get_long() == 0xFFL ); 3502 match(ConL); 3503 op_cost(0); 3504 3505 format %{ %} 3506 interface(CONST_INTER); 3507 %} 3508 3509 // Long Immediate: the value FFFF 3510 operand immL_FFFF() %{ 3511 predicate( n->get_long() == 0xFFFFL ); 3512 match(ConL); 3513 op_cost(0); 3514 3515 format %{ %} 3516 interface(CONST_INTER); 3517 %} 3518 3519 // Pointer Immediate: 32 or 64-bit 3520 operand immP() %{ 3521 match(ConP); 3522 3523 op_cost(5); 3524 // formats are generated automatically for constants and base registers 3525 format %{ %} 3526 interface(CONST_INTER); 3527 %} 3528 3529 #ifdef _LP64 3530 // Pointer Immediate: 64-bit 3531 operand immP_set() %{ 3532 predicate(!VM_Version::is_niagara_plus()); 3533 match(ConP); 3534 3535 op_cost(5); 3536 // formats are generated automatically for constants and base registers 3537 format %{ %} 3538 interface(CONST_INTER); 3539 %} 3540 3541 // Pointer Immediate: 64-bit 3542 // From Niagara2 processors on a load should be better than materializing. 3543 operand immP_load() %{ 3544 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); 3545 match(ConP); 3546 3547 op_cost(5); 3548 // formats are generated automatically for constants and base registers 3549 format %{ %} 3550 interface(CONST_INTER); 3551 %} 3552 3553 // Pointer Immediate: 64-bit 3554 operand immP_no_oop_cheap() %{ 3555 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); 3556 match(ConP); 3557 3558 op_cost(5); 3559 // formats are generated automatically for constants and base registers 3560 format %{ %} 3561 interface(CONST_INTER); 3562 %} 3563 #endif 3564 3565 operand immP13() %{ 3566 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3567 match(ConP); 3568 op_cost(0); 3569 3570 format %{ %} 3571 interface(CONST_INTER); 3572 %} 3573 3574 operand immP0() %{ 3575 predicate(n->get_ptr() == 0); 3576 match(ConP); 3577 op_cost(0); 3578 3579 format %{ %} 3580 interface(CONST_INTER); 3581 %} 3582 3583 operand immP_poll() %{ 3584 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3585 match(ConP); 3586 3587 // formats are generated automatically for constants and base registers 3588 format %{ %} 3589 interface(CONST_INTER); 3590 %} 3591 3592 // Pointer Immediate 3593 operand immN() 3594 %{ 3595 match(ConN); 3596 3597 op_cost(10); 3598 format %{ %} 3599 interface(CONST_INTER); 3600 %} 3601 3602 operand immNKlass() 3603 %{ 3604 match(ConNKlass); 3605 3606 op_cost(10); 3607 format %{ %} 3608 interface(CONST_INTER); 3609 %} 3610 3611 // NULL Pointer Immediate 3612 operand immN0() 3613 %{ 3614 predicate(n->get_narrowcon() == 0); 3615 match(ConN); 3616 3617 op_cost(0); 3618 format %{ %} 3619 interface(CONST_INTER); 3620 %} 3621 3622 operand immL() %{ 3623 match(ConL); 3624 op_cost(40); 3625 // formats are generated automatically for constants and base registers 3626 format %{ %} 3627 interface(CONST_INTER); 3628 %} 3629 3630 operand immL0() %{ 3631 predicate(n->get_long() == 0L); 3632 match(ConL); 3633 op_cost(0); 3634 // formats are generated automatically for constants and base registers 3635 format %{ %} 3636 interface(CONST_INTER); 3637 %} 3638 3639 // Integer Immediate: 5-bit 3640 operand immL5() %{ 3641 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); 3642 match(ConL); 3643 op_cost(0); 3644 format %{ %} 3645 interface(CONST_INTER); 3646 %} 3647 3648 // Long Immediate: 13-bit 3649 operand immL13() %{ 3650 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3651 match(ConL); 3652 op_cost(0); 3653 3654 format %{ %} 3655 interface(CONST_INTER); 3656 %} 3657 3658 // Long Immediate: 13-bit minus 7 3659 operand immL13m7() %{ 3660 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3661 match(ConL); 3662 op_cost(0); 3663 3664 format %{ %} 3665 interface(CONST_INTER); 3666 %} 3667 3668 // Long Immediate: low 32-bit mask 3669 operand immL_32bits() %{ 3670 predicate(n->get_long() == 0xFFFFFFFFL); 3671 match(ConL); 3672 op_cost(0); 3673 3674 format %{ %} 3675 interface(CONST_INTER); 3676 %} 3677 3678 // Long Immediate: cheap (materialize in <= 3 instructions) 3679 operand immL_cheap() %{ 3680 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); 3681 match(ConL); 3682 op_cost(0); 3683 3684 format %{ %} 3685 interface(CONST_INTER); 3686 %} 3687 3688 // Long Immediate: expensive (materialize in > 3 instructions) 3689 operand immL_expensive() %{ 3690 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); 3691 match(ConL); 3692 op_cost(0); 3693 3694 format %{ %} 3695 interface(CONST_INTER); 3696 %} 3697 3698 // Double Immediate 3699 operand immD() %{ 3700 match(ConD); 3701 3702 op_cost(40); 3703 format %{ %} 3704 interface(CONST_INTER); 3705 %} 3706 3707 operand immD0() %{ 3708 #ifdef _LP64 3709 // on 64-bit architectures this comparision is faster 3710 predicate(jlong_cast(n->getd()) == 0); 3711 #else 3712 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); 3713 #endif 3714 match(ConD); 3715 3716 op_cost(0); 3717 format %{ %} 3718 interface(CONST_INTER); 3719 %} 3720 3721 // Float Immediate 3722 operand immF() %{ 3723 match(ConF); 3724 3725 op_cost(20); 3726 format %{ %} 3727 interface(CONST_INTER); 3728 %} 3729 3730 // Float Immediate: 0 3731 operand immF0() %{ 3732 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); 3733 match(ConF); 3734 3735 op_cost(0); 3736 format %{ %} 3737 interface(CONST_INTER); 3738 %} 3739 3740 // Integer Register Operands 3741 // Integer Register 3742 operand iRegI() %{ 3743 constraint(ALLOC_IN_RC(int_reg)); 3744 match(RegI); 3745 3746 match(notemp_iRegI); 3747 match(g1RegI); 3748 match(o0RegI); 3749 match(iRegIsafe); 3750 3751 format %{ %} 3752 interface(REG_INTER); 3753 %} 3754 3755 operand notemp_iRegI() %{ 3756 constraint(ALLOC_IN_RC(notemp_int_reg)); 3757 match(RegI); 3758 3759 match(o0RegI); 3760 3761 format %{ %} 3762 interface(REG_INTER); 3763 %} 3764 3765 operand o0RegI() %{ 3766 constraint(ALLOC_IN_RC(o0_regI)); 3767 match(iRegI); 3768 3769 format %{ %} 3770 interface(REG_INTER); 3771 %} 3772 3773 // Pointer Register 3774 operand iRegP() %{ 3775 constraint(ALLOC_IN_RC(ptr_reg)); 3776 match(RegP); 3777 3778 match(lock_ptr_RegP); 3779 match(g1RegP); 3780 match(g2RegP); 3781 match(g3RegP); 3782 match(g4RegP); 3783 match(i0RegP); 3784 match(o0RegP); 3785 match(o1RegP); 3786 match(l7RegP); 3787 3788 format %{ %} 3789 interface(REG_INTER); 3790 %} 3791 3792 operand sp_ptr_RegP() %{ 3793 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3794 match(RegP); 3795 match(iRegP); 3796 3797 format %{ %} 3798 interface(REG_INTER); 3799 %} 3800 3801 operand lock_ptr_RegP() %{ 3802 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3803 match(RegP); 3804 match(i0RegP); 3805 match(o0RegP); 3806 match(o1RegP); 3807 match(l7RegP); 3808 3809 format %{ %} 3810 interface(REG_INTER); 3811 %} 3812 3813 operand g1RegP() %{ 3814 constraint(ALLOC_IN_RC(g1_regP)); 3815 match(iRegP); 3816 3817 format %{ %} 3818 interface(REG_INTER); 3819 %} 3820 3821 operand g2RegP() %{ 3822 constraint(ALLOC_IN_RC(g2_regP)); 3823 match(iRegP); 3824 3825 format %{ %} 3826 interface(REG_INTER); 3827 %} 3828 3829 operand g3RegP() %{ 3830 constraint(ALLOC_IN_RC(g3_regP)); 3831 match(iRegP); 3832 3833 format %{ %} 3834 interface(REG_INTER); 3835 %} 3836 3837 operand g1RegI() %{ 3838 constraint(ALLOC_IN_RC(g1_regI)); 3839 match(iRegI); 3840 3841 format %{ %} 3842 interface(REG_INTER); 3843 %} 3844 3845 operand g3RegI() %{ 3846 constraint(ALLOC_IN_RC(g3_regI)); 3847 match(iRegI); 3848 3849 format %{ %} 3850 interface(REG_INTER); 3851 %} 3852 3853 operand g4RegI() %{ 3854 constraint(ALLOC_IN_RC(g4_regI)); 3855 match(iRegI); 3856 3857 format %{ %} 3858 interface(REG_INTER); 3859 %} 3860 3861 operand g4RegP() %{ 3862 constraint(ALLOC_IN_RC(g4_regP)); 3863 match(iRegP); 3864 3865 format %{ %} 3866 interface(REG_INTER); 3867 %} 3868 3869 operand i0RegP() %{ 3870 constraint(ALLOC_IN_RC(i0_regP)); 3871 match(iRegP); 3872 3873 format %{ %} 3874 interface(REG_INTER); 3875 %} 3876 3877 operand o0RegP() %{ 3878 constraint(ALLOC_IN_RC(o0_regP)); 3879 match(iRegP); 3880 3881 format %{ %} 3882 interface(REG_INTER); 3883 %} 3884 3885 operand o1RegP() %{ 3886 constraint(ALLOC_IN_RC(o1_regP)); 3887 match(iRegP); 3888 3889 format %{ %} 3890 interface(REG_INTER); 3891 %} 3892 3893 operand o2RegP() %{ 3894 constraint(ALLOC_IN_RC(o2_regP)); 3895 match(iRegP); 3896 3897 format %{ %} 3898 interface(REG_INTER); 3899 %} 3900 3901 operand o7RegP() %{ 3902 constraint(ALLOC_IN_RC(o7_regP)); 3903 match(iRegP); 3904 3905 format %{ %} 3906 interface(REG_INTER); 3907 %} 3908 3909 operand l7RegP() %{ 3910 constraint(ALLOC_IN_RC(l7_regP)); 3911 match(iRegP); 3912 3913 format %{ %} 3914 interface(REG_INTER); 3915 %} 3916 3917 operand o7RegI() %{ 3918 constraint(ALLOC_IN_RC(o7_regI)); 3919 match(iRegI); 3920 3921 format %{ %} 3922 interface(REG_INTER); 3923 %} 3924 3925 operand iRegN() %{ 3926 constraint(ALLOC_IN_RC(int_reg)); 3927 match(RegN); 3928 3929 format %{ %} 3930 interface(REG_INTER); 3931 %} 3932 3933 // Long Register 3934 operand iRegL() %{ 3935 constraint(ALLOC_IN_RC(long_reg)); 3936 match(RegL); 3937 3938 format %{ %} 3939 interface(REG_INTER); 3940 %} 3941 3942 operand o2RegL() %{ 3943 constraint(ALLOC_IN_RC(o2_regL)); 3944 match(iRegL); 3945 3946 format %{ %} 3947 interface(REG_INTER); 3948 %} 3949 3950 operand o7RegL() %{ 3951 constraint(ALLOC_IN_RC(o7_regL)); 3952 match(iRegL); 3953 3954 format %{ %} 3955 interface(REG_INTER); 3956 %} 3957 3958 operand g1RegL() %{ 3959 constraint(ALLOC_IN_RC(g1_regL)); 3960 match(iRegL); 3961 3962 format %{ %} 3963 interface(REG_INTER); 3964 %} 3965 3966 operand g3RegL() %{ 3967 constraint(ALLOC_IN_RC(g3_regL)); 3968 match(iRegL); 3969 3970 format %{ %} 3971 interface(REG_INTER); 3972 %} 3973 3974 // Int Register safe 3975 // This is 64bit safe 3976 operand iRegIsafe() %{ 3977 constraint(ALLOC_IN_RC(long_reg)); 3978 3979 match(iRegI); 3980 3981 format %{ %} 3982 interface(REG_INTER); 3983 %} 3984 3985 // Condition Code Flag Register 3986 operand flagsReg() %{ 3987 constraint(ALLOC_IN_RC(int_flags)); 3988 match(RegFlags); 3989 3990 format %{ "ccr" %} // both ICC and XCC 3991 interface(REG_INTER); 3992 %} 3993 3994 // Condition Code Register, unsigned comparisons. 3995 operand flagsRegU() %{ 3996 constraint(ALLOC_IN_RC(int_flags)); 3997 match(RegFlags); 3998 3999 format %{ "icc_U" %} 4000 interface(REG_INTER); 4001 %} 4002 4003 // Condition Code Register, pointer comparisons. 4004 operand flagsRegP() %{ 4005 constraint(ALLOC_IN_RC(int_flags)); 4006 match(RegFlags); 4007 4008 #ifdef _LP64 4009 format %{ "xcc_P" %} 4010 #else 4011 format %{ "icc_P" %} 4012 #endif 4013 interface(REG_INTER); 4014 %} 4015 4016 // Condition Code Register, long comparisons. 4017 operand flagsRegL() %{ 4018 constraint(ALLOC_IN_RC(int_flags)); 4019 match(RegFlags); 4020 4021 format %{ "xcc_L" %} 4022 interface(REG_INTER); 4023 %} 4024 4025 // Condition Code Register, floating comparisons, unordered same as "less". 4026 operand flagsRegF() %{ 4027 constraint(ALLOC_IN_RC(float_flags)); 4028 match(RegFlags); 4029 match(flagsRegF0); 4030 4031 format %{ %} 4032 interface(REG_INTER); 4033 %} 4034 4035 operand flagsRegF0() %{ 4036 constraint(ALLOC_IN_RC(float_flag0)); 4037 match(RegFlags); 4038 4039 format %{ %} 4040 interface(REG_INTER); 4041 %} 4042 4043 4044 // Condition Code Flag Register used by long compare 4045 operand flagsReg_long_LTGE() %{ 4046 constraint(ALLOC_IN_RC(int_flags)); 4047 match(RegFlags); 4048 format %{ "icc_LTGE" %} 4049 interface(REG_INTER); 4050 %} 4051 operand flagsReg_long_EQNE() %{ 4052 constraint(ALLOC_IN_RC(int_flags)); 4053 match(RegFlags); 4054 format %{ "icc_EQNE" %} 4055 interface(REG_INTER); 4056 %} 4057 operand flagsReg_long_LEGT() %{ 4058 constraint(ALLOC_IN_RC(int_flags)); 4059 match(RegFlags); 4060 format %{ "icc_LEGT" %} 4061 interface(REG_INTER); 4062 %} 4063 4064 4065 operand regD() %{ 4066 constraint(ALLOC_IN_RC(dflt_reg)); 4067 match(RegD); 4068 4069 match(regD_low); 4070 4071 format %{ %} 4072 interface(REG_INTER); 4073 %} 4074 4075 operand regF() %{ 4076 constraint(ALLOC_IN_RC(sflt_reg)); 4077 match(RegF); 4078 4079 format %{ %} 4080 interface(REG_INTER); 4081 %} 4082 4083 operand regD_low() %{ 4084 constraint(ALLOC_IN_RC(dflt_low_reg)); 4085 match(regD); 4086 4087 format %{ %} 4088 interface(REG_INTER); 4089 %} 4090 4091 // Special Registers 4092 4093 // Method Register 4094 operand inline_cache_regP(iRegP reg) %{ 4095 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 4096 match(reg); 4097 format %{ %} 4098 interface(REG_INTER); 4099 %} 4100 4101 operand interpreter_method_oop_regP(iRegP reg) %{ 4102 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 4103 match(reg); 4104 format %{ %} 4105 interface(REG_INTER); 4106 %} 4107 4108 4109 //----------Complex Operands--------------------------------------------------- 4110 // Indirect Memory Reference 4111 operand indirect(sp_ptr_RegP reg) %{ 4112 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4113 match(reg); 4114 4115 op_cost(100); 4116 format %{ "[$reg]" %} 4117 interface(MEMORY_INTER) %{ 4118 base($reg); 4119 index(0x0); 4120 scale(0x0); 4121 disp(0x0); 4122 %} 4123 %} 4124 4125 // Indirect with simm13 Offset 4126 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 4127 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4128 match(AddP reg offset); 4129 4130 op_cost(100); 4131 format %{ "[$reg + $offset]" %} 4132 interface(MEMORY_INTER) %{ 4133 base($reg); 4134 index(0x0); 4135 scale(0x0); 4136 disp($offset); 4137 %} 4138 %} 4139 4140 // Indirect with simm13 Offset minus 7 4141 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 4142 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4143 match(AddP reg offset); 4144 4145 op_cost(100); 4146 format %{ "[$reg + $offset]" %} 4147 interface(MEMORY_INTER) %{ 4148 base($reg); 4149 index(0x0); 4150 scale(0x0); 4151 disp($offset); 4152 %} 4153 %} 4154 4155 // Note: Intel has a swapped version also, like this: 4156 //operand indOffsetX(iRegI reg, immP offset) %{ 4157 // constraint(ALLOC_IN_RC(int_reg)); 4158 // match(AddP offset reg); 4159 // 4160 // op_cost(100); 4161 // format %{ "[$reg + $offset]" %} 4162 // interface(MEMORY_INTER) %{ 4163 // base($reg); 4164 // index(0x0); 4165 // scale(0x0); 4166 // disp($offset); 4167 // %} 4168 //%} 4169 //// However, it doesn't make sense for SPARC, since 4170 // we have no particularly good way to embed oops in 4171 // single instructions. 4172 4173 // Indirect with Register Index 4174 operand indIndex(iRegP addr, iRegX index) %{ 4175 constraint(ALLOC_IN_RC(ptr_reg)); 4176 match(AddP addr index); 4177 4178 op_cost(100); 4179 format %{ "[$addr + $index]" %} 4180 interface(MEMORY_INTER) %{ 4181 base($addr); 4182 index($index); 4183 scale(0x0); 4184 disp(0x0); 4185 %} 4186 %} 4187 4188 //----------Special Memory Operands-------------------------------------------- 4189 // Stack Slot Operand - This operand is used for loading and storing temporary 4190 // values on the stack where a match requires a value to 4191 // flow through memory. 4192 operand stackSlotI(sRegI reg) %{ 4193 constraint(ALLOC_IN_RC(stack_slots)); 4194 op_cost(100); 4195 //match(RegI); 4196 format %{ "[$reg]" %} 4197 interface(MEMORY_INTER) %{ 4198 base(0xE); // R_SP 4199 index(0x0); 4200 scale(0x0); 4201 disp($reg); // Stack Offset 4202 %} 4203 %} 4204 4205 operand stackSlotP(sRegP reg) %{ 4206 constraint(ALLOC_IN_RC(stack_slots)); 4207 op_cost(100); 4208 //match(RegP); 4209 format %{ "[$reg]" %} 4210 interface(MEMORY_INTER) %{ 4211 base(0xE); // R_SP 4212 index(0x0); 4213 scale(0x0); 4214 disp($reg); // Stack Offset 4215 %} 4216 %} 4217 4218 operand stackSlotF(sRegF reg) %{ 4219 constraint(ALLOC_IN_RC(stack_slots)); 4220 op_cost(100); 4221 //match(RegF); 4222 format %{ "[$reg]" %} 4223 interface(MEMORY_INTER) %{ 4224 base(0xE); // R_SP 4225 index(0x0); 4226 scale(0x0); 4227 disp($reg); // Stack Offset 4228 %} 4229 %} 4230 operand stackSlotD(sRegD reg) %{ 4231 constraint(ALLOC_IN_RC(stack_slots)); 4232 op_cost(100); 4233 //match(RegD); 4234 format %{ "[$reg]" %} 4235 interface(MEMORY_INTER) %{ 4236 base(0xE); // R_SP 4237 index(0x0); 4238 scale(0x0); 4239 disp($reg); // Stack Offset 4240 %} 4241 %} 4242 operand stackSlotL(sRegL reg) %{ 4243 constraint(ALLOC_IN_RC(stack_slots)); 4244 op_cost(100); 4245 //match(RegL); 4246 format %{ "[$reg]" %} 4247 interface(MEMORY_INTER) %{ 4248 base(0xE); // R_SP 4249 index(0x0); 4250 scale(0x0); 4251 disp($reg); // Stack Offset 4252 %} 4253 %} 4254 4255 // Operands for expressing Control Flow 4256 // NOTE: Label is a predefined operand which should not be redefined in 4257 // the AD file. It is generically handled within the ADLC. 4258 4259 //----------Conditional Branch Operands---------------------------------------- 4260 // Comparison Op - This is the operation of the comparison, and is limited to 4261 // the following set of codes: 4262 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4263 // 4264 // Other attributes of the comparison, such as unsignedness, are specified 4265 // by the comparison instruction that sets a condition code flags register. 4266 // That result is represented by a flags operand whose subtype is appropriate 4267 // to the unsignedness (etc.) of the comparison. 4268 // 4269 // Later, the instruction which matches both the Comparison Op (a Bool) and 4270 // the flags (produced by the Cmp) specifies the coding of the comparison op 4271 // by matching a specific subtype of Bool operand below, such as cmpOpU. 4272 4273 operand cmpOp() %{ 4274 match(Bool); 4275 4276 format %{ "" %} 4277 interface(COND_INTER) %{ 4278 equal(0x1); 4279 not_equal(0x9); 4280 less(0x3); 4281 greater_equal(0xB); 4282 less_equal(0x2); 4283 greater(0xA); 4284 overflow(0x7); 4285 no_overflow(0xF); 4286 %} 4287 %} 4288 4289 // Comparison Op, unsigned 4290 operand cmpOpU() %{ 4291 match(Bool); 4292 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4293 n->as_Bool()->_test._test != BoolTest::no_overflow); 4294 4295 format %{ "u" %} 4296 interface(COND_INTER) %{ 4297 equal(0x1); 4298 not_equal(0x9); 4299 less(0x5); 4300 greater_equal(0xD); 4301 less_equal(0x4); 4302 greater(0xC); 4303 overflow(0x7); 4304 no_overflow(0xF); 4305 %} 4306 %} 4307 4308 // Comparison Op, pointer (same as unsigned) 4309 operand cmpOpP() %{ 4310 match(Bool); 4311 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4312 n->as_Bool()->_test._test != BoolTest::no_overflow); 4313 4314 format %{ "p" %} 4315 interface(COND_INTER) %{ 4316 equal(0x1); 4317 not_equal(0x9); 4318 less(0x5); 4319 greater_equal(0xD); 4320 less_equal(0x4); 4321 greater(0xC); 4322 overflow(0x7); 4323 no_overflow(0xF); 4324 %} 4325 %} 4326 4327 // Comparison Op, branch-register encoding 4328 operand cmpOp_reg() %{ 4329 match(Bool); 4330 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4331 n->as_Bool()->_test._test != BoolTest::no_overflow); 4332 4333 format %{ "" %} 4334 interface(COND_INTER) %{ 4335 equal (0x1); 4336 not_equal (0x5); 4337 less (0x3); 4338 greater_equal(0x7); 4339 less_equal (0x2); 4340 greater (0x6); 4341 overflow(0x7); // not supported 4342 no_overflow(0xF); // not supported 4343 %} 4344 %} 4345 4346 // Comparison Code, floating, unordered same as less 4347 operand cmpOpF() %{ 4348 match(Bool); 4349 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4350 n->as_Bool()->_test._test != BoolTest::no_overflow); 4351 4352 format %{ "fl" %} 4353 interface(COND_INTER) %{ 4354 equal(0x9); 4355 not_equal(0x1); 4356 less(0x3); 4357 greater_equal(0xB); 4358 less_equal(0xE); 4359 greater(0x6); 4360 4361 overflow(0x7); // not supported 4362 no_overflow(0xF); // not supported 4363 %} 4364 %} 4365 4366 // Used by long compare 4367 operand cmpOp_commute() %{ 4368 match(Bool); 4369 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4370 n->as_Bool()->_test._test != BoolTest::no_overflow); 4371 4372 format %{ "" %} 4373 interface(COND_INTER) %{ 4374 equal(0x1); 4375 not_equal(0x9); 4376 less(0xA); 4377 greater_equal(0x2); 4378 less_equal(0xB); 4379 greater(0x3); 4380 overflow(0x7); 4381 no_overflow(0xF); 4382 %} 4383 %} 4384 4385 //----------OPERAND CLASSES---------------------------------------------------- 4386 // Operand Classes are groups of operands that are used to simplify 4387 // instruction definitions by not requiring the AD writer to specify separate 4388 // instructions for every form of operand when the instruction accepts 4389 // multiple operand types with the same basic encoding and format. The classic 4390 // case of this is memory operands. 4391 opclass memory( indirect, indOffset13, indIndex ); 4392 opclass indIndexMemory( indIndex ); 4393 4394 //----------PIPELINE----------------------------------------------------------- 4395 pipeline %{ 4396 4397 //----------ATTRIBUTES--------------------------------------------------------- 4398 attributes %{ 4399 fixed_size_instructions; // Fixed size instructions 4400 branch_has_delay_slot; // Branch has delay slot following 4401 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4402 instruction_unit_size = 4; // An instruction is 4 bytes long 4403 instruction_fetch_unit_size = 16; // The processor fetches one line 4404 instruction_fetch_units = 1; // of 16 bytes 4405 4406 // List of nop instructions 4407 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4408 %} 4409 4410 //----------RESOURCES---------------------------------------------------------- 4411 // Resources are the functional units available to the machine 4412 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4413 4414 //----------PIPELINE DESCRIPTION----------------------------------------------- 4415 // Pipeline Description specifies the stages in the machine's pipeline 4416 4417 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4418 4419 //----------PIPELINE CLASSES--------------------------------------------------- 4420 // Pipeline Classes describe the stages in which input and output are 4421 // referenced by the hardware pipeline. 4422 4423 // Integer ALU reg-reg operation 4424 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4425 single_instruction; 4426 dst : E(write); 4427 src1 : R(read); 4428 src2 : R(read); 4429 IALU : R; 4430 %} 4431 4432 // Integer ALU reg-reg long operation 4433 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4434 instruction_count(2); 4435 dst : E(write); 4436 src1 : R(read); 4437 src2 : R(read); 4438 IALU : R; 4439 IALU : R; 4440 %} 4441 4442 // Integer ALU reg-reg long dependent operation 4443 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4444 instruction_count(1); multiple_bundles; 4445 dst : E(write); 4446 src1 : R(read); 4447 src2 : R(read); 4448 cr : E(write); 4449 IALU : R(2); 4450 %} 4451 4452 // Integer ALU reg-imm operaion 4453 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4454 single_instruction; 4455 dst : E(write); 4456 src1 : R(read); 4457 IALU : R; 4458 %} 4459 4460 // Integer ALU reg-reg operation with condition code 4461 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4462 single_instruction; 4463 dst : E(write); 4464 cr : E(write); 4465 src1 : R(read); 4466 src2 : R(read); 4467 IALU : R; 4468 %} 4469 4470 // Integer ALU reg-imm operation with condition code 4471 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4472 single_instruction; 4473 dst : E(write); 4474 cr : E(write); 4475 src1 : R(read); 4476 IALU : R; 4477 %} 4478 4479 // Integer ALU zero-reg operation 4480 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4481 single_instruction; 4482 dst : E(write); 4483 src2 : R(read); 4484 IALU : R; 4485 %} 4486 4487 // Integer ALU zero-reg operation with condition code only 4488 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4489 single_instruction; 4490 cr : E(write); 4491 src : R(read); 4492 IALU : R; 4493 %} 4494 4495 // Integer ALU reg-reg operation with condition code only 4496 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4497 single_instruction; 4498 cr : E(write); 4499 src1 : R(read); 4500 src2 : R(read); 4501 IALU : R; 4502 %} 4503 4504 // Integer ALU reg-imm operation with condition code only 4505 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4506 single_instruction; 4507 cr : E(write); 4508 src1 : R(read); 4509 IALU : R; 4510 %} 4511 4512 // Integer ALU reg-reg-zero operation with condition code only 4513 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4514 single_instruction; 4515 cr : E(write); 4516 src1 : R(read); 4517 src2 : R(read); 4518 IALU : R; 4519 %} 4520 4521 // Integer ALU reg-imm-zero operation with condition code only 4522 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4523 single_instruction; 4524 cr : E(write); 4525 src1 : R(read); 4526 IALU : R; 4527 %} 4528 4529 // Integer ALU reg-reg operation with condition code, src1 modified 4530 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4531 single_instruction; 4532 cr : E(write); 4533 src1 : E(write); 4534 src1 : R(read); 4535 src2 : R(read); 4536 IALU : R; 4537 %} 4538 4539 // Integer ALU reg-imm operation with condition code, src1 modified 4540 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4541 single_instruction; 4542 cr : E(write); 4543 src1 : E(write); 4544 src1 : R(read); 4545 IALU : R; 4546 %} 4547 4548 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4549 multiple_bundles; 4550 dst : E(write)+4; 4551 cr : E(write); 4552 src1 : R(read); 4553 src2 : R(read); 4554 IALU : R(3); 4555 BR : R(2); 4556 %} 4557 4558 // Integer ALU operation 4559 pipe_class ialu_none(iRegI dst) %{ 4560 single_instruction; 4561 dst : E(write); 4562 IALU : R; 4563 %} 4564 4565 // Integer ALU reg operation 4566 pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4567 single_instruction; may_have_no_code; 4568 dst : E(write); 4569 src : R(read); 4570 IALU : R; 4571 %} 4572 4573 // Integer ALU reg conditional operation 4574 // This instruction has a 1 cycle stall, and cannot execute 4575 // in the same cycle as the instruction setting the condition 4576 // code. We kludge this by pretending to read the condition code 4577 // 1 cycle earlier, and by marking the functional units as busy 4578 // for 2 cycles with the result available 1 cycle later than 4579 // is really the case. 4580 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4581 single_instruction; 4582 op2_out : C(write); 4583 op1 : R(read); 4584 cr : R(read); // This is really E, with a 1 cycle stall 4585 BR : R(2); 4586 MS : R(2); 4587 %} 4588 4589 #ifdef _LP64 4590 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4591 instruction_count(1); multiple_bundles; 4592 dst : C(write)+1; 4593 src : R(read)+1; 4594 IALU : R(1); 4595 BR : E(2); 4596 MS : E(2); 4597 %} 4598 #endif 4599 4600 // Integer ALU reg operation 4601 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4602 single_instruction; may_have_no_code; 4603 dst : E(write); 4604 src : R(read); 4605 IALU : R; 4606 %} 4607 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4608 single_instruction; may_have_no_code; 4609 dst : E(write); 4610 src : R(read); 4611 IALU : R; 4612 %} 4613 4614 // Two integer ALU reg operations 4615 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4616 instruction_count(2); 4617 dst : E(write); 4618 src : R(read); 4619 A0 : R; 4620 A1 : R; 4621 %} 4622 4623 // Two integer ALU reg operations 4624 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4625 instruction_count(2); may_have_no_code; 4626 dst : E(write); 4627 src : R(read); 4628 A0 : R; 4629 A1 : R; 4630 %} 4631 4632 // Integer ALU imm operation 4633 pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4634 single_instruction; 4635 dst : E(write); 4636 IALU : R; 4637 %} 4638 4639 // Integer ALU reg-reg with carry operation 4640 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4641 single_instruction; 4642 dst : E(write); 4643 src1 : R(read); 4644 src2 : R(read); 4645 IALU : R; 4646 %} 4647 4648 // Integer ALU cc operation 4649 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4650 single_instruction; 4651 dst : E(write); 4652 cc : R(read); 4653 IALU : R; 4654 %} 4655 4656 // Integer ALU cc / second IALU operation 4657 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4658 instruction_count(1); multiple_bundles; 4659 dst : E(write)+1; 4660 src : R(read); 4661 IALU : R; 4662 %} 4663 4664 // Integer ALU cc / second IALU operation 4665 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4666 instruction_count(1); multiple_bundles; 4667 dst : E(write)+1; 4668 p : R(read); 4669 q : R(read); 4670 IALU : R; 4671 %} 4672 4673 // Integer ALU hi-lo-reg operation 4674 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4675 instruction_count(1); multiple_bundles; 4676 dst : E(write)+1; 4677 IALU : R(2); 4678 %} 4679 4680 // Float ALU hi-lo-reg operation (with temp) 4681 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4682 instruction_count(1); multiple_bundles; 4683 dst : E(write)+1; 4684 IALU : R(2); 4685 %} 4686 4687 // Long Constant 4688 pipe_class loadConL( iRegL dst, immL src ) %{ 4689 instruction_count(2); multiple_bundles; 4690 dst : E(write)+1; 4691 IALU : R(2); 4692 IALU : R(2); 4693 %} 4694 4695 // Pointer Constant 4696 pipe_class loadConP( iRegP dst, immP src ) %{ 4697 instruction_count(0); multiple_bundles; 4698 fixed_latency(6); 4699 %} 4700 4701 // Polling Address 4702 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4703 #ifdef _LP64 4704 instruction_count(0); multiple_bundles; 4705 fixed_latency(6); 4706 #else 4707 dst : E(write); 4708 IALU : R; 4709 #endif 4710 %} 4711 4712 // Long Constant small 4713 pipe_class loadConLlo( iRegL dst, immL src ) %{ 4714 instruction_count(2); 4715 dst : E(write); 4716 IALU : R; 4717 IALU : R; 4718 %} 4719 4720 // [PHH] This is wrong for 64-bit. See LdImmF/D. 4721 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4722 instruction_count(1); multiple_bundles; 4723 src : R(read); 4724 dst : M(write)+1; 4725 IALU : R; 4726 MS : E; 4727 %} 4728 4729 // Integer ALU nop operation 4730 pipe_class ialu_nop() %{ 4731 single_instruction; 4732 IALU : R; 4733 %} 4734 4735 // Integer ALU nop operation 4736 pipe_class ialu_nop_A0() %{ 4737 single_instruction; 4738 A0 : R; 4739 %} 4740 4741 // Integer ALU nop operation 4742 pipe_class ialu_nop_A1() %{ 4743 single_instruction; 4744 A1 : R; 4745 %} 4746 4747 // Integer Multiply reg-reg operation 4748 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4749 single_instruction; 4750 dst : E(write); 4751 src1 : R(read); 4752 src2 : R(read); 4753 MS : R(5); 4754 %} 4755 4756 // Integer Multiply reg-imm operation 4757 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4758 single_instruction; 4759 dst : E(write); 4760 src1 : R(read); 4761 MS : R(5); 4762 %} 4763 4764 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4765 single_instruction; 4766 dst : E(write)+4; 4767 src1 : R(read); 4768 src2 : R(read); 4769 MS : R(6); 4770 %} 4771 4772 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4773 single_instruction; 4774 dst : E(write)+4; 4775 src1 : R(read); 4776 MS : R(6); 4777 %} 4778 4779 // Integer Divide reg-reg 4780 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4781 instruction_count(1); multiple_bundles; 4782 dst : E(write); 4783 temp : E(write); 4784 src1 : R(read); 4785 src2 : R(read); 4786 temp : R(read); 4787 MS : R(38); 4788 %} 4789 4790 // Integer Divide reg-imm 4791 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4792 instruction_count(1); multiple_bundles; 4793 dst : E(write); 4794 temp : E(write); 4795 src1 : R(read); 4796 temp : R(read); 4797 MS : R(38); 4798 %} 4799 4800 // Long Divide 4801 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4802 dst : E(write)+71; 4803 src1 : R(read); 4804 src2 : R(read)+1; 4805 MS : R(70); 4806 %} 4807 4808 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4809 dst : E(write)+71; 4810 src1 : R(read); 4811 MS : R(70); 4812 %} 4813 4814 // Floating Point Add Float 4815 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4816 single_instruction; 4817 dst : X(write); 4818 src1 : E(read); 4819 src2 : E(read); 4820 FA : R; 4821 %} 4822 4823 // Floating Point Add Double 4824 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4825 single_instruction; 4826 dst : X(write); 4827 src1 : E(read); 4828 src2 : E(read); 4829 FA : R; 4830 %} 4831 4832 // Floating Point Conditional Move based on integer flags 4833 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4834 single_instruction; 4835 dst : X(write); 4836 src : E(read); 4837 cr : R(read); 4838 FA : R(2); 4839 BR : R(2); 4840 %} 4841 4842 // Floating Point Conditional Move based on integer flags 4843 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4844 single_instruction; 4845 dst : X(write); 4846 src : E(read); 4847 cr : R(read); 4848 FA : R(2); 4849 BR : R(2); 4850 %} 4851 4852 // Floating Point Multiply Float 4853 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4854 single_instruction; 4855 dst : X(write); 4856 src1 : E(read); 4857 src2 : E(read); 4858 FM : R; 4859 %} 4860 4861 // Floating Point Multiply Double 4862 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4863 single_instruction; 4864 dst : X(write); 4865 src1 : E(read); 4866 src2 : E(read); 4867 FM : R; 4868 %} 4869 4870 // Floating Point Divide Float 4871 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4872 single_instruction; 4873 dst : X(write); 4874 src1 : E(read); 4875 src2 : E(read); 4876 FM : R; 4877 FDIV : C(14); 4878 %} 4879 4880 // Floating Point Divide Double 4881 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4882 single_instruction; 4883 dst : X(write); 4884 src1 : E(read); 4885 src2 : E(read); 4886 FM : R; 4887 FDIV : C(17); 4888 %} 4889 4890 // Floating Point Move/Negate/Abs Float 4891 pipe_class faddF_reg(regF dst, regF src) %{ 4892 single_instruction; 4893 dst : W(write); 4894 src : E(read); 4895 FA : R(1); 4896 %} 4897 4898 // Floating Point Move/Negate/Abs Double 4899 pipe_class faddD_reg(regD dst, regD src) %{ 4900 single_instruction; 4901 dst : W(write); 4902 src : E(read); 4903 FA : R; 4904 %} 4905 4906 // Floating Point Convert F->D 4907 pipe_class fcvtF2D(regD dst, regF src) %{ 4908 single_instruction; 4909 dst : X(write); 4910 src : E(read); 4911 FA : R; 4912 %} 4913 4914 // Floating Point Convert I->D 4915 pipe_class fcvtI2D(regD dst, regF src) %{ 4916 single_instruction; 4917 dst : X(write); 4918 src : E(read); 4919 FA : R; 4920 %} 4921 4922 // Floating Point Convert LHi->D 4923 pipe_class fcvtLHi2D(regD dst, regD src) %{ 4924 single_instruction; 4925 dst : X(write); 4926 src : E(read); 4927 FA : R; 4928 %} 4929 4930 // Floating Point Convert L->D 4931 pipe_class fcvtL2D(regD dst, regF src) %{ 4932 single_instruction; 4933 dst : X(write); 4934 src : E(read); 4935 FA : R; 4936 %} 4937 4938 // Floating Point Convert L->F 4939 pipe_class fcvtL2F(regD dst, regF src) %{ 4940 single_instruction; 4941 dst : X(write); 4942 src : E(read); 4943 FA : R; 4944 %} 4945 4946 // Floating Point Convert D->F 4947 pipe_class fcvtD2F(regD dst, regF src) %{ 4948 single_instruction; 4949 dst : X(write); 4950 src : E(read); 4951 FA : R; 4952 %} 4953 4954 // Floating Point Convert I->L 4955 pipe_class fcvtI2L(regD dst, regF src) %{ 4956 single_instruction; 4957 dst : X(write); 4958 src : E(read); 4959 FA : R; 4960 %} 4961 4962 // Floating Point Convert D->F 4963 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4964 instruction_count(1); multiple_bundles; 4965 dst : X(write)+6; 4966 src : E(read); 4967 FA : R; 4968 %} 4969 4970 // Floating Point Convert D->L 4971 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4972 instruction_count(1); multiple_bundles; 4973 dst : X(write)+6; 4974 src : E(read); 4975 FA : R; 4976 %} 4977 4978 // Floating Point Convert F->I 4979 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4980 instruction_count(1); multiple_bundles; 4981 dst : X(write)+6; 4982 src : E(read); 4983 FA : R; 4984 %} 4985 4986 // Floating Point Convert F->L 4987 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4988 instruction_count(1); multiple_bundles; 4989 dst : X(write)+6; 4990 src : E(read); 4991 FA : R; 4992 %} 4993 4994 // Floating Point Convert I->F 4995 pipe_class fcvtI2F(regF dst, regF src) %{ 4996 single_instruction; 4997 dst : X(write); 4998 src : E(read); 4999 FA : R; 5000 %} 5001 5002 // Floating Point Compare 5003 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 5004 single_instruction; 5005 cr : X(write); 5006 src1 : E(read); 5007 src2 : E(read); 5008 FA : R; 5009 %} 5010 5011 // Floating Point Compare 5012 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 5013 single_instruction; 5014 cr : X(write); 5015 src1 : E(read); 5016 src2 : E(read); 5017 FA : R; 5018 %} 5019 5020 // Floating Add Nop 5021 pipe_class fadd_nop() %{ 5022 single_instruction; 5023 FA : R; 5024 %} 5025 5026 // Integer Store to Memory 5027 pipe_class istore_mem_reg(memory mem, iRegI src) %{ 5028 single_instruction; 5029 mem : R(read); 5030 src : C(read); 5031 MS : R; 5032 %} 5033 5034 // Integer Store to Memory 5035 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 5036 single_instruction; 5037 mem : R(read); 5038 src : C(read); 5039 MS : R; 5040 %} 5041 5042 // Integer Store Zero to Memory 5043 pipe_class istore_mem_zero(memory mem, immI0 src) %{ 5044 single_instruction; 5045 mem : R(read); 5046 MS : R; 5047 %} 5048 5049 // Special Stack Slot Store 5050 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 5051 single_instruction; 5052 stkSlot : R(read); 5053 src : C(read); 5054 MS : R; 5055 %} 5056 5057 // Special Stack Slot Store 5058 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 5059 instruction_count(2); multiple_bundles; 5060 stkSlot : R(read); 5061 src : C(read); 5062 MS : R(2); 5063 %} 5064 5065 // Float Store 5066 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 5067 single_instruction; 5068 mem : R(read); 5069 src : C(read); 5070 MS : R; 5071 %} 5072 5073 // Float Store 5074 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 5075 single_instruction; 5076 mem : R(read); 5077 MS : R; 5078 %} 5079 5080 // Double Store 5081 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 5082 instruction_count(1); 5083 mem : R(read); 5084 src : C(read); 5085 MS : R; 5086 %} 5087 5088 // Double Store 5089 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 5090 single_instruction; 5091 mem : R(read); 5092 MS : R; 5093 %} 5094 5095 // Special Stack Slot Float Store 5096 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 5097 single_instruction; 5098 stkSlot : R(read); 5099 src : C(read); 5100 MS : R; 5101 %} 5102 5103 // Special Stack Slot Double Store 5104 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 5105 single_instruction; 5106 stkSlot : R(read); 5107 src : C(read); 5108 MS : R; 5109 %} 5110 5111 // Integer Load (when sign bit propagation not needed) 5112 pipe_class iload_mem(iRegI dst, memory mem) %{ 5113 single_instruction; 5114 mem : R(read); 5115 dst : C(write); 5116 MS : R; 5117 %} 5118 5119 // Integer Load from stack operand 5120 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 5121 single_instruction; 5122 mem : R(read); 5123 dst : C(write); 5124 MS : R; 5125 %} 5126 5127 // Integer Load (when sign bit propagation or masking is needed) 5128 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 5129 single_instruction; 5130 mem : R(read); 5131 dst : M(write); 5132 MS : R; 5133 %} 5134 5135 // Float Load 5136 pipe_class floadF_mem(regF dst, memory mem) %{ 5137 single_instruction; 5138 mem : R(read); 5139 dst : M(write); 5140 MS : R; 5141 %} 5142 5143 // Float Load 5144 pipe_class floadD_mem(regD dst, memory mem) %{ 5145 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 5146 mem : R(read); 5147 dst : M(write); 5148 MS : R; 5149 %} 5150 5151 // Float Load 5152 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 5153 single_instruction; 5154 stkSlot : R(read); 5155 dst : M(write); 5156 MS : R; 5157 %} 5158 5159 // Float Load 5160 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 5161 single_instruction; 5162 stkSlot : R(read); 5163 dst : M(write); 5164 MS : R; 5165 %} 5166 5167 // Memory Nop 5168 pipe_class mem_nop() %{ 5169 single_instruction; 5170 MS : R; 5171 %} 5172 5173 pipe_class sethi(iRegP dst, immI src) %{ 5174 single_instruction; 5175 dst : E(write); 5176 IALU : R; 5177 %} 5178 5179 pipe_class loadPollP(iRegP poll) %{ 5180 single_instruction; 5181 poll : R(read); 5182 MS : R; 5183 %} 5184 5185 pipe_class br(Universe br, label labl) %{ 5186 single_instruction_with_delay_slot; 5187 BR : R; 5188 %} 5189 5190 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 5191 single_instruction_with_delay_slot; 5192 cr : E(read); 5193 BR : R; 5194 %} 5195 5196 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 5197 single_instruction_with_delay_slot; 5198 op1 : E(read); 5199 BR : R; 5200 MS : R; 5201 %} 5202 5203 // Compare and branch 5204 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 5205 instruction_count(2); has_delay_slot; 5206 cr : E(write); 5207 src1 : R(read); 5208 src2 : R(read); 5209 IALU : R; 5210 BR : R; 5211 %} 5212 5213 // Compare and branch 5214 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ 5215 instruction_count(2); has_delay_slot; 5216 cr : E(write); 5217 src1 : R(read); 5218 IALU : R; 5219 BR : R; 5220 %} 5221 5222 // Compare and branch using cbcond 5223 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ 5224 single_instruction; 5225 src1 : E(read); 5226 src2 : E(read); 5227 IALU : R; 5228 BR : R; 5229 %} 5230 5231 // Compare and branch using cbcond 5232 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ 5233 single_instruction; 5234 src1 : E(read); 5235 IALU : R; 5236 BR : R; 5237 %} 5238 5239 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5240 single_instruction_with_delay_slot; 5241 cr : E(read); 5242 BR : R; 5243 %} 5244 5245 pipe_class br_nop() %{ 5246 single_instruction; 5247 BR : R; 5248 %} 5249 5250 pipe_class simple_call(method meth) %{ 5251 instruction_count(2); multiple_bundles; force_serialization; 5252 fixed_latency(100); 5253 BR : R(1); 5254 MS : R(1); 5255 A0 : R(1); 5256 %} 5257 5258 pipe_class compiled_call(method meth) %{ 5259 instruction_count(1); multiple_bundles; force_serialization; 5260 fixed_latency(100); 5261 MS : R(1); 5262 %} 5263 5264 pipe_class call(method meth) %{ 5265 instruction_count(0); multiple_bundles; force_serialization; 5266 fixed_latency(100); 5267 %} 5268 5269 pipe_class tail_call(Universe ignore, label labl) %{ 5270 single_instruction; has_delay_slot; 5271 fixed_latency(100); 5272 BR : R(1); 5273 MS : R(1); 5274 %} 5275 5276 pipe_class ret(Universe ignore) %{ 5277 single_instruction; has_delay_slot; 5278 BR : R(1); 5279 MS : R(1); 5280 %} 5281 5282 pipe_class ret_poll(g3RegP poll) %{ 5283 instruction_count(3); has_delay_slot; 5284 poll : E(read); 5285 MS : R; 5286 %} 5287 5288 // The real do-nothing guy 5289 pipe_class empty( ) %{ 5290 instruction_count(0); 5291 %} 5292 5293 pipe_class long_memory_op() %{ 5294 instruction_count(0); multiple_bundles; force_serialization; 5295 fixed_latency(25); 5296 MS : R(1); 5297 %} 5298 5299 // Check-cast 5300 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5301 array : R(read); 5302 match : R(read); 5303 IALU : R(2); 5304 BR : R(2); 5305 MS : R; 5306 %} 5307 5308 // Convert FPU flags into +1,0,-1 5309 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5310 src1 : E(read); 5311 src2 : E(read); 5312 dst : E(write); 5313 FA : R; 5314 MS : R(2); 5315 BR : R(2); 5316 %} 5317 5318 // Compare for p < q, and conditionally add y 5319 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5320 p : E(read); 5321 q : E(read); 5322 y : E(read); 5323 IALU : R(3) 5324 %} 5325 5326 // Perform a compare, then move conditionally in a branch delay slot. 5327 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5328 src2 : E(read); 5329 srcdst : E(read); 5330 IALU : R; 5331 BR : R; 5332 %} 5333 5334 // Define the class for the Nop node 5335 define %{ 5336 MachNop = ialu_nop; 5337 %} 5338 5339 %} 5340 5341 //----------INSTRUCTIONS------------------------------------------------------- 5342 5343 //------------Special Stack Slot instructions - no match rules----------------- 5344 instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5345 // No match rule to avoid chain rule match. 5346 effect(DEF dst, USE src); 5347 ins_cost(MEMORY_REF_COST); 5348 size(4); 5349 format %{ "LDF $src,$dst\t! stkI to regF" %} 5350 opcode(Assembler::ldf_op3); 5351 ins_encode(simple_form3_mem_reg(src, dst)); 5352 ins_pipe(floadF_stk); 5353 %} 5354 5355 instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5356 // No match rule to avoid chain rule match. 5357 effect(DEF dst, USE src); 5358 ins_cost(MEMORY_REF_COST); 5359 size(4); 5360 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5361 opcode(Assembler::lddf_op3); 5362 ins_encode(simple_form3_mem_reg(src, dst)); 5363 ins_pipe(floadD_stk); 5364 %} 5365 5366 instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5367 // No match rule to avoid chain rule match. 5368 effect(DEF dst, USE src); 5369 ins_cost(MEMORY_REF_COST); 5370 size(4); 5371 format %{ "STF $src,$dst\t! regF to stkI" %} 5372 opcode(Assembler::stf_op3); 5373 ins_encode(simple_form3_mem_reg(dst, src)); 5374 ins_pipe(fstoreF_stk_reg); 5375 %} 5376 5377 instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5378 // No match rule to avoid chain rule match. 5379 effect(DEF dst, USE src); 5380 ins_cost(MEMORY_REF_COST); 5381 size(4); 5382 format %{ "STDF $src,$dst\t! regD to stkL" %} 5383 opcode(Assembler::stdf_op3); 5384 ins_encode(simple_form3_mem_reg(dst, src)); 5385 ins_pipe(fstoreD_stk_reg); 5386 %} 5387 5388 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5389 effect(DEF dst, USE src); 5390 ins_cost(MEMORY_REF_COST*2); 5391 size(8); 5392 format %{ "STW $src,$dst.hi\t! long\n\t" 5393 "STW R_G0,$dst.lo" %} 5394 opcode(Assembler::stw_op3); 5395 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5396 ins_pipe(lstoreI_stk_reg); 5397 %} 5398 5399 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5400 // No match rule to avoid chain rule match. 5401 effect(DEF dst, USE src); 5402 ins_cost(MEMORY_REF_COST); 5403 size(4); 5404 format %{ "STX $src,$dst\t! regL to stkD" %} 5405 opcode(Assembler::stx_op3); 5406 ins_encode(simple_form3_mem_reg( dst, src ) ); 5407 ins_pipe(istore_stk_reg); 5408 %} 5409 5410 //---------- Chain stack slots between similar types -------- 5411 5412 // Load integer from stack slot 5413 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5414 match(Set dst src); 5415 ins_cost(MEMORY_REF_COST); 5416 5417 size(4); 5418 format %{ "LDUW $src,$dst\t!stk" %} 5419 opcode(Assembler::lduw_op3); 5420 ins_encode(simple_form3_mem_reg( src, dst ) ); 5421 ins_pipe(iload_mem); 5422 %} 5423 5424 // Store integer to stack slot 5425 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5426 match(Set dst src); 5427 ins_cost(MEMORY_REF_COST); 5428 5429 size(4); 5430 format %{ "STW $src,$dst\t!stk" %} 5431 opcode(Assembler::stw_op3); 5432 ins_encode(simple_form3_mem_reg( dst, src ) ); 5433 ins_pipe(istore_mem_reg); 5434 %} 5435 5436 // Load long from stack slot 5437 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5438 match(Set dst src); 5439 5440 ins_cost(MEMORY_REF_COST); 5441 size(4); 5442 format %{ "LDX $src,$dst\t! long" %} 5443 opcode(Assembler::ldx_op3); 5444 ins_encode(simple_form3_mem_reg( src, dst ) ); 5445 ins_pipe(iload_mem); 5446 %} 5447 5448 // Store long to stack slot 5449 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5450 match(Set dst src); 5451 5452 ins_cost(MEMORY_REF_COST); 5453 size(4); 5454 format %{ "STX $src,$dst\t! long" %} 5455 opcode(Assembler::stx_op3); 5456 ins_encode(simple_form3_mem_reg( dst, src ) ); 5457 ins_pipe(istore_mem_reg); 5458 %} 5459 5460 #ifdef _LP64 5461 // Load pointer from stack slot, 64-bit encoding 5462 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5463 match(Set dst src); 5464 ins_cost(MEMORY_REF_COST); 5465 size(4); 5466 format %{ "LDX $src,$dst\t!ptr" %} 5467 opcode(Assembler::ldx_op3); 5468 ins_encode(simple_form3_mem_reg( src, dst ) ); 5469 ins_pipe(iload_mem); 5470 %} 5471 5472 // Store pointer to stack slot 5473 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5474 match(Set dst src); 5475 ins_cost(MEMORY_REF_COST); 5476 size(4); 5477 format %{ "STX $src,$dst\t!ptr" %} 5478 opcode(Assembler::stx_op3); 5479 ins_encode(simple_form3_mem_reg( dst, src ) ); 5480 ins_pipe(istore_mem_reg); 5481 %} 5482 #else // _LP64 5483 // Load pointer from stack slot, 32-bit encoding 5484 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5485 match(Set dst src); 5486 ins_cost(MEMORY_REF_COST); 5487 format %{ "LDUW $src,$dst\t!ptr" %} 5488 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5489 ins_encode(simple_form3_mem_reg( src, dst ) ); 5490 ins_pipe(iload_mem); 5491 %} 5492 5493 // Store pointer to stack slot 5494 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5495 match(Set dst src); 5496 ins_cost(MEMORY_REF_COST); 5497 format %{ "STW $src,$dst\t!ptr" %} 5498 opcode(Assembler::stw_op3, Assembler::ldst_op); 5499 ins_encode(simple_form3_mem_reg( dst, src ) ); 5500 ins_pipe(istore_mem_reg); 5501 %} 5502 #endif // _LP64 5503 5504 //------------Special Nop instructions for bundling - no match rules----------- 5505 // Nop using the A0 functional unit 5506 instruct Nop_A0() %{ 5507 ins_cost(0); 5508 5509 format %{ "NOP ! Alu Pipeline" %} 5510 opcode(Assembler::or_op3, Assembler::arith_op); 5511 ins_encode( form2_nop() ); 5512 ins_pipe(ialu_nop_A0); 5513 %} 5514 5515 // Nop using the A1 functional unit 5516 instruct Nop_A1( ) %{ 5517 ins_cost(0); 5518 5519 format %{ "NOP ! Alu Pipeline" %} 5520 opcode(Assembler::or_op3, Assembler::arith_op); 5521 ins_encode( form2_nop() ); 5522 ins_pipe(ialu_nop_A1); 5523 %} 5524 5525 // Nop using the memory functional unit 5526 instruct Nop_MS( ) %{ 5527 ins_cost(0); 5528 5529 format %{ "NOP ! Memory Pipeline" %} 5530 ins_encode( emit_mem_nop ); 5531 ins_pipe(mem_nop); 5532 %} 5533 5534 // Nop using the floating add functional unit 5535 instruct Nop_FA( ) %{ 5536 ins_cost(0); 5537 5538 format %{ "NOP ! Floating Add Pipeline" %} 5539 ins_encode( emit_fadd_nop ); 5540 ins_pipe(fadd_nop); 5541 %} 5542 5543 // Nop using the branch functional unit 5544 instruct Nop_BR( ) %{ 5545 ins_cost(0); 5546 5547 format %{ "NOP ! Branch Pipeline" %} 5548 ins_encode( emit_br_nop ); 5549 ins_pipe(br_nop); 5550 %} 5551 5552 //----------Load/Store/Move Instructions--------------------------------------- 5553 //----------Load Instructions-------------------------------------------------- 5554 // Load Byte (8bit signed) 5555 instruct loadB(iRegI dst, memory mem) %{ 5556 match(Set dst (LoadB mem)); 5557 ins_cost(MEMORY_REF_COST); 5558 5559 size(4); 5560 format %{ "LDSB $mem,$dst\t! byte" %} 5561 ins_encode %{ 5562 __ ldsb($mem$$Address, $dst$$Register); 5563 %} 5564 ins_pipe(iload_mask_mem); 5565 %} 5566 5567 // Load Byte (8bit signed) into a Long Register 5568 instruct loadB2L(iRegL dst, memory mem) %{ 5569 match(Set dst (ConvI2L (LoadB mem))); 5570 ins_cost(MEMORY_REF_COST); 5571 5572 size(4); 5573 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5574 ins_encode %{ 5575 __ ldsb($mem$$Address, $dst$$Register); 5576 %} 5577 ins_pipe(iload_mask_mem); 5578 %} 5579 5580 // Load Unsigned Byte (8bit UNsigned) into an int reg 5581 instruct loadUB(iRegI dst, memory mem) %{ 5582 match(Set dst (LoadUB mem)); 5583 ins_cost(MEMORY_REF_COST); 5584 5585 size(4); 5586 format %{ "LDUB $mem,$dst\t! ubyte" %} 5587 ins_encode %{ 5588 __ ldub($mem$$Address, $dst$$Register); 5589 %} 5590 ins_pipe(iload_mem); 5591 %} 5592 5593 // Load Unsigned Byte (8bit UNsigned) into a Long Register 5594 instruct loadUB2L(iRegL dst, memory mem) %{ 5595 match(Set dst (ConvI2L (LoadUB mem))); 5596 ins_cost(MEMORY_REF_COST); 5597 5598 size(4); 5599 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5600 ins_encode %{ 5601 __ ldub($mem$$Address, $dst$$Register); 5602 %} 5603 ins_pipe(iload_mem); 5604 %} 5605 5606 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register 5607 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ 5608 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5609 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5610 5611 size(2*4); 5612 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" 5613 "AND $dst,$mask,$dst" %} 5614 ins_encode %{ 5615 __ ldub($mem$$Address, $dst$$Register); 5616 __ and3($dst$$Register, $mask$$constant, $dst$$Register); 5617 %} 5618 ins_pipe(iload_mem); 5619 %} 5620 5621 // Load Short (16bit signed) 5622 instruct loadS(iRegI dst, memory mem) %{ 5623 match(Set dst (LoadS mem)); 5624 ins_cost(MEMORY_REF_COST); 5625 5626 size(4); 5627 format %{ "LDSH $mem,$dst\t! short" %} 5628 ins_encode %{ 5629 __ ldsh($mem$$Address, $dst$$Register); 5630 %} 5631 ins_pipe(iload_mask_mem); 5632 %} 5633 5634 // Load Short (16 bit signed) to Byte (8 bit signed) 5635 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5636 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5637 ins_cost(MEMORY_REF_COST); 5638 5639 size(4); 5640 5641 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5642 ins_encode %{ 5643 __ ldsb($mem$$Address, $dst$$Register, 1); 5644 %} 5645 ins_pipe(iload_mask_mem); 5646 %} 5647 5648 // Load Short (16bit signed) into a Long Register 5649 instruct loadS2L(iRegL dst, memory mem) %{ 5650 match(Set dst (ConvI2L (LoadS mem))); 5651 ins_cost(MEMORY_REF_COST); 5652 5653 size(4); 5654 format %{ "LDSH $mem,$dst\t! short -> long" %} 5655 ins_encode %{ 5656 __ ldsh($mem$$Address, $dst$$Register); 5657 %} 5658 ins_pipe(iload_mask_mem); 5659 %} 5660 5661 // Load Unsigned Short/Char (16bit UNsigned) 5662 instruct loadUS(iRegI dst, memory mem) %{ 5663 match(Set dst (LoadUS mem)); 5664 ins_cost(MEMORY_REF_COST); 5665 5666 size(4); 5667 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5668 ins_encode %{ 5669 __ lduh($mem$$Address, $dst$$Register); 5670 %} 5671 ins_pipe(iload_mem); 5672 %} 5673 5674 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5675 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5676 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5677 ins_cost(MEMORY_REF_COST); 5678 5679 size(4); 5680 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5681 ins_encode %{ 5682 __ ldsb($mem$$Address, $dst$$Register, 1); 5683 %} 5684 ins_pipe(iload_mask_mem); 5685 %} 5686 5687 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5688 instruct loadUS2L(iRegL dst, memory mem) %{ 5689 match(Set dst (ConvI2L (LoadUS mem))); 5690 ins_cost(MEMORY_REF_COST); 5691 5692 size(4); 5693 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5694 ins_encode %{ 5695 __ lduh($mem$$Address, $dst$$Register); 5696 %} 5697 ins_pipe(iload_mem); 5698 %} 5699 5700 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5701 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5702 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5703 ins_cost(MEMORY_REF_COST); 5704 5705 size(4); 5706 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5707 ins_encode %{ 5708 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5709 %} 5710 ins_pipe(iload_mem); 5711 %} 5712 5713 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5714 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5715 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5716 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5717 5718 size(2*4); 5719 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5720 "AND $dst,$mask,$dst" %} 5721 ins_encode %{ 5722 Register Rdst = $dst$$Register; 5723 __ lduh($mem$$Address, Rdst); 5724 __ and3(Rdst, $mask$$constant, Rdst); 5725 %} 5726 ins_pipe(iload_mem); 5727 %} 5728 5729 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register 5730 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ 5731 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5732 effect(TEMP dst, TEMP tmp); 5733 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5734 5735 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" 5736 "SET $mask,$tmp\n\t" 5737 "AND $dst,$tmp,$dst" %} 5738 ins_encode %{ 5739 Register Rdst = $dst$$Register; 5740 Register Rtmp = $tmp$$Register; 5741 __ lduh($mem$$Address, Rdst); 5742 __ set($mask$$constant, Rtmp); 5743 __ and3(Rdst, Rtmp, Rdst); 5744 %} 5745 ins_pipe(iload_mem); 5746 %} 5747 5748 // Load Integer 5749 instruct loadI(iRegI dst, memory mem) %{ 5750 match(Set dst (LoadI mem)); 5751 ins_cost(MEMORY_REF_COST); 5752 5753 size(4); 5754 format %{ "LDUW $mem,$dst\t! int" %} 5755 ins_encode %{ 5756 __ lduw($mem$$Address, $dst$$Register); 5757 %} 5758 ins_pipe(iload_mem); 5759 %} 5760 5761 // Load Integer to Byte (8 bit signed) 5762 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5763 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5764 ins_cost(MEMORY_REF_COST); 5765 5766 size(4); 5767 5768 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5769 ins_encode %{ 5770 __ ldsb($mem$$Address, $dst$$Register, 3); 5771 %} 5772 ins_pipe(iload_mask_mem); 5773 %} 5774 5775 // Load Integer to Unsigned Byte (8 bit UNsigned) 5776 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5777 match(Set dst (AndI (LoadI mem) mask)); 5778 ins_cost(MEMORY_REF_COST); 5779 5780 size(4); 5781 5782 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5783 ins_encode %{ 5784 __ ldub($mem$$Address, $dst$$Register, 3); 5785 %} 5786 ins_pipe(iload_mask_mem); 5787 %} 5788 5789 // Load Integer to Short (16 bit signed) 5790 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5791 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5792 ins_cost(MEMORY_REF_COST); 5793 5794 size(4); 5795 5796 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5797 ins_encode %{ 5798 __ ldsh($mem$$Address, $dst$$Register, 2); 5799 %} 5800 ins_pipe(iload_mask_mem); 5801 %} 5802 5803 // Load Integer to Unsigned Short (16 bit UNsigned) 5804 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5805 match(Set dst (AndI (LoadI mem) mask)); 5806 ins_cost(MEMORY_REF_COST); 5807 5808 size(4); 5809 5810 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5811 ins_encode %{ 5812 __ lduh($mem$$Address, $dst$$Register, 2); 5813 %} 5814 ins_pipe(iload_mask_mem); 5815 %} 5816 5817 // Load Integer into a Long Register 5818 instruct loadI2L(iRegL dst, memory mem) %{ 5819 match(Set dst (ConvI2L (LoadI mem))); 5820 ins_cost(MEMORY_REF_COST); 5821 5822 size(4); 5823 format %{ "LDSW $mem,$dst\t! int -> long" %} 5824 ins_encode %{ 5825 __ ldsw($mem$$Address, $dst$$Register); 5826 %} 5827 ins_pipe(iload_mask_mem); 5828 %} 5829 5830 // Load Integer with mask 0xFF into a Long Register 5831 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5832 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5833 ins_cost(MEMORY_REF_COST); 5834 5835 size(4); 5836 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5837 ins_encode %{ 5838 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5839 %} 5840 ins_pipe(iload_mem); 5841 %} 5842 5843 // Load Integer with mask 0xFFFF into a Long Register 5844 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5845 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5846 ins_cost(MEMORY_REF_COST); 5847 5848 size(4); 5849 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5850 ins_encode %{ 5851 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5852 %} 5853 ins_pipe(iload_mem); 5854 %} 5855 5856 // Load Integer with a 12-bit mask into a Long Register 5857 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ 5858 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5859 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5860 5861 size(2*4); 5862 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" 5863 "AND $dst,$mask,$dst" %} 5864 ins_encode %{ 5865 Register Rdst = $dst$$Register; 5866 __ lduw($mem$$Address, Rdst); 5867 __ and3(Rdst, $mask$$constant, Rdst); 5868 %} 5869 ins_pipe(iload_mem); 5870 %} 5871 5872 // Load Integer with a 31-bit mask into a Long Register 5873 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ 5874 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5875 effect(TEMP dst, TEMP tmp); 5876 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5877 5878 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" 5879 "SET $mask,$tmp\n\t" 5880 "AND $dst,$tmp,$dst" %} 5881 ins_encode %{ 5882 Register Rdst = $dst$$Register; 5883 Register Rtmp = $tmp$$Register; 5884 __ lduw($mem$$Address, Rdst); 5885 __ set($mask$$constant, Rtmp); 5886 __ and3(Rdst, Rtmp, Rdst); 5887 %} 5888 ins_pipe(iload_mem); 5889 %} 5890 5891 // Load Unsigned Integer into a Long Register 5892 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ 5893 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5894 ins_cost(MEMORY_REF_COST); 5895 5896 size(4); 5897 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5898 ins_encode %{ 5899 __ lduw($mem$$Address, $dst$$Register); 5900 %} 5901 ins_pipe(iload_mem); 5902 %} 5903 5904 // Load Long - aligned 5905 instruct loadL(iRegL dst, memory mem ) %{ 5906 match(Set dst (LoadL mem)); 5907 ins_cost(MEMORY_REF_COST); 5908 5909 size(4); 5910 format %{ "LDX $mem,$dst\t! long" %} 5911 ins_encode %{ 5912 __ ldx($mem$$Address, $dst$$Register); 5913 %} 5914 ins_pipe(iload_mem); 5915 %} 5916 5917 // Load Long - UNaligned 5918 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5919 match(Set dst (LoadL_unaligned mem)); 5920 effect(KILL tmp); 5921 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5922 size(16); 5923 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5924 "\tLDUW $mem ,$dst\n" 5925 "\tSLLX #32, $dst, $dst\n" 5926 "\tOR $dst, R_O7, $dst" %} 5927 opcode(Assembler::lduw_op3); 5928 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5929 ins_pipe(iload_mem); 5930 %} 5931 5932 // Load Range 5933 instruct loadRange(iRegI dst, memory mem) %{ 5934 match(Set dst (LoadRange mem)); 5935 ins_cost(MEMORY_REF_COST); 5936 5937 size(4); 5938 format %{ "LDUW $mem,$dst\t! range" %} 5939 opcode(Assembler::lduw_op3); 5940 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5941 ins_pipe(iload_mem); 5942 %} 5943 5944 // Load Integer into %f register (for fitos/fitod) 5945 instruct loadI_freg(regF dst, memory mem) %{ 5946 match(Set dst (LoadI mem)); 5947 ins_cost(MEMORY_REF_COST); 5948 size(4); 5949 5950 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5951 opcode(Assembler::ldf_op3); 5952 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5953 ins_pipe(floadF_mem); 5954 %} 5955 5956 // Load Pointer 5957 instruct loadP(iRegP dst, memory mem) %{ 5958 match(Set dst (LoadP mem)); 5959 ins_cost(MEMORY_REF_COST); 5960 size(4); 5961 5962 #ifndef _LP64 5963 format %{ "LDUW $mem,$dst\t! ptr" %} 5964 ins_encode %{ 5965 __ lduw($mem$$Address, $dst$$Register); 5966 %} 5967 #else 5968 format %{ "LDX $mem,$dst\t! ptr" %} 5969 ins_encode %{ 5970 __ ldx($mem$$Address, $dst$$Register); 5971 %} 5972 #endif 5973 ins_pipe(iload_mem); 5974 %} 5975 5976 // Load Compressed Pointer 5977 instruct loadN(iRegN dst, memory mem) %{ 5978 match(Set dst (LoadN mem)); 5979 ins_cost(MEMORY_REF_COST); 5980 size(4); 5981 5982 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5983 ins_encode %{ 5984 __ lduw($mem$$Address, $dst$$Register); 5985 %} 5986 ins_pipe(iload_mem); 5987 %} 5988 5989 // Load Klass Pointer 5990 instruct loadKlass(iRegP dst, memory mem) %{ 5991 match(Set dst (LoadKlass mem)); 5992 ins_cost(MEMORY_REF_COST); 5993 size(4); 5994 5995 #ifndef _LP64 5996 format %{ "LDUW $mem,$dst\t! klass ptr" %} 5997 ins_encode %{ 5998 __ lduw($mem$$Address, $dst$$Register); 5999 %} 6000 #else 6001 format %{ "LDX $mem,$dst\t! klass ptr" %} 6002 ins_encode %{ 6003 __ ldx($mem$$Address, $dst$$Register); 6004 %} 6005 #endif 6006 ins_pipe(iload_mem); 6007 %} 6008 6009 // Load narrow Klass Pointer 6010 instruct loadNKlass(iRegN dst, memory mem) %{ 6011 match(Set dst (LoadNKlass mem)); 6012 ins_cost(MEMORY_REF_COST); 6013 size(4); 6014 6015 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 6016 ins_encode %{ 6017 __ lduw($mem$$Address, $dst$$Register); 6018 %} 6019 ins_pipe(iload_mem); 6020 %} 6021 6022 // Load Double 6023 instruct loadD(regD dst, memory mem) %{ 6024 match(Set dst (LoadD mem)); 6025 ins_cost(MEMORY_REF_COST); 6026 6027 size(4); 6028 format %{ "LDDF $mem,$dst" %} 6029 opcode(Assembler::lddf_op3); 6030 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6031 ins_pipe(floadD_mem); 6032 %} 6033 6034 // Load Double - UNaligned 6035 instruct loadD_unaligned(regD_low dst, memory mem ) %{ 6036 match(Set dst (LoadD_unaligned mem)); 6037 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 6038 size(8); 6039 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 6040 "\tLDF $mem+4,$dst.lo\t!" %} 6041 opcode(Assembler::ldf_op3); 6042 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 6043 ins_pipe(iload_mem); 6044 %} 6045 6046 // Load Float 6047 instruct loadF(regF dst, memory mem) %{ 6048 match(Set dst (LoadF mem)); 6049 ins_cost(MEMORY_REF_COST); 6050 6051 size(4); 6052 format %{ "LDF $mem,$dst" %} 6053 opcode(Assembler::ldf_op3); 6054 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6055 ins_pipe(floadF_mem); 6056 %} 6057 6058 // Load Constant 6059 instruct loadConI( iRegI dst, immI src ) %{ 6060 match(Set dst src); 6061 ins_cost(DEFAULT_COST * 3/2); 6062 format %{ "SET $src,$dst" %} 6063 ins_encode( Set32(src, dst) ); 6064 ins_pipe(ialu_hi_lo_reg); 6065 %} 6066 6067 instruct loadConI13( iRegI dst, immI13 src ) %{ 6068 match(Set dst src); 6069 6070 size(4); 6071 format %{ "MOV $src,$dst" %} 6072 ins_encode( Set13( src, dst ) ); 6073 ins_pipe(ialu_imm); 6074 %} 6075 6076 #ifndef _LP64 6077 instruct loadConP(iRegP dst, immP con) %{ 6078 match(Set dst con); 6079 ins_cost(DEFAULT_COST * 3/2); 6080 format %{ "SET $con,$dst\t!ptr" %} 6081 ins_encode %{ 6082 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 6083 intptr_t val = $con$$constant; 6084 if (constant_reloc == relocInfo::oop_type) { 6085 __ set_oop_constant((jobject) val, $dst$$Register); 6086 } else if (constant_reloc == relocInfo::metadata_type) { 6087 __ set_metadata_constant((Metadata*)val, $dst$$Register); 6088 } else { // non-oop pointers, e.g. card mark base, heap top 6089 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 6090 __ set(val, $dst$$Register); 6091 } 6092 %} 6093 ins_pipe(loadConP); 6094 %} 6095 #else 6096 instruct loadConP_set(iRegP dst, immP_set con) %{ 6097 match(Set dst con); 6098 ins_cost(DEFAULT_COST * 3/2); 6099 format %{ "SET $con,$dst\t! ptr" %} 6100 ins_encode %{ 6101 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 6102 intptr_t val = $con$$constant; 6103 if (constant_reloc == relocInfo::oop_type) { 6104 __ set_oop_constant((jobject) val, $dst$$Register); 6105 } else if (constant_reloc == relocInfo::metadata_type) { 6106 __ set_metadata_constant((Metadata*)val, $dst$$Register); 6107 } else { // non-oop pointers, e.g. card mark base, heap top 6108 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 6109 __ set(val, $dst$$Register); 6110 } 6111 %} 6112 ins_pipe(loadConP); 6113 %} 6114 6115 instruct loadConP_load(iRegP dst, immP_load con) %{ 6116 match(Set dst con); 6117 ins_cost(MEMORY_REF_COST); 6118 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} 6119 ins_encode %{ 6120 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 6121 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); 6122 %} 6123 ins_pipe(loadConP); 6124 %} 6125 6126 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ 6127 match(Set dst con); 6128 ins_cost(DEFAULT_COST * 3/2); 6129 format %{ "SET $con,$dst\t! non-oop ptr" %} 6130 ins_encode %{ 6131 __ set($con$$constant, $dst$$Register); 6132 %} 6133 ins_pipe(loadConP); 6134 %} 6135 #endif // _LP64 6136 6137 instruct loadConP0(iRegP dst, immP0 src) %{ 6138 match(Set dst src); 6139 6140 size(4); 6141 format %{ "CLR $dst\t!ptr" %} 6142 ins_encode %{ 6143 __ clr($dst$$Register); 6144 %} 6145 ins_pipe(ialu_imm); 6146 %} 6147 6148 instruct loadConP_poll(iRegP dst, immP_poll src) %{ 6149 match(Set dst src); 6150 ins_cost(DEFAULT_COST); 6151 format %{ "SET $src,$dst\t!ptr" %} 6152 ins_encode %{ 6153 AddressLiteral polling_page(os::get_polling_page()); 6154 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 6155 %} 6156 ins_pipe(loadConP_poll); 6157 %} 6158 6159 instruct loadConN0(iRegN dst, immN0 src) %{ 6160 match(Set dst src); 6161 6162 size(4); 6163 format %{ "CLR $dst\t! compressed NULL ptr" %} 6164 ins_encode %{ 6165 __ clr($dst$$Register); 6166 %} 6167 ins_pipe(ialu_imm); 6168 %} 6169 6170 instruct loadConN(iRegN dst, immN src) %{ 6171 match(Set dst src); 6172 ins_cost(DEFAULT_COST * 3/2); 6173 format %{ "SET $src,$dst\t! compressed ptr" %} 6174 ins_encode %{ 6175 Register dst = $dst$$Register; 6176 __ set_narrow_oop((jobject)$src$$constant, dst); 6177 %} 6178 ins_pipe(ialu_hi_lo_reg); 6179 %} 6180 6181 instruct loadConNKlass(iRegN dst, immNKlass src) %{ 6182 match(Set dst src); 6183 ins_cost(DEFAULT_COST * 3/2); 6184 format %{ "SET $src,$dst\t! compressed klass ptr" %} 6185 ins_encode %{ 6186 Register dst = $dst$$Register; 6187 __ set_narrow_klass((Klass*)$src$$constant, dst); 6188 %} 6189 ins_pipe(ialu_hi_lo_reg); 6190 %} 6191 6192 // Materialize long value (predicated by immL_cheap). 6193 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ 6194 match(Set dst con); 6195 effect(KILL tmp); 6196 ins_cost(DEFAULT_COST * 3); 6197 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} 6198 ins_encode %{ 6199 __ set64($con$$constant, $dst$$Register, $tmp$$Register); 6200 %} 6201 ins_pipe(loadConL); 6202 %} 6203 6204 // Load long value from constant table (predicated by immL_expensive). 6205 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ 6206 match(Set dst con); 6207 ins_cost(MEMORY_REF_COST); 6208 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} 6209 ins_encode %{ 6210 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 6211 __ ldx($constanttablebase, con_offset, $dst$$Register); 6212 %} 6213 ins_pipe(loadConL); 6214 %} 6215 6216 instruct loadConL0( iRegL dst, immL0 src ) %{ 6217 match(Set dst src); 6218 ins_cost(DEFAULT_COST); 6219 size(4); 6220 format %{ "CLR $dst\t! long" %} 6221 ins_encode( Set13( src, dst ) ); 6222 ins_pipe(ialu_imm); 6223 %} 6224 6225 instruct loadConL13( iRegL dst, immL13 src ) %{ 6226 match(Set dst src); 6227 ins_cost(DEFAULT_COST * 2); 6228 6229 size(4); 6230 format %{ "MOV $src,$dst\t! long" %} 6231 ins_encode( Set13( src, dst ) ); 6232 ins_pipe(ialu_imm); 6233 %} 6234 6235 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ 6236 match(Set dst con); 6237 effect(KILL tmp); 6238 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} 6239 ins_encode %{ 6240 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 6241 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); 6242 %} 6243 ins_pipe(loadConFD); 6244 %} 6245 6246 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ 6247 match(Set dst con); 6248 effect(KILL tmp); 6249 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} 6250 ins_encode %{ 6251 // XXX This is a quick fix for 6833573. 6252 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 6253 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 6254 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 6255 %} 6256 ins_pipe(loadConFD); 6257 %} 6258 6259 // Prefetch instructions. 6260 // Must be safe to execute with invalid address (cannot fault). 6261 6262 instruct prefetchr( memory mem ) %{ 6263 match( PrefetchRead mem ); 6264 ins_cost(MEMORY_REF_COST); 6265 size(4); 6266 6267 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} 6268 opcode(Assembler::prefetch_op3); 6269 ins_encode( form3_mem_prefetch_read( mem ) ); 6270 ins_pipe(iload_mem); 6271 %} 6272 6273 instruct prefetchw( memory mem ) %{ 6274 match( PrefetchWrite mem ); 6275 ins_cost(MEMORY_REF_COST); 6276 size(4); 6277 6278 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} 6279 opcode(Assembler::prefetch_op3); 6280 ins_encode( form3_mem_prefetch_write( mem ) ); 6281 ins_pipe(iload_mem); 6282 %} 6283 6284 // Prefetch instructions for allocation. 6285 6286 instruct prefetchAlloc( memory mem ) %{ 6287 predicate(AllocatePrefetchInstr == 0); 6288 match( PrefetchAllocation mem ); 6289 ins_cost(MEMORY_REF_COST); 6290 size(4); 6291 6292 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} 6293 opcode(Assembler::prefetch_op3); 6294 ins_encode( form3_mem_prefetch_write( mem ) ); 6295 ins_pipe(iload_mem); 6296 %} 6297 6298 // Use BIS instruction to prefetch for allocation. 6299 // Could fault, need space at the end of TLAB. 6300 instruct prefetchAlloc_bis( iRegP dst ) %{ 6301 predicate(AllocatePrefetchInstr == 1); 6302 match( PrefetchAllocation dst ); 6303 ins_cost(MEMORY_REF_COST); 6304 size(4); 6305 6306 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} 6307 ins_encode %{ 6308 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); 6309 %} 6310 ins_pipe(istore_mem_reg); 6311 %} 6312 6313 // Next code is used for finding next cache line address to prefetch. 6314 #ifndef _LP64 6315 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ 6316 match(Set dst (CastX2P (AndI (CastP2X src) mask))); 6317 ins_cost(DEFAULT_COST); 6318 size(4); 6319 6320 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 6321 ins_encode %{ 6322 __ and3($src$$Register, $mask$$constant, $dst$$Register); 6323 %} 6324 ins_pipe(ialu_reg_imm); 6325 %} 6326 #else 6327 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ 6328 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 6329 ins_cost(DEFAULT_COST); 6330 size(4); 6331 6332 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 6333 ins_encode %{ 6334 __ and3($src$$Register, $mask$$constant, $dst$$Register); 6335 %} 6336 ins_pipe(ialu_reg_imm); 6337 %} 6338 #endif 6339 6340 //----------Store Instructions------------------------------------------------- 6341 // Store Byte 6342 instruct storeB(memory mem, iRegI src) %{ 6343 match(Set mem (StoreB mem src)); 6344 ins_cost(MEMORY_REF_COST); 6345 6346 size(4); 6347 format %{ "STB $src,$mem\t! byte" %} 6348 opcode(Assembler::stb_op3); 6349 ins_encode(simple_form3_mem_reg( mem, src ) ); 6350 ins_pipe(istore_mem_reg); 6351 %} 6352 6353 instruct storeB0(memory mem, immI0 src) %{ 6354 match(Set mem (StoreB mem src)); 6355 ins_cost(MEMORY_REF_COST); 6356 6357 size(4); 6358 format %{ "STB $src,$mem\t! byte" %} 6359 opcode(Assembler::stb_op3); 6360 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6361 ins_pipe(istore_mem_zero); 6362 %} 6363 6364 instruct storeCM0(memory mem, immI0 src) %{ 6365 match(Set mem (StoreCM mem src)); 6366 ins_cost(MEMORY_REF_COST); 6367 6368 size(4); 6369 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 6370 opcode(Assembler::stb_op3); 6371 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6372 ins_pipe(istore_mem_zero); 6373 %} 6374 6375 // Store Char/Short 6376 instruct storeC(memory mem, iRegI src) %{ 6377 match(Set mem (StoreC mem src)); 6378 ins_cost(MEMORY_REF_COST); 6379 6380 size(4); 6381 format %{ "STH $src,$mem\t! short" %} 6382 opcode(Assembler::sth_op3); 6383 ins_encode(simple_form3_mem_reg( mem, src ) ); 6384 ins_pipe(istore_mem_reg); 6385 %} 6386 6387 instruct storeC0(memory mem, immI0 src) %{ 6388 match(Set mem (StoreC mem src)); 6389 ins_cost(MEMORY_REF_COST); 6390 6391 size(4); 6392 format %{ "STH $src,$mem\t! short" %} 6393 opcode(Assembler::sth_op3); 6394 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6395 ins_pipe(istore_mem_zero); 6396 %} 6397 6398 // Store Integer 6399 instruct storeI(memory mem, iRegI src) %{ 6400 match(Set mem (StoreI mem src)); 6401 ins_cost(MEMORY_REF_COST); 6402 6403 size(4); 6404 format %{ "STW $src,$mem" %} 6405 opcode(Assembler::stw_op3); 6406 ins_encode(simple_form3_mem_reg( mem, src ) ); 6407 ins_pipe(istore_mem_reg); 6408 %} 6409 6410 // Store Long 6411 instruct storeL(memory mem, iRegL src) %{ 6412 match(Set mem (StoreL mem src)); 6413 ins_cost(MEMORY_REF_COST); 6414 size(4); 6415 format %{ "STX $src,$mem\t! long" %} 6416 opcode(Assembler::stx_op3); 6417 ins_encode(simple_form3_mem_reg( mem, src ) ); 6418 ins_pipe(istore_mem_reg); 6419 %} 6420 6421 instruct storeI0(memory mem, immI0 src) %{ 6422 match(Set mem (StoreI mem src)); 6423 ins_cost(MEMORY_REF_COST); 6424 6425 size(4); 6426 format %{ "STW $src,$mem" %} 6427 opcode(Assembler::stw_op3); 6428 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6429 ins_pipe(istore_mem_zero); 6430 %} 6431 6432 instruct storeL0(memory mem, immL0 src) %{ 6433 match(Set mem (StoreL mem src)); 6434 ins_cost(MEMORY_REF_COST); 6435 6436 size(4); 6437 format %{ "STX $src,$mem" %} 6438 opcode(Assembler::stx_op3); 6439 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6440 ins_pipe(istore_mem_zero); 6441 %} 6442 6443 // Store Integer from float register (used after fstoi) 6444 instruct storeI_Freg(memory mem, regF src) %{ 6445 match(Set mem (StoreI mem src)); 6446 ins_cost(MEMORY_REF_COST); 6447 6448 size(4); 6449 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6450 opcode(Assembler::stf_op3); 6451 ins_encode(simple_form3_mem_reg( mem, src ) ); 6452 ins_pipe(fstoreF_mem_reg); 6453 %} 6454 6455 // Store Pointer 6456 instruct storeP(memory dst, sp_ptr_RegP src) %{ 6457 match(Set dst (StoreP dst src)); 6458 ins_cost(MEMORY_REF_COST); 6459 size(4); 6460 6461 #ifndef _LP64 6462 format %{ "STW $src,$dst\t! ptr" %} 6463 opcode(Assembler::stw_op3, 0, REGP_OP); 6464 #else 6465 format %{ "STX $src,$dst\t! ptr" %} 6466 opcode(Assembler::stx_op3, 0, REGP_OP); 6467 #endif 6468 ins_encode( form3_mem_reg( dst, src ) ); 6469 ins_pipe(istore_mem_spORreg); 6470 %} 6471 6472 instruct storeP0(memory dst, immP0 src) %{ 6473 match(Set dst (StoreP dst src)); 6474 ins_cost(MEMORY_REF_COST); 6475 size(4); 6476 6477 #ifndef _LP64 6478 format %{ "STW $src,$dst\t! ptr" %} 6479 opcode(Assembler::stw_op3, 0, REGP_OP); 6480 #else 6481 format %{ "STX $src,$dst\t! ptr" %} 6482 opcode(Assembler::stx_op3, 0, REGP_OP); 6483 #endif 6484 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6485 ins_pipe(istore_mem_zero); 6486 %} 6487 6488 // Store Compressed Pointer 6489 instruct storeN(memory dst, iRegN src) %{ 6490 match(Set dst (StoreN dst src)); 6491 ins_cost(MEMORY_REF_COST); 6492 size(4); 6493 6494 format %{ "STW $src,$dst\t! compressed ptr" %} 6495 ins_encode %{ 6496 Register base = as_Register($dst$$base); 6497 Register index = as_Register($dst$$index); 6498 Register src = $src$$Register; 6499 if (index != G0) { 6500 __ stw(src, base, index); 6501 } else { 6502 __ stw(src, base, $dst$$disp); 6503 } 6504 %} 6505 ins_pipe(istore_mem_spORreg); 6506 %} 6507 6508 instruct storeNKlass(memory dst, iRegN src) %{ 6509 match(Set dst (StoreNKlass dst src)); 6510 ins_cost(MEMORY_REF_COST); 6511 size(4); 6512 6513 format %{ "STW $src,$dst\t! compressed klass ptr" %} 6514 ins_encode %{ 6515 Register base = as_Register($dst$$base); 6516 Register index = as_Register($dst$$index); 6517 Register src = $src$$Register; 6518 if (index != G0) { 6519 __ stw(src, base, index); 6520 } else { 6521 __ stw(src, base, $dst$$disp); 6522 } 6523 %} 6524 ins_pipe(istore_mem_spORreg); 6525 %} 6526 6527 instruct storeN0(memory dst, immN0 src) %{ 6528 match(Set dst (StoreN dst src)); 6529 ins_cost(MEMORY_REF_COST); 6530 size(4); 6531 6532 format %{ "STW $src,$dst\t! compressed ptr" %} 6533 ins_encode %{ 6534 Register base = as_Register($dst$$base); 6535 Register index = as_Register($dst$$index); 6536 if (index != G0) { 6537 __ stw(0, base, index); 6538 } else { 6539 __ stw(0, base, $dst$$disp); 6540 } 6541 %} 6542 ins_pipe(istore_mem_zero); 6543 %} 6544 6545 // Store Double 6546 instruct storeD( memory mem, regD src) %{ 6547 match(Set mem (StoreD mem src)); 6548 ins_cost(MEMORY_REF_COST); 6549 6550 size(4); 6551 format %{ "STDF $src,$mem" %} 6552 opcode(Assembler::stdf_op3); 6553 ins_encode(simple_form3_mem_reg( mem, src ) ); 6554 ins_pipe(fstoreD_mem_reg); 6555 %} 6556 6557 instruct storeD0( memory mem, immD0 src) %{ 6558 match(Set mem (StoreD mem src)); 6559 ins_cost(MEMORY_REF_COST); 6560 6561 size(4); 6562 format %{ "STX $src,$mem" %} 6563 opcode(Assembler::stx_op3); 6564 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6565 ins_pipe(fstoreD_mem_zero); 6566 %} 6567 6568 // Store Float 6569 instruct storeF( memory mem, regF src) %{ 6570 match(Set mem (StoreF mem src)); 6571 ins_cost(MEMORY_REF_COST); 6572 6573 size(4); 6574 format %{ "STF $src,$mem" %} 6575 opcode(Assembler::stf_op3); 6576 ins_encode(simple_form3_mem_reg( mem, src ) ); 6577 ins_pipe(fstoreF_mem_reg); 6578 %} 6579 6580 instruct storeF0( memory mem, immF0 src) %{ 6581 match(Set mem (StoreF mem src)); 6582 ins_cost(MEMORY_REF_COST); 6583 6584 size(4); 6585 format %{ "STW $src,$mem\t! storeF0" %} 6586 opcode(Assembler::stw_op3); 6587 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6588 ins_pipe(fstoreF_mem_zero); 6589 %} 6590 6591 // Convert oop pointer into compressed form 6592 instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6593 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6594 match(Set dst (EncodeP src)); 6595 format %{ "encode_heap_oop $src, $dst" %} 6596 ins_encode %{ 6597 __ encode_heap_oop($src$$Register, $dst$$Register); 6598 %} 6599 ins_pipe(ialu_reg); 6600 %} 6601 6602 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6603 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6604 match(Set dst (EncodeP src)); 6605 format %{ "encode_heap_oop_not_null $src, $dst" %} 6606 ins_encode %{ 6607 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6608 %} 6609 ins_pipe(ialu_reg); 6610 %} 6611 6612 instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6613 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6614 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6615 match(Set dst (DecodeN src)); 6616 format %{ "decode_heap_oop $src, $dst" %} 6617 ins_encode %{ 6618 __ decode_heap_oop($src$$Register, $dst$$Register); 6619 %} 6620 ins_pipe(ialu_reg); 6621 %} 6622 6623 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6624 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6625 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6626 match(Set dst (DecodeN src)); 6627 format %{ "decode_heap_oop_not_null $src, $dst" %} 6628 ins_encode %{ 6629 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6630 %} 6631 ins_pipe(ialu_reg); 6632 %} 6633 6634 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ 6635 match(Set dst (EncodePKlass src)); 6636 format %{ "encode_klass_not_null $src, $dst" %} 6637 ins_encode %{ 6638 __ encode_klass_not_null($src$$Register, $dst$$Register); 6639 %} 6640 ins_pipe(ialu_reg); 6641 %} 6642 6643 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ 6644 match(Set dst (DecodeNKlass src)); 6645 format %{ "decode_klass_not_null $src, $dst" %} 6646 ins_encode %{ 6647 __ decode_klass_not_null($src$$Register, $dst$$Register); 6648 %} 6649 ins_pipe(ialu_reg); 6650 %} 6651 6652 //----------MemBar Instructions----------------------------------------------- 6653 // Memory barrier flavors 6654 6655 instruct membar_acquire() %{ 6656 match(MemBarAcquire); 6657 match(LoadFence); 6658 ins_cost(4*MEMORY_REF_COST); 6659 6660 size(0); 6661 format %{ "MEMBAR-acquire" %} 6662 ins_encode( enc_membar_acquire ); 6663 ins_pipe(long_memory_op); 6664 %} 6665 6666 instruct membar_acquire_lock() %{ 6667 match(MemBarAcquireLock); 6668 ins_cost(0); 6669 6670 size(0); 6671 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6672 ins_encode( ); 6673 ins_pipe(empty); 6674 %} 6675 6676 instruct membar_release() %{ 6677 match(MemBarRelease); 6678 match(StoreFence); 6679 ins_cost(4*MEMORY_REF_COST); 6680 6681 size(0); 6682 format %{ "MEMBAR-release" %} 6683 ins_encode( enc_membar_release ); 6684 ins_pipe(long_memory_op); 6685 %} 6686 6687 instruct membar_release_lock() %{ 6688 match(MemBarReleaseLock); 6689 ins_cost(0); 6690 6691 size(0); 6692 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6693 ins_encode( ); 6694 ins_pipe(empty); 6695 %} 6696 6697 instruct membar_volatile() %{ 6698 match(MemBarVolatile); 6699 ins_cost(4*MEMORY_REF_COST); 6700 6701 size(4); 6702 format %{ "MEMBAR-volatile" %} 6703 ins_encode( enc_membar_volatile ); 6704 ins_pipe(long_memory_op); 6705 %} 6706 6707 instruct unnecessary_membar_volatile() %{ 6708 match(MemBarVolatile); 6709 predicate(Matcher::post_store_load_barrier(n)); 6710 ins_cost(0); 6711 6712 size(0); 6713 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6714 ins_encode( ); 6715 ins_pipe(empty); 6716 %} 6717 6718 instruct membar_storestore() %{ 6719 match(MemBarStoreStore); 6720 ins_cost(0); 6721 6722 size(0); 6723 format %{ "!MEMBAR-storestore (empty encoding)" %} 6724 ins_encode( ); 6725 ins_pipe(empty); 6726 %} 6727 6728 //----------Register Move Instructions----------------------------------------- 6729 instruct roundDouble_nop(regD dst) %{ 6730 match(Set dst (RoundDouble dst)); 6731 ins_cost(0); 6732 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6733 ins_encode( ); 6734 ins_pipe(empty); 6735 %} 6736 6737 6738 instruct roundFloat_nop(regF dst) %{ 6739 match(Set dst (RoundFloat dst)); 6740 ins_cost(0); 6741 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6742 ins_encode( ); 6743 ins_pipe(empty); 6744 %} 6745 6746 6747 // Cast Index to Pointer for unsafe natives 6748 instruct castX2P(iRegX src, iRegP dst) %{ 6749 match(Set dst (CastX2P src)); 6750 6751 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6752 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6753 ins_pipe(ialu_reg); 6754 %} 6755 6756 // Cast Pointer to Index for unsafe natives 6757 instruct castP2X(iRegP src, iRegX dst) %{ 6758 match(Set dst (CastP2X src)); 6759 6760 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6761 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6762 ins_pipe(ialu_reg); 6763 %} 6764 6765 instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6766 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6767 match(Set stkSlot src); // chain rule 6768 ins_cost(MEMORY_REF_COST); 6769 format %{ "STDF $src,$stkSlot\t!stk" %} 6770 opcode(Assembler::stdf_op3); 6771 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6772 ins_pipe(fstoreD_stk_reg); 6773 %} 6774 6775 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6776 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6777 match(Set dst stkSlot); // chain rule 6778 ins_cost(MEMORY_REF_COST); 6779 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6780 opcode(Assembler::lddf_op3); 6781 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6782 ins_pipe(floadD_stk); 6783 %} 6784 6785 instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6786 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6787 match(Set stkSlot src); // chain rule 6788 ins_cost(MEMORY_REF_COST); 6789 format %{ "STF $src,$stkSlot\t!stk" %} 6790 opcode(Assembler::stf_op3); 6791 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6792 ins_pipe(fstoreF_stk_reg); 6793 %} 6794 6795 //----------Conditional Move--------------------------------------------------- 6796 // Conditional move 6797 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6798 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6799 ins_cost(150); 6800 format %{ "MOV$cmp $pcc,$src,$dst" %} 6801 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6802 ins_pipe(ialu_reg); 6803 %} 6804 6805 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6806 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6807 ins_cost(140); 6808 format %{ "MOV$cmp $pcc,$src,$dst" %} 6809 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6810 ins_pipe(ialu_imm); 6811 %} 6812 6813 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6814 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6815 ins_cost(150); 6816 size(4); 6817 format %{ "MOV$cmp $icc,$src,$dst" %} 6818 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6819 ins_pipe(ialu_reg); 6820 %} 6821 6822 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6823 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6824 ins_cost(140); 6825 size(4); 6826 format %{ "MOV$cmp $icc,$src,$dst" %} 6827 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6828 ins_pipe(ialu_imm); 6829 %} 6830 6831 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6832 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6833 ins_cost(150); 6834 size(4); 6835 format %{ "MOV$cmp $icc,$src,$dst" %} 6836 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6837 ins_pipe(ialu_reg); 6838 %} 6839 6840 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6841 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6842 ins_cost(140); 6843 size(4); 6844 format %{ "MOV$cmp $icc,$src,$dst" %} 6845 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6846 ins_pipe(ialu_imm); 6847 %} 6848 6849 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6850 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6851 ins_cost(150); 6852 size(4); 6853 format %{ "MOV$cmp $fcc,$src,$dst" %} 6854 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6855 ins_pipe(ialu_reg); 6856 %} 6857 6858 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6859 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6860 ins_cost(140); 6861 size(4); 6862 format %{ "MOV$cmp $fcc,$src,$dst" %} 6863 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6864 ins_pipe(ialu_imm); 6865 %} 6866 6867 // Conditional move for RegN. Only cmov(reg,reg). 6868 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6869 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6870 ins_cost(150); 6871 format %{ "MOV$cmp $pcc,$src,$dst" %} 6872 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6873 ins_pipe(ialu_reg); 6874 %} 6875 6876 // This instruction also works with CmpN so we don't need cmovNN_reg. 6877 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6878 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6879 ins_cost(150); 6880 size(4); 6881 format %{ "MOV$cmp $icc,$src,$dst" %} 6882 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6883 ins_pipe(ialu_reg); 6884 %} 6885 6886 // This instruction also works with CmpN so we don't need cmovNN_reg. 6887 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6888 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6889 ins_cost(150); 6890 size(4); 6891 format %{ "MOV$cmp $icc,$src,$dst" %} 6892 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6893 ins_pipe(ialu_reg); 6894 %} 6895 6896 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6897 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6898 ins_cost(150); 6899 size(4); 6900 format %{ "MOV$cmp $fcc,$src,$dst" %} 6901 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6902 ins_pipe(ialu_reg); 6903 %} 6904 6905 // Conditional move 6906 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6907 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6908 ins_cost(150); 6909 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6910 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6911 ins_pipe(ialu_reg); 6912 %} 6913 6914 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6915 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6916 ins_cost(140); 6917 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6918 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6919 ins_pipe(ialu_imm); 6920 %} 6921 6922 // This instruction also works with CmpN so we don't need cmovPN_reg. 6923 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6924 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6925 ins_cost(150); 6926 6927 size(4); 6928 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6929 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6930 ins_pipe(ialu_reg); 6931 %} 6932 6933 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6934 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6935 ins_cost(150); 6936 6937 size(4); 6938 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6939 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6940 ins_pipe(ialu_reg); 6941 %} 6942 6943 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6944 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6945 ins_cost(140); 6946 6947 size(4); 6948 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6949 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6950 ins_pipe(ialu_imm); 6951 %} 6952 6953 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6954 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6955 ins_cost(140); 6956 6957 size(4); 6958 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6959 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6960 ins_pipe(ialu_imm); 6961 %} 6962 6963 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6964 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6965 ins_cost(150); 6966 size(4); 6967 format %{ "MOV$cmp $fcc,$src,$dst" %} 6968 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6969 ins_pipe(ialu_imm); 6970 %} 6971 6972 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6973 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6974 ins_cost(140); 6975 size(4); 6976 format %{ "MOV$cmp $fcc,$src,$dst" %} 6977 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6978 ins_pipe(ialu_imm); 6979 %} 6980 6981 // Conditional move 6982 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6983 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6984 ins_cost(150); 6985 opcode(0x101); 6986 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6987 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6988 ins_pipe(int_conditional_float_move); 6989 %} 6990 6991 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6992 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6993 ins_cost(150); 6994 6995 size(4); 6996 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6997 opcode(0x101); 6998 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6999 ins_pipe(int_conditional_float_move); 7000 %} 7001 7002 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 7003 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 7004 ins_cost(150); 7005 7006 size(4); 7007 format %{ "FMOVS$cmp $icc,$src,$dst" %} 7008 opcode(0x101); 7009 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7010 ins_pipe(int_conditional_float_move); 7011 %} 7012 7013 // Conditional move, 7014 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 7015 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 7016 ins_cost(150); 7017 size(4); 7018 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 7019 opcode(0x1); 7020 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 7021 ins_pipe(int_conditional_double_move); 7022 %} 7023 7024 // Conditional move 7025 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 7026 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 7027 ins_cost(150); 7028 size(4); 7029 opcode(0x102); 7030 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 7031 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 7032 ins_pipe(int_conditional_double_move); 7033 %} 7034 7035 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 7036 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 7037 ins_cost(150); 7038 7039 size(4); 7040 format %{ "FMOVD$cmp $icc,$src,$dst" %} 7041 opcode(0x102); 7042 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7043 ins_pipe(int_conditional_double_move); 7044 %} 7045 7046 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 7047 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 7048 ins_cost(150); 7049 7050 size(4); 7051 format %{ "FMOVD$cmp $icc,$src,$dst" %} 7052 opcode(0x102); 7053 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7054 ins_pipe(int_conditional_double_move); 7055 %} 7056 7057 // Conditional move, 7058 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 7059 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 7060 ins_cost(150); 7061 size(4); 7062 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 7063 opcode(0x2); 7064 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 7065 ins_pipe(int_conditional_double_move); 7066 %} 7067 7068 // Conditional move 7069 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 7070 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 7071 ins_cost(150); 7072 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 7073 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 7074 ins_pipe(ialu_reg); 7075 %} 7076 7077 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 7078 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 7079 ins_cost(140); 7080 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 7081 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 7082 ins_pipe(ialu_imm); 7083 %} 7084 7085 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 7086 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 7087 ins_cost(150); 7088 7089 size(4); 7090 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 7091 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 7092 ins_pipe(ialu_reg); 7093 %} 7094 7095 7096 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 7097 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 7098 ins_cost(150); 7099 7100 size(4); 7101 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 7102 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 7103 ins_pipe(ialu_reg); 7104 %} 7105 7106 7107 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 7108 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 7109 ins_cost(150); 7110 7111 size(4); 7112 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 7113 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 7114 ins_pipe(ialu_reg); 7115 %} 7116 7117 7118 7119 //----------OS and Locking Instructions---------------------------------------- 7120 7121 // This name is KNOWN by the ADLC and cannot be changed. 7122 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 7123 // for this guy. 7124 instruct tlsLoadP(g2RegP dst) %{ 7125 match(Set dst (ThreadLocal)); 7126 7127 size(0); 7128 ins_cost(0); 7129 format %{ "# TLS is in G2" %} 7130 ins_encode( /*empty encoding*/ ); 7131 ins_pipe(ialu_none); 7132 %} 7133 7134 instruct checkCastPP( iRegP dst ) %{ 7135 match(Set dst (CheckCastPP dst)); 7136 7137 size(0); 7138 format %{ "# checkcastPP of $dst" %} 7139 ins_encode( /*empty encoding*/ ); 7140 ins_pipe(empty); 7141 %} 7142 7143 7144 instruct castPP( iRegP dst ) %{ 7145 match(Set dst (CastPP dst)); 7146 format %{ "# castPP of $dst" %} 7147 ins_encode( /*empty encoding*/ ); 7148 ins_pipe(empty); 7149 %} 7150 7151 instruct castII( iRegI dst ) %{ 7152 match(Set dst (CastII dst)); 7153 format %{ "# castII of $dst" %} 7154 ins_encode( /*empty encoding*/ ); 7155 ins_cost(0); 7156 ins_pipe(empty); 7157 %} 7158 7159 //----------Arithmetic Instructions-------------------------------------------- 7160 // Addition Instructions 7161 // Register Addition 7162 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7163 match(Set dst (AddI src1 src2)); 7164 7165 size(4); 7166 format %{ "ADD $src1,$src2,$dst" %} 7167 ins_encode %{ 7168 __ add($src1$$Register, $src2$$Register, $dst$$Register); 7169 %} 7170 ins_pipe(ialu_reg_reg); 7171 %} 7172 7173 // Immediate Addition 7174 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7175 match(Set dst (AddI src1 src2)); 7176 7177 size(4); 7178 format %{ "ADD $src1,$src2,$dst" %} 7179 opcode(Assembler::add_op3, Assembler::arith_op); 7180 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7181 ins_pipe(ialu_reg_imm); 7182 %} 7183 7184 // Pointer Register Addition 7185 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 7186 match(Set dst (AddP src1 src2)); 7187 7188 size(4); 7189 format %{ "ADD $src1,$src2,$dst" %} 7190 opcode(Assembler::add_op3, Assembler::arith_op); 7191 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7192 ins_pipe(ialu_reg_reg); 7193 %} 7194 7195 // Pointer Immediate Addition 7196 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 7197 match(Set dst (AddP src1 src2)); 7198 7199 size(4); 7200 format %{ "ADD $src1,$src2,$dst" %} 7201 opcode(Assembler::add_op3, Assembler::arith_op); 7202 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7203 ins_pipe(ialu_reg_imm); 7204 %} 7205 7206 // Long Addition 7207 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7208 match(Set dst (AddL src1 src2)); 7209 7210 size(4); 7211 format %{ "ADD $src1,$src2,$dst\t! long" %} 7212 opcode(Assembler::add_op3, Assembler::arith_op); 7213 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7214 ins_pipe(ialu_reg_reg); 7215 %} 7216 7217 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7218 match(Set dst (AddL src1 con)); 7219 7220 size(4); 7221 format %{ "ADD $src1,$con,$dst" %} 7222 opcode(Assembler::add_op3, Assembler::arith_op); 7223 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7224 ins_pipe(ialu_reg_imm); 7225 %} 7226 7227 //----------Conditional_store-------------------------------------------------- 7228 // Conditional-store of the updated heap-top. 7229 // Used during allocation of the shared heap. 7230 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7231 7232 // LoadP-locked. Same as a regular pointer load when used with a compare-swap 7233 instruct loadPLocked(iRegP dst, memory mem) %{ 7234 match(Set dst (LoadPLocked mem)); 7235 ins_cost(MEMORY_REF_COST); 7236 7237 #ifndef _LP64 7238 size(4); 7239 format %{ "LDUW $mem,$dst\t! ptr" %} 7240 opcode(Assembler::lduw_op3, 0, REGP_OP); 7241 #else 7242 format %{ "LDX $mem,$dst\t! ptr" %} 7243 opcode(Assembler::ldx_op3, 0, REGP_OP); 7244 #endif 7245 ins_encode( form3_mem_reg( mem, dst ) ); 7246 ins_pipe(iload_mem); 7247 %} 7248 7249 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 7250 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 7251 effect( KILL newval ); 7252 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 7253 "CMP R_G3,$oldval\t\t! See if we made progress" %} 7254 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 7255 ins_pipe( long_memory_op ); 7256 %} 7257 7258 // Conditional-store of an int value. 7259 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 7260 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 7261 effect( KILL newval ); 7262 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7263 "CMP $oldval,$newval\t\t! See if we made progress" %} 7264 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7265 ins_pipe( long_memory_op ); 7266 %} 7267 7268 // Conditional-store of a long value. 7269 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 7270 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 7271 effect( KILL newval ); 7272 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7273 "CMP $oldval,$newval\t\t! See if we made progress" %} 7274 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7275 ins_pipe( long_memory_op ); 7276 %} 7277 7278 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7279 7280 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7281 predicate(VM_Version::supports_cx8()); 7282 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7283 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7284 format %{ 7285 "MOV $newval,O7\n\t" 7286 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7287 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7288 "MOV 1,$res\n\t" 7289 "MOVne xcc,R_G0,$res" 7290 %} 7291 ins_encode( enc_casx(mem_ptr, oldval, newval), 7292 enc_lflags_ne_to_boolean(res) ); 7293 ins_pipe( long_memory_op ); 7294 %} 7295 7296 7297 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7298 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7299 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7300 format %{ 7301 "MOV $newval,O7\n\t" 7302 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7303 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7304 "MOV 1,$res\n\t" 7305 "MOVne icc,R_G0,$res" 7306 %} 7307 ins_encode( enc_casi(mem_ptr, oldval, newval), 7308 enc_iflags_ne_to_boolean(res) ); 7309 ins_pipe( long_memory_op ); 7310 %} 7311 7312 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7313 #ifdef _LP64 7314 predicate(VM_Version::supports_cx8()); 7315 #endif 7316 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7317 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7318 format %{ 7319 "MOV $newval,O7\n\t" 7320 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7321 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7322 "MOV 1,$res\n\t" 7323 "MOVne xcc,R_G0,$res" 7324 %} 7325 #ifdef _LP64 7326 ins_encode( enc_casx(mem_ptr, oldval, newval), 7327 enc_lflags_ne_to_boolean(res) ); 7328 #else 7329 ins_encode( enc_casi(mem_ptr, oldval, newval), 7330 enc_iflags_ne_to_boolean(res) ); 7331 #endif 7332 ins_pipe( long_memory_op ); 7333 %} 7334 7335 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7336 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 7337 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7338 format %{ 7339 "MOV $newval,O7\n\t" 7340 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7341 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7342 "MOV 1,$res\n\t" 7343 "MOVne icc,R_G0,$res" 7344 %} 7345 ins_encode( enc_casi(mem_ptr, oldval, newval), 7346 enc_iflags_ne_to_boolean(res) ); 7347 ins_pipe( long_memory_op ); 7348 %} 7349 7350 instruct xchgI( memory mem, iRegI newval) %{ 7351 match(Set newval (GetAndSetI mem newval)); 7352 format %{ "SWAP [$mem],$newval" %} 7353 size(4); 7354 ins_encode %{ 7355 __ swap($mem$$Address, $newval$$Register); 7356 %} 7357 ins_pipe( long_memory_op ); 7358 %} 7359 7360 #ifndef _LP64 7361 instruct xchgP( memory mem, iRegP newval) %{ 7362 match(Set newval (GetAndSetP mem newval)); 7363 format %{ "SWAP [$mem],$newval" %} 7364 size(4); 7365 ins_encode %{ 7366 __ swap($mem$$Address, $newval$$Register); 7367 %} 7368 ins_pipe( long_memory_op ); 7369 %} 7370 #endif 7371 7372 instruct xchgN( memory mem, iRegN newval) %{ 7373 match(Set newval (GetAndSetN mem newval)); 7374 format %{ "SWAP [$mem],$newval" %} 7375 size(4); 7376 ins_encode %{ 7377 __ swap($mem$$Address, $newval$$Register); 7378 %} 7379 ins_pipe( long_memory_op ); 7380 %} 7381 7382 //--------------------- 7383 // Subtraction Instructions 7384 // Register Subtraction 7385 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7386 match(Set dst (SubI src1 src2)); 7387 7388 size(4); 7389 format %{ "SUB $src1,$src2,$dst" %} 7390 opcode(Assembler::sub_op3, Assembler::arith_op); 7391 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7392 ins_pipe(ialu_reg_reg); 7393 %} 7394 7395 // Immediate Subtraction 7396 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7397 match(Set dst (SubI src1 src2)); 7398 7399 size(4); 7400 format %{ "SUB $src1,$src2,$dst" %} 7401 opcode(Assembler::sub_op3, Assembler::arith_op); 7402 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7403 ins_pipe(ialu_reg_imm); 7404 %} 7405 7406 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7407 match(Set dst (SubI zero src2)); 7408 7409 size(4); 7410 format %{ "NEG $src2,$dst" %} 7411 opcode(Assembler::sub_op3, Assembler::arith_op); 7412 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7413 ins_pipe(ialu_zero_reg); 7414 %} 7415 7416 // Long subtraction 7417 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7418 match(Set dst (SubL src1 src2)); 7419 7420 size(4); 7421 format %{ "SUB $src1,$src2,$dst\t! long" %} 7422 opcode(Assembler::sub_op3, Assembler::arith_op); 7423 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7424 ins_pipe(ialu_reg_reg); 7425 %} 7426 7427 // Immediate Subtraction 7428 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7429 match(Set dst (SubL src1 con)); 7430 7431 size(4); 7432 format %{ "SUB $src1,$con,$dst\t! long" %} 7433 opcode(Assembler::sub_op3, Assembler::arith_op); 7434 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7435 ins_pipe(ialu_reg_imm); 7436 %} 7437 7438 // Long negation 7439 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7440 match(Set dst (SubL zero src2)); 7441 7442 size(4); 7443 format %{ "NEG $src2,$dst\t! long" %} 7444 opcode(Assembler::sub_op3, Assembler::arith_op); 7445 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7446 ins_pipe(ialu_zero_reg); 7447 %} 7448 7449 // Multiplication Instructions 7450 // Integer Multiplication 7451 // Register Multiplication 7452 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7453 match(Set dst (MulI src1 src2)); 7454 7455 size(4); 7456 format %{ "MULX $src1,$src2,$dst" %} 7457 opcode(Assembler::mulx_op3, Assembler::arith_op); 7458 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7459 ins_pipe(imul_reg_reg); 7460 %} 7461 7462 // Immediate Multiplication 7463 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7464 match(Set dst (MulI src1 src2)); 7465 7466 size(4); 7467 format %{ "MULX $src1,$src2,$dst" %} 7468 opcode(Assembler::mulx_op3, Assembler::arith_op); 7469 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7470 ins_pipe(imul_reg_imm); 7471 %} 7472 7473 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7474 match(Set dst (MulL src1 src2)); 7475 ins_cost(DEFAULT_COST * 5); 7476 size(4); 7477 format %{ "MULX $src1,$src2,$dst\t! long" %} 7478 opcode(Assembler::mulx_op3, Assembler::arith_op); 7479 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7480 ins_pipe(mulL_reg_reg); 7481 %} 7482 7483 // Immediate Multiplication 7484 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7485 match(Set dst (MulL src1 src2)); 7486 ins_cost(DEFAULT_COST * 5); 7487 size(4); 7488 format %{ "MULX $src1,$src2,$dst" %} 7489 opcode(Assembler::mulx_op3, Assembler::arith_op); 7490 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7491 ins_pipe(mulL_reg_imm); 7492 %} 7493 7494 // Integer Division 7495 // Register Division 7496 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7497 match(Set dst (DivI src1 src2)); 7498 ins_cost((2+71)*DEFAULT_COST); 7499 7500 format %{ "SRA $src2,0,$src2\n\t" 7501 "SRA $src1,0,$src1\n\t" 7502 "SDIVX $src1,$src2,$dst" %} 7503 ins_encode( idiv_reg( src1, src2, dst ) ); 7504 ins_pipe(sdiv_reg_reg); 7505 %} 7506 7507 // Immediate Division 7508 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7509 match(Set dst (DivI src1 src2)); 7510 ins_cost((2+71)*DEFAULT_COST); 7511 7512 format %{ "SRA $src1,0,$src1\n\t" 7513 "SDIVX $src1,$src2,$dst" %} 7514 ins_encode( idiv_imm( src1, src2, dst ) ); 7515 ins_pipe(sdiv_reg_imm); 7516 %} 7517 7518 //----------Div-By-10-Expansion------------------------------------------------ 7519 // Extract hi bits of a 32x32->64 bit multiply. 7520 // Expand rule only, not matched 7521 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7522 effect( DEF dst, USE src1, USE src2 ); 7523 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7524 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7525 ins_encode( enc_mul_hi(dst,src1,src2)); 7526 ins_pipe(sdiv_reg_reg); 7527 %} 7528 7529 // Magic constant, reciprocal of 10 7530 instruct loadConI_x66666667(iRegIsafe dst) %{ 7531 effect( DEF dst ); 7532 7533 size(8); 7534 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7535 ins_encode( Set32(0x66666667, dst) ); 7536 ins_pipe(ialu_hi_lo_reg); 7537 %} 7538 7539 // Register Shift Right Arithmetic Long by 32-63 7540 instruct sra_31( iRegI dst, iRegI src ) %{ 7541 effect( DEF dst, USE src ); 7542 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7543 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7544 ins_pipe(ialu_reg_reg); 7545 %} 7546 7547 // Arithmetic Shift Right by 8-bit immediate 7548 instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7549 effect( DEF dst, USE src ); 7550 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7551 opcode(Assembler::sra_op3, Assembler::arith_op); 7552 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7553 ins_pipe(ialu_reg_imm); 7554 %} 7555 7556 // Integer DIV with 10 7557 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7558 match(Set dst (DivI src div)); 7559 ins_cost((6+6)*DEFAULT_COST); 7560 expand %{ 7561 iRegIsafe tmp1; // Killed temps; 7562 iRegIsafe tmp2; // Killed temps; 7563 iRegI tmp3; // Killed temps; 7564 iRegI tmp4; // Killed temps; 7565 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7566 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7567 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7568 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7569 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7570 %} 7571 %} 7572 7573 // Register Long Division 7574 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7575 match(Set dst (DivL src1 src2)); 7576 ins_cost(DEFAULT_COST*71); 7577 size(4); 7578 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7579 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7580 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7581 ins_pipe(divL_reg_reg); 7582 %} 7583 7584 // Register Long Division 7585 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7586 match(Set dst (DivL src1 src2)); 7587 ins_cost(DEFAULT_COST*71); 7588 size(4); 7589 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7590 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7591 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7592 ins_pipe(divL_reg_imm); 7593 %} 7594 7595 // Integer Remainder 7596 // Register Remainder 7597 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7598 match(Set dst (ModI src1 src2)); 7599 effect( KILL ccr, KILL temp); 7600 7601 format %{ "SREM $src1,$src2,$dst" %} 7602 ins_encode( irem_reg(src1, src2, dst, temp) ); 7603 ins_pipe(sdiv_reg_reg); 7604 %} 7605 7606 // Immediate Remainder 7607 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7608 match(Set dst (ModI src1 src2)); 7609 effect( KILL ccr, KILL temp); 7610 7611 format %{ "SREM $src1,$src2,$dst" %} 7612 ins_encode( irem_imm(src1, src2, dst, temp) ); 7613 ins_pipe(sdiv_reg_imm); 7614 %} 7615 7616 // Register Long Remainder 7617 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7618 effect(DEF dst, USE src1, USE src2); 7619 size(4); 7620 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7621 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7622 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7623 ins_pipe(divL_reg_reg); 7624 %} 7625 7626 // Register Long Division 7627 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7628 effect(DEF dst, USE src1, USE src2); 7629 size(4); 7630 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7631 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7632 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7633 ins_pipe(divL_reg_imm); 7634 %} 7635 7636 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7637 effect(DEF dst, USE src1, USE src2); 7638 size(4); 7639 format %{ "MULX $src1,$src2,$dst\t! long" %} 7640 opcode(Assembler::mulx_op3, Assembler::arith_op); 7641 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7642 ins_pipe(mulL_reg_reg); 7643 %} 7644 7645 // Immediate Multiplication 7646 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7647 effect(DEF dst, USE src1, USE src2); 7648 size(4); 7649 format %{ "MULX $src1,$src2,$dst" %} 7650 opcode(Assembler::mulx_op3, Assembler::arith_op); 7651 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7652 ins_pipe(mulL_reg_imm); 7653 %} 7654 7655 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7656 effect(DEF dst, USE src1, USE src2); 7657 size(4); 7658 format %{ "SUB $src1,$src2,$dst\t! long" %} 7659 opcode(Assembler::sub_op3, Assembler::arith_op); 7660 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7661 ins_pipe(ialu_reg_reg); 7662 %} 7663 7664 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7665 effect(DEF dst, USE src1, USE src2); 7666 size(4); 7667 format %{ "SUB $src1,$src2,$dst\t! long" %} 7668 opcode(Assembler::sub_op3, Assembler::arith_op); 7669 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7670 ins_pipe(ialu_reg_reg); 7671 %} 7672 7673 // Register Long Remainder 7674 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7675 match(Set dst (ModL src1 src2)); 7676 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7677 expand %{ 7678 iRegL tmp1; 7679 iRegL tmp2; 7680 divL_reg_reg_1(tmp1, src1, src2); 7681 mulL_reg_reg_1(tmp2, tmp1, src2); 7682 subL_reg_reg_1(dst, src1, tmp2); 7683 %} 7684 %} 7685 7686 // Register Long Remainder 7687 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7688 match(Set dst (ModL src1 src2)); 7689 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7690 expand %{ 7691 iRegL tmp1; 7692 iRegL tmp2; 7693 divL_reg_imm13_1(tmp1, src1, src2); 7694 mulL_reg_imm13_1(tmp2, tmp1, src2); 7695 subL_reg_reg_2 (dst, src1, tmp2); 7696 %} 7697 %} 7698 7699 // Integer Shift Instructions 7700 // Register Shift Left 7701 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7702 match(Set dst (LShiftI src1 src2)); 7703 7704 size(4); 7705 format %{ "SLL $src1,$src2,$dst" %} 7706 opcode(Assembler::sll_op3, Assembler::arith_op); 7707 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7708 ins_pipe(ialu_reg_reg); 7709 %} 7710 7711 // Register Shift Left Immediate 7712 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7713 match(Set dst (LShiftI src1 src2)); 7714 7715 size(4); 7716 format %{ "SLL $src1,$src2,$dst" %} 7717 opcode(Assembler::sll_op3, Assembler::arith_op); 7718 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7719 ins_pipe(ialu_reg_imm); 7720 %} 7721 7722 // Register Shift Left 7723 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7724 match(Set dst (LShiftL src1 src2)); 7725 7726 size(4); 7727 format %{ "SLLX $src1,$src2,$dst" %} 7728 opcode(Assembler::sllx_op3, Assembler::arith_op); 7729 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7730 ins_pipe(ialu_reg_reg); 7731 %} 7732 7733 // Register Shift Left Immediate 7734 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7735 match(Set dst (LShiftL src1 src2)); 7736 7737 size(4); 7738 format %{ "SLLX $src1,$src2,$dst" %} 7739 opcode(Assembler::sllx_op3, Assembler::arith_op); 7740 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7741 ins_pipe(ialu_reg_imm); 7742 %} 7743 7744 // Register Arithmetic Shift Right 7745 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7746 match(Set dst (RShiftI src1 src2)); 7747 size(4); 7748 format %{ "SRA $src1,$src2,$dst" %} 7749 opcode(Assembler::sra_op3, Assembler::arith_op); 7750 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7751 ins_pipe(ialu_reg_reg); 7752 %} 7753 7754 // Register Arithmetic Shift Right Immediate 7755 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7756 match(Set dst (RShiftI src1 src2)); 7757 7758 size(4); 7759 format %{ "SRA $src1,$src2,$dst" %} 7760 opcode(Assembler::sra_op3, Assembler::arith_op); 7761 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7762 ins_pipe(ialu_reg_imm); 7763 %} 7764 7765 // Register Shift Right Arithmatic Long 7766 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7767 match(Set dst (RShiftL src1 src2)); 7768 7769 size(4); 7770 format %{ "SRAX $src1,$src2,$dst" %} 7771 opcode(Assembler::srax_op3, Assembler::arith_op); 7772 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7773 ins_pipe(ialu_reg_reg); 7774 %} 7775 7776 // Register Shift Left Immediate 7777 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7778 match(Set dst (RShiftL src1 src2)); 7779 7780 size(4); 7781 format %{ "SRAX $src1,$src2,$dst" %} 7782 opcode(Assembler::srax_op3, Assembler::arith_op); 7783 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7784 ins_pipe(ialu_reg_imm); 7785 %} 7786 7787 // Register Shift Right 7788 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7789 match(Set dst (URShiftI src1 src2)); 7790 7791 size(4); 7792 format %{ "SRL $src1,$src2,$dst" %} 7793 opcode(Assembler::srl_op3, Assembler::arith_op); 7794 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7795 ins_pipe(ialu_reg_reg); 7796 %} 7797 7798 // Register Shift Right Immediate 7799 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7800 match(Set dst (URShiftI src1 src2)); 7801 7802 size(4); 7803 format %{ "SRL $src1,$src2,$dst" %} 7804 opcode(Assembler::srl_op3, Assembler::arith_op); 7805 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7806 ins_pipe(ialu_reg_imm); 7807 %} 7808 7809 // Register Shift Right 7810 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7811 match(Set dst (URShiftL src1 src2)); 7812 7813 size(4); 7814 format %{ "SRLX $src1,$src2,$dst" %} 7815 opcode(Assembler::srlx_op3, Assembler::arith_op); 7816 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7817 ins_pipe(ialu_reg_reg); 7818 %} 7819 7820 // Register Shift Right Immediate 7821 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7822 match(Set dst (URShiftL src1 src2)); 7823 7824 size(4); 7825 format %{ "SRLX $src1,$src2,$dst" %} 7826 opcode(Assembler::srlx_op3, Assembler::arith_op); 7827 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7828 ins_pipe(ialu_reg_imm); 7829 %} 7830 7831 // Register Shift Right Immediate with a CastP2X 7832 #ifdef _LP64 7833 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7834 match(Set dst (URShiftL (CastP2X src1) src2)); 7835 size(4); 7836 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7837 opcode(Assembler::srlx_op3, Assembler::arith_op); 7838 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7839 ins_pipe(ialu_reg_imm); 7840 %} 7841 #else 7842 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7843 match(Set dst (URShiftI (CastP2X src1) src2)); 7844 size(4); 7845 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7846 opcode(Assembler::srl_op3, Assembler::arith_op); 7847 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7848 ins_pipe(ialu_reg_imm); 7849 %} 7850 #endif 7851 7852 7853 //----------Floating Point Arithmetic Instructions----------------------------- 7854 7855 // Add float single precision 7856 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7857 match(Set dst (AddF src1 src2)); 7858 7859 size(4); 7860 format %{ "FADDS $src1,$src2,$dst" %} 7861 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7862 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7863 ins_pipe(faddF_reg_reg); 7864 %} 7865 7866 // Add float double precision 7867 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7868 match(Set dst (AddD src1 src2)); 7869 7870 size(4); 7871 format %{ "FADDD $src1,$src2,$dst" %} 7872 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7873 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7874 ins_pipe(faddD_reg_reg); 7875 %} 7876 7877 // Sub float single precision 7878 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7879 match(Set dst (SubF src1 src2)); 7880 7881 size(4); 7882 format %{ "FSUBS $src1,$src2,$dst" %} 7883 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7884 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7885 ins_pipe(faddF_reg_reg); 7886 %} 7887 7888 // Sub float double precision 7889 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7890 match(Set dst (SubD src1 src2)); 7891 7892 size(4); 7893 format %{ "FSUBD $src1,$src2,$dst" %} 7894 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7895 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7896 ins_pipe(faddD_reg_reg); 7897 %} 7898 7899 // Mul float single precision 7900 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7901 match(Set dst (MulF src1 src2)); 7902 7903 size(4); 7904 format %{ "FMULS $src1,$src2,$dst" %} 7905 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7906 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7907 ins_pipe(fmulF_reg_reg); 7908 %} 7909 7910 // Mul float double precision 7911 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7912 match(Set dst (MulD src1 src2)); 7913 7914 size(4); 7915 format %{ "FMULD $src1,$src2,$dst" %} 7916 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7917 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7918 ins_pipe(fmulD_reg_reg); 7919 %} 7920 7921 // Div float single precision 7922 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7923 match(Set dst (DivF src1 src2)); 7924 7925 size(4); 7926 format %{ "FDIVS $src1,$src2,$dst" %} 7927 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7928 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7929 ins_pipe(fdivF_reg_reg); 7930 %} 7931 7932 // Div float double precision 7933 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7934 match(Set dst (DivD src1 src2)); 7935 7936 size(4); 7937 format %{ "FDIVD $src1,$src2,$dst" %} 7938 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7939 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7940 ins_pipe(fdivD_reg_reg); 7941 %} 7942 7943 // Absolute float double precision 7944 instruct absD_reg(regD dst, regD src) %{ 7945 match(Set dst (AbsD src)); 7946 7947 format %{ "FABSd $src,$dst" %} 7948 ins_encode(fabsd(dst, src)); 7949 ins_pipe(faddD_reg); 7950 %} 7951 7952 // Absolute float single precision 7953 instruct absF_reg(regF dst, regF src) %{ 7954 match(Set dst (AbsF src)); 7955 7956 format %{ "FABSs $src,$dst" %} 7957 ins_encode(fabss(dst, src)); 7958 ins_pipe(faddF_reg); 7959 %} 7960 7961 instruct negF_reg(regF dst, regF src) %{ 7962 match(Set dst (NegF src)); 7963 7964 size(4); 7965 format %{ "FNEGs $src,$dst" %} 7966 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7967 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7968 ins_pipe(faddF_reg); 7969 %} 7970 7971 instruct negD_reg(regD dst, regD src) %{ 7972 match(Set dst (NegD src)); 7973 7974 format %{ "FNEGd $src,$dst" %} 7975 ins_encode(fnegd(dst, src)); 7976 ins_pipe(faddD_reg); 7977 %} 7978 7979 // Sqrt float double precision 7980 instruct sqrtF_reg_reg(regF dst, regF src) %{ 7981 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7982 7983 size(4); 7984 format %{ "FSQRTS $src,$dst" %} 7985 ins_encode(fsqrts(dst, src)); 7986 ins_pipe(fdivF_reg_reg); 7987 %} 7988 7989 // Sqrt float double precision 7990 instruct sqrtD_reg_reg(regD dst, regD src) %{ 7991 match(Set dst (SqrtD src)); 7992 7993 size(4); 7994 format %{ "FSQRTD $src,$dst" %} 7995 ins_encode(fsqrtd(dst, src)); 7996 ins_pipe(fdivD_reg_reg); 7997 %} 7998 7999 //----------Logical Instructions----------------------------------------------- 8000 // And Instructions 8001 // Register And 8002 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8003 match(Set dst (AndI src1 src2)); 8004 8005 size(4); 8006 format %{ "AND $src1,$src2,$dst" %} 8007 opcode(Assembler::and_op3, Assembler::arith_op); 8008 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8009 ins_pipe(ialu_reg_reg); 8010 %} 8011 8012 // Immediate And 8013 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8014 match(Set dst (AndI src1 src2)); 8015 8016 size(4); 8017 format %{ "AND $src1,$src2,$dst" %} 8018 opcode(Assembler::and_op3, Assembler::arith_op); 8019 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8020 ins_pipe(ialu_reg_imm); 8021 %} 8022 8023 // Register And Long 8024 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8025 match(Set dst (AndL src1 src2)); 8026 8027 ins_cost(DEFAULT_COST); 8028 size(4); 8029 format %{ "AND $src1,$src2,$dst\t! long" %} 8030 opcode(Assembler::and_op3, Assembler::arith_op); 8031 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8032 ins_pipe(ialu_reg_reg); 8033 %} 8034 8035 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8036 match(Set dst (AndL src1 con)); 8037 8038 ins_cost(DEFAULT_COST); 8039 size(4); 8040 format %{ "AND $src1,$con,$dst\t! long" %} 8041 opcode(Assembler::and_op3, Assembler::arith_op); 8042 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8043 ins_pipe(ialu_reg_imm); 8044 %} 8045 8046 // Or Instructions 8047 // Register Or 8048 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8049 match(Set dst (OrI src1 src2)); 8050 8051 size(4); 8052 format %{ "OR $src1,$src2,$dst" %} 8053 opcode(Assembler::or_op3, Assembler::arith_op); 8054 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8055 ins_pipe(ialu_reg_reg); 8056 %} 8057 8058 // Immediate Or 8059 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8060 match(Set dst (OrI src1 src2)); 8061 8062 size(4); 8063 format %{ "OR $src1,$src2,$dst" %} 8064 opcode(Assembler::or_op3, Assembler::arith_op); 8065 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8066 ins_pipe(ialu_reg_imm); 8067 %} 8068 8069 // Register Or Long 8070 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8071 match(Set dst (OrL src1 src2)); 8072 8073 ins_cost(DEFAULT_COST); 8074 size(4); 8075 format %{ "OR $src1,$src2,$dst\t! long" %} 8076 opcode(Assembler::or_op3, Assembler::arith_op); 8077 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8078 ins_pipe(ialu_reg_reg); 8079 %} 8080 8081 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8082 match(Set dst (OrL src1 con)); 8083 ins_cost(DEFAULT_COST*2); 8084 8085 ins_cost(DEFAULT_COST); 8086 size(4); 8087 format %{ "OR $src1,$con,$dst\t! long" %} 8088 opcode(Assembler::or_op3, Assembler::arith_op); 8089 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8090 ins_pipe(ialu_reg_imm); 8091 %} 8092 8093 #ifndef _LP64 8094 8095 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. 8096 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ 8097 match(Set dst (OrI src1 (CastP2X src2))); 8098 8099 size(4); 8100 format %{ "OR $src1,$src2,$dst" %} 8101 opcode(Assembler::or_op3, Assembler::arith_op); 8102 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8103 ins_pipe(ialu_reg_reg); 8104 %} 8105 8106 #else 8107 8108 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 8109 match(Set dst (OrL src1 (CastP2X src2))); 8110 8111 ins_cost(DEFAULT_COST); 8112 size(4); 8113 format %{ "OR $src1,$src2,$dst\t! long" %} 8114 opcode(Assembler::or_op3, Assembler::arith_op); 8115 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8116 ins_pipe(ialu_reg_reg); 8117 %} 8118 8119 #endif 8120 8121 // Xor Instructions 8122 // Register Xor 8123 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8124 match(Set dst (XorI src1 src2)); 8125 8126 size(4); 8127 format %{ "XOR $src1,$src2,$dst" %} 8128 opcode(Assembler::xor_op3, Assembler::arith_op); 8129 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8130 ins_pipe(ialu_reg_reg); 8131 %} 8132 8133 // Immediate Xor 8134 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8135 match(Set dst (XorI src1 src2)); 8136 8137 size(4); 8138 format %{ "XOR $src1,$src2,$dst" %} 8139 opcode(Assembler::xor_op3, Assembler::arith_op); 8140 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8141 ins_pipe(ialu_reg_imm); 8142 %} 8143 8144 // Register Xor Long 8145 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8146 match(Set dst (XorL src1 src2)); 8147 8148 ins_cost(DEFAULT_COST); 8149 size(4); 8150 format %{ "XOR $src1,$src2,$dst\t! long" %} 8151 opcode(Assembler::xor_op3, Assembler::arith_op); 8152 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8153 ins_pipe(ialu_reg_reg); 8154 %} 8155 8156 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8157 match(Set dst (XorL src1 con)); 8158 8159 ins_cost(DEFAULT_COST); 8160 size(4); 8161 format %{ "XOR $src1,$con,$dst\t! long" %} 8162 opcode(Assembler::xor_op3, Assembler::arith_op); 8163 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8164 ins_pipe(ialu_reg_imm); 8165 %} 8166 8167 //----------Convert to Boolean------------------------------------------------- 8168 // Nice hack for 32-bit tests but doesn't work for 8169 // 64-bit pointers. 8170 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 8171 match(Set dst (Conv2B src)); 8172 effect( KILL ccr ); 8173 ins_cost(DEFAULT_COST*2); 8174 format %{ "CMP R_G0,$src\n\t" 8175 "ADDX R_G0,0,$dst" %} 8176 ins_encode( enc_to_bool( src, dst ) ); 8177 ins_pipe(ialu_reg_ialu); 8178 %} 8179 8180 #ifndef _LP64 8181 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 8182 match(Set dst (Conv2B src)); 8183 effect( KILL ccr ); 8184 ins_cost(DEFAULT_COST*2); 8185 format %{ "CMP R_G0,$src\n\t" 8186 "ADDX R_G0,0,$dst" %} 8187 ins_encode( enc_to_bool( src, dst ) ); 8188 ins_pipe(ialu_reg_ialu); 8189 %} 8190 #else 8191 instruct convP2B( iRegI dst, iRegP src ) %{ 8192 match(Set dst (Conv2B src)); 8193 ins_cost(DEFAULT_COST*2); 8194 format %{ "MOV $src,$dst\n\t" 8195 "MOVRNZ $src,1,$dst" %} 8196 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 8197 ins_pipe(ialu_clr_and_mover); 8198 %} 8199 #endif 8200 8201 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ 8202 match(Set dst (CmpLTMask src zero)); 8203 effect(KILL ccr); 8204 size(4); 8205 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} 8206 ins_encode %{ 8207 __ sra($src$$Register, 31, $dst$$Register); 8208 %} 8209 ins_pipe(ialu_reg_imm); 8210 %} 8211 8212 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 8213 match(Set dst (CmpLTMask p q)); 8214 effect( KILL ccr ); 8215 ins_cost(DEFAULT_COST*4); 8216 format %{ "CMP $p,$q\n\t" 8217 "MOV #0,$dst\n\t" 8218 "BLT,a .+8\n\t" 8219 "MOV #-1,$dst" %} 8220 ins_encode( enc_ltmask(p,q,dst) ); 8221 ins_pipe(ialu_reg_reg_ialu); 8222 %} 8223 8224 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8225 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8226 effect(KILL ccr, TEMP tmp); 8227 ins_cost(DEFAULT_COST*3); 8228 8229 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8230 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8231 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8232 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); 8233 ins_pipe(cadd_cmpltmask); 8234 %} 8235 8236 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ 8237 match(Set p (AndI (CmpLTMask p q) y)); 8238 effect(KILL ccr); 8239 ins_cost(DEFAULT_COST*3); 8240 8241 format %{ "CMP $p,$q\n\t" 8242 "MOV $y,$p\n\t" 8243 "MOVge G0,$p" %} 8244 ins_encode %{ 8245 __ cmp($p$$Register, $q$$Register); 8246 __ mov($y$$Register, $p$$Register); 8247 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); 8248 %} 8249 ins_pipe(ialu_reg_reg_ialu); 8250 %} 8251 8252 //----------------------------------------------------------------- 8253 // Direct raw moves between float and general registers using VIS3. 8254 8255 // ins_pipe(faddF_reg); 8256 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ 8257 predicate(UseVIS >= 3); 8258 match(Set dst (MoveF2I src)); 8259 8260 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} 8261 ins_encode %{ 8262 __ movstouw($src$$FloatRegister, $dst$$Register); 8263 %} 8264 ins_pipe(ialu_reg_reg); 8265 %} 8266 8267 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ 8268 predicate(UseVIS >= 3); 8269 match(Set dst (MoveI2F src)); 8270 8271 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} 8272 ins_encode %{ 8273 __ movwtos($src$$Register, $dst$$FloatRegister); 8274 %} 8275 ins_pipe(ialu_reg_reg); 8276 %} 8277 8278 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ 8279 predicate(UseVIS >= 3); 8280 match(Set dst (MoveD2L src)); 8281 8282 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} 8283 ins_encode %{ 8284 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); 8285 %} 8286 ins_pipe(ialu_reg_reg); 8287 %} 8288 8289 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ 8290 predicate(UseVIS >= 3); 8291 match(Set dst (MoveL2D src)); 8292 8293 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} 8294 ins_encode %{ 8295 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); 8296 %} 8297 ins_pipe(ialu_reg_reg); 8298 %} 8299 8300 8301 // Raw moves between float and general registers using stack. 8302 8303 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8304 match(Set dst (MoveF2I src)); 8305 effect(DEF dst, USE src); 8306 ins_cost(MEMORY_REF_COST); 8307 8308 size(4); 8309 format %{ "LDUW $src,$dst\t! MoveF2I" %} 8310 opcode(Assembler::lduw_op3); 8311 ins_encode(simple_form3_mem_reg( src, dst ) ); 8312 ins_pipe(iload_mem); 8313 %} 8314 8315 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8316 match(Set dst (MoveI2F src)); 8317 effect(DEF dst, USE src); 8318 ins_cost(MEMORY_REF_COST); 8319 8320 size(4); 8321 format %{ "LDF $src,$dst\t! MoveI2F" %} 8322 opcode(Assembler::ldf_op3); 8323 ins_encode(simple_form3_mem_reg(src, dst)); 8324 ins_pipe(floadF_stk); 8325 %} 8326 8327 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8328 match(Set dst (MoveD2L src)); 8329 effect(DEF dst, USE src); 8330 ins_cost(MEMORY_REF_COST); 8331 8332 size(4); 8333 format %{ "LDX $src,$dst\t! MoveD2L" %} 8334 opcode(Assembler::ldx_op3); 8335 ins_encode(simple_form3_mem_reg( src, dst ) ); 8336 ins_pipe(iload_mem); 8337 %} 8338 8339 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8340 match(Set dst (MoveL2D src)); 8341 effect(DEF dst, USE src); 8342 ins_cost(MEMORY_REF_COST); 8343 8344 size(4); 8345 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8346 opcode(Assembler::lddf_op3); 8347 ins_encode(simple_form3_mem_reg(src, dst)); 8348 ins_pipe(floadD_stk); 8349 %} 8350 8351 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8352 match(Set dst (MoveF2I src)); 8353 effect(DEF dst, USE src); 8354 ins_cost(MEMORY_REF_COST); 8355 8356 size(4); 8357 format %{ "STF $src,$dst\t! MoveF2I" %} 8358 opcode(Assembler::stf_op3); 8359 ins_encode(simple_form3_mem_reg(dst, src)); 8360 ins_pipe(fstoreF_stk_reg); 8361 %} 8362 8363 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8364 match(Set dst (MoveI2F src)); 8365 effect(DEF dst, USE src); 8366 ins_cost(MEMORY_REF_COST); 8367 8368 size(4); 8369 format %{ "STW $src,$dst\t! MoveI2F" %} 8370 opcode(Assembler::stw_op3); 8371 ins_encode(simple_form3_mem_reg( dst, src ) ); 8372 ins_pipe(istore_mem_reg); 8373 %} 8374 8375 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8376 match(Set dst (MoveD2L src)); 8377 effect(DEF dst, USE src); 8378 ins_cost(MEMORY_REF_COST); 8379 8380 size(4); 8381 format %{ "STDF $src,$dst\t! MoveD2L" %} 8382 opcode(Assembler::stdf_op3); 8383 ins_encode(simple_form3_mem_reg(dst, src)); 8384 ins_pipe(fstoreD_stk_reg); 8385 %} 8386 8387 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8388 match(Set dst (MoveL2D src)); 8389 effect(DEF dst, USE src); 8390 ins_cost(MEMORY_REF_COST); 8391 8392 size(4); 8393 format %{ "STX $src,$dst\t! MoveL2D" %} 8394 opcode(Assembler::stx_op3); 8395 ins_encode(simple_form3_mem_reg( dst, src ) ); 8396 ins_pipe(istore_mem_reg); 8397 %} 8398 8399 8400 //----------Arithmetic Conversion Instructions--------------------------------- 8401 // The conversions operations are all Alpha sorted. Please keep it that way! 8402 8403 instruct convD2F_reg(regF dst, regD src) %{ 8404 match(Set dst (ConvD2F src)); 8405 size(4); 8406 format %{ "FDTOS $src,$dst" %} 8407 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 8408 ins_encode(form3_opf_rs2D_rdF(src, dst)); 8409 ins_pipe(fcvtD2F); 8410 %} 8411 8412 8413 // Convert a double to an int in a float register. 8414 // If the double is a NAN, stuff a zero in instead. 8415 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 8416 effect(DEF dst, USE src, KILL fcc0); 8417 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8418 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8419 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8420 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8421 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8422 "skip:" %} 8423 ins_encode(form_d2i_helper(src,dst)); 8424 ins_pipe(fcvtD2I); 8425 %} 8426 8427 instruct convD2I_stk(stackSlotI dst, regD src) %{ 8428 match(Set dst (ConvD2I src)); 8429 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8430 expand %{ 8431 regF tmp; 8432 convD2I_helper(tmp, src); 8433 regF_to_stkI(dst, tmp); 8434 %} 8435 %} 8436 8437 instruct convD2I_reg(iRegI dst, regD src) %{ 8438 predicate(UseVIS >= 3); 8439 match(Set dst (ConvD2I src)); 8440 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8441 expand %{ 8442 regF tmp; 8443 convD2I_helper(tmp, src); 8444 MoveF2I_reg_reg(dst, tmp); 8445 %} 8446 %} 8447 8448 8449 // Convert a double to a long in a double register. 8450 // If the double is a NAN, stuff a zero in instead. 8451 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8452 effect(DEF dst, USE src, KILL fcc0); 8453 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8454 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8455 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8456 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8457 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8458 "skip:" %} 8459 ins_encode(form_d2l_helper(src,dst)); 8460 ins_pipe(fcvtD2L); 8461 %} 8462 8463 instruct convD2L_stk(stackSlotL dst, regD src) %{ 8464 match(Set dst (ConvD2L src)); 8465 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8466 expand %{ 8467 regD tmp; 8468 convD2L_helper(tmp, src); 8469 regD_to_stkL(dst, tmp); 8470 %} 8471 %} 8472 8473 instruct convD2L_reg(iRegL dst, regD src) %{ 8474 predicate(UseVIS >= 3); 8475 match(Set dst (ConvD2L src)); 8476 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8477 expand %{ 8478 regD tmp; 8479 convD2L_helper(tmp, src); 8480 MoveD2L_reg_reg(dst, tmp); 8481 %} 8482 %} 8483 8484 8485 instruct convF2D_reg(regD dst, regF src) %{ 8486 match(Set dst (ConvF2D src)); 8487 format %{ "FSTOD $src,$dst" %} 8488 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8489 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8490 ins_pipe(fcvtF2D); 8491 %} 8492 8493 8494 // Convert a float to an int in a float register. 8495 // If the float is a NAN, stuff a zero in instead. 8496 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8497 effect(DEF dst, USE src, KILL fcc0); 8498 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8499 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8500 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8501 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8502 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8503 "skip:" %} 8504 ins_encode(form_f2i_helper(src,dst)); 8505 ins_pipe(fcvtF2I); 8506 %} 8507 8508 instruct convF2I_stk(stackSlotI dst, regF src) %{ 8509 match(Set dst (ConvF2I src)); 8510 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8511 expand %{ 8512 regF tmp; 8513 convF2I_helper(tmp, src); 8514 regF_to_stkI(dst, tmp); 8515 %} 8516 %} 8517 8518 instruct convF2I_reg(iRegI dst, regF src) %{ 8519 predicate(UseVIS >= 3); 8520 match(Set dst (ConvF2I src)); 8521 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8522 expand %{ 8523 regF tmp; 8524 convF2I_helper(tmp, src); 8525 MoveF2I_reg_reg(dst, tmp); 8526 %} 8527 %} 8528 8529 8530 // Convert a float to a long in a float register. 8531 // If the float is a NAN, stuff a zero in instead. 8532 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8533 effect(DEF dst, USE src, KILL fcc0); 8534 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8535 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8536 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8537 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8538 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8539 "skip:" %} 8540 ins_encode(form_f2l_helper(src,dst)); 8541 ins_pipe(fcvtF2L); 8542 %} 8543 8544 instruct convF2L_stk(stackSlotL dst, regF src) %{ 8545 match(Set dst (ConvF2L src)); 8546 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8547 expand %{ 8548 regD tmp; 8549 convF2L_helper(tmp, src); 8550 regD_to_stkL(dst, tmp); 8551 %} 8552 %} 8553 8554 instruct convF2L_reg(iRegL dst, regF src) %{ 8555 predicate(UseVIS >= 3); 8556 match(Set dst (ConvF2L src)); 8557 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8558 expand %{ 8559 regD tmp; 8560 convF2L_helper(tmp, src); 8561 MoveD2L_reg_reg(dst, tmp); 8562 %} 8563 %} 8564 8565 8566 instruct convI2D_helper(regD dst, regF tmp) %{ 8567 effect(USE tmp, DEF dst); 8568 format %{ "FITOD $tmp,$dst" %} 8569 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8570 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8571 ins_pipe(fcvtI2D); 8572 %} 8573 8574 instruct convI2D_stk(stackSlotI src, regD dst) %{ 8575 match(Set dst (ConvI2D src)); 8576 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8577 expand %{ 8578 regF tmp; 8579 stkI_to_regF(tmp, src); 8580 convI2D_helper(dst, tmp); 8581 %} 8582 %} 8583 8584 instruct convI2D_reg(regD_low dst, iRegI src) %{ 8585 predicate(UseVIS >= 3); 8586 match(Set dst (ConvI2D src)); 8587 expand %{ 8588 regF tmp; 8589 MoveI2F_reg_reg(tmp, src); 8590 convI2D_helper(dst, tmp); 8591 %} 8592 %} 8593 8594 instruct convI2D_mem(regD_low dst, memory mem) %{ 8595 match(Set dst (ConvI2D (LoadI mem))); 8596 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8597 size(8); 8598 format %{ "LDF $mem,$dst\n\t" 8599 "FITOD $dst,$dst" %} 8600 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8601 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8602 ins_pipe(floadF_mem); 8603 %} 8604 8605 8606 instruct convI2F_helper(regF dst, regF tmp) %{ 8607 effect(DEF dst, USE tmp); 8608 format %{ "FITOS $tmp,$dst" %} 8609 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8610 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8611 ins_pipe(fcvtI2F); 8612 %} 8613 8614 instruct convI2F_stk(regF dst, stackSlotI src) %{ 8615 match(Set dst (ConvI2F src)); 8616 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8617 expand %{ 8618 regF tmp; 8619 stkI_to_regF(tmp,src); 8620 convI2F_helper(dst, tmp); 8621 %} 8622 %} 8623 8624 instruct convI2F_reg(regF dst, iRegI src) %{ 8625 predicate(UseVIS >= 3); 8626 match(Set dst (ConvI2F src)); 8627 ins_cost(DEFAULT_COST); 8628 expand %{ 8629 regF tmp; 8630 MoveI2F_reg_reg(tmp, src); 8631 convI2F_helper(dst, tmp); 8632 %} 8633 %} 8634 8635 instruct convI2F_mem( regF dst, memory mem ) %{ 8636 match(Set dst (ConvI2F (LoadI mem))); 8637 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8638 size(8); 8639 format %{ "LDF $mem,$dst\n\t" 8640 "FITOS $dst,$dst" %} 8641 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8642 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8643 ins_pipe(floadF_mem); 8644 %} 8645 8646 8647 instruct convI2L_reg(iRegL dst, iRegI src) %{ 8648 match(Set dst (ConvI2L src)); 8649 size(4); 8650 format %{ "SRA $src,0,$dst\t! int->long" %} 8651 opcode(Assembler::sra_op3, Assembler::arith_op); 8652 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8653 ins_pipe(ialu_reg_reg); 8654 %} 8655 8656 // Zero-extend convert int to long 8657 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8658 match(Set dst (AndL (ConvI2L src) mask) ); 8659 size(4); 8660 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8661 opcode(Assembler::srl_op3, Assembler::arith_op); 8662 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8663 ins_pipe(ialu_reg_reg); 8664 %} 8665 8666 // Zero-extend long 8667 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8668 match(Set dst (AndL src mask) ); 8669 size(4); 8670 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8671 opcode(Assembler::srl_op3, Assembler::arith_op); 8672 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8673 ins_pipe(ialu_reg_reg); 8674 %} 8675 8676 8677 //----------- 8678 // Long to Double conversion using V8 opcodes. 8679 // Still useful because cheetah traps and becomes 8680 // amazingly slow for some common numbers. 8681 8682 // Magic constant, 0x43300000 8683 instruct loadConI_x43300000(iRegI dst) %{ 8684 effect(DEF dst); 8685 size(4); 8686 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8687 ins_encode(SetHi22(0x43300000, dst)); 8688 ins_pipe(ialu_none); 8689 %} 8690 8691 // Magic constant, 0x41f00000 8692 instruct loadConI_x41f00000(iRegI dst) %{ 8693 effect(DEF dst); 8694 size(4); 8695 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8696 ins_encode(SetHi22(0x41f00000, dst)); 8697 ins_pipe(ialu_none); 8698 %} 8699 8700 // Construct a double from two float halves 8701 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8702 effect(DEF dst, USE src1, USE src2); 8703 size(8); 8704 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8705 "FMOVS $src2.lo,$dst.lo" %} 8706 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8707 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8708 ins_pipe(faddD_reg_reg); 8709 %} 8710 8711 // Convert integer in high half of a double register (in the lower half of 8712 // the double register file) to double 8713 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8714 effect(DEF dst, USE src); 8715 size(4); 8716 format %{ "FITOD $src,$dst" %} 8717 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8718 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8719 ins_pipe(fcvtLHi2D); 8720 %} 8721 8722 // Add float double precision 8723 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8724 effect(DEF dst, USE src1, USE src2); 8725 size(4); 8726 format %{ "FADDD $src1,$src2,$dst" %} 8727 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8728 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8729 ins_pipe(faddD_reg_reg); 8730 %} 8731 8732 // Sub float double precision 8733 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8734 effect(DEF dst, USE src1, USE src2); 8735 size(4); 8736 format %{ "FSUBD $src1,$src2,$dst" %} 8737 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8738 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8739 ins_pipe(faddD_reg_reg); 8740 %} 8741 8742 // Mul float double precision 8743 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8744 effect(DEF dst, USE src1, USE src2); 8745 size(4); 8746 format %{ "FMULD $src1,$src2,$dst" %} 8747 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8748 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8749 ins_pipe(fmulD_reg_reg); 8750 %} 8751 8752 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 8753 match(Set dst (ConvL2D src)); 8754 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 8755 8756 expand %{ 8757 regD_low tmpsrc; 8758 iRegI ix43300000; 8759 iRegI ix41f00000; 8760 stackSlotL lx43300000; 8761 stackSlotL lx41f00000; 8762 regD_low dx43300000; 8763 regD dx41f00000; 8764 regD tmp1; 8765 regD_low tmp2; 8766 regD tmp3; 8767 regD tmp4; 8768 8769 stkL_to_regD(tmpsrc, src); 8770 8771 loadConI_x43300000(ix43300000); 8772 loadConI_x41f00000(ix41f00000); 8773 regI_to_stkLHi(lx43300000, ix43300000); 8774 regI_to_stkLHi(lx41f00000, ix41f00000); 8775 stkL_to_regD(dx43300000, lx43300000); 8776 stkL_to_regD(dx41f00000, lx41f00000); 8777 8778 convI2D_regDHi_regD(tmp1, tmpsrc); 8779 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 8780 subD_regD_regD(tmp3, tmp2, dx43300000); 8781 mulD_regD_regD(tmp4, tmp1, dx41f00000); 8782 addD_regD_regD(dst, tmp3, tmp4); 8783 %} 8784 %} 8785 8786 // Long to Double conversion using fast fxtof 8787 instruct convL2D_helper(regD dst, regD tmp) %{ 8788 effect(DEF dst, USE tmp); 8789 size(4); 8790 format %{ "FXTOD $tmp,$dst" %} 8791 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8792 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8793 ins_pipe(fcvtL2D); 8794 %} 8795 8796 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ 8797 predicate(VM_Version::has_fast_fxtof()); 8798 match(Set dst (ConvL2D src)); 8799 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8800 expand %{ 8801 regD tmp; 8802 stkL_to_regD(tmp, src); 8803 convL2D_helper(dst, tmp); 8804 %} 8805 %} 8806 8807 instruct convL2D_reg(regD dst, iRegL src) %{ 8808 predicate(UseVIS >= 3); 8809 match(Set dst (ConvL2D src)); 8810 expand %{ 8811 regD tmp; 8812 MoveL2D_reg_reg(tmp, src); 8813 convL2D_helper(dst, tmp); 8814 %} 8815 %} 8816 8817 // Long to Float conversion using fast fxtof 8818 instruct convL2F_helper(regF dst, regD tmp) %{ 8819 effect(DEF dst, USE tmp); 8820 size(4); 8821 format %{ "FXTOS $tmp,$dst" %} 8822 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8823 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8824 ins_pipe(fcvtL2F); 8825 %} 8826 8827 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ 8828 match(Set dst (ConvL2F src)); 8829 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8830 expand %{ 8831 regD tmp; 8832 stkL_to_regD(tmp, src); 8833 convL2F_helper(dst, tmp); 8834 %} 8835 %} 8836 8837 instruct convL2F_reg(regF dst, iRegL src) %{ 8838 predicate(UseVIS >= 3); 8839 match(Set dst (ConvL2F src)); 8840 ins_cost(DEFAULT_COST); 8841 expand %{ 8842 regD tmp; 8843 MoveL2D_reg_reg(tmp, src); 8844 convL2F_helper(dst, tmp); 8845 %} 8846 %} 8847 8848 //----------- 8849 8850 instruct convL2I_reg(iRegI dst, iRegL src) %{ 8851 match(Set dst (ConvL2I src)); 8852 #ifndef _LP64 8853 format %{ "MOV $src.lo,$dst\t! long->int" %} 8854 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 8855 ins_pipe(ialu_move_reg_I_to_L); 8856 #else 8857 size(4); 8858 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8859 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8860 ins_pipe(ialu_reg); 8861 #endif 8862 %} 8863 8864 // Register Shift Right Immediate 8865 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8866 match(Set dst (ConvL2I (RShiftL src cnt))); 8867 8868 size(4); 8869 format %{ "SRAX $src,$cnt,$dst" %} 8870 opcode(Assembler::srax_op3, Assembler::arith_op); 8871 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8872 ins_pipe(ialu_reg_imm); 8873 %} 8874 8875 //----------Control Flow Instructions------------------------------------------ 8876 // Compare Instructions 8877 // Compare Integers 8878 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8879 match(Set icc (CmpI op1 op2)); 8880 effect( DEF icc, USE op1, USE op2 ); 8881 8882 size(4); 8883 format %{ "CMP $op1,$op2" %} 8884 opcode(Assembler::subcc_op3, Assembler::arith_op); 8885 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8886 ins_pipe(ialu_cconly_reg_reg); 8887 %} 8888 8889 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8890 match(Set icc (CmpU op1 op2)); 8891 8892 size(4); 8893 format %{ "CMP $op1,$op2\t! unsigned" %} 8894 opcode(Assembler::subcc_op3, Assembler::arith_op); 8895 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8896 ins_pipe(ialu_cconly_reg_reg); 8897 %} 8898 8899 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8900 match(Set icc (CmpI op1 op2)); 8901 effect( DEF icc, USE op1 ); 8902 8903 size(4); 8904 format %{ "CMP $op1,$op2" %} 8905 opcode(Assembler::subcc_op3, Assembler::arith_op); 8906 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8907 ins_pipe(ialu_cconly_reg_imm); 8908 %} 8909 8910 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8911 match(Set icc (CmpI (AndI op1 op2) zero)); 8912 8913 size(4); 8914 format %{ "BTST $op2,$op1" %} 8915 opcode(Assembler::andcc_op3, Assembler::arith_op); 8916 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8917 ins_pipe(ialu_cconly_reg_reg_zero); 8918 %} 8919 8920 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8921 match(Set icc (CmpI (AndI op1 op2) zero)); 8922 8923 size(4); 8924 format %{ "BTST $op2,$op1" %} 8925 opcode(Assembler::andcc_op3, Assembler::arith_op); 8926 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8927 ins_pipe(ialu_cconly_reg_imm_zero); 8928 %} 8929 8930 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8931 match(Set xcc (CmpL op1 op2)); 8932 effect( DEF xcc, USE op1, USE op2 ); 8933 8934 size(4); 8935 format %{ "CMP $op1,$op2\t\t! long" %} 8936 opcode(Assembler::subcc_op3, Assembler::arith_op); 8937 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8938 ins_pipe(ialu_cconly_reg_reg); 8939 %} 8940 8941 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8942 match(Set xcc (CmpL op1 con)); 8943 effect( DEF xcc, USE op1, USE con ); 8944 8945 size(4); 8946 format %{ "CMP $op1,$con\t\t! long" %} 8947 opcode(Assembler::subcc_op3, Assembler::arith_op); 8948 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8949 ins_pipe(ialu_cconly_reg_reg); 8950 %} 8951 8952 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8953 match(Set xcc (CmpL (AndL op1 op2) zero)); 8954 effect( DEF xcc, USE op1, USE op2 ); 8955 8956 size(4); 8957 format %{ "BTST $op1,$op2\t\t! long" %} 8958 opcode(Assembler::andcc_op3, Assembler::arith_op); 8959 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8960 ins_pipe(ialu_cconly_reg_reg); 8961 %} 8962 8963 // useful for checking the alignment of a pointer: 8964 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8965 match(Set xcc (CmpL (AndL op1 con) zero)); 8966 effect( DEF xcc, USE op1, USE con ); 8967 8968 size(4); 8969 format %{ "BTST $op1,$con\t\t! long" %} 8970 opcode(Assembler::andcc_op3, Assembler::arith_op); 8971 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8972 ins_pipe(ialu_cconly_reg_reg); 8973 %} 8974 8975 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ 8976 match(Set icc (CmpU op1 op2)); 8977 8978 size(4); 8979 format %{ "CMP $op1,$op2\t! unsigned" %} 8980 opcode(Assembler::subcc_op3, Assembler::arith_op); 8981 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8982 ins_pipe(ialu_cconly_reg_imm); 8983 %} 8984 8985 // Compare Pointers 8986 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8987 match(Set pcc (CmpP op1 op2)); 8988 8989 size(4); 8990 format %{ "CMP $op1,$op2\t! ptr" %} 8991 opcode(Assembler::subcc_op3, Assembler::arith_op); 8992 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8993 ins_pipe(ialu_cconly_reg_reg); 8994 %} 8995 8996 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8997 match(Set pcc (CmpP op1 op2)); 8998 8999 size(4); 9000 format %{ "CMP $op1,$op2\t! ptr" %} 9001 opcode(Assembler::subcc_op3, Assembler::arith_op); 9002 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9003 ins_pipe(ialu_cconly_reg_imm); 9004 %} 9005 9006 // Compare Narrow oops 9007 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 9008 match(Set icc (CmpN op1 op2)); 9009 9010 size(4); 9011 format %{ "CMP $op1,$op2\t! compressed ptr" %} 9012 opcode(Assembler::subcc_op3, Assembler::arith_op); 9013 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9014 ins_pipe(ialu_cconly_reg_reg); 9015 %} 9016 9017 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 9018 match(Set icc (CmpN op1 op2)); 9019 9020 size(4); 9021 format %{ "CMP $op1,$op2\t! compressed ptr" %} 9022 opcode(Assembler::subcc_op3, Assembler::arith_op); 9023 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9024 ins_pipe(ialu_cconly_reg_imm); 9025 %} 9026 9027 //----------Max and Min-------------------------------------------------------- 9028 // Min Instructions 9029 // Conditional move for min 9030 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 9031 effect( USE_DEF op2, USE op1, USE icc ); 9032 9033 size(4); 9034 format %{ "MOVlt icc,$op1,$op2\t! min" %} 9035 opcode(Assembler::less); 9036 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 9037 ins_pipe(ialu_reg_flags); 9038 %} 9039 9040 // Min Register with Register. 9041 instruct minI_eReg(iRegI op1, iRegI op2) %{ 9042 match(Set op2 (MinI op1 op2)); 9043 ins_cost(DEFAULT_COST*2); 9044 expand %{ 9045 flagsReg icc; 9046 compI_iReg(icc,op1,op2); 9047 cmovI_reg_lt(op2,op1,icc); 9048 %} 9049 %} 9050 9051 // Max Instructions 9052 // Conditional move for max 9053 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 9054 effect( USE_DEF op2, USE op1, USE icc ); 9055 format %{ "MOVgt icc,$op1,$op2\t! max" %} 9056 opcode(Assembler::greater); 9057 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 9058 ins_pipe(ialu_reg_flags); 9059 %} 9060 9061 // Max Register with Register 9062 instruct maxI_eReg(iRegI op1, iRegI op2) %{ 9063 match(Set op2 (MaxI op1 op2)); 9064 ins_cost(DEFAULT_COST*2); 9065 expand %{ 9066 flagsReg icc; 9067 compI_iReg(icc,op1,op2); 9068 cmovI_reg_gt(op2,op1,icc); 9069 %} 9070 %} 9071 9072 9073 //----------Float Compares---------------------------------------------------- 9074 // Compare floating, generate condition code 9075 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 9076 match(Set fcc (CmpF src1 src2)); 9077 9078 size(4); 9079 format %{ "FCMPs $fcc,$src1,$src2" %} 9080 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 9081 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 9082 ins_pipe(faddF_fcc_reg_reg_zero); 9083 %} 9084 9085 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 9086 match(Set fcc (CmpD src1 src2)); 9087 9088 size(4); 9089 format %{ "FCMPd $fcc,$src1,$src2" %} 9090 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 9091 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 9092 ins_pipe(faddD_fcc_reg_reg_zero); 9093 %} 9094 9095 9096 // Compare floating, generate -1,0,1 9097 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 9098 match(Set dst (CmpF3 src1 src2)); 9099 effect(KILL fcc0); 9100 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 9101 format %{ "fcmpl $dst,$src1,$src2" %} 9102 // Primary = float 9103 opcode( true ); 9104 ins_encode( floating_cmp( dst, src1, src2 ) ); 9105 ins_pipe( floating_cmp ); 9106 %} 9107 9108 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 9109 match(Set dst (CmpD3 src1 src2)); 9110 effect(KILL fcc0); 9111 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 9112 format %{ "dcmpl $dst,$src1,$src2" %} 9113 // Primary = double (not float) 9114 opcode( false ); 9115 ins_encode( floating_cmp( dst, src1, src2 ) ); 9116 ins_pipe( floating_cmp ); 9117 %} 9118 9119 //----------Branches--------------------------------------------------------- 9120 // Jump 9121 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 9122 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 9123 match(Jump switch_val); 9124 effect(TEMP table); 9125 9126 ins_cost(350); 9127 9128 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" 9129 "LD [O7 + $switch_val], O7\n\t" 9130 "JUMP O7" %} 9131 ins_encode %{ 9132 // Calculate table address into a register. 9133 Register table_reg; 9134 Register label_reg = O7; 9135 // If we are calculating the size of this instruction don't trust 9136 // zero offsets because they might change when 9137 // MachConstantBaseNode decides to optimize the constant table 9138 // base. 9139 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { 9140 table_reg = $constanttablebase; 9141 } else { 9142 table_reg = O7; 9143 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); 9144 __ add($constanttablebase, con_offset, table_reg); 9145 } 9146 9147 // Jump to base address + switch value 9148 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); 9149 __ jmp(label_reg, G0); 9150 __ delayed()->nop(); 9151 %} 9152 ins_pipe(ialu_reg_reg); 9153 %} 9154 9155 // Direct Branch. Use V8 version with longer range. 9156 instruct branch(label labl) %{ 9157 match(Goto); 9158 effect(USE labl); 9159 9160 size(8); 9161 ins_cost(BRANCH_COST); 9162 format %{ "BA $labl" %} 9163 ins_encode %{ 9164 Label* L = $labl$$label; 9165 __ ba(*L); 9166 __ delayed()->nop(); 9167 %} 9168 ins_pipe(br); 9169 %} 9170 9171 // Direct Branch, short with no delay slot 9172 instruct branch_short(label labl) %{ 9173 match(Goto); 9174 predicate(UseCBCond); 9175 effect(USE labl); 9176 9177 size(4); 9178 ins_cost(BRANCH_COST); 9179 format %{ "BA $labl\t! short branch" %} 9180 ins_encode %{ 9181 Label* L = $labl$$label; 9182 assert(__ use_cbcond(*L), "back to back cbcond"); 9183 __ ba_short(*L); 9184 %} 9185 ins_short_branch(1); 9186 ins_avoid_back_to_back(1); 9187 ins_pipe(cbcond_reg_imm); 9188 %} 9189 9190 // Conditional Direct Branch 9191 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 9192 match(If cmp icc); 9193 effect(USE labl); 9194 9195 size(8); 9196 ins_cost(BRANCH_COST); 9197 format %{ "BP$cmp $icc,$labl" %} 9198 // Prim = bits 24-22, Secnd = bits 31-30 9199 ins_encode( enc_bp( labl, cmp, icc ) ); 9200 ins_pipe(br_cc); 9201 %} 9202 9203 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9204 match(If cmp icc); 9205 effect(USE labl); 9206 9207 ins_cost(BRANCH_COST); 9208 format %{ "BP$cmp $icc,$labl" %} 9209 // Prim = bits 24-22, Secnd = bits 31-30 9210 ins_encode( enc_bp( labl, cmp, icc ) ); 9211 ins_pipe(br_cc); 9212 %} 9213 9214 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 9215 match(If cmp pcc); 9216 effect(USE labl); 9217 9218 size(8); 9219 ins_cost(BRANCH_COST); 9220 format %{ "BP$cmp $pcc,$labl" %} 9221 ins_encode %{ 9222 Label* L = $labl$$label; 9223 Assembler::Predict predict_taken = 9224 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9225 9226 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9227 __ delayed()->nop(); 9228 %} 9229 ins_pipe(br_cc); 9230 %} 9231 9232 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 9233 match(If cmp fcc); 9234 effect(USE labl); 9235 9236 size(8); 9237 ins_cost(BRANCH_COST); 9238 format %{ "FBP$cmp $fcc,$labl" %} 9239 ins_encode %{ 9240 Label* L = $labl$$label; 9241 Assembler::Predict predict_taken = 9242 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9243 9244 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); 9245 __ delayed()->nop(); 9246 %} 9247 ins_pipe(br_fcc); 9248 %} 9249 9250 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 9251 match(CountedLoopEnd cmp icc); 9252 effect(USE labl); 9253 9254 size(8); 9255 ins_cost(BRANCH_COST); 9256 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9257 // Prim = bits 24-22, Secnd = bits 31-30 9258 ins_encode( enc_bp( labl, cmp, icc ) ); 9259 ins_pipe(br_cc); 9260 %} 9261 9262 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9263 match(CountedLoopEnd cmp icc); 9264 effect(USE labl); 9265 9266 size(8); 9267 ins_cost(BRANCH_COST); 9268 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9269 // Prim = bits 24-22, Secnd = bits 31-30 9270 ins_encode( enc_bp( labl, cmp, icc ) ); 9271 ins_pipe(br_cc); 9272 %} 9273 9274 // Compare and branch instructions 9275 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9276 match(If cmp (CmpI op1 op2)); 9277 effect(USE labl, KILL icc); 9278 9279 size(12); 9280 ins_cost(BRANCH_COST); 9281 format %{ "CMP $op1,$op2\t! int\n\t" 9282 "BP$cmp $labl" %} 9283 ins_encode %{ 9284 Label* L = $labl$$label; 9285 Assembler::Predict predict_taken = 9286 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9287 __ cmp($op1$$Register, $op2$$Register); 9288 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9289 __ delayed()->nop(); 9290 %} 9291 ins_pipe(cmp_br_reg_reg); 9292 %} 9293 9294 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9295 match(If cmp (CmpI op1 op2)); 9296 effect(USE labl, KILL icc); 9297 9298 size(12); 9299 ins_cost(BRANCH_COST); 9300 format %{ "CMP $op1,$op2\t! int\n\t" 9301 "BP$cmp $labl" %} 9302 ins_encode %{ 9303 Label* L = $labl$$label; 9304 Assembler::Predict predict_taken = 9305 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9306 __ cmp($op1$$Register, $op2$$constant); 9307 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9308 __ delayed()->nop(); 9309 %} 9310 ins_pipe(cmp_br_reg_imm); 9311 %} 9312 9313 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9314 match(If cmp (CmpU op1 op2)); 9315 effect(USE labl, KILL icc); 9316 9317 size(12); 9318 ins_cost(BRANCH_COST); 9319 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9320 "BP$cmp $labl" %} 9321 ins_encode %{ 9322 Label* L = $labl$$label; 9323 Assembler::Predict predict_taken = 9324 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9325 __ cmp($op1$$Register, $op2$$Register); 9326 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9327 __ delayed()->nop(); 9328 %} 9329 ins_pipe(cmp_br_reg_reg); 9330 %} 9331 9332 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9333 match(If cmp (CmpU op1 op2)); 9334 effect(USE labl, KILL icc); 9335 9336 size(12); 9337 ins_cost(BRANCH_COST); 9338 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9339 "BP$cmp $labl" %} 9340 ins_encode %{ 9341 Label* L = $labl$$label; 9342 Assembler::Predict predict_taken = 9343 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9344 __ cmp($op1$$Register, $op2$$constant); 9345 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9346 __ delayed()->nop(); 9347 %} 9348 ins_pipe(cmp_br_reg_imm); 9349 %} 9350 9351 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9352 match(If cmp (CmpL op1 op2)); 9353 effect(USE labl, KILL xcc); 9354 9355 size(12); 9356 ins_cost(BRANCH_COST); 9357 format %{ "CMP $op1,$op2\t! long\n\t" 9358 "BP$cmp $labl" %} 9359 ins_encode %{ 9360 Label* L = $labl$$label; 9361 Assembler::Predict predict_taken = 9362 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9363 __ cmp($op1$$Register, $op2$$Register); 9364 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9365 __ delayed()->nop(); 9366 %} 9367 ins_pipe(cmp_br_reg_reg); 9368 %} 9369 9370 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9371 match(If cmp (CmpL op1 op2)); 9372 effect(USE labl, KILL xcc); 9373 9374 size(12); 9375 ins_cost(BRANCH_COST); 9376 format %{ "CMP $op1,$op2\t! long\n\t" 9377 "BP$cmp $labl" %} 9378 ins_encode %{ 9379 Label* L = $labl$$label; 9380 Assembler::Predict predict_taken = 9381 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9382 __ cmp($op1$$Register, $op2$$constant); 9383 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9384 __ delayed()->nop(); 9385 %} 9386 ins_pipe(cmp_br_reg_imm); 9387 %} 9388 9389 // Compare Pointers and branch 9390 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9391 match(If cmp (CmpP op1 op2)); 9392 effect(USE labl, KILL pcc); 9393 9394 size(12); 9395 ins_cost(BRANCH_COST); 9396 format %{ "CMP $op1,$op2\t! ptr\n\t" 9397 "B$cmp $labl" %} 9398 ins_encode %{ 9399 Label* L = $labl$$label; 9400 Assembler::Predict predict_taken = 9401 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9402 __ cmp($op1$$Register, $op2$$Register); 9403 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9404 __ delayed()->nop(); 9405 %} 9406 ins_pipe(cmp_br_reg_reg); 9407 %} 9408 9409 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9410 match(If cmp (CmpP op1 null)); 9411 effect(USE labl, KILL pcc); 9412 9413 size(12); 9414 ins_cost(BRANCH_COST); 9415 format %{ "CMP $op1,0\t! ptr\n\t" 9416 "B$cmp $labl" %} 9417 ins_encode %{ 9418 Label* L = $labl$$label; 9419 Assembler::Predict predict_taken = 9420 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9421 __ cmp($op1$$Register, G0); 9422 // bpr() is not used here since it has shorter distance. 9423 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9424 __ delayed()->nop(); 9425 %} 9426 ins_pipe(cmp_br_reg_reg); 9427 %} 9428 9429 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9430 match(If cmp (CmpN op1 op2)); 9431 effect(USE labl, KILL icc); 9432 9433 size(12); 9434 ins_cost(BRANCH_COST); 9435 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" 9436 "BP$cmp $labl" %} 9437 ins_encode %{ 9438 Label* L = $labl$$label; 9439 Assembler::Predict predict_taken = 9440 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9441 __ cmp($op1$$Register, $op2$$Register); 9442 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9443 __ delayed()->nop(); 9444 %} 9445 ins_pipe(cmp_br_reg_reg); 9446 %} 9447 9448 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9449 match(If cmp (CmpN op1 null)); 9450 effect(USE labl, KILL icc); 9451 9452 size(12); 9453 ins_cost(BRANCH_COST); 9454 format %{ "CMP $op1,0\t! compressed ptr\n\t" 9455 "BP$cmp $labl" %} 9456 ins_encode %{ 9457 Label* L = $labl$$label; 9458 Assembler::Predict predict_taken = 9459 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9460 __ cmp($op1$$Register, G0); 9461 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9462 __ delayed()->nop(); 9463 %} 9464 ins_pipe(cmp_br_reg_reg); 9465 %} 9466 9467 // Loop back branch 9468 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9469 match(CountedLoopEnd cmp (CmpI op1 op2)); 9470 effect(USE labl, KILL icc); 9471 9472 size(12); 9473 ins_cost(BRANCH_COST); 9474 format %{ "CMP $op1,$op2\t! int\n\t" 9475 "BP$cmp $labl\t! Loop end" %} 9476 ins_encode %{ 9477 Label* L = $labl$$label; 9478 Assembler::Predict predict_taken = 9479 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9480 __ cmp($op1$$Register, $op2$$Register); 9481 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9482 __ delayed()->nop(); 9483 %} 9484 ins_pipe(cmp_br_reg_reg); 9485 %} 9486 9487 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9488 match(CountedLoopEnd cmp (CmpI op1 op2)); 9489 effect(USE labl, KILL icc); 9490 9491 size(12); 9492 ins_cost(BRANCH_COST); 9493 format %{ "CMP $op1,$op2\t! int\n\t" 9494 "BP$cmp $labl\t! Loop end" %} 9495 ins_encode %{ 9496 Label* L = $labl$$label; 9497 Assembler::Predict predict_taken = 9498 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9499 __ cmp($op1$$Register, $op2$$constant); 9500 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9501 __ delayed()->nop(); 9502 %} 9503 ins_pipe(cmp_br_reg_imm); 9504 %} 9505 9506 // Short compare and branch instructions 9507 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9508 match(If cmp (CmpI op1 op2)); 9509 predicate(UseCBCond); 9510 effect(USE labl, KILL icc); 9511 9512 size(4); 9513 ins_cost(BRANCH_COST); 9514 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9515 ins_encode %{ 9516 Label* L = $labl$$label; 9517 assert(__ use_cbcond(*L), "back to back cbcond"); 9518 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9519 %} 9520 ins_short_branch(1); 9521 ins_avoid_back_to_back(1); 9522 ins_pipe(cbcond_reg_reg); 9523 %} 9524 9525 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9526 match(If cmp (CmpI op1 op2)); 9527 predicate(UseCBCond); 9528 effect(USE labl, KILL icc); 9529 9530 size(4); 9531 ins_cost(BRANCH_COST); 9532 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9533 ins_encode %{ 9534 Label* L = $labl$$label; 9535 assert(__ use_cbcond(*L), "back to back cbcond"); 9536 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9537 %} 9538 ins_short_branch(1); 9539 ins_avoid_back_to_back(1); 9540 ins_pipe(cbcond_reg_imm); 9541 %} 9542 9543 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9544 match(If cmp (CmpU op1 op2)); 9545 predicate(UseCBCond); 9546 effect(USE labl, KILL icc); 9547 9548 size(4); 9549 ins_cost(BRANCH_COST); 9550 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9551 ins_encode %{ 9552 Label* L = $labl$$label; 9553 assert(__ use_cbcond(*L), "back to back cbcond"); 9554 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9555 %} 9556 ins_short_branch(1); 9557 ins_avoid_back_to_back(1); 9558 ins_pipe(cbcond_reg_reg); 9559 %} 9560 9561 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9562 match(If cmp (CmpU op1 op2)); 9563 predicate(UseCBCond); 9564 effect(USE labl, KILL icc); 9565 9566 size(4); 9567 ins_cost(BRANCH_COST); 9568 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9569 ins_encode %{ 9570 Label* L = $labl$$label; 9571 assert(__ use_cbcond(*L), "back to back cbcond"); 9572 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9573 %} 9574 ins_short_branch(1); 9575 ins_avoid_back_to_back(1); 9576 ins_pipe(cbcond_reg_imm); 9577 %} 9578 9579 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9580 match(If cmp (CmpL op1 op2)); 9581 predicate(UseCBCond); 9582 effect(USE labl, KILL xcc); 9583 9584 size(4); 9585 ins_cost(BRANCH_COST); 9586 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9587 ins_encode %{ 9588 Label* L = $labl$$label; 9589 assert(__ use_cbcond(*L), "back to back cbcond"); 9590 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9591 %} 9592 ins_short_branch(1); 9593 ins_avoid_back_to_back(1); 9594 ins_pipe(cbcond_reg_reg); 9595 %} 9596 9597 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9598 match(If cmp (CmpL op1 op2)); 9599 predicate(UseCBCond); 9600 effect(USE labl, KILL xcc); 9601 9602 size(4); 9603 ins_cost(BRANCH_COST); 9604 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9605 ins_encode %{ 9606 Label* L = $labl$$label; 9607 assert(__ use_cbcond(*L), "back to back cbcond"); 9608 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9609 %} 9610 ins_short_branch(1); 9611 ins_avoid_back_to_back(1); 9612 ins_pipe(cbcond_reg_imm); 9613 %} 9614 9615 // Compare Pointers and branch 9616 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9617 match(If cmp (CmpP op1 op2)); 9618 predicate(UseCBCond); 9619 effect(USE labl, KILL pcc); 9620 9621 size(4); 9622 ins_cost(BRANCH_COST); 9623 #ifdef _LP64 9624 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} 9625 #else 9626 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} 9627 #endif 9628 ins_encode %{ 9629 Label* L = $labl$$label; 9630 assert(__ use_cbcond(*L), "back to back cbcond"); 9631 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); 9632 %} 9633 ins_short_branch(1); 9634 ins_avoid_back_to_back(1); 9635 ins_pipe(cbcond_reg_reg); 9636 %} 9637 9638 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9639 match(If cmp (CmpP op1 null)); 9640 predicate(UseCBCond); 9641 effect(USE labl, KILL pcc); 9642 9643 size(4); 9644 ins_cost(BRANCH_COST); 9645 #ifdef _LP64 9646 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} 9647 #else 9648 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} 9649 #endif 9650 ins_encode %{ 9651 Label* L = $labl$$label; 9652 assert(__ use_cbcond(*L), "back to back cbcond"); 9653 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); 9654 %} 9655 ins_short_branch(1); 9656 ins_avoid_back_to_back(1); 9657 ins_pipe(cbcond_reg_reg); 9658 %} 9659 9660 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9661 match(If cmp (CmpN op1 op2)); 9662 predicate(UseCBCond); 9663 effect(USE labl, KILL icc); 9664 9665 size(4); 9666 ins_cost(BRANCH_COST); 9667 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} 9668 ins_encode %{ 9669 Label* L = $labl$$label; 9670 assert(__ use_cbcond(*L), "back to back cbcond"); 9671 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9672 %} 9673 ins_short_branch(1); 9674 ins_avoid_back_to_back(1); 9675 ins_pipe(cbcond_reg_reg); 9676 %} 9677 9678 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9679 match(If cmp (CmpN op1 null)); 9680 predicate(UseCBCond); 9681 effect(USE labl, KILL icc); 9682 9683 size(4); 9684 ins_cost(BRANCH_COST); 9685 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} 9686 ins_encode %{ 9687 Label* L = $labl$$label; 9688 assert(__ use_cbcond(*L), "back to back cbcond"); 9689 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); 9690 %} 9691 ins_short_branch(1); 9692 ins_avoid_back_to_back(1); 9693 ins_pipe(cbcond_reg_reg); 9694 %} 9695 9696 // Loop back branch 9697 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9698 match(CountedLoopEnd cmp (CmpI op1 op2)); 9699 predicate(UseCBCond); 9700 effect(USE labl, KILL icc); 9701 9702 size(4); 9703 ins_cost(BRANCH_COST); 9704 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9705 ins_encode %{ 9706 Label* L = $labl$$label; 9707 assert(__ use_cbcond(*L), "back to back cbcond"); 9708 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9709 %} 9710 ins_short_branch(1); 9711 ins_avoid_back_to_back(1); 9712 ins_pipe(cbcond_reg_reg); 9713 %} 9714 9715 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9716 match(CountedLoopEnd cmp (CmpI op1 op2)); 9717 predicate(UseCBCond); 9718 effect(USE labl, KILL icc); 9719 9720 size(4); 9721 ins_cost(BRANCH_COST); 9722 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9723 ins_encode %{ 9724 Label* L = $labl$$label; 9725 assert(__ use_cbcond(*L), "back to back cbcond"); 9726 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9727 %} 9728 ins_short_branch(1); 9729 ins_avoid_back_to_back(1); 9730 ins_pipe(cbcond_reg_imm); 9731 %} 9732 9733 // Branch-on-register tests all 64 bits. We assume that values 9734 // in 64-bit registers always remains zero or sign extended 9735 // unless our code munges the high bits. Interrupts can chop 9736 // the high order bits to zero or sign at any time. 9737 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9738 match(If cmp (CmpI op1 zero)); 9739 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9740 effect(USE labl); 9741 9742 size(8); 9743 ins_cost(BRANCH_COST); 9744 format %{ "BR$cmp $op1,$labl" %} 9745 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9746 ins_pipe(br_reg); 9747 %} 9748 9749 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9750 match(If cmp (CmpP op1 null)); 9751 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9752 effect(USE labl); 9753 9754 size(8); 9755 ins_cost(BRANCH_COST); 9756 format %{ "BR$cmp $op1,$labl" %} 9757 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9758 ins_pipe(br_reg); 9759 %} 9760 9761 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9762 match(If cmp (CmpL op1 zero)); 9763 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9764 effect(USE labl); 9765 9766 size(8); 9767 ins_cost(BRANCH_COST); 9768 format %{ "BR$cmp $op1,$labl" %} 9769 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9770 ins_pipe(br_reg); 9771 %} 9772 9773 9774 // ============================================================================ 9775 // Long Compare 9776 // 9777 // Currently we hold longs in 2 registers. Comparing such values efficiently 9778 // is tricky. The flavor of compare used depends on whether we are testing 9779 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9780 // The GE test is the negated LT test. The LE test can be had by commuting 9781 // the operands (yielding a GE test) and then negating; negate again for the 9782 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9783 // NE test is negated from that. 9784 9785 // Due to a shortcoming in the ADLC, it mixes up expressions like: 9786 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9787 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9788 // are collapsed internally in the ADLC's dfa-gen code. The match for 9789 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9790 // foo match ends up with the wrong leaf. One fix is to not match both 9791 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 9792 // both forms beat the trinary form of long-compare and both are very useful 9793 // on Intel which has so few registers. 9794 9795 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9796 match(If cmp xcc); 9797 effect(USE labl); 9798 9799 size(8); 9800 ins_cost(BRANCH_COST); 9801 format %{ "BP$cmp $xcc,$labl" %} 9802 ins_encode %{ 9803 Label* L = $labl$$label; 9804 Assembler::Predict predict_taken = 9805 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9806 9807 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9808 __ delayed()->nop(); 9809 %} 9810 ins_pipe(br_cc); 9811 %} 9812 9813 // Manifest a CmpL3 result in an integer register. Very painful. 9814 // This is the test to avoid. 9815 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9816 match(Set dst (CmpL3 src1 src2) ); 9817 effect( KILL ccr ); 9818 ins_cost(6*DEFAULT_COST); 9819 size(24); 9820 format %{ "CMP $src1,$src2\t\t! long\n" 9821 "\tBLT,a,pn done\n" 9822 "\tMOV -1,$dst\t! delay slot\n" 9823 "\tBGT,a,pn done\n" 9824 "\tMOV 1,$dst\t! delay slot\n" 9825 "\tCLR $dst\n" 9826 "done:" %} 9827 ins_encode( cmpl_flag(src1,src2,dst) ); 9828 ins_pipe(cmpL_reg); 9829 %} 9830 9831 // Conditional move 9832 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9833 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9834 ins_cost(150); 9835 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9836 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9837 ins_pipe(ialu_reg); 9838 %} 9839 9840 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9841 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9842 ins_cost(140); 9843 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9844 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9845 ins_pipe(ialu_imm); 9846 %} 9847 9848 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9849 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9850 ins_cost(150); 9851 format %{ "MOV$cmp $xcc,$src,$dst" %} 9852 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9853 ins_pipe(ialu_reg); 9854 %} 9855 9856 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9857 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9858 ins_cost(140); 9859 format %{ "MOV$cmp $xcc,$src,$dst" %} 9860 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9861 ins_pipe(ialu_imm); 9862 %} 9863 9864 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9865 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9866 ins_cost(150); 9867 format %{ "MOV$cmp $xcc,$src,$dst" %} 9868 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9869 ins_pipe(ialu_reg); 9870 %} 9871 9872 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9873 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9874 ins_cost(150); 9875 format %{ "MOV$cmp $xcc,$src,$dst" %} 9876 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9877 ins_pipe(ialu_reg); 9878 %} 9879 9880 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9881 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9882 ins_cost(140); 9883 format %{ "MOV$cmp $xcc,$src,$dst" %} 9884 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9885 ins_pipe(ialu_imm); 9886 %} 9887 9888 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9889 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9890 ins_cost(150); 9891 opcode(0x101); 9892 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9893 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9894 ins_pipe(int_conditional_float_move); 9895 %} 9896 9897 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9898 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9899 ins_cost(150); 9900 opcode(0x102); 9901 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9902 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9903 ins_pipe(int_conditional_float_move); 9904 %} 9905 9906 // ============================================================================ 9907 // Safepoint Instruction 9908 instruct safePoint_poll(iRegP poll) %{ 9909 match(SafePoint poll); 9910 effect(USE poll); 9911 9912 size(4); 9913 #ifdef _LP64 9914 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9915 #else 9916 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 9917 #endif 9918 ins_encode %{ 9919 __ relocate(relocInfo::poll_type); 9920 __ ld_ptr($poll$$Register, 0, G0); 9921 %} 9922 ins_pipe(loadPollP); 9923 %} 9924 9925 // ============================================================================ 9926 // Call Instructions 9927 // Call Java Static Instruction 9928 instruct CallStaticJavaDirect( method meth ) %{ 9929 match(CallStaticJava); 9930 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9931 effect(USE meth); 9932 9933 size(8); 9934 ins_cost(CALL_COST); 9935 format %{ "CALL,static ; NOP ==> " %} 9936 ins_encode( Java_Static_Call( meth ), call_epilog ); 9937 ins_pipe(simple_call); 9938 %} 9939 9940 // Call Java Static Instruction (method handle version) 9941 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 9942 match(CallStaticJava); 9943 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9944 effect(USE meth, KILL l7_mh_SP_save); 9945 9946 size(16); 9947 ins_cost(CALL_COST); 9948 format %{ "CALL,static/MethodHandle" %} 9949 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 9950 ins_pipe(simple_call); 9951 %} 9952 9953 // Call Java Dynamic Instruction 9954 instruct CallDynamicJavaDirect( method meth ) %{ 9955 match(CallDynamicJava); 9956 effect(USE meth); 9957 9958 ins_cost(CALL_COST); 9959 format %{ "SET (empty),R_G5\n\t" 9960 "CALL,dynamic ; NOP ==> " %} 9961 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 9962 ins_pipe(call); 9963 %} 9964 9965 // Call Runtime Instruction 9966 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 9967 match(CallRuntime); 9968 effect(USE meth, KILL l7); 9969 ins_cost(CALL_COST); 9970 format %{ "CALL,runtime" %} 9971 ins_encode( Java_To_Runtime( meth ), 9972 call_epilog, adjust_long_from_native_call ); 9973 ins_pipe(simple_call); 9974 %} 9975 9976 // Call runtime without safepoint - same as CallRuntime 9977 instruct CallLeafDirect(method meth, l7RegP l7) %{ 9978 match(CallLeaf); 9979 effect(USE meth, KILL l7); 9980 ins_cost(CALL_COST); 9981 format %{ "CALL,runtime leaf" %} 9982 ins_encode( Java_To_Runtime( meth ), 9983 call_epilog, 9984 adjust_long_from_native_call ); 9985 ins_pipe(simple_call); 9986 %} 9987 9988 // Call runtime without safepoint - same as CallLeaf 9989 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 9990 match(CallLeafNoFP); 9991 effect(USE meth, KILL l7); 9992 ins_cost(CALL_COST); 9993 format %{ "CALL,runtime leaf nofp" %} 9994 ins_encode( Java_To_Runtime( meth ), 9995 call_epilog, 9996 adjust_long_from_native_call ); 9997 ins_pipe(simple_call); 9998 %} 9999 10000 // Tail Call; Jump from runtime stub to Java code. 10001 // Also known as an 'interprocedural jump'. 10002 // Target of jump will eventually return to caller. 10003 // TailJump below removes the return address. 10004 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 10005 match(TailCall jump_target method_oop ); 10006 10007 ins_cost(CALL_COST); 10008 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 10009 ins_encode(form_jmpl(jump_target)); 10010 ins_pipe(tail_call); 10011 %} 10012 10013 10014 // Return Instruction 10015 instruct Ret() %{ 10016 match(Return); 10017 10018 // The epilogue node did the ret already. 10019 size(0); 10020 format %{ "! return" %} 10021 ins_encode(); 10022 ins_pipe(empty); 10023 %} 10024 10025 10026 // Tail Jump; remove the return address; jump to target. 10027 // TailCall above leaves the return address around. 10028 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 10029 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 10030 // "restore" before this instruction (in Epilogue), we need to materialize it 10031 // in %i0. 10032 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 10033 match( TailJump jump_target ex_oop ); 10034 ins_cost(CALL_COST); 10035 format %{ "! discard R_O7\n\t" 10036 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 10037 ins_encode(form_jmpl_set_exception_pc(jump_target)); 10038 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 10039 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 10040 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 10041 ins_pipe(tail_call); 10042 %} 10043 10044 // Create exception oop: created by stack-crawling runtime code. 10045 // Created exception is now available to this handler, and is setup 10046 // just prior to jumping to this handler. No code emitted. 10047 instruct CreateException( o0RegP ex_oop ) 10048 %{ 10049 match(Set ex_oop (CreateEx)); 10050 ins_cost(0); 10051 10052 size(0); 10053 // use the following format syntax 10054 format %{ "! exception oop is in R_O0; no code emitted" %} 10055 ins_encode(); 10056 ins_pipe(empty); 10057 %} 10058 10059 10060 // Rethrow exception: 10061 // The exception oop will come in the first argument position. 10062 // Then JUMP (not call) to the rethrow stub code. 10063 instruct RethrowException() 10064 %{ 10065 match(Rethrow); 10066 ins_cost(CALL_COST); 10067 10068 // use the following format syntax 10069 format %{ "Jmp rethrow_stub" %} 10070 ins_encode(enc_rethrow); 10071 ins_pipe(tail_call); 10072 %} 10073 10074 10075 // Die now 10076 instruct ShouldNotReachHere( ) 10077 %{ 10078 match(Halt); 10079 ins_cost(CALL_COST); 10080 10081 size(4); 10082 // Use the following format syntax 10083 format %{ "ILLTRAP ; ShouldNotReachHere" %} 10084 ins_encode( form2_illtrap() ); 10085 ins_pipe(tail_call); 10086 %} 10087 10088 // ============================================================================ 10089 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10090 // array for an instance of the superklass. Set a hidden internal cache on a 10091 // hit (cache is checked with exposed code in gen_subtype_check()). Return 10092 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10093 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 10094 match(Set index (PartialSubtypeCheck sub super)); 10095 effect( KILL pcc, KILL o7 ); 10096 ins_cost(DEFAULT_COST*10); 10097 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 10098 ins_encode( enc_PartialSubtypeCheck() ); 10099 ins_pipe(partial_subtype_check_pipe); 10100 %} 10101 10102 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 10103 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 10104 effect( KILL idx, KILL o7 ); 10105 ins_cost(DEFAULT_COST*10); 10106 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 10107 ins_encode( enc_PartialSubtypeCheck() ); 10108 ins_pipe(partial_subtype_check_pipe); 10109 %} 10110 10111 10112 // ============================================================================ 10113 // inlined locking and unlocking 10114 10115 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 10116 match(Set pcc (FastLock object box)); 10117 10118 effect(TEMP scratch2, USE_KILL box, KILL scratch); 10119 ins_cost(100); 10120 10121 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 10122 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 10123 ins_pipe(long_memory_op); 10124 %} 10125 10126 10127 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 10128 match(Set pcc (FastUnlock object box)); 10129 effect(TEMP scratch2, USE_KILL box, KILL scratch); 10130 ins_cost(100); 10131 10132 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 10133 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 10134 ins_pipe(long_memory_op); 10135 %} 10136 10137 // The encodings are generic. 10138 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 10139 predicate(!use_block_zeroing(n->in(2)) ); 10140 match(Set dummy (ClearArray cnt base)); 10141 effect(TEMP temp, KILL ccr); 10142 ins_cost(300); 10143 format %{ "MOV $cnt,$temp\n" 10144 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 10145 " BRge loop\t\t! Clearing loop\n" 10146 " STX G0,[$base+$temp]\t! delay slot" %} 10147 10148 ins_encode %{ 10149 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 10150 Register nof_bytes_arg = $cnt$$Register; 10151 Register nof_bytes_tmp = $temp$$Register; 10152 Register base_pointer_arg = $base$$Register; 10153 10154 Label loop; 10155 __ mov(nof_bytes_arg, nof_bytes_tmp); 10156 10157 // Loop and clear, walking backwards through the array. 10158 // nof_bytes_tmp (if >0) is always the number of bytes to zero 10159 __ bind(loop); 10160 __ deccc(nof_bytes_tmp, 8); 10161 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 10162 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 10163 // %%%% this mini-loop must not cross a cache boundary! 10164 %} 10165 ins_pipe(long_memory_op); 10166 %} 10167 10168 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ 10169 predicate(use_block_zeroing(n->in(2))); 10170 match(Set dummy (ClearArray cnt base)); 10171 effect(USE_KILL cnt, USE_KILL base, KILL ccr); 10172 ins_cost(300); 10173 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 10174 10175 ins_encode %{ 10176 10177 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 10178 Register to = $base$$Register; 10179 Register count = $cnt$$Register; 10180 10181 Label Ldone; 10182 __ nop(); // Separate short branches 10183 // Use BIS for zeroing (temp is not used). 10184 __ bis_zeroing(to, count, G0, Ldone); 10185 __ bind(Ldone); 10186 10187 %} 10188 ins_pipe(long_memory_op); 10189 %} 10190 10191 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ 10192 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); 10193 match(Set dummy (ClearArray cnt base)); 10194 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); 10195 ins_cost(300); 10196 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 10197 10198 ins_encode %{ 10199 10200 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 10201 Register to = $base$$Register; 10202 Register count = $cnt$$Register; 10203 Register temp = $tmp$$Register; 10204 10205 Label Ldone; 10206 __ nop(); // Separate short branches 10207 // Use BIS for zeroing 10208 __ bis_zeroing(to, count, temp, Ldone); 10209 __ bind(Ldone); 10210 10211 %} 10212 ins_pipe(long_memory_op); 10213 %} 10214 10215 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10216 o7RegI tmp, flagsReg ccr) %{ 10217 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10218 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 10219 ins_cost(300); 10220 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 10221 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); 10222 ins_pipe(long_memory_op); 10223 %} 10224 10225 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 10226 o7RegI tmp, flagsReg ccr) %{ 10227 match(Set result (StrEquals (Binary str1 str2) cnt)); 10228 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 10229 ins_cost(300); 10230 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} 10231 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); 10232 ins_pipe(long_memory_op); 10233 %} 10234 10235 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 10236 o7RegI tmp2, flagsReg ccr) %{ 10237 match(Set result (AryEq ary1 ary2)); 10238 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 10239 ins_cost(300); 10240 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 10241 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); 10242 ins_pipe(long_memory_op); 10243 %} 10244 10245 10246 //---------- Zeros Count Instructions ------------------------------------------ 10247 10248 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ 10249 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10250 match(Set dst (CountLeadingZerosI src)); 10251 effect(TEMP dst, TEMP tmp, KILL cr); 10252 10253 // x |= (x >> 1); 10254 // x |= (x >> 2); 10255 // x |= (x >> 4); 10256 // x |= (x >> 8); 10257 // x |= (x >> 16); 10258 // return (WORDBITS - popc(x)); 10259 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 10260 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 10261 "OR $dst,$tmp,$dst\n\t" 10262 "SRL $dst,2,$tmp\n\t" 10263 "OR $dst,$tmp,$dst\n\t" 10264 "SRL $dst,4,$tmp\n\t" 10265 "OR $dst,$tmp,$dst\n\t" 10266 "SRL $dst,8,$tmp\n\t" 10267 "OR $dst,$tmp,$dst\n\t" 10268 "SRL $dst,16,$tmp\n\t" 10269 "OR $dst,$tmp,$dst\n\t" 10270 "POPC $dst,$dst\n\t" 10271 "MOV 32,$tmp\n\t" 10272 "SUB $tmp,$dst,$dst" %} 10273 ins_encode %{ 10274 Register Rdst = $dst$$Register; 10275 Register Rsrc = $src$$Register; 10276 Register Rtmp = $tmp$$Register; 10277 __ srl(Rsrc, 1, Rtmp); 10278 __ srl(Rsrc, 0, Rdst); 10279 __ or3(Rdst, Rtmp, Rdst); 10280 __ srl(Rdst, 2, Rtmp); 10281 __ or3(Rdst, Rtmp, Rdst); 10282 __ srl(Rdst, 4, Rtmp); 10283 __ or3(Rdst, Rtmp, Rdst); 10284 __ srl(Rdst, 8, Rtmp); 10285 __ or3(Rdst, Rtmp, Rdst); 10286 __ srl(Rdst, 16, Rtmp); 10287 __ or3(Rdst, Rtmp, Rdst); 10288 __ popc(Rdst, Rdst); 10289 __ mov(BitsPerInt, Rtmp); 10290 __ sub(Rtmp, Rdst, Rdst); 10291 %} 10292 ins_pipe(ialu_reg); 10293 %} 10294 10295 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ 10296 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10297 match(Set dst (CountLeadingZerosL src)); 10298 effect(TEMP dst, TEMP tmp, KILL cr); 10299 10300 // x |= (x >> 1); 10301 // x |= (x >> 2); 10302 // x |= (x >> 4); 10303 // x |= (x >> 8); 10304 // x |= (x >> 16); 10305 // x |= (x >> 32); 10306 // return (WORDBITS - popc(x)); 10307 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 10308 "OR $src,$tmp,$dst\n\t" 10309 "SRLX $dst,2,$tmp\n\t" 10310 "OR $dst,$tmp,$dst\n\t" 10311 "SRLX $dst,4,$tmp\n\t" 10312 "OR $dst,$tmp,$dst\n\t" 10313 "SRLX $dst,8,$tmp\n\t" 10314 "OR $dst,$tmp,$dst\n\t" 10315 "SRLX $dst,16,$tmp\n\t" 10316 "OR $dst,$tmp,$dst\n\t" 10317 "SRLX $dst,32,$tmp\n\t" 10318 "OR $dst,$tmp,$dst\n\t" 10319 "POPC $dst,$dst\n\t" 10320 "MOV 64,$tmp\n\t" 10321 "SUB $tmp,$dst,$dst" %} 10322 ins_encode %{ 10323 Register Rdst = $dst$$Register; 10324 Register Rsrc = $src$$Register; 10325 Register Rtmp = $tmp$$Register; 10326 __ srlx(Rsrc, 1, Rtmp); 10327 __ or3( Rsrc, Rtmp, Rdst); 10328 __ srlx(Rdst, 2, Rtmp); 10329 __ or3( Rdst, Rtmp, Rdst); 10330 __ srlx(Rdst, 4, Rtmp); 10331 __ or3( Rdst, Rtmp, Rdst); 10332 __ srlx(Rdst, 8, Rtmp); 10333 __ or3( Rdst, Rtmp, Rdst); 10334 __ srlx(Rdst, 16, Rtmp); 10335 __ or3( Rdst, Rtmp, Rdst); 10336 __ srlx(Rdst, 32, Rtmp); 10337 __ or3( Rdst, Rtmp, Rdst); 10338 __ popc(Rdst, Rdst); 10339 __ mov(BitsPerLong, Rtmp); 10340 __ sub(Rtmp, Rdst, Rdst); 10341 %} 10342 ins_pipe(ialu_reg); 10343 %} 10344 10345 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ 10346 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10347 match(Set dst (CountTrailingZerosI src)); 10348 effect(TEMP dst, KILL cr); 10349 10350 // return popc(~x & (x - 1)); 10351 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 10352 "ANDN $dst,$src,$dst\n\t" 10353 "SRL $dst,R_G0,$dst\n\t" 10354 "POPC $dst,$dst" %} 10355 ins_encode %{ 10356 Register Rdst = $dst$$Register; 10357 Register Rsrc = $src$$Register; 10358 __ sub(Rsrc, 1, Rdst); 10359 __ andn(Rdst, Rsrc, Rdst); 10360 __ srl(Rdst, G0, Rdst); 10361 __ popc(Rdst, Rdst); 10362 %} 10363 ins_pipe(ialu_reg); 10364 %} 10365 10366 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ 10367 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10368 match(Set dst (CountTrailingZerosL src)); 10369 effect(TEMP dst, KILL cr); 10370 10371 // return popc(~x & (x - 1)); 10372 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 10373 "ANDN $dst,$src,$dst\n\t" 10374 "POPC $dst,$dst" %} 10375 ins_encode %{ 10376 Register Rdst = $dst$$Register; 10377 Register Rsrc = $src$$Register; 10378 __ sub(Rsrc, 1, Rdst); 10379 __ andn(Rdst, Rsrc, Rdst); 10380 __ popc(Rdst, Rdst); 10381 %} 10382 ins_pipe(ialu_reg); 10383 %} 10384 10385 10386 //---------- Population Count Instructions ------------------------------------- 10387 10388 instruct popCountI(iRegIsafe dst, iRegI src) %{ 10389 predicate(UsePopCountInstruction); 10390 match(Set dst (PopCountI src)); 10391 10392 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" 10393 "POPC $dst, $dst" %} 10394 ins_encode %{ 10395 __ srl($src$$Register, G0, $dst$$Register); 10396 __ popc($dst$$Register, $dst$$Register); 10397 %} 10398 ins_pipe(ialu_reg); 10399 %} 10400 10401 // Note: Long.bitCount(long) returns an int. 10402 instruct popCountL(iRegIsafe dst, iRegL src) %{ 10403 predicate(UsePopCountInstruction); 10404 match(Set dst (PopCountL src)); 10405 10406 format %{ "POPC $src, $dst" %} 10407 ins_encode %{ 10408 __ popc($src$$Register, $dst$$Register); 10409 %} 10410 ins_pipe(ialu_reg); 10411 %} 10412 10413 10414 // ============================================================================ 10415 //------------Bytes reverse-------------------------------------------------- 10416 10417 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 10418 match(Set dst (ReverseBytesI src)); 10419 10420 // Op cost is artificially doubled to make sure that load or store 10421 // instructions are preferred over this one which requires a spill 10422 // onto a stack slot. 10423 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10424 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10425 10426 ins_encode %{ 10427 __ set($src$$disp + STACK_BIAS, O7); 10428 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10429 %} 10430 ins_pipe( iload_mem ); 10431 %} 10432 10433 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 10434 match(Set dst (ReverseBytesL src)); 10435 10436 // Op cost is artificially doubled to make sure that load or store 10437 // instructions are preferred over this one which requires a spill 10438 // onto a stack slot. 10439 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10440 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10441 10442 ins_encode %{ 10443 __ set($src$$disp + STACK_BIAS, O7); 10444 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10445 %} 10446 ins_pipe( iload_mem ); 10447 %} 10448 10449 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 10450 match(Set dst (ReverseBytesUS src)); 10451 10452 // Op cost is artificially doubled to make sure that load or store 10453 // instructions are preferred over this one which requires a spill 10454 // onto a stack slot. 10455 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10456 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 10457 10458 ins_encode %{ 10459 // the value was spilled as an int so bias the load 10460 __ set($src$$disp + STACK_BIAS + 2, O7); 10461 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10462 %} 10463 ins_pipe( iload_mem ); 10464 %} 10465 10466 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 10467 match(Set dst (ReverseBytesS src)); 10468 10469 // Op cost is artificially doubled to make sure that load or store 10470 // instructions are preferred over this one which requires a spill 10471 // onto a stack slot. 10472 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10473 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 10474 10475 ins_encode %{ 10476 // the value was spilled as an int so bias the load 10477 __ set($src$$disp + STACK_BIAS + 2, O7); 10478 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10479 %} 10480 ins_pipe( iload_mem ); 10481 %} 10482 10483 // Load Integer reversed byte order 10484 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 10485 match(Set dst (ReverseBytesI (LoadI src))); 10486 10487 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10488 size(4); 10489 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10490 10491 ins_encode %{ 10492 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10493 %} 10494 ins_pipe(iload_mem); 10495 %} 10496 10497 // Load Long - aligned and reversed 10498 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 10499 match(Set dst (ReverseBytesL (LoadL src))); 10500 10501 ins_cost(MEMORY_REF_COST); 10502 size(4); 10503 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10504 10505 ins_encode %{ 10506 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10507 %} 10508 ins_pipe(iload_mem); 10509 %} 10510 10511 // Load unsigned short / char reversed byte order 10512 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 10513 match(Set dst (ReverseBytesUS (LoadUS src))); 10514 10515 ins_cost(MEMORY_REF_COST); 10516 size(4); 10517 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 10518 10519 ins_encode %{ 10520 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10521 %} 10522 ins_pipe(iload_mem); 10523 %} 10524 10525 // Load short reversed byte order 10526 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 10527 match(Set dst (ReverseBytesS (LoadS src))); 10528 10529 ins_cost(MEMORY_REF_COST); 10530 size(4); 10531 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 10532 10533 ins_encode %{ 10534 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10535 %} 10536 ins_pipe(iload_mem); 10537 %} 10538 10539 // Store Integer reversed byte order 10540 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 10541 match(Set dst (StoreI dst (ReverseBytesI src))); 10542 10543 ins_cost(MEMORY_REF_COST); 10544 size(4); 10545 format %{ "STWA $src, $dst\t!asi=primary_little" %} 10546 10547 ins_encode %{ 10548 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10549 %} 10550 ins_pipe(istore_mem_reg); 10551 %} 10552 10553 // Store Long reversed byte order 10554 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 10555 match(Set dst (StoreL dst (ReverseBytesL src))); 10556 10557 ins_cost(MEMORY_REF_COST); 10558 size(4); 10559 format %{ "STXA $src, $dst\t!asi=primary_little" %} 10560 10561 ins_encode %{ 10562 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10563 %} 10564 ins_pipe(istore_mem_reg); 10565 %} 10566 10567 // Store unsighed short/char reversed byte order 10568 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 10569 match(Set dst (StoreC dst (ReverseBytesUS src))); 10570 10571 ins_cost(MEMORY_REF_COST); 10572 size(4); 10573 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10574 10575 ins_encode %{ 10576 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10577 %} 10578 ins_pipe(istore_mem_reg); 10579 %} 10580 10581 // Store short reversed byte order 10582 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 10583 match(Set dst (StoreC dst (ReverseBytesS src))); 10584 10585 ins_cost(MEMORY_REF_COST); 10586 size(4); 10587 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10588 10589 ins_encode %{ 10590 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10591 %} 10592 ins_pipe(istore_mem_reg); 10593 %} 10594 10595 // ====================VECTOR INSTRUCTIONS===================================== 10596 10597 // Load Aligned Packed values into a Double Register 10598 instruct loadV8(regD dst, memory mem) %{ 10599 predicate(n->as_LoadVector()->memory_size() == 8); 10600 match(Set dst (LoadVector mem)); 10601 ins_cost(MEMORY_REF_COST); 10602 size(4); 10603 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} 10604 ins_encode %{ 10605 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); 10606 %} 10607 ins_pipe(floadD_mem); 10608 %} 10609 10610 // Store Vector in Double register to memory 10611 instruct storeV8(memory mem, regD src) %{ 10612 predicate(n->as_StoreVector()->memory_size() == 8); 10613 match(Set mem (StoreVector mem src)); 10614 ins_cost(MEMORY_REF_COST); 10615 size(4); 10616 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} 10617 ins_encode %{ 10618 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); 10619 %} 10620 ins_pipe(fstoreD_mem_reg); 10621 %} 10622 10623 // Store Zero into vector in memory 10624 instruct storeV8B_zero(memory mem, immI0 zero) %{ 10625 predicate(n->as_StoreVector()->memory_size() == 8); 10626 match(Set mem (StoreVector mem (ReplicateB zero))); 10627 ins_cost(MEMORY_REF_COST); 10628 size(4); 10629 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} 10630 ins_encode %{ 10631 __ stx(G0, $mem$$Address); 10632 %} 10633 ins_pipe(fstoreD_mem_zero); 10634 %} 10635 10636 instruct storeV4S_zero(memory mem, immI0 zero) %{ 10637 predicate(n->as_StoreVector()->memory_size() == 8); 10638 match(Set mem (StoreVector mem (ReplicateS zero))); 10639 ins_cost(MEMORY_REF_COST); 10640 size(4); 10641 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} 10642 ins_encode %{ 10643 __ stx(G0, $mem$$Address); 10644 %} 10645 ins_pipe(fstoreD_mem_zero); 10646 %} 10647 10648 instruct storeV2I_zero(memory mem, immI0 zero) %{ 10649 predicate(n->as_StoreVector()->memory_size() == 8); 10650 match(Set mem (StoreVector mem (ReplicateI zero))); 10651 ins_cost(MEMORY_REF_COST); 10652 size(4); 10653 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} 10654 ins_encode %{ 10655 __ stx(G0, $mem$$Address); 10656 %} 10657 ins_pipe(fstoreD_mem_zero); 10658 %} 10659 10660 instruct storeV2F_zero(memory mem, immF0 zero) %{ 10661 predicate(n->as_StoreVector()->memory_size() == 8); 10662 match(Set mem (StoreVector mem (ReplicateF zero))); 10663 ins_cost(MEMORY_REF_COST); 10664 size(4); 10665 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} 10666 ins_encode %{ 10667 __ stx(G0, $mem$$Address); 10668 %} 10669 ins_pipe(fstoreD_mem_zero); 10670 %} 10671 10672 // Replicate scalar to packed byte values into Double register 10673 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10674 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); 10675 match(Set dst (ReplicateB src)); 10676 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10677 format %{ "SLLX $src,56,$tmp\n\t" 10678 "SRLX $tmp, 8,$tmp2\n\t" 10679 "OR $tmp,$tmp2,$tmp\n\t" 10680 "SRLX $tmp,16,$tmp2\n\t" 10681 "OR $tmp,$tmp2,$tmp\n\t" 10682 "SRLX $tmp,32,$tmp2\n\t" 10683 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10684 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10685 ins_encode %{ 10686 Register Rsrc = $src$$Register; 10687 Register Rtmp = $tmp$$Register; 10688 Register Rtmp2 = $tmp2$$Register; 10689 __ sllx(Rsrc, 56, Rtmp); 10690 __ srlx(Rtmp, 8, Rtmp2); 10691 __ or3 (Rtmp, Rtmp2, Rtmp); 10692 __ srlx(Rtmp, 16, Rtmp2); 10693 __ or3 (Rtmp, Rtmp2, Rtmp); 10694 __ srlx(Rtmp, 32, Rtmp2); 10695 __ or3 (Rtmp, Rtmp2, Rtmp); 10696 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10697 %} 10698 ins_pipe(ialu_reg); 10699 %} 10700 10701 // Replicate scalar to packed byte values into Double stack 10702 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10703 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); 10704 match(Set dst (ReplicateB src)); 10705 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10706 format %{ "SLLX $src,56,$tmp\n\t" 10707 "SRLX $tmp, 8,$tmp2\n\t" 10708 "OR $tmp,$tmp2,$tmp\n\t" 10709 "SRLX $tmp,16,$tmp2\n\t" 10710 "OR $tmp,$tmp2,$tmp\n\t" 10711 "SRLX $tmp,32,$tmp2\n\t" 10712 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10713 "STX $tmp,$dst\t! regL to stkD" %} 10714 ins_encode %{ 10715 Register Rsrc = $src$$Register; 10716 Register Rtmp = $tmp$$Register; 10717 Register Rtmp2 = $tmp2$$Register; 10718 __ sllx(Rsrc, 56, Rtmp); 10719 __ srlx(Rtmp, 8, Rtmp2); 10720 __ or3 (Rtmp, Rtmp2, Rtmp); 10721 __ srlx(Rtmp, 16, Rtmp2); 10722 __ or3 (Rtmp, Rtmp2, Rtmp); 10723 __ srlx(Rtmp, 32, Rtmp2); 10724 __ or3 (Rtmp, Rtmp2, Rtmp); 10725 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10726 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10727 %} 10728 ins_pipe(ialu_reg); 10729 %} 10730 10731 // Replicate scalar constant to packed byte values in Double register 10732 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ 10733 predicate(n->as_Vector()->length() == 8); 10734 match(Set dst (ReplicateB con)); 10735 effect(KILL tmp); 10736 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} 10737 ins_encode %{ 10738 // XXX This is a quick fix for 6833573. 10739 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); 10740 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); 10741 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10742 %} 10743 ins_pipe(loadConFD); 10744 %} 10745 10746 // Replicate scalar to packed char/short values into Double register 10747 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10748 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); 10749 match(Set dst (ReplicateS src)); 10750 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10751 format %{ "SLLX $src,48,$tmp\n\t" 10752 "SRLX $tmp,16,$tmp2\n\t" 10753 "OR $tmp,$tmp2,$tmp\n\t" 10754 "SRLX $tmp,32,$tmp2\n\t" 10755 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10756 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10757 ins_encode %{ 10758 Register Rsrc = $src$$Register; 10759 Register Rtmp = $tmp$$Register; 10760 Register Rtmp2 = $tmp2$$Register; 10761 __ sllx(Rsrc, 48, Rtmp); 10762 __ srlx(Rtmp, 16, Rtmp2); 10763 __ or3 (Rtmp, Rtmp2, Rtmp); 10764 __ srlx(Rtmp, 32, Rtmp2); 10765 __ or3 (Rtmp, Rtmp2, Rtmp); 10766 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10767 %} 10768 ins_pipe(ialu_reg); 10769 %} 10770 10771 // Replicate scalar to packed char/short values into Double stack 10772 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10773 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); 10774 match(Set dst (ReplicateS src)); 10775 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10776 format %{ "SLLX $src,48,$tmp\n\t" 10777 "SRLX $tmp,16,$tmp2\n\t" 10778 "OR $tmp,$tmp2,$tmp\n\t" 10779 "SRLX $tmp,32,$tmp2\n\t" 10780 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10781 "STX $tmp,$dst\t! regL to stkD" %} 10782 ins_encode %{ 10783 Register Rsrc = $src$$Register; 10784 Register Rtmp = $tmp$$Register; 10785 Register Rtmp2 = $tmp2$$Register; 10786 __ sllx(Rsrc, 48, Rtmp); 10787 __ srlx(Rtmp, 16, Rtmp2); 10788 __ or3 (Rtmp, Rtmp2, Rtmp); 10789 __ srlx(Rtmp, 32, Rtmp2); 10790 __ or3 (Rtmp, Rtmp2, Rtmp); 10791 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10792 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10793 %} 10794 ins_pipe(ialu_reg); 10795 %} 10796 10797 // Replicate scalar constant to packed char/short values in Double register 10798 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ 10799 predicate(n->as_Vector()->length() == 4); 10800 match(Set dst (ReplicateS con)); 10801 effect(KILL tmp); 10802 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} 10803 ins_encode %{ 10804 // XXX This is a quick fix for 6833573. 10805 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 10806 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); 10807 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10808 %} 10809 ins_pipe(loadConFD); 10810 %} 10811 10812 // Replicate scalar to packed int values into Double register 10813 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10814 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); 10815 match(Set dst (ReplicateI src)); 10816 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10817 format %{ "SLLX $src,32,$tmp\n\t" 10818 "SRLX $tmp,32,$tmp2\n\t" 10819 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10820 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10821 ins_encode %{ 10822 Register Rsrc = $src$$Register; 10823 Register Rtmp = $tmp$$Register; 10824 Register Rtmp2 = $tmp2$$Register; 10825 __ sllx(Rsrc, 32, Rtmp); 10826 __ srlx(Rtmp, 32, Rtmp2); 10827 __ or3 (Rtmp, Rtmp2, Rtmp); 10828 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10829 %} 10830 ins_pipe(ialu_reg); 10831 %} 10832 10833 // Replicate scalar to packed int values into Double stack 10834 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10835 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); 10836 match(Set dst (ReplicateI src)); 10837 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10838 format %{ "SLLX $src,32,$tmp\n\t" 10839 "SRLX $tmp,32,$tmp2\n\t" 10840 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10841 "STX $tmp,$dst\t! regL to stkD" %} 10842 ins_encode %{ 10843 Register Rsrc = $src$$Register; 10844 Register Rtmp = $tmp$$Register; 10845 Register Rtmp2 = $tmp2$$Register; 10846 __ sllx(Rsrc, 32, Rtmp); 10847 __ srlx(Rtmp, 32, Rtmp2); 10848 __ or3 (Rtmp, Rtmp2, Rtmp); 10849 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10850 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10851 %} 10852 ins_pipe(ialu_reg); 10853 %} 10854 10855 // Replicate scalar zero constant to packed int values in Double register 10856 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ 10857 predicate(n->as_Vector()->length() == 2); 10858 match(Set dst (ReplicateI con)); 10859 effect(KILL tmp); 10860 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} 10861 ins_encode %{ 10862 // XXX This is a quick fix for 6833573. 10863 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); 10864 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); 10865 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10866 %} 10867 ins_pipe(loadConFD); 10868 %} 10869 10870 // Replicate scalar to packed float values into Double stack 10871 instruct Repl2F_stk(stackSlotD dst, regF src) %{ 10872 predicate(n->as_Vector()->length() == 2); 10873 match(Set dst (ReplicateF src)); 10874 ins_cost(MEMORY_REF_COST*2); 10875 format %{ "STF $src,$dst.hi\t! packed2F\n\t" 10876 "STF $src,$dst.lo" %} 10877 opcode(Assembler::stf_op3); 10878 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); 10879 ins_pipe(fstoreF_stk_reg); 10880 %} 10881 10882 // Replicate scalar zero constant to packed float values in Double register 10883 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ 10884 predicate(n->as_Vector()->length() == 2); 10885 match(Set dst (ReplicateF con)); 10886 effect(KILL tmp); 10887 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} 10888 ins_encode %{ 10889 // XXX This is a quick fix for 6833573. 10890 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); 10891 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); 10892 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10893 %} 10894 ins_pipe(loadConFD); 10895 %} 10896 10897 //----------PEEPHOLE RULES----------------------------------------------------- 10898 // These must follow all instruction definitions as they use the names 10899 // defined in the instructions definitions. 10900 // 10901 // peepmatch ( root_instr_name [preceding_instruction]* ); 10902 // 10903 // peepconstraint %{ 10904 // (instruction_number.operand_name relational_op instruction_number.operand_name 10905 // [, ...] ); 10906 // // instruction numbers are zero-based using left to right order in peepmatch 10907 // 10908 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 10909 // // provide an instruction_number.operand_name for each operand that appears 10910 // // in the replacement instruction's match rule 10911 // 10912 // ---------VM FLAGS--------------------------------------------------------- 10913 // 10914 // All peephole optimizations can be turned off using -XX:-OptoPeephole 10915 // 10916 // Each peephole rule is given an identifying number starting with zero and 10917 // increasing by one in the order seen by the parser. An individual peephole 10918 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10919 // on the command-line. 10920 // 10921 // ---------CURRENT LIMITATIONS---------------------------------------------- 10922 // 10923 // Only match adjacent instructions in same basic block 10924 // Only equality constraints 10925 // Only constraints between operands, not (0.dest_reg == EAX_enc) 10926 // Only one replacement instruction 10927 // 10928 // ---------EXAMPLE---------------------------------------------------------- 10929 // 10930 // // pertinent parts of existing instructions in architecture description 10931 // instruct movI(eRegI dst, eRegI src) %{ 10932 // match(Set dst (CopyI src)); 10933 // %} 10934 // 10935 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10936 // match(Set dst (AddI dst src)); 10937 // effect(KILL cr); 10938 // %} 10939 // 10940 // // Change (inc mov) to lea 10941 // peephole %{ 10942 // // increment preceeded by register-register move 10943 // peepmatch ( incI_eReg movI ); 10944 // // require that the destination register of the increment 10945 // // match the destination register of the move 10946 // peepconstraint ( 0.dst == 1.dst ); 10947 // // construct a replacement instruction that sets 10948 // // the destination to ( move's source register + one ) 10949 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 10950 // %} 10951 // 10952 10953 // // Change load of spilled value to only a spill 10954 // instruct storeI(memory mem, eRegI src) %{ 10955 // match(Set mem (StoreI mem src)); 10956 // %} 10957 // 10958 // instruct loadI(eRegI dst, memory mem) %{ 10959 // match(Set dst (LoadI mem)); 10960 // %} 10961 // 10962 // peephole %{ 10963 // peepmatch ( loadI storeI ); 10964 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 10965 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 10966 // %} 10967 10968 //----------SMARTSPILL RULES--------------------------------------------------- 10969 // These must follow all instruction definitions as they use the names 10970 // defined in the instructions definitions. 10971 // 10972 // SPARC will probably not have any of these rules due to RISC instruction set. 10973 10974 //----------PIPELINE----------------------------------------------------------- 10975 // Rules which define the behavior of the target architectures pipeline.