1 //
2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 extern bool use_block_zeroing(Node* count);
464
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
470
471 %}
472
473 source %{
474 #define __ _masm.
475
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
478
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
482
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
501
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
506
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
525
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
531
532 // ****************************************************************************
533
534 // REQUIRED FUNCTIONALITY
535
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
540
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
547
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedClassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
563 } else {
564 klass_load_size = 1*BytesPerInstWord;
565 }
566 if (Assembler::is_simm13(v_off)) {
567 return klass_load_size +
568 (2*BytesPerInstWord + // ld_ptr, ld_ptr
569 NativeCall::instruction_size); // call; delay slot
570 } else {
571 return klass_load_size +
572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
573 NativeCall::instruction_size); // call; delay slot
574 }
575 }
576 }
577
578 int MachCallRuntimeNode::ret_addr_offset() {
579 #ifdef _LP64
580 if (MacroAssembler::is_far_target(entry_point())) {
581 return NativeFarCall::instruction_size;
582 } else {
583 return NativeCall::instruction_size;
584 }
585 #else
586 return NativeCall::instruction_size; // call; delay slot
587 #endif
588 }
589
590 // Indicate if the safepoint node needs the polling page as an input.
591 // Since Sparc does not have absolute addressing, it does.
592 bool SafePointNode::needs_polling_address_input() {
593 return true;
594 }
595
596 // emit an interrupt that is caught by the debugger (for debugging compiler)
597 void emit_break(CodeBuffer &cbuf) {
598 MacroAssembler _masm(&cbuf);
599 __ breakpoint_trap();
600 }
601
602 #ifndef PRODUCT
603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
604 st->print("TA");
605 }
606 #endif
607
608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
609 emit_break(cbuf);
610 }
611
612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
613 return MachNode::size(ra_);
614 }
615
616 // Traceable jump
617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
618 MacroAssembler _masm(&cbuf);
619 Register rdest = reg_to_register_object(jump_target);
620 __ JMP(rdest, 0);
621 __ delayed()->nop();
622 }
623
624 // Traceable jump and set exception pc
625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
626 MacroAssembler _masm(&cbuf);
627 Register rdest = reg_to_register_object(jump_target);
628 __ JMP(rdest, 0);
629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
630 }
631
632 void emit_nop(CodeBuffer &cbuf) {
633 MacroAssembler _masm(&cbuf);
634 __ nop();
635 }
636
637 void emit_illtrap(CodeBuffer &cbuf) {
638 MacroAssembler _masm(&cbuf);
639 __ illtrap(0);
640 }
641
642
643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
644 assert(n->rule() != loadUB_rule, "");
645
646 intptr_t offset = 0;
647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
648 const Node* addr = n->get_base_and_disp(offset, adr_type);
649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
650 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 atype = atype->add_offset(offset);
653 assert(disp32 == offset, "wrong disp32");
654 return atype->_offset;
655 }
656
657
658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
659 assert(n->rule() != loadUB_rule, "");
660
661 intptr_t offset = 0;
662 Node* addr = n->in(2);
663 assert(addr->bottom_type()->isa_oopptr() == atype, "");
664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
665 Node* a = addr->in(2/*AddPNode::Address*/);
666 Node* o = addr->in(3/*AddPNode::Offset*/);
667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
668 atype = a->bottom_type()->is_ptr()->add_offset(offset);
669 assert(atype->isa_oop_ptr(), "still an oop");
670 }
671 offset = atype->is_ptr()->_offset;
672 if (offset != Type::OffsetBot) offset += disp32;
673 return offset;
674 }
675
676 static inline jdouble replicate_immI(int con, int count, int width) {
677 // Load a constant replicated "count" times with width "width"
678 assert(count*width == 8 && width <= 4, "sanity");
679 int bit_width = width * 8;
680 jlong val = con;
681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
682 for (int i = 0; i < count - 1; i++) {
683 val |= (val << bit_width);
684 }
685 jdouble dval = *((jdouble*) &val); // coerce to double type
686 return dval;
687 }
688
689 static inline jdouble replicate_immF(float con) {
690 // Replicate float con 2 times and pack into vector.
691 int val = *((int*)&con);
692 jlong lval = val;
693 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
694 jdouble dval = *((jdouble*) &lval); // coerce to double type
695 return dval;
696 }
697
698 // Standard Sparc opcode form2 field breakdown
699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
700 f0 &= (1<<19)-1; // Mask displacement to 19 bits
701 int op = (f30 << 30) |
702 (f29 << 29) |
703 (f25 << 25) |
704 (f22 << 22) |
705 (f20 << 20) |
706 (f19 << 19) |
707 (f0 << 0);
708 cbuf.insts()->emit_int32(op);
709 }
710
711 // Standard Sparc opcode form2 field breakdown
712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
713 f0 >>= 10; // Drop 10 bits
714 f0 &= (1<<22)-1; // Mask displacement to 22 bits
715 int op = (f30 << 30) |
716 (f25 << 25) |
717 (f22 << 22) |
718 (f0 << 0);
719 cbuf.insts()->emit_int32(op);
720 }
721
722 // Standard Sparc opcode form3 field breakdown
723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
724 int op = (f30 << 30) |
725 (f25 << 25) |
726 (f19 << 19) |
727 (f14 << 14) |
728 (f5 << 5) |
729 (f0 << 0);
730 cbuf.insts()->emit_int32(op);
731 }
732
733 // Standard Sparc opcode form3 field breakdown
734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
735 simm13 &= (1<<13)-1; // Mask to 13 bits
736 int op = (f30 << 30) |
737 (f25 << 25) |
738 (f19 << 19) |
739 (f14 << 14) |
740 (1 << 13) | // bit to indicate immediate-mode
741 (simm13<<0);
742 cbuf.insts()->emit_int32(op);
743 }
744
745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
746 simm10 &= (1<<10)-1; // Mask to 10 bits
747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
748 }
749
750 #ifdef ASSERT
751 // Helper function for VerifyOops in emit_form3_mem_reg
752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
753 warning("VerifyOops encountered unexpected instruction:");
754 n->dump(2);
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
756 }
757 #endif
758
759
760 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
761 int src1_enc, int disp32, int src2_enc, int dst_enc) {
762
763 #ifdef ASSERT
764 // The following code implements the +VerifyOops feature.
765 // It verifies oop values which are loaded into or stored out of
766 // the current method activation. +VerifyOops complements techniques
767 // like ScavengeALot, because it eagerly inspects oops in transit,
768 // as they enter or leave the stack, as opposed to ScavengeALot,
769 // which inspects oops "at rest", in the stack or heap, at safepoints.
770 // For this reason, +VerifyOops can sometimes detect bugs very close
771 // to their point of creation. It can also serve as a cross-check
772 // on the validity of oop maps, when used toegether with ScavengeALot.
773
774 // It would be good to verify oops at other points, especially
775 // when an oop is used as a base pointer for a load or store.
776 // This is presently difficult, because it is hard to know when
777 // a base address is biased or not. (If we had such information,
778 // it would be easy and useful to make a two-argument version of
779 // verify_oop which unbiases the base, and performs verification.)
780
781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
782 bool is_verified_oop_base = false;
783 bool is_verified_oop_load = false;
784 bool is_verified_oop_store = false;
785 int tmp_enc = -1;
786 if (VerifyOops && src1_enc != R_SP_enc) {
787 // classify the op, mainly for an assert check
788 int st_op = 0, ld_op = 0;
789 switch (primary) {
790 case Assembler::stb_op3: st_op = Op_StoreB; break;
791 case Assembler::sth_op3: st_op = Op_StoreC; break;
792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
793 case Assembler::stw_op3: st_op = Op_StoreI; break;
794 case Assembler::std_op3: st_op = Op_StoreL; break;
795 case Assembler::stf_op3: st_op = Op_StoreF; break;
796 case Assembler::stdf_op3: st_op = Op_StoreD; break;
797
798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
802 case Assembler::ldx_op3: // may become LoadP or stay LoadI
803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
804 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
805 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
806 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
807 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
809
810 default: ShouldNotReachHere();
811 }
812 if (tertiary == REGP_OP) {
813 if (st_op == Op_StoreI) st_op = Op_StoreP;
814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
815 else ShouldNotReachHere();
816 if (st_op) {
817 // a store
818 // inputs are (0:control, 1:memory, 2:address, 3:value)
819 Node* n2 = n->in(3);
820 if (n2 != NULL) {
821 const Type* t = n2->bottom_type();
822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 } else {
825 // a load
826 const Type* t = n->bottom_type();
827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
828 }
829 }
830
831 if (ld_op) {
832 // a Load
833 // inputs are (0:control, 1:memory, 2:address)
834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
849 !(n->rule() == loadUB_rule)) {
850 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
851 }
852 } else if (st_op) {
853 // a Store
854 // inputs are (0:control, 1:memory, 2:address, 3:value)
855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
862 verify_oops_warning(n, n->ideal_Opcode(), st_op);
863 }
864 }
865
866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
867 Node* addr = n->in(2);
868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
870 if (atype != NULL) {
871 intptr_t offset = get_offset_from_base(n, atype, disp32);
872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
873 if (offset != offset_2) {
874 get_offset_from_base(n, atype, disp32);
875 get_offset_from_base_2(n, atype, disp32);
876 }
877 assert(offset == offset_2, "different offsets");
878 if (offset == disp32) {
879 // we now know that src1 is a true oop pointer
880 is_verified_oop_base = true;
881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
882 if( primary == Assembler::ldd_op3 ) {
883 is_verified_oop_base = false; // Cannot 'ldd' into O7
884 } else {
885 tmp_enc = dst_enc;
886 dst_enc = R_O7_enc; // Load into O7; preserve source oop
887 assert(src1_enc != dst_enc, "");
888 }
889 }
890 }
891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
892 || offset == oopDesc::mark_offset_in_bytes())) {
893 // loading the mark should not be allowed either, but
894 // we don't check this since it conflicts with InlineObjectHash
895 // usage of LoadINode to get the mark. We could keep the
896 // check if we create a new LoadMarkNode
897 // but do not verify the object before its header is initialized
898 ShouldNotReachHere();
899 }
900 }
901 }
902 }
903 }
904 #endif
905
906 uint instr;
907 instr = (Assembler::ldst_op << 30)
908 | (dst_enc << 25)
909 | (primary << 19)
910 | (src1_enc << 14);
911
912 uint index = src2_enc;
913 int disp = disp32;
914
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
916 disp += STACK_BIAS;
917 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
918 if (!Assembler::is_simm13(disp)) {
919 ra->C->record_method_not_compilable("unable to handle large constant offsets");
920 return;
921 }
922 }
923
924 // We should have a compiler bailout here rather than a guarantee.
925 // Better yet would be some mechanism to handle variable-size matches correctly.
926 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
927
928 if( disp == 0 ) {
929 // use reg-reg form
930 // bit 13 is already zero
931 instr |= index;
932 } else {
933 // use reg-imm form
934 instr |= 0x00002000; // set bit 13 to one
935 instr |= disp & 0x1FFF;
936 }
937
938 cbuf.insts()->emit_int32(instr);
939
940 #ifdef ASSERT
941 {
942 MacroAssembler _masm(&cbuf);
943 if (is_verified_oop_base) {
944 __ verify_oop(reg_to_register_object(src1_enc));
945 }
946 if (is_verified_oop_store) {
947 __ verify_oop(reg_to_register_object(dst_enc));
948 }
949 if (tmp_enc != -1) {
950 __ mov(O7, reg_to_register_object(tmp_enc));
951 }
952 if (is_verified_oop_load) {
953 __ verify_oop(reg_to_register_object(dst_enc));
954 }
955 }
956 #endif
957 }
958
959 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
960 // The method which records debug information at every safepoint
961 // expects the call to be the first instruction in the snippet as
962 // it creates a PcDesc structure which tracks the offset of a call
963 // from the start of the codeBlob. This offset is computed as
964 // code_end() - code_begin() of the code which has been emitted
965 // so far.
966 // In this particular case we have skirted around the problem by
967 // putting the "mov" instruction in the delay slot but the problem
968 // may bite us again at some other point and a cleaner/generic
969 // solution using relocations would be needed.
970 MacroAssembler _masm(&cbuf);
971 __ set_inst_mark();
972
973 // We flush the current window just so that there is a valid stack copy
974 // the fact that the current window becomes active again instantly is
975 // not a problem there is nothing live in it.
976
977 #ifdef ASSERT
978 int startpos = __ offset();
979 #endif /* ASSERT */
980
981 __ call((address)entry_point, rtype);
982
983 if (preserve_g2) __ delayed()->mov(G2, L7);
984 else __ delayed()->nop();
985
986 if (preserve_g2) __ mov(L7, G2);
987
988 #ifdef ASSERT
989 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
990 #ifdef _LP64
991 // Trash argument dump slots.
992 __ set(0xb0b8ac0db0b8ac0d, G1);
993 __ mov(G1, G5);
994 __ stx(G1, SP, STACK_BIAS + 0x80);
995 __ stx(G1, SP, STACK_BIAS + 0x88);
996 __ stx(G1, SP, STACK_BIAS + 0x90);
997 __ stx(G1, SP, STACK_BIAS + 0x98);
998 __ stx(G1, SP, STACK_BIAS + 0xA0);
999 __ stx(G1, SP, STACK_BIAS + 0xA8);
1000 #else // _LP64
1001 // this is also a native call, so smash the first 7 stack locations,
1002 // and the various registers
1003
1004 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1005 // while [SP+0x44..0x58] are the argument dump slots.
1006 __ set((intptr_t)0xbaadf00d, G1);
1007 __ mov(G1, G5);
1008 __ sllx(G1, 32, G1);
1009 __ or3(G1, G5, G1);
1010 __ mov(G1, G5);
1011 __ stx(G1, SP, 0x40);
1012 __ stx(G1, SP, 0x48);
1013 __ stx(G1, SP, 0x50);
1014 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1015 #endif // _LP64
1016 }
1017 #endif /*ASSERT*/
1018 }
1019
1020 //=============================================================================
1021 // REQUIRED FUNCTIONALITY for encoding
1022 void emit_lo(CodeBuffer &cbuf, int val) { }
1023 void emit_hi(CodeBuffer &cbuf, int val) { }
1024
1025
1026 //=============================================================================
1027 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1028
1029 int Compile::ConstantTable::calculate_table_base_offset() const {
1030 if (UseRDPCForConstantTableBase) {
1031 // The table base offset might be less but then it fits into
1032 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1033 return Assembler::min_simm13();
1034 } else {
1035 int offset = -(size() / 2);
1036 if (!Assembler::is_simm13(offset)) {
1037 offset = Assembler::min_simm13();
1038 }
1039 return offset;
1040 }
1041 }
1042
1043 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1044 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1045 ShouldNotReachHere();
1046 }
1047
1048 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1049 Compile* C = ra_->C;
1050 Compile::ConstantTable& constant_table = C->constant_table();
1051 MacroAssembler _masm(&cbuf);
1052
1053 Register r = as_Register(ra_->get_encode(this));
1054 CodeSection* consts_section = __ code()->consts();
1055 int consts_size = consts_section->align_at_start(consts_section->size());
1056 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1057
1058 if (UseRDPCForConstantTableBase) {
1059 // For the following RDPC logic to work correctly the consts
1060 // section must be allocated right before the insts section. This
1061 // assert checks for that. The layout and the SECT_* constants
1062 // are defined in src/share/vm/asm/codeBuffer.hpp.
1063 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1064 int insts_offset = __ offset();
1065
1066 // Layout:
1067 //
1068 // |----------- consts section ------------|----------- insts section -----------...
1069 // |------ constant table -----|- padding -|------------------x----
1070 // \ current PC (RDPC instruction)
1071 // |<------------- consts_size ----------->|<- insts_offset ->|
1072 // \ table base
1073 // The table base offset is later added to the load displacement
1074 // so it has to be negative.
1075 int table_base_offset = -(consts_size + insts_offset);
1076 int disp;
1077
1078 // If the displacement from the current PC to the constant table
1079 // base fits into simm13 we set the constant table base to the
1080 // current PC.
1081 if (Assembler::is_simm13(table_base_offset)) {
1082 constant_table.set_table_base_offset(table_base_offset);
1083 disp = 0;
1084 } else {
1085 // Otherwise we set the constant table base offset to the
1086 // maximum negative displacement of load instructions to keep
1087 // the disp as small as possible:
1088 //
1089 // |<------------- consts_size ----------->|<- insts_offset ->|
1090 // |<--------- min_simm13 --------->|<-------- disp --------->|
1091 // \ table base
1092 table_base_offset = Assembler::min_simm13();
1093 constant_table.set_table_base_offset(table_base_offset);
1094 disp = (consts_size + insts_offset) + table_base_offset;
1095 }
1096
1097 __ rdpc(r);
1098
1099 if (disp != 0) {
1100 assert(r != O7, "need temporary");
1101 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1102 }
1103 }
1104 else {
1105 // Materialize the constant table base.
1106 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1107 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1108 AddressLiteral base(baseaddr, rspec);
1109 __ set(base, r);
1110 }
1111 }
1112
1113 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1114 if (UseRDPCForConstantTableBase) {
1115 // This is really the worst case but generally it's only 1 instruction.
1116 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1117 } else {
1118 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1119 }
1120 }
1121
1122 #ifndef PRODUCT
1123 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1124 char reg[128];
1125 ra_->dump_register(this, reg);
1126 if (UseRDPCForConstantTableBase) {
1127 st->print("RDPC %s\t! constant table base", reg);
1128 } else {
1129 st->print("SET &constanttable,%s\t! constant table base", reg);
1130 }
1131 }
1132 #endif
1133
1134
1135 //=============================================================================
1136
1137 #ifndef PRODUCT
1138 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1139 Compile* C = ra_->C;
1140
1141 for (int i = 0; i < OptoPrologueNops; i++) {
1142 st->print_cr("NOP"); st->print("\t");
1143 }
1144
1145 if( VerifyThread ) {
1146 st->print_cr("Verify_Thread"); st->print("\t");
1147 }
1148
1149 size_t framesize = C->frame_size_in_bytes();
1150 int bangsize = C->bang_size_in_bytes();
1151
1152 // Calls to C2R adapters often do not accept exceptional returns.
1153 // We require that their callers must bang for them. But be careful, because
1154 // some VM calls (such as call site linkage) can use several kilobytes of
1155 // stack. But the stack safety zone should account for that.
1156 // See bugs 4446381, 4468289, 4497237.
1157 if (C->need_stack_bang(bangsize)) {
1158 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1159 }
1160
1161 if (Assembler::is_simm13(-framesize)) {
1162 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1163 } else {
1164 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1165 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1166 st->print ("SAVE R_SP,R_G3,R_SP");
1167 }
1168
1169 }
1170 #endif
1171
1172 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1173 Compile* C = ra_->C;
1174 MacroAssembler _masm(&cbuf);
1175
1176 for (int i = 0; i < OptoPrologueNops; i++) {
1177 __ nop();
1178 }
1179
1180 __ verify_thread();
1181
1182 size_t framesize = C->frame_size_in_bytes();
1183 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1184 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1185 int bangsize = C->bang_size_in_bytes();
1186
1187 // Calls to C2R adapters often do not accept exceptional returns.
1188 // We require that their callers must bang for them. But be careful, because
1189 // some VM calls (such as call site linkage) can use several kilobytes of
1190 // stack. But the stack safety zone should account for that.
1191 // See bugs 4446381, 4468289, 4497237.
1192 if (C->need_stack_bang(bangsize)) {
1193 __ generate_stack_overflow_check(bangsize);
1194 }
1195
1196 if (Assembler::is_simm13(-framesize)) {
1197 __ save(SP, -framesize, SP);
1198 } else {
1199 __ sethi(-framesize & ~0x3ff, G3);
1200 __ add(G3, -framesize & 0x3ff, G3);
1201 __ save(SP, G3, SP);
1202 }
1203 C->set_frame_complete( __ offset() );
1204
1205 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1206 // NOTE: We set the table base offset here because users might be
1207 // emitted before MachConstantBaseNode.
1208 Compile::ConstantTable& constant_table = C->constant_table();
1209 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1210 }
1211 }
1212
1213 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1214 return MachNode::size(ra_);
1215 }
1216
1217 int MachPrologNode::reloc() const {
1218 return 10; // a large enough number
1219 }
1220
1221 //=============================================================================
1222 #ifndef PRODUCT
1223 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1224 Compile* C = ra_->C;
1225
1226 if( do_polling() && ra_->C->is_method_compilation() ) {
1227 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1228 #ifdef _LP64
1229 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1230 #else
1231 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1232 #endif
1233 }
1234
1235 if( do_polling() )
1236 st->print("RET\n\t");
1237
1238 st->print("RESTORE");
1239 }
1240 #endif
1241
1242 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1243 MacroAssembler _masm(&cbuf);
1244 Compile* C = ra_->C;
1245
1246 __ verify_thread();
1247
1248 // If this does safepoint polling, then do it here
1249 if( do_polling() && ra_->C->is_method_compilation() ) {
1250 AddressLiteral polling_page(os::get_polling_page());
1251 __ sethi(polling_page, L0);
1252 __ relocate(relocInfo::poll_return_type);
1253 __ ld_ptr( L0, 0, G0 );
1254 }
1255
1256 // If this is a return, then stuff the restore in the delay slot
1257 if( do_polling() ) {
1258 __ ret();
1259 __ delayed()->restore();
1260 } else {
1261 __ restore();
1262 }
1263 }
1264
1265 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1266 return MachNode::size(ra_);
1267 }
1268
1269 int MachEpilogNode::reloc() const {
1270 return 16; // a large enough number
1271 }
1272
1273 const Pipeline * MachEpilogNode::pipeline() const {
1274 return MachNode::pipeline_class();
1275 }
1276
1277 int MachEpilogNode::safepoint_offset() const {
1278 assert( do_polling(), "no return for this epilog node");
1279 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1280 }
1281
1282 //=============================================================================
1283
1284 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1285 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1286 static enum RC rc_class( OptoReg::Name reg ) {
1287 if( !OptoReg::is_valid(reg) ) return rc_bad;
1288 if (OptoReg::is_stack(reg)) return rc_stack;
1289 VMReg r = OptoReg::as_VMReg(reg);
1290 if (r->is_Register()) return rc_int;
1291 assert(r->is_FloatRegister(), "must be");
1292 return rc_float;
1293 }
1294
1295 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1296 if (cbuf) {
1297 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1298 }
1299 #ifndef PRODUCT
1300 else if (!do_size) {
1301 if (size != 0) st->print("\n\t");
1302 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1303 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1304 }
1305 #endif
1306 return size+4;
1307 }
1308
1309 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1310 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1311 #ifndef PRODUCT
1312 else if( !do_size ) {
1313 if( size != 0 ) st->print("\n\t");
1314 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1315 }
1316 #endif
1317 return size+4;
1318 }
1319
1320 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1321 PhaseRegAlloc *ra_,
1322 bool do_size,
1323 outputStream* st ) const {
1324 // Get registers to move
1325 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1326 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1327 OptoReg::Name dst_second = ra_->get_reg_second(this );
1328 OptoReg::Name dst_first = ra_->get_reg_first(this );
1329
1330 enum RC src_second_rc = rc_class(src_second);
1331 enum RC src_first_rc = rc_class(src_first);
1332 enum RC dst_second_rc = rc_class(dst_second);
1333 enum RC dst_first_rc = rc_class(dst_first);
1334
1335 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1336
1337 // Generate spill code!
1338 int size = 0;
1339
1340 if( src_first == dst_first && src_second == dst_second )
1341 return size; // Self copy, no move
1342
1343 // --------------------------------------
1344 // Check for mem-mem move. Load into unused float registers and fall into
1345 // the float-store case.
1346 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1347 int offset = ra_->reg2offset(src_first);
1348 // Further check for aligned-adjacent pair, so we can use a double load
1349 if( (src_first&1)==0 && src_first+1 == src_second ) {
1350 src_second = OptoReg::Name(R_F31_num);
1351 src_second_rc = rc_float;
1352 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1353 } else {
1354 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1355 }
1356 src_first = OptoReg::Name(R_F30_num);
1357 src_first_rc = rc_float;
1358 }
1359
1360 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1361 int offset = ra_->reg2offset(src_second);
1362 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1363 src_second = OptoReg::Name(R_F31_num);
1364 src_second_rc = rc_float;
1365 }
1366
1367 // --------------------------------------
1368 // Check for float->int copy; requires a trip through memory
1369 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1370 int offset = frame::register_save_words*wordSize;
1371 if (cbuf) {
1372 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1373 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1374 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1375 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1376 }
1377 #ifndef PRODUCT
1378 else if (!do_size) {
1379 if (size != 0) st->print("\n\t");
1380 st->print( "SUB R_SP,16,R_SP\n");
1381 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1382 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1383 st->print("\tADD R_SP,16,R_SP\n");
1384 }
1385 #endif
1386 size += 16;
1387 }
1388
1389 // Check for float->int copy on T4
1390 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1391 // Further check for aligned-adjacent pair, so we can use a double move
1392 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1393 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1394 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1395 }
1396 // Check for int->float copy on T4
1397 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1398 // Further check for aligned-adjacent pair, so we can use a double move
1399 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1400 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1401 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1402 }
1403
1404 // --------------------------------------
1405 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1406 // In such cases, I have to do the big-endian swap. For aligned targets, the
1407 // hardware does the flop for me. Doubles are always aligned, so no problem
1408 // there. Misaligned sources only come from native-long-returns (handled
1409 // special below).
1410 #ifndef _LP64
1411 if( src_first_rc == rc_int && // source is already big-endian
1412 src_second_rc != rc_bad && // 64-bit move
1413 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1414 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1415 // Do the big-endian flop.
1416 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1417 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1418 }
1419 #endif
1420
1421 // --------------------------------------
1422 // Check for integer reg-reg copy
1423 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1424 #ifndef _LP64
1425 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1426 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1427 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1428 // operand contains the least significant word of the 64-bit value and vice versa.
1429 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1430 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1431 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1432 if( cbuf ) {
1433 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1434 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1435 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1436 #ifndef PRODUCT
1437 } else if( !do_size ) {
1438 if( size != 0 ) st->print("\n\t");
1439 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1440 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1441 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1442 #endif
1443 }
1444 return size+12;
1445 }
1446 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1447 // returning a long value in I0/I1
1448 // a SpillCopy must be able to target a return instruction's reg_class
1449 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1450 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1451 // operand contains the least significant word of the 64-bit value and vice versa.
1452 OptoReg::Name tdest = dst_first;
1453
1454 if (src_first == dst_first) {
1455 tdest = OptoReg::Name(R_O7_num);
1456 size += 4;
1457 }
1458
1459 if( cbuf ) {
1460 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1461 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1462 // ShrL_reg_imm6
1463 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1464 // ShrR_reg_imm6 src, 0, dst
1465 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1466 if (tdest != dst_first) {
1467 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1468 }
1469 }
1470 #ifndef PRODUCT
1471 else if( !do_size ) {
1472 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1473 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1474 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1475 if (tdest != dst_first) {
1476 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1477 }
1478 }
1479 #endif // PRODUCT
1480 return size+8;
1481 }
1482 #endif // !_LP64
1483 // Else normal reg-reg copy
1484 assert( src_second != dst_first, "smashed second before evacuating it" );
1485 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1486 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1487 // This moves an aligned adjacent pair.
1488 // See if we are done.
1489 if( src_first+1 == src_second && dst_first+1 == dst_second )
1490 return size;
1491 }
1492
1493 // Check for integer store
1494 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1495 int offset = ra_->reg2offset(dst_first);
1496 // Further check for aligned-adjacent pair, so we can use a double store
1497 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1498 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1499 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1500 }
1501
1502 // Check for integer load
1503 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1504 int offset = ra_->reg2offset(src_first);
1505 // Further check for aligned-adjacent pair, so we can use a double load
1506 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1507 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1508 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1509 }
1510
1511 // Check for float reg-reg copy
1512 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1513 // Further check for aligned-adjacent pair, so we can use a double move
1514 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1515 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1516 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1517 }
1518
1519 // Check for float store
1520 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1521 int offset = ra_->reg2offset(dst_first);
1522 // Further check for aligned-adjacent pair, so we can use a double store
1523 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1524 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1525 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1526 }
1527
1528 // Check for float load
1529 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1530 int offset = ra_->reg2offset(src_first);
1531 // Further check for aligned-adjacent pair, so we can use a double load
1532 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1533 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1534 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1535 }
1536
1537 // --------------------------------------------------------------------
1538 // Check for hi bits still needing moving. Only happens for misaligned
1539 // arguments to native calls.
1540 if( src_second == dst_second )
1541 return size; // Self copy; no move
1542 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1543
1544 #ifndef _LP64
1545 // In the LP64 build, all registers can be moved as aligned/adjacent
1546 // pairs, so there's never any need to move the high bits separately.
1547 // The 32-bit builds have to deal with the 32-bit ABI which can force
1548 // all sorts of silly alignment problems.
1549
1550 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1551 // 32-bits of a 64-bit register, but are needed in low bits of another
1552 // register (else it's a hi-bits-to-hi-bits copy which should have
1553 // happened already as part of a 64-bit move)
1554 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1555 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1556 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1557 // Shift src_second down to dst_second's low bits.
1558 if( cbuf ) {
1559 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1560 #ifndef PRODUCT
1561 } else if( !do_size ) {
1562 if( size != 0 ) st->print("\n\t");
1563 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1564 #endif
1565 }
1566 return size+4;
1567 }
1568
1569 // Check for high word integer store. Must down-shift the hi bits
1570 // into a temp register, then fall into the case of storing int bits.
1571 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1572 // Shift src_second down to dst_second's low bits.
1573 if( cbuf ) {
1574 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1575 #ifndef PRODUCT
1576 } else if( !do_size ) {
1577 if( size != 0 ) st->print("\n\t");
1578 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1579 #endif
1580 }
1581 size+=4;
1582 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1583 }
1584
1585 // Check for high word integer load
1586 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1587 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1588
1589 // Check for high word integer store
1590 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1591 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1592
1593 // Check for high word float store
1594 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1595 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1596
1597 #endif // !_LP64
1598
1599 Unimplemented();
1600 }
1601
1602 #ifndef PRODUCT
1603 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1604 implementation( NULL, ra_, false, st );
1605 }
1606 #endif
1607
1608 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1609 implementation( &cbuf, ra_, false, NULL );
1610 }
1611
1612 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1613 return implementation( NULL, ra_, true, NULL );
1614 }
1615
1616 //=============================================================================
1617 #ifndef PRODUCT
1618 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1619 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1620 }
1621 #endif
1622
1623 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1624 MacroAssembler _masm(&cbuf);
1625 for(int i = 0; i < _count; i += 1) {
1626 __ nop();
1627 }
1628 }
1629
1630 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1631 return 4 * _count;
1632 }
1633
1634
1635 //=============================================================================
1636 #ifndef PRODUCT
1637 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1638 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1639 int reg = ra_->get_reg_first(this);
1640 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1641 }
1642 #endif
1643
1644 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1645 MacroAssembler _masm(&cbuf);
1646 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1647 int reg = ra_->get_encode(this);
1648
1649 if (Assembler::is_simm13(offset)) {
1650 __ add(SP, offset, reg_to_register_object(reg));
1651 } else {
1652 __ set(offset, O7);
1653 __ add(SP, O7, reg_to_register_object(reg));
1654 }
1655 }
1656
1657 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1658 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1659 assert(ra_ == ra_->C->regalloc(), "sanity");
1660 return ra_->C->scratch_emit_size(this);
1661 }
1662
1663 //=============================================================================
1664 #ifndef PRODUCT
1665 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1666 st->print_cr("\nUEP:");
1667 #ifdef _LP64
1668 if (UseCompressedClassPointers) {
1669 assert(Universe::heap() != NULL, "java heap should be initialized");
1670 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1671 if (Universe::narrow_klass_base() != 0) {
1672 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1673 if (Universe::narrow_klass_shift() != 0) {
1674 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1675 }
1676 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1677 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1678 } else {
1679 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1680 }
1681 } else {
1682 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1683 }
1684 st->print_cr("\tCMP R_G5,R_G3" );
1685 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1686 #else // _LP64
1687 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1688 st->print_cr("\tCMP R_G5,R_G3" );
1689 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1690 #endif // _LP64
1691 }
1692 #endif
1693
1694 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1695 MacroAssembler _masm(&cbuf);
1696 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1697 Register temp_reg = G3;
1698 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1699
1700 // Load klass from receiver
1701 __ load_klass(O0, temp_reg);
1702 // Compare against expected klass
1703 __ cmp(temp_reg, G5_ic_reg);
1704 // Branch to miss code, checks xcc or icc depending
1705 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1706 }
1707
1708 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1709 return MachNode::size(ra_);
1710 }
1711
1712
1713 //=============================================================================
1714
1715 uint size_exception_handler() {
1716 if (TraceJumps) {
1717 return (400); // just a guess
1718 }
1719 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1720 }
1721
1722 uint size_deopt_handler() {
1723 if (TraceJumps) {
1724 return (400); // just a guess
1725 }
1726 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1727 }
1728
1729 // Emit exception handler code.
1730 int emit_exception_handler(CodeBuffer& cbuf) {
1731 Register temp_reg = G3;
1732 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1733 MacroAssembler _masm(&cbuf);
1734
1735 address base =
1736 __ start_a_stub(size_exception_handler());
1737 if (base == NULL) return 0; // CodeBuffer::expand failed
1738
1739 int offset = __ offset();
1740
1741 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1742 __ delayed()->nop();
1743
1744 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1745
1746 __ end_a_stub();
1747
1748 return offset;
1749 }
1750
1751 int emit_deopt_handler(CodeBuffer& cbuf) {
1752 // Can't use any of the current frame's registers as we may have deopted
1753 // at a poll and everything (including G3) can be live.
1754 Register temp_reg = L0;
1755 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1756 MacroAssembler _masm(&cbuf);
1757
1758 address base =
1759 __ start_a_stub(size_deopt_handler());
1760 if (base == NULL) return 0; // CodeBuffer::expand failed
1761
1762 int offset = __ offset();
1763 __ save_frame(0);
1764 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1765 __ delayed()->restore();
1766
1767 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1768
1769 __ end_a_stub();
1770 return offset;
1771
1772 }
1773
1774 // Given a register encoding, produce a Integer Register object
1775 static Register reg_to_register_object(int register_encoding) {
1776 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1777 return as_Register(register_encoding);
1778 }
1779
1780 // Given a register encoding, produce a single-precision Float Register object
1781 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1782 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1783 return as_SingleFloatRegister(register_encoding);
1784 }
1785
1786 // Given a register encoding, produce a double-precision Float Register object
1787 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1788 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1789 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1790 return as_DoubleFloatRegister(register_encoding);
1791 }
1792
1793 const bool Matcher::match_rule_supported(int opcode) {
1794 if (!has_match_rule(opcode))
1795 return false;
1796
1797 switch (opcode) {
1798 case Op_CountLeadingZerosI:
1799 case Op_CountLeadingZerosL:
1800 case Op_CountTrailingZerosI:
1801 case Op_CountTrailingZerosL:
1802 case Op_PopCountI:
1803 case Op_PopCountL:
1804 if (!UsePopCountInstruction)
1805 return false;
1806 case Op_CompareAndSwapL:
1807 #ifdef _LP64
1808 case Op_CompareAndSwapP:
1809 #endif
1810 if (!VM_Version::supports_cx8())
1811 return false;
1812 break;
1813 }
1814
1815 return true; // Per default match rules are supported.
1816 }
1817
1818 int Matcher::regnum_to_fpu_offset(int regnum) {
1819 return regnum - 32; // The FP registers are in the second chunk
1820 }
1821
1822 #ifdef ASSERT
1823 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1824 #endif
1825
1826 // Vector width in bytes
1827 const int Matcher::vector_width_in_bytes(BasicType bt) {
1828 assert(MaxVectorSize == 8, "");
1829 return 8;
1830 }
1831
1832 // Vector ideal reg
1833 const int Matcher::vector_ideal_reg(int size) {
1834 assert(MaxVectorSize == 8, "");
1835 return Op_RegD;
1836 }
1837
1838 const int Matcher::vector_shift_count_ideal_reg(int size) {
1839 fatal("vector shift is not supported");
1840 return Node::NotAMachineReg;
1841 }
1842
1843 // Limits on vector size (number of elements) loaded into vector.
1844 const int Matcher::max_vector_size(const BasicType bt) {
1845 assert(is_java_primitive(bt), "only primitive type vectors");
1846 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1847 }
1848
1849 const int Matcher::min_vector_size(const BasicType bt) {
1850 return max_vector_size(bt); // Same as max.
1851 }
1852
1853 // SPARC doesn't support misaligned vectors store/load.
1854 const bool Matcher::misaligned_vectors_ok() {
1855 return false;
1856 }
1857
1858 // Current (2013) SPARC platforms need to read original key
1859 // to construct decryption expanded key
1860 const bool Matcher::pass_original_key_for_aes() {
1861 return true;
1862 }
1863
1864 // USII supports fxtof through the whole range of number, USIII doesn't
1865 const bool Matcher::convL2FSupported(void) {
1866 return VM_Version::has_fast_fxtof();
1867 }
1868
1869 // Is this branch offset short enough that a short branch can be used?
1870 //
1871 // NOTE: If the platform does not provide any short branch variants, then
1872 // this method should return false for offset 0.
1873 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1874 // The passed offset is relative to address of the branch.
1875 // Don't need to adjust the offset.
1876 return UseCBCond && Assembler::is_simm12(offset);
1877 }
1878
1879 const bool Matcher::isSimpleConstant64(jlong value) {
1880 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1881 // Depends on optimizations in MacroAssembler::setx.
1882 int hi = (int)(value >> 32);
1883 int lo = (int)(value & ~0);
1884 return (hi == 0) || (hi == -1) || (lo == 0);
1885 }
1886
1887 // No scaling for the parameter the ClearArray node.
1888 const bool Matcher::init_array_count_is_in_bytes = true;
1889
1890 // Threshold size for cleararray.
1891 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1892
1893 // No additional cost for CMOVL.
1894 const int Matcher::long_cmove_cost() { return 0; }
1895
1896 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1897 const int Matcher::float_cmove_cost() {
1898 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1899 }
1900
1901 // Does the CPU require late expand (see block.cpp for description of late expand)?
1902 const bool Matcher::require_postalloc_expand = false;
1903
1904 // Should the Matcher clone shifts on addressing modes, expecting them to
1905 // be subsumed into complex addressing expressions or compute them into
1906 // registers? True for Intel but false for most RISCs
1907 const bool Matcher::clone_shift_expressions = false;
1908
1909 // Do we need to mask the count passed to shift instructions or does
1910 // the cpu only look at the lower 5/6 bits anyway?
1911 const bool Matcher::need_masked_shift_count = false;
1912
1913 bool Matcher::narrow_oop_use_complex_address() {
1914 NOT_LP64(ShouldNotCallThis());
1915 assert(UseCompressedOops, "only for compressed oops code");
1916 return false;
1917 }
1918
1919 bool Matcher::narrow_klass_use_complex_address() {
1920 NOT_LP64(ShouldNotCallThis());
1921 assert(UseCompressedClassPointers, "only for compressed klass code");
1922 return false;
1923 }
1924
1925 // Is it better to copy float constants, or load them directly from memory?
1926 // Intel can load a float constant from a direct address, requiring no
1927 // extra registers. Most RISCs will have to materialize an address into a
1928 // register first, so they would do better to copy the constant from stack.
1929 const bool Matcher::rematerialize_float_constants = false;
1930
1931 // If CPU can load and store mis-aligned doubles directly then no fixup is
1932 // needed. Else we split the double into 2 integer pieces and move it
1933 // piece-by-piece. Only happens when passing doubles into C code as the
1934 // Java calling convention forces doubles to be aligned.
1935 #ifdef _LP64
1936 const bool Matcher::misaligned_doubles_ok = true;
1937 #else
1938 const bool Matcher::misaligned_doubles_ok = false;
1939 #endif
1940
1941 // No-op on SPARC.
1942 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1943 }
1944
1945 // Advertise here if the CPU requires explicit rounding operations
1946 // to implement the UseStrictFP mode.
1947 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1948
1949 // Are floats conerted to double when stored to stack during deoptimization?
1950 // Sparc does not handle callee-save floats.
1951 bool Matcher::float_in_double() { return false; }
1952
1953 // Do ints take an entire long register or just half?
1954 // Note that we if-def off of _LP64.
1955 // The relevant question is how the int is callee-saved. In _LP64
1956 // the whole long is written but de-opt'ing will have to extract
1957 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1958 #ifdef _LP64
1959 const bool Matcher::int_in_long = true;
1960 #else
1961 const bool Matcher::int_in_long = false;
1962 #endif
1963
1964 // Return whether or not this register is ever used as an argument. This
1965 // function is used on startup to build the trampoline stubs in generateOptoStub.
1966 // Registers not mentioned will be killed by the VM call in the trampoline, and
1967 // arguments in those registers not be available to the callee.
1968 bool Matcher::can_be_java_arg( int reg ) {
1969 // Standard sparc 6 args in registers
1970 if( reg == R_I0_num ||
1971 reg == R_I1_num ||
1972 reg == R_I2_num ||
1973 reg == R_I3_num ||
1974 reg == R_I4_num ||
1975 reg == R_I5_num ) return true;
1976 #ifdef _LP64
1977 // 64-bit builds can pass 64-bit pointers and longs in
1978 // the high I registers
1979 if( reg == R_I0H_num ||
1980 reg == R_I1H_num ||
1981 reg == R_I2H_num ||
1982 reg == R_I3H_num ||
1983 reg == R_I4H_num ||
1984 reg == R_I5H_num ) return true;
1985
1986 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1987 return true;
1988 }
1989
1990 #else
1991 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1992 // Longs cannot be passed in O regs, because O regs become I regs
1993 // after a 'save' and I regs get their high bits chopped off on
1994 // interrupt.
1995 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1996 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1997 #endif
1998 // A few float args in registers
1999 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2000
2001 return false;
2002 }
2003
2004 bool Matcher::is_spillable_arg( int reg ) {
2005 return can_be_java_arg(reg);
2006 }
2007
2008 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2009 // Use hardware SDIVX instruction when it is
2010 // faster than a code which use multiply.
2011 return VM_Version::has_fast_idiv();
2012 }
2013
2014 // Register for DIVI projection of divmodI
2015 RegMask Matcher::divI_proj_mask() {
2016 ShouldNotReachHere();
2017 return RegMask();
2018 }
2019
2020 // Register for MODI projection of divmodI
2021 RegMask Matcher::modI_proj_mask() {
2022 ShouldNotReachHere();
2023 return RegMask();
2024 }
2025
2026 // Register for DIVL projection of divmodL
2027 RegMask Matcher::divL_proj_mask() {
2028 ShouldNotReachHere();
2029 return RegMask();
2030 }
2031
2032 // Register for MODL projection of divmodL
2033 RegMask Matcher::modL_proj_mask() {
2034 ShouldNotReachHere();
2035 return RegMask();
2036 }
2037
2038 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2039 return L7_REGP_mask();
2040 }
2041
2042 %}
2043
2044
2045 // The intptr_t operand types, defined by textual substitution.
2046 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2047 #ifdef _LP64
2048 #define immX immL
2049 #define immX13 immL13
2050 #define immX13m7 immL13m7
2051 #define iRegX iRegL
2052 #define g1RegX g1RegL
2053 #else
2054 #define immX immI
2055 #define immX13 immI13
2056 #define immX13m7 immI13m7
2057 #define iRegX iRegI
2058 #define g1RegX g1RegI
2059 #endif
2060
2061 //----------ENCODING BLOCK-----------------------------------------------------
2062 // This block specifies the encoding classes used by the compiler to output
2063 // byte streams. Encoding classes are parameterized macros used by
2064 // Machine Instruction Nodes in order to generate the bit encoding of the
2065 // instruction. Operands specify their base encoding interface with the
2066 // interface keyword. There are currently supported four interfaces,
2067 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2068 // operand to generate a function which returns its register number when
2069 // queried. CONST_INTER causes an operand to generate a function which
2070 // returns the value of the constant when queried. MEMORY_INTER causes an
2071 // operand to generate four functions which return the Base Register, the
2072 // Index Register, the Scale Value, and the Offset Value of the operand when
2073 // queried. COND_INTER causes an operand to generate six functions which
2074 // return the encoding code (ie - encoding bits for the instruction)
2075 // associated with each basic boolean condition for a conditional instruction.
2076 //
2077 // Instructions specify two basic values for encoding. Again, a function
2078 // is available to check if the constant displacement is an oop. They use the
2079 // ins_encode keyword to specify their encoding classes (which must be
2080 // a sequence of enc_class names, and their parameters, specified in
2081 // the encoding block), and they use the
2082 // opcode keyword to specify, in order, their primary, secondary, and
2083 // tertiary opcode. Only the opcode sections which a particular instruction
2084 // needs for encoding need to be specified.
2085 encode %{
2086 enc_class enc_untested %{
2087 #ifdef ASSERT
2088 MacroAssembler _masm(&cbuf);
2089 __ untested("encoding");
2090 #endif
2091 %}
2092
2093 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2094 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2095 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2096 %}
2097
2098 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2099 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2100 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2101 %}
2102
2103 enc_class form3_mem_prefetch_read( memory mem ) %{
2104 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2105 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2106 %}
2107
2108 enc_class form3_mem_prefetch_write( memory mem ) %{
2109 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2110 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2111 %}
2112
2113 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2114 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2115 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2116 guarantee($mem$$index == R_G0_enc, "double index?");
2117 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2118 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2119 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2120 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2121 %}
2122
2123 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2124 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2125 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2126 guarantee($mem$$index == R_G0_enc, "double index?");
2127 // Load long with 2 instructions
2128 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2129 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2130 %}
2131
2132 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2133 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2134 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2135 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2136 %}
2137
2138 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2139 // Encode a reg-reg copy. If it is useless, then empty encoding.
2140 if( $rs2$$reg != $rd$$reg )
2141 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2142 %}
2143
2144 // Target lo half of long
2145 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2146 // Encode a reg-reg copy. If it is useless, then empty encoding.
2147 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2148 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2149 %}
2150
2151 // Source lo half of long
2152 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2153 // Encode a reg-reg copy. If it is useless, then empty encoding.
2154 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2155 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2156 %}
2157
2158 // Target hi half of long
2159 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2160 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2161 %}
2162
2163 // Source lo half of long, and leave it sign extended.
2164 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2165 // Sign extend low half
2166 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2167 %}
2168
2169 // Source hi half of long, and leave it sign extended.
2170 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2171 // Shift high half to low half
2172 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2173 %}
2174
2175 // Source hi half of long
2176 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2177 // Encode a reg-reg copy. If it is useless, then empty encoding.
2178 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2179 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2180 %}
2181
2182 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2183 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2184 %}
2185
2186 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2187 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2188 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2189 %}
2190
2191 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2192 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2193 // clear if nothing else is happening
2194 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2195 // blt,a,pn done
2196 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2197 // mov dst,-1 in delay slot
2198 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2199 %}
2200
2201 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2202 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2203 %}
2204
2205 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2206 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2207 %}
2208
2209 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2210 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2211 %}
2212
2213 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2214 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2215 %}
2216
2217 enc_class move_return_pc_to_o1() %{
2218 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2219 %}
2220
2221 #ifdef _LP64
2222 /* %%% merge with enc_to_bool */
2223 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2224 MacroAssembler _masm(&cbuf);
2225
2226 Register src_reg = reg_to_register_object($src$$reg);
2227 Register dst_reg = reg_to_register_object($dst$$reg);
2228 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2229 %}
2230 #endif
2231
2232 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2233 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2234 MacroAssembler _masm(&cbuf);
2235
2236 Register p_reg = reg_to_register_object($p$$reg);
2237 Register q_reg = reg_to_register_object($q$$reg);
2238 Register y_reg = reg_to_register_object($y$$reg);
2239 Register tmp_reg = reg_to_register_object($tmp$$reg);
2240
2241 __ subcc( p_reg, q_reg, p_reg );
2242 __ add ( p_reg, y_reg, tmp_reg );
2243 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2244 %}
2245
2246 enc_class form_d2i_helper(regD src, regF dst) %{
2247 // fcmp %fcc0,$src,$src
2248 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2249 // branch %fcc0 not-nan, predict taken
2250 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2251 // fdtoi $src,$dst
2252 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2253 // fitos $dst,$dst (if nan)
2254 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2255 // clear $dst (if nan)
2256 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2257 // carry on here...
2258 %}
2259
2260 enc_class form_d2l_helper(regD src, regD dst) %{
2261 // fcmp %fcc0,$src,$src check for NAN
2262 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2263 // branch %fcc0 not-nan, predict taken
2264 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2265 // fdtox $src,$dst convert in delay slot
2266 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2267 // fxtod $dst,$dst (if nan)
2268 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2269 // clear $dst (if nan)
2270 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2271 // carry on here...
2272 %}
2273
2274 enc_class form_f2i_helper(regF src, regF dst) %{
2275 // fcmps %fcc0,$src,$src
2276 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2277 // branch %fcc0 not-nan, predict taken
2278 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2279 // fstoi $src,$dst
2280 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2281 // fitos $dst,$dst (if nan)
2282 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2283 // clear $dst (if nan)
2284 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2285 // carry on here...
2286 %}
2287
2288 enc_class form_f2l_helper(regF src, regD dst) %{
2289 // fcmps %fcc0,$src,$src
2290 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2291 // branch %fcc0 not-nan, predict taken
2292 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2293 // fstox $src,$dst
2294 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2295 // fxtod $dst,$dst (if nan)
2296 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2297 // clear $dst (if nan)
2298 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2299 // carry on here...
2300 %}
2301
2302 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2303 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2304 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2305 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2306
2307 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2308
2309 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2310 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2311
2312 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2313 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2314 %}
2315
2316 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2317 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2318 %}
2319
2320 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2321 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2322 %}
2323
2324 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2325 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2326 %}
2327
2328 enc_class form3_convI2F(regF rs2, regF rd) %{
2329 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2330 %}
2331
2332 // Encloding class for traceable jumps
2333 enc_class form_jmpl(g3RegP dest) %{
2334 emit_jmpl(cbuf, $dest$$reg);
2335 %}
2336
2337 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2338 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2339 %}
2340
2341 enc_class form2_nop() %{
2342 emit_nop(cbuf);
2343 %}
2344
2345 enc_class form2_illtrap() %{
2346 emit_illtrap(cbuf);
2347 %}
2348
2349
2350 // Compare longs and convert into -1, 0, 1.
2351 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2352 // CMP $src1,$src2
2353 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2354 // blt,a,pn done
2355 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2356 // mov dst,-1 in delay slot
2357 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2358 // bgt,a,pn done
2359 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2360 // mov dst,1 in delay slot
2361 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2362 // CLR $dst
2363 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2364 %}
2365
2366 enc_class enc_PartialSubtypeCheck() %{
2367 MacroAssembler _masm(&cbuf);
2368 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2369 __ delayed()->nop();
2370 %}
2371
2372 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2373 MacroAssembler _masm(&cbuf);
2374 Label* L = $labl$$label;
2375 Assembler::Predict predict_taken =
2376 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2377
2378 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2379 __ delayed()->nop();
2380 %}
2381
2382 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2383 MacroAssembler _masm(&cbuf);
2384 Label* L = $labl$$label;
2385 Assembler::Predict predict_taken =
2386 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2387
2388 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2389 __ delayed()->nop();
2390 %}
2391
2392 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2393 int op = (Assembler::arith_op << 30) |
2394 ($dst$$reg << 25) |
2395 (Assembler::movcc_op3 << 19) |
2396 (1 << 18) | // cc2 bit for 'icc'
2397 ($cmp$$cmpcode << 14) |
2398 (0 << 13) | // select register move
2399 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2400 ($src$$reg << 0);
2401 cbuf.insts()->emit_int32(op);
2402 %}
2403
2404 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2405 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2406 int op = (Assembler::arith_op << 30) |
2407 ($dst$$reg << 25) |
2408 (Assembler::movcc_op3 << 19) |
2409 (1 << 18) | // cc2 bit for 'icc'
2410 ($cmp$$cmpcode << 14) |
2411 (1 << 13) | // select immediate move
2412 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2413 (simm11 << 0);
2414 cbuf.insts()->emit_int32(op);
2415 %}
2416
2417 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2418 int op = (Assembler::arith_op << 30) |
2419 ($dst$$reg << 25) |
2420 (Assembler::movcc_op3 << 19) |
2421 (0 << 18) | // cc2 bit for 'fccX'
2422 ($cmp$$cmpcode << 14) |
2423 (0 << 13) | // select register move
2424 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2425 ($src$$reg << 0);
2426 cbuf.insts()->emit_int32(op);
2427 %}
2428
2429 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2430 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2431 int op = (Assembler::arith_op << 30) |
2432 ($dst$$reg << 25) |
2433 (Assembler::movcc_op3 << 19) |
2434 (0 << 18) | // cc2 bit for 'fccX'
2435 ($cmp$$cmpcode << 14) |
2436 (1 << 13) | // select immediate move
2437 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2438 (simm11 << 0);
2439 cbuf.insts()->emit_int32(op);
2440 %}
2441
2442 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2443 int op = (Assembler::arith_op << 30) |
2444 ($dst$$reg << 25) |
2445 (Assembler::fpop2_op3 << 19) |
2446 (0 << 18) |
2447 ($cmp$$cmpcode << 14) |
2448 (1 << 13) | // select register move
2449 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2450 ($primary << 5) | // select single, double or quad
2451 ($src$$reg << 0);
2452 cbuf.insts()->emit_int32(op);
2453 %}
2454
2455 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2456 int op = (Assembler::arith_op << 30) |
2457 ($dst$$reg << 25) |
2458 (Assembler::fpop2_op3 << 19) |
2459 (0 << 18) |
2460 ($cmp$$cmpcode << 14) |
2461 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2462 ($primary << 5) | // select single, double or quad
2463 ($src$$reg << 0);
2464 cbuf.insts()->emit_int32(op);
2465 %}
2466
2467 // Used by the MIN/MAX encodings. Same as a CMOV, but
2468 // the condition comes from opcode-field instead of an argument.
2469 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2470 int op = (Assembler::arith_op << 30) |
2471 ($dst$$reg << 25) |
2472 (Assembler::movcc_op3 << 19) |
2473 (1 << 18) | // cc2 bit for 'icc'
2474 ($primary << 14) |
2475 (0 << 13) | // select register move
2476 (0 << 11) | // cc1, cc0 bits for 'icc'
2477 ($src$$reg << 0);
2478 cbuf.insts()->emit_int32(op);
2479 %}
2480
2481 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2482 int op = (Assembler::arith_op << 30) |
2483 ($dst$$reg << 25) |
2484 (Assembler::movcc_op3 << 19) |
2485 (6 << 16) | // cc2 bit for 'xcc'
2486 ($primary << 14) |
2487 (0 << 13) | // select register move
2488 (0 << 11) | // cc1, cc0 bits for 'icc'
2489 ($src$$reg << 0);
2490 cbuf.insts()->emit_int32(op);
2491 %}
2492
2493 enc_class Set13( immI13 src, iRegI rd ) %{
2494 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2495 %}
2496
2497 enc_class SetHi22( immI src, iRegI rd ) %{
2498 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2499 %}
2500
2501 enc_class Set32( immI src, iRegI rd ) %{
2502 MacroAssembler _masm(&cbuf);
2503 __ set($src$$constant, reg_to_register_object($rd$$reg));
2504 %}
2505
2506 enc_class call_epilog %{
2507 if( VerifyStackAtCalls ) {
2508 MacroAssembler _masm(&cbuf);
2509 int framesize = ra_->C->frame_size_in_bytes();
2510 Register temp_reg = G3;
2511 __ add(SP, framesize, temp_reg);
2512 __ cmp(temp_reg, FP);
2513 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2514 }
2515 %}
2516
2517 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2518 // to G1 so the register allocator will not have to deal with the misaligned register
2519 // pair.
2520 enc_class adjust_long_from_native_call %{
2521 #ifndef _LP64
2522 if (returns_long()) {
2523 // sllx O0,32,O0
2524 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2525 // srl O1,0,O1
2526 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2527 // or O0,O1,G1
2528 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2529 }
2530 #endif
2531 %}
2532
2533 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2534 // CALL directly to the runtime
2535 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2536 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2537 /*preserve_g2=*/true);
2538 %}
2539
2540 enc_class preserve_SP %{
2541 MacroAssembler _masm(&cbuf);
2542 __ mov(SP, L7_mh_SP_save);
2543 %}
2544
2545 enc_class restore_SP %{
2546 MacroAssembler _masm(&cbuf);
2547 __ mov(L7_mh_SP_save, SP);
2548 %}
2549
2550 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2551 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2552 // who we intended to call.
2553 if (!_method) {
2554 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2555 } else if (_optimized_virtual) {
2556 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2557 } else {
2558 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2559 }
2560 if (_method) { // Emit stub for static call.
2561 CompiledStaticCall::emit_to_interp_stub(cbuf);
2562 }
2563 %}
2564
2565 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2566 MacroAssembler _masm(&cbuf);
2567 __ set_inst_mark();
2568 int vtable_index = this->_vtable_index;
2569 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2570 if (vtable_index < 0) {
2571 // must be invalid_vtable_index, not nonvirtual_vtable_index
2572 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2573 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2574 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2575 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2576 __ ic_call((address)$meth$$method);
2577 } else {
2578 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2579 // Just go thru the vtable
2580 // get receiver klass (receiver already checked for non-null)
2581 // If we end up going thru a c2i adapter interpreter expects method in G5
2582 int off = __ offset();
2583 __ load_klass(O0, G3_scratch);
2584 int klass_load_size;
2585 if (UseCompressedClassPointers) {
2586 assert(Universe::heap() != NULL, "java heap should be initialized");
2587 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2588 } else {
2589 klass_load_size = 1*BytesPerInstWord;
2590 }
2591 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2592 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2593 if (Assembler::is_simm13(v_off)) {
2594 __ ld_ptr(G3, v_off, G5_method);
2595 } else {
2596 // Generate 2 instructions
2597 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2598 __ or3(G5_method, v_off & 0x3ff, G5_method);
2599 // ld_ptr, set_hi, set
2600 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2601 "Unexpected instruction size(s)");
2602 __ ld_ptr(G3, G5_method, G5_method);
2603 }
2604 // NOTE: for vtable dispatches, the vtable entry will never be null.
2605 // However it may very well end up in handle_wrong_method if the
2606 // method is abstract for the particular class.
2607 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2608 // jump to target (either compiled code or c2iadapter)
2609 __ jmpl(G3_scratch, G0, O7);
2610 __ delayed()->nop();
2611 }
2612 %}
2613
2614 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2615 MacroAssembler _masm(&cbuf);
2616
2617 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2618 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2619 // we might be calling a C2I adapter which needs it.
2620
2621 assert(temp_reg != G5_ic_reg, "conflicting registers");
2622 // Load nmethod
2623 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2624
2625 // CALL to compiled java, indirect the contents of G3
2626 __ set_inst_mark();
2627 __ callr(temp_reg, G0);
2628 __ delayed()->nop();
2629 %}
2630
2631 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2632 MacroAssembler _masm(&cbuf);
2633 Register Rdividend = reg_to_register_object($src1$$reg);
2634 Register Rdivisor = reg_to_register_object($src2$$reg);
2635 Register Rresult = reg_to_register_object($dst$$reg);
2636
2637 __ sra(Rdivisor, 0, Rdivisor);
2638 __ sra(Rdividend, 0, Rdividend);
2639 __ sdivx(Rdividend, Rdivisor, Rresult);
2640 %}
2641
2642 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2643 MacroAssembler _masm(&cbuf);
2644
2645 Register Rdividend = reg_to_register_object($src1$$reg);
2646 int divisor = $imm$$constant;
2647 Register Rresult = reg_to_register_object($dst$$reg);
2648
2649 __ sra(Rdividend, 0, Rdividend);
2650 __ sdivx(Rdividend, divisor, Rresult);
2651 %}
2652
2653 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2654 MacroAssembler _masm(&cbuf);
2655 Register Rsrc1 = reg_to_register_object($src1$$reg);
2656 Register Rsrc2 = reg_to_register_object($src2$$reg);
2657 Register Rdst = reg_to_register_object($dst$$reg);
2658
2659 __ sra( Rsrc1, 0, Rsrc1 );
2660 __ sra( Rsrc2, 0, Rsrc2 );
2661 __ mulx( Rsrc1, Rsrc2, Rdst );
2662 __ srlx( Rdst, 32, Rdst );
2663 %}
2664
2665 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2666 MacroAssembler _masm(&cbuf);
2667 Register Rdividend = reg_to_register_object($src1$$reg);
2668 Register Rdivisor = reg_to_register_object($src2$$reg);
2669 Register Rresult = reg_to_register_object($dst$$reg);
2670 Register Rscratch = reg_to_register_object($scratch$$reg);
2671
2672 assert(Rdividend != Rscratch, "");
2673 assert(Rdivisor != Rscratch, "");
2674
2675 __ sra(Rdividend, 0, Rdividend);
2676 __ sra(Rdivisor, 0, Rdivisor);
2677 __ sdivx(Rdividend, Rdivisor, Rscratch);
2678 __ mulx(Rscratch, Rdivisor, Rscratch);
2679 __ sub(Rdividend, Rscratch, Rresult);
2680 %}
2681
2682 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2683 MacroAssembler _masm(&cbuf);
2684
2685 Register Rdividend = reg_to_register_object($src1$$reg);
2686 int divisor = $imm$$constant;
2687 Register Rresult = reg_to_register_object($dst$$reg);
2688 Register Rscratch = reg_to_register_object($scratch$$reg);
2689
2690 assert(Rdividend != Rscratch, "");
2691
2692 __ sra(Rdividend, 0, Rdividend);
2693 __ sdivx(Rdividend, divisor, Rscratch);
2694 __ mulx(Rscratch, divisor, Rscratch);
2695 __ sub(Rdividend, Rscratch, Rresult);
2696 %}
2697
2698 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2699 MacroAssembler _masm(&cbuf);
2700
2701 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2702 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2703
2704 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2705 %}
2706
2707 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2708 MacroAssembler _masm(&cbuf);
2709
2710 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2711 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2712
2713 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2714 %}
2715
2716 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2717 MacroAssembler _masm(&cbuf);
2718
2719 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2720 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2721
2722 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2723 %}
2724
2725 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2726 MacroAssembler _masm(&cbuf);
2727
2728 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2729 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2730
2731 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2732 %}
2733
2734 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2735 MacroAssembler _masm(&cbuf);
2736
2737 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2738 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2739
2740 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2741 %}
2742
2743 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2744 MacroAssembler _masm(&cbuf);
2745
2746 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2747 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2748
2749 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2750 %}
2751
2752 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2753 MacroAssembler _masm(&cbuf);
2754
2755 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2756 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2757
2758 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2759 %}
2760
2761 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2762 MacroAssembler _masm(&cbuf);
2763
2764 Register Roop = reg_to_register_object($oop$$reg);
2765 Register Rbox = reg_to_register_object($box$$reg);
2766 Register Rscratch = reg_to_register_object($scratch$$reg);
2767 Register Rmark = reg_to_register_object($scratch2$$reg);
2768
2769 assert(Roop != Rscratch, "");
2770 assert(Roop != Rmark, "");
2771 assert(Rbox != Rscratch, "");
2772 assert(Rbox != Rmark, "");
2773
2774 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2775 %}
2776
2777 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2778 MacroAssembler _masm(&cbuf);
2779
2780 Register Roop = reg_to_register_object($oop$$reg);
2781 Register Rbox = reg_to_register_object($box$$reg);
2782 Register Rscratch = reg_to_register_object($scratch$$reg);
2783 Register Rmark = reg_to_register_object($scratch2$$reg);
2784
2785 assert(Roop != Rscratch, "");
2786 assert(Roop != Rmark, "");
2787 assert(Rbox != Rscratch, "");
2788 assert(Rbox != Rmark, "");
2789
2790 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2791 %}
2792
2793 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2794 MacroAssembler _masm(&cbuf);
2795 Register Rmem = reg_to_register_object($mem$$reg);
2796 Register Rold = reg_to_register_object($old$$reg);
2797 Register Rnew = reg_to_register_object($new$$reg);
2798
2799 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2800 __ cmp( Rold, Rnew );
2801 %}
2802
2803 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2804 Register Rmem = reg_to_register_object($mem$$reg);
2805 Register Rold = reg_to_register_object($old$$reg);
2806 Register Rnew = reg_to_register_object($new$$reg);
2807
2808 MacroAssembler _masm(&cbuf);
2809 __ mov(Rnew, O7);
2810 __ casx(Rmem, Rold, O7);
2811 __ cmp( Rold, O7 );
2812 %}
2813
2814 // raw int cas, used for compareAndSwap
2815 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2816 Register Rmem = reg_to_register_object($mem$$reg);
2817 Register Rold = reg_to_register_object($old$$reg);
2818 Register Rnew = reg_to_register_object($new$$reg);
2819
2820 MacroAssembler _masm(&cbuf);
2821 __ mov(Rnew, O7);
2822 __ cas(Rmem, Rold, O7);
2823 __ cmp( Rold, O7 );
2824 %}
2825
2826 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2827 Register Rres = reg_to_register_object($res$$reg);
2828
2829 MacroAssembler _masm(&cbuf);
2830 __ mov(1, Rres);
2831 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2832 %}
2833
2834 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2835 Register Rres = reg_to_register_object($res$$reg);
2836
2837 MacroAssembler _masm(&cbuf);
2838 __ mov(1, Rres);
2839 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2840 %}
2841
2842 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2843 MacroAssembler _masm(&cbuf);
2844 Register Rdst = reg_to_register_object($dst$$reg);
2845 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2846 : reg_to_DoubleFloatRegister_object($src1$$reg);
2847 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2848 : reg_to_DoubleFloatRegister_object($src2$$reg);
2849
2850 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2851 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2852 %}
2853
2854
2855 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2856 Label Ldone, Lloop;
2857 MacroAssembler _masm(&cbuf);
2858
2859 Register str1_reg = reg_to_register_object($str1$$reg);
2860 Register str2_reg = reg_to_register_object($str2$$reg);
2861 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2862 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2863 Register result_reg = reg_to_register_object($result$$reg);
2864
2865 assert(result_reg != str1_reg &&
2866 result_reg != str2_reg &&
2867 result_reg != cnt1_reg &&
2868 result_reg != cnt2_reg ,
2869 "need different registers");
2870
2871 // Compute the minimum of the string lengths(str1_reg) and the
2872 // difference of the string lengths (stack)
2873
2874 // See if the lengths are different, and calculate min in str1_reg.
2875 // Stash diff in O7 in case we need it for a tie-breaker.
2876 Label Lskip;
2877 __ subcc(cnt1_reg, cnt2_reg, O7);
2878 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2879 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2880 // cnt2 is shorter, so use its count:
2881 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2882 __ bind(Lskip);
2883
2884 // reallocate cnt1_reg, cnt2_reg, result_reg
2885 // Note: limit_reg holds the string length pre-scaled by 2
2886 Register limit_reg = cnt1_reg;
2887 Register chr2_reg = cnt2_reg;
2888 Register chr1_reg = result_reg;
2889 // str{12} are the base pointers
2890
2891 // Is the minimum length zero?
2892 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2893 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2894 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2895
2896 // Load first characters
2897 __ lduh(str1_reg, 0, chr1_reg);
2898 __ lduh(str2_reg, 0, chr2_reg);
2899
2900 // Compare first characters
2901 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2902 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2903 assert(chr1_reg == result_reg, "result must be pre-placed");
2904 __ delayed()->nop();
2905
2906 {
2907 // Check after comparing first character to see if strings are equivalent
2908 Label LSkip2;
2909 // Check if the strings start at same location
2910 __ cmp(str1_reg, str2_reg);
2911 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2912 __ delayed()->nop();
2913
2914 // Check if the length difference is zero (in O7)
2915 __ cmp(G0, O7);
2916 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2917 __ delayed()->mov(G0, result_reg); // result is zero
2918
2919 // Strings might not be equal
2920 __ bind(LSkip2);
2921 }
2922
2923 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2924 __ signx(limit_reg);
2925
2926 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2927 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2928 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2929
2930 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2931 __ add(str1_reg, limit_reg, str1_reg);
2932 __ add(str2_reg, limit_reg, str2_reg);
2933 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2934
2935 // Compare the rest of the characters
2936 __ lduh(str1_reg, limit_reg, chr1_reg);
2937 __ bind(Lloop);
2938 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2939 __ lduh(str2_reg, limit_reg, chr2_reg);
2940 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2941 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2942 assert(chr1_reg == result_reg, "result must be pre-placed");
2943 __ delayed()->inccc(limit_reg, sizeof(jchar));
2944 // annul LDUH if branch is not taken to prevent access past end of string
2945 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2946 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2947
2948 // If strings are equal up to min length, return the length difference.
2949 __ mov(O7, result_reg);
2950
2951 // Otherwise, return the difference between the first mismatched chars.
2952 __ bind(Ldone);
2953 %}
2954
2955 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2956 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2957 MacroAssembler _masm(&cbuf);
2958
2959 Register str1_reg = reg_to_register_object($str1$$reg);
2960 Register str2_reg = reg_to_register_object($str2$$reg);
2961 Register cnt_reg = reg_to_register_object($cnt$$reg);
2962 Register tmp1_reg = O7;
2963 Register result_reg = reg_to_register_object($result$$reg);
2964
2965 assert(result_reg != str1_reg &&
2966 result_reg != str2_reg &&
2967 result_reg != cnt_reg &&
2968 result_reg != tmp1_reg ,
2969 "need different registers");
2970
2971 __ cmp(str1_reg, str2_reg); //same char[] ?
2972 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2973 __ delayed()->add(G0, 1, result_reg);
2974
2975 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2976 __ delayed()->add(G0, 1, result_reg); // count == 0
2977
2978 //rename registers
2979 Register limit_reg = cnt_reg;
2980 Register chr1_reg = result_reg;
2981 Register chr2_reg = tmp1_reg;
2982
2983 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2984 __ signx(limit_reg);
2985
2986 //check for alignment and position the pointers to the ends
2987 __ or3(str1_reg, str2_reg, chr1_reg);
2988 __ andcc(chr1_reg, 0x3, chr1_reg);
2989 // notZero means at least one not 4-byte aligned.
2990 // We could optimize the case when both arrays are not aligned
2991 // but it is not frequent case and it requires additional checks.
2992 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2993 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2994
2995 // Compare char[] arrays aligned to 4 bytes.
2996 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2997 chr1_reg, chr2_reg, Ldone);
2998 __ ba(Ldone);
2999 __ delayed()->add(G0, 1, result_reg);
3000
3001 // char by char compare
3002 __ bind(Lchar);
3003 __ add(str1_reg, limit_reg, str1_reg);
3004 __ add(str2_reg, limit_reg, str2_reg);
3005 __ neg(limit_reg); //negate count
3006
3007 __ lduh(str1_reg, limit_reg, chr1_reg);
3008 // Lchar_loop
3009 __ bind(Lchar_loop);
3010 __ lduh(str2_reg, limit_reg, chr2_reg);
3011 __ cmp(chr1_reg, chr2_reg);
3012 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3013 __ delayed()->mov(G0, result_reg); //not equal
3014 __ inccc(limit_reg, sizeof(jchar));
3015 // annul LDUH if branch is not taken to prevent access past end of string
3016 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3017 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3018
3019 __ add(G0, 1, result_reg); //equal
3020
3021 __ bind(Ldone);
3022 %}
3023
3024 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3025 Label Lvector, Ldone, Lloop;
3026 MacroAssembler _masm(&cbuf);
3027
3028 Register ary1_reg = reg_to_register_object($ary1$$reg);
3029 Register ary2_reg = reg_to_register_object($ary2$$reg);
3030 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3031 Register tmp2_reg = O7;
3032 Register result_reg = reg_to_register_object($result$$reg);
3033
3034 int length_offset = arrayOopDesc::length_offset_in_bytes();
3035 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3036
3037 // return true if the same array
3038 __ cmp(ary1_reg, ary2_reg);
3039 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3040 __ delayed()->add(G0, 1, result_reg); // equal
3041
3042 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3043 __ delayed()->mov(G0, result_reg); // not equal
3044
3045 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3046 __ delayed()->mov(G0, result_reg); // not equal
3047
3048 //load the lengths of arrays
3049 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3050 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3051
3052 // return false if the two arrays are not equal length
3053 __ cmp(tmp1_reg, tmp2_reg);
3054 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3055 __ delayed()->mov(G0, result_reg); // not equal
3056
3057 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3058 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3059
3060 // load array addresses
3061 __ add(ary1_reg, base_offset, ary1_reg);
3062 __ add(ary2_reg, base_offset, ary2_reg);
3063
3064 // renaming registers
3065 Register chr1_reg = result_reg; // for characters in ary1
3066 Register chr2_reg = tmp2_reg; // for characters in ary2
3067 Register limit_reg = tmp1_reg; // length
3068
3069 // set byte count
3070 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3071
3072 // Compare char[] arrays aligned to 4 bytes.
3073 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3074 chr1_reg, chr2_reg, Ldone);
3075 __ add(G0, 1, result_reg); // equals
3076
3077 __ bind(Ldone);
3078 %}
3079
3080 enc_class enc_rethrow() %{
3081 cbuf.set_insts_mark();
3082 Register temp_reg = G3;
3083 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3084 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3085 MacroAssembler _masm(&cbuf);
3086 #ifdef ASSERT
3087 __ save_frame(0);
3088 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3089 __ sethi(last_rethrow_addrlit, L1);
3090 Address addr(L1, last_rethrow_addrlit.low10());
3091 __ rdpc(L2);
3092 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3093 __ st_ptr(L2, addr);
3094 __ restore();
3095 #endif
3096 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3097 __ delayed()->nop();
3098 %}
3099
3100 enc_class emit_mem_nop() %{
3101 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3102 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3103 %}
3104
3105 enc_class emit_fadd_nop() %{
3106 // Generates the instruction FMOVS f31,f31
3107 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3108 %}
3109
3110 enc_class emit_br_nop() %{
3111 // Generates the instruction BPN,PN .
3112 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3113 %}
3114
3115 enc_class enc_membar_acquire %{
3116 MacroAssembler _masm(&cbuf);
3117 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3118 %}
3119
3120 enc_class enc_membar_release %{
3121 MacroAssembler _masm(&cbuf);
3122 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3123 %}
3124
3125 enc_class enc_membar_volatile %{
3126 MacroAssembler _masm(&cbuf);
3127 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3128 %}
3129
3130 %}
3131
3132 //----------FRAME--------------------------------------------------------------
3133 // Definition of frame structure and management information.
3134 //
3135 // S T A C K L A Y O U T Allocators stack-slot number
3136 // | (to get allocators register number
3137 // G Owned by | | v add VMRegImpl::stack0)
3138 // r CALLER | |
3139 // o | +--------+ pad to even-align allocators stack-slot
3140 // w V | pad0 | numbers; owned by CALLER
3141 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3142 // h ^ | in | 5
3143 // | | args | 4 Holes in incoming args owned by SELF
3144 // | | | | 3
3145 // | | +--------+
3146 // V | | old out| Empty on Intel, window on Sparc
3147 // | old |preserve| Must be even aligned.
3148 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3149 // | | in | 3 area for Intel ret address
3150 // Owned by |preserve| Empty on Sparc.
3151 // SELF +--------+
3152 // | | pad2 | 2 pad to align old SP
3153 // | +--------+ 1
3154 // | | locks | 0
3155 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3156 // | | pad1 | 11 pad to align new SP
3157 // | +--------+
3158 // | | | 10
3159 // | | spills | 9 spills
3160 // V | | 8 (pad0 slot for callee)
3161 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3162 // ^ | out | 7
3163 // | | args | 6 Holes in outgoing args owned by CALLEE
3164 // Owned by +--------+
3165 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3166 // | new |preserve| Must be even-aligned.
3167 // | SP-+--------+----> Matcher::_new_SP, even aligned
3168 // | | |
3169 //
3170 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3171 // known from SELF's arguments and the Java calling convention.
3172 // Region 6-7 is determined per call site.
3173 // Note 2: If the calling convention leaves holes in the incoming argument
3174 // area, those holes are owned by SELF. Holes in the outgoing area
3175 // are owned by the CALLEE. Holes should not be nessecary in the
3176 // incoming area, as the Java calling convention is completely under
3177 // the control of the AD file. Doubles can be sorted and packed to
3178 // avoid holes. Holes in the outgoing arguments may be nessecary for
3179 // varargs C calling conventions.
3180 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3181 // even aligned with pad0 as needed.
3182 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3183 // region 6-11 is even aligned; it may be padded out more so that
3184 // the region from SP to FP meets the minimum stack alignment.
3185
3186 frame %{
3187 // What direction does stack grow in (assumed to be same for native & Java)
3188 stack_direction(TOWARDS_LOW);
3189
3190 // These two registers define part of the calling convention
3191 // between compiled code and the interpreter.
3192 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3193 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3194
3195 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3196 cisc_spilling_operand_name(indOffset);
3197
3198 // Number of stack slots consumed by a Monitor enter
3199 #ifdef _LP64
3200 sync_stack_slots(2);
3201 #else
3202 sync_stack_slots(1);
3203 #endif
3204
3205 // Compiled code's Frame Pointer
3206 frame_pointer(R_SP);
3207
3208 // Stack alignment requirement
3209 stack_alignment(StackAlignmentInBytes);
3210 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3211 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3212
3213 // Number of stack slots between incoming argument block and the start of
3214 // a new frame. The PROLOG must add this many slots to the stack. The
3215 // EPILOG must remove this many slots.
3216 in_preserve_stack_slots(0);
3217
3218 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3219 // for calls to C. Supports the var-args backing area for register parms.
3220 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3221 #ifdef _LP64
3222 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3223 varargs_C_out_slots_killed(12);
3224 #else
3225 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3226 varargs_C_out_slots_killed( 7);
3227 #endif
3228
3229 // The after-PROLOG location of the return address. Location of
3230 // return address specifies a type (REG or STACK) and a number
3231 // representing the register number (i.e. - use a register name) or
3232 // stack slot.
3233 return_addr(REG R_I7); // Ret Addr is in register I7
3234
3235 // Body of function which returns an OptoRegs array locating
3236 // arguments either in registers or in stack slots for calling
3237 // java
3238 calling_convention %{
3239 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3240
3241 %}
3242
3243 // Body of function which returns an OptoRegs array locating
3244 // arguments either in registers or in stack slots for callin
3245 // C.
3246 c_calling_convention %{
3247 // This is obviously always outgoing
3248 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3249 %}
3250
3251 // Location of native (C/C++) and interpreter return values. This is specified to
3252 // be the same as Java. In the 32-bit VM, long values are actually returned from
3253 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3254 // to and from the register pairs is done by the appropriate call and epilog
3255 // opcodes. This simplifies the register allocator.
3256 c_return_value %{
3257 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3258 #ifdef _LP64
3259 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3260 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3261 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3262 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3263 #else // !_LP64
3264 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3265 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3266 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3267 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3268 #endif
3269 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3270 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3271 %}
3272
3273 // Location of compiled Java return values. Same as C
3274 return_value %{
3275 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3276 #ifdef _LP64
3277 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3278 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3279 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3280 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3281 #else // !_LP64
3282 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3283 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3284 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3285 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3286 #endif
3287 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3288 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3289 %}
3290
3291 %}
3292
3293
3294 //----------ATTRIBUTES---------------------------------------------------------
3295 //----------Operand Attributes-------------------------------------------------
3296 op_attrib op_cost(1); // Required cost attribute
3297
3298 //----------Instruction Attributes---------------------------------------------
3299 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3300 ins_attrib ins_size(32); // Required size attribute (in bits)
3301 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3302 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3303 // non-matching short branch variant of some
3304 // long branch?
3305
3306 //----------OPERANDS-----------------------------------------------------------
3307 // Operand definitions must precede instruction definitions for correct parsing
3308 // in the ADLC because operands constitute user defined types which are used in
3309 // instruction definitions.
3310
3311 //----------Simple Operands----------------------------------------------------
3312 // Immediate Operands
3313 // Integer Immediate: 32-bit
3314 operand immI() %{
3315 match(ConI);
3316
3317 op_cost(0);
3318 // formats are generated automatically for constants and base registers
3319 format %{ %}
3320 interface(CONST_INTER);
3321 %}
3322
3323 // Integer Immediate: 8-bit
3324 operand immI8() %{
3325 predicate(Assembler::is_simm8(n->get_int()));
3326 match(ConI);
3327 op_cost(0);
3328 format %{ %}
3329 interface(CONST_INTER);
3330 %}
3331
3332 // Integer Immediate: 13-bit
3333 operand immI13() %{
3334 predicate(Assembler::is_simm13(n->get_int()));
3335 match(ConI);
3336 op_cost(0);
3337
3338 format %{ %}
3339 interface(CONST_INTER);
3340 %}
3341
3342 // Integer Immediate: 13-bit minus 7
3343 operand immI13m7() %{
3344 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3345 match(ConI);
3346 op_cost(0);
3347
3348 format %{ %}
3349 interface(CONST_INTER);
3350 %}
3351
3352 // Integer Immediate: 16-bit
3353 operand immI16() %{
3354 predicate(Assembler::is_simm16(n->get_int()));
3355 match(ConI);
3356 op_cost(0);
3357 format %{ %}
3358 interface(CONST_INTER);
3359 %}
3360
3361 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3362 operand immU12() %{
3363 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3364 match(ConI);
3365 op_cost(0);
3366
3367 format %{ %}
3368 interface(CONST_INTER);
3369 %}
3370
3371 // Integer Immediate: 6-bit
3372 operand immU6() %{
3373 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3374 match(ConI);
3375 op_cost(0);
3376 format %{ %}
3377 interface(CONST_INTER);
3378 %}
3379
3380 // Integer Immediate: 11-bit
3381 operand immI11() %{
3382 predicate(Assembler::is_simm11(n->get_int()));
3383 match(ConI);
3384 op_cost(0);
3385 format %{ %}
3386 interface(CONST_INTER);
3387 %}
3388
3389 // Integer Immediate: 5-bit
3390 operand immI5() %{
3391 predicate(Assembler::is_simm5(n->get_int()));
3392 match(ConI);
3393 op_cost(0);
3394 format %{ %}
3395 interface(CONST_INTER);
3396 %}
3397
3398 // Int Immediate non-negative
3399 operand immU31()
3400 %{
3401 predicate(n->get_int() >= 0);
3402 match(ConI);
3403
3404 op_cost(0);
3405 format %{ %}
3406 interface(CONST_INTER);
3407 %}
3408
3409 // Integer Immediate: 0-bit
3410 operand immI0() %{
3411 predicate(n->get_int() == 0);
3412 match(ConI);
3413 op_cost(0);
3414
3415 format %{ %}
3416 interface(CONST_INTER);
3417 %}
3418
3419 // Integer Immediate: the value 10
3420 operand immI10() %{
3421 predicate(n->get_int() == 10);
3422 match(ConI);
3423 op_cost(0);
3424
3425 format %{ %}
3426 interface(CONST_INTER);
3427 %}
3428
3429 // Integer Immediate: the values 0-31
3430 operand immU5() %{
3431 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3432 match(ConI);
3433 op_cost(0);
3434
3435 format %{ %}
3436 interface(CONST_INTER);
3437 %}
3438
3439 // Integer Immediate: the values 1-31
3440 operand immI_1_31() %{
3441 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3442 match(ConI);
3443 op_cost(0);
3444
3445 format %{ %}
3446 interface(CONST_INTER);
3447 %}
3448
3449 // Integer Immediate: the values 32-63
3450 operand immI_32_63() %{
3451 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3452 match(ConI);
3453 op_cost(0);
3454
3455 format %{ %}
3456 interface(CONST_INTER);
3457 %}
3458
3459 // Immediates for special shifts (sign extend)
3460
3461 // Integer Immediate: the value 16
3462 operand immI_16() %{
3463 predicate(n->get_int() == 16);
3464 match(ConI);
3465 op_cost(0);
3466
3467 format %{ %}
3468 interface(CONST_INTER);
3469 %}
3470
3471 // Integer Immediate: the value 24
3472 operand immI_24() %{
3473 predicate(n->get_int() == 24);
3474 match(ConI);
3475 op_cost(0);
3476
3477 format %{ %}
3478 interface(CONST_INTER);
3479 %}
3480
3481 // Integer Immediate: the value 255
3482 operand immI_255() %{
3483 predicate( n->get_int() == 255 );
3484 match(ConI);
3485 op_cost(0);
3486
3487 format %{ %}
3488 interface(CONST_INTER);
3489 %}
3490
3491 // Integer Immediate: the value 65535
3492 operand immI_65535() %{
3493 predicate(n->get_int() == 65535);
3494 match(ConI);
3495 op_cost(0);
3496
3497 format %{ %}
3498 interface(CONST_INTER);
3499 %}
3500
3501 // Long Immediate: the value FF
3502 operand immL_FF() %{
3503 predicate( n->get_long() == 0xFFL );
3504 match(ConL);
3505 op_cost(0);
3506
3507 format %{ %}
3508 interface(CONST_INTER);
3509 %}
3510
3511 // Long Immediate: the value FFFF
3512 operand immL_FFFF() %{
3513 predicate( n->get_long() == 0xFFFFL );
3514 match(ConL);
3515 op_cost(0);
3516
3517 format %{ %}
3518 interface(CONST_INTER);
3519 %}
3520
3521 // Pointer Immediate: 32 or 64-bit
3522 operand immP() %{
3523 match(ConP);
3524
3525 op_cost(5);
3526 // formats are generated automatically for constants and base registers
3527 format %{ %}
3528 interface(CONST_INTER);
3529 %}
3530
3531 #ifdef _LP64
3532 // Pointer Immediate: 64-bit
3533 operand immP_set() %{
3534 predicate(!VM_Version::is_niagara_plus());
3535 match(ConP);
3536
3537 op_cost(5);
3538 // formats are generated automatically for constants and base registers
3539 format %{ %}
3540 interface(CONST_INTER);
3541 %}
3542
3543 // Pointer Immediate: 64-bit
3544 // From Niagara2 processors on a load should be better than materializing.
3545 operand immP_load() %{
3546 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3547 match(ConP);
3548
3549 op_cost(5);
3550 // formats are generated automatically for constants and base registers
3551 format %{ %}
3552 interface(CONST_INTER);
3553 %}
3554
3555 // Pointer Immediate: 64-bit
3556 operand immP_no_oop_cheap() %{
3557 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3558 match(ConP);
3559
3560 op_cost(5);
3561 // formats are generated automatically for constants and base registers
3562 format %{ %}
3563 interface(CONST_INTER);
3564 %}
3565 #endif
3566
3567 operand immP13() %{
3568 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3569 match(ConP);
3570 op_cost(0);
3571
3572 format %{ %}
3573 interface(CONST_INTER);
3574 %}
3575
3576 operand immP0() %{
3577 predicate(n->get_ptr() == 0);
3578 match(ConP);
3579 op_cost(0);
3580
3581 format %{ %}
3582 interface(CONST_INTER);
3583 %}
3584
3585 operand immP_poll() %{
3586 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3587 match(ConP);
3588
3589 // formats are generated automatically for constants and base registers
3590 format %{ %}
3591 interface(CONST_INTER);
3592 %}
3593
3594 // Pointer Immediate
3595 operand immN()
3596 %{
3597 match(ConN);
3598
3599 op_cost(10);
3600 format %{ %}
3601 interface(CONST_INTER);
3602 %}
3603
3604 operand immNKlass()
3605 %{
3606 match(ConNKlass);
3607
3608 op_cost(10);
3609 format %{ %}
3610 interface(CONST_INTER);
3611 %}
3612
3613 // NULL Pointer Immediate
3614 operand immN0()
3615 %{
3616 predicate(n->get_narrowcon() == 0);
3617 match(ConN);
3618
3619 op_cost(0);
3620 format %{ %}
3621 interface(CONST_INTER);
3622 %}
3623
3624 operand immL() %{
3625 match(ConL);
3626 op_cost(40);
3627 // formats are generated automatically for constants and base registers
3628 format %{ %}
3629 interface(CONST_INTER);
3630 %}
3631
3632 operand immL0() %{
3633 predicate(n->get_long() == 0L);
3634 match(ConL);
3635 op_cost(0);
3636 // formats are generated automatically for constants and base registers
3637 format %{ %}
3638 interface(CONST_INTER);
3639 %}
3640
3641 // Integer Immediate: 5-bit
3642 operand immL5() %{
3643 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3644 match(ConL);
3645 op_cost(0);
3646 format %{ %}
3647 interface(CONST_INTER);
3648 %}
3649
3650 // Long Immediate: 13-bit
3651 operand immL13() %{
3652 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3653 match(ConL);
3654 op_cost(0);
3655
3656 format %{ %}
3657 interface(CONST_INTER);
3658 %}
3659
3660 // Long Immediate: 13-bit minus 7
3661 operand immL13m7() %{
3662 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3663 match(ConL);
3664 op_cost(0);
3665
3666 format %{ %}
3667 interface(CONST_INTER);
3668 %}
3669
3670 // Long Immediate: low 32-bit mask
3671 operand immL_32bits() %{
3672 predicate(n->get_long() == 0xFFFFFFFFL);
3673 match(ConL);
3674 op_cost(0);
3675
3676 format %{ %}
3677 interface(CONST_INTER);
3678 %}
3679
3680 // Long Immediate: cheap (materialize in <= 3 instructions)
3681 operand immL_cheap() %{
3682 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3683 match(ConL);
3684 op_cost(0);
3685
3686 format %{ %}
3687 interface(CONST_INTER);
3688 %}
3689
3690 // Long Immediate: expensive (materialize in > 3 instructions)
3691 operand immL_expensive() %{
3692 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3693 match(ConL);
3694 op_cost(0);
3695
3696 format %{ %}
3697 interface(CONST_INTER);
3698 %}
3699
3700 // Double Immediate
3701 operand immD() %{
3702 match(ConD);
3703
3704 op_cost(40);
3705 format %{ %}
3706 interface(CONST_INTER);
3707 %}
3708
3709 operand immD0() %{
3710 #ifdef _LP64
3711 // on 64-bit architectures this comparision is faster
3712 predicate(jlong_cast(n->getd()) == 0);
3713 #else
3714 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3715 #endif
3716 match(ConD);
3717
3718 op_cost(0);
3719 format %{ %}
3720 interface(CONST_INTER);
3721 %}
3722
3723 // Float Immediate
3724 operand immF() %{
3725 match(ConF);
3726
3727 op_cost(20);
3728 format %{ %}
3729 interface(CONST_INTER);
3730 %}
3731
3732 // Float Immediate: 0
3733 operand immF0() %{
3734 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3735 match(ConF);
3736
3737 op_cost(0);
3738 format %{ %}
3739 interface(CONST_INTER);
3740 %}
3741
3742 // Integer Register Operands
3743 // Integer Register
3744 operand iRegI() %{
3745 constraint(ALLOC_IN_RC(int_reg));
3746 match(RegI);
3747
3748 match(notemp_iRegI);
3749 match(g1RegI);
3750 match(o0RegI);
3751 match(iRegIsafe);
3752
3753 format %{ %}
3754 interface(REG_INTER);
3755 %}
3756
3757 operand notemp_iRegI() %{
3758 constraint(ALLOC_IN_RC(notemp_int_reg));
3759 match(RegI);
3760
3761 match(o0RegI);
3762
3763 format %{ %}
3764 interface(REG_INTER);
3765 %}
3766
3767 operand o0RegI() %{
3768 constraint(ALLOC_IN_RC(o0_regI));
3769 match(iRegI);
3770
3771 format %{ %}
3772 interface(REG_INTER);
3773 %}
3774
3775 // Pointer Register
3776 operand iRegP() %{
3777 constraint(ALLOC_IN_RC(ptr_reg));
3778 match(RegP);
3779
3780 match(lock_ptr_RegP);
3781 match(g1RegP);
3782 match(g2RegP);
3783 match(g3RegP);
3784 match(g4RegP);
3785 match(i0RegP);
3786 match(o0RegP);
3787 match(o1RegP);
3788 match(l7RegP);
3789
3790 format %{ %}
3791 interface(REG_INTER);
3792 %}
3793
3794 operand sp_ptr_RegP() %{
3795 constraint(ALLOC_IN_RC(sp_ptr_reg));
3796 match(RegP);
3797 match(iRegP);
3798
3799 format %{ %}
3800 interface(REG_INTER);
3801 %}
3802
3803 operand lock_ptr_RegP() %{
3804 constraint(ALLOC_IN_RC(lock_ptr_reg));
3805 match(RegP);
3806 match(i0RegP);
3807 match(o0RegP);
3808 match(o1RegP);
3809 match(l7RegP);
3810
3811 format %{ %}
3812 interface(REG_INTER);
3813 %}
3814
3815 operand g1RegP() %{
3816 constraint(ALLOC_IN_RC(g1_regP));
3817 match(iRegP);
3818
3819 format %{ %}
3820 interface(REG_INTER);
3821 %}
3822
3823 operand g2RegP() %{
3824 constraint(ALLOC_IN_RC(g2_regP));
3825 match(iRegP);
3826
3827 format %{ %}
3828 interface(REG_INTER);
3829 %}
3830
3831 operand g3RegP() %{
3832 constraint(ALLOC_IN_RC(g3_regP));
3833 match(iRegP);
3834
3835 format %{ %}
3836 interface(REG_INTER);
3837 %}
3838
3839 operand g1RegI() %{
3840 constraint(ALLOC_IN_RC(g1_regI));
3841 match(iRegI);
3842
3843 format %{ %}
3844 interface(REG_INTER);
3845 %}
3846
3847 operand g3RegI() %{
3848 constraint(ALLOC_IN_RC(g3_regI));
3849 match(iRegI);
3850
3851 format %{ %}
3852 interface(REG_INTER);
3853 %}
3854
3855 operand g4RegI() %{
3856 constraint(ALLOC_IN_RC(g4_regI));
3857 match(iRegI);
3858
3859 format %{ %}
3860 interface(REG_INTER);
3861 %}
3862
3863 operand g4RegP() %{
3864 constraint(ALLOC_IN_RC(g4_regP));
3865 match(iRegP);
3866
3867 format %{ %}
3868 interface(REG_INTER);
3869 %}
3870
3871 operand i0RegP() %{
3872 constraint(ALLOC_IN_RC(i0_regP));
3873 match(iRegP);
3874
3875 format %{ %}
3876 interface(REG_INTER);
3877 %}
3878
3879 operand o0RegP() %{
3880 constraint(ALLOC_IN_RC(o0_regP));
3881 match(iRegP);
3882
3883 format %{ %}
3884 interface(REG_INTER);
3885 %}
3886
3887 operand o1RegP() %{
3888 constraint(ALLOC_IN_RC(o1_regP));
3889 match(iRegP);
3890
3891 format %{ %}
3892 interface(REG_INTER);
3893 %}
3894
3895 operand o2RegP() %{
3896 constraint(ALLOC_IN_RC(o2_regP));
3897 match(iRegP);
3898
3899 format %{ %}
3900 interface(REG_INTER);
3901 %}
3902
3903 operand o7RegP() %{
3904 constraint(ALLOC_IN_RC(o7_regP));
3905 match(iRegP);
3906
3907 format %{ %}
3908 interface(REG_INTER);
3909 %}
3910
3911 operand l7RegP() %{
3912 constraint(ALLOC_IN_RC(l7_regP));
3913 match(iRegP);
3914
3915 format %{ %}
3916 interface(REG_INTER);
3917 %}
3918
3919 operand o7RegI() %{
3920 constraint(ALLOC_IN_RC(o7_regI));
3921 match(iRegI);
3922
3923 format %{ %}
3924 interface(REG_INTER);
3925 %}
3926
3927 operand iRegN() %{
3928 constraint(ALLOC_IN_RC(int_reg));
3929 match(RegN);
3930
3931 format %{ %}
3932 interface(REG_INTER);
3933 %}
3934
3935 // Long Register
3936 operand iRegL() %{
3937 constraint(ALLOC_IN_RC(long_reg));
3938 match(RegL);
3939
3940 format %{ %}
3941 interface(REG_INTER);
3942 %}
3943
3944 operand o2RegL() %{
3945 constraint(ALLOC_IN_RC(o2_regL));
3946 match(iRegL);
3947
3948 format %{ %}
3949 interface(REG_INTER);
3950 %}
3951
3952 operand o7RegL() %{
3953 constraint(ALLOC_IN_RC(o7_regL));
3954 match(iRegL);
3955
3956 format %{ %}
3957 interface(REG_INTER);
3958 %}
3959
3960 operand g1RegL() %{
3961 constraint(ALLOC_IN_RC(g1_regL));
3962 match(iRegL);
3963
3964 format %{ %}
3965 interface(REG_INTER);
3966 %}
3967
3968 operand g3RegL() %{
3969 constraint(ALLOC_IN_RC(g3_regL));
3970 match(iRegL);
3971
3972 format %{ %}
3973 interface(REG_INTER);
3974 %}
3975
3976 // Int Register safe
3977 // This is 64bit safe
3978 operand iRegIsafe() %{
3979 constraint(ALLOC_IN_RC(long_reg));
3980
3981 match(iRegI);
3982
3983 format %{ %}
3984 interface(REG_INTER);
3985 %}
3986
3987 // Condition Code Flag Register
3988 operand flagsReg() %{
3989 constraint(ALLOC_IN_RC(int_flags));
3990 match(RegFlags);
3991
3992 format %{ "ccr" %} // both ICC and XCC
3993 interface(REG_INTER);
3994 %}
3995
3996 // Condition Code Register, unsigned comparisons.
3997 operand flagsRegU() %{
3998 constraint(ALLOC_IN_RC(int_flags));
3999 match(RegFlags);
4000
4001 format %{ "icc_U" %}
4002 interface(REG_INTER);
4003 %}
4004
4005 // Condition Code Register, pointer comparisons.
4006 operand flagsRegP() %{
4007 constraint(ALLOC_IN_RC(int_flags));
4008 match(RegFlags);
4009
4010 #ifdef _LP64
4011 format %{ "xcc_P" %}
4012 #else
4013 format %{ "icc_P" %}
4014 #endif
4015 interface(REG_INTER);
4016 %}
4017
4018 // Condition Code Register, long comparisons.
4019 operand flagsRegL() %{
4020 constraint(ALLOC_IN_RC(int_flags));
4021 match(RegFlags);
4022
4023 format %{ "xcc_L" %}
4024 interface(REG_INTER);
4025 %}
4026
4027 // Condition Code Register, floating comparisons, unordered same as "less".
4028 operand flagsRegF() %{
4029 constraint(ALLOC_IN_RC(float_flags));
4030 match(RegFlags);
4031 match(flagsRegF0);
4032
4033 format %{ %}
4034 interface(REG_INTER);
4035 %}
4036
4037 operand flagsRegF0() %{
4038 constraint(ALLOC_IN_RC(float_flag0));
4039 match(RegFlags);
4040
4041 format %{ %}
4042 interface(REG_INTER);
4043 %}
4044
4045
4046 // Condition Code Flag Register used by long compare
4047 operand flagsReg_long_LTGE() %{
4048 constraint(ALLOC_IN_RC(int_flags));
4049 match(RegFlags);
4050 format %{ "icc_LTGE" %}
4051 interface(REG_INTER);
4052 %}
4053 operand flagsReg_long_EQNE() %{
4054 constraint(ALLOC_IN_RC(int_flags));
4055 match(RegFlags);
4056 format %{ "icc_EQNE" %}
4057 interface(REG_INTER);
4058 %}
4059 operand flagsReg_long_LEGT() %{
4060 constraint(ALLOC_IN_RC(int_flags));
4061 match(RegFlags);
4062 format %{ "icc_LEGT" %}
4063 interface(REG_INTER);
4064 %}
4065
4066
4067 operand regD() %{
4068 constraint(ALLOC_IN_RC(dflt_reg));
4069 match(RegD);
4070
4071 match(regD_low);
4072
4073 format %{ %}
4074 interface(REG_INTER);
4075 %}
4076
4077 operand regF() %{
4078 constraint(ALLOC_IN_RC(sflt_reg));
4079 match(RegF);
4080
4081 format %{ %}
4082 interface(REG_INTER);
4083 %}
4084
4085 operand regD_low() %{
4086 constraint(ALLOC_IN_RC(dflt_low_reg));
4087 match(regD);
4088
4089 format %{ %}
4090 interface(REG_INTER);
4091 %}
4092
4093 // Special Registers
4094
4095 // Method Register
4096 operand inline_cache_regP(iRegP reg) %{
4097 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4098 match(reg);
4099 format %{ %}
4100 interface(REG_INTER);
4101 %}
4102
4103 operand interpreter_method_oop_regP(iRegP reg) %{
4104 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4105 match(reg);
4106 format %{ %}
4107 interface(REG_INTER);
4108 %}
4109
4110
4111 //----------Complex Operands---------------------------------------------------
4112 // Indirect Memory Reference
4113 operand indirect(sp_ptr_RegP reg) %{
4114 constraint(ALLOC_IN_RC(sp_ptr_reg));
4115 match(reg);
4116
4117 op_cost(100);
4118 format %{ "[$reg]" %}
4119 interface(MEMORY_INTER) %{
4120 base($reg);
4121 index(0x0);
4122 scale(0x0);
4123 disp(0x0);
4124 %}
4125 %}
4126
4127 // Indirect with simm13 Offset
4128 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4129 constraint(ALLOC_IN_RC(sp_ptr_reg));
4130 match(AddP reg offset);
4131
4132 op_cost(100);
4133 format %{ "[$reg + $offset]" %}
4134 interface(MEMORY_INTER) %{
4135 base($reg);
4136 index(0x0);
4137 scale(0x0);
4138 disp($offset);
4139 %}
4140 %}
4141
4142 // Indirect with simm13 Offset minus 7
4143 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4144 constraint(ALLOC_IN_RC(sp_ptr_reg));
4145 match(AddP reg offset);
4146
4147 op_cost(100);
4148 format %{ "[$reg + $offset]" %}
4149 interface(MEMORY_INTER) %{
4150 base($reg);
4151 index(0x0);
4152 scale(0x0);
4153 disp($offset);
4154 %}
4155 %}
4156
4157 // Note: Intel has a swapped version also, like this:
4158 //operand indOffsetX(iRegI reg, immP offset) %{
4159 // constraint(ALLOC_IN_RC(int_reg));
4160 // match(AddP offset reg);
4161 //
4162 // op_cost(100);
4163 // format %{ "[$reg + $offset]" %}
4164 // interface(MEMORY_INTER) %{
4165 // base($reg);
4166 // index(0x0);
4167 // scale(0x0);
4168 // disp($offset);
4169 // %}
4170 //%}
4171 //// However, it doesn't make sense for SPARC, since
4172 // we have no particularly good way to embed oops in
4173 // single instructions.
4174
4175 // Indirect with Register Index
4176 operand indIndex(iRegP addr, iRegX index) %{
4177 constraint(ALLOC_IN_RC(ptr_reg));
4178 match(AddP addr index);
4179
4180 op_cost(100);
4181 format %{ "[$addr + $index]" %}
4182 interface(MEMORY_INTER) %{
4183 base($addr);
4184 index($index);
4185 scale(0x0);
4186 disp(0x0);
4187 %}
4188 %}
4189
4190 //----------Special Memory Operands--------------------------------------------
4191 // Stack Slot Operand - This operand is used for loading and storing temporary
4192 // values on the stack where a match requires a value to
4193 // flow through memory.
4194 operand stackSlotI(sRegI reg) %{
4195 constraint(ALLOC_IN_RC(stack_slots));
4196 op_cost(100);
4197 //match(RegI);
4198 format %{ "[$reg]" %}
4199 interface(MEMORY_INTER) %{
4200 base(0xE); // R_SP
4201 index(0x0);
4202 scale(0x0);
4203 disp($reg); // Stack Offset
4204 %}
4205 %}
4206
4207 operand stackSlotP(sRegP reg) %{
4208 constraint(ALLOC_IN_RC(stack_slots));
4209 op_cost(100);
4210 //match(RegP);
4211 format %{ "[$reg]" %}
4212 interface(MEMORY_INTER) %{
4213 base(0xE); // R_SP
4214 index(0x0);
4215 scale(0x0);
4216 disp($reg); // Stack Offset
4217 %}
4218 %}
4219
4220 operand stackSlotF(sRegF reg) %{
4221 constraint(ALLOC_IN_RC(stack_slots));
4222 op_cost(100);
4223 //match(RegF);
4224 format %{ "[$reg]" %}
4225 interface(MEMORY_INTER) %{
4226 base(0xE); // R_SP
4227 index(0x0);
4228 scale(0x0);
4229 disp($reg); // Stack Offset
4230 %}
4231 %}
4232 operand stackSlotD(sRegD reg) %{
4233 constraint(ALLOC_IN_RC(stack_slots));
4234 op_cost(100);
4235 //match(RegD);
4236 format %{ "[$reg]" %}
4237 interface(MEMORY_INTER) %{
4238 base(0xE); // R_SP
4239 index(0x0);
4240 scale(0x0);
4241 disp($reg); // Stack Offset
4242 %}
4243 %}
4244 operand stackSlotL(sRegL reg) %{
4245 constraint(ALLOC_IN_RC(stack_slots));
4246 op_cost(100);
4247 //match(RegL);
4248 format %{ "[$reg]" %}
4249 interface(MEMORY_INTER) %{
4250 base(0xE); // R_SP
4251 index(0x0);
4252 scale(0x0);
4253 disp($reg); // Stack Offset
4254 %}
4255 %}
4256
4257 // Operands for expressing Control Flow
4258 // NOTE: Label is a predefined operand which should not be redefined in
4259 // the AD file. It is generically handled within the ADLC.
4260
4261 //----------Conditional Branch Operands----------------------------------------
4262 // Comparison Op - This is the operation of the comparison, and is limited to
4263 // the following set of codes:
4264 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4265 //
4266 // Other attributes of the comparison, such as unsignedness, are specified
4267 // by the comparison instruction that sets a condition code flags register.
4268 // That result is represented by a flags operand whose subtype is appropriate
4269 // to the unsignedness (etc.) of the comparison.
4270 //
4271 // Later, the instruction which matches both the Comparison Op (a Bool) and
4272 // the flags (produced by the Cmp) specifies the coding of the comparison op
4273 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4274
4275 operand cmpOp() %{
4276 match(Bool);
4277
4278 format %{ "" %}
4279 interface(COND_INTER) %{
4280 equal(0x1);
4281 not_equal(0x9);
4282 less(0x3);
4283 greater_equal(0xB);
4284 less_equal(0x2);
4285 greater(0xA);
4286 overflow(0x7);
4287 no_overflow(0xF);
4288 %}
4289 %}
4290
4291 // Comparison Op, unsigned
4292 operand cmpOpU() %{
4293 match(Bool);
4294 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4295 n->as_Bool()->_test._test != BoolTest::no_overflow);
4296
4297 format %{ "u" %}
4298 interface(COND_INTER) %{
4299 equal(0x1);
4300 not_equal(0x9);
4301 less(0x5);
4302 greater_equal(0xD);
4303 less_equal(0x4);
4304 greater(0xC);
4305 overflow(0x7);
4306 no_overflow(0xF);
4307 %}
4308 %}
4309
4310 // Comparison Op, pointer (same as unsigned)
4311 operand cmpOpP() %{
4312 match(Bool);
4313 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4314 n->as_Bool()->_test._test != BoolTest::no_overflow);
4315
4316 format %{ "p" %}
4317 interface(COND_INTER) %{
4318 equal(0x1);
4319 not_equal(0x9);
4320 less(0x5);
4321 greater_equal(0xD);
4322 less_equal(0x4);
4323 greater(0xC);
4324 overflow(0x7);
4325 no_overflow(0xF);
4326 %}
4327 %}
4328
4329 // Comparison Op, branch-register encoding
4330 operand cmpOp_reg() %{
4331 match(Bool);
4332 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4333 n->as_Bool()->_test._test != BoolTest::no_overflow);
4334
4335 format %{ "" %}
4336 interface(COND_INTER) %{
4337 equal (0x1);
4338 not_equal (0x5);
4339 less (0x3);
4340 greater_equal(0x7);
4341 less_equal (0x2);
4342 greater (0x6);
4343 overflow(0x7); // not supported
4344 no_overflow(0xF); // not supported
4345 %}
4346 %}
4347
4348 // Comparison Code, floating, unordered same as less
4349 operand cmpOpF() %{
4350 match(Bool);
4351 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4352 n->as_Bool()->_test._test != BoolTest::no_overflow);
4353
4354 format %{ "fl" %}
4355 interface(COND_INTER) %{
4356 equal(0x9);
4357 not_equal(0x1);
4358 less(0x3);
4359 greater_equal(0xB);
4360 less_equal(0xE);
4361 greater(0x6);
4362
4363 overflow(0x7); // not supported
4364 no_overflow(0xF); // not supported
4365 %}
4366 %}
4367
4368 // Used by long compare
4369 operand cmpOp_commute() %{
4370 match(Bool);
4371 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4372 n->as_Bool()->_test._test != BoolTest::no_overflow);
4373
4374 format %{ "" %}
4375 interface(COND_INTER) %{
4376 equal(0x1);
4377 not_equal(0x9);
4378 less(0xA);
4379 greater_equal(0x2);
4380 less_equal(0xB);
4381 greater(0x3);
4382 overflow(0x7);
4383 no_overflow(0xF);
4384 %}
4385 %}
4386
4387 //----------OPERAND CLASSES----------------------------------------------------
4388 // Operand Classes are groups of operands that are used to simplify
4389 // instruction definitions by not requiring the AD writer to specify separate
4390 // instructions for every form of operand when the instruction accepts
4391 // multiple operand types with the same basic encoding and format. The classic
4392 // case of this is memory operands.
4393 opclass memory( indirect, indOffset13, indIndex );
4394 opclass indIndexMemory( indIndex );
4395
4396 //----------PIPELINE-----------------------------------------------------------
4397 pipeline %{
4398
4399 //----------ATTRIBUTES---------------------------------------------------------
4400 attributes %{
4401 fixed_size_instructions; // Fixed size instructions
4402 branch_has_delay_slot; // Branch has delay slot following
4403 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4404 instruction_unit_size = 4; // An instruction is 4 bytes long
4405 instruction_fetch_unit_size = 16; // The processor fetches one line
4406 instruction_fetch_units = 1; // of 16 bytes
4407
4408 // List of nop instructions
4409 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4410 %}
4411
4412 //----------RESOURCES----------------------------------------------------------
4413 // Resources are the functional units available to the machine
4414 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4415
4416 //----------PIPELINE DESCRIPTION-----------------------------------------------
4417 // Pipeline Description specifies the stages in the machine's pipeline
4418
4419 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4420
4421 //----------PIPELINE CLASSES---------------------------------------------------
4422 // Pipeline Classes describe the stages in which input and output are
4423 // referenced by the hardware pipeline.
4424
4425 // Integer ALU reg-reg operation
4426 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4427 single_instruction;
4428 dst : E(write);
4429 src1 : R(read);
4430 src2 : R(read);
4431 IALU : R;
4432 %}
4433
4434 // Integer ALU reg-reg long operation
4435 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4436 instruction_count(2);
4437 dst : E(write);
4438 src1 : R(read);
4439 src2 : R(read);
4440 IALU : R;
4441 IALU : R;
4442 %}
4443
4444 // Integer ALU reg-reg long dependent operation
4445 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4446 instruction_count(1); multiple_bundles;
4447 dst : E(write);
4448 src1 : R(read);
4449 src2 : R(read);
4450 cr : E(write);
4451 IALU : R(2);
4452 %}
4453
4454 // Integer ALU reg-imm operaion
4455 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4456 single_instruction;
4457 dst : E(write);
4458 src1 : R(read);
4459 IALU : R;
4460 %}
4461
4462 // Integer ALU reg-reg operation with condition code
4463 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4464 single_instruction;
4465 dst : E(write);
4466 cr : E(write);
4467 src1 : R(read);
4468 src2 : R(read);
4469 IALU : R;
4470 %}
4471
4472 // Integer ALU reg-imm operation with condition code
4473 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4474 single_instruction;
4475 dst : E(write);
4476 cr : E(write);
4477 src1 : R(read);
4478 IALU : R;
4479 %}
4480
4481 // Integer ALU zero-reg operation
4482 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4483 single_instruction;
4484 dst : E(write);
4485 src2 : R(read);
4486 IALU : R;
4487 %}
4488
4489 // Integer ALU zero-reg operation with condition code only
4490 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4491 single_instruction;
4492 cr : E(write);
4493 src : R(read);
4494 IALU : R;
4495 %}
4496
4497 // Integer ALU reg-reg operation with condition code only
4498 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4499 single_instruction;
4500 cr : E(write);
4501 src1 : R(read);
4502 src2 : R(read);
4503 IALU : R;
4504 %}
4505
4506 // Integer ALU reg-imm operation with condition code only
4507 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4508 single_instruction;
4509 cr : E(write);
4510 src1 : R(read);
4511 IALU : R;
4512 %}
4513
4514 // Integer ALU reg-reg-zero operation with condition code only
4515 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4516 single_instruction;
4517 cr : E(write);
4518 src1 : R(read);
4519 src2 : R(read);
4520 IALU : R;
4521 %}
4522
4523 // Integer ALU reg-imm-zero operation with condition code only
4524 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4525 single_instruction;
4526 cr : E(write);
4527 src1 : R(read);
4528 IALU : R;
4529 %}
4530
4531 // Integer ALU reg-reg operation with condition code, src1 modified
4532 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4533 single_instruction;
4534 cr : E(write);
4535 src1 : E(write);
4536 src1 : R(read);
4537 src2 : R(read);
4538 IALU : R;
4539 %}
4540
4541 // Integer ALU reg-imm operation with condition code, src1 modified
4542 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4543 single_instruction;
4544 cr : E(write);
4545 src1 : E(write);
4546 src1 : R(read);
4547 IALU : R;
4548 %}
4549
4550 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4551 multiple_bundles;
4552 dst : E(write)+4;
4553 cr : E(write);
4554 src1 : R(read);
4555 src2 : R(read);
4556 IALU : R(3);
4557 BR : R(2);
4558 %}
4559
4560 // Integer ALU operation
4561 pipe_class ialu_none(iRegI dst) %{
4562 single_instruction;
4563 dst : E(write);
4564 IALU : R;
4565 %}
4566
4567 // Integer ALU reg operation
4568 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4569 single_instruction; may_have_no_code;
4570 dst : E(write);
4571 src : R(read);
4572 IALU : R;
4573 %}
4574
4575 // Integer ALU reg conditional operation
4576 // This instruction has a 1 cycle stall, and cannot execute
4577 // in the same cycle as the instruction setting the condition
4578 // code. We kludge this by pretending to read the condition code
4579 // 1 cycle earlier, and by marking the functional units as busy
4580 // for 2 cycles with the result available 1 cycle later than
4581 // is really the case.
4582 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4583 single_instruction;
4584 op2_out : C(write);
4585 op1 : R(read);
4586 cr : R(read); // This is really E, with a 1 cycle stall
4587 BR : R(2);
4588 MS : R(2);
4589 %}
4590
4591 #ifdef _LP64
4592 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4593 instruction_count(1); multiple_bundles;
4594 dst : C(write)+1;
4595 src : R(read)+1;
4596 IALU : R(1);
4597 BR : E(2);
4598 MS : E(2);
4599 %}
4600 #endif
4601
4602 // Integer ALU reg operation
4603 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4604 single_instruction; may_have_no_code;
4605 dst : E(write);
4606 src : R(read);
4607 IALU : R;
4608 %}
4609 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4610 single_instruction; may_have_no_code;
4611 dst : E(write);
4612 src : R(read);
4613 IALU : R;
4614 %}
4615
4616 // Two integer ALU reg operations
4617 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4618 instruction_count(2);
4619 dst : E(write);
4620 src : R(read);
4621 A0 : R;
4622 A1 : R;
4623 %}
4624
4625 // Two integer ALU reg operations
4626 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4627 instruction_count(2); may_have_no_code;
4628 dst : E(write);
4629 src : R(read);
4630 A0 : R;
4631 A1 : R;
4632 %}
4633
4634 // Integer ALU imm operation
4635 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4636 single_instruction;
4637 dst : E(write);
4638 IALU : R;
4639 %}
4640
4641 // Integer ALU reg-reg with carry operation
4642 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4643 single_instruction;
4644 dst : E(write);
4645 src1 : R(read);
4646 src2 : R(read);
4647 IALU : R;
4648 %}
4649
4650 // Integer ALU cc operation
4651 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4652 single_instruction;
4653 dst : E(write);
4654 cc : R(read);
4655 IALU : R;
4656 %}
4657
4658 // Integer ALU cc / second IALU operation
4659 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4660 instruction_count(1); multiple_bundles;
4661 dst : E(write)+1;
4662 src : R(read);
4663 IALU : R;
4664 %}
4665
4666 // Integer ALU cc / second IALU operation
4667 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4668 instruction_count(1); multiple_bundles;
4669 dst : E(write)+1;
4670 p : R(read);
4671 q : R(read);
4672 IALU : R;
4673 %}
4674
4675 // Integer ALU hi-lo-reg operation
4676 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4677 instruction_count(1); multiple_bundles;
4678 dst : E(write)+1;
4679 IALU : R(2);
4680 %}
4681
4682 // Float ALU hi-lo-reg operation (with temp)
4683 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4684 instruction_count(1); multiple_bundles;
4685 dst : E(write)+1;
4686 IALU : R(2);
4687 %}
4688
4689 // Long Constant
4690 pipe_class loadConL( iRegL dst, immL src ) %{
4691 instruction_count(2); multiple_bundles;
4692 dst : E(write)+1;
4693 IALU : R(2);
4694 IALU : R(2);
4695 %}
4696
4697 // Pointer Constant
4698 pipe_class loadConP( iRegP dst, immP src ) %{
4699 instruction_count(0); multiple_bundles;
4700 fixed_latency(6);
4701 %}
4702
4703 // Polling Address
4704 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4705 #ifdef _LP64
4706 instruction_count(0); multiple_bundles;
4707 fixed_latency(6);
4708 #else
4709 dst : E(write);
4710 IALU : R;
4711 #endif
4712 %}
4713
4714 // Long Constant small
4715 pipe_class loadConLlo( iRegL dst, immL src ) %{
4716 instruction_count(2);
4717 dst : E(write);
4718 IALU : R;
4719 IALU : R;
4720 %}
4721
4722 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4723 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4724 instruction_count(1); multiple_bundles;
4725 src : R(read);
4726 dst : M(write)+1;
4727 IALU : R;
4728 MS : E;
4729 %}
4730
4731 // Integer ALU nop operation
4732 pipe_class ialu_nop() %{
4733 single_instruction;
4734 IALU : R;
4735 %}
4736
4737 // Integer ALU nop operation
4738 pipe_class ialu_nop_A0() %{
4739 single_instruction;
4740 A0 : R;
4741 %}
4742
4743 // Integer ALU nop operation
4744 pipe_class ialu_nop_A1() %{
4745 single_instruction;
4746 A1 : R;
4747 %}
4748
4749 // Integer Multiply reg-reg operation
4750 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4751 single_instruction;
4752 dst : E(write);
4753 src1 : R(read);
4754 src2 : R(read);
4755 MS : R(5);
4756 %}
4757
4758 // Integer Multiply reg-imm operation
4759 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4760 single_instruction;
4761 dst : E(write);
4762 src1 : R(read);
4763 MS : R(5);
4764 %}
4765
4766 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4767 single_instruction;
4768 dst : E(write)+4;
4769 src1 : R(read);
4770 src2 : R(read);
4771 MS : R(6);
4772 %}
4773
4774 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4775 single_instruction;
4776 dst : E(write)+4;
4777 src1 : R(read);
4778 MS : R(6);
4779 %}
4780
4781 // Integer Divide reg-reg
4782 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4783 instruction_count(1); multiple_bundles;
4784 dst : E(write);
4785 temp : E(write);
4786 src1 : R(read);
4787 src2 : R(read);
4788 temp : R(read);
4789 MS : R(38);
4790 %}
4791
4792 // Integer Divide reg-imm
4793 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4794 instruction_count(1); multiple_bundles;
4795 dst : E(write);
4796 temp : E(write);
4797 src1 : R(read);
4798 temp : R(read);
4799 MS : R(38);
4800 %}
4801
4802 // Long Divide
4803 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4804 dst : E(write)+71;
4805 src1 : R(read);
4806 src2 : R(read)+1;
4807 MS : R(70);
4808 %}
4809
4810 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4811 dst : E(write)+71;
4812 src1 : R(read);
4813 MS : R(70);
4814 %}
4815
4816 // Floating Point Add Float
4817 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4818 single_instruction;
4819 dst : X(write);
4820 src1 : E(read);
4821 src2 : E(read);
4822 FA : R;
4823 %}
4824
4825 // Floating Point Add Double
4826 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4827 single_instruction;
4828 dst : X(write);
4829 src1 : E(read);
4830 src2 : E(read);
4831 FA : R;
4832 %}
4833
4834 // Floating Point Conditional Move based on integer flags
4835 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4836 single_instruction;
4837 dst : X(write);
4838 src : E(read);
4839 cr : R(read);
4840 FA : R(2);
4841 BR : R(2);
4842 %}
4843
4844 // Floating Point Conditional Move based on integer flags
4845 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4846 single_instruction;
4847 dst : X(write);
4848 src : E(read);
4849 cr : R(read);
4850 FA : R(2);
4851 BR : R(2);
4852 %}
4853
4854 // Floating Point Multiply Float
4855 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4856 single_instruction;
4857 dst : X(write);
4858 src1 : E(read);
4859 src2 : E(read);
4860 FM : R;
4861 %}
4862
4863 // Floating Point Multiply Double
4864 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4865 single_instruction;
4866 dst : X(write);
4867 src1 : E(read);
4868 src2 : E(read);
4869 FM : R;
4870 %}
4871
4872 // Floating Point Divide Float
4873 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4874 single_instruction;
4875 dst : X(write);
4876 src1 : E(read);
4877 src2 : E(read);
4878 FM : R;
4879 FDIV : C(14);
4880 %}
4881
4882 // Floating Point Divide Double
4883 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4884 single_instruction;
4885 dst : X(write);
4886 src1 : E(read);
4887 src2 : E(read);
4888 FM : R;
4889 FDIV : C(17);
4890 %}
4891
4892 // Floating Point Move/Negate/Abs Float
4893 pipe_class faddF_reg(regF dst, regF src) %{
4894 single_instruction;
4895 dst : W(write);
4896 src : E(read);
4897 FA : R(1);
4898 %}
4899
4900 // Floating Point Move/Negate/Abs Double
4901 pipe_class faddD_reg(regD dst, regD src) %{
4902 single_instruction;
4903 dst : W(write);
4904 src : E(read);
4905 FA : R;
4906 %}
4907
4908 // Floating Point Convert F->D
4909 pipe_class fcvtF2D(regD dst, regF src) %{
4910 single_instruction;
4911 dst : X(write);
4912 src : E(read);
4913 FA : R;
4914 %}
4915
4916 // Floating Point Convert I->D
4917 pipe_class fcvtI2D(regD dst, regF src) %{
4918 single_instruction;
4919 dst : X(write);
4920 src : E(read);
4921 FA : R;
4922 %}
4923
4924 // Floating Point Convert LHi->D
4925 pipe_class fcvtLHi2D(regD dst, regD src) %{
4926 single_instruction;
4927 dst : X(write);
4928 src : E(read);
4929 FA : R;
4930 %}
4931
4932 // Floating Point Convert L->D
4933 pipe_class fcvtL2D(regD dst, regF src) %{
4934 single_instruction;
4935 dst : X(write);
4936 src : E(read);
4937 FA : R;
4938 %}
4939
4940 // Floating Point Convert L->F
4941 pipe_class fcvtL2F(regD dst, regF src) %{
4942 single_instruction;
4943 dst : X(write);
4944 src : E(read);
4945 FA : R;
4946 %}
4947
4948 // Floating Point Convert D->F
4949 pipe_class fcvtD2F(regD dst, regF src) %{
4950 single_instruction;
4951 dst : X(write);
4952 src : E(read);
4953 FA : R;
4954 %}
4955
4956 // Floating Point Convert I->L
4957 pipe_class fcvtI2L(regD dst, regF src) %{
4958 single_instruction;
4959 dst : X(write);
4960 src : E(read);
4961 FA : R;
4962 %}
4963
4964 // Floating Point Convert D->F
4965 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4966 instruction_count(1); multiple_bundles;
4967 dst : X(write)+6;
4968 src : E(read);
4969 FA : R;
4970 %}
4971
4972 // Floating Point Convert D->L
4973 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4974 instruction_count(1); multiple_bundles;
4975 dst : X(write)+6;
4976 src : E(read);
4977 FA : R;
4978 %}
4979
4980 // Floating Point Convert F->I
4981 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4982 instruction_count(1); multiple_bundles;
4983 dst : X(write)+6;
4984 src : E(read);
4985 FA : R;
4986 %}
4987
4988 // Floating Point Convert F->L
4989 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4990 instruction_count(1); multiple_bundles;
4991 dst : X(write)+6;
4992 src : E(read);
4993 FA : R;
4994 %}
4995
4996 // Floating Point Convert I->F
4997 pipe_class fcvtI2F(regF dst, regF src) %{
4998 single_instruction;
4999 dst : X(write);
5000 src : E(read);
5001 FA : R;
5002 %}
5003
5004 // Floating Point Compare
5005 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
5006 single_instruction;
5007 cr : X(write);
5008 src1 : E(read);
5009 src2 : E(read);
5010 FA : R;
5011 %}
5012
5013 // Floating Point Compare
5014 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5015 single_instruction;
5016 cr : X(write);
5017 src1 : E(read);
5018 src2 : E(read);
5019 FA : R;
5020 %}
5021
5022 // Floating Add Nop
5023 pipe_class fadd_nop() %{
5024 single_instruction;
5025 FA : R;
5026 %}
5027
5028 // Integer Store to Memory
5029 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5030 single_instruction;
5031 mem : R(read);
5032 src : C(read);
5033 MS : R;
5034 %}
5035
5036 // Integer Store to Memory
5037 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5038 single_instruction;
5039 mem : R(read);
5040 src : C(read);
5041 MS : R;
5042 %}
5043
5044 // Integer Store Zero to Memory
5045 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5046 single_instruction;
5047 mem : R(read);
5048 MS : R;
5049 %}
5050
5051 // Special Stack Slot Store
5052 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5053 single_instruction;
5054 stkSlot : R(read);
5055 src : C(read);
5056 MS : R;
5057 %}
5058
5059 // Special Stack Slot Store
5060 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5061 instruction_count(2); multiple_bundles;
5062 stkSlot : R(read);
5063 src : C(read);
5064 MS : R(2);
5065 %}
5066
5067 // Float Store
5068 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5069 single_instruction;
5070 mem : R(read);
5071 src : C(read);
5072 MS : R;
5073 %}
5074
5075 // Float Store
5076 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5077 single_instruction;
5078 mem : R(read);
5079 MS : R;
5080 %}
5081
5082 // Double Store
5083 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5084 instruction_count(1);
5085 mem : R(read);
5086 src : C(read);
5087 MS : R;
5088 %}
5089
5090 // Double Store
5091 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5092 single_instruction;
5093 mem : R(read);
5094 MS : R;
5095 %}
5096
5097 // Special Stack Slot Float Store
5098 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5099 single_instruction;
5100 stkSlot : R(read);
5101 src : C(read);
5102 MS : R;
5103 %}
5104
5105 // Special Stack Slot Double Store
5106 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5107 single_instruction;
5108 stkSlot : R(read);
5109 src : C(read);
5110 MS : R;
5111 %}
5112
5113 // Integer Load (when sign bit propagation not needed)
5114 pipe_class iload_mem(iRegI dst, memory mem) %{
5115 single_instruction;
5116 mem : R(read);
5117 dst : C(write);
5118 MS : R;
5119 %}
5120
5121 // Integer Load from stack operand
5122 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5123 single_instruction;
5124 mem : R(read);
5125 dst : C(write);
5126 MS : R;
5127 %}
5128
5129 // Integer Load (when sign bit propagation or masking is needed)
5130 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5131 single_instruction;
5132 mem : R(read);
5133 dst : M(write);
5134 MS : R;
5135 %}
5136
5137 // Float Load
5138 pipe_class floadF_mem(regF dst, memory mem) %{
5139 single_instruction;
5140 mem : R(read);
5141 dst : M(write);
5142 MS : R;
5143 %}
5144
5145 // Float Load
5146 pipe_class floadD_mem(regD dst, memory mem) %{
5147 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5148 mem : R(read);
5149 dst : M(write);
5150 MS : R;
5151 %}
5152
5153 // Float Load
5154 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5155 single_instruction;
5156 stkSlot : R(read);
5157 dst : M(write);
5158 MS : R;
5159 %}
5160
5161 // Float Load
5162 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5163 single_instruction;
5164 stkSlot : R(read);
5165 dst : M(write);
5166 MS : R;
5167 %}
5168
5169 // Memory Nop
5170 pipe_class mem_nop() %{
5171 single_instruction;
5172 MS : R;
5173 %}
5174
5175 pipe_class sethi(iRegP dst, immI src) %{
5176 single_instruction;
5177 dst : E(write);
5178 IALU : R;
5179 %}
5180
5181 pipe_class loadPollP(iRegP poll) %{
5182 single_instruction;
5183 poll : R(read);
5184 MS : R;
5185 %}
5186
5187 pipe_class br(Universe br, label labl) %{
5188 single_instruction_with_delay_slot;
5189 BR : R;
5190 %}
5191
5192 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5193 single_instruction_with_delay_slot;
5194 cr : E(read);
5195 BR : R;
5196 %}
5197
5198 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5199 single_instruction_with_delay_slot;
5200 op1 : E(read);
5201 BR : R;
5202 MS : R;
5203 %}
5204
5205 // Compare and branch
5206 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5207 instruction_count(2); has_delay_slot;
5208 cr : E(write);
5209 src1 : R(read);
5210 src2 : R(read);
5211 IALU : R;
5212 BR : R;
5213 %}
5214
5215 // Compare and branch
5216 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5217 instruction_count(2); has_delay_slot;
5218 cr : E(write);
5219 src1 : R(read);
5220 IALU : R;
5221 BR : R;
5222 %}
5223
5224 // Compare and branch using cbcond
5225 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5226 single_instruction;
5227 src1 : E(read);
5228 src2 : E(read);
5229 IALU : R;
5230 BR : R;
5231 %}
5232
5233 // Compare and branch using cbcond
5234 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5235 single_instruction;
5236 src1 : E(read);
5237 IALU : R;
5238 BR : R;
5239 %}
5240
5241 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5242 single_instruction_with_delay_slot;
5243 cr : E(read);
5244 BR : R;
5245 %}
5246
5247 pipe_class br_nop() %{
5248 single_instruction;
5249 BR : R;
5250 %}
5251
5252 pipe_class simple_call(method meth) %{
5253 instruction_count(2); multiple_bundles; force_serialization;
5254 fixed_latency(100);
5255 BR : R(1);
5256 MS : R(1);
5257 A0 : R(1);
5258 %}
5259
5260 pipe_class compiled_call(method meth) %{
5261 instruction_count(1); multiple_bundles; force_serialization;
5262 fixed_latency(100);
5263 MS : R(1);
5264 %}
5265
5266 pipe_class call(method meth) %{
5267 instruction_count(0); multiple_bundles; force_serialization;
5268 fixed_latency(100);
5269 %}
5270
5271 pipe_class tail_call(Universe ignore, label labl) %{
5272 single_instruction; has_delay_slot;
5273 fixed_latency(100);
5274 BR : R(1);
5275 MS : R(1);
5276 %}
5277
5278 pipe_class ret(Universe ignore) %{
5279 single_instruction; has_delay_slot;
5280 BR : R(1);
5281 MS : R(1);
5282 %}
5283
5284 pipe_class ret_poll(g3RegP poll) %{
5285 instruction_count(3); has_delay_slot;
5286 poll : E(read);
5287 MS : R;
5288 %}
5289
5290 // The real do-nothing guy
5291 pipe_class empty( ) %{
5292 instruction_count(0);
5293 %}
5294
5295 pipe_class long_memory_op() %{
5296 instruction_count(0); multiple_bundles; force_serialization;
5297 fixed_latency(25);
5298 MS : R(1);
5299 %}
5300
5301 // Check-cast
5302 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5303 array : R(read);
5304 match : R(read);
5305 IALU : R(2);
5306 BR : R(2);
5307 MS : R;
5308 %}
5309
5310 // Convert FPU flags into +1,0,-1
5311 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5312 src1 : E(read);
5313 src2 : E(read);
5314 dst : E(write);
5315 FA : R;
5316 MS : R(2);
5317 BR : R(2);
5318 %}
5319
5320 // Compare for p < q, and conditionally add y
5321 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5322 p : E(read);
5323 q : E(read);
5324 y : E(read);
5325 IALU : R(3)
5326 %}
5327
5328 // Perform a compare, then move conditionally in a branch delay slot.
5329 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5330 src2 : E(read);
5331 srcdst : E(read);
5332 IALU : R;
5333 BR : R;
5334 %}
5335
5336 // Define the class for the Nop node
5337 define %{
5338 MachNop = ialu_nop;
5339 %}
5340
5341 %}
5342
5343 //----------INSTRUCTIONS-------------------------------------------------------
5344
5345 //------------Special Stack Slot instructions - no match rules-----------------
5346 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5347 // No match rule to avoid chain rule match.
5348 effect(DEF dst, USE src);
5349 ins_cost(MEMORY_REF_COST);
5350 size(4);
5351 format %{ "LDF $src,$dst\t! stkI to regF" %}
5352 opcode(Assembler::ldf_op3);
5353 ins_encode(simple_form3_mem_reg(src, dst));
5354 ins_pipe(floadF_stk);
5355 %}
5356
5357 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5358 // No match rule to avoid chain rule match.
5359 effect(DEF dst, USE src);
5360 ins_cost(MEMORY_REF_COST);
5361 size(4);
5362 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5363 opcode(Assembler::lddf_op3);
5364 ins_encode(simple_form3_mem_reg(src, dst));
5365 ins_pipe(floadD_stk);
5366 %}
5367
5368 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5369 // No match rule to avoid chain rule match.
5370 effect(DEF dst, USE src);
5371 ins_cost(MEMORY_REF_COST);
5372 size(4);
5373 format %{ "STF $src,$dst\t! regF to stkI" %}
5374 opcode(Assembler::stf_op3);
5375 ins_encode(simple_form3_mem_reg(dst, src));
5376 ins_pipe(fstoreF_stk_reg);
5377 %}
5378
5379 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5380 // No match rule to avoid chain rule match.
5381 effect(DEF dst, USE src);
5382 ins_cost(MEMORY_REF_COST);
5383 size(4);
5384 format %{ "STDF $src,$dst\t! regD to stkL" %}
5385 opcode(Assembler::stdf_op3);
5386 ins_encode(simple_form3_mem_reg(dst, src));
5387 ins_pipe(fstoreD_stk_reg);
5388 %}
5389
5390 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5391 effect(DEF dst, USE src);
5392 ins_cost(MEMORY_REF_COST*2);
5393 size(8);
5394 format %{ "STW $src,$dst.hi\t! long\n\t"
5395 "STW R_G0,$dst.lo" %}
5396 opcode(Assembler::stw_op3);
5397 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5398 ins_pipe(lstoreI_stk_reg);
5399 %}
5400
5401 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5402 // No match rule to avoid chain rule match.
5403 effect(DEF dst, USE src);
5404 ins_cost(MEMORY_REF_COST);
5405 size(4);
5406 format %{ "STX $src,$dst\t! regL to stkD" %}
5407 opcode(Assembler::stx_op3);
5408 ins_encode(simple_form3_mem_reg( dst, src ) );
5409 ins_pipe(istore_stk_reg);
5410 %}
5411
5412 //---------- Chain stack slots between similar types --------
5413
5414 // Load integer from stack slot
5415 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5416 match(Set dst src);
5417 ins_cost(MEMORY_REF_COST);
5418
5419 size(4);
5420 format %{ "LDUW $src,$dst\t!stk" %}
5421 opcode(Assembler::lduw_op3);
5422 ins_encode(simple_form3_mem_reg( src, dst ) );
5423 ins_pipe(iload_mem);
5424 %}
5425
5426 // Store integer to stack slot
5427 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5428 match(Set dst src);
5429 ins_cost(MEMORY_REF_COST);
5430
5431 size(4);
5432 format %{ "STW $src,$dst\t!stk" %}
5433 opcode(Assembler::stw_op3);
5434 ins_encode(simple_form3_mem_reg( dst, src ) );
5435 ins_pipe(istore_mem_reg);
5436 %}
5437
5438 // Load long from stack slot
5439 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5440 match(Set dst src);
5441
5442 ins_cost(MEMORY_REF_COST);
5443 size(4);
5444 format %{ "LDX $src,$dst\t! long" %}
5445 opcode(Assembler::ldx_op3);
5446 ins_encode(simple_form3_mem_reg( src, dst ) );
5447 ins_pipe(iload_mem);
5448 %}
5449
5450 // Store long to stack slot
5451 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5452 match(Set dst src);
5453
5454 ins_cost(MEMORY_REF_COST);
5455 size(4);
5456 format %{ "STX $src,$dst\t! long" %}
5457 opcode(Assembler::stx_op3);
5458 ins_encode(simple_form3_mem_reg( dst, src ) );
5459 ins_pipe(istore_mem_reg);
5460 %}
5461
5462 #ifdef _LP64
5463 // Load pointer from stack slot, 64-bit encoding
5464 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5465 match(Set dst src);
5466 ins_cost(MEMORY_REF_COST);
5467 size(4);
5468 format %{ "LDX $src,$dst\t!ptr" %}
5469 opcode(Assembler::ldx_op3);
5470 ins_encode(simple_form3_mem_reg( src, dst ) );
5471 ins_pipe(iload_mem);
5472 %}
5473
5474 // Store pointer to stack slot
5475 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5476 match(Set dst src);
5477 ins_cost(MEMORY_REF_COST);
5478 size(4);
5479 format %{ "STX $src,$dst\t!ptr" %}
5480 opcode(Assembler::stx_op3);
5481 ins_encode(simple_form3_mem_reg( dst, src ) );
5482 ins_pipe(istore_mem_reg);
5483 %}
5484 #else // _LP64
5485 // Load pointer from stack slot, 32-bit encoding
5486 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5487 match(Set dst src);
5488 ins_cost(MEMORY_REF_COST);
5489 format %{ "LDUW $src,$dst\t!ptr" %}
5490 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5491 ins_encode(simple_form3_mem_reg( src, dst ) );
5492 ins_pipe(iload_mem);
5493 %}
5494
5495 // Store pointer to stack slot
5496 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5497 match(Set dst src);
5498 ins_cost(MEMORY_REF_COST);
5499 format %{ "STW $src,$dst\t!ptr" %}
5500 opcode(Assembler::stw_op3, Assembler::ldst_op);
5501 ins_encode(simple_form3_mem_reg( dst, src ) );
5502 ins_pipe(istore_mem_reg);
5503 %}
5504 #endif // _LP64
5505
5506 //------------Special Nop instructions for bundling - no match rules-----------
5507 // Nop using the A0 functional unit
5508 instruct Nop_A0() %{
5509 ins_cost(0);
5510
5511 format %{ "NOP ! Alu Pipeline" %}
5512 opcode(Assembler::or_op3, Assembler::arith_op);
5513 ins_encode( form2_nop() );
5514 ins_pipe(ialu_nop_A0);
5515 %}
5516
5517 // Nop using the A1 functional unit
5518 instruct Nop_A1( ) %{
5519 ins_cost(0);
5520
5521 format %{ "NOP ! Alu Pipeline" %}
5522 opcode(Assembler::or_op3, Assembler::arith_op);
5523 ins_encode( form2_nop() );
5524 ins_pipe(ialu_nop_A1);
5525 %}
5526
5527 // Nop using the memory functional unit
5528 instruct Nop_MS( ) %{
5529 ins_cost(0);
5530
5531 format %{ "NOP ! Memory Pipeline" %}
5532 ins_encode( emit_mem_nop );
5533 ins_pipe(mem_nop);
5534 %}
5535
5536 // Nop using the floating add functional unit
5537 instruct Nop_FA( ) %{
5538 ins_cost(0);
5539
5540 format %{ "NOP ! Floating Add Pipeline" %}
5541 ins_encode( emit_fadd_nop );
5542 ins_pipe(fadd_nop);
5543 %}
5544
5545 // Nop using the branch functional unit
5546 instruct Nop_BR( ) %{
5547 ins_cost(0);
5548
5549 format %{ "NOP ! Branch Pipeline" %}
5550 ins_encode( emit_br_nop );
5551 ins_pipe(br_nop);
5552 %}
5553
5554 //----------Load/Store/Move Instructions---------------------------------------
5555 //----------Load Instructions--------------------------------------------------
5556 // Load Byte (8bit signed)
5557 instruct loadB(iRegI dst, memory mem) %{
5558 match(Set dst (LoadB mem));
5559 ins_cost(MEMORY_REF_COST);
5560
5561 size(4);
5562 format %{ "LDSB $mem,$dst\t! byte" %}
5563 ins_encode %{
5564 __ ldsb($mem$$Address, $dst$$Register);
5565 %}
5566 ins_pipe(iload_mask_mem);
5567 %}
5568
5569 // Load Byte (8bit signed) into a Long Register
5570 instruct loadB2L(iRegL dst, memory mem) %{
5571 match(Set dst (ConvI2L (LoadB mem)));
5572 ins_cost(MEMORY_REF_COST);
5573
5574 size(4);
5575 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5576 ins_encode %{
5577 __ ldsb($mem$$Address, $dst$$Register);
5578 %}
5579 ins_pipe(iload_mask_mem);
5580 %}
5581
5582 // Load Unsigned Byte (8bit UNsigned) into an int reg
5583 instruct loadUB(iRegI dst, memory mem) %{
5584 match(Set dst (LoadUB mem));
5585 ins_cost(MEMORY_REF_COST);
5586
5587 size(4);
5588 format %{ "LDUB $mem,$dst\t! ubyte" %}
5589 ins_encode %{
5590 __ ldub($mem$$Address, $dst$$Register);
5591 %}
5592 ins_pipe(iload_mem);
5593 %}
5594
5595 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5596 instruct loadUB2L(iRegL dst, memory mem) %{
5597 match(Set dst (ConvI2L (LoadUB mem)));
5598 ins_cost(MEMORY_REF_COST);
5599
5600 size(4);
5601 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5602 ins_encode %{
5603 __ ldub($mem$$Address, $dst$$Register);
5604 %}
5605 ins_pipe(iload_mem);
5606 %}
5607
5608 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5609 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5610 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5611 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5612
5613 size(2*4);
5614 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5615 "AND $dst,$mask,$dst" %}
5616 ins_encode %{
5617 __ ldub($mem$$Address, $dst$$Register);
5618 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5619 %}
5620 ins_pipe(iload_mem);
5621 %}
5622
5623 // Load Short (16bit signed)
5624 instruct loadS(iRegI dst, memory mem) %{
5625 match(Set dst (LoadS mem));
5626 ins_cost(MEMORY_REF_COST);
5627
5628 size(4);
5629 format %{ "LDSH $mem,$dst\t! short" %}
5630 ins_encode %{
5631 __ ldsh($mem$$Address, $dst$$Register);
5632 %}
5633 ins_pipe(iload_mask_mem);
5634 %}
5635
5636 // Load Short (16 bit signed) to Byte (8 bit signed)
5637 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5638 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5639 ins_cost(MEMORY_REF_COST);
5640
5641 size(4);
5642
5643 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5644 ins_encode %{
5645 __ ldsb($mem$$Address, $dst$$Register, 1);
5646 %}
5647 ins_pipe(iload_mask_mem);
5648 %}
5649
5650 // Load Short (16bit signed) into a Long Register
5651 instruct loadS2L(iRegL dst, memory mem) %{
5652 match(Set dst (ConvI2L (LoadS mem)));
5653 ins_cost(MEMORY_REF_COST);
5654
5655 size(4);
5656 format %{ "LDSH $mem,$dst\t! short -> long" %}
5657 ins_encode %{
5658 __ ldsh($mem$$Address, $dst$$Register);
5659 %}
5660 ins_pipe(iload_mask_mem);
5661 %}
5662
5663 // Load Unsigned Short/Char (16bit UNsigned)
5664 instruct loadUS(iRegI dst, memory mem) %{
5665 match(Set dst (LoadUS mem));
5666 ins_cost(MEMORY_REF_COST);
5667
5668 size(4);
5669 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5670 ins_encode %{
5671 __ lduh($mem$$Address, $dst$$Register);
5672 %}
5673 ins_pipe(iload_mem);
5674 %}
5675
5676 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5677 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5678 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5679 ins_cost(MEMORY_REF_COST);
5680
5681 size(4);
5682 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5683 ins_encode %{
5684 __ ldsb($mem$$Address, $dst$$Register, 1);
5685 %}
5686 ins_pipe(iload_mask_mem);
5687 %}
5688
5689 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5690 instruct loadUS2L(iRegL dst, memory mem) %{
5691 match(Set dst (ConvI2L (LoadUS mem)));
5692 ins_cost(MEMORY_REF_COST);
5693
5694 size(4);
5695 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5696 ins_encode %{
5697 __ lduh($mem$$Address, $dst$$Register);
5698 %}
5699 ins_pipe(iload_mem);
5700 %}
5701
5702 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5703 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5704 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5705 ins_cost(MEMORY_REF_COST);
5706
5707 size(4);
5708 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5709 ins_encode %{
5710 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5711 %}
5712 ins_pipe(iload_mem);
5713 %}
5714
5715 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5716 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5717 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5718 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5719
5720 size(2*4);
5721 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5722 "AND $dst,$mask,$dst" %}
5723 ins_encode %{
5724 Register Rdst = $dst$$Register;
5725 __ lduh($mem$$Address, Rdst);
5726 __ and3(Rdst, $mask$$constant, Rdst);
5727 %}
5728 ins_pipe(iload_mem);
5729 %}
5730
5731 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5732 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5733 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5734 effect(TEMP dst, TEMP tmp);
5735 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5736
5737 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5738 "SET $mask,$tmp\n\t"
5739 "AND $dst,$tmp,$dst" %}
5740 ins_encode %{
5741 Register Rdst = $dst$$Register;
5742 Register Rtmp = $tmp$$Register;
5743 __ lduh($mem$$Address, Rdst);
5744 __ set($mask$$constant, Rtmp);
5745 __ and3(Rdst, Rtmp, Rdst);
5746 %}
5747 ins_pipe(iload_mem);
5748 %}
5749
5750 // Load Integer
5751 instruct loadI(iRegI dst, memory mem) %{
5752 match(Set dst (LoadI mem));
5753 ins_cost(MEMORY_REF_COST);
5754
5755 size(4);
5756 format %{ "LDUW $mem,$dst\t! int" %}
5757 ins_encode %{
5758 __ lduw($mem$$Address, $dst$$Register);
5759 %}
5760 ins_pipe(iload_mem);
5761 %}
5762
5763 // Load Integer to Byte (8 bit signed)
5764 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5765 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5766 ins_cost(MEMORY_REF_COST);
5767
5768 size(4);
5769
5770 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5771 ins_encode %{
5772 __ ldsb($mem$$Address, $dst$$Register, 3);
5773 %}
5774 ins_pipe(iload_mask_mem);
5775 %}
5776
5777 // Load Integer to Unsigned Byte (8 bit UNsigned)
5778 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5779 match(Set dst (AndI (LoadI mem) mask));
5780 ins_cost(MEMORY_REF_COST);
5781
5782 size(4);
5783
5784 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5785 ins_encode %{
5786 __ ldub($mem$$Address, $dst$$Register, 3);
5787 %}
5788 ins_pipe(iload_mask_mem);
5789 %}
5790
5791 // Load Integer to Short (16 bit signed)
5792 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5793 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5794 ins_cost(MEMORY_REF_COST);
5795
5796 size(4);
5797
5798 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5799 ins_encode %{
5800 __ ldsh($mem$$Address, $dst$$Register, 2);
5801 %}
5802 ins_pipe(iload_mask_mem);
5803 %}
5804
5805 // Load Integer to Unsigned Short (16 bit UNsigned)
5806 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5807 match(Set dst (AndI (LoadI mem) mask));
5808 ins_cost(MEMORY_REF_COST);
5809
5810 size(4);
5811
5812 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5813 ins_encode %{
5814 __ lduh($mem$$Address, $dst$$Register, 2);
5815 %}
5816 ins_pipe(iload_mask_mem);
5817 %}
5818
5819 // Load Integer into a Long Register
5820 instruct loadI2L(iRegL dst, memory mem) %{
5821 match(Set dst (ConvI2L (LoadI mem)));
5822 ins_cost(MEMORY_REF_COST);
5823
5824 size(4);
5825 format %{ "LDSW $mem,$dst\t! int -> long" %}
5826 ins_encode %{
5827 __ ldsw($mem$$Address, $dst$$Register);
5828 %}
5829 ins_pipe(iload_mask_mem);
5830 %}
5831
5832 // Load Integer with mask 0xFF into a Long Register
5833 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5834 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5835 ins_cost(MEMORY_REF_COST);
5836
5837 size(4);
5838 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5839 ins_encode %{
5840 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5841 %}
5842 ins_pipe(iload_mem);
5843 %}
5844
5845 // Load Integer with mask 0xFFFF into a Long Register
5846 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5847 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5848 ins_cost(MEMORY_REF_COST);
5849
5850 size(4);
5851 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5852 ins_encode %{
5853 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5854 %}
5855 ins_pipe(iload_mem);
5856 %}
5857
5858 // Load Integer with a 12-bit mask into a Long Register
5859 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5860 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5861 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5862
5863 size(2*4);
5864 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5865 "AND $dst,$mask,$dst" %}
5866 ins_encode %{
5867 Register Rdst = $dst$$Register;
5868 __ lduw($mem$$Address, Rdst);
5869 __ and3(Rdst, $mask$$constant, Rdst);
5870 %}
5871 ins_pipe(iload_mem);
5872 %}
5873
5874 // Load Integer with a 31-bit mask into a Long Register
5875 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5876 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5877 effect(TEMP dst, TEMP tmp);
5878 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5879
5880 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5881 "SET $mask,$tmp\n\t"
5882 "AND $dst,$tmp,$dst" %}
5883 ins_encode %{
5884 Register Rdst = $dst$$Register;
5885 Register Rtmp = $tmp$$Register;
5886 __ lduw($mem$$Address, Rdst);
5887 __ set($mask$$constant, Rtmp);
5888 __ and3(Rdst, Rtmp, Rdst);
5889 %}
5890 ins_pipe(iload_mem);
5891 %}
5892
5893 // Load Unsigned Integer into a Long Register
5894 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5895 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5896 ins_cost(MEMORY_REF_COST);
5897
5898 size(4);
5899 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5900 ins_encode %{
5901 __ lduw($mem$$Address, $dst$$Register);
5902 %}
5903 ins_pipe(iload_mem);
5904 %}
5905
5906 // Load Long - aligned
5907 instruct loadL(iRegL dst, memory mem ) %{
5908 match(Set dst (LoadL mem));
5909 ins_cost(MEMORY_REF_COST);
5910
5911 size(4);
5912 format %{ "LDX $mem,$dst\t! long" %}
5913 ins_encode %{
5914 __ ldx($mem$$Address, $dst$$Register);
5915 %}
5916 ins_pipe(iload_mem);
5917 %}
5918
5919 // Load Long - UNaligned
5920 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5921 match(Set dst (LoadL_unaligned mem));
5922 effect(KILL tmp);
5923 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5924 size(16);
5925 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5926 "\tLDUW $mem ,$dst\n"
5927 "\tSLLX #32, $dst, $dst\n"
5928 "\tOR $dst, R_O7, $dst" %}
5929 opcode(Assembler::lduw_op3);
5930 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5931 ins_pipe(iload_mem);
5932 %}
5933
5934 // Load Range
5935 instruct loadRange(iRegI dst, memory mem) %{
5936 match(Set dst (LoadRange mem));
5937 ins_cost(MEMORY_REF_COST);
5938
5939 size(4);
5940 format %{ "LDUW $mem,$dst\t! range" %}
5941 opcode(Assembler::lduw_op3);
5942 ins_encode(simple_form3_mem_reg( mem, dst ) );
5943 ins_pipe(iload_mem);
5944 %}
5945
5946 // Load Integer into %f register (for fitos/fitod)
5947 instruct loadI_freg(regF dst, memory mem) %{
5948 match(Set dst (LoadI mem));
5949 ins_cost(MEMORY_REF_COST);
5950 size(4);
5951
5952 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5953 opcode(Assembler::ldf_op3);
5954 ins_encode(simple_form3_mem_reg( mem, dst ) );
5955 ins_pipe(floadF_mem);
5956 %}
5957
5958 // Load Pointer
5959 instruct loadP(iRegP dst, memory mem) %{
5960 match(Set dst (LoadP mem));
5961 ins_cost(MEMORY_REF_COST);
5962 size(4);
5963
5964 #ifndef _LP64
5965 format %{ "LDUW $mem,$dst\t! ptr" %}
5966 ins_encode %{
5967 __ lduw($mem$$Address, $dst$$Register);
5968 %}
5969 #else
5970 format %{ "LDX $mem,$dst\t! ptr" %}
5971 ins_encode %{
5972 __ ldx($mem$$Address, $dst$$Register);
5973 %}
5974 #endif
5975 ins_pipe(iload_mem);
5976 %}
5977
5978 // Load Compressed Pointer
5979 instruct loadN(iRegN dst, memory mem) %{
5980 match(Set dst (LoadN mem));
5981 ins_cost(MEMORY_REF_COST);
5982 size(4);
5983
5984 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5985 ins_encode %{
5986 __ lduw($mem$$Address, $dst$$Register);
5987 %}
5988 ins_pipe(iload_mem);
5989 %}
5990
5991 // Load Klass Pointer
5992 instruct loadKlass(iRegP dst, memory mem) %{
5993 match(Set dst (LoadKlass mem));
5994 ins_cost(MEMORY_REF_COST);
5995 size(4);
5996
5997 #ifndef _LP64
5998 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5999 ins_encode %{
6000 __ lduw($mem$$Address, $dst$$Register);
6001 %}
6002 #else
6003 format %{ "LDX $mem,$dst\t! klass ptr" %}
6004 ins_encode %{
6005 __ ldx($mem$$Address, $dst$$Register);
6006 %}
6007 #endif
6008 ins_pipe(iload_mem);
6009 %}
6010
6011 // Load narrow Klass Pointer
6012 instruct loadNKlass(iRegN dst, memory mem) %{
6013 match(Set dst (LoadNKlass mem));
6014 ins_cost(MEMORY_REF_COST);
6015 size(4);
6016
6017 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6018 ins_encode %{
6019 __ lduw($mem$$Address, $dst$$Register);
6020 %}
6021 ins_pipe(iload_mem);
6022 %}
6023
6024 // Load Double
6025 instruct loadD(regD dst, memory mem) %{
6026 match(Set dst (LoadD mem));
6027 ins_cost(MEMORY_REF_COST);
6028
6029 size(4);
6030 format %{ "LDDF $mem,$dst" %}
6031 opcode(Assembler::lddf_op3);
6032 ins_encode(simple_form3_mem_reg( mem, dst ) );
6033 ins_pipe(floadD_mem);
6034 %}
6035
6036 // Load Double - UNaligned
6037 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6038 match(Set dst (LoadD_unaligned mem));
6039 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6040 size(8);
6041 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6042 "\tLDF $mem+4,$dst.lo\t!" %}
6043 opcode(Assembler::ldf_op3);
6044 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6045 ins_pipe(iload_mem);
6046 %}
6047
6048 // Load Float
6049 instruct loadF(regF dst, memory mem) %{
6050 match(Set dst (LoadF mem));
6051 ins_cost(MEMORY_REF_COST);
6052
6053 size(4);
6054 format %{ "LDF $mem,$dst" %}
6055 opcode(Assembler::ldf_op3);
6056 ins_encode(simple_form3_mem_reg( mem, dst ) );
6057 ins_pipe(floadF_mem);
6058 %}
6059
6060 // Load Constant
6061 instruct loadConI( iRegI dst, immI src ) %{
6062 match(Set dst src);
6063 ins_cost(DEFAULT_COST * 3/2);
6064 format %{ "SET $src,$dst" %}
6065 ins_encode( Set32(src, dst) );
6066 ins_pipe(ialu_hi_lo_reg);
6067 %}
6068
6069 instruct loadConI13( iRegI dst, immI13 src ) %{
6070 match(Set dst src);
6071
6072 size(4);
6073 format %{ "MOV $src,$dst" %}
6074 ins_encode( Set13( src, dst ) );
6075 ins_pipe(ialu_imm);
6076 %}
6077
6078 #ifndef _LP64
6079 instruct loadConP(iRegP dst, immP con) %{
6080 match(Set dst con);
6081 ins_cost(DEFAULT_COST * 3/2);
6082 format %{ "SET $con,$dst\t!ptr" %}
6083 ins_encode %{
6084 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6085 intptr_t val = $con$$constant;
6086 if (constant_reloc == relocInfo::oop_type) {
6087 __ set_oop_constant((jobject) val, $dst$$Register);
6088 } else if (constant_reloc == relocInfo::metadata_type) {
6089 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6090 } else { // non-oop pointers, e.g. card mark base, heap top
6091 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6092 __ set(val, $dst$$Register);
6093 }
6094 %}
6095 ins_pipe(loadConP);
6096 %}
6097 #else
6098 instruct loadConP_set(iRegP dst, immP_set con) %{
6099 match(Set dst con);
6100 ins_cost(DEFAULT_COST * 3/2);
6101 format %{ "SET $con,$dst\t! ptr" %}
6102 ins_encode %{
6103 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6104 intptr_t val = $con$$constant;
6105 if (constant_reloc == relocInfo::oop_type) {
6106 __ set_oop_constant((jobject) val, $dst$$Register);
6107 } else if (constant_reloc == relocInfo::metadata_type) {
6108 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6109 } else { // non-oop pointers, e.g. card mark base, heap top
6110 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6111 __ set(val, $dst$$Register);
6112 }
6113 %}
6114 ins_pipe(loadConP);
6115 %}
6116
6117 instruct loadConP_load(iRegP dst, immP_load con) %{
6118 match(Set dst con);
6119 ins_cost(MEMORY_REF_COST);
6120 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6121 ins_encode %{
6122 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6123 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6124 %}
6125 ins_pipe(loadConP);
6126 %}
6127
6128 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6129 match(Set dst con);
6130 ins_cost(DEFAULT_COST * 3/2);
6131 format %{ "SET $con,$dst\t! non-oop ptr" %}
6132 ins_encode %{
6133 __ set($con$$constant, $dst$$Register);
6134 %}
6135 ins_pipe(loadConP);
6136 %}
6137 #endif // _LP64
6138
6139 instruct loadConP0(iRegP dst, immP0 src) %{
6140 match(Set dst src);
6141
6142 size(4);
6143 format %{ "CLR $dst\t!ptr" %}
6144 ins_encode %{
6145 __ clr($dst$$Register);
6146 %}
6147 ins_pipe(ialu_imm);
6148 %}
6149
6150 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6151 match(Set dst src);
6152 ins_cost(DEFAULT_COST);
6153 format %{ "SET $src,$dst\t!ptr" %}
6154 ins_encode %{
6155 AddressLiteral polling_page(os::get_polling_page());
6156 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6157 %}
6158 ins_pipe(loadConP_poll);
6159 %}
6160
6161 instruct loadConN0(iRegN dst, immN0 src) %{
6162 match(Set dst src);
6163
6164 size(4);
6165 format %{ "CLR $dst\t! compressed NULL ptr" %}
6166 ins_encode %{
6167 __ clr($dst$$Register);
6168 %}
6169 ins_pipe(ialu_imm);
6170 %}
6171
6172 instruct loadConN(iRegN dst, immN src) %{
6173 match(Set dst src);
6174 ins_cost(DEFAULT_COST * 3/2);
6175 format %{ "SET $src,$dst\t! compressed ptr" %}
6176 ins_encode %{
6177 Register dst = $dst$$Register;
6178 __ set_narrow_oop((jobject)$src$$constant, dst);
6179 %}
6180 ins_pipe(ialu_hi_lo_reg);
6181 %}
6182
6183 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6184 match(Set dst src);
6185 ins_cost(DEFAULT_COST * 3/2);
6186 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6187 ins_encode %{
6188 Register dst = $dst$$Register;
6189 __ set_narrow_klass((Klass*)$src$$constant, dst);
6190 %}
6191 ins_pipe(ialu_hi_lo_reg);
6192 %}
6193
6194 // Materialize long value (predicated by immL_cheap).
6195 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6196 match(Set dst con);
6197 effect(KILL tmp);
6198 ins_cost(DEFAULT_COST * 3);
6199 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6200 ins_encode %{
6201 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6202 %}
6203 ins_pipe(loadConL);
6204 %}
6205
6206 // Load long value from constant table (predicated by immL_expensive).
6207 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6208 match(Set dst con);
6209 ins_cost(MEMORY_REF_COST);
6210 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6211 ins_encode %{
6212 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6213 __ ldx($constanttablebase, con_offset, $dst$$Register);
6214 %}
6215 ins_pipe(loadConL);
6216 %}
6217
6218 instruct loadConL0( iRegL dst, immL0 src ) %{
6219 match(Set dst src);
6220 ins_cost(DEFAULT_COST);
6221 size(4);
6222 format %{ "CLR $dst\t! long" %}
6223 ins_encode( Set13( src, dst ) );
6224 ins_pipe(ialu_imm);
6225 %}
6226
6227 instruct loadConL13( iRegL dst, immL13 src ) %{
6228 match(Set dst src);
6229 ins_cost(DEFAULT_COST * 2);
6230
6231 size(4);
6232 format %{ "MOV $src,$dst\t! long" %}
6233 ins_encode( Set13( src, dst ) );
6234 ins_pipe(ialu_imm);
6235 %}
6236
6237 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6238 match(Set dst con);
6239 effect(KILL tmp);
6240 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6241 ins_encode %{
6242 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6243 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6244 %}
6245 ins_pipe(loadConFD);
6246 %}
6247
6248 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6249 match(Set dst con);
6250 effect(KILL tmp);
6251 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6252 ins_encode %{
6253 // XXX This is a quick fix for 6833573.
6254 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6255 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6256 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6257 %}
6258 ins_pipe(loadConFD);
6259 %}
6260
6261 // Prefetch instructions.
6262 // Must be safe to execute with invalid address (cannot fault).
6263
6264 instruct prefetchr( memory mem ) %{
6265 match( PrefetchRead mem );
6266 ins_cost(MEMORY_REF_COST);
6267 size(4);
6268
6269 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6270 opcode(Assembler::prefetch_op3);
6271 ins_encode( form3_mem_prefetch_read( mem ) );
6272 ins_pipe(iload_mem);
6273 %}
6274
6275 instruct prefetchw( memory mem ) %{
6276 match( PrefetchWrite mem );
6277 ins_cost(MEMORY_REF_COST);
6278 size(4);
6279
6280 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6281 opcode(Assembler::prefetch_op3);
6282 ins_encode( form3_mem_prefetch_write( mem ) );
6283 ins_pipe(iload_mem);
6284 %}
6285
6286 // Prefetch instructions for allocation.
6287
6288 instruct prefetchAlloc( memory mem ) %{
6289 predicate(AllocatePrefetchInstr == 0);
6290 match( PrefetchAllocation mem );
6291 ins_cost(MEMORY_REF_COST);
6292 size(4);
6293
6294 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6295 opcode(Assembler::prefetch_op3);
6296 ins_encode( form3_mem_prefetch_write( mem ) );
6297 ins_pipe(iload_mem);
6298 %}
6299
6300 // Use BIS instruction to prefetch for allocation.
6301 // Could fault, need space at the end of TLAB.
6302 instruct prefetchAlloc_bis( iRegP dst ) %{
6303 predicate(AllocatePrefetchInstr == 1);
6304 match( PrefetchAllocation dst );
6305 ins_cost(MEMORY_REF_COST);
6306 size(4);
6307
6308 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6309 ins_encode %{
6310 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6311 %}
6312 ins_pipe(istore_mem_reg);
6313 %}
6314
6315 // Next code is used for finding next cache line address to prefetch.
6316 #ifndef _LP64
6317 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6318 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6319 ins_cost(DEFAULT_COST);
6320 size(4);
6321
6322 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6323 ins_encode %{
6324 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6325 %}
6326 ins_pipe(ialu_reg_imm);
6327 %}
6328 #else
6329 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6330 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6331 ins_cost(DEFAULT_COST);
6332 size(4);
6333
6334 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6335 ins_encode %{
6336 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6337 %}
6338 ins_pipe(ialu_reg_imm);
6339 %}
6340 #endif
6341
6342 //----------Store Instructions-------------------------------------------------
6343 // Store Byte
6344 instruct storeB(memory mem, iRegI src) %{
6345 match(Set mem (StoreB mem src));
6346 ins_cost(MEMORY_REF_COST);
6347
6348 size(4);
6349 format %{ "STB $src,$mem\t! byte" %}
6350 opcode(Assembler::stb_op3);
6351 ins_encode(simple_form3_mem_reg( mem, src ) );
6352 ins_pipe(istore_mem_reg);
6353 %}
6354
6355 instruct storeB0(memory mem, immI0 src) %{
6356 match(Set mem (StoreB mem src));
6357 ins_cost(MEMORY_REF_COST);
6358
6359 size(4);
6360 format %{ "STB $src,$mem\t! byte" %}
6361 opcode(Assembler::stb_op3);
6362 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6363 ins_pipe(istore_mem_zero);
6364 %}
6365
6366 instruct storeCM0(memory mem, immI0 src) %{
6367 match(Set mem (StoreCM mem src));
6368 ins_cost(MEMORY_REF_COST);
6369
6370 size(4);
6371 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6372 opcode(Assembler::stb_op3);
6373 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6374 ins_pipe(istore_mem_zero);
6375 %}
6376
6377 // Store Char/Short
6378 instruct storeC(memory mem, iRegI src) %{
6379 match(Set mem (StoreC mem src));
6380 ins_cost(MEMORY_REF_COST);
6381
6382 size(4);
6383 format %{ "STH $src,$mem\t! short" %}
6384 opcode(Assembler::sth_op3);
6385 ins_encode(simple_form3_mem_reg( mem, src ) );
6386 ins_pipe(istore_mem_reg);
6387 %}
6388
6389 instruct storeC0(memory mem, immI0 src) %{
6390 match(Set mem (StoreC mem src));
6391 ins_cost(MEMORY_REF_COST);
6392
6393 size(4);
6394 format %{ "STH $src,$mem\t! short" %}
6395 opcode(Assembler::sth_op3);
6396 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6397 ins_pipe(istore_mem_zero);
6398 %}
6399
6400 // Store Integer
6401 instruct storeI(memory mem, iRegI src) %{
6402 match(Set mem (StoreI mem src));
6403 ins_cost(MEMORY_REF_COST);
6404
6405 size(4);
6406 format %{ "STW $src,$mem" %}
6407 opcode(Assembler::stw_op3);
6408 ins_encode(simple_form3_mem_reg( mem, src ) );
6409 ins_pipe(istore_mem_reg);
6410 %}
6411
6412 // Store Long
6413 instruct storeL(memory mem, iRegL src) %{
6414 match(Set mem (StoreL mem src));
6415 ins_cost(MEMORY_REF_COST);
6416 size(4);
6417 format %{ "STX $src,$mem\t! long" %}
6418 opcode(Assembler::stx_op3);
6419 ins_encode(simple_form3_mem_reg( mem, src ) );
6420 ins_pipe(istore_mem_reg);
6421 %}
6422
6423 instruct storeI0(memory mem, immI0 src) %{
6424 match(Set mem (StoreI mem src));
6425 ins_cost(MEMORY_REF_COST);
6426
6427 size(4);
6428 format %{ "STW $src,$mem" %}
6429 opcode(Assembler::stw_op3);
6430 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6431 ins_pipe(istore_mem_zero);
6432 %}
6433
6434 instruct storeL0(memory mem, immL0 src) %{
6435 match(Set mem (StoreL mem src));
6436 ins_cost(MEMORY_REF_COST);
6437
6438 size(4);
6439 format %{ "STX $src,$mem" %}
6440 opcode(Assembler::stx_op3);
6441 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6442 ins_pipe(istore_mem_zero);
6443 %}
6444
6445 // Store Integer from float register (used after fstoi)
6446 instruct storeI_Freg(memory mem, regF src) %{
6447 match(Set mem (StoreI mem src));
6448 ins_cost(MEMORY_REF_COST);
6449
6450 size(4);
6451 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6452 opcode(Assembler::stf_op3);
6453 ins_encode(simple_form3_mem_reg( mem, src ) );
6454 ins_pipe(fstoreF_mem_reg);
6455 %}
6456
6457 // Store Pointer
6458 instruct storeP(memory dst, sp_ptr_RegP src) %{
6459 match(Set dst (StoreP dst src));
6460 ins_cost(MEMORY_REF_COST);
6461 size(4);
6462
6463 #ifndef _LP64
6464 format %{ "STW $src,$dst\t! ptr" %}
6465 opcode(Assembler::stw_op3, 0, REGP_OP);
6466 #else
6467 format %{ "STX $src,$dst\t! ptr" %}
6468 opcode(Assembler::stx_op3, 0, REGP_OP);
6469 #endif
6470 ins_encode( form3_mem_reg( dst, src ) );
6471 ins_pipe(istore_mem_spORreg);
6472 %}
6473
6474 instruct storeP0(memory dst, immP0 src) %{
6475 match(Set dst (StoreP dst src));
6476 ins_cost(MEMORY_REF_COST);
6477 size(4);
6478
6479 #ifndef _LP64
6480 format %{ "STW $src,$dst\t! ptr" %}
6481 opcode(Assembler::stw_op3, 0, REGP_OP);
6482 #else
6483 format %{ "STX $src,$dst\t! ptr" %}
6484 opcode(Assembler::stx_op3, 0, REGP_OP);
6485 #endif
6486 ins_encode( form3_mem_reg( dst, R_G0 ) );
6487 ins_pipe(istore_mem_zero);
6488 %}
6489
6490 // Store Compressed Pointer
6491 instruct storeN(memory dst, iRegN src) %{
6492 match(Set dst (StoreN dst src));
6493 ins_cost(MEMORY_REF_COST);
6494 size(4);
6495
6496 format %{ "STW $src,$dst\t! compressed ptr" %}
6497 ins_encode %{
6498 Register base = as_Register($dst$$base);
6499 Register index = as_Register($dst$$index);
6500 Register src = $src$$Register;
6501 if (index != G0) {
6502 __ stw(src, base, index);
6503 } else {
6504 __ stw(src, base, $dst$$disp);
6505 }
6506 %}
6507 ins_pipe(istore_mem_spORreg);
6508 %}
6509
6510 instruct storeNKlass(memory dst, iRegN src) %{
6511 match(Set dst (StoreNKlass dst src));
6512 ins_cost(MEMORY_REF_COST);
6513 size(4);
6514
6515 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6516 ins_encode %{
6517 Register base = as_Register($dst$$base);
6518 Register index = as_Register($dst$$index);
6519 Register src = $src$$Register;
6520 if (index != G0) {
6521 __ stw(src, base, index);
6522 } else {
6523 __ stw(src, base, $dst$$disp);
6524 }
6525 %}
6526 ins_pipe(istore_mem_spORreg);
6527 %}
6528
6529 instruct storeN0(memory dst, immN0 src) %{
6530 match(Set dst (StoreN dst src));
6531 ins_cost(MEMORY_REF_COST);
6532 size(4);
6533
6534 format %{ "STW $src,$dst\t! compressed ptr" %}
6535 ins_encode %{
6536 Register base = as_Register($dst$$base);
6537 Register index = as_Register($dst$$index);
6538 if (index != G0) {
6539 __ stw(0, base, index);
6540 } else {
6541 __ stw(0, base, $dst$$disp);
6542 }
6543 %}
6544 ins_pipe(istore_mem_zero);
6545 %}
6546
6547 // Store Double
6548 instruct storeD( memory mem, regD src) %{
6549 match(Set mem (StoreD mem src));
6550 ins_cost(MEMORY_REF_COST);
6551
6552 size(4);
6553 format %{ "STDF $src,$mem" %}
6554 opcode(Assembler::stdf_op3);
6555 ins_encode(simple_form3_mem_reg( mem, src ) );
6556 ins_pipe(fstoreD_mem_reg);
6557 %}
6558
6559 instruct storeD0( memory mem, immD0 src) %{
6560 match(Set mem (StoreD mem src));
6561 ins_cost(MEMORY_REF_COST);
6562
6563 size(4);
6564 format %{ "STX $src,$mem" %}
6565 opcode(Assembler::stx_op3);
6566 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6567 ins_pipe(fstoreD_mem_zero);
6568 %}
6569
6570 // Store Float
6571 instruct storeF( memory mem, regF src) %{
6572 match(Set mem (StoreF mem src));
6573 ins_cost(MEMORY_REF_COST);
6574
6575 size(4);
6576 format %{ "STF $src,$mem" %}
6577 opcode(Assembler::stf_op3);
6578 ins_encode(simple_form3_mem_reg( mem, src ) );
6579 ins_pipe(fstoreF_mem_reg);
6580 %}
6581
6582 instruct storeF0( memory mem, immF0 src) %{
6583 match(Set mem (StoreF mem src));
6584 ins_cost(MEMORY_REF_COST);
6585
6586 size(4);
6587 format %{ "STW $src,$mem\t! storeF0" %}
6588 opcode(Assembler::stw_op3);
6589 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6590 ins_pipe(fstoreF_mem_zero);
6591 %}
6592
6593 // Convert oop pointer into compressed form
6594 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6595 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6596 match(Set dst (EncodeP src));
6597 format %{ "encode_heap_oop $src, $dst" %}
6598 ins_encode %{
6599 __ encode_heap_oop($src$$Register, $dst$$Register);
6600 %}
6601 ins_pipe(ialu_reg);
6602 %}
6603
6604 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6605 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6606 match(Set dst (EncodeP src));
6607 format %{ "encode_heap_oop_not_null $src, $dst" %}
6608 ins_encode %{
6609 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6610 %}
6611 ins_pipe(ialu_reg);
6612 %}
6613
6614 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6615 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6616 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6617 match(Set dst (DecodeN src));
6618 format %{ "decode_heap_oop $src, $dst" %}
6619 ins_encode %{
6620 __ decode_heap_oop($src$$Register, $dst$$Register);
6621 %}
6622 ins_pipe(ialu_reg);
6623 %}
6624
6625 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6626 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6627 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6628 match(Set dst (DecodeN src));
6629 format %{ "decode_heap_oop_not_null $src, $dst" %}
6630 ins_encode %{
6631 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6632 %}
6633 ins_pipe(ialu_reg);
6634 %}
6635
6636 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6637 match(Set dst (EncodePKlass src));
6638 format %{ "encode_klass_not_null $src, $dst" %}
6639 ins_encode %{
6640 __ encode_klass_not_null($src$$Register, $dst$$Register);
6641 %}
6642 ins_pipe(ialu_reg);
6643 %}
6644
6645 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6646 match(Set dst (DecodeNKlass src));
6647 format %{ "decode_klass_not_null $src, $dst" %}
6648 ins_encode %{
6649 __ decode_klass_not_null($src$$Register, $dst$$Register);
6650 %}
6651 ins_pipe(ialu_reg);
6652 %}
6653
6654 //----------MemBar Instructions-----------------------------------------------
6655 // Memory barrier flavors
6656
6657 instruct membar_acquire() %{
6658 match(MemBarAcquire);
6659 match(LoadFence);
6660 ins_cost(4*MEMORY_REF_COST);
6661
6662 size(0);
6663 format %{ "MEMBAR-acquire" %}
6664 ins_encode( enc_membar_acquire );
6665 ins_pipe(long_memory_op);
6666 %}
6667
6668 instruct membar_acquire_lock() %{
6669 match(MemBarAcquireLock);
6670 ins_cost(0);
6671
6672 size(0);
6673 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6674 ins_encode( );
6675 ins_pipe(empty);
6676 %}
6677
6678 instruct membar_release() %{
6679 match(MemBarRelease);
6680 match(StoreFence);
6681 ins_cost(4*MEMORY_REF_COST);
6682
6683 size(0);
6684 format %{ "MEMBAR-release" %}
6685 ins_encode( enc_membar_release );
6686 ins_pipe(long_memory_op);
6687 %}
6688
6689 instruct membar_release_lock() %{
6690 match(MemBarReleaseLock);
6691 ins_cost(0);
6692
6693 size(0);
6694 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6695 ins_encode( );
6696 ins_pipe(empty);
6697 %}
6698
6699 instruct membar_volatile() %{
6700 match(MemBarVolatile);
6701 ins_cost(4*MEMORY_REF_COST);
6702
6703 size(4);
6704 format %{ "MEMBAR-volatile" %}
6705 ins_encode( enc_membar_volatile );
6706 ins_pipe(long_memory_op);
6707 %}
6708
6709 instruct unnecessary_membar_volatile() %{
6710 match(MemBarVolatile);
6711 predicate(Matcher::post_store_load_barrier(n));
6712 ins_cost(0);
6713
6714 size(0);
6715 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6716 ins_encode( );
6717 ins_pipe(empty);
6718 %}
6719
6720 instruct membar_storestore() %{
6721 match(MemBarStoreStore);
6722 ins_cost(0);
6723
6724 size(0);
6725 format %{ "!MEMBAR-storestore (empty encoding)" %}
6726 ins_encode( );
6727 ins_pipe(empty);
6728 %}
6729
6730 //----------Register Move Instructions-----------------------------------------
6731 instruct roundDouble_nop(regD dst) %{
6732 match(Set dst (RoundDouble dst));
6733 ins_cost(0);
6734 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6735 ins_encode( );
6736 ins_pipe(empty);
6737 %}
6738
6739
6740 instruct roundFloat_nop(regF dst) %{
6741 match(Set dst (RoundFloat dst));
6742 ins_cost(0);
6743 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6744 ins_encode( );
6745 ins_pipe(empty);
6746 %}
6747
6748
6749 // Cast Index to Pointer for unsafe natives
6750 instruct castX2P(iRegX src, iRegP dst) %{
6751 match(Set dst (CastX2P src));
6752
6753 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6754 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6755 ins_pipe(ialu_reg);
6756 %}
6757
6758 // Cast Pointer to Index for unsafe natives
6759 instruct castP2X(iRegP src, iRegX dst) %{
6760 match(Set dst (CastP2X src));
6761
6762 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6763 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6764 ins_pipe(ialu_reg);
6765 %}
6766
6767 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6768 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6769 match(Set stkSlot src); // chain rule
6770 ins_cost(MEMORY_REF_COST);
6771 format %{ "STDF $src,$stkSlot\t!stk" %}
6772 opcode(Assembler::stdf_op3);
6773 ins_encode(simple_form3_mem_reg(stkSlot, src));
6774 ins_pipe(fstoreD_stk_reg);
6775 %}
6776
6777 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6778 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6779 match(Set dst stkSlot); // chain rule
6780 ins_cost(MEMORY_REF_COST);
6781 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6782 opcode(Assembler::lddf_op3);
6783 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6784 ins_pipe(floadD_stk);
6785 %}
6786
6787 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6788 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6789 match(Set stkSlot src); // chain rule
6790 ins_cost(MEMORY_REF_COST);
6791 format %{ "STF $src,$stkSlot\t!stk" %}
6792 opcode(Assembler::stf_op3);
6793 ins_encode(simple_form3_mem_reg(stkSlot, src));
6794 ins_pipe(fstoreF_stk_reg);
6795 %}
6796
6797 //----------Conditional Move---------------------------------------------------
6798 // Conditional move
6799 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6800 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6801 ins_cost(150);
6802 format %{ "MOV$cmp $pcc,$src,$dst" %}
6803 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6804 ins_pipe(ialu_reg);
6805 %}
6806
6807 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6808 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6809 ins_cost(140);
6810 format %{ "MOV$cmp $pcc,$src,$dst" %}
6811 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6812 ins_pipe(ialu_imm);
6813 %}
6814
6815 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6816 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6817 ins_cost(150);
6818 size(4);
6819 format %{ "MOV$cmp $icc,$src,$dst" %}
6820 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6821 ins_pipe(ialu_reg);
6822 %}
6823
6824 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6825 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6826 ins_cost(140);
6827 size(4);
6828 format %{ "MOV$cmp $icc,$src,$dst" %}
6829 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6830 ins_pipe(ialu_imm);
6831 %}
6832
6833 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6834 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6835 ins_cost(150);
6836 size(4);
6837 format %{ "MOV$cmp $icc,$src,$dst" %}
6838 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6839 ins_pipe(ialu_reg);
6840 %}
6841
6842 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6843 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6844 ins_cost(140);
6845 size(4);
6846 format %{ "MOV$cmp $icc,$src,$dst" %}
6847 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6848 ins_pipe(ialu_imm);
6849 %}
6850
6851 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6852 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6853 ins_cost(150);
6854 size(4);
6855 format %{ "MOV$cmp $fcc,$src,$dst" %}
6856 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6857 ins_pipe(ialu_reg);
6858 %}
6859
6860 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6861 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6862 ins_cost(140);
6863 size(4);
6864 format %{ "MOV$cmp $fcc,$src,$dst" %}
6865 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6866 ins_pipe(ialu_imm);
6867 %}
6868
6869 // Conditional move for RegN. Only cmov(reg,reg).
6870 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6871 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6872 ins_cost(150);
6873 format %{ "MOV$cmp $pcc,$src,$dst" %}
6874 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6875 ins_pipe(ialu_reg);
6876 %}
6877
6878 // This instruction also works with CmpN so we don't need cmovNN_reg.
6879 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6880 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6881 ins_cost(150);
6882 size(4);
6883 format %{ "MOV$cmp $icc,$src,$dst" %}
6884 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6885 ins_pipe(ialu_reg);
6886 %}
6887
6888 // This instruction also works with CmpN so we don't need cmovNN_reg.
6889 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6890 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6891 ins_cost(150);
6892 size(4);
6893 format %{ "MOV$cmp $icc,$src,$dst" %}
6894 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6895 ins_pipe(ialu_reg);
6896 %}
6897
6898 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6899 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6900 ins_cost(150);
6901 size(4);
6902 format %{ "MOV$cmp $fcc,$src,$dst" %}
6903 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6904 ins_pipe(ialu_reg);
6905 %}
6906
6907 // Conditional move
6908 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6909 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6910 ins_cost(150);
6911 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6912 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6913 ins_pipe(ialu_reg);
6914 %}
6915
6916 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6917 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6918 ins_cost(140);
6919 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6920 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6921 ins_pipe(ialu_imm);
6922 %}
6923
6924 // This instruction also works with CmpN so we don't need cmovPN_reg.
6925 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6926 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6927 ins_cost(150);
6928
6929 size(4);
6930 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6931 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6932 ins_pipe(ialu_reg);
6933 %}
6934
6935 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6936 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6937 ins_cost(150);
6938
6939 size(4);
6940 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6941 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6942 ins_pipe(ialu_reg);
6943 %}
6944
6945 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6946 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6947 ins_cost(140);
6948
6949 size(4);
6950 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6951 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6952 ins_pipe(ialu_imm);
6953 %}
6954
6955 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6956 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6957 ins_cost(140);
6958
6959 size(4);
6960 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6961 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6962 ins_pipe(ialu_imm);
6963 %}
6964
6965 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6966 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6967 ins_cost(150);
6968 size(4);
6969 format %{ "MOV$cmp $fcc,$src,$dst" %}
6970 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6971 ins_pipe(ialu_imm);
6972 %}
6973
6974 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6975 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6976 ins_cost(140);
6977 size(4);
6978 format %{ "MOV$cmp $fcc,$src,$dst" %}
6979 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6980 ins_pipe(ialu_imm);
6981 %}
6982
6983 // Conditional move
6984 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6985 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6986 ins_cost(150);
6987 opcode(0x101);
6988 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6989 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6990 ins_pipe(int_conditional_float_move);
6991 %}
6992
6993 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6994 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6995 ins_cost(150);
6996
6997 size(4);
6998 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6999 opcode(0x101);
7000 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7001 ins_pipe(int_conditional_float_move);
7002 %}
7003
7004 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7005 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7006 ins_cost(150);
7007
7008 size(4);
7009 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7010 opcode(0x101);
7011 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7012 ins_pipe(int_conditional_float_move);
7013 %}
7014
7015 // Conditional move,
7016 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7017 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7018 ins_cost(150);
7019 size(4);
7020 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7021 opcode(0x1);
7022 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7023 ins_pipe(int_conditional_double_move);
7024 %}
7025
7026 // Conditional move
7027 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7028 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7029 ins_cost(150);
7030 size(4);
7031 opcode(0x102);
7032 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7033 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7034 ins_pipe(int_conditional_double_move);
7035 %}
7036
7037 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7038 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7039 ins_cost(150);
7040
7041 size(4);
7042 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7043 opcode(0x102);
7044 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7045 ins_pipe(int_conditional_double_move);
7046 %}
7047
7048 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7049 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7050 ins_cost(150);
7051
7052 size(4);
7053 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7054 opcode(0x102);
7055 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7056 ins_pipe(int_conditional_double_move);
7057 %}
7058
7059 // Conditional move,
7060 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7061 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7062 ins_cost(150);
7063 size(4);
7064 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7065 opcode(0x2);
7066 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7067 ins_pipe(int_conditional_double_move);
7068 %}
7069
7070 // Conditional move
7071 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7072 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7073 ins_cost(150);
7074 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7075 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7076 ins_pipe(ialu_reg);
7077 %}
7078
7079 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7080 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7081 ins_cost(140);
7082 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7083 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7084 ins_pipe(ialu_imm);
7085 %}
7086
7087 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7088 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7089 ins_cost(150);
7090
7091 size(4);
7092 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7093 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7094 ins_pipe(ialu_reg);
7095 %}
7096
7097
7098 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7099 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7100 ins_cost(150);
7101
7102 size(4);
7103 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7104 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7105 ins_pipe(ialu_reg);
7106 %}
7107
7108
7109 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7110 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7111 ins_cost(150);
7112
7113 size(4);
7114 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7115 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7116 ins_pipe(ialu_reg);
7117 %}
7118
7119
7120
7121 //----------OS and Locking Instructions----------------------------------------
7122
7123 // This name is KNOWN by the ADLC and cannot be changed.
7124 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7125 // for this guy.
7126 instruct tlsLoadP(g2RegP dst) %{
7127 match(Set dst (ThreadLocal));
7128
7129 size(0);
7130 ins_cost(0);
7131 format %{ "# TLS is in G2" %}
7132 ins_encode( /*empty encoding*/ );
7133 ins_pipe(ialu_none);
7134 %}
7135
7136 instruct checkCastPP( iRegP dst ) %{
7137 match(Set dst (CheckCastPP dst));
7138
7139 size(0);
7140 format %{ "# checkcastPP of $dst" %}
7141 ins_encode( /*empty encoding*/ );
7142 ins_pipe(empty);
7143 %}
7144
7145
7146 instruct castPP( iRegP dst ) %{
7147 match(Set dst (CastPP dst));
7148 format %{ "# castPP of $dst" %}
7149 ins_encode( /*empty encoding*/ );
7150 ins_pipe(empty);
7151 %}
7152
7153 instruct castII( iRegI dst ) %{
7154 match(Set dst (CastII dst));
7155 format %{ "# castII of $dst" %}
7156 ins_encode( /*empty encoding*/ );
7157 ins_cost(0);
7158 ins_pipe(empty);
7159 %}
7160
7161 //----------Arithmetic Instructions--------------------------------------------
7162 // Addition Instructions
7163 // Register Addition
7164 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7165 match(Set dst (AddI src1 src2));
7166
7167 size(4);
7168 format %{ "ADD $src1,$src2,$dst" %}
7169 ins_encode %{
7170 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7171 %}
7172 ins_pipe(ialu_reg_reg);
7173 %}
7174
7175 // Immediate Addition
7176 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7177 match(Set dst (AddI src1 src2));
7178
7179 size(4);
7180 format %{ "ADD $src1,$src2,$dst" %}
7181 opcode(Assembler::add_op3, Assembler::arith_op);
7182 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7183 ins_pipe(ialu_reg_imm);
7184 %}
7185
7186 // Pointer Register Addition
7187 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7188 match(Set dst (AddP src1 src2));
7189
7190 size(4);
7191 format %{ "ADD $src1,$src2,$dst" %}
7192 opcode(Assembler::add_op3, Assembler::arith_op);
7193 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7194 ins_pipe(ialu_reg_reg);
7195 %}
7196
7197 // Pointer Immediate Addition
7198 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7199 match(Set dst (AddP src1 src2));
7200
7201 size(4);
7202 format %{ "ADD $src1,$src2,$dst" %}
7203 opcode(Assembler::add_op3, Assembler::arith_op);
7204 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7205 ins_pipe(ialu_reg_imm);
7206 %}
7207
7208 // Long Addition
7209 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7210 match(Set dst (AddL src1 src2));
7211
7212 size(4);
7213 format %{ "ADD $src1,$src2,$dst\t! long" %}
7214 opcode(Assembler::add_op3, Assembler::arith_op);
7215 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7216 ins_pipe(ialu_reg_reg);
7217 %}
7218
7219 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7220 match(Set dst (AddL src1 con));
7221
7222 size(4);
7223 format %{ "ADD $src1,$con,$dst" %}
7224 opcode(Assembler::add_op3, Assembler::arith_op);
7225 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7226 ins_pipe(ialu_reg_imm);
7227 %}
7228
7229 //----------Conditional_store--------------------------------------------------
7230 // Conditional-store of the updated heap-top.
7231 // Used during allocation of the shared heap.
7232 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7233
7234 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7235 instruct loadPLocked(iRegP dst, memory mem) %{
7236 match(Set dst (LoadPLocked mem));
7237 ins_cost(MEMORY_REF_COST);
7238
7239 #ifndef _LP64
7240 size(4);
7241 format %{ "LDUW $mem,$dst\t! ptr" %}
7242 opcode(Assembler::lduw_op3, 0, REGP_OP);
7243 #else
7244 format %{ "LDX $mem,$dst\t! ptr" %}
7245 opcode(Assembler::ldx_op3, 0, REGP_OP);
7246 #endif
7247 ins_encode( form3_mem_reg( mem, dst ) );
7248 ins_pipe(iload_mem);
7249 %}
7250
7251 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7252 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7253 effect( KILL newval );
7254 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7255 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7256 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7257 ins_pipe( long_memory_op );
7258 %}
7259
7260 // Conditional-store of an int value.
7261 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7262 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7263 effect( KILL newval );
7264 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7265 "CMP $oldval,$newval\t\t! See if we made progress" %}
7266 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7267 ins_pipe( long_memory_op );
7268 %}
7269
7270 // Conditional-store of a long value.
7271 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7272 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7273 effect( KILL newval );
7274 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7275 "CMP $oldval,$newval\t\t! See if we made progress" %}
7276 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7277 ins_pipe( long_memory_op );
7278 %}
7279
7280 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7281
7282 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7283 predicate(VM_Version::supports_cx8());
7284 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7285 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7286 format %{
7287 "MOV $newval,O7\n\t"
7288 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7289 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7290 "MOV 1,$res\n\t"
7291 "MOVne xcc,R_G0,$res"
7292 %}
7293 ins_encode( enc_casx(mem_ptr, oldval, newval),
7294 enc_lflags_ne_to_boolean(res) );
7295 ins_pipe( long_memory_op );
7296 %}
7297
7298
7299 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7300 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7301 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7302 format %{
7303 "MOV $newval,O7\n\t"
7304 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7305 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7306 "MOV 1,$res\n\t"
7307 "MOVne icc,R_G0,$res"
7308 %}
7309 ins_encode( enc_casi(mem_ptr, oldval, newval),
7310 enc_iflags_ne_to_boolean(res) );
7311 ins_pipe( long_memory_op );
7312 %}
7313
7314 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7315 #ifdef _LP64
7316 predicate(VM_Version::supports_cx8());
7317 #endif
7318 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7319 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7320 format %{
7321 "MOV $newval,O7\n\t"
7322 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7323 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7324 "MOV 1,$res\n\t"
7325 "MOVne xcc,R_G0,$res"
7326 %}
7327 #ifdef _LP64
7328 ins_encode( enc_casx(mem_ptr, oldval, newval),
7329 enc_lflags_ne_to_boolean(res) );
7330 #else
7331 ins_encode( enc_casi(mem_ptr, oldval, newval),
7332 enc_iflags_ne_to_boolean(res) );
7333 #endif
7334 ins_pipe( long_memory_op );
7335 %}
7336
7337 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7338 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7339 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7340 format %{
7341 "MOV $newval,O7\n\t"
7342 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7343 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7344 "MOV 1,$res\n\t"
7345 "MOVne icc,R_G0,$res"
7346 %}
7347 ins_encode( enc_casi(mem_ptr, oldval, newval),
7348 enc_iflags_ne_to_boolean(res) );
7349 ins_pipe( long_memory_op );
7350 %}
7351
7352 instruct xchgI( memory mem, iRegI newval) %{
7353 match(Set newval (GetAndSetI mem newval));
7354 format %{ "SWAP [$mem],$newval" %}
7355 size(4);
7356 ins_encode %{
7357 __ swap($mem$$Address, $newval$$Register);
7358 %}
7359 ins_pipe( long_memory_op );
7360 %}
7361
7362 #ifndef _LP64
7363 instruct xchgP( memory mem, iRegP newval) %{
7364 match(Set newval (GetAndSetP mem newval));
7365 format %{ "SWAP [$mem],$newval" %}
7366 size(4);
7367 ins_encode %{
7368 __ swap($mem$$Address, $newval$$Register);
7369 %}
7370 ins_pipe( long_memory_op );
7371 %}
7372 #endif
7373
7374 instruct xchgN( memory mem, iRegN newval) %{
7375 match(Set newval (GetAndSetN mem newval));
7376 format %{ "SWAP [$mem],$newval" %}
7377 size(4);
7378 ins_encode %{
7379 __ swap($mem$$Address, $newval$$Register);
7380 %}
7381 ins_pipe( long_memory_op );
7382 %}
7383
7384 //---------------------
7385 // Subtraction Instructions
7386 // Register Subtraction
7387 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7388 match(Set dst (SubI src1 src2));
7389
7390 size(4);
7391 format %{ "SUB $src1,$src2,$dst" %}
7392 opcode(Assembler::sub_op3, Assembler::arith_op);
7393 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7394 ins_pipe(ialu_reg_reg);
7395 %}
7396
7397 // Immediate Subtraction
7398 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7399 match(Set dst (SubI src1 src2));
7400
7401 size(4);
7402 format %{ "SUB $src1,$src2,$dst" %}
7403 opcode(Assembler::sub_op3, Assembler::arith_op);
7404 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7405 ins_pipe(ialu_reg_imm);
7406 %}
7407
7408 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7409 match(Set dst (SubI zero src2));
7410
7411 size(4);
7412 format %{ "NEG $src2,$dst" %}
7413 opcode(Assembler::sub_op3, Assembler::arith_op);
7414 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7415 ins_pipe(ialu_zero_reg);
7416 %}
7417
7418 // Long subtraction
7419 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7420 match(Set dst (SubL src1 src2));
7421
7422 size(4);
7423 format %{ "SUB $src1,$src2,$dst\t! long" %}
7424 opcode(Assembler::sub_op3, Assembler::arith_op);
7425 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7426 ins_pipe(ialu_reg_reg);
7427 %}
7428
7429 // Immediate Subtraction
7430 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7431 match(Set dst (SubL src1 con));
7432
7433 size(4);
7434 format %{ "SUB $src1,$con,$dst\t! long" %}
7435 opcode(Assembler::sub_op3, Assembler::arith_op);
7436 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7437 ins_pipe(ialu_reg_imm);
7438 %}
7439
7440 // Long negation
7441 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7442 match(Set dst (SubL zero src2));
7443
7444 size(4);
7445 format %{ "NEG $src2,$dst\t! long" %}
7446 opcode(Assembler::sub_op3, Assembler::arith_op);
7447 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7448 ins_pipe(ialu_zero_reg);
7449 %}
7450
7451 // Multiplication Instructions
7452 // Integer Multiplication
7453 // Register Multiplication
7454 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7455 match(Set dst (MulI src1 src2));
7456
7457 size(4);
7458 format %{ "MULX $src1,$src2,$dst" %}
7459 opcode(Assembler::mulx_op3, Assembler::arith_op);
7460 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7461 ins_pipe(imul_reg_reg);
7462 %}
7463
7464 // Immediate Multiplication
7465 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7466 match(Set dst (MulI src1 src2));
7467
7468 size(4);
7469 format %{ "MULX $src1,$src2,$dst" %}
7470 opcode(Assembler::mulx_op3, Assembler::arith_op);
7471 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7472 ins_pipe(imul_reg_imm);
7473 %}
7474
7475 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7476 match(Set dst (MulL src1 src2));
7477 ins_cost(DEFAULT_COST * 5);
7478 size(4);
7479 format %{ "MULX $src1,$src2,$dst\t! long" %}
7480 opcode(Assembler::mulx_op3, Assembler::arith_op);
7481 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7482 ins_pipe(mulL_reg_reg);
7483 %}
7484
7485 // Immediate Multiplication
7486 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7487 match(Set dst (MulL src1 src2));
7488 ins_cost(DEFAULT_COST * 5);
7489 size(4);
7490 format %{ "MULX $src1,$src2,$dst" %}
7491 opcode(Assembler::mulx_op3, Assembler::arith_op);
7492 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7493 ins_pipe(mulL_reg_imm);
7494 %}
7495
7496 // Integer Division
7497 // Register Division
7498 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7499 match(Set dst (DivI src1 src2));
7500 ins_cost((2+71)*DEFAULT_COST);
7501
7502 format %{ "SRA $src2,0,$src2\n\t"
7503 "SRA $src1,0,$src1\n\t"
7504 "SDIVX $src1,$src2,$dst" %}
7505 ins_encode( idiv_reg( src1, src2, dst ) );
7506 ins_pipe(sdiv_reg_reg);
7507 %}
7508
7509 // Immediate Division
7510 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7511 match(Set dst (DivI src1 src2));
7512 ins_cost((2+71)*DEFAULT_COST);
7513
7514 format %{ "SRA $src1,0,$src1\n\t"
7515 "SDIVX $src1,$src2,$dst" %}
7516 ins_encode( idiv_imm( src1, src2, dst ) );
7517 ins_pipe(sdiv_reg_imm);
7518 %}
7519
7520 //----------Div-By-10-Expansion------------------------------------------------
7521 // Extract hi bits of a 32x32->64 bit multiply.
7522 // Expand rule only, not matched
7523 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7524 effect( DEF dst, USE src1, USE src2 );
7525 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7526 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7527 ins_encode( enc_mul_hi(dst,src1,src2));
7528 ins_pipe(sdiv_reg_reg);
7529 %}
7530
7531 // Magic constant, reciprocal of 10
7532 instruct loadConI_x66666667(iRegIsafe dst) %{
7533 effect( DEF dst );
7534
7535 size(8);
7536 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7537 ins_encode( Set32(0x66666667, dst) );
7538 ins_pipe(ialu_hi_lo_reg);
7539 %}
7540
7541 // Register Shift Right Arithmetic Long by 32-63
7542 instruct sra_31( iRegI dst, iRegI src ) %{
7543 effect( DEF dst, USE src );
7544 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7545 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7546 ins_pipe(ialu_reg_reg);
7547 %}
7548
7549 // Arithmetic Shift Right by 8-bit immediate
7550 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7551 effect( DEF dst, USE src );
7552 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7553 opcode(Assembler::sra_op3, Assembler::arith_op);
7554 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7555 ins_pipe(ialu_reg_imm);
7556 %}
7557
7558 // Integer DIV with 10
7559 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7560 match(Set dst (DivI src div));
7561 ins_cost((6+6)*DEFAULT_COST);
7562 expand %{
7563 iRegIsafe tmp1; // Killed temps;
7564 iRegIsafe tmp2; // Killed temps;
7565 iRegI tmp3; // Killed temps;
7566 iRegI tmp4; // Killed temps;
7567 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7568 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7569 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7570 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7571 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7572 %}
7573 %}
7574
7575 // Register Long Division
7576 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7577 match(Set dst (DivL src1 src2));
7578 ins_cost(DEFAULT_COST*71);
7579 size(4);
7580 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7581 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7582 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7583 ins_pipe(divL_reg_reg);
7584 %}
7585
7586 // Register Long Division
7587 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7588 match(Set dst (DivL src1 src2));
7589 ins_cost(DEFAULT_COST*71);
7590 size(4);
7591 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7592 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7593 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7594 ins_pipe(divL_reg_imm);
7595 %}
7596
7597 // Integer Remainder
7598 // Register Remainder
7599 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7600 match(Set dst (ModI src1 src2));
7601 effect( KILL ccr, KILL temp);
7602
7603 format %{ "SREM $src1,$src2,$dst" %}
7604 ins_encode( irem_reg(src1, src2, dst, temp) );
7605 ins_pipe(sdiv_reg_reg);
7606 %}
7607
7608 // Immediate Remainder
7609 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7610 match(Set dst (ModI src1 src2));
7611 effect( KILL ccr, KILL temp);
7612
7613 format %{ "SREM $src1,$src2,$dst" %}
7614 ins_encode( irem_imm(src1, src2, dst, temp) );
7615 ins_pipe(sdiv_reg_imm);
7616 %}
7617
7618 // Register Long Remainder
7619 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7620 effect(DEF dst, USE src1, USE src2);
7621 size(4);
7622 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7623 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7624 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7625 ins_pipe(divL_reg_reg);
7626 %}
7627
7628 // Register Long Division
7629 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7630 effect(DEF dst, USE src1, USE src2);
7631 size(4);
7632 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7633 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7634 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7635 ins_pipe(divL_reg_imm);
7636 %}
7637
7638 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7639 effect(DEF dst, USE src1, USE src2);
7640 size(4);
7641 format %{ "MULX $src1,$src2,$dst\t! long" %}
7642 opcode(Assembler::mulx_op3, Assembler::arith_op);
7643 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7644 ins_pipe(mulL_reg_reg);
7645 %}
7646
7647 // Immediate Multiplication
7648 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7649 effect(DEF dst, USE src1, USE src2);
7650 size(4);
7651 format %{ "MULX $src1,$src2,$dst" %}
7652 opcode(Assembler::mulx_op3, Assembler::arith_op);
7653 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7654 ins_pipe(mulL_reg_imm);
7655 %}
7656
7657 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7658 effect(DEF dst, USE src1, USE src2);
7659 size(4);
7660 format %{ "SUB $src1,$src2,$dst\t! long" %}
7661 opcode(Assembler::sub_op3, Assembler::arith_op);
7662 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7663 ins_pipe(ialu_reg_reg);
7664 %}
7665
7666 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7667 effect(DEF dst, USE src1, USE src2);
7668 size(4);
7669 format %{ "SUB $src1,$src2,$dst\t! long" %}
7670 opcode(Assembler::sub_op3, Assembler::arith_op);
7671 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7672 ins_pipe(ialu_reg_reg);
7673 %}
7674
7675 // Register Long Remainder
7676 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7677 match(Set dst (ModL src1 src2));
7678 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7679 expand %{
7680 iRegL tmp1;
7681 iRegL tmp2;
7682 divL_reg_reg_1(tmp1, src1, src2);
7683 mulL_reg_reg_1(tmp2, tmp1, src2);
7684 subL_reg_reg_1(dst, src1, tmp2);
7685 %}
7686 %}
7687
7688 // Register Long Remainder
7689 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7690 match(Set dst (ModL src1 src2));
7691 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7692 expand %{
7693 iRegL tmp1;
7694 iRegL tmp2;
7695 divL_reg_imm13_1(tmp1, src1, src2);
7696 mulL_reg_imm13_1(tmp2, tmp1, src2);
7697 subL_reg_reg_2 (dst, src1, tmp2);
7698 %}
7699 %}
7700
7701 // Integer Shift Instructions
7702 // Register Shift Left
7703 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7704 match(Set dst (LShiftI src1 src2));
7705
7706 size(4);
7707 format %{ "SLL $src1,$src2,$dst" %}
7708 opcode(Assembler::sll_op3, Assembler::arith_op);
7709 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7710 ins_pipe(ialu_reg_reg);
7711 %}
7712
7713 // Register Shift Left Immediate
7714 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7715 match(Set dst (LShiftI src1 src2));
7716
7717 size(4);
7718 format %{ "SLL $src1,$src2,$dst" %}
7719 opcode(Assembler::sll_op3, Assembler::arith_op);
7720 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7721 ins_pipe(ialu_reg_imm);
7722 %}
7723
7724 // Register Shift Left
7725 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7726 match(Set dst (LShiftL src1 src2));
7727
7728 size(4);
7729 format %{ "SLLX $src1,$src2,$dst" %}
7730 opcode(Assembler::sllx_op3, Assembler::arith_op);
7731 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7732 ins_pipe(ialu_reg_reg);
7733 %}
7734
7735 // Register Shift Left Immediate
7736 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7737 match(Set dst (LShiftL src1 src2));
7738
7739 size(4);
7740 format %{ "SLLX $src1,$src2,$dst" %}
7741 opcode(Assembler::sllx_op3, Assembler::arith_op);
7742 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7743 ins_pipe(ialu_reg_imm);
7744 %}
7745
7746 // Register Arithmetic Shift Right
7747 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7748 match(Set dst (RShiftI src1 src2));
7749 size(4);
7750 format %{ "SRA $src1,$src2,$dst" %}
7751 opcode(Assembler::sra_op3, Assembler::arith_op);
7752 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7753 ins_pipe(ialu_reg_reg);
7754 %}
7755
7756 // Register Arithmetic Shift Right Immediate
7757 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7758 match(Set dst (RShiftI src1 src2));
7759
7760 size(4);
7761 format %{ "SRA $src1,$src2,$dst" %}
7762 opcode(Assembler::sra_op3, Assembler::arith_op);
7763 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7764 ins_pipe(ialu_reg_imm);
7765 %}
7766
7767 // Register Shift Right Arithmatic Long
7768 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7769 match(Set dst (RShiftL src1 src2));
7770
7771 size(4);
7772 format %{ "SRAX $src1,$src2,$dst" %}
7773 opcode(Assembler::srax_op3, Assembler::arith_op);
7774 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7775 ins_pipe(ialu_reg_reg);
7776 %}
7777
7778 // Register Shift Left Immediate
7779 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7780 match(Set dst (RShiftL src1 src2));
7781
7782 size(4);
7783 format %{ "SRAX $src1,$src2,$dst" %}
7784 opcode(Assembler::srax_op3, Assembler::arith_op);
7785 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7786 ins_pipe(ialu_reg_imm);
7787 %}
7788
7789 // Register Shift Right
7790 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7791 match(Set dst (URShiftI src1 src2));
7792
7793 size(4);
7794 format %{ "SRL $src1,$src2,$dst" %}
7795 opcode(Assembler::srl_op3, Assembler::arith_op);
7796 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7797 ins_pipe(ialu_reg_reg);
7798 %}
7799
7800 // Register Shift Right Immediate
7801 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7802 match(Set dst (URShiftI src1 src2));
7803
7804 size(4);
7805 format %{ "SRL $src1,$src2,$dst" %}
7806 opcode(Assembler::srl_op3, Assembler::arith_op);
7807 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7808 ins_pipe(ialu_reg_imm);
7809 %}
7810
7811 // Register Shift Right
7812 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7813 match(Set dst (URShiftL src1 src2));
7814
7815 size(4);
7816 format %{ "SRLX $src1,$src2,$dst" %}
7817 opcode(Assembler::srlx_op3, Assembler::arith_op);
7818 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7819 ins_pipe(ialu_reg_reg);
7820 %}
7821
7822 // Register Shift Right Immediate
7823 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7824 match(Set dst (URShiftL src1 src2));
7825
7826 size(4);
7827 format %{ "SRLX $src1,$src2,$dst" %}
7828 opcode(Assembler::srlx_op3, Assembler::arith_op);
7829 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7830 ins_pipe(ialu_reg_imm);
7831 %}
7832
7833 // Register Shift Right Immediate with a CastP2X
7834 #ifdef _LP64
7835 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7836 match(Set dst (URShiftL (CastP2X src1) src2));
7837 size(4);
7838 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7839 opcode(Assembler::srlx_op3, Assembler::arith_op);
7840 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7841 ins_pipe(ialu_reg_imm);
7842 %}
7843 #else
7844 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7845 match(Set dst (URShiftI (CastP2X src1) src2));
7846 size(4);
7847 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7848 opcode(Assembler::srl_op3, Assembler::arith_op);
7849 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7850 ins_pipe(ialu_reg_imm);
7851 %}
7852 #endif
7853
7854
7855 //----------Floating Point Arithmetic Instructions-----------------------------
7856
7857 // Add float single precision
7858 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7859 match(Set dst (AddF src1 src2));
7860
7861 size(4);
7862 format %{ "FADDS $src1,$src2,$dst" %}
7863 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7864 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7865 ins_pipe(faddF_reg_reg);
7866 %}
7867
7868 // Add float double precision
7869 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7870 match(Set dst (AddD src1 src2));
7871
7872 size(4);
7873 format %{ "FADDD $src1,$src2,$dst" %}
7874 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7875 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7876 ins_pipe(faddD_reg_reg);
7877 %}
7878
7879 // Sub float single precision
7880 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7881 match(Set dst (SubF src1 src2));
7882
7883 size(4);
7884 format %{ "FSUBS $src1,$src2,$dst" %}
7885 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7886 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7887 ins_pipe(faddF_reg_reg);
7888 %}
7889
7890 // Sub float double precision
7891 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7892 match(Set dst (SubD src1 src2));
7893
7894 size(4);
7895 format %{ "FSUBD $src1,$src2,$dst" %}
7896 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7897 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7898 ins_pipe(faddD_reg_reg);
7899 %}
7900
7901 // Mul float single precision
7902 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7903 match(Set dst (MulF src1 src2));
7904
7905 size(4);
7906 format %{ "FMULS $src1,$src2,$dst" %}
7907 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7908 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7909 ins_pipe(fmulF_reg_reg);
7910 %}
7911
7912 // Mul float double precision
7913 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7914 match(Set dst (MulD src1 src2));
7915
7916 size(4);
7917 format %{ "FMULD $src1,$src2,$dst" %}
7918 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7919 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7920 ins_pipe(fmulD_reg_reg);
7921 %}
7922
7923 // Div float single precision
7924 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7925 match(Set dst (DivF src1 src2));
7926
7927 size(4);
7928 format %{ "FDIVS $src1,$src2,$dst" %}
7929 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7930 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7931 ins_pipe(fdivF_reg_reg);
7932 %}
7933
7934 // Div float double precision
7935 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7936 match(Set dst (DivD src1 src2));
7937
7938 size(4);
7939 format %{ "FDIVD $src1,$src2,$dst" %}
7940 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7941 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7942 ins_pipe(fdivD_reg_reg);
7943 %}
7944
7945 // Absolute float double precision
7946 instruct absD_reg(regD dst, regD src) %{
7947 match(Set dst (AbsD src));
7948
7949 format %{ "FABSd $src,$dst" %}
7950 ins_encode(fabsd(dst, src));
7951 ins_pipe(faddD_reg);
7952 %}
7953
7954 // Absolute float single precision
7955 instruct absF_reg(regF dst, regF src) %{
7956 match(Set dst (AbsF src));
7957
7958 format %{ "FABSs $src,$dst" %}
7959 ins_encode(fabss(dst, src));
7960 ins_pipe(faddF_reg);
7961 %}
7962
7963 instruct negF_reg(regF dst, regF src) %{
7964 match(Set dst (NegF src));
7965
7966 size(4);
7967 format %{ "FNEGs $src,$dst" %}
7968 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7969 ins_encode(form3_opf_rs2F_rdF(src, dst));
7970 ins_pipe(faddF_reg);
7971 %}
7972
7973 instruct negD_reg(regD dst, regD src) %{
7974 match(Set dst (NegD src));
7975
7976 format %{ "FNEGd $src,$dst" %}
7977 ins_encode(fnegd(dst, src));
7978 ins_pipe(faddD_reg);
7979 %}
7980
7981 // Sqrt float double precision
7982 instruct sqrtF_reg_reg(regF dst, regF src) %{
7983 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7984
7985 size(4);
7986 format %{ "FSQRTS $src,$dst" %}
7987 ins_encode(fsqrts(dst, src));
7988 ins_pipe(fdivF_reg_reg);
7989 %}
7990
7991 // Sqrt float double precision
7992 instruct sqrtD_reg_reg(regD dst, regD src) %{
7993 match(Set dst (SqrtD src));
7994
7995 size(4);
7996 format %{ "FSQRTD $src,$dst" %}
7997 ins_encode(fsqrtd(dst, src));
7998 ins_pipe(fdivD_reg_reg);
7999 %}
8000
8001 //----------Logical Instructions-----------------------------------------------
8002 // And Instructions
8003 // Register And
8004 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8005 match(Set dst (AndI src1 src2));
8006
8007 size(4);
8008 format %{ "AND $src1,$src2,$dst" %}
8009 opcode(Assembler::and_op3, Assembler::arith_op);
8010 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8011 ins_pipe(ialu_reg_reg);
8012 %}
8013
8014 // Immediate And
8015 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8016 match(Set dst (AndI src1 src2));
8017
8018 size(4);
8019 format %{ "AND $src1,$src2,$dst" %}
8020 opcode(Assembler::and_op3, Assembler::arith_op);
8021 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8022 ins_pipe(ialu_reg_imm);
8023 %}
8024
8025 // Register And Long
8026 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8027 match(Set dst (AndL src1 src2));
8028
8029 ins_cost(DEFAULT_COST);
8030 size(4);
8031 format %{ "AND $src1,$src2,$dst\t! long" %}
8032 opcode(Assembler::and_op3, Assembler::arith_op);
8033 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8034 ins_pipe(ialu_reg_reg);
8035 %}
8036
8037 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8038 match(Set dst (AndL src1 con));
8039
8040 ins_cost(DEFAULT_COST);
8041 size(4);
8042 format %{ "AND $src1,$con,$dst\t! long" %}
8043 opcode(Assembler::and_op3, Assembler::arith_op);
8044 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8045 ins_pipe(ialu_reg_imm);
8046 %}
8047
8048 // Or Instructions
8049 // Register Or
8050 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8051 match(Set dst (OrI src1 src2));
8052
8053 size(4);
8054 format %{ "OR $src1,$src2,$dst" %}
8055 opcode(Assembler::or_op3, Assembler::arith_op);
8056 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8057 ins_pipe(ialu_reg_reg);
8058 %}
8059
8060 // Immediate Or
8061 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8062 match(Set dst (OrI src1 src2));
8063
8064 size(4);
8065 format %{ "OR $src1,$src2,$dst" %}
8066 opcode(Assembler::or_op3, Assembler::arith_op);
8067 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8068 ins_pipe(ialu_reg_imm);
8069 %}
8070
8071 // Register Or Long
8072 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8073 match(Set dst (OrL src1 src2));
8074
8075 ins_cost(DEFAULT_COST);
8076 size(4);
8077 format %{ "OR $src1,$src2,$dst\t! long" %}
8078 opcode(Assembler::or_op3, Assembler::arith_op);
8079 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8080 ins_pipe(ialu_reg_reg);
8081 %}
8082
8083 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8084 match(Set dst (OrL src1 con));
8085 ins_cost(DEFAULT_COST*2);
8086
8087 ins_cost(DEFAULT_COST);
8088 size(4);
8089 format %{ "OR $src1,$con,$dst\t! long" %}
8090 opcode(Assembler::or_op3, Assembler::arith_op);
8091 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8092 ins_pipe(ialu_reg_imm);
8093 %}
8094
8095 #ifndef _LP64
8096
8097 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8098 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8099 match(Set dst (OrI src1 (CastP2X src2)));
8100
8101 size(4);
8102 format %{ "OR $src1,$src2,$dst" %}
8103 opcode(Assembler::or_op3, Assembler::arith_op);
8104 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8105 ins_pipe(ialu_reg_reg);
8106 %}
8107
8108 #else
8109
8110 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8111 match(Set dst (OrL src1 (CastP2X src2)));
8112
8113 ins_cost(DEFAULT_COST);
8114 size(4);
8115 format %{ "OR $src1,$src2,$dst\t! long" %}
8116 opcode(Assembler::or_op3, Assembler::arith_op);
8117 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8118 ins_pipe(ialu_reg_reg);
8119 %}
8120
8121 #endif
8122
8123 // Xor Instructions
8124 // Register Xor
8125 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8126 match(Set dst (XorI src1 src2));
8127
8128 size(4);
8129 format %{ "XOR $src1,$src2,$dst" %}
8130 opcode(Assembler::xor_op3, Assembler::arith_op);
8131 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8132 ins_pipe(ialu_reg_reg);
8133 %}
8134
8135 // Immediate Xor
8136 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8137 match(Set dst (XorI src1 src2));
8138
8139 size(4);
8140 format %{ "XOR $src1,$src2,$dst" %}
8141 opcode(Assembler::xor_op3, Assembler::arith_op);
8142 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8143 ins_pipe(ialu_reg_imm);
8144 %}
8145
8146 // Register Xor Long
8147 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8148 match(Set dst (XorL src1 src2));
8149
8150 ins_cost(DEFAULT_COST);
8151 size(4);
8152 format %{ "XOR $src1,$src2,$dst\t! long" %}
8153 opcode(Assembler::xor_op3, Assembler::arith_op);
8154 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8155 ins_pipe(ialu_reg_reg);
8156 %}
8157
8158 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8159 match(Set dst (XorL src1 con));
8160
8161 ins_cost(DEFAULT_COST);
8162 size(4);
8163 format %{ "XOR $src1,$con,$dst\t! long" %}
8164 opcode(Assembler::xor_op3, Assembler::arith_op);
8165 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8166 ins_pipe(ialu_reg_imm);
8167 %}
8168
8169 //----------Convert to Boolean-------------------------------------------------
8170 // Nice hack for 32-bit tests but doesn't work for
8171 // 64-bit pointers.
8172 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8173 match(Set dst (Conv2B src));
8174 effect( KILL ccr );
8175 ins_cost(DEFAULT_COST*2);
8176 format %{ "CMP R_G0,$src\n\t"
8177 "ADDX R_G0,0,$dst" %}
8178 ins_encode( enc_to_bool( src, dst ) );
8179 ins_pipe(ialu_reg_ialu);
8180 %}
8181
8182 #ifndef _LP64
8183 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8184 match(Set dst (Conv2B src));
8185 effect( KILL ccr );
8186 ins_cost(DEFAULT_COST*2);
8187 format %{ "CMP R_G0,$src\n\t"
8188 "ADDX R_G0,0,$dst" %}
8189 ins_encode( enc_to_bool( src, dst ) );
8190 ins_pipe(ialu_reg_ialu);
8191 %}
8192 #else
8193 instruct convP2B( iRegI dst, iRegP src ) %{
8194 match(Set dst (Conv2B src));
8195 ins_cost(DEFAULT_COST*2);
8196 format %{ "MOV $src,$dst\n\t"
8197 "MOVRNZ $src,1,$dst" %}
8198 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8199 ins_pipe(ialu_clr_and_mover);
8200 %}
8201 #endif
8202
8203 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8204 match(Set dst (CmpLTMask src zero));
8205 effect(KILL ccr);
8206 size(4);
8207 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8208 ins_encode %{
8209 __ sra($src$$Register, 31, $dst$$Register);
8210 %}
8211 ins_pipe(ialu_reg_imm);
8212 %}
8213
8214 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8215 match(Set dst (CmpLTMask p q));
8216 effect( KILL ccr );
8217 ins_cost(DEFAULT_COST*4);
8218 format %{ "CMP $p,$q\n\t"
8219 "MOV #0,$dst\n\t"
8220 "BLT,a .+8\n\t"
8221 "MOV #-1,$dst" %}
8222 ins_encode( enc_ltmask(p,q,dst) );
8223 ins_pipe(ialu_reg_reg_ialu);
8224 %}
8225
8226 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8227 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8228 effect(KILL ccr, TEMP tmp);
8229 ins_cost(DEFAULT_COST*3);
8230
8231 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8232 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8233 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8234 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8235 ins_pipe(cadd_cmpltmask);
8236 %}
8237
8238 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8239 match(Set p (AndI (CmpLTMask p q) y));
8240 effect(KILL ccr);
8241 ins_cost(DEFAULT_COST*3);
8242
8243 format %{ "CMP $p,$q\n\t"
8244 "MOV $y,$p\n\t"
8245 "MOVge G0,$p" %}
8246 ins_encode %{
8247 __ cmp($p$$Register, $q$$Register);
8248 __ mov($y$$Register, $p$$Register);
8249 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8250 %}
8251 ins_pipe(ialu_reg_reg_ialu);
8252 %}
8253
8254 //-----------------------------------------------------------------
8255 // Direct raw moves between float and general registers using VIS3.
8256
8257 // ins_pipe(faddF_reg);
8258 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8259 predicate(UseVIS >= 3);
8260 match(Set dst (MoveF2I src));
8261
8262 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8263 ins_encode %{
8264 __ movstouw($src$$FloatRegister, $dst$$Register);
8265 %}
8266 ins_pipe(ialu_reg_reg);
8267 %}
8268
8269 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8270 predicate(UseVIS >= 3);
8271 match(Set dst (MoveI2F src));
8272
8273 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8274 ins_encode %{
8275 __ movwtos($src$$Register, $dst$$FloatRegister);
8276 %}
8277 ins_pipe(ialu_reg_reg);
8278 %}
8279
8280 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8281 predicate(UseVIS >= 3);
8282 match(Set dst (MoveD2L src));
8283
8284 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8285 ins_encode %{
8286 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8287 %}
8288 ins_pipe(ialu_reg_reg);
8289 %}
8290
8291 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8292 predicate(UseVIS >= 3);
8293 match(Set dst (MoveL2D src));
8294
8295 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8296 ins_encode %{
8297 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8298 %}
8299 ins_pipe(ialu_reg_reg);
8300 %}
8301
8302
8303 // Raw moves between float and general registers using stack.
8304
8305 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8306 match(Set dst (MoveF2I src));
8307 effect(DEF dst, USE src);
8308 ins_cost(MEMORY_REF_COST);
8309
8310 size(4);
8311 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8312 opcode(Assembler::lduw_op3);
8313 ins_encode(simple_form3_mem_reg( src, dst ) );
8314 ins_pipe(iload_mem);
8315 %}
8316
8317 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8318 match(Set dst (MoveI2F src));
8319 effect(DEF dst, USE src);
8320 ins_cost(MEMORY_REF_COST);
8321
8322 size(4);
8323 format %{ "LDF $src,$dst\t! MoveI2F" %}
8324 opcode(Assembler::ldf_op3);
8325 ins_encode(simple_form3_mem_reg(src, dst));
8326 ins_pipe(floadF_stk);
8327 %}
8328
8329 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8330 match(Set dst (MoveD2L src));
8331 effect(DEF dst, USE src);
8332 ins_cost(MEMORY_REF_COST);
8333
8334 size(4);
8335 format %{ "LDX $src,$dst\t! MoveD2L" %}
8336 opcode(Assembler::ldx_op3);
8337 ins_encode(simple_form3_mem_reg( src, dst ) );
8338 ins_pipe(iload_mem);
8339 %}
8340
8341 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8342 match(Set dst (MoveL2D src));
8343 effect(DEF dst, USE src);
8344 ins_cost(MEMORY_REF_COST);
8345
8346 size(4);
8347 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8348 opcode(Assembler::lddf_op3);
8349 ins_encode(simple_form3_mem_reg(src, dst));
8350 ins_pipe(floadD_stk);
8351 %}
8352
8353 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8354 match(Set dst (MoveF2I src));
8355 effect(DEF dst, USE src);
8356 ins_cost(MEMORY_REF_COST);
8357
8358 size(4);
8359 format %{ "STF $src,$dst\t! MoveF2I" %}
8360 opcode(Assembler::stf_op3);
8361 ins_encode(simple_form3_mem_reg(dst, src));
8362 ins_pipe(fstoreF_stk_reg);
8363 %}
8364
8365 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8366 match(Set dst (MoveI2F src));
8367 effect(DEF dst, USE src);
8368 ins_cost(MEMORY_REF_COST);
8369
8370 size(4);
8371 format %{ "STW $src,$dst\t! MoveI2F" %}
8372 opcode(Assembler::stw_op3);
8373 ins_encode(simple_form3_mem_reg( dst, src ) );
8374 ins_pipe(istore_mem_reg);
8375 %}
8376
8377 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8378 match(Set dst (MoveD2L src));
8379 effect(DEF dst, USE src);
8380 ins_cost(MEMORY_REF_COST);
8381
8382 size(4);
8383 format %{ "STDF $src,$dst\t! MoveD2L" %}
8384 opcode(Assembler::stdf_op3);
8385 ins_encode(simple_form3_mem_reg(dst, src));
8386 ins_pipe(fstoreD_stk_reg);
8387 %}
8388
8389 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8390 match(Set dst (MoveL2D src));
8391 effect(DEF dst, USE src);
8392 ins_cost(MEMORY_REF_COST);
8393
8394 size(4);
8395 format %{ "STX $src,$dst\t! MoveL2D" %}
8396 opcode(Assembler::stx_op3);
8397 ins_encode(simple_form3_mem_reg( dst, src ) );
8398 ins_pipe(istore_mem_reg);
8399 %}
8400
8401
8402 //----------Arithmetic Conversion Instructions---------------------------------
8403 // The conversions operations are all Alpha sorted. Please keep it that way!
8404
8405 instruct convD2F_reg(regF dst, regD src) %{
8406 match(Set dst (ConvD2F src));
8407 size(4);
8408 format %{ "FDTOS $src,$dst" %}
8409 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8410 ins_encode(form3_opf_rs2D_rdF(src, dst));
8411 ins_pipe(fcvtD2F);
8412 %}
8413
8414
8415 // Convert a double to an int in a float register.
8416 // If the double is a NAN, stuff a zero in instead.
8417 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8418 effect(DEF dst, USE src, KILL fcc0);
8419 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8420 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8421 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8422 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8423 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8424 "skip:" %}
8425 ins_encode(form_d2i_helper(src,dst));
8426 ins_pipe(fcvtD2I);
8427 %}
8428
8429 instruct convD2I_stk(stackSlotI dst, regD src) %{
8430 match(Set dst (ConvD2I src));
8431 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8432 expand %{
8433 regF tmp;
8434 convD2I_helper(tmp, src);
8435 regF_to_stkI(dst, tmp);
8436 %}
8437 %}
8438
8439 instruct convD2I_reg(iRegI dst, regD src) %{
8440 predicate(UseVIS >= 3);
8441 match(Set dst (ConvD2I src));
8442 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8443 expand %{
8444 regF tmp;
8445 convD2I_helper(tmp, src);
8446 MoveF2I_reg_reg(dst, tmp);
8447 %}
8448 %}
8449
8450
8451 // Convert a double to a long in a double register.
8452 // If the double is a NAN, stuff a zero in instead.
8453 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8454 effect(DEF dst, USE src, KILL fcc0);
8455 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8456 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8457 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8458 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8459 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8460 "skip:" %}
8461 ins_encode(form_d2l_helper(src,dst));
8462 ins_pipe(fcvtD2L);
8463 %}
8464
8465 instruct convD2L_stk(stackSlotL dst, regD src) %{
8466 match(Set dst (ConvD2L src));
8467 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8468 expand %{
8469 regD tmp;
8470 convD2L_helper(tmp, src);
8471 regD_to_stkL(dst, tmp);
8472 %}
8473 %}
8474
8475 instruct convD2L_reg(iRegL dst, regD src) %{
8476 predicate(UseVIS >= 3);
8477 match(Set dst (ConvD2L src));
8478 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8479 expand %{
8480 regD tmp;
8481 convD2L_helper(tmp, src);
8482 MoveD2L_reg_reg(dst, tmp);
8483 %}
8484 %}
8485
8486
8487 instruct convF2D_reg(regD dst, regF src) %{
8488 match(Set dst (ConvF2D src));
8489 format %{ "FSTOD $src,$dst" %}
8490 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8491 ins_encode(form3_opf_rs2F_rdD(src, dst));
8492 ins_pipe(fcvtF2D);
8493 %}
8494
8495
8496 // Convert a float to an int in a float register.
8497 // If the float is a NAN, stuff a zero in instead.
8498 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8499 effect(DEF dst, USE src, KILL fcc0);
8500 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8501 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8502 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8503 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8504 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8505 "skip:" %}
8506 ins_encode(form_f2i_helper(src,dst));
8507 ins_pipe(fcvtF2I);
8508 %}
8509
8510 instruct convF2I_stk(stackSlotI dst, regF src) %{
8511 match(Set dst (ConvF2I src));
8512 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8513 expand %{
8514 regF tmp;
8515 convF2I_helper(tmp, src);
8516 regF_to_stkI(dst, tmp);
8517 %}
8518 %}
8519
8520 instruct convF2I_reg(iRegI dst, regF src) %{
8521 predicate(UseVIS >= 3);
8522 match(Set dst (ConvF2I src));
8523 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8524 expand %{
8525 regF tmp;
8526 convF2I_helper(tmp, src);
8527 MoveF2I_reg_reg(dst, tmp);
8528 %}
8529 %}
8530
8531
8532 // Convert a float to a long in a float register.
8533 // If the float is a NAN, stuff a zero in instead.
8534 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8535 effect(DEF dst, USE src, KILL fcc0);
8536 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8537 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8538 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8539 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8540 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8541 "skip:" %}
8542 ins_encode(form_f2l_helper(src,dst));
8543 ins_pipe(fcvtF2L);
8544 %}
8545
8546 instruct convF2L_stk(stackSlotL dst, regF src) %{
8547 match(Set dst (ConvF2L src));
8548 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8549 expand %{
8550 regD tmp;
8551 convF2L_helper(tmp, src);
8552 regD_to_stkL(dst, tmp);
8553 %}
8554 %}
8555
8556 instruct convF2L_reg(iRegL dst, regF src) %{
8557 predicate(UseVIS >= 3);
8558 match(Set dst (ConvF2L src));
8559 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8560 expand %{
8561 regD tmp;
8562 convF2L_helper(tmp, src);
8563 MoveD2L_reg_reg(dst, tmp);
8564 %}
8565 %}
8566
8567
8568 instruct convI2D_helper(regD dst, regF tmp) %{
8569 effect(USE tmp, DEF dst);
8570 format %{ "FITOD $tmp,$dst" %}
8571 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8572 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8573 ins_pipe(fcvtI2D);
8574 %}
8575
8576 instruct convI2D_stk(stackSlotI src, regD dst) %{
8577 match(Set dst (ConvI2D src));
8578 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8579 expand %{
8580 regF tmp;
8581 stkI_to_regF(tmp, src);
8582 convI2D_helper(dst, tmp);
8583 %}
8584 %}
8585
8586 instruct convI2D_reg(regD_low dst, iRegI src) %{
8587 predicate(UseVIS >= 3);
8588 match(Set dst (ConvI2D src));
8589 expand %{
8590 regF tmp;
8591 MoveI2F_reg_reg(tmp, src);
8592 convI2D_helper(dst, tmp);
8593 %}
8594 %}
8595
8596 instruct convI2D_mem(regD_low dst, memory mem) %{
8597 match(Set dst (ConvI2D (LoadI mem)));
8598 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8599 size(8);
8600 format %{ "LDF $mem,$dst\n\t"
8601 "FITOD $dst,$dst" %}
8602 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8603 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8604 ins_pipe(floadF_mem);
8605 %}
8606
8607
8608 instruct convI2F_helper(regF dst, regF tmp) %{
8609 effect(DEF dst, USE tmp);
8610 format %{ "FITOS $tmp,$dst" %}
8611 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8612 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8613 ins_pipe(fcvtI2F);
8614 %}
8615
8616 instruct convI2F_stk(regF dst, stackSlotI src) %{
8617 match(Set dst (ConvI2F src));
8618 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8619 expand %{
8620 regF tmp;
8621 stkI_to_regF(tmp,src);
8622 convI2F_helper(dst, tmp);
8623 %}
8624 %}
8625
8626 instruct convI2F_reg(regF dst, iRegI src) %{
8627 predicate(UseVIS >= 3);
8628 match(Set dst (ConvI2F src));
8629 ins_cost(DEFAULT_COST);
8630 expand %{
8631 regF tmp;
8632 MoveI2F_reg_reg(tmp, src);
8633 convI2F_helper(dst, tmp);
8634 %}
8635 %}
8636
8637 instruct convI2F_mem( regF dst, memory mem ) %{
8638 match(Set dst (ConvI2F (LoadI mem)));
8639 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8640 size(8);
8641 format %{ "LDF $mem,$dst\n\t"
8642 "FITOS $dst,$dst" %}
8643 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8644 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8645 ins_pipe(floadF_mem);
8646 %}
8647
8648
8649 instruct convI2L_reg(iRegL dst, iRegI src) %{
8650 match(Set dst (ConvI2L src));
8651 size(4);
8652 format %{ "SRA $src,0,$dst\t! int->long" %}
8653 opcode(Assembler::sra_op3, Assembler::arith_op);
8654 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8655 ins_pipe(ialu_reg_reg);
8656 %}
8657
8658 // Zero-extend convert int to long
8659 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8660 match(Set dst (AndL (ConvI2L src) mask) );
8661 size(4);
8662 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8663 opcode(Assembler::srl_op3, Assembler::arith_op);
8664 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8665 ins_pipe(ialu_reg_reg);
8666 %}
8667
8668 // Zero-extend long
8669 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8670 match(Set dst (AndL src mask) );
8671 size(4);
8672 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8673 opcode(Assembler::srl_op3, Assembler::arith_op);
8674 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8675 ins_pipe(ialu_reg_reg);
8676 %}
8677
8678
8679 //-----------
8680 // Long to Double conversion using V8 opcodes.
8681 // Still useful because cheetah traps and becomes
8682 // amazingly slow for some common numbers.
8683
8684 // Magic constant, 0x43300000
8685 instruct loadConI_x43300000(iRegI dst) %{
8686 effect(DEF dst);
8687 size(4);
8688 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8689 ins_encode(SetHi22(0x43300000, dst));
8690 ins_pipe(ialu_none);
8691 %}
8692
8693 // Magic constant, 0x41f00000
8694 instruct loadConI_x41f00000(iRegI dst) %{
8695 effect(DEF dst);
8696 size(4);
8697 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8698 ins_encode(SetHi22(0x41f00000, dst));
8699 ins_pipe(ialu_none);
8700 %}
8701
8702 // Construct a double from two float halves
8703 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8704 effect(DEF dst, USE src1, USE src2);
8705 size(8);
8706 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8707 "FMOVS $src2.lo,$dst.lo" %}
8708 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8709 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8710 ins_pipe(faddD_reg_reg);
8711 %}
8712
8713 // Convert integer in high half of a double register (in the lower half of
8714 // the double register file) to double
8715 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8716 effect(DEF dst, USE src);
8717 size(4);
8718 format %{ "FITOD $src,$dst" %}
8719 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8720 ins_encode(form3_opf_rs2D_rdD(src, dst));
8721 ins_pipe(fcvtLHi2D);
8722 %}
8723
8724 // Add float double precision
8725 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8726 effect(DEF dst, USE src1, USE src2);
8727 size(4);
8728 format %{ "FADDD $src1,$src2,$dst" %}
8729 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8730 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8731 ins_pipe(faddD_reg_reg);
8732 %}
8733
8734 // Sub float double precision
8735 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8736 effect(DEF dst, USE src1, USE src2);
8737 size(4);
8738 format %{ "FSUBD $src1,$src2,$dst" %}
8739 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8740 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8741 ins_pipe(faddD_reg_reg);
8742 %}
8743
8744 // Mul float double precision
8745 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8746 effect(DEF dst, USE src1, USE src2);
8747 size(4);
8748 format %{ "FMULD $src1,$src2,$dst" %}
8749 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8750 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8751 ins_pipe(fmulD_reg_reg);
8752 %}
8753
8754 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8755 match(Set dst (ConvL2D src));
8756 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8757
8758 expand %{
8759 regD_low tmpsrc;
8760 iRegI ix43300000;
8761 iRegI ix41f00000;
8762 stackSlotL lx43300000;
8763 stackSlotL lx41f00000;
8764 regD_low dx43300000;
8765 regD dx41f00000;
8766 regD tmp1;
8767 regD_low tmp2;
8768 regD tmp3;
8769 regD tmp4;
8770
8771 stkL_to_regD(tmpsrc, src);
8772
8773 loadConI_x43300000(ix43300000);
8774 loadConI_x41f00000(ix41f00000);
8775 regI_to_stkLHi(lx43300000, ix43300000);
8776 regI_to_stkLHi(lx41f00000, ix41f00000);
8777 stkL_to_regD(dx43300000, lx43300000);
8778 stkL_to_regD(dx41f00000, lx41f00000);
8779
8780 convI2D_regDHi_regD(tmp1, tmpsrc);
8781 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8782 subD_regD_regD(tmp3, tmp2, dx43300000);
8783 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8784 addD_regD_regD(dst, tmp3, tmp4);
8785 %}
8786 %}
8787
8788 // Long to Double conversion using fast fxtof
8789 instruct convL2D_helper(regD dst, regD tmp) %{
8790 effect(DEF dst, USE tmp);
8791 size(4);
8792 format %{ "FXTOD $tmp,$dst" %}
8793 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8794 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8795 ins_pipe(fcvtL2D);
8796 %}
8797
8798 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8799 predicate(VM_Version::has_fast_fxtof());
8800 match(Set dst (ConvL2D src));
8801 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8802 expand %{
8803 regD tmp;
8804 stkL_to_regD(tmp, src);
8805 convL2D_helper(dst, tmp);
8806 %}
8807 %}
8808
8809 instruct convL2D_reg(regD dst, iRegL src) %{
8810 predicate(UseVIS >= 3);
8811 match(Set dst (ConvL2D src));
8812 expand %{
8813 regD tmp;
8814 MoveL2D_reg_reg(tmp, src);
8815 convL2D_helper(dst, tmp);
8816 %}
8817 %}
8818
8819 // Long to Float conversion using fast fxtof
8820 instruct convL2F_helper(regF dst, regD tmp) %{
8821 effect(DEF dst, USE tmp);
8822 size(4);
8823 format %{ "FXTOS $tmp,$dst" %}
8824 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8825 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8826 ins_pipe(fcvtL2F);
8827 %}
8828
8829 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8830 match(Set dst (ConvL2F src));
8831 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8832 expand %{
8833 regD tmp;
8834 stkL_to_regD(tmp, src);
8835 convL2F_helper(dst, tmp);
8836 %}
8837 %}
8838
8839 instruct convL2F_reg(regF dst, iRegL src) %{
8840 predicate(UseVIS >= 3);
8841 match(Set dst (ConvL2F src));
8842 ins_cost(DEFAULT_COST);
8843 expand %{
8844 regD tmp;
8845 MoveL2D_reg_reg(tmp, src);
8846 convL2F_helper(dst, tmp);
8847 %}
8848 %}
8849
8850 //-----------
8851
8852 instruct convL2I_reg(iRegI dst, iRegL src) %{
8853 match(Set dst (ConvL2I src));
8854 #ifndef _LP64
8855 format %{ "MOV $src.lo,$dst\t! long->int" %}
8856 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8857 ins_pipe(ialu_move_reg_I_to_L);
8858 #else
8859 size(4);
8860 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8861 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8862 ins_pipe(ialu_reg);
8863 #endif
8864 %}
8865
8866 // Register Shift Right Immediate
8867 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8868 match(Set dst (ConvL2I (RShiftL src cnt)));
8869
8870 size(4);
8871 format %{ "SRAX $src,$cnt,$dst" %}
8872 opcode(Assembler::srax_op3, Assembler::arith_op);
8873 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8874 ins_pipe(ialu_reg_imm);
8875 %}
8876
8877 //----------Control Flow Instructions------------------------------------------
8878 // Compare Instructions
8879 // Compare Integers
8880 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8881 match(Set icc (CmpI op1 op2));
8882 effect( DEF icc, USE op1, USE op2 );
8883
8884 size(4);
8885 format %{ "CMP $op1,$op2" %}
8886 opcode(Assembler::subcc_op3, Assembler::arith_op);
8887 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8888 ins_pipe(ialu_cconly_reg_reg);
8889 %}
8890
8891 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8892 match(Set icc (CmpU op1 op2));
8893
8894 size(4);
8895 format %{ "CMP $op1,$op2\t! unsigned" %}
8896 opcode(Assembler::subcc_op3, Assembler::arith_op);
8897 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8898 ins_pipe(ialu_cconly_reg_reg);
8899 %}
8900
8901 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8902 match(Set icc (CmpI op1 op2));
8903 effect( DEF icc, USE op1 );
8904
8905 size(4);
8906 format %{ "CMP $op1,$op2" %}
8907 opcode(Assembler::subcc_op3, Assembler::arith_op);
8908 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8909 ins_pipe(ialu_cconly_reg_imm);
8910 %}
8911
8912 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8913 match(Set icc (CmpI (AndI op1 op2) zero));
8914
8915 size(4);
8916 format %{ "BTST $op2,$op1" %}
8917 opcode(Assembler::andcc_op3, Assembler::arith_op);
8918 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8919 ins_pipe(ialu_cconly_reg_reg_zero);
8920 %}
8921
8922 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8923 match(Set icc (CmpI (AndI op1 op2) zero));
8924
8925 size(4);
8926 format %{ "BTST $op2,$op1" %}
8927 opcode(Assembler::andcc_op3, Assembler::arith_op);
8928 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8929 ins_pipe(ialu_cconly_reg_imm_zero);
8930 %}
8931
8932 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8933 match(Set xcc (CmpL op1 op2));
8934 effect( DEF xcc, USE op1, USE op2 );
8935
8936 size(4);
8937 format %{ "CMP $op1,$op2\t\t! long" %}
8938 opcode(Assembler::subcc_op3, Assembler::arith_op);
8939 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8940 ins_pipe(ialu_cconly_reg_reg);
8941 %}
8942
8943 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8944 match(Set xcc (CmpL op1 con));
8945 effect( DEF xcc, USE op1, USE con );
8946
8947 size(4);
8948 format %{ "CMP $op1,$con\t\t! long" %}
8949 opcode(Assembler::subcc_op3, Assembler::arith_op);
8950 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8951 ins_pipe(ialu_cconly_reg_reg);
8952 %}
8953
8954 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8955 match(Set xcc (CmpL (AndL op1 op2) zero));
8956 effect( DEF xcc, USE op1, USE op2 );
8957
8958 size(4);
8959 format %{ "BTST $op1,$op2\t\t! long" %}
8960 opcode(Assembler::andcc_op3, Assembler::arith_op);
8961 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8962 ins_pipe(ialu_cconly_reg_reg);
8963 %}
8964
8965 // useful for checking the alignment of a pointer:
8966 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8967 match(Set xcc (CmpL (AndL op1 con) zero));
8968 effect( DEF xcc, USE op1, USE con );
8969
8970 size(4);
8971 format %{ "BTST $op1,$con\t\t! long" %}
8972 opcode(Assembler::andcc_op3, Assembler::arith_op);
8973 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8974 ins_pipe(ialu_cconly_reg_reg);
8975 %}
8976
8977 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8978 match(Set icc (CmpU op1 op2));
8979
8980 size(4);
8981 format %{ "CMP $op1,$op2\t! unsigned" %}
8982 opcode(Assembler::subcc_op3, Assembler::arith_op);
8983 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8984 ins_pipe(ialu_cconly_reg_imm);
8985 %}
8986
8987 // Compare Pointers
8988 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8989 match(Set pcc (CmpP op1 op2));
8990
8991 size(4);
8992 format %{ "CMP $op1,$op2\t! ptr" %}
8993 opcode(Assembler::subcc_op3, Assembler::arith_op);
8994 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8995 ins_pipe(ialu_cconly_reg_reg);
8996 %}
8997
8998 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8999 match(Set pcc (CmpP op1 op2));
9000
9001 size(4);
9002 format %{ "CMP $op1,$op2\t! ptr" %}
9003 opcode(Assembler::subcc_op3, Assembler::arith_op);
9004 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9005 ins_pipe(ialu_cconly_reg_imm);
9006 %}
9007
9008 // Compare Narrow oops
9009 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9010 match(Set icc (CmpN op1 op2));
9011
9012 size(4);
9013 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9014 opcode(Assembler::subcc_op3, Assembler::arith_op);
9015 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9016 ins_pipe(ialu_cconly_reg_reg);
9017 %}
9018
9019 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9020 match(Set icc (CmpN op1 op2));
9021
9022 size(4);
9023 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9024 opcode(Assembler::subcc_op3, Assembler::arith_op);
9025 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9026 ins_pipe(ialu_cconly_reg_imm);
9027 %}
9028
9029 //----------Max and Min--------------------------------------------------------
9030 // Min Instructions
9031 // Conditional move for min
9032 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9033 effect( USE_DEF op2, USE op1, USE icc );
9034
9035 size(4);
9036 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9037 opcode(Assembler::less);
9038 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9039 ins_pipe(ialu_reg_flags);
9040 %}
9041
9042 // Min Register with Register.
9043 instruct minI_eReg(iRegI op1, iRegI op2) %{
9044 match(Set op2 (MinI op1 op2));
9045 ins_cost(DEFAULT_COST*2);
9046 expand %{
9047 flagsReg icc;
9048 compI_iReg(icc,op1,op2);
9049 cmovI_reg_lt(op2,op1,icc);
9050 %}
9051 %}
9052
9053 // Max Instructions
9054 // Conditional move for max
9055 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9056 effect( USE_DEF op2, USE op1, USE icc );
9057 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9058 opcode(Assembler::greater);
9059 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9060 ins_pipe(ialu_reg_flags);
9061 %}
9062
9063 // Max Register with Register
9064 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9065 match(Set op2 (MaxI op1 op2));
9066 ins_cost(DEFAULT_COST*2);
9067 expand %{
9068 flagsReg icc;
9069 compI_iReg(icc,op1,op2);
9070 cmovI_reg_gt(op2,op1,icc);
9071 %}
9072 %}
9073
9074
9075 //----------Float Compares----------------------------------------------------
9076 // Compare floating, generate condition code
9077 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9078 match(Set fcc (CmpF src1 src2));
9079
9080 size(4);
9081 format %{ "FCMPs $fcc,$src1,$src2" %}
9082 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9083 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9084 ins_pipe(faddF_fcc_reg_reg_zero);
9085 %}
9086
9087 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9088 match(Set fcc (CmpD src1 src2));
9089
9090 size(4);
9091 format %{ "FCMPd $fcc,$src1,$src2" %}
9092 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9093 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9094 ins_pipe(faddD_fcc_reg_reg_zero);
9095 %}
9096
9097
9098 // Compare floating, generate -1,0,1
9099 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9100 match(Set dst (CmpF3 src1 src2));
9101 effect(KILL fcc0);
9102 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9103 format %{ "fcmpl $dst,$src1,$src2" %}
9104 // Primary = float
9105 opcode( true );
9106 ins_encode( floating_cmp( dst, src1, src2 ) );
9107 ins_pipe( floating_cmp );
9108 %}
9109
9110 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9111 match(Set dst (CmpD3 src1 src2));
9112 effect(KILL fcc0);
9113 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9114 format %{ "dcmpl $dst,$src1,$src2" %}
9115 // Primary = double (not float)
9116 opcode( false );
9117 ins_encode( floating_cmp( dst, src1, src2 ) );
9118 ins_pipe( floating_cmp );
9119 %}
9120
9121 //----------Branches---------------------------------------------------------
9122 // Jump
9123 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9124 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9125 match(Jump switch_val);
9126 effect(TEMP table);
9127
9128 ins_cost(350);
9129
9130 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9131 "LD [O7 + $switch_val], O7\n\t"
9132 "JUMP O7" %}
9133 ins_encode %{
9134 // Calculate table address into a register.
9135 Register table_reg;
9136 Register label_reg = O7;
9137 // If we are calculating the size of this instruction don't trust
9138 // zero offsets because they might change when
9139 // MachConstantBaseNode decides to optimize the constant table
9140 // base.
9141 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9142 table_reg = $constanttablebase;
9143 } else {
9144 table_reg = O7;
9145 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9146 __ add($constanttablebase, con_offset, table_reg);
9147 }
9148
9149 // Jump to base address + switch value
9150 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9151 __ jmp(label_reg, G0);
9152 __ delayed()->nop();
9153 %}
9154 ins_pipe(ialu_reg_reg);
9155 %}
9156
9157 // Direct Branch. Use V8 version with longer range.
9158 instruct branch(label labl) %{
9159 match(Goto);
9160 effect(USE labl);
9161
9162 size(8);
9163 ins_cost(BRANCH_COST);
9164 format %{ "BA $labl" %}
9165 ins_encode %{
9166 Label* L = $labl$$label;
9167 __ ba(*L);
9168 __ delayed()->nop();
9169 %}
9170 ins_pipe(br);
9171 %}
9172
9173 // Direct Branch, short with no delay slot
9174 instruct branch_short(label labl) %{
9175 match(Goto);
9176 predicate(UseCBCond);
9177 effect(USE labl);
9178
9179 size(4);
9180 ins_cost(BRANCH_COST);
9181 format %{ "BA $labl\t! short branch" %}
9182 ins_encode %{
9183 Label* L = $labl$$label;
9184 assert(__ use_cbcond(*L), "back to back cbcond");
9185 __ ba_short(*L);
9186 %}
9187 ins_short_branch(1);
9188 ins_avoid_back_to_back(1);
9189 ins_pipe(cbcond_reg_imm);
9190 %}
9191
9192 // Conditional Direct Branch
9193 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9194 match(If cmp icc);
9195 effect(USE labl);
9196
9197 size(8);
9198 ins_cost(BRANCH_COST);
9199 format %{ "BP$cmp $icc,$labl" %}
9200 // Prim = bits 24-22, Secnd = bits 31-30
9201 ins_encode( enc_bp( labl, cmp, icc ) );
9202 ins_pipe(br_cc);
9203 %}
9204
9205 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9206 match(If cmp icc);
9207 effect(USE labl);
9208
9209 ins_cost(BRANCH_COST);
9210 format %{ "BP$cmp $icc,$labl" %}
9211 // Prim = bits 24-22, Secnd = bits 31-30
9212 ins_encode( enc_bp( labl, cmp, icc ) );
9213 ins_pipe(br_cc);
9214 %}
9215
9216 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9217 match(If cmp pcc);
9218 effect(USE labl);
9219
9220 size(8);
9221 ins_cost(BRANCH_COST);
9222 format %{ "BP$cmp $pcc,$labl" %}
9223 ins_encode %{
9224 Label* L = $labl$$label;
9225 Assembler::Predict predict_taken =
9226 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9227
9228 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9229 __ delayed()->nop();
9230 %}
9231 ins_pipe(br_cc);
9232 %}
9233
9234 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9235 match(If cmp fcc);
9236 effect(USE labl);
9237
9238 size(8);
9239 ins_cost(BRANCH_COST);
9240 format %{ "FBP$cmp $fcc,$labl" %}
9241 ins_encode %{
9242 Label* L = $labl$$label;
9243 Assembler::Predict predict_taken =
9244 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9245
9246 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9247 __ delayed()->nop();
9248 %}
9249 ins_pipe(br_fcc);
9250 %}
9251
9252 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9253 match(CountedLoopEnd cmp icc);
9254 effect(USE labl);
9255
9256 size(8);
9257 ins_cost(BRANCH_COST);
9258 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9259 // Prim = bits 24-22, Secnd = bits 31-30
9260 ins_encode( enc_bp( labl, cmp, icc ) );
9261 ins_pipe(br_cc);
9262 %}
9263
9264 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9265 match(CountedLoopEnd cmp icc);
9266 effect(USE labl);
9267
9268 size(8);
9269 ins_cost(BRANCH_COST);
9270 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9271 // Prim = bits 24-22, Secnd = bits 31-30
9272 ins_encode( enc_bp( labl, cmp, icc ) );
9273 ins_pipe(br_cc);
9274 %}
9275
9276 // Compare and branch instructions
9277 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9278 match(If cmp (CmpI op1 op2));
9279 effect(USE labl, KILL icc);
9280
9281 size(12);
9282 ins_cost(BRANCH_COST);
9283 format %{ "CMP $op1,$op2\t! int\n\t"
9284 "BP$cmp $labl" %}
9285 ins_encode %{
9286 Label* L = $labl$$label;
9287 Assembler::Predict predict_taken =
9288 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9289 __ cmp($op1$$Register, $op2$$Register);
9290 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9291 __ delayed()->nop();
9292 %}
9293 ins_pipe(cmp_br_reg_reg);
9294 %}
9295
9296 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9297 match(If cmp (CmpI op1 op2));
9298 effect(USE labl, KILL icc);
9299
9300 size(12);
9301 ins_cost(BRANCH_COST);
9302 format %{ "CMP $op1,$op2\t! int\n\t"
9303 "BP$cmp $labl" %}
9304 ins_encode %{
9305 Label* L = $labl$$label;
9306 Assembler::Predict predict_taken =
9307 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9308 __ cmp($op1$$Register, $op2$$constant);
9309 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9310 __ delayed()->nop();
9311 %}
9312 ins_pipe(cmp_br_reg_imm);
9313 %}
9314
9315 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9316 match(If cmp (CmpU op1 op2));
9317 effect(USE labl, KILL icc);
9318
9319 size(12);
9320 ins_cost(BRANCH_COST);
9321 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9322 "BP$cmp $labl" %}
9323 ins_encode %{
9324 Label* L = $labl$$label;
9325 Assembler::Predict predict_taken =
9326 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9327 __ cmp($op1$$Register, $op2$$Register);
9328 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9329 __ delayed()->nop();
9330 %}
9331 ins_pipe(cmp_br_reg_reg);
9332 %}
9333
9334 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9335 match(If cmp (CmpU op1 op2));
9336 effect(USE labl, KILL icc);
9337
9338 size(12);
9339 ins_cost(BRANCH_COST);
9340 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9341 "BP$cmp $labl" %}
9342 ins_encode %{
9343 Label* L = $labl$$label;
9344 Assembler::Predict predict_taken =
9345 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9346 __ cmp($op1$$Register, $op2$$constant);
9347 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9348 __ delayed()->nop();
9349 %}
9350 ins_pipe(cmp_br_reg_imm);
9351 %}
9352
9353 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9354 match(If cmp (CmpL op1 op2));
9355 effect(USE labl, KILL xcc);
9356
9357 size(12);
9358 ins_cost(BRANCH_COST);
9359 format %{ "CMP $op1,$op2\t! long\n\t"
9360 "BP$cmp $labl" %}
9361 ins_encode %{
9362 Label* L = $labl$$label;
9363 Assembler::Predict predict_taken =
9364 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9365 __ cmp($op1$$Register, $op2$$Register);
9366 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9367 __ delayed()->nop();
9368 %}
9369 ins_pipe(cmp_br_reg_reg);
9370 %}
9371
9372 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9373 match(If cmp (CmpL op1 op2));
9374 effect(USE labl, KILL xcc);
9375
9376 size(12);
9377 ins_cost(BRANCH_COST);
9378 format %{ "CMP $op1,$op2\t! long\n\t"
9379 "BP$cmp $labl" %}
9380 ins_encode %{
9381 Label* L = $labl$$label;
9382 Assembler::Predict predict_taken =
9383 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9384 __ cmp($op1$$Register, $op2$$constant);
9385 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9386 __ delayed()->nop();
9387 %}
9388 ins_pipe(cmp_br_reg_imm);
9389 %}
9390
9391 // Compare Pointers and branch
9392 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9393 match(If cmp (CmpP op1 op2));
9394 effect(USE labl, KILL pcc);
9395
9396 size(12);
9397 ins_cost(BRANCH_COST);
9398 format %{ "CMP $op1,$op2\t! ptr\n\t"
9399 "B$cmp $labl" %}
9400 ins_encode %{
9401 Label* L = $labl$$label;
9402 Assembler::Predict predict_taken =
9403 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9404 __ cmp($op1$$Register, $op2$$Register);
9405 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9406 __ delayed()->nop();
9407 %}
9408 ins_pipe(cmp_br_reg_reg);
9409 %}
9410
9411 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9412 match(If cmp (CmpP op1 null));
9413 effect(USE labl, KILL pcc);
9414
9415 size(12);
9416 ins_cost(BRANCH_COST);
9417 format %{ "CMP $op1,0\t! ptr\n\t"
9418 "B$cmp $labl" %}
9419 ins_encode %{
9420 Label* L = $labl$$label;
9421 Assembler::Predict predict_taken =
9422 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9423 __ cmp($op1$$Register, G0);
9424 // bpr() is not used here since it has shorter distance.
9425 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9426 __ delayed()->nop();
9427 %}
9428 ins_pipe(cmp_br_reg_reg);
9429 %}
9430
9431 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9432 match(If cmp (CmpN op1 op2));
9433 effect(USE labl, KILL icc);
9434
9435 size(12);
9436 ins_cost(BRANCH_COST);
9437 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9438 "BP$cmp $labl" %}
9439 ins_encode %{
9440 Label* L = $labl$$label;
9441 Assembler::Predict predict_taken =
9442 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9443 __ cmp($op1$$Register, $op2$$Register);
9444 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9445 __ delayed()->nop();
9446 %}
9447 ins_pipe(cmp_br_reg_reg);
9448 %}
9449
9450 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9451 match(If cmp (CmpN op1 null));
9452 effect(USE labl, KILL icc);
9453
9454 size(12);
9455 ins_cost(BRANCH_COST);
9456 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9457 "BP$cmp $labl" %}
9458 ins_encode %{
9459 Label* L = $labl$$label;
9460 Assembler::Predict predict_taken =
9461 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9462 __ cmp($op1$$Register, G0);
9463 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9464 __ delayed()->nop();
9465 %}
9466 ins_pipe(cmp_br_reg_reg);
9467 %}
9468
9469 // Loop back branch
9470 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9471 match(CountedLoopEnd cmp (CmpI op1 op2));
9472 effect(USE labl, KILL icc);
9473
9474 size(12);
9475 ins_cost(BRANCH_COST);
9476 format %{ "CMP $op1,$op2\t! int\n\t"
9477 "BP$cmp $labl\t! Loop end" %}
9478 ins_encode %{
9479 Label* L = $labl$$label;
9480 Assembler::Predict predict_taken =
9481 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9482 __ cmp($op1$$Register, $op2$$Register);
9483 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9484 __ delayed()->nop();
9485 %}
9486 ins_pipe(cmp_br_reg_reg);
9487 %}
9488
9489 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9490 match(CountedLoopEnd cmp (CmpI op1 op2));
9491 effect(USE labl, KILL icc);
9492
9493 size(12);
9494 ins_cost(BRANCH_COST);
9495 format %{ "CMP $op1,$op2\t! int\n\t"
9496 "BP$cmp $labl\t! Loop end" %}
9497 ins_encode %{
9498 Label* L = $labl$$label;
9499 Assembler::Predict predict_taken =
9500 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9501 __ cmp($op1$$Register, $op2$$constant);
9502 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9503 __ delayed()->nop();
9504 %}
9505 ins_pipe(cmp_br_reg_imm);
9506 %}
9507
9508 // Short compare and branch instructions
9509 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9510 match(If cmp (CmpI op1 op2));
9511 predicate(UseCBCond);
9512 effect(USE labl, KILL icc);
9513
9514 size(4);
9515 ins_cost(BRANCH_COST);
9516 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9517 ins_encode %{
9518 Label* L = $labl$$label;
9519 assert(__ use_cbcond(*L), "back to back cbcond");
9520 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9521 %}
9522 ins_short_branch(1);
9523 ins_avoid_back_to_back(1);
9524 ins_pipe(cbcond_reg_reg);
9525 %}
9526
9527 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9528 match(If cmp (CmpI op1 op2));
9529 predicate(UseCBCond);
9530 effect(USE labl, KILL icc);
9531
9532 size(4);
9533 ins_cost(BRANCH_COST);
9534 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9535 ins_encode %{
9536 Label* L = $labl$$label;
9537 assert(__ use_cbcond(*L), "back to back cbcond");
9538 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9539 %}
9540 ins_short_branch(1);
9541 ins_avoid_back_to_back(1);
9542 ins_pipe(cbcond_reg_imm);
9543 %}
9544
9545 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9546 match(If cmp (CmpU op1 op2));
9547 predicate(UseCBCond);
9548 effect(USE labl, KILL icc);
9549
9550 size(4);
9551 ins_cost(BRANCH_COST);
9552 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9553 ins_encode %{
9554 Label* L = $labl$$label;
9555 assert(__ use_cbcond(*L), "back to back cbcond");
9556 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9557 %}
9558 ins_short_branch(1);
9559 ins_avoid_back_to_back(1);
9560 ins_pipe(cbcond_reg_reg);
9561 %}
9562
9563 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9564 match(If cmp (CmpU op1 op2));
9565 predicate(UseCBCond);
9566 effect(USE labl, KILL icc);
9567
9568 size(4);
9569 ins_cost(BRANCH_COST);
9570 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9571 ins_encode %{
9572 Label* L = $labl$$label;
9573 assert(__ use_cbcond(*L), "back to back cbcond");
9574 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9575 %}
9576 ins_short_branch(1);
9577 ins_avoid_back_to_back(1);
9578 ins_pipe(cbcond_reg_imm);
9579 %}
9580
9581 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9582 match(If cmp (CmpL op1 op2));
9583 predicate(UseCBCond);
9584 effect(USE labl, KILL xcc);
9585
9586 size(4);
9587 ins_cost(BRANCH_COST);
9588 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9589 ins_encode %{
9590 Label* L = $labl$$label;
9591 assert(__ use_cbcond(*L), "back to back cbcond");
9592 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9593 %}
9594 ins_short_branch(1);
9595 ins_avoid_back_to_back(1);
9596 ins_pipe(cbcond_reg_reg);
9597 %}
9598
9599 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9600 match(If cmp (CmpL op1 op2));
9601 predicate(UseCBCond);
9602 effect(USE labl, KILL xcc);
9603
9604 size(4);
9605 ins_cost(BRANCH_COST);
9606 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9607 ins_encode %{
9608 Label* L = $labl$$label;
9609 assert(__ use_cbcond(*L), "back to back cbcond");
9610 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9611 %}
9612 ins_short_branch(1);
9613 ins_avoid_back_to_back(1);
9614 ins_pipe(cbcond_reg_imm);
9615 %}
9616
9617 // Compare Pointers and branch
9618 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9619 match(If cmp (CmpP op1 op2));
9620 predicate(UseCBCond);
9621 effect(USE labl, KILL pcc);
9622
9623 size(4);
9624 ins_cost(BRANCH_COST);
9625 #ifdef _LP64
9626 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9627 #else
9628 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9629 #endif
9630 ins_encode %{
9631 Label* L = $labl$$label;
9632 assert(__ use_cbcond(*L), "back to back cbcond");
9633 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9634 %}
9635 ins_short_branch(1);
9636 ins_avoid_back_to_back(1);
9637 ins_pipe(cbcond_reg_reg);
9638 %}
9639
9640 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9641 match(If cmp (CmpP op1 null));
9642 predicate(UseCBCond);
9643 effect(USE labl, KILL pcc);
9644
9645 size(4);
9646 ins_cost(BRANCH_COST);
9647 #ifdef _LP64
9648 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9649 #else
9650 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9651 #endif
9652 ins_encode %{
9653 Label* L = $labl$$label;
9654 assert(__ use_cbcond(*L), "back to back cbcond");
9655 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9656 %}
9657 ins_short_branch(1);
9658 ins_avoid_back_to_back(1);
9659 ins_pipe(cbcond_reg_reg);
9660 %}
9661
9662 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9663 match(If cmp (CmpN op1 op2));
9664 predicate(UseCBCond);
9665 effect(USE labl, KILL icc);
9666
9667 size(4);
9668 ins_cost(BRANCH_COST);
9669 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9670 ins_encode %{
9671 Label* L = $labl$$label;
9672 assert(__ use_cbcond(*L), "back to back cbcond");
9673 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9674 %}
9675 ins_short_branch(1);
9676 ins_avoid_back_to_back(1);
9677 ins_pipe(cbcond_reg_reg);
9678 %}
9679
9680 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9681 match(If cmp (CmpN op1 null));
9682 predicate(UseCBCond);
9683 effect(USE labl, KILL icc);
9684
9685 size(4);
9686 ins_cost(BRANCH_COST);
9687 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9688 ins_encode %{
9689 Label* L = $labl$$label;
9690 assert(__ use_cbcond(*L), "back to back cbcond");
9691 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9692 %}
9693 ins_short_branch(1);
9694 ins_avoid_back_to_back(1);
9695 ins_pipe(cbcond_reg_reg);
9696 %}
9697
9698 // Loop back branch
9699 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9700 match(CountedLoopEnd cmp (CmpI op1 op2));
9701 predicate(UseCBCond);
9702 effect(USE labl, KILL icc);
9703
9704 size(4);
9705 ins_cost(BRANCH_COST);
9706 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9707 ins_encode %{
9708 Label* L = $labl$$label;
9709 assert(__ use_cbcond(*L), "back to back cbcond");
9710 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9711 %}
9712 ins_short_branch(1);
9713 ins_avoid_back_to_back(1);
9714 ins_pipe(cbcond_reg_reg);
9715 %}
9716
9717 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9718 match(CountedLoopEnd cmp (CmpI op1 op2));
9719 predicate(UseCBCond);
9720 effect(USE labl, KILL icc);
9721
9722 size(4);
9723 ins_cost(BRANCH_COST);
9724 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9725 ins_encode %{
9726 Label* L = $labl$$label;
9727 assert(__ use_cbcond(*L), "back to back cbcond");
9728 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9729 %}
9730 ins_short_branch(1);
9731 ins_avoid_back_to_back(1);
9732 ins_pipe(cbcond_reg_imm);
9733 %}
9734
9735 // Branch-on-register tests all 64 bits. We assume that values
9736 // in 64-bit registers always remains zero or sign extended
9737 // unless our code munges the high bits. Interrupts can chop
9738 // the high order bits to zero or sign at any time.
9739 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9740 match(If cmp (CmpI op1 zero));
9741 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9742 effect(USE labl);
9743
9744 size(8);
9745 ins_cost(BRANCH_COST);
9746 format %{ "BR$cmp $op1,$labl" %}
9747 ins_encode( enc_bpr( labl, cmp, op1 ) );
9748 ins_pipe(br_reg);
9749 %}
9750
9751 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9752 match(If cmp (CmpP op1 null));
9753 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9754 effect(USE labl);
9755
9756 size(8);
9757 ins_cost(BRANCH_COST);
9758 format %{ "BR$cmp $op1,$labl" %}
9759 ins_encode( enc_bpr( labl, cmp, op1 ) );
9760 ins_pipe(br_reg);
9761 %}
9762
9763 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9764 match(If cmp (CmpL op1 zero));
9765 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9766 effect(USE labl);
9767
9768 size(8);
9769 ins_cost(BRANCH_COST);
9770 format %{ "BR$cmp $op1,$labl" %}
9771 ins_encode( enc_bpr( labl, cmp, op1 ) );
9772 ins_pipe(br_reg);
9773 %}
9774
9775
9776 // ============================================================================
9777 // Long Compare
9778 //
9779 // Currently we hold longs in 2 registers. Comparing such values efficiently
9780 // is tricky. The flavor of compare used depends on whether we are testing
9781 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9782 // The GE test is the negated LT test. The LE test can be had by commuting
9783 // the operands (yielding a GE test) and then negating; negate again for the
9784 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9785 // NE test is negated from that.
9786
9787 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9788 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9789 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9790 // are collapsed internally in the ADLC's dfa-gen code. The match for
9791 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9792 // foo match ends up with the wrong leaf. One fix is to not match both
9793 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9794 // both forms beat the trinary form of long-compare and both are very useful
9795 // on Intel which has so few registers.
9796
9797 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9798 match(If cmp xcc);
9799 effect(USE labl);
9800
9801 size(8);
9802 ins_cost(BRANCH_COST);
9803 format %{ "BP$cmp $xcc,$labl" %}
9804 ins_encode %{
9805 Label* L = $labl$$label;
9806 Assembler::Predict predict_taken =
9807 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9808
9809 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9810 __ delayed()->nop();
9811 %}
9812 ins_pipe(br_cc);
9813 %}
9814
9815 // Manifest a CmpL3 result in an integer register. Very painful.
9816 // This is the test to avoid.
9817 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9818 match(Set dst (CmpL3 src1 src2) );
9819 effect( KILL ccr );
9820 ins_cost(6*DEFAULT_COST);
9821 size(24);
9822 format %{ "CMP $src1,$src2\t\t! long\n"
9823 "\tBLT,a,pn done\n"
9824 "\tMOV -1,$dst\t! delay slot\n"
9825 "\tBGT,a,pn done\n"
9826 "\tMOV 1,$dst\t! delay slot\n"
9827 "\tCLR $dst\n"
9828 "done:" %}
9829 ins_encode( cmpl_flag(src1,src2,dst) );
9830 ins_pipe(cmpL_reg);
9831 %}
9832
9833 // Conditional move
9834 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9835 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9836 ins_cost(150);
9837 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9838 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9839 ins_pipe(ialu_reg);
9840 %}
9841
9842 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9843 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9844 ins_cost(140);
9845 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9846 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9847 ins_pipe(ialu_imm);
9848 %}
9849
9850 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9851 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9852 ins_cost(150);
9853 format %{ "MOV$cmp $xcc,$src,$dst" %}
9854 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9855 ins_pipe(ialu_reg);
9856 %}
9857
9858 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9859 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9860 ins_cost(140);
9861 format %{ "MOV$cmp $xcc,$src,$dst" %}
9862 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9863 ins_pipe(ialu_imm);
9864 %}
9865
9866 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9867 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9868 ins_cost(150);
9869 format %{ "MOV$cmp $xcc,$src,$dst" %}
9870 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9871 ins_pipe(ialu_reg);
9872 %}
9873
9874 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9875 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9876 ins_cost(150);
9877 format %{ "MOV$cmp $xcc,$src,$dst" %}
9878 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9879 ins_pipe(ialu_reg);
9880 %}
9881
9882 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9883 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9884 ins_cost(140);
9885 format %{ "MOV$cmp $xcc,$src,$dst" %}
9886 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9887 ins_pipe(ialu_imm);
9888 %}
9889
9890 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9891 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9892 ins_cost(150);
9893 opcode(0x101);
9894 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9895 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9896 ins_pipe(int_conditional_float_move);
9897 %}
9898
9899 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9900 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9901 ins_cost(150);
9902 opcode(0x102);
9903 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9904 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9905 ins_pipe(int_conditional_float_move);
9906 %}
9907
9908 // ============================================================================
9909 // Safepoint Instruction
9910 instruct safePoint_poll(iRegP poll) %{
9911 match(SafePoint poll);
9912 effect(USE poll);
9913
9914 size(4);
9915 #ifdef _LP64
9916 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9917 #else
9918 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9919 #endif
9920 ins_encode %{
9921 __ relocate(relocInfo::poll_type);
9922 __ ld_ptr($poll$$Register, 0, G0);
9923 %}
9924 ins_pipe(loadPollP);
9925 %}
9926
9927 // ============================================================================
9928 // Call Instructions
9929 // Call Java Static Instruction
9930 instruct CallStaticJavaDirect( method meth ) %{
9931 match(CallStaticJava);
9932 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9933 effect(USE meth);
9934
9935 size(8);
9936 ins_cost(CALL_COST);
9937 format %{ "CALL,static ; NOP ==> " %}
9938 ins_encode( Java_Static_Call( meth ), call_epilog );
9939 ins_pipe(simple_call);
9940 %}
9941
9942 // Call Java Static Instruction (method handle version)
9943 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9944 match(CallStaticJava);
9945 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9946 effect(USE meth, KILL l7_mh_SP_save);
9947
9948 size(16);
9949 ins_cost(CALL_COST);
9950 format %{ "CALL,static/MethodHandle" %}
9951 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9952 ins_pipe(simple_call);
9953 %}
9954
9955 // Call Java Dynamic Instruction
9956 instruct CallDynamicJavaDirect( method meth ) %{
9957 match(CallDynamicJava);
9958 effect(USE meth);
9959
9960 ins_cost(CALL_COST);
9961 format %{ "SET (empty),R_G5\n\t"
9962 "CALL,dynamic ; NOP ==> " %}
9963 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9964 ins_pipe(call);
9965 %}
9966
9967 // Call Runtime Instruction
9968 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9969 match(CallRuntime);
9970 effect(USE meth, KILL l7);
9971 ins_cost(CALL_COST);
9972 format %{ "CALL,runtime" %}
9973 ins_encode( Java_To_Runtime( meth ),
9974 call_epilog, adjust_long_from_native_call );
9975 ins_pipe(simple_call);
9976 %}
9977
9978 // Call runtime without safepoint - same as CallRuntime
9979 instruct CallLeafDirect(method meth, l7RegP l7) %{
9980 match(CallLeaf);
9981 effect(USE meth, KILL l7);
9982 ins_cost(CALL_COST);
9983 format %{ "CALL,runtime leaf" %}
9984 ins_encode( Java_To_Runtime( meth ),
9985 call_epilog,
9986 adjust_long_from_native_call );
9987 ins_pipe(simple_call);
9988 %}
9989
9990 // Call runtime without safepoint - same as CallLeaf
9991 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9992 match(CallLeafNoFP);
9993 effect(USE meth, KILL l7);
9994 ins_cost(CALL_COST);
9995 format %{ "CALL,runtime leaf nofp" %}
9996 ins_encode( Java_To_Runtime( meth ),
9997 call_epilog,
9998 adjust_long_from_native_call );
9999 ins_pipe(simple_call);
10000 %}
10001
10002 // Tail Call; Jump from runtime stub to Java code.
10003 // Also known as an 'interprocedural jump'.
10004 // Target of jump will eventually return to caller.
10005 // TailJump below removes the return address.
10006 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10007 match(TailCall jump_target method_oop );
10008
10009 ins_cost(CALL_COST);
10010 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
10011 ins_encode(form_jmpl(jump_target));
10012 ins_pipe(tail_call);
10013 %}
10014
10015
10016 // Return Instruction
10017 instruct Ret() %{
10018 match(Return);
10019
10020 // The epilogue node did the ret already.
10021 size(0);
10022 format %{ "! return" %}
10023 ins_encode();
10024 ins_pipe(empty);
10025 %}
10026
10027
10028 // Tail Jump; remove the return address; jump to target.
10029 // TailCall above leaves the return address around.
10030 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10031 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10032 // "restore" before this instruction (in Epilogue), we need to materialize it
10033 // in %i0.
10034 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10035 match( TailJump jump_target ex_oop );
10036 ins_cost(CALL_COST);
10037 format %{ "! discard R_O7\n\t"
10038 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10039 ins_encode(form_jmpl_set_exception_pc(jump_target));
10040 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10041 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10042 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10043 ins_pipe(tail_call);
10044 %}
10045
10046 // Create exception oop: created by stack-crawling runtime code.
10047 // Created exception is now available to this handler, and is setup
10048 // just prior to jumping to this handler. No code emitted.
10049 instruct CreateException( o0RegP ex_oop )
10050 %{
10051 match(Set ex_oop (CreateEx));
10052 ins_cost(0);
10053
10054 size(0);
10055 // use the following format syntax
10056 format %{ "! exception oop is in R_O0; no code emitted" %}
10057 ins_encode();
10058 ins_pipe(empty);
10059 %}
10060
10061
10062 // Rethrow exception:
10063 // The exception oop will come in the first argument position.
10064 // Then JUMP (not call) to the rethrow stub code.
10065 instruct RethrowException()
10066 %{
10067 match(Rethrow);
10068 ins_cost(CALL_COST);
10069
10070 // use the following format syntax
10071 format %{ "Jmp rethrow_stub" %}
10072 ins_encode(enc_rethrow);
10073 ins_pipe(tail_call);
10074 %}
10075
10076
10077 // Die now
10078 instruct ShouldNotReachHere( )
10079 %{
10080 match(Halt);
10081 ins_cost(CALL_COST);
10082
10083 size(4);
10084 // Use the following format syntax
10085 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10086 ins_encode( form2_illtrap() );
10087 ins_pipe(tail_call);
10088 %}
10089
10090 // ============================================================================
10091 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10092 // array for an instance of the superklass. Set a hidden internal cache on a
10093 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10094 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10095 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10096 match(Set index (PartialSubtypeCheck sub super));
10097 effect( KILL pcc, KILL o7 );
10098 ins_cost(DEFAULT_COST*10);
10099 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10100 ins_encode( enc_PartialSubtypeCheck() );
10101 ins_pipe(partial_subtype_check_pipe);
10102 %}
10103
10104 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10105 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10106 effect( KILL idx, KILL o7 );
10107 ins_cost(DEFAULT_COST*10);
10108 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10109 ins_encode( enc_PartialSubtypeCheck() );
10110 ins_pipe(partial_subtype_check_pipe);
10111 %}
10112
10113
10114 // ============================================================================
10115 // inlined locking and unlocking
10116
10117 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10118 match(Set pcc (FastLock object box));
10119
10120 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10121 ins_cost(100);
10122
10123 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10124 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10125 ins_pipe(long_memory_op);
10126 %}
10127
10128
10129 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10130 match(Set pcc (FastUnlock object box));
10131 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10132 ins_cost(100);
10133
10134 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10135 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10136 ins_pipe(long_memory_op);
10137 %}
10138
10139 // The encodings are generic.
10140 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10141 predicate(!use_block_zeroing(n->in(2)) );
10142 match(Set dummy (ClearArray cnt base));
10143 effect(TEMP temp, KILL ccr);
10144 ins_cost(300);
10145 format %{ "MOV $cnt,$temp\n"
10146 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10147 " BRge loop\t\t! Clearing loop\n"
10148 " STX G0,[$base+$temp]\t! delay slot" %}
10149
10150 ins_encode %{
10151 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10152 Register nof_bytes_arg = $cnt$$Register;
10153 Register nof_bytes_tmp = $temp$$Register;
10154 Register base_pointer_arg = $base$$Register;
10155
10156 Label loop;
10157 __ mov(nof_bytes_arg, nof_bytes_tmp);
10158
10159 // Loop and clear, walking backwards through the array.
10160 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10161 __ bind(loop);
10162 __ deccc(nof_bytes_tmp, 8);
10163 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10164 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10165 // %%%% this mini-loop must not cross a cache boundary!
10166 %}
10167 ins_pipe(long_memory_op);
10168 %}
10169
10170 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10171 predicate(use_block_zeroing(n->in(2)));
10172 match(Set dummy (ClearArray cnt base));
10173 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10174 ins_cost(300);
10175 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10176
10177 ins_encode %{
10178
10179 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10180 Register to = $base$$Register;
10181 Register count = $cnt$$Register;
10182
10183 Label Ldone;
10184 __ nop(); // Separate short branches
10185 // Use BIS for zeroing (temp is not used).
10186 __ bis_zeroing(to, count, G0, Ldone);
10187 __ bind(Ldone);
10188
10189 %}
10190 ins_pipe(long_memory_op);
10191 %}
10192
10193 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10194 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10195 match(Set dummy (ClearArray cnt base));
10196 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10197 ins_cost(300);
10198 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10199
10200 ins_encode %{
10201
10202 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10203 Register to = $base$$Register;
10204 Register count = $cnt$$Register;
10205 Register temp = $tmp$$Register;
10206
10207 Label Ldone;
10208 __ nop(); // Separate short branches
10209 // Use BIS for zeroing
10210 __ bis_zeroing(to, count, temp, Ldone);
10211 __ bind(Ldone);
10212
10213 %}
10214 ins_pipe(long_memory_op);
10215 %}
10216
10217 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10218 o7RegI tmp, flagsReg ccr) %{
10219 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10220 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10221 ins_cost(300);
10222 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10223 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10224 ins_pipe(long_memory_op);
10225 %}
10226
10227 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10228 o7RegI tmp, flagsReg ccr) %{
10229 match(Set result (StrEquals (Binary str1 str2) cnt));
10230 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10231 ins_cost(300);
10232 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10233 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10234 ins_pipe(long_memory_op);
10235 %}
10236
10237 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10238 o7RegI tmp2, flagsReg ccr) %{
10239 match(Set result (AryEq ary1 ary2));
10240 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10241 ins_cost(300);
10242 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10243 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10244 ins_pipe(long_memory_op);
10245 %}
10246
10247
10248 //---------- Zeros Count Instructions ------------------------------------------
10249
10250 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10251 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10252 match(Set dst (CountLeadingZerosI src));
10253 effect(TEMP dst, TEMP tmp, KILL cr);
10254
10255 // x |= (x >> 1);
10256 // x |= (x >> 2);
10257 // x |= (x >> 4);
10258 // x |= (x >> 8);
10259 // x |= (x >> 16);
10260 // return (WORDBITS - popc(x));
10261 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10262 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10263 "OR $dst,$tmp,$dst\n\t"
10264 "SRL $dst,2,$tmp\n\t"
10265 "OR $dst,$tmp,$dst\n\t"
10266 "SRL $dst,4,$tmp\n\t"
10267 "OR $dst,$tmp,$dst\n\t"
10268 "SRL $dst,8,$tmp\n\t"
10269 "OR $dst,$tmp,$dst\n\t"
10270 "SRL $dst,16,$tmp\n\t"
10271 "OR $dst,$tmp,$dst\n\t"
10272 "POPC $dst,$dst\n\t"
10273 "MOV 32,$tmp\n\t"
10274 "SUB $tmp,$dst,$dst" %}
10275 ins_encode %{
10276 Register Rdst = $dst$$Register;
10277 Register Rsrc = $src$$Register;
10278 Register Rtmp = $tmp$$Register;
10279 __ srl(Rsrc, 1, Rtmp);
10280 __ srl(Rsrc, 0, Rdst);
10281 __ or3(Rdst, Rtmp, Rdst);
10282 __ srl(Rdst, 2, Rtmp);
10283 __ or3(Rdst, Rtmp, Rdst);
10284 __ srl(Rdst, 4, Rtmp);
10285 __ or3(Rdst, Rtmp, Rdst);
10286 __ srl(Rdst, 8, Rtmp);
10287 __ or3(Rdst, Rtmp, Rdst);
10288 __ srl(Rdst, 16, Rtmp);
10289 __ or3(Rdst, Rtmp, Rdst);
10290 __ popc(Rdst, Rdst);
10291 __ mov(BitsPerInt, Rtmp);
10292 __ sub(Rtmp, Rdst, Rdst);
10293 %}
10294 ins_pipe(ialu_reg);
10295 %}
10296
10297 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10298 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10299 match(Set dst (CountLeadingZerosL src));
10300 effect(TEMP dst, TEMP tmp, KILL cr);
10301
10302 // x |= (x >> 1);
10303 // x |= (x >> 2);
10304 // x |= (x >> 4);
10305 // x |= (x >> 8);
10306 // x |= (x >> 16);
10307 // x |= (x >> 32);
10308 // return (WORDBITS - popc(x));
10309 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10310 "OR $src,$tmp,$dst\n\t"
10311 "SRLX $dst,2,$tmp\n\t"
10312 "OR $dst,$tmp,$dst\n\t"
10313 "SRLX $dst,4,$tmp\n\t"
10314 "OR $dst,$tmp,$dst\n\t"
10315 "SRLX $dst,8,$tmp\n\t"
10316 "OR $dst,$tmp,$dst\n\t"
10317 "SRLX $dst,16,$tmp\n\t"
10318 "OR $dst,$tmp,$dst\n\t"
10319 "SRLX $dst,32,$tmp\n\t"
10320 "OR $dst,$tmp,$dst\n\t"
10321 "POPC $dst,$dst\n\t"
10322 "MOV 64,$tmp\n\t"
10323 "SUB $tmp,$dst,$dst" %}
10324 ins_encode %{
10325 Register Rdst = $dst$$Register;
10326 Register Rsrc = $src$$Register;
10327 Register Rtmp = $tmp$$Register;
10328 __ srlx(Rsrc, 1, Rtmp);
10329 __ or3( Rsrc, Rtmp, Rdst);
10330 __ srlx(Rdst, 2, Rtmp);
10331 __ or3( Rdst, Rtmp, Rdst);
10332 __ srlx(Rdst, 4, Rtmp);
10333 __ or3( Rdst, Rtmp, Rdst);
10334 __ srlx(Rdst, 8, Rtmp);
10335 __ or3( Rdst, Rtmp, Rdst);
10336 __ srlx(Rdst, 16, Rtmp);
10337 __ or3( Rdst, Rtmp, Rdst);
10338 __ srlx(Rdst, 32, Rtmp);
10339 __ or3( Rdst, Rtmp, Rdst);
10340 __ popc(Rdst, Rdst);
10341 __ mov(BitsPerLong, Rtmp);
10342 __ sub(Rtmp, Rdst, Rdst);
10343 %}
10344 ins_pipe(ialu_reg);
10345 %}
10346
10347 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10348 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10349 match(Set dst (CountTrailingZerosI src));
10350 effect(TEMP dst, KILL cr);
10351
10352 // return popc(~x & (x - 1));
10353 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10354 "ANDN $dst,$src,$dst\n\t"
10355 "SRL $dst,R_G0,$dst\n\t"
10356 "POPC $dst,$dst" %}
10357 ins_encode %{
10358 Register Rdst = $dst$$Register;
10359 Register Rsrc = $src$$Register;
10360 __ sub(Rsrc, 1, Rdst);
10361 __ andn(Rdst, Rsrc, Rdst);
10362 __ srl(Rdst, G0, Rdst);
10363 __ popc(Rdst, Rdst);
10364 %}
10365 ins_pipe(ialu_reg);
10366 %}
10367
10368 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10369 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10370 match(Set dst (CountTrailingZerosL src));
10371 effect(TEMP dst, KILL cr);
10372
10373 // return popc(~x & (x - 1));
10374 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10375 "ANDN $dst,$src,$dst\n\t"
10376 "POPC $dst,$dst" %}
10377 ins_encode %{
10378 Register Rdst = $dst$$Register;
10379 Register Rsrc = $src$$Register;
10380 __ sub(Rsrc, 1, Rdst);
10381 __ andn(Rdst, Rsrc, Rdst);
10382 __ popc(Rdst, Rdst);
10383 %}
10384 ins_pipe(ialu_reg);
10385 %}
10386
10387
10388 //---------- Population Count Instructions -------------------------------------
10389
10390 instruct popCountI(iRegIsafe dst, iRegI src) %{
10391 predicate(UsePopCountInstruction);
10392 match(Set dst (PopCountI src));
10393
10394 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10395 "POPC $dst, $dst" %}
10396 ins_encode %{
10397 __ srl($src$$Register, G0, $dst$$Register);
10398 __ popc($dst$$Register, $dst$$Register);
10399 %}
10400 ins_pipe(ialu_reg);
10401 %}
10402
10403 // Note: Long.bitCount(long) returns an int.
10404 instruct popCountL(iRegIsafe dst, iRegL src) %{
10405 predicate(UsePopCountInstruction);
10406 match(Set dst (PopCountL src));
10407
10408 format %{ "POPC $src, $dst" %}
10409 ins_encode %{
10410 __ popc($src$$Register, $dst$$Register);
10411 %}
10412 ins_pipe(ialu_reg);
10413 %}
10414
10415
10416 // ============================================================================
10417 //------------Bytes reverse--------------------------------------------------
10418
10419 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10420 match(Set dst (ReverseBytesI src));
10421
10422 // Op cost is artificially doubled to make sure that load or store
10423 // instructions are preferred over this one which requires a spill
10424 // onto a stack slot.
10425 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10426 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10427
10428 ins_encode %{
10429 __ set($src$$disp + STACK_BIAS, O7);
10430 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10431 %}
10432 ins_pipe( iload_mem );
10433 %}
10434
10435 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10436 match(Set dst (ReverseBytesL src));
10437
10438 // Op cost is artificially doubled to make sure that load or store
10439 // instructions are preferred over this one which requires a spill
10440 // onto a stack slot.
10441 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10442 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10443
10444 ins_encode %{
10445 __ set($src$$disp + STACK_BIAS, O7);
10446 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10447 %}
10448 ins_pipe( iload_mem );
10449 %}
10450
10451 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10452 match(Set dst (ReverseBytesUS src));
10453
10454 // Op cost is artificially doubled to make sure that load or store
10455 // instructions are preferred over this one which requires a spill
10456 // onto a stack slot.
10457 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10458 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10459
10460 ins_encode %{
10461 // the value was spilled as an int so bias the load
10462 __ set($src$$disp + STACK_BIAS + 2, O7);
10463 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10464 %}
10465 ins_pipe( iload_mem );
10466 %}
10467
10468 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10469 match(Set dst (ReverseBytesS src));
10470
10471 // Op cost is artificially doubled to make sure that load or store
10472 // instructions are preferred over this one which requires a spill
10473 // onto a stack slot.
10474 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10475 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10476
10477 ins_encode %{
10478 // the value was spilled as an int so bias the load
10479 __ set($src$$disp + STACK_BIAS + 2, O7);
10480 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10481 %}
10482 ins_pipe( iload_mem );
10483 %}
10484
10485 // Load Integer reversed byte order
10486 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10487 match(Set dst (ReverseBytesI (LoadI src)));
10488
10489 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10490 size(4);
10491 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10492
10493 ins_encode %{
10494 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10495 %}
10496 ins_pipe(iload_mem);
10497 %}
10498
10499 // Load Long - aligned and reversed
10500 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10501 match(Set dst (ReverseBytesL (LoadL src)));
10502
10503 ins_cost(MEMORY_REF_COST);
10504 size(4);
10505 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10506
10507 ins_encode %{
10508 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10509 %}
10510 ins_pipe(iload_mem);
10511 %}
10512
10513 // Load unsigned short / char reversed byte order
10514 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10515 match(Set dst (ReverseBytesUS (LoadUS src)));
10516
10517 ins_cost(MEMORY_REF_COST);
10518 size(4);
10519 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10520
10521 ins_encode %{
10522 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10523 %}
10524 ins_pipe(iload_mem);
10525 %}
10526
10527 // Load short reversed byte order
10528 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10529 match(Set dst (ReverseBytesS (LoadS src)));
10530
10531 ins_cost(MEMORY_REF_COST);
10532 size(4);
10533 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10534
10535 ins_encode %{
10536 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10537 %}
10538 ins_pipe(iload_mem);
10539 %}
10540
10541 // Store Integer reversed byte order
10542 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10543 match(Set dst (StoreI dst (ReverseBytesI src)));
10544
10545 ins_cost(MEMORY_REF_COST);
10546 size(4);
10547 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10548
10549 ins_encode %{
10550 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10551 %}
10552 ins_pipe(istore_mem_reg);
10553 %}
10554
10555 // Store Long reversed byte order
10556 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10557 match(Set dst (StoreL dst (ReverseBytesL src)));
10558
10559 ins_cost(MEMORY_REF_COST);
10560 size(4);
10561 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10562
10563 ins_encode %{
10564 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10565 %}
10566 ins_pipe(istore_mem_reg);
10567 %}
10568
10569 // Store unsighed short/char reversed byte order
10570 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10571 match(Set dst (StoreC dst (ReverseBytesUS src)));
10572
10573 ins_cost(MEMORY_REF_COST);
10574 size(4);
10575 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10576
10577 ins_encode %{
10578 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10579 %}
10580 ins_pipe(istore_mem_reg);
10581 %}
10582
10583 // Store short reversed byte order
10584 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10585 match(Set dst (StoreC dst (ReverseBytesS src)));
10586
10587 ins_cost(MEMORY_REF_COST);
10588 size(4);
10589 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10590
10591 ins_encode %{
10592 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10593 %}
10594 ins_pipe(istore_mem_reg);
10595 %}
10596
10597 // ====================VECTOR INSTRUCTIONS=====================================
10598
10599 // Load Aligned Packed values into a Double Register
10600 instruct loadV8(regD dst, memory mem) %{
10601 predicate(n->as_LoadVector()->memory_size() == 8);
10602 match(Set dst (LoadVector mem));
10603 ins_cost(MEMORY_REF_COST);
10604 size(4);
10605 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10606 ins_encode %{
10607 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10608 %}
10609 ins_pipe(floadD_mem);
10610 %}
10611
10612 // Store Vector in Double register to memory
10613 instruct storeV8(memory mem, regD src) %{
10614 predicate(n->as_StoreVector()->memory_size() == 8);
10615 match(Set mem (StoreVector mem src));
10616 ins_cost(MEMORY_REF_COST);
10617 size(4);
10618 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10619 ins_encode %{
10620 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10621 %}
10622 ins_pipe(fstoreD_mem_reg);
10623 %}
10624
10625 // Store Zero into vector in memory
10626 instruct storeV8B_zero(memory mem, immI0 zero) %{
10627 predicate(n->as_StoreVector()->memory_size() == 8);
10628 match(Set mem (StoreVector mem (ReplicateB zero)));
10629 ins_cost(MEMORY_REF_COST);
10630 size(4);
10631 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10632 ins_encode %{
10633 __ stx(G0, $mem$$Address);
10634 %}
10635 ins_pipe(fstoreD_mem_zero);
10636 %}
10637
10638 instruct storeV4S_zero(memory mem, immI0 zero) %{
10639 predicate(n->as_StoreVector()->memory_size() == 8);
10640 match(Set mem (StoreVector mem (ReplicateS zero)));
10641 ins_cost(MEMORY_REF_COST);
10642 size(4);
10643 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10644 ins_encode %{
10645 __ stx(G0, $mem$$Address);
10646 %}
10647 ins_pipe(fstoreD_mem_zero);
10648 %}
10649
10650 instruct storeV2I_zero(memory mem, immI0 zero) %{
10651 predicate(n->as_StoreVector()->memory_size() == 8);
10652 match(Set mem (StoreVector mem (ReplicateI zero)));
10653 ins_cost(MEMORY_REF_COST);
10654 size(4);
10655 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10656 ins_encode %{
10657 __ stx(G0, $mem$$Address);
10658 %}
10659 ins_pipe(fstoreD_mem_zero);
10660 %}
10661
10662 instruct storeV2F_zero(memory mem, immF0 zero) %{
10663 predicate(n->as_StoreVector()->memory_size() == 8);
10664 match(Set mem (StoreVector mem (ReplicateF zero)));
10665 ins_cost(MEMORY_REF_COST);
10666 size(4);
10667 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10668 ins_encode %{
10669 __ stx(G0, $mem$$Address);
10670 %}
10671 ins_pipe(fstoreD_mem_zero);
10672 %}
10673
10674 // Replicate scalar to packed byte values into Double register
10675 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10676 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10677 match(Set dst (ReplicateB src));
10678 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10679 format %{ "SLLX $src,56,$tmp\n\t"
10680 "SRLX $tmp, 8,$tmp2\n\t"
10681 "OR $tmp,$tmp2,$tmp\n\t"
10682 "SRLX $tmp,16,$tmp2\n\t"
10683 "OR $tmp,$tmp2,$tmp\n\t"
10684 "SRLX $tmp,32,$tmp2\n\t"
10685 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10686 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10687 ins_encode %{
10688 Register Rsrc = $src$$Register;
10689 Register Rtmp = $tmp$$Register;
10690 Register Rtmp2 = $tmp2$$Register;
10691 __ sllx(Rsrc, 56, Rtmp);
10692 __ srlx(Rtmp, 8, Rtmp2);
10693 __ or3 (Rtmp, Rtmp2, Rtmp);
10694 __ srlx(Rtmp, 16, Rtmp2);
10695 __ or3 (Rtmp, Rtmp2, Rtmp);
10696 __ srlx(Rtmp, 32, Rtmp2);
10697 __ or3 (Rtmp, Rtmp2, Rtmp);
10698 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10699 %}
10700 ins_pipe(ialu_reg);
10701 %}
10702
10703 // Replicate scalar to packed byte values into Double stack
10704 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10705 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10706 match(Set dst (ReplicateB src));
10707 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10708 format %{ "SLLX $src,56,$tmp\n\t"
10709 "SRLX $tmp, 8,$tmp2\n\t"
10710 "OR $tmp,$tmp2,$tmp\n\t"
10711 "SRLX $tmp,16,$tmp2\n\t"
10712 "OR $tmp,$tmp2,$tmp\n\t"
10713 "SRLX $tmp,32,$tmp2\n\t"
10714 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10715 "STX $tmp,$dst\t! regL to stkD" %}
10716 ins_encode %{
10717 Register Rsrc = $src$$Register;
10718 Register Rtmp = $tmp$$Register;
10719 Register Rtmp2 = $tmp2$$Register;
10720 __ sllx(Rsrc, 56, Rtmp);
10721 __ srlx(Rtmp, 8, Rtmp2);
10722 __ or3 (Rtmp, Rtmp2, Rtmp);
10723 __ srlx(Rtmp, 16, Rtmp2);
10724 __ or3 (Rtmp, Rtmp2, Rtmp);
10725 __ srlx(Rtmp, 32, Rtmp2);
10726 __ or3 (Rtmp, Rtmp2, Rtmp);
10727 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10728 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10729 %}
10730 ins_pipe(ialu_reg);
10731 %}
10732
10733 // Replicate scalar constant to packed byte values in Double register
10734 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10735 predicate(n->as_Vector()->length() == 8);
10736 match(Set dst (ReplicateB con));
10737 effect(KILL tmp);
10738 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10739 ins_encode %{
10740 // XXX This is a quick fix for 6833573.
10741 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10742 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10743 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10744 %}
10745 ins_pipe(loadConFD);
10746 %}
10747
10748 // Replicate scalar to packed char/short values into Double register
10749 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10750 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10751 match(Set dst (ReplicateS src));
10752 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10753 format %{ "SLLX $src,48,$tmp\n\t"
10754 "SRLX $tmp,16,$tmp2\n\t"
10755 "OR $tmp,$tmp2,$tmp\n\t"
10756 "SRLX $tmp,32,$tmp2\n\t"
10757 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10758 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10759 ins_encode %{
10760 Register Rsrc = $src$$Register;
10761 Register Rtmp = $tmp$$Register;
10762 Register Rtmp2 = $tmp2$$Register;
10763 __ sllx(Rsrc, 48, Rtmp);
10764 __ srlx(Rtmp, 16, Rtmp2);
10765 __ or3 (Rtmp, Rtmp2, Rtmp);
10766 __ srlx(Rtmp, 32, Rtmp2);
10767 __ or3 (Rtmp, Rtmp2, Rtmp);
10768 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10769 %}
10770 ins_pipe(ialu_reg);
10771 %}
10772
10773 // Replicate scalar to packed char/short values into Double stack
10774 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10775 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10776 match(Set dst (ReplicateS src));
10777 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10778 format %{ "SLLX $src,48,$tmp\n\t"
10779 "SRLX $tmp,16,$tmp2\n\t"
10780 "OR $tmp,$tmp2,$tmp\n\t"
10781 "SRLX $tmp,32,$tmp2\n\t"
10782 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10783 "STX $tmp,$dst\t! regL to stkD" %}
10784 ins_encode %{
10785 Register Rsrc = $src$$Register;
10786 Register Rtmp = $tmp$$Register;
10787 Register Rtmp2 = $tmp2$$Register;
10788 __ sllx(Rsrc, 48, Rtmp);
10789 __ srlx(Rtmp, 16, Rtmp2);
10790 __ or3 (Rtmp, Rtmp2, Rtmp);
10791 __ srlx(Rtmp, 32, Rtmp2);
10792 __ or3 (Rtmp, Rtmp2, Rtmp);
10793 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10794 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10795 %}
10796 ins_pipe(ialu_reg);
10797 %}
10798
10799 // Replicate scalar constant to packed char/short values in Double register
10800 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10801 predicate(n->as_Vector()->length() == 4);
10802 match(Set dst (ReplicateS con));
10803 effect(KILL tmp);
10804 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10805 ins_encode %{
10806 // XXX This is a quick fix for 6833573.
10807 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10808 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10809 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10810 %}
10811 ins_pipe(loadConFD);
10812 %}
10813
10814 // Replicate scalar to packed int values into Double register
10815 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10816 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10817 match(Set dst (ReplicateI src));
10818 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10819 format %{ "SLLX $src,32,$tmp\n\t"
10820 "SRLX $tmp,32,$tmp2\n\t"
10821 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10822 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10823 ins_encode %{
10824 Register Rsrc = $src$$Register;
10825 Register Rtmp = $tmp$$Register;
10826 Register Rtmp2 = $tmp2$$Register;
10827 __ sllx(Rsrc, 32, Rtmp);
10828 __ srlx(Rtmp, 32, Rtmp2);
10829 __ or3 (Rtmp, Rtmp2, Rtmp);
10830 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10831 %}
10832 ins_pipe(ialu_reg);
10833 %}
10834
10835 // Replicate scalar to packed int values into Double stack
10836 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10837 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10838 match(Set dst (ReplicateI src));
10839 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10840 format %{ "SLLX $src,32,$tmp\n\t"
10841 "SRLX $tmp,32,$tmp2\n\t"
10842 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10843 "STX $tmp,$dst\t! regL to stkD" %}
10844 ins_encode %{
10845 Register Rsrc = $src$$Register;
10846 Register Rtmp = $tmp$$Register;
10847 Register Rtmp2 = $tmp2$$Register;
10848 __ sllx(Rsrc, 32, Rtmp);
10849 __ srlx(Rtmp, 32, Rtmp2);
10850 __ or3 (Rtmp, Rtmp2, Rtmp);
10851 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10852 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10853 %}
10854 ins_pipe(ialu_reg);
10855 %}
10856
10857 // Replicate scalar zero constant to packed int values in Double register
10858 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10859 predicate(n->as_Vector()->length() == 2);
10860 match(Set dst (ReplicateI con));
10861 effect(KILL tmp);
10862 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10863 ins_encode %{
10864 // XXX This is a quick fix for 6833573.
10865 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10866 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10867 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10868 %}
10869 ins_pipe(loadConFD);
10870 %}
10871
10872 // Replicate scalar to packed float values into Double stack
10873 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10874 predicate(n->as_Vector()->length() == 2);
10875 match(Set dst (ReplicateF src));
10876 ins_cost(MEMORY_REF_COST*2);
10877 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10878 "STF $src,$dst.lo" %}
10879 opcode(Assembler::stf_op3);
10880 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10881 ins_pipe(fstoreF_stk_reg);
10882 %}
10883
10884 // Replicate scalar zero constant to packed float values in Double register
10885 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10886 predicate(n->as_Vector()->length() == 2);
10887 match(Set dst (ReplicateF con));
10888 effect(KILL tmp);
10889 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10890 ins_encode %{
10891 // XXX This is a quick fix for 6833573.
10892 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10893 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10894 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10895 %}
10896 ins_pipe(loadConFD);
10897 %}
10898
10899 //----------PEEPHOLE RULES-----------------------------------------------------
10900 // These must follow all instruction definitions as they use the names
10901 // defined in the instructions definitions.
10902 //
10903 // peepmatch ( root_instr_name [preceding_instruction]* );
10904 //
10905 // peepconstraint %{
10906 // (instruction_number.operand_name relational_op instruction_number.operand_name
10907 // [, ...] );
10908 // // instruction numbers are zero-based using left to right order in peepmatch
10909 //
10910 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10911 // // provide an instruction_number.operand_name for each operand that appears
10912 // // in the replacement instruction's match rule
10913 //
10914 // ---------VM FLAGS---------------------------------------------------------
10915 //
10916 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10917 //
10918 // Each peephole rule is given an identifying number starting with zero and
10919 // increasing by one in the order seen by the parser. An individual peephole
10920 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10921 // on the command-line.
10922 //
10923 // ---------CURRENT LIMITATIONS----------------------------------------------
10924 //
10925 // Only match adjacent instructions in same basic block
10926 // Only equality constraints
10927 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10928 // Only one replacement instruction
10929 //
10930 // ---------EXAMPLE----------------------------------------------------------
10931 //
10932 // // pertinent parts of existing instructions in architecture description
10933 // instruct movI(eRegI dst, eRegI src) %{
10934 // match(Set dst (CopyI src));
10935 // %}
10936 //
10937 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10938 // match(Set dst (AddI dst src));
10939 // effect(KILL cr);
10940 // %}
10941 //
10942 // // Change (inc mov) to lea
10943 // peephole %{
10944 // // increment preceeded by register-register move
10945 // peepmatch ( incI_eReg movI );
10946 // // require that the destination register of the increment
10947 // // match the destination register of the move
10948 // peepconstraint ( 0.dst == 1.dst );
10949 // // construct a replacement instruction that sets
10950 // // the destination to ( move's source register + one )
10951 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10952 // %}
10953 //
10954
10955 // // Change load of spilled value to only a spill
10956 // instruct storeI(memory mem, eRegI src) %{
10957 // match(Set mem (StoreI mem src));
10958 // %}
10959 //
10960 // instruct loadI(eRegI dst, memory mem) %{
10961 // match(Set dst (LoadI mem));
10962 // %}
10963 //
10964 // peephole %{
10965 // peepmatch ( loadI storeI );
10966 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10967 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10968 // %}
10969
10970 //----------SMARTSPILL RULES---------------------------------------------------
10971 // These must follow all instruction definitions as they use the names
10972 // defined in the instructions definitions.
10973 //
10974 // SPARC will probably not have any of these rules due to RISC instruction set.
10975
10976 //----------PIPELINE-----------------------------------------------------------
10977 // Rules which define the behavior of the target architectures pipeline.