1 //
2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Class for all pointer registers (including RSP)
170 reg_class any_reg(RAX, RAX_H,
171 RDX, RDX_H,
172 RBP, RBP_H,
173 RDI, RDI_H,
174 RSI, RSI_H,
175 RCX, RCX_H,
176 RBX, RBX_H,
177 RSP, RSP_H,
178 R8, R8_H,
179 R9, R9_H,
180 R10, R10_H,
181 R11, R11_H,
182 R12, R12_H,
183 R13, R13_H,
184 R14, R14_H,
185 R15, R15_H);
186
187 // Class for all pointer registers except RSP
188 reg_class ptr_reg(RAX, RAX_H,
189 RDX, RDX_H,
190 RBP, RBP_H,
191 RDI, RDI_H,
192 RSI, RSI_H,
193 RCX, RCX_H,
194 RBX, RBX_H,
195 R8, R8_H,
196 R9, R9_H,
197 R10, R10_H,
198 R11, R11_H,
199 R13, R13_H,
200 R14, R14_H);
201
202 // Class for all pointer registers except RAX and RSP
203 reg_class ptr_no_rax_reg(RDX, RDX_H,
204 RBP, RBP_H,
205 RDI, RDI_H,
206 RSI, RSI_H,
207 RCX, RCX_H,
208 RBX, RBX_H,
209 R8, R8_H,
210 R9, R9_H,
211 R10, R10_H,
212 R11, R11_H,
213 R13, R13_H,
214 R14, R14_H);
215
216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
217 RAX, RAX_H,
218 RDI, RDI_H,
219 RSI, RSI_H,
220 RCX, RCX_H,
221 RBX, RBX_H,
222 R8, R8_H,
223 R9, R9_H,
224 R10, R10_H,
225 R11, R11_H,
226 R13, R13_H,
227 R14, R14_H);
228
229 // Class for all pointer registers except RAX, RBX and RSP
230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
231 RBP, RBP_H,
232 RDI, RDI_H,
233 RSI, RSI_H,
234 RCX, RCX_H,
235 R8, R8_H,
236 R9, R9_H,
237 R10, R10_H,
238 R11, R11_H,
239 R13, R13_H,
240 R14, R14_H);
241
242 // Singleton class for RAX pointer register
243 reg_class ptr_rax_reg(RAX, RAX_H);
244
245 // Singleton class for RBX pointer register
246 reg_class ptr_rbx_reg(RBX, RBX_H);
247
248 // Singleton class for RSI pointer register
249 reg_class ptr_rsi_reg(RSI, RSI_H);
250
251 // Singleton class for RDI pointer register
252 reg_class ptr_rdi_reg(RDI, RDI_H);
253
254 // Singleton class for RBP pointer register
255 reg_class ptr_rbp_reg(RBP, RBP_H);
256
257 // Singleton class for stack pointer
258 reg_class ptr_rsp_reg(RSP, RSP_H);
259
260 // Singleton class for TLS pointer
261 reg_class ptr_r15_reg(R15, R15_H);
262
263 // Class for all long registers (except RSP)
264 reg_class long_reg(RAX, RAX_H,
265 RDX, RDX_H,
266 RBP, RBP_H,
267 RDI, RDI_H,
268 RSI, RSI_H,
269 RCX, RCX_H,
270 RBX, RBX_H,
271 R8, R8_H,
272 R9, R9_H,
273 R10, R10_H,
274 R11, R11_H,
275 R13, R13_H,
276 R14, R14_H);
277
278 // Class for all long registers except RAX, RDX (and RSP)
279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
280 RDI, RDI_H,
281 RSI, RSI_H,
282 RCX, RCX_H,
283 RBX, RBX_H,
284 R8, R8_H,
285 R9, R9_H,
286 R10, R10_H,
287 R11, R11_H,
288 R13, R13_H,
289 R14, R14_H);
290
291 // Class for all long registers except RCX (and RSP)
292 reg_class long_no_rcx_reg(RBP, RBP_H,
293 RDI, RDI_H,
294 RSI, RSI_H,
295 RAX, RAX_H,
296 RDX, RDX_H,
297 RBX, RBX_H,
298 R8, R8_H,
299 R9, R9_H,
300 R10, R10_H,
301 R11, R11_H,
302 R13, R13_H,
303 R14, R14_H);
304
305 // Class for all long registers except RAX (and RSP)
306 reg_class long_no_rax_reg(RBP, RBP_H,
307 RDX, RDX_H,
308 RDI, RDI_H,
309 RSI, RSI_H,
310 RCX, RCX_H,
311 RBX, RBX_H,
312 R8, R8_H,
313 R9, R9_H,
314 R10, R10_H,
315 R11, R11_H,
316 R13, R13_H,
317 R14, R14_H);
318
319 // Singleton class for RAX long register
320 reg_class long_rax_reg(RAX, RAX_H);
321
322 // Singleton class for RCX long register
323 reg_class long_rcx_reg(RCX, RCX_H);
324
325 // Singleton class for RDX long register
326 reg_class long_rdx_reg(RDX, RDX_H);
327
328 // Class for all int registers (except RSP)
329 reg_class int_reg(RAX,
330 RDX,
331 RBP,
332 RDI,
333 RSI,
334 RCX,
335 RBX,
336 R8,
337 R9,
338 R10,
339 R11,
340 R13,
341 R14);
342
343 // Class for all int registers except RCX (and RSP)
344 reg_class int_no_rcx_reg(RAX,
345 RDX,
346 RBP,
347 RDI,
348 RSI,
349 RBX,
350 R8,
351 R9,
352 R10,
353 R11,
354 R13,
355 R14);
356
357 // Class for all int registers except RAX, RDX (and RSP)
358 reg_class int_no_rax_rdx_reg(RBP,
359 RDI,
360 RSI,
361 RCX,
362 RBX,
363 R8,
364 R9,
365 R10,
366 R11,
367 R13,
368 R14);
369
370 // Singleton class for RAX int register
371 reg_class int_rax_reg(RAX);
372
373 // Singleton class for RBX int register
374 reg_class int_rbx_reg(RBX);
375
376 // Singleton class for RCX int register
377 reg_class int_rcx_reg(RCX);
378
379 // Singleton class for RCX int register
380 reg_class int_rdx_reg(RDX);
381
382 // Singleton class for RCX int register
383 reg_class int_rdi_reg(RDI);
384
385 // Singleton class for instruction pointer
386 // reg_class ip_reg(RIP);
387
388 %}
389
390 //----------SOURCE BLOCK-------------------------------------------------------
391 // This is a block of C++ code which provides values, functions, and
392 // definitions necessary in the rest of the architecture description
393 source %{
394 #define RELOC_IMM64 Assembler::imm_operand
395 #define RELOC_DISP32 Assembler::disp32_operand
396
397 #define __ _masm.
398
399 static int preserve_SP_size() {
400 return 3; // rex.w, op, rm(reg/reg)
401 }
402 static int clear_avx_size() {
403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
404 }
405
406 // !!!!! Special hack to get all types of calls to specify the byte offset
407 // from the start of the call to the point where the return address
408 // will point.
409 int MachCallStaticJavaNode::ret_addr_offset()
410 {
411 int offset = 5; // 5 bytes from start of call to where return address points
412 offset += clear_avx_size();
413 if (_method_handle_invoke)
414 offset += preserve_SP_size();
415 return offset;
416 }
417
418 int MachCallDynamicJavaNode::ret_addr_offset()
419 {
420 int offset = 15; // 15 bytes from start of call to where return address points
421 offset += clear_avx_size();
422 return offset;
423 }
424
425 int MachCallRuntimeNode::ret_addr_offset() {
426 int offset = 13; // movq r10,#addr; callq (r10)
427 offset += clear_avx_size();
428 return offset;
429 }
430
431 // Indicate if the safepoint node needs the polling page as an input,
432 // it does if the polling page is more than disp32 away.
433 bool SafePointNode::needs_polling_address_input()
434 {
435 return Assembler::is_polling_page_far();
436 }
437
438 //
439 // Compute padding required for nodes which need alignment
440 //
441
442 // The address of the call instruction needs to be 4-byte aligned to
443 // ensure that it does not span a cache line so that it can be patched.
444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
445 {
446 current_offset += clear_avx_size(); // skip vzeroupper
447 current_offset += 1; // skip call opcode byte
448 return round_to(current_offset, alignment_required()) - current_offset;
449 }
450
451 // The address of the call instruction needs to be 4-byte aligned to
452 // ensure that it does not span a cache line so that it can be patched.
453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
454 {
455 current_offset += preserve_SP_size(); // skip mov rbp, rsp
456 current_offset += clear_avx_size(); // skip vzeroupper
457 current_offset += 1; // skip call opcode byte
458 return round_to(current_offset, alignment_required()) - current_offset;
459 }
460
461 // The address of the call instruction needs to be 4-byte aligned to
462 // ensure that it does not span a cache line so that it can be patched.
463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
464 {
465 current_offset += clear_avx_size(); // skip vzeroupper
466 current_offset += 11; // skip movq instruction + call opcode byte
467 return round_to(current_offset, alignment_required()) - current_offset;
468 }
469
470 // EMIT_RM()
471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
473 cbuf.insts()->emit_int8(c);
474 }
475
476 // EMIT_CC()
477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
478 unsigned char c = (unsigned char) (f1 | f2);
479 cbuf.insts()->emit_int8(c);
480 }
481
482 // EMIT_OPCODE()
483 void emit_opcode(CodeBuffer &cbuf, int code) {
484 cbuf.insts()->emit_int8((unsigned char) code);
485 }
486
487 // EMIT_OPCODE() w/ relocation information
488 void emit_opcode(CodeBuffer &cbuf,
489 int code, relocInfo::relocType reloc, int offset, int format)
490 {
491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
492 emit_opcode(cbuf, code);
493 }
494
495 // EMIT_D8()
496 void emit_d8(CodeBuffer &cbuf, int d8) {
497 cbuf.insts()->emit_int8((unsigned char) d8);
498 }
499
500 // EMIT_D16()
501 void emit_d16(CodeBuffer &cbuf, int d16) {
502 cbuf.insts()->emit_int16(d16);
503 }
504
505 // EMIT_D32()
506 void emit_d32(CodeBuffer &cbuf, int d32) {
507 cbuf.insts()->emit_int32(d32);
508 }
509
510 // EMIT_D64()
511 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
512 cbuf.insts()->emit_int64(d64);
513 }
514
515 // emit 32 bit value and construct relocation entry from relocInfo::relocType
516 void emit_d32_reloc(CodeBuffer& cbuf,
517 int d32,
518 relocInfo::relocType reloc,
519 int format)
520 {
521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
522 cbuf.relocate(cbuf.insts_mark(), reloc, format);
523 cbuf.insts()->emit_int32(d32);
524 }
525
526 // emit 32 bit value and construct relocation entry from RelocationHolder
527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
528 #ifdef ASSERT
529 if (rspec.reloc()->type() == relocInfo::oop_type &&
530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
532 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
533 }
534 #endif
535 cbuf.relocate(cbuf.insts_mark(), rspec, format);
536 cbuf.insts()->emit_int32(d32);
537 }
538
539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
540 address next_ip = cbuf.insts_end() + 4;
541 emit_d32_reloc(cbuf, (int) (addr - next_ip),
542 external_word_Relocation::spec(addr),
543 RELOC_DISP32);
544 }
545
546
547 // emit 64 bit value and construct relocation entry from relocInfo::relocType
548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
549 cbuf.relocate(cbuf.insts_mark(), reloc, format);
550 cbuf.insts()->emit_int64(d64);
551 }
552
553 // emit 64 bit value and construct relocation entry from RelocationHolder
554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
555 #ifdef ASSERT
556 if (rspec.reloc()->type() == relocInfo::oop_type &&
557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
559 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
560 "cannot embed scavengable oops in code");
561 }
562 #endif
563 cbuf.relocate(cbuf.insts_mark(), rspec, format);
564 cbuf.insts()->emit_int64(d64);
565 }
566
567 // Access stack slot for load or store
568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
569 {
570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
571 if (-0x80 <= disp && disp < 0x80) {
572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
574 emit_d8(cbuf, disp); // Displacement // R/M byte
575 } else {
576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
578 emit_d32(cbuf, disp); // Displacement // R/M byte
579 }
580 }
581
582 // rRegI ereg, memory mem) %{ // emit_reg_mem
583 void encode_RegMem(CodeBuffer &cbuf,
584 int reg,
585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
586 {
587 assert(disp_reloc == relocInfo::none, "cannot have disp");
588 int regenc = reg & 7;
589 int baseenc = base & 7;
590 int indexenc = index & 7;
591
592 // There is no index & no scale, use form without SIB byte
593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
595 if (disp == 0 && base != RBP_enc && base != R13_enc) {
596 emit_rm(cbuf, 0x0, regenc, baseenc); // *
597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
598 // If 8-bit displacement, mode 0x1
599 emit_rm(cbuf, 0x1, regenc, baseenc); // *
600 emit_d8(cbuf, disp);
601 } else {
602 // If 32-bit displacement
603 if (base == -1) { // Special flag for absolute address
604 emit_rm(cbuf, 0x0, regenc, 0x5); // *
605 if (disp_reloc != relocInfo::none) {
606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
607 } else {
608 emit_d32(cbuf, disp);
609 }
610 } else {
611 // Normal base + offset
612 emit_rm(cbuf, 0x2, regenc, baseenc); // *
613 if (disp_reloc != relocInfo::none) {
614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
615 } else {
616 emit_d32(cbuf, disp);
617 }
618 }
619 }
620 } else {
621 // Else, encode with the SIB byte
622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
623 if (disp == 0 && base != RBP_enc && base != R13_enc) {
624 // If no displacement
625 emit_rm(cbuf, 0x0, regenc, 0x4); // *
626 emit_rm(cbuf, scale, indexenc, baseenc);
627 } else {
628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
629 // If 8-bit displacement, mode 0x1
630 emit_rm(cbuf, 0x1, regenc, 0x4); // *
631 emit_rm(cbuf, scale, indexenc, baseenc);
632 emit_d8(cbuf, disp);
633 } else {
634 // If 32-bit displacement
635 if (base == 0x04 ) {
636 emit_rm(cbuf, 0x2, regenc, 0x4);
637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
638 } else {
639 emit_rm(cbuf, 0x2, regenc, 0x4);
640 emit_rm(cbuf, scale, indexenc, baseenc); // *
641 }
642 if (disp_reloc != relocInfo::none) {
643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
644 } else {
645 emit_d32(cbuf, disp);
646 }
647 }
648 }
649 }
650 }
651
652 // This could be in MacroAssembler but it's fairly C2 specific
653 void emit_cmpfp_fixup(MacroAssembler& _masm) {
654 Label exit;
655 __ jccb(Assembler::noParity, exit);
656 __ pushf();
657 //
658 // comiss/ucomiss instructions set ZF,PF,CF flags and
659 // zero OF,AF,SF for NaN values.
660 // Fixup flags by zeroing ZF,PF so that compare of NaN
661 // values returns 'less than' result (CF is set).
662 // Leave the rest of flags unchanged.
663 //
664 // 7 6 5 4 3 2 1 0
665 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
666 // 0 0 1 0 1 0 1 1 (0x2B)
667 //
668 __ andq(Address(rsp, 0), 0xffffff2b);
669 __ popf();
670 __ bind(exit);
671 }
672
673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
674 Label done;
675 __ movl(dst, -1);
676 __ jcc(Assembler::parity, done);
677 __ jcc(Assembler::below, done);
678 __ setb(Assembler::notEqual, dst);
679 __ movzbl(dst, dst);
680 __ bind(done);
681 }
682
683
684 //=============================================================================
685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
686
687 int Compile::ConstantTable::calculate_table_base_offset() const {
688 return 0; // absolute addressing, no offset
689 }
690
691 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
692 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
693 ShouldNotReachHere();
694 }
695
696 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
697 // Empty encoding
698 }
699
700 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
701 return 0;
702 }
703
704 #ifndef PRODUCT
705 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
706 st->print("# MachConstantBaseNode (empty encoding)");
707 }
708 #endif
709
710
711 //=============================================================================
712 #ifndef PRODUCT
713 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
714 Compile* C = ra_->C;
715
716 int framesize = C->frame_slots() << LogBytesPerInt;
717 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
718 // Remove wordSize for return addr which is already pushed.
719 framesize -= wordSize;
720
721 if (C->need_stack_bang(framesize)) {
722 framesize -= wordSize;
723 st->print("# stack bang");
724 st->print("\n\t");
725 st->print("pushq rbp\t# Save rbp");
726 if (framesize) {
727 st->print("\n\t");
728 st->print("subq rsp, #%d\t# Create frame",framesize);
729 }
730 } else {
731 st->print("subq rsp, #%d\t# Create frame",framesize);
732 st->print("\n\t");
733 framesize -= wordSize;
734 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
735 }
736
737 if (VerifyStackAtCalls) {
738 st->print("\n\t");
739 framesize -= wordSize;
740 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
741 #ifdef ASSERT
742 st->print("\n\t");
743 st->print("# stack alignment check");
744 #endif
745 }
746 st->cr();
747 }
748 #endif
749
750 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
751 Compile* C = ra_->C;
752 MacroAssembler _masm(&cbuf);
753
754 int framesize = C->frame_slots() << LogBytesPerInt;
755
756 __ verified_entry(framesize, C->need_stack_bang(framesize), false);
757
758 C->set_frame_complete(cbuf.insts_size());
759
760 if (C->has_mach_constant_base_node()) {
761 // NOTE: We set the table base offset here because users might be
762 // emitted before MachConstantBaseNode.
763 Compile::ConstantTable& constant_table = C->constant_table();
764 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
765 }
766 }
767
768 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
769 {
770 return MachNode::size(ra_); // too many variables; just compute it
771 // the hard way
772 }
773
774 int MachPrologNode::reloc() const
775 {
776 return 0; // a large enough number
777 }
778
779 //=============================================================================
780 #ifndef PRODUCT
781 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
782 {
783 Compile* C = ra_->C;
784 if (C->max_vector_size() > 16) {
785 st->print("vzeroupper");
786 st->cr(); st->print("\t");
787 }
788
789 int framesize = C->frame_slots() << LogBytesPerInt;
790 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
791 // Remove word for return adr already pushed
792 // and RBP
793 framesize -= 2*wordSize;
794
795 if (framesize) {
796 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
797 st->print("\t");
798 }
799
800 st->print_cr("popq rbp");
801 if (do_polling() && C->is_method_compilation()) {
802 st->print("\t");
803 if (Assembler::is_polling_page_far()) {
804 st->print_cr("movq rscratch1, #polling_page_address\n\t"
805 "testl rax, [rscratch1]\t"
806 "# Safepoint: poll for GC");
807 } else {
808 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
809 "# Safepoint: poll for GC");
810 }
811 }
812 }
813 #endif
814
815 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
816 {
817 Compile* C = ra_->C;
818 if (C->max_vector_size() > 16) {
819 // Clear upper bits of YMM registers when current compiled code uses
820 // wide vectors to avoid AVX <-> SSE transition penalty during call.
821 MacroAssembler _masm(&cbuf);
822 __ vzeroupper();
823 }
824
825 int framesize = C->frame_slots() << LogBytesPerInt;
826 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
827 // Remove word for return adr already pushed
828 // and RBP
829 framesize -= 2*wordSize;
830
831 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
832
833 if (framesize) {
834 emit_opcode(cbuf, Assembler::REX_W);
835 if (framesize < 0x80) {
836 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
837 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
838 emit_d8(cbuf, framesize);
839 } else {
840 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
841 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
842 emit_d32(cbuf, framesize);
843 }
844 }
845
846 // popq rbp
847 emit_opcode(cbuf, 0x58 | RBP_enc);
848
849 if (do_polling() && C->is_method_compilation()) {
850 MacroAssembler _masm(&cbuf);
851 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
852 if (Assembler::is_polling_page_far()) {
853 __ lea(rscratch1, polling_page);
854 __ relocate(relocInfo::poll_return_type);
855 __ testl(rax, Address(rscratch1, 0));
856 } else {
857 __ testl(rax, polling_page);
858 }
859 }
860 }
861
862 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
863 {
864 return MachNode::size(ra_); // too many variables; just compute it
865 // the hard way
866 }
867
868 int MachEpilogNode::reloc() const
869 {
870 return 2; // a large enough number
871 }
872
873 const Pipeline* MachEpilogNode::pipeline() const
874 {
875 return MachNode::pipeline_class();
876 }
877
878 int MachEpilogNode::safepoint_offset() const
879 {
880 return 0;
881 }
882
883 //=============================================================================
884
885 enum RC {
886 rc_bad,
887 rc_int,
888 rc_float,
889 rc_stack
890 };
891
892 static enum RC rc_class(OptoReg::Name reg)
893 {
894 if( !OptoReg::is_valid(reg) ) return rc_bad;
895
896 if (OptoReg::is_stack(reg)) return rc_stack;
897
898 VMReg r = OptoReg::as_VMReg(reg);
899
900 if (r->is_Register()) return rc_int;
901
902 assert(r->is_XMMRegister(), "must be");
903 return rc_float;
904 }
905
906 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
907 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
908 int src_hi, int dst_hi, uint ireg, outputStream* st);
909
910 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
911 int stack_offset, int reg, uint ireg, outputStream* st);
912
913 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
914 int dst_offset, uint ireg, outputStream* st) {
915 if (cbuf) {
916 MacroAssembler _masm(cbuf);
917 switch (ireg) {
918 case Op_VecS:
919 __ movq(Address(rsp, -8), rax);
920 __ movl(rax, Address(rsp, src_offset));
921 __ movl(Address(rsp, dst_offset), rax);
922 __ movq(rax, Address(rsp, -8));
923 break;
924 case Op_VecD:
925 __ pushq(Address(rsp, src_offset));
926 __ popq (Address(rsp, dst_offset));
927 break;
928 case Op_VecX:
929 __ pushq(Address(rsp, src_offset));
930 __ popq (Address(rsp, dst_offset));
931 __ pushq(Address(rsp, src_offset+8));
932 __ popq (Address(rsp, dst_offset+8));
933 break;
934 case Op_VecY:
935 __ vmovdqu(Address(rsp, -32), xmm0);
936 __ vmovdqu(xmm0, Address(rsp, src_offset));
937 __ vmovdqu(Address(rsp, dst_offset), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, -32));
939 break;
940 default:
941 ShouldNotReachHere();
942 }
943 #ifndef PRODUCT
944 } else {
945 switch (ireg) {
946 case Op_VecS:
947 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
948 "movl rax, [rsp + #%d]\n\t"
949 "movl [rsp + #%d], rax\n\t"
950 "movq rax, [rsp - #8]",
951 src_offset, dst_offset);
952 break;
953 case Op_VecD:
954 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
955 "popq [rsp + #%d]",
956 src_offset, dst_offset);
957 break;
958 case Op_VecX:
959 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
960 "popq [rsp + #%d]\n\t"
961 "pushq [rsp + #%d]\n\t"
962 "popq [rsp + #%d]",
963 src_offset, dst_offset, src_offset+8, dst_offset+8);
964 break;
965 case Op_VecY:
966 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
967 "vmovdqu xmm0, [rsp + #%d]\n\t"
968 "vmovdqu [rsp + #%d], xmm0\n\t"
969 "vmovdqu xmm0, [rsp - #32]",
970 src_offset, dst_offset);
971 break;
972 default:
973 ShouldNotReachHere();
974 }
975 #endif
976 }
977 }
978
979 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
980 PhaseRegAlloc* ra_,
981 bool do_size,
982 outputStream* st) const {
983 assert(cbuf != NULL || st != NULL, "sanity");
984 // Get registers to move
985 OptoReg::Name src_second = ra_->get_reg_second(in(1));
986 OptoReg::Name src_first = ra_->get_reg_first(in(1));
987 OptoReg::Name dst_second = ra_->get_reg_second(this);
988 OptoReg::Name dst_first = ra_->get_reg_first(this);
989
990 enum RC src_second_rc = rc_class(src_second);
991 enum RC src_first_rc = rc_class(src_first);
992 enum RC dst_second_rc = rc_class(dst_second);
993 enum RC dst_first_rc = rc_class(dst_first);
994
995 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
996 "must move at least 1 register" );
997
998 if (src_first == dst_first && src_second == dst_second) {
999 // Self copy, no move
1000 return 0;
1001 }
1002 if (bottom_type()->isa_vect() != NULL) {
1003 uint ireg = ideal_reg();
1004 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1005 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1006 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1007 // mem -> mem
1008 int src_offset = ra_->reg2offset(src_first);
1009 int dst_offset = ra_->reg2offset(dst_first);
1010 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1011 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1012 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1013 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1014 int stack_offset = ra_->reg2offset(dst_first);
1015 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1016 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1017 int stack_offset = ra_->reg2offset(src_first);
1018 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1019 } else {
1020 ShouldNotReachHere();
1021 }
1022 return 0;
1023 }
1024 if (src_first_rc == rc_stack) {
1025 // mem ->
1026 if (dst_first_rc == rc_stack) {
1027 // mem -> mem
1028 assert(src_second != dst_first, "overlap");
1029 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1030 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1031 // 64-bit
1032 int src_offset = ra_->reg2offset(src_first);
1033 int dst_offset = ra_->reg2offset(dst_first);
1034 if (cbuf) {
1035 MacroAssembler _masm(cbuf);
1036 __ pushq(Address(rsp, src_offset));
1037 __ popq (Address(rsp, dst_offset));
1038 #ifndef PRODUCT
1039 } else {
1040 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1041 "popq [rsp + #%d]",
1042 src_offset, dst_offset);
1043 #endif
1044 }
1045 } else {
1046 // 32-bit
1047 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1048 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1049 // No pushl/popl, so:
1050 int src_offset = ra_->reg2offset(src_first);
1051 int dst_offset = ra_->reg2offset(dst_first);
1052 if (cbuf) {
1053 MacroAssembler _masm(cbuf);
1054 __ movq(Address(rsp, -8), rax);
1055 __ movl(rax, Address(rsp, src_offset));
1056 __ movl(Address(rsp, dst_offset), rax);
1057 __ movq(rax, Address(rsp, -8));
1058 #ifndef PRODUCT
1059 } else {
1060 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1061 "movl rax, [rsp + #%d]\n\t"
1062 "movl [rsp + #%d], rax\n\t"
1063 "movq rax, [rsp - #8]",
1064 src_offset, dst_offset);
1065 #endif
1066 }
1067 }
1068 return 0;
1069 } else if (dst_first_rc == rc_int) {
1070 // mem -> gpr
1071 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1072 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1073 // 64-bit
1074 int offset = ra_->reg2offset(src_first);
1075 if (cbuf) {
1076 MacroAssembler _masm(cbuf);
1077 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1078 #ifndef PRODUCT
1079 } else {
1080 st->print("movq %s, [rsp + #%d]\t# spill",
1081 Matcher::regName[dst_first],
1082 offset);
1083 #endif
1084 }
1085 } else {
1086 // 32-bit
1087 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1088 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1089 int offset = ra_->reg2offset(src_first);
1090 if (cbuf) {
1091 MacroAssembler _masm(cbuf);
1092 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1093 #ifndef PRODUCT
1094 } else {
1095 st->print("movl %s, [rsp + #%d]\t# spill",
1096 Matcher::regName[dst_first],
1097 offset);
1098 #endif
1099 }
1100 }
1101 return 0;
1102 } else if (dst_first_rc == rc_float) {
1103 // mem-> xmm
1104 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1105 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1106 // 64-bit
1107 int offset = ra_->reg2offset(src_first);
1108 if (cbuf) {
1109 MacroAssembler _masm(cbuf);
1110 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1111 #ifndef PRODUCT
1112 } else {
1113 st->print("%s %s, [rsp + #%d]\t# spill",
1114 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1115 Matcher::regName[dst_first],
1116 offset);
1117 #endif
1118 }
1119 } else {
1120 // 32-bit
1121 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1122 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1123 int offset = ra_->reg2offset(src_first);
1124 if (cbuf) {
1125 MacroAssembler _masm(cbuf);
1126 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1127 #ifndef PRODUCT
1128 } else {
1129 st->print("movss %s, [rsp + #%d]\t# spill",
1130 Matcher::regName[dst_first],
1131 offset);
1132 #endif
1133 }
1134 }
1135 return 0;
1136 }
1137 } else if (src_first_rc == rc_int) {
1138 // gpr ->
1139 if (dst_first_rc == rc_stack) {
1140 // gpr -> mem
1141 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1142 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1143 // 64-bit
1144 int offset = ra_->reg2offset(dst_first);
1145 if (cbuf) {
1146 MacroAssembler _masm(cbuf);
1147 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1148 #ifndef PRODUCT
1149 } else {
1150 st->print("movq [rsp + #%d], %s\t# spill",
1151 offset,
1152 Matcher::regName[src_first]);
1153 #endif
1154 }
1155 } else {
1156 // 32-bit
1157 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1158 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1159 int offset = ra_->reg2offset(dst_first);
1160 if (cbuf) {
1161 MacroAssembler _masm(cbuf);
1162 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1163 #ifndef PRODUCT
1164 } else {
1165 st->print("movl [rsp + #%d], %s\t# spill",
1166 offset,
1167 Matcher::regName[src_first]);
1168 #endif
1169 }
1170 }
1171 return 0;
1172 } else if (dst_first_rc == rc_int) {
1173 // gpr -> gpr
1174 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1175 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1176 // 64-bit
1177 if (cbuf) {
1178 MacroAssembler _masm(cbuf);
1179 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1180 as_Register(Matcher::_regEncode[src_first]));
1181 #ifndef PRODUCT
1182 } else {
1183 st->print("movq %s, %s\t# spill",
1184 Matcher::regName[dst_first],
1185 Matcher::regName[src_first]);
1186 #endif
1187 }
1188 return 0;
1189 } else {
1190 // 32-bit
1191 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1192 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1193 if (cbuf) {
1194 MacroAssembler _masm(cbuf);
1195 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1196 as_Register(Matcher::_regEncode[src_first]));
1197 #ifndef PRODUCT
1198 } else {
1199 st->print("movl %s, %s\t# spill",
1200 Matcher::regName[dst_first],
1201 Matcher::regName[src_first]);
1202 #endif
1203 }
1204 return 0;
1205 }
1206 } else if (dst_first_rc == rc_float) {
1207 // gpr -> xmm
1208 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1209 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1210 // 64-bit
1211 if (cbuf) {
1212 MacroAssembler _masm(cbuf);
1213 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1214 #ifndef PRODUCT
1215 } else {
1216 st->print("movdq %s, %s\t# spill",
1217 Matcher::regName[dst_first],
1218 Matcher::regName[src_first]);
1219 #endif
1220 }
1221 } else {
1222 // 32-bit
1223 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1224 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1225 if (cbuf) {
1226 MacroAssembler _masm(cbuf);
1227 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1228 #ifndef PRODUCT
1229 } else {
1230 st->print("movdl %s, %s\t# spill",
1231 Matcher::regName[dst_first],
1232 Matcher::regName[src_first]);
1233 #endif
1234 }
1235 }
1236 return 0;
1237 }
1238 } else if (src_first_rc == rc_float) {
1239 // xmm ->
1240 if (dst_first_rc == rc_stack) {
1241 // xmm -> mem
1242 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1243 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1244 // 64-bit
1245 int offset = ra_->reg2offset(dst_first);
1246 if (cbuf) {
1247 MacroAssembler _masm(cbuf);
1248 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1249 #ifndef PRODUCT
1250 } else {
1251 st->print("movsd [rsp + #%d], %s\t# spill",
1252 offset,
1253 Matcher::regName[src_first]);
1254 #endif
1255 }
1256 } else {
1257 // 32-bit
1258 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1259 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1260 int offset = ra_->reg2offset(dst_first);
1261 if (cbuf) {
1262 MacroAssembler _masm(cbuf);
1263 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1264 #ifndef PRODUCT
1265 } else {
1266 st->print("movss [rsp + #%d], %s\t# spill",
1267 offset,
1268 Matcher::regName[src_first]);
1269 #endif
1270 }
1271 }
1272 return 0;
1273 } else if (dst_first_rc == rc_int) {
1274 // xmm -> gpr
1275 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1276 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1277 // 64-bit
1278 if (cbuf) {
1279 MacroAssembler _masm(cbuf);
1280 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1281 #ifndef PRODUCT
1282 } else {
1283 st->print("movdq %s, %s\t# spill",
1284 Matcher::regName[dst_first],
1285 Matcher::regName[src_first]);
1286 #endif
1287 }
1288 } else {
1289 // 32-bit
1290 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1291 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1292 if (cbuf) {
1293 MacroAssembler _masm(cbuf);
1294 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1295 #ifndef PRODUCT
1296 } else {
1297 st->print("movdl %s, %s\t# spill",
1298 Matcher::regName[dst_first],
1299 Matcher::regName[src_first]);
1300 #endif
1301 }
1302 }
1303 return 0;
1304 } else if (dst_first_rc == rc_float) {
1305 // xmm -> xmm
1306 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1307 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1308 // 64-bit
1309 if (cbuf) {
1310 MacroAssembler _masm(cbuf);
1311 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1312 #ifndef PRODUCT
1313 } else {
1314 st->print("%s %s, %s\t# spill",
1315 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1316 Matcher::regName[dst_first],
1317 Matcher::regName[src_first]);
1318 #endif
1319 }
1320 } else {
1321 // 32-bit
1322 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1323 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1324 if (cbuf) {
1325 MacroAssembler _masm(cbuf);
1326 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1327 #ifndef PRODUCT
1328 } else {
1329 st->print("%s %s, %s\t# spill",
1330 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1331 Matcher::regName[dst_first],
1332 Matcher::regName[src_first]);
1333 #endif
1334 }
1335 }
1336 return 0;
1337 }
1338 }
1339
1340 assert(0," foo ");
1341 Unimplemented();
1342 return 0;
1343 }
1344
1345 #ifndef PRODUCT
1346 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1347 implementation(NULL, ra_, false, st);
1348 }
1349 #endif
1350
1351 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1352 implementation(&cbuf, ra_, false, NULL);
1353 }
1354
1355 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1356 return MachNode::size(ra_);
1357 }
1358
1359 //=============================================================================
1360 #ifndef PRODUCT
1361 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1362 {
1363 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1364 int reg = ra_->get_reg_first(this);
1365 st->print("leaq %s, [rsp + #%d]\t# box lock",
1366 Matcher::regName[reg], offset);
1367 }
1368 #endif
1369
1370 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1371 {
1372 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1373 int reg = ra_->get_encode(this);
1374 if (offset >= 0x80) {
1375 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1376 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1377 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1378 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1379 emit_d32(cbuf, offset);
1380 } else {
1381 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1382 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1383 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1384 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1385 emit_d8(cbuf, offset);
1386 }
1387 }
1388
1389 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1390 {
1391 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1392 return (offset < 0x80) ? 5 : 8; // REX
1393 }
1394
1395 //=============================================================================
1396 #ifndef PRODUCT
1397 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1398 {
1399 if (UseCompressedClassPointers) {
1400 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1401 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1402 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1403 } else {
1404 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1405 "# Inline cache check");
1406 }
1407 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1408 st->print_cr("\tnop\t# nops to align entry point");
1409 }
1410 #endif
1411
1412 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1413 {
1414 MacroAssembler masm(&cbuf);
1415 uint insts_size = cbuf.insts_size();
1416 if (UseCompressedClassPointers) {
1417 masm.load_klass(rscratch1, j_rarg0);
1418 masm.cmpptr(rax, rscratch1);
1419 } else {
1420 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1421 }
1422
1423 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1424
1425 /* WARNING these NOPs are critical so that verified entry point is properly
1426 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1427 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1428 if (OptoBreakpoint) {
1429 // Leave space for int3
1430 nops_cnt -= 1;
1431 }
1432 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1433 if (nops_cnt > 0)
1434 masm.nop(nops_cnt);
1435 }
1436
1437 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1438 {
1439 return MachNode::size(ra_); // too many variables; just compute it
1440 // the hard way
1441 }
1442
1443
1444 //=============================================================================
1445 uint size_exception_handler()
1446 {
1447 // NativeCall instruction size is the same as NativeJump.
1448 // Note that this value is also credited (in output.cpp) to
1449 // the size of the code section.
1450 return NativeJump::instruction_size;
1451 }
1452
1453 // Emit exception handler code.
1454 int emit_exception_handler(CodeBuffer& cbuf)
1455 {
1456
1457 // Note that the code buffer's insts_mark is always relative to insts.
1458 // That's why we must use the macroassembler to generate a handler.
1459 MacroAssembler _masm(&cbuf);
1460 address base =
1461 __ start_a_stub(size_exception_handler());
1462 if (base == NULL) return 0; // CodeBuffer::expand failed
1463 int offset = __ offset();
1464 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1465 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1466 __ end_a_stub();
1467 return offset;
1468 }
1469
1470 uint size_deopt_handler()
1471 {
1472 // three 5 byte instructions
1473 return 15;
1474 }
1475
1476 // Emit deopt handler code.
1477 int emit_deopt_handler(CodeBuffer& cbuf)
1478 {
1479
1480 // Note that the code buffer's insts_mark is always relative to insts.
1481 // That's why we must use the macroassembler to generate a handler.
1482 MacroAssembler _masm(&cbuf);
1483 address base =
1484 __ start_a_stub(size_deopt_handler());
1485 if (base == NULL) return 0; // CodeBuffer::expand failed
1486 int offset = __ offset();
1487 address the_pc = (address) __ pc();
1488 Label next;
1489 // push a "the_pc" on the stack without destroying any registers
1490 // as they all may be live.
1491
1492 // push address of "next"
1493 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1494 __ bind(next);
1495 // adjust it so it matches "the_pc"
1496 __ subptr(Address(rsp, 0), __ offset() - offset);
1497 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1498 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1499 __ end_a_stub();
1500 return offset;
1501 }
1502
1503 int Matcher::regnum_to_fpu_offset(int regnum)
1504 {
1505 return regnum - 32; // The FP registers are in the second chunk
1506 }
1507
1508 // This is UltraSparc specific, true just means we have fast l2f conversion
1509 const bool Matcher::convL2FSupported(void) {
1510 return true;
1511 }
1512
1513 // Is this branch offset short enough that a short branch can be used?
1514 //
1515 // NOTE: If the platform does not provide any short branch variants, then
1516 // this method should return false for offset 0.
1517 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1518 // The passed offset is relative to address of the branch.
1519 // On 86 a branch displacement is calculated relative to address
1520 // of a next instruction.
1521 offset -= br_size;
1522
1523 // the short version of jmpConUCF2 contains multiple branches,
1524 // making the reach slightly less
1525 if (rule == jmpConUCF2_rule)
1526 return (-126 <= offset && offset <= 125);
1527 return (-128 <= offset && offset <= 127);
1528 }
1529
1530 const bool Matcher::isSimpleConstant64(jlong value) {
1531 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1532 //return value == (int) value; // Cf. storeImmL and immL32.
1533
1534 // Probably always true, even if a temp register is required.
1535 return true;
1536 }
1537
1538 // The ecx parameter to rep stosq for the ClearArray node is in words.
1539 const bool Matcher::init_array_count_is_in_bytes = false;
1540
1541 // Threshold size for cleararray.
1542 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1543
1544 // No additional cost for CMOVL.
1545 const int Matcher::long_cmove_cost() { return 0; }
1546
1547 // No CMOVF/CMOVD with SSE2
1548 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1549
1550 // Does the CPU require late expand (see block.cpp for description of late expand)?
1551 const bool Matcher::require_postalloc_expand = false;
1552
1553 // Should the Matcher clone shifts on addressing modes, expecting them
1554 // to be subsumed into complex addressing expressions or compute them
1555 // into registers? True for Intel but false for most RISCs
1556 const bool Matcher::clone_shift_expressions = true;
1557
1558 // Do we need to mask the count passed to shift instructions or does
1559 // the cpu only look at the lower 5/6 bits anyway?
1560 const bool Matcher::need_masked_shift_count = false;
1561
1562 bool Matcher::narrow_oop_use_complex_address() {
1563 assert(UseCompressedOops, "only for compressed oops code");
1564 return (LogMinObjAlignmentInBytes <= 3);
1565 }
1566
1567 bool Matcher::narrow_klass_use_complex_address() {
1568 assert(UseCompressedClassPointers, "only for compressed klass code");
1569 return (LogKlassAlignmentInBytes <= 3);
1570 }
1571
1572 // Is it better to copy float constants, or load them directly from
1573 // memory? Intel can load a float constant from a direct address,
1574 // requiring no extra registers. Most RISCs will have to materialize
1575 // an address into a register first, so they would do better to copy
1576 // the constant from stack.
1577 const bool Matcher::rematerialize_float_constants = true; // XXX
1578
1579 // If CPU can load and store mis-aligned doubles directly then no
1580 // fixup is needed. Else we split the double into 2 integer pieces
1581 // and move it piece-by-piece. Only happens when passing doubles into
1582 // C code as the Java calling convention forces doubles to be aligned.
1583 const bool Matcher::misaligned_doubles_ok = true;
1584
1585 // No-op on amd64
1586 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1587
1588 // Advertise here if the CPU requires explicit rounding operations to
1589 // implement the UseStrictFP mode.
1590 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1591
1592 // Are floats conerted to double when stored to stack during deoptimization?
1593 // On x64 it is stored without convertion so we can use normal access.
1594 bool Matcher::float_in_double() { return false; }
1595
1596 // Do ints take an entire long register or just half?
1597 const bool Matcher::int_in_long = true;
1598
1599 // Return whether or not this register is ever used as an argument.
1600 // This function is used on startup to build the trampoline stubs in
1601 // generateOptoStub. Registers not mentioned will be killed by the VM
1602 // call in the trampoline, and arguments in those registers not be
1603 // available to the callee.
1604 bool Matcher::can_be_java_arg(int reg)
1605 {
1606 return
1607 reg == RDI_num || reg == RDI_H_num ||
1608 reg == RSI_num || reg == RSI_H_num ||
1609 reg == RDX_num || reg == RDX_H_num ||
1610 reg == RCX_num || reg == RCX_H_num ||
1611 reg == R8_num || reg == R8_H_num ||
1612 reg == R9_num || reg == R9_H_num ||
1613 reg == R12_num || reg == R12_H_num ||
1614 reg == XMM0_num || reg == XMM0b_num ||
1615 reg == XMM1_num || reg == XMM1b_num ||
1616 reg == XMM2_num || reg == XMM2b_num ||
1617 reg == XMM3_num || reg == XMM3b_num ||
1618 reg == XMM4_num || reg == XMM4b_num ||
1619 reg == XMM5_num || reg == XMM5b_num ||
1620 reg == XMM6_num || reg == XMM6b_num ||
1621 reg == XMM7_num || reg == XMM7b_num;
1622 }
1623
1624 bool Matcher::is_spillable_arg(int reg)
1625 {
1626 return can_be_java_arg(reg);
1627 }
1628
1629 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1630 // In 64 bit mode a code which use multiply when
1631 // devisor is constant is faster than hardware
1632 // DIV instruction (it uses MulHiL).
1633 return false;
1634 }
1635
1636 // Register for DIVI projection of divmodI
1637 RegMask Matcher::divI_proj_mask() {
1638 return INT_RAX_REG_mask();
1639 }
1640
1641 // Register for MODI projection of divmodI
1642 RegMask Matcher::modI_proj_mask() {
1643 return INT_RDX_REG_mask();
1644 }
1645
1646 // Register for DIVL projection of divmodL
1647 RegMask Matcher::divL_proj_mask() {
1648 return LONG_RAX_REG_mask();
1649 }
1650
1651 // Register for MODL projection of divmodL
1652 RegMask Matcher::modL_proj_mask() {
1653 return LONG_RDX_REG_mask();
1654 }
1655
1656 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1657 return PTR_RBP_REG_mask();
1658 }
1659
1660 %}
1661
1662 //----------ENCODING BLOCK-----------------------------------------------------
1663 // This block specifies the encoding classes used by the compiler to
1664 // output byte streams. Encoding classes are parameterized macros
1665 // used by Machine Instruction Nodes in order to generate the bit
1666 // encoding of the instruction. Operands specify their base encoding
1667 // interface with the interface keyword. There are currently
1668 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1669 // COND_INTER. REG_INTER causes an operand to generate a function
1670 // which returns its register number when queried. CONST_INTER causes
1671 // an operand to generate a function which returns the value of the
1672 // constant when queried. MEMORY_INTER causes an operand to generate
1673 // four functions which return the Base Register, the Index Register,
1674 // the Scale Value, and the Offset Value of the operand when queried.
1675 // COND_INTER causes an operand to generate six functions which return
1676 // the encoding code (ie - encoding bits for the instruction)
1677 // associated with each basic boolean condition for a conditional
1678 // instruction.
1679 //
1680 // Instructions specify two basic values for encoding. Again, a
1681 // function is available to check if the constant displacement is an
1682 // oop. They use the ins_encode keyword to specify their encoding
1683 // classes (which must be a sequence of enc_class names, and their
1684 // parameters, specified in the encoding block), and they use the
1685 // opcode keyword to specify, in order, their primary, secondary, and
1686 // tertiary opcode. Only the opcode sections which a particular
1687 // instruction needs for encoding need to be specified.
1688 encode %{
1689 // Build emit functions for each basic byte or larger field in the
1690 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1691 // from C++ code in the enc_class source block. Emit functions will
1692 // live in the main source block for now. In future, we can
1693 // generalize this by adding a syntax that specifies the sizes of
1694 // fields in an order, so that the adlc can build the emit functions
1695 // automagically
1696
1697 // Emit primary opcode
1698 enc_class OpcP
1699 %{
1700 emit_opcode(cbuf, $primary);
1701 %}
1702
1703 // Emit secondary opcode
1704 enc_class OpcS
1705 %{
1706 emit_opcode(cbuf, $secondary);
1707 %}
1708
1709 // Emit tertiary opcode
1710 enc_class OpcT
1711 %{
1712 emit_opcode(cbuf, $tertiary);
1713 %}
1714
1715 // Emit opcode directly
1716 enc_class Opcode(immI d8)
1717 %{
1718 emit_opcode(cbuf, $d8$$constant);
1719 %}
1720
1721 // Emit size prefix
1722 enc_class SizePrefix
1723 %{
1724 emit_opcode(cbuf, 0x66);
1725 %}
1726
1727 enc_class reg(rRegI reg)
1728 %{
1729 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1730 %}
1731
1732 enc_class reg_reg(rRegI dst, rRegI src)
1733 %{
1734 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1735 %}
1736
1737 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1738 %{
1739 emit_opcode(cbuf, $opcode$$constant);
1740 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1741 %}
1742
1743 enc_class cdql_enc(no_rax_rdx_RegI div)
1744 %{
1745 // Full implementation of Java idiv and irem; checks for
1746 // special case as described in JVM spec., p.243 & p.271.
1747 //
1748 // normal case special case
1749 //
1750 // input : rax: dividend min_int
1751 // reg: divisor -1
1752 //
1753 // output: rax: quotient (= rax idiv reg) min_int
1754 // rdx: remainder (= rax irem reg) 0
1755 //
1756 // Code sequnce:
1757 //
1758 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1759 // 5: 75 07/08 jne e <normal>
1760 // 7: 33 d2 xor %edx,%edx
1761 // [div >= 8 -> offset + 1]
1762 // [REX_B]
1763 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1764 // c: 74 03/04 je 11 <done>
1765 // 000000000000000e <normal>:
1766 // e: 99 cltd
1767 // [div >= 8 -> offset + 1]
1768 // [REX_B]
1769 // f: f7 f9 idiv $div
1770 // 0000000000000011 <done>:
1771
1772 // cmp $0x80000000,%eax
1773 emit_opcode(cbuf, 0x3d);
1774 emit_d8(cbuf, 0x00);
1775 emit_d8(cbuf, 0x00);
1776 emit_d8(cbuf, 0x00);
1777 emit_d8(cbuf, 0x80);
1778
1779 // jne e <normal>
1780 emit_opcode(cbuf, 0x75);
1781 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1782
1783 // xor %edx,%edx
1784 emit_opcode(cbuf, 0x33);
1785 emit_d8(cbuf, 0xD2);
1786
1787 // cmp $0xffffffffffffffff,%ecx
1788 if ($div$$reg >= 8) {
1789 emit_opcode(cbuf, Assembler::REX_B);
1790 }
1791 emit_opcode(cbuf, 0x83);
1792 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1793 emit_d8(cbuf, 0xFF);
1794
1795 // je 11 <done>
1796 emit_opcode(cbuf, 0x74);
1797 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1798
1799 // <normal>
1800 // cltd
1801 emit_opcode(cbuf, 0x99);
1802
1803 // idivl (note: must be emitted by the user of this rule)
1804 // <done>
1805 %}
1806
1807 enc_class cdqq_enc(no_rax_rdx_RegL div)
1808 %{
1809 // Full implementation of Java ldiv and lrem; checks for
1810 // special case as described in JVM spec., p.243 & p.271.
1811 //
1812 // normal case special case
1813 //
1814 // input : rax: dividend min_long
1815 // reg: divisor -1
1816 //
1817 // output: rax: quotient (= rax idiv reg) min_long
1818 // rdx: remainder (= rax irem reg) 0
1819 //
1820 // Code sequnce:
1821 //
1822 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1823 // 7: 00 00 80
1824 // a: 48 39 d0 cmp %rdx,%rax
1825 // d: 75 08 jne 17 <normal>
1826 // f: 33 d2 xor %edx,%edx
1827 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1828 // 15: 74 05 je 1c <done>
1829 // 0000000000000017 <normal>:
1830 // 17: 48 99 cqto
1831 // 19: 48 f7 f9 idiv $div
1832 // 000000000000001c <done>:
1833
1834 // mov $0x8000000000000000,%rdx
1835 emit_opcode(cbuf, Assembler::REX_W);
1836 emit_opcode(cbuf, 0xBA);
1837 emit_d8(cbuf, 0x00);
1838 emit_d8(cbuf, 0x00);
1839 emit_d8(cbuf, 0x00);
1840 emit_d8(cbuf, 0x00);
1841 emit_d8(cbuf, 0x00);
1842 emit_d8(cbuf, 0x00);
1843 emit_d8(cbuf, 0x00);
1844 emit_d8(cbuf, 0x80);
1845
1846 // cmp %rdx,%rax
1847 emit_opcode(cbuf, Assembler::REX_W);
1848 emit_opcode(cbuf, 0x39);
1849 emit_d8(cbuf, 0xD0);
1850
1851 // jne 17 <normal>
1852 emit_opcode(cbuf, 0x75);
1853 emit_d8(cbuf, 0x08);
1854
1855 // xor %edx,%edx
1856 emit_opcode(cbuf, 0x33);
1857 emit_d8(cbuf, 0xD2);
1858
1859 // cmp $0xffffffffffffffff,$div
1860 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1861 emit_opcode(cbuf, 0x83);
1862 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1863 emit_d8(cbuf, 0xFF);
1864
1865 // je 1e <done>
1866 emit_opcode(cbuf, 0x74);
1867 emit_d8(cbuf, 0x05);
1868
1869 // <normal>
1870 // cqto
1871 emit_opcode(cbuf, Assembler::REX_W);
1872 emit_opcode(cbuf, 0x99);
1873
1874 // idivq (note: must be emitted by the user of this rule)
1875 // <done>
1876 %}
1877
1878 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1879 enc_class OpcSE(immI imm)
1880 %{
1881 // Emit primary opcode and set sign-extend bit
1882 // Check for 8-bit immediate, and set sign extend bit in opcode
1883 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1884 emit_opcode(cbuf, $primary | 0x02);
1885 } else {
1886 // 32-bit immediate
1887 emit_opcode(cbuf, $primary);
1888 }
1889 %}
1890
1891 enc_class OpcSErm(rRegI dst, immI imm)
1892 %{
1893 // OpcSEr/m
1894 int dstenc = $dst$$reg;
1895 if (dstenc >= 8) {
1896 emit_opcode(cbuf, Assembler::REX_B);
1897 dstenc -= 8;
1898 }
1899 // Emit primary opcode and set sign-extend bit
1900 // Check for 8-bit immediate, and set sign extend bit in opcode
1901 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1902 emit_opcode(cbuf, $primary | 0x02);
1903 } else {
1904 // 32-bit immediate
1905 emit_opcode(cbuf, $primary);
1906 }
1907 // Emit r/m byte with secondary opcode, after primary opcode.
1908 emit_rm(cbuf, 0x3, $secondary, dstenc);
1909 %}
1910
1911 enc_class OpcSErm_wide(rRegL dst, immI imm)
1912 %{
1913 // OpcSEr/m
1914 int dstenc = $dst$$reg;
1915 if (dstenc < 8) {
1916 emit_opcode(cbuf, Assembler::REX_W);
1917 } else {
1918 emit_opcode(cbuf, Assembler::REX_WB);
1919 dstenc -= 8;
1920 }
1921 // Emit primary opcode and set sign-extend bit
1922 // Check for 8-bit immediate, and set sign extend bit in opcode
1923 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1924 emit_opcode(cbuf, $primary | 0x02);
1925 } else {
1926 // 32-bit immediate
1927 emit_opcode(cbuf, $primary);
1928 }
1929 // Emit r/m byte with secondary opcode, after primary opcode.
1930 emit_rm(cbuf, 0x3, $secondary, dstenc);
1931 %}
1932
1933 enc_class Con8or32(immI imm)
1934 %{
1935 // Check for 8-bit immediate, and set sign extend bit in opcode
1936 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1937 $$$emit8$imm$$constant;
1938 } else {
1939 // 32-bit immediate
1940 $$$emit32$imm$$constant;
1941 }
1942 %}
1943
1944 enc_class opc2_reg(rRegI dst)
1945 %{
1946 // BSWAP
1947 emit_cc(cbuf, $secondary, $dst$$reg);
1948 %}
1949
1950 enc_class opc3_reg(rRegI dst)
1951 %{
1952 // BSWAP
1953 emit_cc(cbuf, $tertiary, $dst$$reg);
1954 %}
1955
1956 enc_class reg_opc(rRegI div)
1957 %{
1958 // INC, DEC, IDIV, IMOD, JMP indirect, ...
1959 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
1960 %}
1961
1962 enc_class enc_cmov(cmpOp cop)
1963 %{
1964 // CMOV
1965 $$$emit8$primary;
1966 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1967 %}
1968
1969 enc_class enc_PartialSubtypeCheck()
1970 %{
1971 Register Rrdi = as_Register(RDI_enc); // result register
1972 Register Rrax = as_Register(RAX_enc); // super class
1973 Register Rrcx = as_Register(RCX_enc); // killed
1974 Register Rrsi = as_Register(RSI_enc); // sub class
1975 Label miss;
1976 const bool set_cond_codes = true;
1977
1978 MacroAssembler _masm(&cbuf);
1979 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
1980 NULL, &miss,
1981 /*set_cond_codes:*/ true);
1982 if ($primary) {
1983 __ xorptr(Rrdi, Rrdi);
1984 }
1985 __ bind(miss);
1986 %}
1987
1988 enc_class clear_avx %{
1989 debug_only(int off0 = cbuf.insts_size());
1990 if (ra_->C->max_vector_size() > 16) {
1991 // Clear upper bits of YMM registers when current compiled code uses
1992 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1993 MacroAssembler _masm(&cbuf);
1994 __ vzeroupper();
1995 }
1996 debug_only(int off1 = cbuf.insts_size());
1997 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
1998 %}
1999
2000 enc_class Java_To_Runtime(method meth) %{
2001 // No relocation needed
2002 MacroAssembler _masm(&cbuf);
2003 __ mov64(r10, (int64_t) $meth$$method);
2004 __ call(r10);
2005 %}
2006
2007 enc_class Java_To_Interpreter(method meth)
2008 %{
2009 // CALL Java_To_Interpreter
2010 // This is the instruction starting address for relocation info.
2011 cbuf.set_insts_mark();
2012 $$$emit8$primary;
2013 // CALL directly to the runtime
2014 emit_d32_reloc(cbuf,
2015 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2016 runtime_call_Relocation::spec(),
2017 RELOC_DISP32);
2018 %}
2019
2020 enc_class Java_Static_Call(method meth)
2021 %{
2022 // JAVA STATIC CALL
2023 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2024 // determine who we intended to call.
2025 cbuf.set_insts_mark();
2026 $$$emit8$primary;
2027
2028 if (!_method) {
2029 emit_d32_reloc(cbuf,
2030 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2031 runtime_call_Relocation::spec(),
2032 RELOC_DISP32);
2033 } else if (_optimized_virtual) {
2034 emit_d32_reloc(cbuf,
2035 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2036 opt_virtual_call_Relocation::spec(),
2037 RELOC_DISP32);
2038 } else {
2039 emit_d32_reloc(cbuf,
2040 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2041 static_call_Relocation::spec(),
2042 RELOC_DISP32);
2043 }
2044 if (_method) {
2045 // Emit stub for static call.
2046 CompiledStaticCall::emit_to_interp_stub(cbuf);
2047 }
2048 %}
2049
2050 enc_class Java_Dynamic_Call(method meth) %{
2051 MacroAssembler _masm(&cbuf);
2052 __ ic_call((address)$meth$$method);
2053 %}
2054
2055 enc_class Java_Compiled_Call(method meth)
2056 %{
2057 // JAVA COMPILED CALL
2058 int disp = in_bytes(Method:: from_compiled_offset());
2059
2060 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2061 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2062
2063 // callq *disp(%rax)
2064 cbuf.set_insts_mark();
2065 $$$emit8$primary;
2066 if (disp < 0x80) {
2067 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2068 emit_d8(cbuf, disp); // Displacement
2069 } else {
2070 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2071 emit_d32(cbuf, disp); // Displacement
2072 }
2073 %}
2074
2075 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2076 %{
2077 // SAL, SAR, SHR
2078 int dstenc = $dst$$reg;
2079 if (dstenc >= 8) {
2080 emit_opcode(cbuf, Assembler::REX_B);
2081 dstenc -= 8;
2082 }
2083 $$$emit8$primary;
2084 emit_rm(cbuf, 0x3, $secondary, dstenc);
2085 $$$emit8$shift$$constant;
2086 %}
2087
2088 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2089 %{
2090 // SAL, SAR, SHR
2091 int dstenc = $dst$$reg;
2092 if (dstenc < 8) {
2093 emit_opcode(cbuf, Assembler::REX_W);
2094 } else {
2095 emit_opcode(cbuf, Assembler::REX_WB);
2096 dstenc -= 8;
2097 }
2098 $$$emit8$primary;
2099 emit_rm(cbuf, 0x3, $secondary, dstenc);
2100 $$$emit8$shift$$constant;
2101 %}
2102
2103 enc_class load_immI(rRegI dst, immI src)
2104 %{
2105 int dstenc = $dst$$reg;
2106 if (dstenc >= 8) {
2107 emit_opcode(cbuf, Assembler::REX_B);
2108 dstenc -= 8;
2109 }
2110 emit_opcode(cbuf, 0xB8 | dstenc);
2111 $$$emit32$src$$constant;
2112 %}
2113
2114 enc_class load_immL(rRegL dst, immL src)
2115 %{
2116 int dstenc = $dst$$reg;
2117 if (dstenc < 8) {
2118 emit_opcode(cbuf, Assembler::REX_W);
2119 } else {
2120 emit_opcode(cbuf, Assembler::REX_WB);
2121 dstenc -= 8;
2122 }
2123 emit_opcode(cbuf, 0xB8 | dstenc);
2124 emit_d64(cbuf, $src$$constant);
2125 %}
2126
2127 enc_class load_immUL32(rRegL dst, immUL32 src)
2128 %{
2129 // same as load_immI, but this time we care about zeroes in the high word
2130 int dstenc = $dst$$reg;
2131 if (dstenc >= 8) {
2132 emit_opcode(cbuf, Assembler::REX_B);
2133 dstenc -= 8;
2134 }
2135 emit_opcode(cbuf, 0xB8 | dstenc);
2136 $$$emit32$src$$constant;
2137 %}
2138
2139 enc_class load_immL32(rRegL dst, immL32 src)
2140 %{
2141 int dstenc = $dst$$reg;
2142 if (dstenc < 8) {
2143 emit_opcode(cbuf, Assembler::REX_W);
2144 } else {
2145 emit_opcode(cbuf, Assembler::REX_WB);
2146 dstenc -= 8;
2147 }
2148 emit_opcode(cbuf, 0xC7);
2149 emit_rm(cbuf, 0x03, 0x00, dstenc);
2150 $$$emit32$src$$constant;
2151 %}
2152
2153 enc_class load_immP31(rRegP dst, immP32 src)
2154 %{
2155 // same as load_immI, but this time we care about zeroes in the high word
2156 int dstenc = $dst$$reg;
2157 if (dstenc >= 8) {
2158 emit_opcode(cbuf, Assembler::REX_B);
2159 dstenc -= 8;
2160 }
2161 emit_opcode(cbuf, 0xB8 | dstenc);
2162 $$$emit32$src$$constant;
2163 %}
2164
2165 enc_class load_immP(rRegP dst, immP src)
2166 %{
2167 int dstenc = $dst$$reg;
2168 if (dstenc < 8) {
2169 emit_opcode(cbuf, Assembler::REX_W);
2170 } else {
2171 emit_opcode(cbuf, Assembler::REX_WB);
2172 dstenc -= 8;
2173 }
2174 emit_opcode(cbuf, 0xB8 | dstenc);
2175 // This next line should be generated from ADLC
2176 if ($src->constant_reloc() != relocInfo::none) {
2177 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2178 } else {
2179 emit_d64(cbuf, $src$$constant);
2180 }
2181 %}
2182
2183 enc_class Con32(immI src)
2184 %{
2185 // Output immediate
2186 $$$emit32$src$$constant;
2187 %}
2188
2189 enc_class Con32F_as_bits(immF src)
2190 %{
2191 // Output Float immediate bits
2192 jfloat jf = $src$$constant;
2193 jint jf_as_bits = jint_cast(jf);
2194 emit_d32(cbuf, jf_as_bits);
2195 %}
2196
2197 enc_class Con16(immI src)
2198 %{
2199 // Output immediate
2200 $$$emit16$src$$constant;
2201 %}
2202
2203 // How is this different from Con32??? XXX
2204 enc_class Con_d32(immI src)
2205 %{
2206 emit_d32(cbuf,$src$$constant);
2207 %}
2208
2209 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2210 // Output immediate memory reference
2211 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2212 emit_d32(cbuf, 0x00);
2213 %}
2214
2215 enc_class lock_prefix()
2216 %{
2217 if (os::is_MP()) {
2218 emit_opcode(cbuf, 0xF0); // lock
2219 }
2220 %}
2221
2222 enc_class REX_mem(memory mem)
2223 %{
2224 if ($mem$$base >= 8) {
2225 if ($mem$$index < 8) {
2226 emit_opcode(cbuf, Assembler::REX_B);
2227 } else {
2228 emit_opcode(cbuf, Assembler::REX_XB);
2229 }
2230 } else {
2231 if ($mem$$index >= 8) {
2232 emit_opcode(cbuf, Assembler::REX_X);
2233 }
2234 }
2235 %}
2236
2237 enc_class REX_mem_wide(memory mem)
2238 %{
2239 if ($mem$$base >= 8) {
2240 if ($mem$$index < 8) {
2241 emit_opcode(cbuf, Assembler::REX_WB);
2242 } else {
2243 emit_opcode(cbuf, Assembler::REX_WXB);
2244 }
2245 } else {
2246 if ($mem$$index < 8) {
2247 emit_opcode(cbuf, Assembler::REX_W);
2248 } else {
2249 emit_opcode(cbuf, Assembler::REX_WX);
2250 }
2251 }
2252 %}
2253
2254 // for byte regs
2255 enc_class REX_breg(rRegI reg)
2256 %{
2257 if ($reg$$reg >= 4) {
2258 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2259 }
2260 %}
2261
2262 // for byte regs
2263 enc_class REX_reg_breg(rRegI dst, rRegI src)
2264 %{
2265 if ($dst$$reg < 8) {
2266 if ($src$$reg >= 4) {
2267 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2268 }
2269 } else {
2270 if ($src$$reg < 8) {
2271 emit_opcode(cbuf, Assembler::REX_R);
2272 } else {
2273 emit_opcode(cbuf, Assembler::REX_RB);
2274 }
2275 }
2276 %}
2277
2278 // for byte regs
2279 enc_class REX_breg_mem(rRegI reg, memory mem)
2280 %{
2281 if ($reg$$reg < 8) {
2282 if ($mem$$base < 8) {
2283 if ($mem$$index >= 8) {
2284 emit_opcode(cbuf, Assembler::REX_X);
2285 } else if ($reg$$reg >= 4) {
2286 emit_opcode(cbuf, Assembler::REX);
2287 }
2288 } else {
2289 if ($mem$$index < 8) {
2290 emit_opcode(cbuf, Assembler::REX_B);
2291 } else {
2292 emit_opcode(cbuf, Assembler::REX_XB);
2293 }
2294 }
2295 } else {
2296 if ($mem$$base < 8) {
2297 if ($mem$$index < 8) {
2298 emit_opcode(cbuf, Assembler::REX_R);
2299 } else {
2300 emit_opcode(cbuf, Assembler::REX_RX);
2301 }
2302 } else {
2303 if ($mem$$index < 8) {
2304 emit_opcode(cbuf, Assembler::REX_RB);
2305 } else {
2306 emit_opcode(cbuf, Assembler::REX_RXB);
2307 }
2308 }
2309 }
2310 %}
2311
2312 enc_class REX_reg(rRegI reg)
2313 %{
2314 if ($reg$$reg >= 8) {
2315 emit_opcode(cbuf, Assembler::REX_B);
2316 }
2317 %}
2318
2319 enc_class REX_reg_wide(rRegI reg)
2320 %{
2321 if ($reg$$reg < 8) {
2322 emit_opcode(cbuf, Assembler::REX_W);
2323 } else {
2324 emit_opcode(cbuf, Assembler::REX_WB);
2325 }
2326 %}
2327
2328 enc_class REX_reg_reg(rRegI dst, rRegI src)
2329 %{
2330 if ($dst$$reg < 8) {
2331 if ($src$$reg >= 8) {
2332 emit_opcode(cbuf, Assembler::REX_B);
2333 }
2334 } else {
2335 if ($src$$reg < 8) {
2336 emit_opcode(cbuf, Assembler::REX_R);
2337 } else {
2338 emit_opcode(cbuf, Assembler::REX_RB);
2339 }
2340 }
2341 %}
2342
2343 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2344 %{
2345 if ($dst$$reg < 8) {
2346 if ($src$$reg < 8) {
2347 emit_opcode(cbuf, Assembler::REX_W);
2348 } else {
2349 emit_opcode(cbuf, Assembler::REX_WB);
2350 }
2351 } else {
2352 if ($src$$reg < 8) {
2353 emit_opcode(cbuf, Assembler::REX_WR);
2354 } else {
2355 emit_opcode(cbuf, Assembler::REX_WRB);
2356 }
2357 }
2358 %}
2359
2360 enc_class REX_reg_mem(rRegI reg, memory mem)
2361 %{
2362 if ($reg$$reg < 8) {
2363 if ($mem$$base < 8) {
2364 if ($mem$$index >= 8) {
2365 emit_opcode(cbuf, Assembler::REX_X);
2366 }
2367 } else {
2368 if ($mem$$index < 8) {
2369 emit_opcode(cbuf, Assembler::REX_B);
2370 } else {
2371 emit_opcode(cbuf, Assembler::REX_XB);
2372 }
2373 }
2374 } else {
2375 if ($mem$$base < 8) {
2376 if ($mem$$index < 8) {
2377 emit_opcode(cbuf, Assembler::REX_R);
2378 } else {
2379 emit_opcode(cbuf, Assembler::REX_RX);
2380 }
2381 } else {
2382 if ($mem$$index < 8) {
2383 emit_opcode(cbuf, Assembler::REX_RB);
2384 } else {
2385 emit_opcode(cbuf, Assembler::REX_RXB);
2386 }
2387 }
2388 }
2389 %}
2390
2391 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2392 %{
2393 if ($reg$$reg < 8) {
2394 if ($mem$$base < 8) {
2395 if ($mem$$index < 8) {
2396 emit_opcode(cbuf, Assembler::REX_W);
2397 } else {
2398 emit_opcode(cbuf, Assembler::REX_WX);
2399 }
2400 } else {
2401 if ($mem$$index < 8) {
2402 emit_opcode(cbuf, Assembler::REX_WB);
2403 } else {
2404 emit_opcode(cbuf, Assembler::REX_WXB);
2405 }
2406 }
2407 } else {
2408 if ($mem$$base < 8) {
2409 if ($mem$$index < 8) {
2410 emit_opcode(cbuf, Assembler::REX_WR);
2411 } else {
2412 emit_opcode(cbuf, Assembler::REX_WRX);
2413 }
2414 } else {
2415 if ($mem$$index < 8) {
2416 emit_opcode(cbuf, Assembler::REX_WRB);
2417 } else {
2418 emit_opcode(cbuf, Assembler::REX_WRXB);
2419 }
2420 }
2421 }
2422 %}
2423
2424 enc_class reg_mem(rRegI ereg, memory mem)
2425 %{
2426 // High registers handle in encode_RegMem
2427 int reg = $ereg$$reg;
2428 int base = $mem$$base;
2429 int index = $mem$$index;
2430 int scale = $mem$$scale;
2431 int disp = $mem$$disp;
2432 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2433
2434 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2435 %}
2436
2437 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2438 %{
2439 int rm_byte_opcode = $rm_opcode$$constant;
2440
2441 // High registers handle in encode_RegMem
2442 int base = $mem$$base;
2443 int index = $mem$$index;
2444 int scale = $mem$$scale;
2445 int displace = $mem$$disp;
2446
2447 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2448 // working with static
2449 // globals
2450 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2451 disp_reloc);
2452 %}
2453
2454 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2455 %{
2456 int reg_encoding = $dst$$reg;
2457 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2458 int index = 0x04; // 0x04 indicates no index
2459 int scale = 0x00; // 0x00 indicates no scale
2460 int displace = $src1$$constant; // 0x00 indicates no displacement
2461 relocInfo::relocType disp_reloc = relocInfo::none;
2462 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2463 disp_reloc);
2464 %}
2465
2466 enc_class neg_reg(rRegI dst)
2467 %{
2468 int dstenc = $dst$$reg;
2469 if (dstenc >= 8) {
2470 emit_opcode(cbuf, Assembler::REX_B);
2471 dstenc -= 8;
2472 }
2473 // NEG $dst
2474 emit_opcode(cbuf, 0xF7);
2475 emit_rm(cbuf, 0x3, 0x03, dstenc);
2476 %}
2477
2478 enc_class neg_reg_wide(rRegI dst)
2479 %{
2480 int dstenc = $dst$$reg;
2481 if (dstenc < 8) {
2482 emit_opcode(cbuf, Assembler::REX_W);
2483 } else {
2484 emit_opcode(cbuf, Assembler::REX_WB);
2485 dstenc -= 8;
2486 }
2487 // NEG $dst
2488 emit_opcode(cbuf, 0xF7);
2489 emit_rm(cbuf, 0x3, 0x03, dstenc);
2490 %}
2491
2492 enc_class setLT_reg(rRegI dst)
2493 %{
2494 int dstenc = $dst$$reg;
2495 if (dstenc >= 8) {
2496 emit_opcode(cbuf, Assembler::REX_B);
2497 dstenc -= 8;
2498 } else if (dstenc >= 4) {
2499 emit_opcode(cbuf, Assembler::REX);
2500 }
2501 // SETLT $dst
2502 emit_opcode(cbuf, 0x0F);
2503 emit_opcode(cbuf, 0x9C);
2504 emit_rm(cbuf, 0x3, 0x0, dstenc);
2505 %}
2506
2507 enc_class setNZ_reg(rRegI dst)
2508 %{
2509 int dstenc = $dst$$reg;
2510 if (dstenc >= 8) {
2511 emit_opcode(cbuf, Assembler::REX_B);
2512 dstenc -= 8;
2513 } else if (dstenc >= 4) {
2514 emit_opcode(cbuf, Assembler::REX);
2515 }
2516 // SETNZ $dst
2517 emit_opcode(cbuf, 0x0F);
2518 emit_opcode(cbuf, 0x95);
2519 emit_rm(cbuf, 0x3, 0x0, dstenc);
2520 %}
2521
2522
2523 // Compare the lonogs and set -1, 0, or 1 into dst
2524 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2525 %{
2526 int src1enc = $src1$$reg;
2527 int src2enc = $src2$$reg;
2528 int dstenc = $dst$$reg;
2529
2530 // cmpq $src1, $src2
2531 if (src1enc < 8) {
2532 if (src2enc < 8) {
2533 emit_opcode(cbuf, Assembler::REX_W);
2534 } else {
2535 emit_opcode(cbuf, Assembler::REX_WB);
2536 }
2537 } else {
2538 if (src2enc < 8) {
2539 emit_opcode(cbuf, Assembler::REX_WR);
2540 } else {
2541 emit_opcode(cbuf, Assembler::REX_WRB);
2542 }
2543 }
2544 emit_opcode(cbuf, 0x3B);
2545 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2546
2547 // movl $dst, -1
2548 if (dstenc >= 8) {
2549 emit_opcode(cbuf, Assembler::REX_B);
2550 }
2551 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2552 emit_d32(cbuf, -1);
2553
2554 // jl,s done
2555 emit_opcode(cbuf, 0x7C);
2556 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2557
2558 // setne $dst
2559 if (dstenc >= 4) {
2560 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2561 }
2562 emit_opcode(cbuf, 0x0F);
2563 emit_opcode(cbuf, 0x95);
2564 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2565
2566 // movzbl $dst, $dst
2567 if (dstenc >= 4) {
2568 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2569 }
2570 emit_opcode(cbuf, 0x0F);
2571 emit_opcode(cbuf, 0xB6);
2572 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2573 %}
2574
2575 enc_class Push_ResultXD(regD dst) %{
2576 MacroAssembler _masm(&cbuf);
2577 __ fstp_d(Address(rsp, 0));
2578 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2579 __ addptr(rsp, 8);
2580 %}
2581
2582 enc_class Push_SrcXD(regD src) %{
2583 MacroAssembler _masm(&cbuf);
2584 __ subptr(rsp, 8);
2585 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2586 __ fld_d(Address(rsp, 0));
2587 %}
2588
2589
2590 enc_class enc_rethrow()
2591 %{
2592 cbuf.set_insts_mark();
2593 emit_opcode(cbuf, 0xE9); // jmp entry
2594 emit_d32_reloc(cbuf,
2595 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2596 runtime_call_Relocation::spec(),
2597 RELOC_DISP32);
2598 %}
2599
2600 %}
2601
2602
2603
2604 //----------FRAME--------------------------------------------------------------
2605 // Definition of frame structure and management information.
2606 //
2607 // S T A C K L A Y O U T Allocators stack-slot number
2608 // | (to get allocators register number
2609 // G Owned by | | v add OptoReg::stack0())
2610 // r CALLER | |
2611 // o | +--------+ pad to even-align allocators stack-slot
2612 // w V | pad0 | numbers; owned by CALLER
2613 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2614 // h ^ | in | 5
2615 // | | args | 4 Holes in incoming args owned by SELF
2616 // | | | | 3
2617 // | | +--------+
2618 // V | | old out| Empty on Intel, window on Sparc
2619 // | old |preserve| Must be even aligned.
2620 // | SP-+--------+----> Matcher::_old_SP, even aligned
2621 // | | in | 3 area for Intel ret address
2622 // Owned by |preserve| Empty on Sparc.
2623 // SELF +--------+
2624 // | | pad2 | 2 pad to align old SP
2625 // | +--------+ 1
2626 // | | locks | 0
2627 // | +--------+----> OptoReg::stack0(), even aligned
2628 // | | pad1 | 11 pad to align new SP
2629 // | +--------+
2630 // | | | 10
2631 // | | spills | 9 spills
2632 // V | | 8 (pad0 slot for callee)
2633 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2634 // ^ | out | 7
2635 // | | args | 6 Holes in outgoing args owned by CALLEE
2636 // Owned by +--------+
2637 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2638 // | new |preserve| Must be even-aligned.
2639 // | SP-+--------+----> Matcher::_new_SP, even aligned
2640 // | | |
2641 //
2642 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2643 // known from SELF's arguments and the Java calling convention.
2644 // Region 6-7 is determined per call site.
2645 // Note 2: If the calling convention leaves holes in the incoming argument
2646 // area, those holes are owned by SELF. Holes in the outgoing area
2647 // are owned by the CALLEE. Holes should not be nessecary in the
2648 // incoming area, as the Java calling convention is completely under
2649 // the control of the AD file. Doubles can be sorted and packed to
2650 // avoid holes. Holes in the outgoing arguments may be nessecary for
2651 // varargs C calling conventions.
2652 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2653 // even aligned with pad0 as needed.
2654 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2655 // region 6-11 is even aligned; it may be padded out more so that
2656 // the region from SP to FP meets the minimum stack alignment.
2657 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2658 // alignment. Region 11, pad1, may be dynamically extended so that
2659 // SP meets the minimum alignment.
2660
2661 frame
2662 %{
2663 // What direction does stack grow in (assumed to be same for C & Java)
2664 stack_direction(TOWARDS_LOW);
2665
2666 // These three registers define part of the calling convention
2667 // between compiled code and the interpreter.
2668 inline_cache_reg(RAX); // Inline Cache Register
2669 interpreter_method_oop_reg(RBX); // Method Oop Register when
2670 // calling interpreter
2671
2672 // Optional: name the operand used by cisc-spilling to access
2673 // [stack_pointer + offset]
2674 cisc_spilling_operand_name(indOffset32);
2675
2676 // Number of stack slots consumed by locking an object
2677 sync_stack_slots(2);
2678
2679 // Compiled code's Frame Pointer
2680 frame_pointer(RSP);
2681
2682 // Interpreter stores its frame pointer in a register which is
2683 // stored to the stack by I2CAdaptors.
2684 // I2CAdaptors convert from interpreted java to compiled java.
2685 interpreter_frame_pointer(RBP);
2686
2687 // Stack alignment requirement
2688 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2689
2690 // Number of stack slots between incoming argument block and the start of
2691 // a new frame. The PROLOG must add this many slots to the stack. The
2692 // EPILOG must remove this many slots. amd64 needs two slots for
2693 // return address.
2694 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2695
2696 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2697 // for calls to C. Supports the var-args backing area for register parms.
2698 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2699
2700 // The after-PROLOG location of the return address. Location of
2701 // return address specifies a type (REG or STACK) and a number
2702 // representing the register number (i.e. - use a register name) or
2703 // stack slot.
2704 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2705 // Otherwise, it is above the locks and verification slot and alignment word
2706 return_addr(STACK - 2 +
2707 round_to((Compile::current()->in_preserve_stack_slots() +
2708 Compile::current()->fixed_slots()),
2709 stack_alignment_in_slots()));
2710
2711 // Body of function which returns an integer array locating
2712 // arguments either in registers or in stack slots. Passed an array
2713 // of ideal registers called "sig" and a "length" count. Stack-slot
2714 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2715 // arguments for a CALLEE. Incoming stack arguments are
2716 // automatically biased by the preserve_stack_slots field above.
2717
2718 calling_convention
2719 %{
2720 // No difference between ingoing/outgoing just pass false
2721 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2722 %}
2723
2724 c_calling_convention
2725 %{
2726 // This is obviously always outgoing
2727 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2728 %}
2729
2730 // Location of compiled Java return values. Same as C for now.
2731 return_value
2732 %{
2733 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2734 "only return normal values");
2735
2736 static const int lo[Op_RegL + 1] = {
2737 0,
2738 0,
2739 RAX_num, // Op_RegN
2740 RAX_num, // Op_RegI
2741 RAX_num, // Op_RegP
2742 XMM0_num, // Op_RegF
2743 XMM0_num, // Op_RegD
2744 RAX_num // Op_RegL
2745 };
2746 static const int hi[Op_RegL + 1] = {
2747 0,
2748 0,
2749 OptoReg::Bad, // Op_RegN
2750 OptoReg::Bad, // Op_RegI
2751 RAX_H_num, // Op_RegP
2752 OptoReg::Bad, // Op_RegF
2753 XMM0b_num, // Op_RegD
2754 RAX_H_num // Op_RegL
2755 };
2756 // Excluded flags and vector registers.
2757 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
2758 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2759 %}
2760 %}
2761
2762 //----------ATTRIBUTES---------------------------------------------------------
2763 //----------Operand Attributes-------------------------------------------------
2764 op_attrib op_cost(0); // Required cost attribute
2765
2766 //----------Instruction Attributes---------------------------------------------
2767 ins_attrib ins_cost(100); // Required cost attribute
2768 ins_attrib ins_size(8); // Required size attribute (in bits)
2769 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2770 // a non-matching short branch variant
2771 // of some long branch?
2772 ins_attrib ins_alignment(1); // Required alignment attribute (must
2773 // be a power of 2) specifies the
2774 // alignment that some part of the
2775 // instruction (not necessarily the
2776 // start) requires. If > 1, a
2777 // compute_padding() function must be
2778 // provided for the instruction
2779
2780 //----------OPERANDS-----------------------------------------------------------
2781 // Operand definitions must precede instruction definitions for correct parsing
2782 // in the ADLC because operands constitute user defined types which are used in
2783 // instruction definitions.
2784
2785 //----------Simple Operands----------------------------------------------------
2786 // Immediate Operands
2787 // Integer Immediate
2788 operand immI()
2789 %{
2790 match(ConI);
2791
2792 op_cost(10);
2793 format %{ %}
2794 interface(CONST_INTER);
2795 %}
2796
2797 // Constant for test vs zero
2798 operand immI0()
2799 %{
2800 predicate(n->get_int() == 0);
2801 match(ConI);
2802
2803 op_cost(0);
2804 format %{ %}
2805 interface(CONST_INTER);
2806 %}
2807
2808 // Constant for increment
2809 operand immI1()
2810 %{
2811 predicate(n->get_int() == 1);
2812 match(ConI);
2813
2814 op_cost(0);
2815 format %{ %}
2816 interface(CONST_INTER);
2817 %}
2818
2819 // Constant for decrement
2820 operand immI_M1()
2821 %{
2822 predicate(n->get_int() == -1);
2823 match(ConI);
2824
2825 op_cost(0);
2826 format %{ %}
2827 interface(CONST_INTER);
2828 %}
2829
2830 // Valid scale values for addressing modes
2831 operand immI2()
2832 %{
2833 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2834 match(ConI);
2835
2836 format %{ %}
2837 interface(CONST_INTER);
2838 %}
2839
2840 operand immI8()
2841 %{
2842 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2843 match(ConI);
2844
2845 op_cost(5);
2846 format %{ %}
2847 interface(CONST_INTER);
2848 %}
2849
2850 operand immI16()
2851 %{
2852 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2853 match(ConI);
2854
2855 op_cost(10);
2856 format %{ %}
2857 interface(CONST_INTER);
2858 %}
2859
2860 // Int Immediate non-negative
2861 operand immU31()
2862 %{
2863 predicate(n->get_int() >= 0);
2864 match(ConI);
2865
2866 op_cost(0);
2867 format %{ %}
2868 interface(CONST_INTER);
2869 %}
2870
2871 // Constant for long shifts
2872 operand immI_32()
2873 %{
2874 predicate( n->get_int() == 32 );
2875 match(ConI);
2876
2877 op_cost(0);
2878 format %{ %}
2879 interface(CONST_INTER);
2880 %}
2881
2882 // Constant for long shifts
2883 operand immI_64()
2884 %{
2885 predicate( n->get_int() == 64 );
2886 match(ConI);
2887
2888 op_cost(0);
2889 format %{ %}
2890 interface(CONST_INTER);
2891 %}
2892
2893 // Pointer Immediate
2894 operand immP()
2895 %{
2896 match(ConP);
2897
2898 op_cost(10);
2899 format %{ %}
2900 interface(CONST_INTER);
2901 %}
2902
2903 // NULL Pointer Immediate
2904 operand immP0()
2905 %{
2906 predicate(n->get_ptr() == 0);
2907 match(ConP);
2908
2909 op_cost(5);
2910 format %{ %}
2911 interface(CONST_INTER);
2912 %}
2913
2914 // Pointer Immediate
2915 operand immN() %{
2916 match(ConN);
2917
2918 op_cost(10);
2919 format %{ %}
2920 interface(CONST_INTER);
2921 %}
2922
2923 operand immNKlass() %{
2924 match(ConNKlass);
2925
2926 op_cost(10);
2927 format %{ %}
2928 interface(CONST_INTER);
2929 %}
2930
2931 // NULL Pointer Immediate
2932 operand immN0() %{
2933 predicate(n->get_narrowcon() == 0);
2934 match(ConN);
2935
2936 op_cost(5);
2937 format %{ %}
2938 interface(CONST_INTER);
2939 %}
2940
2941 operand immP31()
2942 %{
2943 predicate(n->as_Type()->type()->reloc() == relocInfo::none
2944 && (n->get_ptr() >> 31) == 0);
2945 match(ConP);
2946
2947 op_cost(5);
2948 format %{ %}
2949 interface(CONST_INTER);
2950 %}
2951
2952
2953 // Long Immediate
2954 operand immL()
2955 %{
2956 match(ConL);
2957
2958 op_cost(20);
2959 format %{ %}
2960 interface(CONST_INTER);
2961 %}
2962
2963 // Long Immediate 8-bit
2964 operand immL8()
2965 %{
2966 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
2967 match(ConL);
2968
2969 op_cost(5);
2970 format %{ %}
2971 interface(CONST_INTER);
2972 %}
2973
2974 // Long Immediate 32-bit unsigned
2975 operand immUL32()
2976 %{
2977 predicate(n->get_long() == (unsigned int) (n->get_long()));
2978 match(ConL);
2979
2980 op_cost(10);
2981 format %{ %}
2982 interface(CONST_INTER);
2983 %}
2984
2985 // Long Immediate 32-bit signed
2986 operand immL32()
2987 %{
2988 predicate(n->get_long() == (int) (n->get_long()));
2989 match(ConL);
2990
2991 op_cost(15);
2992 format %{ %}
2993 interface(CONST_INTER);
2994 %}
2995
2996 // Long Immediate zero
2997 operand immL0()
2998 %{
2999 predicate(n->get_long() == 0L);
3000 match(ConL);
3001
3002 op_cost(10);
3003 format %{ %}
3004 interface(CONST_INTER);
3005 %}
3006
3007 // Constant for increment
3008 operand immL1()
3009 %{
3010 predicate(n->get_long() == 1);
3011 match(ConL);
3012
3013 format %{ %}
3014 interface(CONST_INTER);
3015 %}
3016
3017 // Constant for decrement
3018 operand immL_M1()
3019 %{
3020 predicate(n->get_long() == -1);
3021 match(ConL);
3022
3023 format %{ %}
3024 interface(CONST_INTER);
3025 %}
3026
3027 // Long Immediate: the value 10
3028 operand immL10()
3029 %{
3030 predicate(n->get_long() == 10);
3031 match(ConL);
3032
3033 format %{ %}
3034 interface(CONST_INTER);
3035 %}
3036
3037 // Long immediate from 0 to 127.
3038 // Used for a shorter form of long mul by 10.
3039 operand immL_127()
3040 %{
3041 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3042 match(ConL);
3043
3044 op_cost(10);
3045 format %{ %}
3046 interface(CONST_INTER);
3047 %}
3048
3049 // Long Immediate: low 32-bit mask
3050 operand immL_32bits()
3051 %{
3052 predicate(n->get_long() == 0xFFFFFFFFL);
3053 match(ConL);
3054 op_cost(20);
3055
3056 format %{ %}
3057 interface(CONST_INTER);
3058 %}
3059
3060 // Float Immediate zero
3061 operand immF0()
3062 %{
3063 predicate(jint_cast(n->getf()) == 0);
3064 match(ConF);
3065
3066 op_cost(5);
3067 format %{ %}
3068 interface(CONST_INTER);
3069 %}
3070
3071 // Float Immediate
3072 operand immF()
3073 %{
3074 match(ConF);
3075
3076 op_cost(15);
3077 format %{ %}
3078 interface(CONST_INTER);
3079 %}
3080
3081 // Double Immediate zero
3082 operand immD0()
3083 %{
3084 predicate(jlong_cast(n->getd()) == 0);
3085 match(ConD);
3086
3087 op_cost(5);
3088 format %{ %}
3089 interface(CONST_INTER);
3090 %}
3091
3092 // Double Immediate
3093 operand immD()
3094 %{
3095 match(ConD);
3096
3097 op_cost(15);
3098 format %{ %}
3099 interface(CONST_INTER);
3100 %}
3101
3102 // Immediates for special shifts (sign extend)
3103
3104 // Constants for increment
3105 operand immI_16()
3106 %{
3107 predicate(n->get_int() == 16);
3108 match(ConI);
3109
3110 format %{ %}
3111 interface(CONST_INTER);
3112 %}
3113
3114 operand immI_24()
3115 %{
3116 predicate(n->get_int() == 24);
3117 match(ConI);
3118
3119 format %{ %}
3120 interface(CONST_INTER);
3121 %}
3122
3123 // Constant for byte-wide masking
3124 operand immI_255()
3125 %{
3126 predicate(n->get_int() == 255);
3127 match(ConI);
3128
3129 format %{ %}
3130 interface(CONST_INTER);
3131 %}
3132
3133 // Constant for short-wide masking
3134 operand immI_65535()
3135 %{
3136 predicate(n->get_int() == 65535);
3137 match(ConI);
3138
3139 format %{ %}
3140 interface(CONST_INTER);
3141 %}
3142
3143 // Constant for byte-wide masking
3144 operand immL_255()
3145 %{
3146 predicate(n->get_long() == 255);
3147 match(ConL);
3148
3149 format %{ %}
3150 interface(CONST_INTER);
3151 %}
3152
3153 // Constant for short-wide masking
3154 operand immL_65535()
3155 %{
3156 predicate(n->get_long() == 65535);
3157 match(ConL);
3158
3159 format %{ %}
3160 interface(CONST_INTER);
3161 %}
3162
3163 // Register Operands
3164 // Integer Register
3165 operand rRegI()
3166 %{
3167 constraint(ALLOC_IN_RC(int_reg));
3168 match(RegI);
3169
3170 match(rax_RegI);
3171 match(rbx_RegI);
3172 match(rcx_RegI);
3173 match(rdx_RegI);
3174 match(rdi_RegI);
3175
3176 format %{ %}
3177 interface(REG_INTER);
3178 %}
3179
3180 // Special Registers
3181 operand rax_RegI()
3182 %{
3183 constraint(ALLOC_IN_RC(int_rax_reg));
3184 match(RegI);
3185 match(rRegI);
3186
3187 format %{ "RAX" %}
3188 interface(REG_INTER);
3189 %}
3190
3191 // Special Registers
3192 operand rbx_RegI()
3193 %{
3194 constraint(ALLOC_IN_RC(int_rbx_reg));
3195 match(RegI);
3196 match(rRegI);
3197
3198 format %{ "RBX" %}
3199 interface(REG_INTER);
3200 %}
3201
3202 operand rcx_RegI()
3203 %{
3204 constraint(ALLOC_IN_RC(int_rcx_reg));
3205 match(RegI);
3206 match(rRegI);
3207
3208 format %{ "RCX" %}
3209 interface(REG_INTER);
3210 %}
3211
3212 operand rdx_RegI()
3213 %{
3214 constraint(ALLOC_IN_RC(int_rdx_reg));
3215 match(RegI);
3216 match(rRegI);
3217
3218 format %{ "RDX" %}
3219 interface(REG_INTER);
3220 %}
3221
3222 operand rdi_RegI()
3223 %{
3224 constraint(ALLOC_IN_RC(int_rdi_reg));
3225 match(RegI);
3226 match(rRegI);
3227
3228 format %{ "RDI" %}
3229 interface(REG_INTER);
3230 %}
3231
3232 operand no_rcx_RegI()
3233 %{
3234 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3235 match(RegI);
3236 match(rax_RegI);
3237 match(rbx_RegI);
3238 match(rdx_RegI);
3239 match(rdi_RegI);
3240
3241 format %{ %}
3242 interface(REG_INTER);
3243 %}
3244
3245 operand no_rax_rdx_RegI()
3246 %{
3247 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3248 match(RegI);
3249 match(rbx_RegI);
3250 match(rcx_RegI);
3251 match(rdi_RegI);
3252
3253 format %{ %}
3254 interface(REG_INTER);
3255 %}
3256
3257 // Pointer Register
3258 operand any_RegP()
3259 %{
3260 constraint(ALLOC_IN_RC(any_reg));
3261 match(RegP);
3262 match(rax_RegP);
3263 match(rbx_RegP);
3264 match(rdi_RegP);
3265 match(rsi_RegP);
3266 match(rbp_RegP);
3267 match(r15_RegP);
3268 match(rRegP);
3269
3270 format %{ %}
3271 interface(REG_INTER);
3272 %}
3273
3274 operand rRegP()
3275 %{
3276 constraint(ALLOC_IN_RC(ptr_reg));
3277 match(RegP);
3278 match(rax_RegP);
3279 match(rbx_RegP);
3280 match(rdi_RegP);
3281 match(rsi_RegP);
3282 match(rbp_RegP);
3283 match(r15_RegP); // See Q&A below about r15_RegP.
3284
3285 format %{ %}
3286 interface(REG_INTER);
3287 %}
3288
3289 operand rRegN() %{
3290 constraint(ALLOC_IN_RC(int_reg));
3291 match(RegN);
3292
3293 format %{ %}
3294 interface(REG_INTER);
3295 %}
3296
3297 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3298 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3299 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
3300 // The output of an instruction is controlled by the allocator, which respects
3301 // register class masks, not match rules. Unless an instruction mentions
3302 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3303 // by the allocator as an input.
3304
3305 operand no_rax_RegP()
3306 %{
3307 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3308 match(RegP);
3309 match(rbx_RegP);
3310 match(rsi_RegP);
3311 match(rdi_RegP);
3312
3313 format %{ %}
3314 interface(REG_INTER);
3315 %}
3316
3317 operand no_rbp_RegP()
3318 %{
3319 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
3320 match(RegP);
3321 match(rbx_RegP);
3322 match(rsi_RegP);
3323 match(rdi_RegP);
3324
3325 format %{ %}
3326 interface(REG_INTER);
3327 %}
3328
3329 operand no_rax_rbx_RegP()
3330 %{
3331 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3332 match(RegP);
3333 match(rsi_RegP);
3334 match(rdi_RegP);
3335
3336 format %{ %}
3337 interface(REG_INTER);
3338 %}
3339
3340 // Special Registers
3341 // Return a pointer value
3342 operand rax_RegP()
3343 %{
3344 constraint(ALLOC_IN_RC(ptr_rax_reg));
3345 match(RegP);
3346 match(rRegP);
3347
3348 format %{ %}
3349 interface(REG_INTER);
3350 %}
3351
3352 // Special Registers
3353 // Return a compressed pointer value
3354 operand rax_RegN()
3355 %{
3356 constraint(ALLOC_IN_RC(int_rax_reg));
3357 match(RegN);
3358 match(rRegN);
3359
3360 format %{ %}
3361 interface(REG_INTER);
3362 %}
3363
3364 // Used in AtomicAdd
3365 operand rbx_RegP()
3366 %{
3367 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3368 match(RegP);
3369 match(rRegP);
3370
3371 format %{ %}
3372 interface(REG_INTER);
3373 %}
3374
3375 operand rsi_RegP()
3376 %{
3377 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3378 match(RegP);
3379 match(rRegP);
3380
3381 format %{ %}
3382 interface(REG_INTER);
3383 %}
3384
3385 // Used in rep stosq
3386 operand rdi_RegP()
3387 %{
3388 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3389 match(RegP);
3390 match(rRegP);
3391
3392 format %{ %}
3393 interface(REG_INTER);
3394 %}
3395
3396 operand rbp_RegP()
3397 %{
3398 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3399 match(RegP);
3400 match(rRegP);
3401
3402 format %{ %}
3403 interface(REG_INTER);
3404 %}
3405
3406 operand r15_RegP()
3407 %{
3408 constraint(ALLOC_IN_RC(ptr_r15_reg));
3409 match(RegP);
3410 match(rRegP);
3411
3412 format %{ %}
3413 interface(REG_INTER);
3414 %}
3415
3416 operand rRegL()
3417 %{
3418 constraint(ALLOC_IN_RC(long_reg));
3419 match(RegL);
3420 match(rax_RegL);
3421 match(rdx_RegL);
3422
3423 format %{ %}
3424 interface(REG_INTER);
3425 %}
3426
3427 // Special Registers
3428 operand no_rax_rdx_RegL()
3429 %{
3430 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3431 match(RegL);
3432 match(rRegL);
3433
3434 format %{ %}
3435 interface(REG_INTER);
3436 %}
3437
3438 operand no_rax_RegL()
3439 %{
3440 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3441 match(RegL);
3442 match(rRegL);
3443 match(rdx_RegL);
3444
3445 format %{ %}
3446 interface(REG_INTER);
3447 %}
3448
3449 operand no_rcx_RegL()
3450 %{
3451 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3452 match(RegL);
3453 match(rRegL);
3454
3455 format %{ %}
3456 interface(REG_INTER);
3457 %}
3458
3459 operand rax_RegL()
3460 %{
3461 constraint(ALLOC_IN_RC(long_rax_reg));
3462 match(RegL);
3463 match(rRegL);
3464
3465 format %{ "RAX" %}
3466 interface(REG_INTER);
3467 %}
3468
3469 operand rcx_RegL()
3470 %{
3471 constraint(ALLOC_IN_RC(long_rcx_reg));
3472 match(RegL);
3473 match(rRegL);
3474
3475 format %{ %}
3476 interface(REG_INTER);
3477 %}
3478
3479 operand rdx_RegL()
3480 %{
3481 constraint(ALLOC_IN_RC(long_rdx_reg));
3482 match(RegL);
3483 match(rRegL);
3484
3485 format %{ %}
3486 interface(REG_INTER);
3487 %}
3488
3489 // Flags register, used as output of compare instructions
3490 operand rFlagsReg()
3491 %{
3492 constraint(ALLOC_IN_RC(int_flags));
3493 match(RegFlags);
3494
3495 format %{ "RFLAGS" %}
3496 interface(REG_INTER);
3497 %}
3498
3499 // Flags register, used as output of FLOATING POINT compare instructions
3500 operand rFlagsRegU()
3501 %{
3502 constraint(ALLOC_IN_RC(int_flags));
3503 match(RegFlags);
3504
3505 format %{ "RFLAGS_U" %}
3506 interface(REG_INTER);
3507 %}
3508
3509 operand rFlagsRegUCF() %{
3510 constraint(ALLOC_IN_RC(int_flags));
3511 match(RegFlags);
3512 predicate(false);
3513
3514 format %{ "RFLAGS_U_CF" %}
3515 interface(REG_INTER);
3516 %}
3517
3518 // Float register operands
3519 operand regF()
3520 %{
3521 constraint(ALLOC_IN_RC(float_reg));
3522 match(RegF);
3523
3524 format %{ %}
3525 interface(REG_INTER);
3526 %}
3527
3528 // Double register operands
3529 operand regD()
3530 %{
3531 constraint(ALLOC_IN_RC(double_reg));
3532 match(RegD);
3533
3534 format %{ %}
3535 interface(REG_INTER);
3536 %}
3537
3538 //----------Memory Operands----------------------------------------------------
3539 // Direct Memory Operand
3540 // operand direct(immP addr)
3541 // %{
3542 // match(addr);
3543
3544 // format %{ "[$addr]" %}
3545 // interface(MEMORY_INTER) %{
3546 // base(0xFFFFFFFF);
3547 // index(0x4);
3548 // scale(0x0);
3549 // disp($addr);
3550 // %}
3551 // %}
3552
3553 // Indirect Memory Operand
3554 operand indirect(any_RegP reg)
3555 %{
3556 constraint(ALLOC_IN_RC(ptr_reg));
3557 match(reg);
3558
3559 format %{ "[$reg]" %}
3560 interface(MEMORY_INTER) %{
3561 base($reg);
3562 index(0x4);
3563 scale(0x0);
3564 disp(0x0);
3565 %}
3566 %}
3567
3568 // Indirect Memory Plus Short Offset Operand
3569 operand indOffset8(any_RegP reg, immL8 off)
3570 %{
3571 constraint(ALLOC_IN_RC(ptr_reg));
3572 match(AddP reg off);
3573
3574 format %{ "[$reg + $off (8-bit)]" %}
3575 interface(MEMORY_INTER) %{
3576 base($reg);
3577 index(0x4);
3578 scale(0x0);
3579 disp($off);
3580 %}
3581 %}
3582
3583 // Indirect Memory Plus Long Offset Operand
3584 operand indOffset32(any_RegP reg, immL32 off)
3585 %{
3586 constraint(ALLOC_IN_RC(ptr_reg));
3587 match(AddP reg off);
3588
3589 format %{ "[$reg + $off (32-bit)]" %}
3590 interface(MEMORY_INTER) %{
3591 base($reg);
3592 index(0x4);
3593 scale(0x0);
3594 disp($off);
3595 %}
3596 %}
3597
3598 // Indirect Memory Plus Index Register Plus Offset Operand
3599 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3600 %{
3601 constraint(ALLOC_IN_RC(ptr_reg));
3602 match(AddP (AddP reg lreg) off);
3603
3604 op_cost(10);
3605 format %{"[$reg + $off + $lreg]" %}
3606 interface(MEMORY_INTER) %{
3607 base($reg);
3608 index($lreg);
3609 scale(0x0);
3610 disp($off);
3611 %}
3612 %}
3613
3614 // Indirect Memory Plus Index Register Plus Offset Operand
3615 operand indIndex(any_RegP reg, rRegL lreg)
3616 %{
3617 constraint(ALLOC_IN_RC(ptr_reg));
3618 match(AddP reg lreg);
3619
3620 op_cost(10);
3621 format %{"[$reg + $lreg]" %}
3622 interface(MEMORY_INTER) %{
3623 base($reg);
3624 index($lreg);
3625 scale(0x0);
3626 disp(0x0);
3627 %}
3628 %}
3629
3630 // Indirect Memory Times Scale Plus Index Register
3631 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3632 %{
3633 constraint(ALLOC_IN_RC(ptr_reg));
3634 match(AddP reg (LShiftL lreg scale));
3635
3636 op_cost(10);
3637 format %{"[$reg + $lreg << $scale]" %}
3638 interface(MEMORY_INTER) %{
3639 base($reg);
3640 index($lreg);
3641 scale($scale);
3642 disp(0x0);
3643 %}
3644 %}
3645
3646 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3647 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3648 %{
3649 constraint(ALLOC_IN_RC(ptr_reg));
3650 match(AddP (AddP reg (LShiftL lreg scale)) off);
3651
3652 op_cost(10);
3653 format %{"[$reg + $off + $lreg << $scale]" %}
3654 interface(MEMORY_INTER) %{
3655 base($reg);
3656 index($lreg);
3657 scale($scale);
3658 disp($off);
3659 %}
3660 %}
3661
3662 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3663 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3664 %{
3665 constraint(ALLOC_IN_RC(ptr_reg));
3666 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3667 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3668
3669 op_cost(10);
3670 format %{"[$reg + $off + $idx << $scale]" %}
3671 interface(MEMORY_INTER) %{
3672 base($reg);
3673 index($idx);
3674 scale($scale);
3675 disp($off);
3676 %}
3677 %}
3678
3679 // Indirect Narrow Oop Plus Offset Operand
3680 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3681 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3682 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3683 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3684 constraint(ALLOC_IN_RC(ptr_reg));
3685 match(AddP (DecodeN reg) off);
3686
3687 op_cost(10);
3688 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3689 interface(MEMORY_INTER) %{
3690 base(0xc); // R12
3691 index($reg);
3692 scale(0x3);
3693 disp($off);
3694 %}
3695 %}
3696
3697 // Indirect Memory Operand
3698 operand indirectNarrow(rRegN reg)
3699 %{
3700 predicate(Universe::narrow_oop_shift() == 0);
3701 constraint(ALLOC_IN_RC(ptr_reg));
3702 match(DecodeN reg);
3703
3704 format %{ "[$reg]" %}
3705 interface(MEMORY_INTER) %{
3706 base($reg);
3707 index(0x4);
3708 scale(0x0);
3709 disp(0x0);
3710 %}
3711 %}
3712
3713 // Indirect Memory Plus Short Offset Operand
3714 operand indOffset8Narrow(rRegN reg, immL8 off)
3715 %{
3716 predicate(Universe::narrow_oop_shift() == 0);
3717 constraint(ALLOC_IN_RC(ptr_reg));
3718 match(AddP (DecodeN reg) off);
3719
3720 format %{ "[$reg + $off (8-bit)]" %}
3721 interface(MEMORY_INTER) %{
3722 base($reg);
3723 index(0x4);
3724 scale(0x0);
3725 disp($off);
3726 %}
3727 %}
3728
3729 // Indirect Memory Plus Long Offset Operand
3730 operand indOffset32Narrow(rRegN reg, immL32 off)
3731 %{
3732 predicate(Universe::narrow_oop_shift() == 0);
3733 constraint(ALLOC_IN_RC(ptr_reg));
3734 match(AddP (DecodeN reg) off);
3735
3736 format %{ "[$reg + $off (32-bit)]" %}
3737 interface(MEMORY_INTER) %{
3738 base($reg);
3739 index(0x4);
3740 scale(0x0);
3741 disp($off);
3742 %}
3743 %}
3744
3745 // Indirect Memory Plus Index Register Plus Offset Operand
3746 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3747 %{
3748 predicate(Universe::narrow_oop_shift() == 0);
3749 constraint(ALLOC_IN_RC(ptr_reg));
3750 match(AddP (AddP (DecodeN reg) lreg) off);
3751
3752 op_cost(10);
3753 format %{"[$reg + $off + $lreg]" %}
3754 interface(MEMORY_INTER) %{
3755 base($reg);
3756 index($lreg);
3757 scale(0x0);
3758 disp($off);
3759 %}
3760 %}
3761
3762 // Indirect Memory Plus Index Register Plus Offset Operand
3763 operand indIndexNarrow(rRegN reg, rRegL lreg)
3764 %{
3765 predicate(Universe::narrow_oop_shift() == 0);
3766 constraint(ALLOC_IN_RC(ptr_reg));
3767 match(AddP (DecodeN reg) lreg);
3768
3769 op_cost(10);
3770 format %{"[$reg + $lreg]" %}
3771 interface(MEMORY_INTER) %{
3772 base($reg);
3773 index($lreg);
3774 scale(0x0);
3775 disp(0x0);
3776 %}
3777 %}
3778
3779 // Indirect Memory Times Scale Plus Index Register
3780 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3781 %{
3782 predicate(Universe::narrow_oop_shift() == 0);
3783 constraint(ALLOC_IN_RC(ptr_reg));
3784 match(AddP (DecodeN reg) (LShiftL lreg scale));
3785
3786 op_cost(10);
3787 format %{"[$reg + $lreg << $scale]" %}
3788 interface(MEMORY_INTER) %{
3789 base($reg);
3790 index($lreg);
3791 scale($scale);
3792 disp(0x0);
3793 %}
3794 %}
3795
3796 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3797 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3798 %{
3799 predicate(Universe::narrow_oop_shift() == 0);
3800 constraint(ALLOC_IN_RC(ptr_reg));
3801 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3802
3803 op_cost(10);
3804 format %{"[$reg + $off + $lreg << $scale]" %}
3805 interface(MEMORY_INTER) %{
3806 base($reg);
3807 index($lreg);
3808 scale($scale);
3809 disp($off);
3810 %}
3811 %}
3812
3813 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3814 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3815 %{
3816 constraint(ALLOC_IN_RC(ptr_reg));
3817 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3818 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3819
3820 op_cost(10);
3821 format %{"[$reg + $off + $idx << $scale]" %}
3822 interface(MEMORY_INTER) %{
3823 base($reg);
3824 index($idx);
3825 scale($scale);
3826 disp($off);
3827 %}
3828 %}
3829
3830 //----------Special Memory Operands--------------------------------------------
3831 // Stack Slot Operand - This operand is used for loading and storing temporary
3832 // values on the stack where a match requires a value to
3833 // flow through memory.
3834 operand stackSlotP(sRegP reg)
3835 %{
3836 constraint(ALLOC_IN_RC(stack_slots));
3837 // No match rule because this operand is only generated in matching
3838
3839 format %{ "[$reg]" %}
3840 interface(MEMORY_INTER) %{
3841 base(0x4); // RSP
3842 index(0x4); // No Index
3843 scale(0x0); // No Scale
3844 disp($reg); // Stack Offset
3845 %}
3846 %}
3847
3848 operand stackSlotI(sRegI reg)
3849 %{
3850 constraint(ALLOC_IN_RC(stack_slots));
3851 // No match rule because this operand is only generated in matching
3852
3853 format %{ "[$reg]" %}
3854 interface(MEMORY_INTER) %{
3855 base(0x4); // RSP
3856 index(0x4); // No Index
3857 scale(0x0); // No Scale
3858 disp($reg); // Stack Offset
3859 %}
3860 %}
3861
3862 operand stackSlotF(sRegF reg)
3863 %{
3864 constraint(ALLOC_IN_RC(stack_slots));
3865 // No match rule because this operand is only generated in matching
3866
3867 format %{ "[$reg]" %}
3868 interface(MEMORY_INTER) %{
3869 base(0x4); // RSP
3870 index(0x4); // No Index
3871 scale(0x0); // No Scale
3872 disp($reg); // Stack Offset
3873 %}
3874 %}
3875
3876 operand stackSlotD(sRegD reg)
3877 %{
3878 constraint(ALLOC_IN_RC(stack_slots));
3879 // No match rule because this operand is only generated in matching
3880
3881 format %{ "[$reg]" %}
3882 interface(MEMORY_INTER) %{
3883 base(0x4); // RSP
3884 index(0x4); // No Index
3885 scale(0x0); // No Scale
3886 disp($reg); // Stack Offset
3887 %}
3888 %}
3889 operand stackSlotL(sRegL reg)
3890 %{
3891 constraint(ALLOC_IN_RC(stack_slots));
3892 // No match rule because this operand is only generated in matching
3893
3894 format %{ "[$reg]" %}
3895 interface(MEMORY_INTER) %{
3896 base(0x4); // RSP
3897 index(0x4); // No Index
3898 scale(0x0); // No Scale
3899 disp($reg); // Stack Offset
3900 %}
3901 %}
3902
3903 //----------Conditional Branch Operands----------------------------------------
3904 // Comparison Op - This is the operation of the comparison, and is limited to
3905 // the following set of codes:
3906 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3907 //
3908 // Other attributes of the comparison, such as unsignedness, are specified
3909 // by the comparison instruction that sets a condition code flags register.
3910 // That result is represented by a flags operand whose subtype is appropriate
3911 // to the unsignedness (etc.) of the comparison.
3912 //
3913 // Later, the instruction which matches both the Comparison Op (a Bool) and
3914 // the flags (produced by the Cmp) specifies the coding of the comparison op
3915 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3916
3917 // Comparision Code
3918 operand cmpOp()
3919 %{
3920 match(Bool);
3921
3922 format %{ "" %}
3923 interface(COND_INTER) %{
3924 equal(0x4, "e");
3925 not_equal(0x5, "ne");
3926 less(0xC, "l");
3927 greater_equal(0xD, "ge");
3928 less_equal(0xE, "le");
3929 greater(0xF, "g");
3930 overflow(0x0, "o");
3931 no_overflow(0x1, "no");
3932 %}
3933 %}
3934
3935 // Comparison Code, unsigned compare. Used by FP also, with
3936 // C2 (unordered) turned into GT or LT already. The other bits
3937 // C0 and C3 are turned into Carry & Zero flags.
3938 operand cmpOpU()
3939 %{
3940 match(Bool);
3941
3942 format %{ "" %}
3943 interface(COND_INTER) %{
3944 equal(0x4, "e");
3945 not_equal(0x5, "ne");
3946 less(0x2, "b");
3947 greater_equal(0x3, "nb");
3948 less_equal(0x6, "be");
3949 greater(0x7, "nbe");
3950 overflow(0x0, "o");
3951 no_overflow(0x1, "no");
3952 %}
3953 %}
3954
3955
3956 // Floating comparisons that don't require any fixup for the unordered case
3957 operand cmpOpUCF() %{
3958 match(Bool);
3959 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3960 n->as_Bool()->_test._test == BoolTest::ge ||
3961 n->as_Bool()->_test._test == BoolTest::le ||
3962 n->as_Bool()->_test._test == BoolTest::gt);
3963 format %{ "" %}
3964 interface(COND_INTER) %{
3965 equal(0x4, "e");
3966 not_equal(0x5, "ne");
3967 less(0x2, "b");
3968 greater_equal(0x3, "nb");
3969 less_equal(0x6, "be");
3970 greater(0x7, "nbe");
3971 overflow(0x0, "o");
3972 no_overflow(0x1, "no");
3973 %}
3974 %}
3975
3976
3977 // Floating comparisons that can be fixed up with extra conditional jumps
3978 operand cmpOpUCF2() %{
3979 match(Bool);
3980 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3981 n->as_Bool()->_test._test == BoolTest::eq);
3982 format %{ "" %}
3983 interface(COND_INTER) %{
3984 equal(0x4, "e");
3985 not_equal(0x5, "ne");
3986 less(0x2, "b");
3987 greater_equal(0x3, "nb");
3988 less_equal(0x6, "be");
3989 greater(0x7, "nbe");
3990 overflow(0x0, "o");
3991 no_overflow(0x1, "no");
3992 %}
3993 %}
3994
3995
3996 //----------OPERAND CLASSES----------------------------------------------------
3997 // Operand Classes are groups of operands that are used as to simplify
3998 // instruction definitions by not requiring the AD writer to specify separate
3999 // instructions for every form of operand when the instruction accepts
4000 // multiple operand types with the same basic encoding and format. The classic
4001 // case of this is memory operands.
4002
4003 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4004 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
4005 indCompressedOopOffset,
4006 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4007 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4008 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
4009
4010 //----------PIPELINE-----------------------------------------------------------
4011 // Rules which define the behavior of the target architectures pipeline.
4012 pipeline %{
4013
4014 //----------ATTRIBUTES---------------------------------------------------------
4015 attributes %{
4016 variable_size_instructions; // Fixed size instructions
4017 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4018 instruction_unit_size = 1; // An instruction is 1 bytes long
4019 instruction_fetch_unit_size = 16; // The processor fetches one line
4020 instruction_fetch_units = 1; // of 16 bytes
4021
4022 // List of nop instructions
4023 nops( MachNop );
4024 %}
4025
4026 //----------RESOURCES----------------------------------------------------------
4027 // Resources are the functional units available to the machine
4028
4029 // Generic P2/P3 pipeline
4030 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4031 // 3 instructions decoded per cycle.
4032 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4033 // 3 ALU op, only ALU0 handles mul instructions.
4034 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4035 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4036 BR, FPU,
4037 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4038
4039 //----------PIPELINE DESCRIPTION-----------------------------------------------
4040 // Pipeline Description specifies the stages in the machine's pipeline
4041
4042 // Generic P2/P3 pipeline
4043 pipe_desc(S0, S1, S2, S3, S4, S5);
4044
4045 //----------PIPELINE CLASSES---------------------------------------------------
4046 // Pipeline Classes describe the stages in which input and output are
4047 // referenced by the hardware pipeline.
4048
4049 // Naming convention: ialu or fpu
4050 // Then: _reg
4051 // Then: _reg if there is a 2nd register
4052 // Then: _long if it's a pair of instructions implementing a long
4053 // Then: _fat if it requires the big decoder
4054 // Or: _mem if it requires the big decoder and a memory unit.
4055
4056 // Integer ALU reg operation
4057 pipe_class ialu_reg(rRegI dst)
4058 %{
4059 single_instruction;
4060 dst : S4(write);
4061 dst : S3(read);
4062 DECODE : S0; // any decoder
4063 ALU : S3; // any alu
4064 %}
4065
4066 // Long ALU reg operation
4067 pipe_class ialu_reg_long(rRegL dst)
4068 %{
4069 instruction_count(2);
4070 dst : S4(write);
4071 dst : S3(read);
4072 DECODE : S0(2); // any 2 decoders
4073 ALU : S3(2); // both alus
4074 %}
4075
4076 // Integer ALU reg operation using big decoder
4077 pipe_class ialu_reg_fat(rRegI dst)
4078 %{
4079 single_instruction;
4080 dst : S4(write);
4081 dst : S3(read);
4082 D0 : S0; // big decoder only
4083 ALU : S3; // any alu
4084 %}
4085
4086 // Long ALU reg operation using big decoder
4087 pipe_class ialu_reg_long_fat(rRegL dst)
4088 %{
4089 instruction_count(2);
4090 dst : S4(write);
4091 dst : S3(read);
4092 D0 : S0(2); // big decoder only; twice
4093 ALU : S3(2); // any 2 alus
4094 %}
4095
4096 // Integer ALU reg-reg operation
4097 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4098 %{
4099 single_instruction;
4100 dst : S4(write);
4101 src : S3(read);
4102 DECODE : S0; // any decoder
4103 ALU : S3; // any alu
4104 %}
4105
4106 // Long ALU reg-reg operation
4107 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4108 %{
4109 instruction_count(2);
4110 dst : S4(write);
4111 src : S3(read);
4112 DECODE : S0(2); // any 2 decoders
4113 ALU : S3(2); // both alus
4114 %}
4115
4116 // Integer ALU reg-reg operation
4117 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4118 %{
4119 single_instruction;
4120 dst : S4(write);
4121 src : S3(read);
4122 D0 : S0; // big decoder only
4123 ALU : S3; // any alu
4124 %}
4125
4126 // Long ALU reg-reg operation
4127 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4128 %{
4129 instruction_count(2);
4130 dst : S4(write);
4131 src : S3(read);
4132 D0 : S0(2); // big decoder only; twice
4133 ALU : S3(2); // both alus
4134 %}
4135
4136 // Integer ALU reg-mem operation
4137 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4138 %{
4139 single_instruction;
4140 dst : S5(write);
4141 mem : S3(read);
4142 D0 : S0; // big decoder only
4143 ALU : S4; // any alu
4144 MEM : S3; // any mem
4145 %}
4146
4147 // Integer mem operation (prefetch)
4148 pipe_class ialu_mem(memory mem)
4149 %{
4150 single_instruction;
4151 mem : S3(read);
4152 D0 : S0; // big decoder only
4153 MEM : S3; // any mem
4154 %}
4155
4156 // Integer Store to Memory
4157 pipe_class ialu_mem_reg(memory mem, rRegI src)
4158 %{
4159 single_instruction;
4160 mem : S3(read);
4161 src : S5(read);
4162 D0 : S0; // big decoder only
4163 ALU : S4; // any alu
4164 MEM : S3;
4165 %}
4166
4167 // // Long Store to Memory
4168 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4169 // %{
4170 // instruction_count(2);
4171 // mem : S3(read);
4172 // src : S5(read);
4173 // D0 : S0(2); // big decoder only; twice
4174 // ALU : S4(2); // any 2 alus
4175 // MEM : S3(2); // Both mems
4176 // %}
4177
4178 // Integer Store to Memory
4179 pipe_class ialu_mem_imm(memory mem)
4180 %{
4181 single_instruction;
4182 mem : S3(read);
4183 D0 : S0; // big decoder only
4184 ALU : S4; // any alu
4185 MEM : S3;
4186 %}
4187
4188 // Integer ALU0 reg-reg operation
4189 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4190 %{
4191 single_instruction;
4192 dst : S4(write);
4193 src : S3(read);
4194 D0 : S0; // Big decoder only
4195 ALU0 : S3; // only alu0
4196 %}
4197
4198 // Integer ALU0 reg-mem operation
4199 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4200 %{
4201 single_instruction;
4202 dst : S5(write);
4203 mem : S3(read);
4204 D0 : S0; // big decoder only
4205 ALU0 : S4; // ALU0 only
4206 MEM : S3; // any mem
4207 %}
4208
4209 // Integer ALU reg-reg operation
4210 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4211 %{
4212 single_instruction;
4213 cr : S4(write);
4214 src1 : S3(read);
4215 src2 : S3(read);
4216 DECODE : S0; // any decoder
4217 ALU : S3; // any alu
4218 %}
4219
4220 // Integer ALU reg-imm operation
4221 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4222 %{
4223 single_instruction;
4224 cr : S4(write);
4225 src1 : S3(read);
4226 DECODE : S0; // any decoder
4227 ALU : S3; // any alu
4228 %}
4229
4230 // Integer ALU reg-mem operation
4231 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4232 %{
4233 single_instruction;
4234 cr : S4(write);
4235 src1 : S3(read);
4236 src2 : S3(read);
4237 D0 : S0; // big decoder only
4238 ALU : S4; // any alu
4239 MEM : S3;
4240 %}
4241
4242 // Conditional move reg-reg
4243 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4244 %{
4245 instruction_count(4);
4246 y : S4(read);
4247 q : S3(read);
4248 p : S3(read);
4249 DECODE : S0(4); // any decoder
4250 %}
4251
4252 // Conditional move reg-reg
4253 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4254 %{
4255 single_instruction;
4256 dst : S4(write);
4257 src : S3(read);
4258 cr : S3(read);
4259 DECODE : S0; // any decoder
4260 %}
4261
4262 // Conditional move reg-mem
4263 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4264 %{
4265 single_instruction;
4266 dst : S4(write);
4267 src : S3(read);
4268 cr : S3(read);
4269 DECODE : S0; // any decoder
4270 MEM : S3;
4271 %}
4272
4273 // Conditional move reg-reg long
4274 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4275 %{
4276 single_instruction;
4277 dst : S4(write);
4278 src : S3(read);
4279 cr : S3(read);
4280 DECODE : S0(2); // any 2 decoders
4281 %}
4282
4283 // XXX
4284 // // Conditional move double reg-reg
4285 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4286 // %{
4287 // single_instruction;
4288 // dst : S4(write);
4289 // src : S3(read);
4290 // cr : S3(read);
4291 // DECODE : S0; // any decoder
4292 // %}
4293
4294 // Float reg-reg operation
4295 pipe_class fpu_reg(regD dst)
4296 %{
4297 instruction_count(2);
4298 dst : S3(read);
4299 DECODE : S0(2); // any 2 decoders
4300 FPU : S3;
4301 %}
4302
4303 // Float reg-reg operation
4304 pipe_class fpu_reg_reg(regD dst, regD src)
4305 %{
4306 instruction_count(2);
4307 dst : S4(write);
4308 src : S3(read);
4309 DECODE : S0(2); // any 2 decoders
4310 FPU : S3;
4311 %}
4312
4313 // Float reg-reg operation
4314 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4315 %{
4316 instruction_count(3);
4317 dst : S4(write);
4318 src1 : S3(read);
4319 src2 : S3(read);
4320 DECODE : S0(3); // any 3 decoders
4321 FPU : S3(2);
4322 %}
4323
4324 // Float reg-reg operation
4325 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4326 %{
4327 instruction_count(4);
4328 dst : S4(write);
4329 src1 : S3(read);
4330 src2 : S3(read);
4331 src3 : S3(read);
4332 DECODE : S0(4); // any 3 decoders
4333 FPU : S3(2);
4334 %}
4335
4336 // Float reg-reg operation
4337 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4338 %{
4339 instruction_count(4);
4340 dst : S4(write);
4341 src1 : S3(read);
4342 src2 : S3(read);
4343 src3 : S3(read);
4344 DECODE : S1(3); // any 3 decoders
4345 D0 : S0; // Big decoder only
4346 FPU : S3(2);
4347 MEM : S3;
4348 %}
4349
4350 // Float reg-mem operation
4351 pipe_class fpu_reg_mem(regD dst, memory mem)
4352 %{
4353 instruction_count(2);
4354 dst : S5(write);
4355 mem : S3(read);
4356 D0 : S0; // big decoder only
4357 DECODE : S1; // any decoder for FPU POP
4358 FPU : S4;
4359 MEM : S3; // any mem
4360 %}
4361
4362 // Float reg-mem operation
4363 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4364 %{
4365 instruction_count(3);
4366 dst : S5(write);
4367 src1 : S3(read);
4368 mem : S3(read);
4369 D0 : S0; // big decoder only
4370 DECODE : S1(2); // any decoder for FPU POP
4371 FPU : S4;
4372 MEM : S3; // any mem
4373 %}
4374
4375 // Float mem-reg operation
4376 pipe_class fpu_mem_reg(memory mem, regD src)
4377 %{
4378 instruction_count(2);
4379 src : S5(read);
4380 mem : S3(read);
4381 DECODE : S0; // any decoder for FPU PUSH
4382 D0 : S1; // big decoder only
4383 FPU : S4;
4384 MEM : S3; // any mem
4385 %}
4386
4387 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4388 %{
4389 instruction_count(3);
4390 src1 : S3(read);
4391 src2 : S3(read);
4392 mem : S3(read);
4393 DECODE : S0(2); // any decoder for FPU PUSH
4394 D0 : S1; // big decoder only
4395 FPU : S4;
4396 MEM : S3; // any mem
4397 %}
4398
4399 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4400 %{
4401 instruction_count(3);
4402 src1 : S3(read);
4403 src2 : S3(read);
4404 mem : S4(read);
4405 DECODE : S0; // any decoder for FPU PUSH
4406 D0 : S0(2); // big decoder only
4407 FPU : S4;
4408 MEM : S3(2); // any mem
4409 %}
4410
4411 pipe_class fpu_mem_mem(memory dst, memory src1)
4412 %{
4413 instruction_count(2);
4414 src1 : S3(read);
4415 dst : S4(read);
4416 D0 : S0(2); // big decoder only
4417 MEM : S3(2); // any mem
4418 %}
4419
4420 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4421 %{
4422 instruction_count(3);
4423 src1 : S3(read);
4424 src2 : S3(read);
4425 dst : S4(read);
4426 D0 : S0(3); // big decoder only
4427 FPU : S4;
4428 MEM : S3(3); // any mem
4429 %}
4430
4431 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4432 %{
4433 instruction_count(3);
4434 src1 : S4(read);
4435 mem : S4(read);
4436 DECODE : S0; // any decoder for FPU PUSH
4437 D0 : S0(2); // big decoder only
4438 FPU : S4;
4439 MEM : S3(2); // any mem
4440 %}
4441
4442 // Float load constant
4443 pipe_class fpu_reg_con(regD dst)
4444 %{
4445 instruction_count(2);
4446 dst : S5(write);
4447 D0 : S0; // big decoder only for the load
4448 DECODE : S1; // any decoder for FPU POP
4449 FPU : S4;
4450 MEM : S3; // any mem
4451 %}
4452
4453 // Float load constant
4454 pipe_class fpu_reg_reg_con(regD dst, regD src)
4455 %{
4456 instruction_count(3);
4457 dst : S5(write);
4458 src : S3(read);
4459 D0 : S0; // big decoder only for the load
4460 DECODE : S1(2); // any decoder for FPU POP
4461 FPU : S4;
4462 MEM : S3; // any mem
4463 %}
4464
4465 // UnConditional branch
4466 pipe_class pipe_jmp(label labl)
4467 %{
4468 single_instruction;
4469 BR : S3;
4470 %}
4471
4472 // Conditional branch
4473 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4474 %{
4475 single_instruction;
4476 cr : S1(read);
4477 BR : S3;
4478 %}
4479
4480 // Allocation idiom
4481 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4482 %{
4483 instruction_count(1); force_serialization;
4484 fixed_latency(6);
4485 heap_ptr : S3(read);
4486 DECODE : S0(3);
4487 D0 : S2;
4488 MEM : S3;
4489 ALU : S3(2);
4490 dst : S5(write);
4491 BR : S5;
4492 %}
4493
4494 // Generic big/slow expanded idiom
4495 pipe_class pipe_slow()
4496 %{
4497 instruction_count(10); multiple_bundles; force_serialization;
4498 fixed_latency(100);
4499 D0 : S0(2);
4500 MEM : S3(2);
4501 %}
4502
4503 // The real do-nothing guy
4504 pipe_class empty()
4505 %{
4506 instruction_count(0);
4507 %}
4508
4509 // Define the class for the Nop node
4510 define
4511 %{
4512 MachNop = empty;
4513 %}
4514
4515 %}
4516
4517 //----------INSTRUCTIONS-------------------------------------------------------
4518 //
4519 // match -- States which machine-independent subtree may be replaced
4520 // by this instruction.
4521 // ins_cost -- The estimated cost of this instruction is used by instruction
4522 // selection to identify a minimum cost tree of machine
4523 // instructions that matches a tree of machine-independent
4524 // instructions.
4525 // format -- A string providing the disassembly for this instruction.
4526 // The value of an instruction's operand may be inserted
4527 // by referring to it with a '$' prefix.
4528 // opcode -- Three instruction opcodes may be provided. These are referred
4529 // to within an encode class as $primary, $secondary, and $tertiary
4530 // rrspectively. The primary opcode is commonly used to
4531 // indicate the type of machine instruction, while secondary
4532 // and tertiary are often used for prefix options or addressing
4533 // modes.
4534 // ins_encode -- A list of encode classes with parameters. The encode class
4535 // name must have been defined in an 'enc_class' specification
4536 // in the encode section of the architecture description.
4537
4538
4539 //----------Load/Store/Move Instructions---------------------------------------
4540 //----------Load Instructions--------------------------------------------------
4541
4542 // Load Byte (8 bit signed)
4543 instruct loadB(rRegI dst, memory mem)
4544 %{
4545 match(Set dst (LoadB mem));
4546
4547 ins_cost(125);
4548 format %{ "movsbl $dst, $mem\t# byte" %}
4549
4550 ins_encode %{
4551 __ movsbl($dst$$Register, $mem$$Address);
4552 %}
4553
4554 ins_pipe(ialu_reg_mem);
4555 %}
4556
4557 // Load Byte (8 bit signed) into Long Register
4558 instruct loadB2L(rRegL dst, memory mem)
4559 %{
4560 match(Set dst (ConvI2L (LoadB mem)));
4561
4562 ins_cost(125);
4563 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4564
4565 ins_encode %{
4566 __ movsbq($dst$$Register, $mem$$Address);
4567 %}
4568
4569 ins_pipe(ialu_reg_mem);
4570 %}
4571
4572 // Load Unsigned Byte (8 bit UNsigned)
4573 instruct loadUB(rRegI dst, memory mem)
4574 %{
4575 match(Set dst (LoadUB mem));
4576
4577 ins_cost(125);
4578 format %{ "movzbl $dst, $mem\t# ubyte" %}
4579
4580 ins_encode %{
4581 __ movzbl($dst$$Register, $mem$$Address);
4582 %}
4583
4584 ins_pipe(ialu_reg_mem);
4585 %}
4586
4587 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4588 instruct loadUB2L(rRegL dst, memory mem)
4589 %{
4590 match(Set dst (ConvI2L (LoadUB mem)));
4591
4592 ins_cost(125);
4593 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4594
4595 ins_encode %{
4596 __ movzbq($dst$$Register, $mem$$Address);
4597 %}
4598
4599 ins_pipe(ialu_reg_mem);
4600 %}
4601
4602 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
4603 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
4604 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4605 effect(KILL cr);
4606
4607 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
4608 "andl $dst, $mask" %}
4609 ins_encode %{
4610 Register Rdst = $dst$$Register;
4611 __ movzbq(Rdst, $mem$$Address);
4612 __ andl(Rdst, $mask$$constant);
4613 %}
4614 ins_pipe(ialu_reg_mem);
4615 %}
4616
4617 // Load Short (16 bit signed)
4618 instruct loadS(rRegI dst, memory mem)
4619 %{
4620 match(Set dst (LoadS mem));
4621
4622 ins_cost(125);
4623 format %{ "movswl $dst, $mem\t# short" %}
4624
4625 ins_encode %{
4626 __ movswl($dst$$Register, $mem$$Address);
4627 %}
4628
4629 ins_pipe(ialu_reg_mem);
4630 %}
4631
4632 // Load Short (16 bit signed) to Byte (8 bit signed)
4633 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4634 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4635
4636 ins_cost(125);
4637 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4638 ins_encode %{
4639 __ movsbl($dst$$Register, $mem$$Address);
4640 %}
4641 ins_pipe(ialu_reg_mem);
4642 %}
4643
4644 // Load Short (16 bit signed) into Long Register
4645 instruct loadS2L(rRegL dst, memory mem)
4646 %{
4647 match(Set dst (ConvI2L (LoadS mem)));
4648
4649 ins_cost(125);
4650 format %{ "movswq $dst, $mem\t# short -> long" %}
4651
4652 ins_encode %{
4653 __ movswq($dst$$Register, $mem$$Address);
4654 %}
4655
4656 ins_pipe(ialu_reg_mem);
4657 %}
4658
4659 // Load Unsigned Short/Char (16 bit UNsigned)
4660 instruct loadUS(rRegI dst, memory mem)
4661 %{
4662 match(Set dst (LoadUS mem));
4663
4664 ins_cost(125);
4665 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4666
4667 ins_encode %{
4668 __ movzwl($dst$$Register, $mem$$Address);
4669 %}
4670
4671 ins_pipe(ialu_reg_mem);
4672 %}
4673
4674 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4675 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4676 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4677
4678 ins_cost(125);
4679 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4680 ins_encode %{
4681 __ movsbl($dst$$Register, $mem$$Address);
4682 %}
4683 ins_pipe(ialu_reg_mem);
4684 %}
4685
4686 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4687 instruct loadUS2L(rRegL dst, memory mem)
4688 %{
4689 match(Set dst (ConvI2L (LoadUS mem)));
4690
4691 ins_cost(125);
4692 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4693
4694 ins_encode %{
4695 __ movzwq($dst$$Register, $mem$$Address);
4696 %}
4697
4698 ins_pipe(ialu_reg_mem);
4699 %}
4700
4701 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4702 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4703 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4704
4705 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4706 ins_encode %{
4707 __ movzbq($dst$$Register, $mem$$Address);
4708 %}
4709 ins_pipe(ialu_reg_mem);
4710 %}
4711
4712 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
4713 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
4714 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4715 effect(KILL cr);
4716
4717 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
4718 "andl $dst, $mask" %}
4719 ins_encode %{
4720 Register Rdst = $dst$$Register;
4721 __ movzwq(Rdst, $mem$$Address);
4722 __ andl(Rdst, $mask$$constant);
4723 %}
4724 ins_pipe(ialu_reg_mem);
4725 %}
4726
4727 // Load Integer
4728 instruct loadI(rRegI dst, memory mem)
4729 %{
4730 match(Set dst (LoadI mem));
4731
4732 ins_cost(125);
4733 format %{ "movl $dst, $mem\t# int" %}
4734
4735 ins_encode %{
4736 __ movl($dst$$Register, $mem$$Address);
4737 %}
4738
4739 ins_pipe(ialu_reg_mem);
4740 %}
4741
4742 // Load Integer (32 bit signed) to Byte (8 bit signed)
4743 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4744 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4745
4746 ins_cost(125);
4747 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4748 ins_encode %{
4749 __ movsbl($dst$$Register, $mem$$Address);
4750 %}
4751 ins_pipe(ialu_reg_mem);
4752 %}
4753
4754 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4755 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4756 match(Set dst (AndI (LoadI mem) mask));
4757
4758 ins_cost(125);
4759 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4760 ins_encode %{
4761 __ movzbl($dst$$Register, $mem$$Address);
4762 %}
4763 ins_pipe(ialu_reg_mem);
4764 %}
4765
4766 // Load Integer (32 bit signed) to Short (16 bit signed)
4767 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4768 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4769
4770 ins_cost(125);
4771 format %{ "movswl $dst, $mem\t# int -> short" %}
4772 ins_encode %{
4773 __ movswl($dst$$Register, $mem$$Address);
4774 %}
4775 ins_pipe(ialu_reg_mem);
4776 %}
4777
4778 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4779 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4780 match(Set dst (AndI (LoadI mem) mask));
4781
4782 ins_cost(125);
4783 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4784 ins_encode %{
4785 __ movzwl($dst$$Register, $mem$$Address);
4786 %}
4787 ins_pipe(ialu_reg_mem);
4788 %}
4789
4790 // Load Integer into Long Register
4791 instruct loadI2L(rRegL dst, memory mem)
4792 %{
4793 match(Set dst (ConvI2L (LoadI mem)));
4794
4795 ins_cost(125);
4796 format %{ "movslq $dst, $mem\t# int -> long" %}
4797
4798 ins_encode %{
4799 __ movslq($dst$$Register, $mem$$Address);
4800 %}
4801
4802 ins_pipe(ialu_reg_mem);
4803 %}
4804
4805 // Load Integer with mask 0xFF into Long Register
4806 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4807 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4808
4809 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4810 ins_encode %{
4811 __ movzbq($dst$$Register, $mem$$Address);
4812 %}
4813 ins_pipe(ialu_reg_mem);
4814 %}
4815
4816 // Load Integer with mask 0xFFFF into Long Register
4817 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4818 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4819
4820 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4821 ins_encode %{
4822 __ movzwq($dst$$Register, $mem$$Address);
4823 %}
4824 ins_pipe(ialu_reg_mem);
4825 %}
4826
4827 // Load Integer with a 31-bit mask into Long Register
4828 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
4829 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4830 effect(KILL cr);
4831
4832 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
4833 "andl $dst, $mask" %}
4834 ins_encode %{
4835 Register Rdst = $dst$$Register;
4836 __ movl(Rdst, $mem$$Address);
4837 __ andl(Rdst, $mask$$constant);
4838 %}
4839 ins_pipe(ialu_reg_mem);
4840 %}
4841
4842 // Load Unsigned Integer into Long Register
4843 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
4844 %{
4845 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4846
4847 ins_cost(125);
4848 format %{ "movl $dst, $mem\t# uint -> long" %}
4849
4850 ins_encode %{
4851 __ movl($dst$$Register, $mem$$Address);
4852 %}
4853
4854 ins_pipe(ialu_reg_mem);
4855 %}
4856
4857 // Load Long
4858 instruct loadL(rRegL dst, memory mem)
4859 %{
4860 match(Set dst (LoadL mem));
4861
4862 ins_cost(125);
4863 format %{ "movq $dst, $mem\t# long" %}
4864
4865 ins_encode %{
4866 __ movq($dst$$Register, $mem$$Address);
4867 %}
4868
4869 ins_pipe(ialu_reg_mem); // XXX
4870 %}
4871
4872 // Load Range
4873 instruct loadRange(rRegI dst, memory mem)
4874 %{
4875 match(Set dst (LoadRange mem));
4876
4877 ins_cost(125); // XXX
4878 format %{ "movl $dst, $mem\t# range" %}
4879 opcode(0x8B);
4880 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
4881 ins_pipe(ialu_reg_mem);
4882 %}
4883
4884 // Load Pointer
4885 instruct loadP(rRegP dst, memory mem)
4886 %{
4887 match(Set dst (LoadP mem));
4888
4889 ins_cost(125); // XXX
4890 format %{ "movq $dst, $mem\t# ptr" %}
4891 opcode(0x8B);
4892 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4893 ins_pipe(ialu_reg_mem); // XXX
4894 %}
4895
4896 // Load Compressed Pointer
4897 instruct loadN(rRegN dst, memory mem)
4898 %{
4899 match(Set dst (LoadN mem));
4900
4901 ins_cost(125); // XXX
4902 format %{ "movl $dst, $mem\t# compressed ptr" %}
4903 ins_encode %{
4904 __ movl($dst$$Register, $mem$$Address);
4905 %}
4906 ins_pipe(ialu_reg_mem); // XXX
4907 %}
4908
4909
4910 // Load Klass Pointer
4911 instruct loadKlass(rRegP dst, memory mem)
4912 %{
4913 match(Set dst (LoadKlass mem));
4914
4915 ins_cost(125); // XXX
4916 format %{ "movq $dst, $mem\t# class" %}
4917 opcode(0x8B);
4918 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4919 ins_pipe(ialu_reg_mem); // XXX
4920 %}
4921
4922 // Load narrow Klass Pointer
4923 instruct loadNKlass(rRegN dst, memory mem)
4924 %{
4925 match(Set dst (LoadNKlass mem));
4926
4927 ins_cost(125); // XXX
4928 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
4929 ins_encode %{
4930 __ movl($dst$$Register, $mem$$Address);
4931 %}
4932 ins_pipe(ialu_reg_mem); // XXX
4933 %}
4934
4935 // Load Float
4936 instruct loadF(regF dst, memory mem)
4937 %{
4938 match(Set dst (LoadF mem));
4939
4940 ins_cost(145); // XXX
4941 format %{ "movss $dst, $mem\t# float" %}
4942 ins_encode %{
4943 __ movflt($dst$$XMMRegister, $mem$$Address);
4944 %}
4945 ins_pipe(pipe_slow); // XXX
4946 %}
4947
4948 // Load Double
4949 instruct loadD_partial(regD dst, memory mem)
4950 %{
4951 predicate(!UseXmmLoadAndClearUpper);
4952 match(Set dst (LoadD mem));
4953
4954 ins_cost(145); // XXX
4955 format %{ "movlpd $dst, $mem\t# double" %}
4956 ins_encode %{
4957 __ movdbl($dst$$XMMRegister, $mem$$Address);
4958 %}
4959 ins_pipe(pipe_slow); // XXX
4960 %}
4961
4962 instruct loadD(regD dst, memory mem)
4963 %{
4964 predicate(UseXmmLoadAndClearUpper);
4965 match(Set dst (LoadD mem));
4966
4967 ins_cost(145); // XXX
4968 format %{ "movsd $dst, $mem\t# double" %}
4969 ins_encode %{
4970 __ movdbl($dst$$XMMRegister, $mem$$Address);
4971 %}
4972 ins_pipe(pipe_slow); // XXX
4973 %}
4974
4975 // Load Effective Address
4976 instruct leaP8(rRegP dst, indOffset8 mem)
4977 %{
4978 match(Set dst mem);
4979
4980 ins_cost(110); // XXX
4981 format %{ "leaq $dst, $mem\t# ptr 8" %}
4982 opcode(0x8D);
4983 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4984 ins_pipe(ialu_reg_reg_fat);
4985 %}
4986
4987 instruct leaP32(rRegP dst, indOffset32 mem)
4988 %{
4989 match(Set dst mem);
4990
4991 ins_cost(110);
4992 format %{ "leaq $dst, $mem\t# ptr 32" %}
4993 opcode(0x8D);
4994 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4995 ins_pipe(ialu_reg_reg_fat);
4996 %}
4997
4998 // instruct leaPIdx(rRegP dst, indIndex mem)
4999 // %{
5000 // match(Set dst mem);
5001
5002 // ins_cost(110);
5003 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5004 // opcode(0x8D);
5005 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5006 // ins_pipe(ialu_reg_reg_fat);
5007 // %}
5008
5009 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5010 %{
5011 match(Set dst mem);
5012
5013 ins_cost(110);
5014 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5015 opcode(0x8D);
5016 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5017 ins_pipe(ialu_reg_reg_fat);
5018 %}
5019
5020 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5021 %{
5022 match(Set dst mem);
5023
5024 ins_cost(110);
5025 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5026 opcode(0x8D);
5027 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5028 ins_pipe(ialu_reg_reg_fat);
5029 %}
5030
5031 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5032 %{
5033 match(Set dst mem);
5034
5035 ins_cost(110);
5036 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5037 opcode(0x8D);
5038 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5039 ins_pipe(ialu_reg_reg_fat);
5040 %}
5041
5042 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5043 %{
5044 match(Set dst mem);
5045
5046 ins_cost(110);
5047 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5048 opcode(0x8D);
5049 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5050 ins_pipe(ialu_reg_reg_fat);
5051 %}
5052
5053 // Load Effective Address which uses Narrow (32-bits) oop
5054 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5055 %{
5056 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5057 match(Set dst mem);
5058
5059 ins_cost(110);
5060 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5061 opcode(0x8D);
5062 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5063 ins_pipe(ialu_reg_reg_fat);
5064 %}
5065
5066 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5067 %{
5068 predicate(Universe::narrow_oop_shift() == 0);
5069 match(Set dst mem);
5070
5071 ins_cost(110); // XXX
5072 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5073 opcode(0x8D);
5074 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5075 ins_pipe(ialu_reg_reg_fat);
5076 %}
5077
5078 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5079 %{
5080 predicate(Universe::narrow_oop_shift() == 0);
5081 match(Set dst mem);
5082
5083 ins_cost(110);
5084 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5085 opcode(0x8D);
5086 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5087 ins_pipe(ialu_reg_reg_fat);
5088 %}
5089
5090 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5091 %{
5092 predicate(Universe::narrow_oop_shift() == 0);
5093 match(Set dst mem);
5094
5095 ins_cost(110);
5096 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5097 opcode(0x8D);
5098 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5099 ins_pipe(ialu_reg_reg_fat);
5100 %}
5101
5102 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5103 %{
5104 predicate(Universe::narrow_oop_shift() == 0);
5105 match(Set dst mem);
5106
5107 ins_cost(110);
5108 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5109 opcode(0x8D);
5110 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5111 ins_pipe(ialu_reg_reg_fat);
5112 %}
5113
5114 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5115 %{
5116 predicate(Universe::narrow_oop_shift() == 0);
5117 match(Set dst mem);
5118
5119 ins_cost(110);
5120 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5121 opcode(0x8D);
5122 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5123 ins_pipe(ialu_reg_reg_fat);
5124 %}
5125
5126 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5127 %{
5128 predicate(Universe::narrow_oop_shift() == 0);
5129 match(Set dst mem);
5130
5131 ins_cost(110);
5132 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5133 opcode(0x8D);
5134 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5135 ins_pipe(ialu_reg_reg_fat);
5136 %}
5137
5138 instruct loadConI(rRegI dst, immI src)
5139 %{
5140 match(Set dst src);
5141
5142 format %{ "movl $dst, $src\t# int" %}
5143 ins_encode(load_immI(dst, src));
5144 ins_pipe(ialu_reg_fat); // XXX
5145 %}
5146
5147 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5148 %{
5149 match(Set dst src);
5150 effect(KILL cr);
5151
5152 ins_cost(50);
5153 format %{ "xorl $dst, $dst\t# int" %}
5154 opcode(0x33); /* + rd */
5155 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5156 ins_pipe(ialu_reg);
5157 %}
5158
5159 instruct loadConL(rRegL dst, immL src)
5160 %{
5161 match(Set dst src);
5162
5163 ins_cost(150);
5164 format %{ "movq $dst, $src\t# long" %}
5165 ins_encode(load_immL(dst, src));
5166 ins_pipe(ialu_reg);
5167 %}
5168
5169 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5170 %{
5171 match(Set dst src);
5172 effect(KILL cr);
5173
5174 ins_cost(50);
5175 format %{ "xorl $dst, $dst\t# long" %}
5176 opcode(0x33); /* + rd */
5177 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5178 ins_pipe(ialu_reg); // XXX
5179 %}
5180
5181 instruct loadConUL32(rRegL dst, immUL32 src)
5182 %{
5183 match(Set dst src);
5184
5185 ins_cost(60);
5186 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5187 ins_encode(load_immUL32(dst, src));
5188 ins_pipe(ialu_reg);
5189 %}
5190
5191 instruct loadConL32(rRegL dst, immL32 src)
5192 %{
5193 match(Set dst src);
5194
5195 ins_cost(70);
5196 format %{ "movq $dst, $src\t# long (32-bit)" %}
5197 ins_encode(load_immL32(dst, src));
5198 ins_pipe(ialu_reg);
5199 %}
5200
5201 instruct loadConP(rRegP dst, immP con) %{
5202 match(Set dst con);
5203
5204 format %{ "movq $dst, $con\t# ptr" %}
5205 ins_encode(load_immP(dst, con));
5206 ins_pipe(ialu_reg_fat); // XXX
5207 %}
5208
5209 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5210 %{
5211 match(Set dst src);
5212 effect(KILL cr);
5213
5214 ins_cost(50);
5215 format %{ "xorl $dst, $dst\t# ptr" %}
5216 opcode(0x33); /* + rd */
5217 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5218 ins_pipe(ialu_reg);
5219 %}
5220
5221 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5222 %{
5223 match(Set dst src);
5224 effect(KILL cr);
5225
5226 ins_cost(60);
5227 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5228 ins_encode(load_immP31(dst, src));
5229 ins_pipe(ialu_reg);
5230 %}
5231
5232 instruct loadConF(regF dst, immF con) %{
5233 match(Set dst con);
5234 ins_cost(125);
5235 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5236 ins_encode %{
5237 __ movflt($dst$$XMMRegister, $constantaddress($con));
5238 %}
5239 ins_pipe(pipe_slow);
5240 %}
5241
5242 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5243 match(Set dst src);
5244 effect(KILL cr);
5245 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5246 ins_encode %{
5247 __ xorq($dst$$Register, $dst$$Register);
5248 %}
5249 ins_pipe(ialu_reg);
5250 %}
5251
5252 instruct loadConN(rRegN dst, immN src) %{
5253 match(Set dst src);
5254
5255 ins_cost(125);
5256 format %{ "movl $dst, $src\t# compressed ptr" %}
5257 ins_encode %{
5258 address con = (address)$src$$constant;
5259 if (con == NULL) {
5260 ShouldNotReachHere();
5261 } else {
5262 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5263 }
5264 %}
5265 ins_pipe(ialu_reg_fat); // XXX
5266 %}
5267
5268 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5269 match(Set dst src);
5270
5271 ins_cost(125);
5272 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5273 ins_encode %{
5274 address con = (address)$src$$constant;
5275 if (con == NULL) {
5276 ShouldNotReachHere();
5277 } else {
5278 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5279 }
5280 %}
5281 ins_pipe(ialu_reg_fat); // XXX
5282 %}
5283
5284 instruct loadConF0(regF dst, immF0 src)
5285 %{
5286 match(Set dst src);
5287 ins_cost(100);
5288
5289 format %{ "xorps $dst, $dst\t# float 0.0" %}
5290 ins_encode %{
5291 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5292 %}
5293 ins_pipe(pipe_slow);
5294 %}
5295
5296 // Use the same format since predicate() can not be used here.
5297 instruct loadConD(regD dst, immD con) %{
5298 match(Set dst con);
5299 ins_cost(125);
5300 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5301 ins_encode %{
5302 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5303 %}
5304 ins_pipe(pipe_slow);
5305 %}
5306
5307 instruct loadConD0(regD dst, immD0 src)
5308 %{
5309 match(Set dst src);
5310 ins_cost(100);
5311
5312 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5313 ins_encode %{
5314 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5315 %}
5316 ins_pipe(pipe_slow);
5317 %}
5318
5319 instruct loadSSI(rRegI dst, stackSlotI src)
5320 %{
5321 match(Set dst src);
5322
5323 ins_cost(125);
5324 format %{ "movl $dst, $src\t# int stk" %}
5325 opcode(0x8B);
5326 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5327 ins_pipe(ialu_reg_mem);
5328 %}
5329
5330 instruct loadSSL(rRegL dst, stackSlotL src)
5331 %{
5332 match(Set dst src);
5333
5334 ins_cost(125);
5335 format %{ "movq $dst, $src\t# long stk" %}
5336 opcode(0x8B);
5337 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5338 ins_pipe(ialu_reg_mem);
5339 %}
5340
5341 instruct loadSSP(rRegP dst, stackSlotP src)
5342 %{
5343 match(Set dst src);
5344
5345 ins_cost(125);
5346 format %{ "movq $dst, $src\t# ptr stk" %}
5347 opcode(0x8B);
5348 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5349 ins_pipe(ialu_reg_mem);
5350 %}
5351
5352 instruct loadSSF(regF dst, stackSlotF src)
5353 %{
5354 match(Set dst src);
5355
5356 ins_cost(125);
5357 format %{ "movss $dst, $src\t# float stk" %}
5358 ins_encode %{
5359 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5360 %}
5361 ins_pipe(pipe_slow); // XXX
5362 %}
5363
5364 // Use the same format since predicate() can not be used here.
5365 instruct loadSSD(regD dst, stackSlotD src)
5366 %{
5367 match(Set dst src);
5368
5369 ins_cost(125);
5370 format %{ "movsd $dst, $src\t# double stk" %}
5371 ins_encode %{
5372 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5373 %}
5374 ins_pipe(pipe_slow); // XXX
5375 %}
5376
5377 // Prefetch instructions.
5378 // Must be safe to execute with invalid address (cannot fault).
5379
5380 instruct prefetchr( memory mem ) %{
5381 predicate(ReadPrefetchInstr==3);
5382 match(PrefetchRead mem);
5383 ins_cost(125);
5384
5385 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
5386 ins_encode %{
5387 __ prefetchr($mem$$Address);
5388 %}
5389 ins_pipe(ialu_mem);
5390 %}
5391
5392 instruct prefetchrNTA( memory mem ) %{
5393 predicate(ReadPrefetchInstr==0);
5394 match(PrefetchRead mem);
5395 ins_cost(125);
5396
5397 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
5398 ins_encode %{
5399 __ prefetchnta($mem$$Address);
5400 %}
5401 ins_pipe(ialu_mem);
5402 %}
5403
5404 instruct prefetchrT0( memory mem ) %{
5405 predicate(ReadPrefetchInstr==1);
5406 match(PrefetchRead mem);
5407 ins_cost(125);
5408
5409 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
5410 ins_encode %{
5411 __ prefetcht0($mem$$Address);
5412 %}
5413 ins_pipe(ialu_mem);
5414 %}
5415
5416 instruct prefetchrT2( memory mem ) %{
5417 predicate(ReadPrefetchInstr==2);
5418 match(PrefetchRead mem);
5419 ins_cost(125);
5420
5421 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
5422 ins_encode %{
5423 __ prefetcht2($mem$$Address);
5424 %}
5425 ins_pipe(ialu_mem);
5426 %}
5427
5428 instruct prefetchwNTA( memory mem ) %{
5429 match(PrefetchWrite mem);
5430 ins_cost(125);
5431
5432 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
5433 ins_encode %{
5434 __ prefetchnta($mem$$Address);
5435 %}
5436 ins_pipe(ialu_mem);
5437 %}
5438
5439 // Prefetch instructions for allocation.
5440
5441 instruct prefetchAlloc( memory mem ) %{
5442 predicate(AllocatePrefetchInstr==3);
5443 match(PrefetchAllocation mem);
5444 ins_cost(125);
5445
5446 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5447 ins_encode %{
5448 __ prefetchw($mem$$Address);
5449 %}
5450 ins_pipe(ialu_mem);
5451 %}
5452
5453 instruct prefetchAllocNTA( memory mem ) %{
5454 predicate(AllocatePrefetchInstr==0);
5455 match(PrefetchAllocation mem);
5456 ins_cost(125);
5457
5458 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5459 ins_encode %{
5460 __ prefetchnta($mem$$Address);
5461 %}
5462 ins_pipe(ialu_mem);
5463 %}
5464
5465 instruct prefetchAllocT0( memory mem ) %{
5466 predicate(AllocatePrefetchInstr==1);
5467 match(PrefetchAllocation mem);
5468 ins_cost(125);
5469
5470 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5471 ins_encode %{
5472 __ prefetcht0($mem$$Address);
5473 %}
5474 ins_pipe(ialu_mem);
5475 %}
5476
5477 instruct prefetchAllocT2( memory mem ) %{
5478 predicate(AllocatePrefetchInstr==2);
5479 match(PrefetchAllocation mem);
5480 ins_cost(125);
5481
5482 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5483 ins_encode %{
5484 __ prefetcht2($mem$$Address);
5485 %}
5486 ins_pipe(ialu_mem);
5487 %}
5488
5489 //----------Store Instructions-------------------------------------------------
5490
5491 // Store Byte
5492 instruct storeB(memory mem, rRegI src)
5493 %{
5494 match(Set mem (StoreB mem src));
5495
5496 ins_cost(125); // XXX
5497 format %{ "movb $mem, $src\t# byte" %}
5498 opcode(0x88);
5499 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5500 ins_pipe(ialu_mem_reg);
5501 %}
5502
5503 // Store Char/Short
5504 instruct storeC(memory mem, rRegI src)
5505 %{
5506 match(Set mem (StoreC mem src));
5507
5508 ins_cost(125); // XXX
5509 format %{ "movw $mem, $src\t# char/short" %}
5510 opcode(0x89);
5511 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5512 ins_pipe(ialu_mem_reg);
5513 %}
5514
5515 // Store Integer
5516 instruct storeI(memory mem, rRegI src)
5517 %{
5518 match(Set mem (StoreI mem src));
5519
5520 ins_cost(125); // XXX
5521 format %{ "movl $mem, $src\t# int" %}
5522 opcode(0x89);
5523 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5524 ins_pipe(ialu_mem_reg);
5525 %}
5526
5527 // Store Long
5528 instruct storeL(memory mem, rRegL src)
5529 %{
5530 match(Set mem (StoreL mem src));
5531
5532 ins_cost(125); // XXX
5533 format %{ "movq $mem, $src\t# long" %}
5534 opcode(0x89);
5535 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5536 ins_pipe(ialu_mem_reg); // XXX
5537 %}
5538
5539 // Store Pointer
5540 instruct storeP(memory mem, any_RegP src)
5541 %{
5542 match(Set mem (StoreP mem src));
5543
5544 ins_cost(125); // XXX
5545 format %{ "movq $mem, $src\t# ptr" %}
5546 opcode(0x89);
5547 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5548 ins_pipe(ialu_mem_reg);
5549 %}
5550
5551 instruct storeImmP0(memory mem, immP0 zero)
5552 %{
5553 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5554 match(Set mem (StoreP mem zero));
5555
5556 ins_cost(125); // XXX
5557 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5558 ins_encode %{
5559 __ movq($mem$$Address, r12);
5560 %}
5561 ins_pipe(ialu_mem_reg);
5562 %}
5563
5564 // Store NULL Pointer, mark word, or other simple pointer constant.
5565 instruct storeImmP(memory mem, immP31 src)
5566 %{
5567 match(Set mem (StoreP mem src));
5568
5569 ins_cost(150); // XXX
5570 format %{ "movq $mem, $src\t# ptr" %}
5571 opcode(0xC7); /* C7 /0 */
5572 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5573 ins_pipe(ialu_mem_imm);
5574 %}
5575
5576 // Store Compressed Pointer
5577 instruct storeN(memory mem, rRegN src)
5578 %{
5579 match(Set mem (StoreN mem src));
5580
5581 ins_cost(125); // XXX
5582 format %{ "movl $mem, $src\t# compressed ptr" %}
5583 ins_encode %{
5584 __ movl($mem$$Address, $src$$Register);
5585 %}
5586 ins_pipe(ialu_mem_reg);
5587 %}
5588
5589 instruct storeNKlass(memory mem, rRegN src)
5590 %{
5591 match(Set mem (StoreNKlass mem src));
5592
5593 ins_cost(125); // XXX
5594 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5595 ins_encode %{
5596 __ movl($mem$$Address, $src$$Register);
5597 %}
5598 ins_pipe(ialu_mem_reg);
5599 %}
5600
5601 instruct storeImmN0(memory mem, immN0 zero)
5602 %{
5603 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5604 match(Set mem (StoreN mem zero));
5605
5606 ins_cost(125); // XXX
5607 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5608 ins_encode %{
5609 __ movl($mem$$Address, r12);
5610 %}
5611 ins_pipe(ialu_mem_reg);
5612 %}
5613
5614 instruct storeImmN(memory mem, immN src)
5615 %{
5616 match(Set mem (StoreN mem src));
5617
5618 ins_cost(150); // XXX
5619 format %{ "movl $mem, $src\t# compressed ptr" %}
5620 ins_encode %{
5621 address con = (address)$src$$constant;
5622 if (con == NULL) {
5623 __ movl($mem$$Address, (int32_t)0);
5624 } else {
5625 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5626 }
5627 %}
5628 ins_pipe(ialu_mem_imm);
5629 %}
5630
5631 instruct storeImmNKlass(memory mem, immNKlass src)
5632 %{
5633 match(Set mem (StoreNKlass mem src));
5634
5635 ins_cost(150); // XXX
5636 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5637 ins_encode %{
5638 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5639 %}
5640 ins_pipe(ialu_mem_imm);
5641 %}
5642
5643 // Store Integer Immediate
5644 instruct storeImmI0(memory mem, immI0 zero)
5645 %{
5646 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5647 match(Set mem (StoreI mem zero));
5648
5649 ins_cost(125); // XXX
5650 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5651 ins_encode %{
5652 __ movl($mem$$Address, r12);
5653 %}
5654 ins_pipe(ialu_mem_reg);
5655 %}
5656
5657 instruct storeImmI(memory mem, immI src)
5658 %{
5659 match(Set mem (StoreI mem src));
5660
5661 ins_cost(150);
5662 format %{ "movl $mem, $src\t# int" %}
5663 opcode(0xC7); /* C7 /0 */
5664 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5665 ins_pipe(ialu_mem_imm);
5666 %}
5667
5668 // Store Long Immediate
5669 instruct storeImmL0(memory mem, immL0 zero)
5670 %{
5671 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5672 match(Set mem (StoreL mem zero));
5673
5674 ins_cost(125); // XXX
5675 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5676 ins_encode %{
5677 __ movq($mem$$Address, r12);
5678 %}
5679 ins_pipe(ialu_mem_reg);
5680 %}
5681
5682 instruct storeImmL(memory mem, immL32 src)
5683 %{
5684 match(Set mem (StoreL mem src));
5685
5686 ins_cost(150);
5687 format %{ "movq $mem, $src\t# long" %}
5688 opcode(0xC7); /* C7 /0 */
5689 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5690 ins_pipe(ialu_mem_imm);
5691 %}
5692
5693 // Store Short/Char Immediate
5694 instruct storeImmC0(memory mem, immI0 zero)
5695 %{
5696 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5697 match(Set mem (StoreC mem zero));
5698
5699 ins_cost(125); // XXX
5700 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5701 ins_encode %{
5702 __ movw($mem$$Address, r12);
5703 %}
5704 ins_pipe(ialu_mem_reg);
5705 %}
5706
5707 instruct storeImmI16(memory mem, immI16 src)
5708 %{
5709 predicate(UseStoreImmI16);
5710 match(Set mem (StoreC mem src));
5711
5712 ins_cost(150);
5713 format %{ "movw $mem, $src\t# short/char" %}
5714 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5715 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5716 ins_pipe(ialu_mem_imm);
5717 %}
5718
5719 // Store Byte Immediate
5720 instruct storeImmB0(memory mem, immI0 zero)
5721 %{
5722 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5723 match(Set mem (StoreB mem zero));
5724
5725 ins_cost(125); // XXX
5726 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5727 ins_encode %{
5728 __ movb($mem$$Address, r12);
5729 %}
5730 ins_pipe(ialu_mem_reg);
5731 %}
5732
5733 instruct storeImmB(memory mem, immI8 src)
5734 %{
5735 match(Set mem (StoreB mem src));
5736
5737 ins_cost(150); // XXX
5738 format %{ "movb $mem, $src\t# byte" %}
5739 opcode(0xC6); /* C6 /0 */
5740 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5741 ins_pipe(ialu_mem_imm);
5742 %}
5743
5744 // Store CMS card-mark Immediate
5745 instruct storeImmCM0_reg(memory mem, immI0 zero)
5746 %{
5747 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5748 match(Set mem (StoreCM mem zero));
5749
5750 ins_cost(125); // XXX
5751 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5752 ins_encode %{
5753 __ movb($mem$$Address, r12);
5754 %}
5755 ins_pipe(ialu_mem_reg);
5756 %}
5757
5758 instruct storeImmCM0(memory mem, immI0 src)
5759 %{
5760 match(Set mem (StoreCM mem src));
5761
5762 ins_cost(150); // XXX
5763 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5764 opcode(0xC6); /* C6 /0 */
5765 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5766 ins_pipe(ialu_mem_imm);
5767 %}
5768
5769 // Store Float
5770 instruct storeF(memory mem, regF src)
5771 %{
5772 match(Set mem (StoreF mem src));
5773
5774 ins_cost(95); // XXX
5775 format %{ "movss $mem, $src\t# float" %}
5776 ins_encode %{
5777 __ movflt($mem$$Address, $src$$XMMRegister);
5778 %}
5779 ins_pipe(pipe_slow); // XXX
5780 %}
5781
5782 // Store immediate Float value (it is faster than store from XMM register)
5783 instruct storeF0(memory mem, immF0 zero)
5784 %{
5785 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5786 match(Set mem (StoreF mem zero));
5787
5788 ins_cost(25); // XXX
5789 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5790 ins_encode %{
5791 __ movl($mem$$Address, r12);
5792 %}
5793 ins_pipe(ialu_mem_reg);
5794 %}
5795
5796 instruct storeF_imm(memory mem, immF src)
5797 %{
5798 match(Set mem (StoreF mem src));
5799
5800 ins_cost(50);
5801 format %{ "movl $mem, $src\t# float" %}
5802 opcode(0xC7); /* C7 /0 */
5803 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5804 ins_pipe(ialu_mem_imm);
5805 %}
5806
5807 // Store Double
5808 instruct storeD(memory mem, regD src)
5809 %{
5810 match(Set mem (StoreD mem src));
5811
5812 ins_cost(95); // XXX
5813 format %{ "movsd $mem, $src\t# double" %}
5814 ins_encode %{
5815 __ movdbl($mem$$Address, $src$$XMMRegister);
5816 %}
5817 ins_pipe(pipe_slow); // XXX
5818 %}
5819
5820 // Store immediate double 0.0 (it is faster than store from XMM register)
5821 instruct storeD0_imm(memory mem, immD0 src)
5822 %{
5823 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
5824 match(Set mem (StoreD mem src));
5825
5826 ins_cost(50);
5827 format %{ "movq $mem, $src\t# double 0." %}
5828 opcode(0xC7); /* C7 /0 */
5829 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5830 ins_pipe(ialu_mem_imm);
5831 %}
5832
5833 instruct storeD0(memory mem, immD0 zero)
5834 %{
5835 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5836 match(Set mem (StoreD mem zero));
5837
5838 ins_cost(25); // XXX
5839 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5840 ins_encode %{
5841 __ movq($mem$$Address, r12);
5842 %}
5843 ins_pipe(ialu_mem_reg);
5844 %}
5845
5846 instruct storeSSI(stackSlotI dst, rRegI src)
5847 %{
5848 match(Set dst src);
5849
5850 ins_cost(100);
5851 format %{ "movl $dst, $src\t# int stk" %}
5852 opcode(0x89);
5853 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
5854 ins_pipe( ialu_mem_reg );
5855 %}
5856
5857 instruct storeSSL(stackSlotL dst, rRegL src)
5858 %{
5859 match(Set dst src);
5860
5861 ins_cost(100);
5862 format %{ "movq $dst, $src\t# long stk" %}
5863 opcode(0x89);
5864 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
5865 ins_pipe(ialu_mem_reg);
5866 %}
5867
5868 instruct storeSSP(stackSlotP dst, rRegP src)
5869 %{
5870 match(Set dst src);
5871
5872 ins_cost(100);
5873 format %{ "movq $dst, $src\t# ptr stk" %}
5874 opcode(0x89);
5875 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
5876 ins_pipe(ialu_mem_reg);
5877 %}
5878
5879 instruct storeSSF(stackSlotF dst, regF src)
5880 %{
5881 match(Set dst src);
5882
5883 ins_cost(95); // XXX
5884 format %{ "movss $dst, $src\t# float stk" %}
5885 ins_encode %{
5886 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
5887 %}
5888 ins_pipe(pipe_slow); // XXX
5889 %}
5890
5891 instruct storeSSD(stackSlotD dst, regD src)
5892 %{
5893 match(Set dst src);
5894
5895 ins_cost(95); // XXX
5896 format %{ "movsd $dst, $src\t# double stk" %}
5897 ins_encode %{
5898 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
5899 %}
5900 ins_pipe(pipe_slow); // XXX
5901 %}
5902
5903 //----------BSWAP Instructions-------------------------------------------------
5904 instruct bytes_reverse_int(rRegI dst) %{
5905 match(Set dst (ReverseBytesI dst));
5906
5907 format %{ "bswapl $dst" %}
5908 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
5909 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
5910 ins_pipe( ialu_reg );
5911 %}
5912
5913 instruct bytes_reverse_long(rRegL dst) %{
5914 match(Set dst (ReverseBytesL dst));
5915
5916 format %{ "bswapq $dst" %}
5917 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
5918 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
5919 ins_pipe( ialu_reg);
5920 %}
5921
5922 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
5923 match(Set dst (ReverseBytesUS dst));
5924 effect(KILL cr);
5925
5926 format %{ "bswapl $dst\n\t"
5927 "shrl $dst,16\n\t" %}
5928 ins_encode %{
5929 __ bswapl($dst$$Register);
5930 __ shrl($dst$$Register, 16);
5931 %}
5932 ins_pipe( ialu_reg );
5933 %}
5934
5935 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
5936 match(Set dst (ReverseBytesS dst));
5937 effect(KILL cr);
5938
5939 format %{ "bswapl $dst\n\t"
5940 "sar $dst,16\n\t" %}
5941 ins_encode %{
5942 __ bswapl($dst$$Register);
5943 __ sarl($dst$$Register, 16);
5944 %}
5945 ins_pipe( ialu_reg );
5946 %}
5947
5948 //---------- Zeros Count Instructions ------------------------------------------
5949
5950 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5951 predicate(UseCountLeadingZerosInstruction);
5952 match(Set dst (CountLeadingZerosI src));
5953 effect(KILL cr);
5954
5955 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5956 ins_encode %{
5957 __ lzcntl($dst$$Register, $src$$Register);
5958 %}
5959 ins_pipe(ialu_reg);
5960 %}
5961
5962 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
5963 predicate(!UseCountLeadingZerosInstruction);
5964 match(Set dst (CountLeadingZerosI src));
5965 effect(KILL cr);
5966
5967 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
5968 "jnz skip\n\t"
5969 "movl $dst, -1\n"
5970 "skip:\n\t"
5971 "negl $dst\n\t"
5972 "addl $dst, 31" %}
5973 ins_encode %{
5974 Register Rdst = $dst$$Register;
5975 Register Rsrc = $src$$Register;
5976 Label skip;
5977 __ bsrl(Rdst, Rsrc);
5978 __ jccb(Assembler::notZero, skip);
5979 __ movl(Rdst, -1);
5980 __ bind(skip);
5981 __ negl(Rdst);
5982 __ addl(Rdst, BitsPerInt - 1);
5983 %}
5984 ins_pipe(ialu_reg);
5985 %}
5986
5987 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5988 predicate(UseCountLeadingZerosInstruction);
5989 match(Set dst (CountLeadingZerosL src));
5990 effect(KILL cr);
5991
5992 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5993 ins_encode %{
5994 __ lzcntq($dst$$Register, $src$$Register);
5995 %}
5996 ins_pipe(ialu_reg);
5997 %}
5998
5999 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6000 predicate(!UseCountLeadingZerosInstruction);
6001 match(Set dst (CountLeadingZerosL src));
6002 effect(KILL cr);
6003
6004 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6005 "jnz skip\n\t"
6006 "movl $dst, -1\n"
6007 "skip:\n\t"
6008 "negl $dst\n\t"
6009 "addl $dst, 63" %}
6010 ins_encode %{
6011 Register Rdst = $dst$$Register;
6012 Register Rsrc = $src$$Register;
6013 Label skip;
6014 __ bsrq(Rdst, Rsrc);
6015 __ jccb(Assembler::notZero, skip);
6016 __ movl(Rdst, -1);
6017 __ bind(skip);
6018 __ negl(Rdst);
6019 __ addl(Rdst, BitsPerLong - 1);
6020 %}
6021 ins_pipe(ialu_reg);
6022 %}
6023
6024 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6025 match(Set dst (CountTrailingZerosI src));
6026 effect(KILL cr);
6027
6028 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6029 "jnz done\n\t"
6030 "movl $dst, 32\n"
6031 "done:" %}
6032 ins_encode %{
6033 Register Rdst = $dst$$Register;
6034 Label done;
6035 __ bsfl(Rdst, $src$$Register);
6036 __ jccb(Assembler::notZero, done);
6037 __ movl(Rdst, BitsPerInt);
6038 __ bind(done);
6039 %}
6040 ins_pipe(ialu_reg);
6041 %}
6042
6043 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6044 match(Set dst (CountTrailingZerosL src));
6045 effect(KILL cr);
6046
6047 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6048 "jnz done\n\t"
6049 "movl $dst, 64\n"
6050 "done:" %}
6051 ins_encode %{
6052 Register Rdst = $dst$$Register;
6053 Label done;
6054 __ bsfq(Rdst, $src$$Register);
6055 __ jccb(Assembler::notZero, done);
6056 __ movl(Rdst, BitsPerLong);
6057 __ bind(done);
6058 %}
6059 ins_pipe(ialu_reg);
6060 %}
6061
6062
6063 //---------- Population Count Instructions -------------------------------------
6064
6065 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6066 predicate(UsePopCountInstruction);
6067 match(Set dst (PopCountI src));
6068 effect(KILL cr);
6069
6070 format %{ "popcnt $dst, $src" %}
6071 ins_encode %{
6072 __ popcntl($dst$$Register, $src$$Register);
6073 %}
6074 ins_pipe(ialu_reg);
6075 %}
6076
6077 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6078 predicate(UsePopCountInstruction);
6079 match(Set dst (PopCountI (LoadI mem)));
6080 effect(KILL cr);
6081
6082 format %{ "popcnt $dst, $mem" %}
6083 ins_encode %{
6084 __ popcntl($dst$$Register, $mem$$Address);
6085 %}
6086 ins_pipe(ialu_reg);
6087 %}
6088
6089 // Note: Long.bitCount(long) returns an int.
6090 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6091 predicate(UsePopCountInstruction);
6092 match(Set dst (PopCountL src));
6093 effect(KILL cr);
6094
6095 format %{ "popcnt $dst, $src" %}
6096 ins_encode %{
6097 __ popcntq($dst$$Register, $src$$Register);
6098 %}
6099 ins_pipe(ialu_reg);
6100 %}
6101
6102 // Note: Long.bitCount(long) returns an int.
6103 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6104 predicate(UsePopCountInstruction);
6105 match(Set dst (PopCountL (LoadL mem)));
6106 effect(KILL cr);
6107
6108 format %{ "popcnt $dst, $mem" %}
6109 ins_encode %{
6110 __ popcntq($dst$$Register, $mem$$Address);
6111 %}
6112 ins_pipe(ialu_reg);
6113 %}
6114
6115
6116 //----------MemBar Instructions-----------------------------------------------
6117 // Memory barrier flavors
6118
6119 instruct membar_acquire()
6120 %{
6121 match(MemBarAcquire);
6122 match(LoadFence);
6123 ins_cost(0);
6124
6125 size(0);
6126 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6127 ins_encode();
6128 ins_pipe(empty);
6129 %}
6130
6131 instruct membar_acquire_lock()
6132 %{
6133 match(MemBarAcquireLock);
6134 ins_cost(0);
6135
6136 size(0);
6137 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6138 ins_encode();
6139 ins_pipe(empty);
6140 %}
6141
6142 instruct membar_release()
6143 %{
6144 match(MemBarRelease);
6145 match(StoreFence);
6146 ins_cost(0);
6147
6148 size(0);
6149 format %{ "MEMBAR-release ! (empty encoding)" %}
6150 ins_encode();
6151 ins_pipe(empty);
6152 %}
6153
6154 instruct membar_release_lock()
6155 %{
6156 match(MemBarReleaseLock);
6157 ins_cost(0);
6158
6159 size(0);
6160 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6161 ins_encode();
6162 ins_pipe(empty);
6163 %}
6164
6165 instruct membar_volatile(rFlagsReg cr) %{
6166 match(MemBarVolatile);
6167 effect(KILL cr);
6168 ins_cost(400);
6169
6170 format %{
6171 $$template
6172 if (os::is_MP()) {
6173 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6174 } else {
6175 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6176 }
6177 %}
6178 ins_encode %{
6179 __ membar(Assembler::StoreLoad);
6180 %}
6181 ins_pipe(pipe_slow);
6182 %}
6183
6184 instruct unnecessary_membar_volatile()
6185 %{
6186 match(MemBarVolatile);
6187 predicate(Matcher::post_store_load_barrier(n));
6188 ins_cost(0);
6189
6190 size(0);
6191 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6192 ins_encode();
6193 ins_pipe(empty);
6194 %}
6195
6196 instruct membar_storestore() %{
6197 match(MemBarStoreStore);
6198 ins_cost(0);
6199
6200 size(0);
6201 format %{ "MEMBAR-storestore (empty encoding)" %}
6202 ins_encode( );
6203 ins_pipe(empty);
6204 %}
6205
6206 //----------Move Instructions--------------------------------------------------
6207
6208 instruct castX2P(rRegP dst, rRegL src)
6209 %{
6210 match(Set dst (CastX2P src));
6211
6212 format %{ "movq $dst, $src\t# long->ptr" %}
6213 ins_encode %{
6214 if ($dst$$reg != $src$$reg) {
6215 __ movptr($dst$$Register, $src$$Register);
6216 }
6217 %}
6218 ins_pipe(ialu_reg_reg); // XXX
6219 %}
6220
6221 instruct castP2X(rRegL dst, rRegP src)
6222 %{
6223 match(Set dst (CastP2X src));
6224
6225 format %{ "movq $dst, $src\t# ptr -> long" %}
6226 ins_encode %{
6227 if ($dst$$reg != $src$$reg) {
6228 __ movptr($dst$$Register, $src$$Register);
6229 }
6230 %}
6231 ins_pipe(ialu_reg_reg); // XXX
6232 %}
6233
6234 // Convert oop into int for vectors alignment masking
6235 instruct convP2I(rRegI dst, rRegP src)
6236 %{
6237 match(Set dst (ConvL2I (CastP2X src)));
6238
6239 format %{ "movl $dst, $src\t# ptr -> int" %}
6240 ins_encode %{
6241 __ movl($dst$$Register, $src$$Register);
6242 %}
6243 ins_pipe(ialu_reg_reg); // XXX
6244 %}
6245
6246 // Convert compressed oop into int for vectors alignment masking
6247 // in case of 32bit oops (heap < 4Gb).
6248 instruct convN2I(rRegI dst, rRegN src)
6249 %{
6250 predicate(Universe::narrow_oop_shift() == 0);
6251 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6252
6253 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6254 ins_encode %{
6255 __ movl($dst$$Register, $src$$Register);
6256 %}
6257 ins_pipe(ialu_reg_reg); // XXX
6258 %}
6259
6260 // Convert oop pointer into compressed form
6261 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6262 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6263 match(Set dst (EncodeP src));
6264 effect(KILL cr);
6265 format %{ "encode_heap_oop $dst,$src" %}
6266 ins_encode %{
6267 Register s = $src$$Register;
6268 Register d = $dst$$Register;
6269 if (s != d) {
6270 __ movq(d, s);
6271 }
6272 __ encode_heap_oop(d);
6273 %}
6274 ins_pipe(ialu_reg_long);
6275 %}
6276
6277 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6278 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6279 match(Set dst (EncodeP src));
6280 effect(KILL cr);
6281 format %{ "encode_heap_oop_not_null $dst,$src" %}
6282 ins_encode %{
6283 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6284 %}
6285 ins_pipe(ialu_reg_long);
6286 %}
6287
6288 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6289 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6290 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6291 match(Set dst (DecodeN src));
6292 effect(KILL cr);
6293 format %{ "decode_heap_oop $dst,$src" %}
6294 ins_encode %{
6295 Register s = $src$$Register;
6296 Register d = $dst$$Register;
6297 if (s != d) {
6298 __ movq(d, s);
6299 }
6300 __ decode_heap_oop(d);
6301 %}
6302 ins_pipe(ialu_reg_long);
6303 %}
6304
6305 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6306 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6307 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6308 match(Set dst (DecodeN src));
6309 effect(KILL cr);
6310 format %{ "decode_heap_oop_not_null $dst,$src" %}
6311 ins_encode %{
6312 Register s = $src$$Register;
6313 Register d = $dst$$Register;
6314 if (s != d) {
6315 __ decode_heap_oop_not_null(d, s);
6316 } else {
6317 __ decode_heap_oop_not_null(d);
6318 }
6319 %}
6320 ins_pipe(ialu_reg_long);
6321 %}
6322
6323 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6324 match(Set dst (EncodePKlass src));
6325 effect(KILL cr);
6326 format %{ "encode_klass_not_null $dst,$src" %}
6327 ins_encode %{
6328 __ encode_klass_not_null($dst$$Register, $src$$Register);
6329 %}
6330 ins_pipe(ialu_reg_long);
6331 %}
6332
6333 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6334 match(Set dst (DecodeNKlass src));
6335 effect(KILL cr);
6336 format %{ "decode_klass_not_null $dst,$src" %}
6337 ins_encode %{
6338 Register s = $src$$Register;
6339 Register d = $dst$$Register;
6340 if (s != d) {
6341 __ decode_klass_not_null(d, s);
6342 } else {
6343 __ decode_klass_not_null(d);
6344 }
6345 %}
6346 ins_pipe(ialu_reg_long);
6347 %}
6348
6349
6350 //----------Conditional Move---------------------------------------------------
6351 // Jump
6352 // dummy instruction for generating temp registers
6353 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6354 match(Jump (LShiftL switch_val shift));
6355 ins_cost(350);
6356 predicate(false);
6357 effect(TEMP dest);
6358
6359 format %{ "leaq $dest, [$constantaddress]\n\t"
6360 "jmp [$dest + $switch_val << $shift]\n\t" %}
6361 ins_encode %{
6362 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6363 // to do that and the compiler is using that register as one it can allocate.
6364 // So we build it all by hand.
6365 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6366 // ArrayAddress dispatch(table, index);
6367 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6368 __ lea($dest$$Register, $constantaddress);
6369 __ jmp(dispatch);
6370 %}
6371 ins_pipe(pipe_jmp);
6372 %}
6373
6374 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6375 match(Jump (AddL (LShiftL switch_val shift) offset));
6376 ins_cost(350);
6377 effect(TEMP dest);
6378
6379 format %{ "leaq $dest, [$constantaddress]\n\t"
6380 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6381 ins_encode %{
6382 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6383 // to do that and the compiler is using that register as one it can allocate.
6384 // So we build it all by hand.
6385 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6386 // ArrayAddress dispatch(table, index);
6387 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6388 __ lea($dest$$Register, $constantaddress);
6389 __ jmp(dispatch);
6390 %}
6391 ins_pipe(pipe_jmp);
6392 %}
6393
6394 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6395 match(Jump switch_val);
6396 ins_cost(350);
6397 effect(TEMP dest);
6398
6399 format %{ "leaq $dest, [$constantaddress]\n\t"
6400 "jmp [$dest + $switch_val]\n\t" %}
6401 ins_encode %{
6402 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6403 // to do that and the compiler is using that register as one it can allocate.
6404 // So we build it all by hand.
6405 // Address index(noreg, switch_reg, Address::times_1);
6406 // ArrayAddress dispatch(table, index);
6407 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6408 __ lea($dest$$Register, $constantaddress);
6409 __ jmp(dispatch);
6410 %}
6411 ins_pipe(pipe_jmp);
6412 %}
6413
6414 // Conditional move
6415 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6416 %{
6417 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6418
6419 ins_cost(200); // XXX
6420 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6421 opcode(0x0F, 0x40);
6422 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6423 ins_pipe(pipe_cmov_reg);
6424 %}
6425
6426 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6427 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6428
6429 ins_cost(200); // XXX
6430 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6431 opcode(0x0F, 0x40);
6432 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6433 ins_pipe(pipe_cmov_reg);
6434 %}
6435
6436 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6437 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6438 ins_cost(200);
6439 expand %{
6440 cmovI_regU(cop, cr, dst, src);
6441 %}
6442 %}
6443
6444 // Conditional move
6445 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6446 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6447
6448 ins_cost(250); // XXX
6449 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6450 opcode(0x0F, 0x40);
6451 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6452 ins_pipe(pipe_cmov_mem);
6453 %}
6454
6455 // Conditional move
6456 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6457 %{
6458 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6459
6460 ins_cost(250); // XXX
6461 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6462 opcode(0x0F, 0x40);
6463 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6464 ins_pipe(pipe_cmov_mem);
6465 %}
6466
6467 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6468 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6469 ins_cost(250);
6470 expand %{
6471 cmovI_memU(cop, cr, dst, src);
6472 %}
6473 %}
6474
6475 // Conditional move
6476 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6477 %{
6478 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6479
6480 ins_cost(200); // XXX
6481 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6482 opcode(0x0F, 0x40);
6483 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6484 ins_pipe(pipe_cmov_reg);
6485 %}
6486
6487 // Conditional move
6488 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6489 %{
6490 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6491
6492 ins_cost(200); // XXX
6493 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6494 opcode(0x0F, 0x40);
6495 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6496 ins_pipe(pipe_cmov_reg);
6497 %}
6498
6499 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6500 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6501 ins_cost(200);
6502 expand %{
6503 cmovN_regU(cop, cr, dst, src);
6504 %}
6505 %}
6506
6507 // Conditional move
6508 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6509 %{
6510 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6511
6512 ins_cost(200); // XXX
6513 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6514 opcode(0x0F, 0x40);
6515 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6516 ins_pipe(pipe_cmov_reg); // XXX
6517 %}
6518
6519 // Conditional move
6520 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6521 %{
6522 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6523
6524 ins_cost(200); // XXX
6525 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6526 opcode(0x0F, 0x40);
6527 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6528 ins_pipe(pipe_cmov_reg); // XXX
6529 %}
6530
6531 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6532 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6533 ins_cost(200);
6534 expand %{
6535 cmovP_regU(cop, cr, dst, src);
6536 %}
6537 %}
6538
6539 // DISABLED: Requires the ADLC to emit a bottom_type call that
6540 // correctly meets the two pointer arguments; one is an incoming
6541 // register but the other is a memory operand. ALSO appears to
6542 // be buggy with implicit null checks.
6543 //
6544 //// Conditional move
6545 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6546 //%{
6547 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6548 // ins_cost(250);
6549 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6550 // opcode(0x0F,0x40);
6551 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6552 // ins_pipe( pipe_cmov_mem );
6553 //%}
6554 //
6555 //// Conditional move
6556 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6557 //%{
6558 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6559 // ins_cost(250);
6560 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6561 // opcode(0x0F,0x40);
6562 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6563 // ins_pipe( pipe_cmov_mem );
6564 //%}
6565
6566 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6567 %{
6568 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6569
6570 ins_cost(200); // XXX
6571 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6572 opcode(0x0F, 0x40);
6573 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6574 ins_pipe(pipe_cmov_reg); // XXX
6575 %}
6576
6577 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6578 %{
6579 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6580
6581 ins_cost(200); // XXX
6582 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6583 opcode(0x0F, 0x40);
6584 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6585 ins_pipe(pipe_cmov_mem); // XXX
6586 %}
6587
6588 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6589 %{
6590 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6591
6592 ins_cost(200); // XXX
6593 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6594 opcode(0x0F, 0x40);
6595 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6596 ins_pipe(pipe_cmov_reg); // XXX
6597 %}
6598
6599 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6600 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6601 ins_cost(200);
6602 expand %{
6603 cmovL_regU(cop, cr, dst, src);
6604 %}
6605 %}
6606
6607 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6608 %{
6609 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6610
6611 ins_cost(200); // XXX
6612 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6613 opcode(0x0F, 0x40);
6614 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6615 ins_pipe(pipe_cmov_mem); // XXX
6616 %}
6617
6618 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6619 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6620 ins_cost(200);
6621 expand %{
6622 cmovL_memU(cop, cr, dst, src);
6623 %}
6624 %}
6625
6626 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6627 %{
6628 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6629
6630 ins_cost(200); // XXX
6631 format %{ "jn$cop skip\t# signed cmove float\n\t"
6632 "movss $dst, $src\n"
6633 "skip:" %}
6634 ins_encode %{
6635 Label Lskip;
6636 // Invert sense of branch from sense of CMOV
6637 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6638 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6639 __ bind(Lskip);
6640 %}
6641 ins_pipe(pipe_slow);
6642 %}
6643
6644 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6645 // %{
6646 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6647
6648 // ins_cost(200); // XXX
6649 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6650 // "movss $dst, $src\n"
6651 // "skip:" %}
6652 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6653 // ins_pipe(pipe_slow);
6654 // %}
6655
6656 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6657 %{
6658 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6659
6660 ins_cost(200); // XXX
6661 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6662 "movss $dst, $src\n"
6663 "skip:" %}
6664 ins_encode %{
6665 Label Lskip;
6666 // Invert sense of branch from sense of CMOV
6667 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6668 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6669 __ bind(Lskip);
6670 %}
6671 ins_pipe(pipe_slow);
6672 %}
6673
6674 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6675 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6676 ins_cost(200);
6677 expand %{
6678 cmovF_regU(cop, cr, dst, src);
6679 %}
6680 %}
6681
6682 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6683 %{
6684 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6685
6686 ins_cost(200); // XXX
6687 format %{ "jn$cop skip\t# signed cmove double\n\t"
6688 "movsd $dst, $src\n"
6689 "skip:" %}
6690 ins_encode %{
6691 Label Lskip;
6692 // Invert sense of branch from sense of CMOV
6693 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6694 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6695 __ bind(Lskip);
6696 %}
6697 ins_pipe(pipe_slow);
6698 %}
6699
6700 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6701 %{
6702 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6703
6704 ins_cost(200); // XXX
6705 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6706 "movsd $dst, $src\n"
6707 "skip:" %}
6708 ins_encode %{
6709 Label Lskip;
6710 // Invert sense of branch from sense of CMOV
6711 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6712 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6713 __ bind(Lskip);
6714 %}
6715 ins_pipe(pipe_slow);
6716 %}
6717
6718 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6719 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6720 ins_cost(200);
6721 expand %{
6722 cmovD_regU(cop, cr, dst, src);
6723 %}
6724 %}
6725
6726 //----------Arithmetic Instructions--------------------------------------------
6727 //----------Addition Instructions----------------------------------------------
6728
6729 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6730 %{
6731 match(Set dst (AddI dst src));
6732 effect(KILL cr);
6733
6734 format %{ "addl $dst, $src\t# int" %}
6735 opcode(0x03);
6736 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6737 ins_pipe(ialu_reg_reg);
6738 %}
6739
6740 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6741 %{
6742 match(Set dst (AddI dst src));
6743 effect(KILL cr);
6744
6745 format %{ "addl $dst, $src\t# int" %}
6746 opcode(0x81, 0x00); /* /0 id */
6747 ins_encode(OpcSErm(dst, src), Con8or32(src));
6748 ins_pipe( ialu_reg );
6749 %}
6750
6751 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6752 %{
6753 match(Set dst (AddI dst (LoadI src)));
6754 effect(KILL cr);
6755
6756 ins_cost(125); // XXX
6757 format %{ "addl $dst, $src\t# int" %}
6758 opcode(0x03);
6759 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6760 ins_pipe(ialu_reg_mem);
6761 %}
6762
6763 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6764 %{
6765 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6766 effect(KILL cr);
6767
6768 ins_cost(150); // XXX
6769 format %{ "addl $dst, $src\t# int" %}
6770 opcode(0x01); /* Opcode 01 /r */
6771 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6772 ins_pipe(ialu_mem_reg);
6773 %}
6774
6775 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6776 %{
6777 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6778 effect(KILL cr);
6779
6780 ins_cost(125); // XXX
6781 format %{ "addl $dst, $src\t# int" %}
6782 opcode(0x81); /* Opcode 81 /0 id */
6783 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6784 ins_pipe(ialu_mem_imm);
6785 %}
6786
6787 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6788 %{
6789 predicate(UseIncDec);
6790 match(Set dst (AddI dst src));
6791 effect(KILL cr);
6792
6793 format %{ "incl $dst\t# int" %}
6794 opcode(0xFF, 0x00); // FF /0
6795 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6796 ins_pipe(ialu_reg);
6797 %}
6798
6799 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6800 %{
6801 predicate(UseIncDec);
6802 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6803 effect(KILL cr);
6804
6805 ins_cost(125); // XXX
6806 format %{ "incl $dst\t# int" %}
6807 opcode(0xFF); /* Opcode FF /0 */
6808 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6809 ins_pipe(ialu_mem_imm);
6810 %}
6811
6812 // XXX why does that use AddI
6813 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6814 %{
6815 predicate(UseIncDec);
6816 match(Set dst (AddI dst src));
6817 effect(KILL cr);
6818
6819 format %{ "decl $dst\t# int" %}
6820 opcode(0xFF, 0x01); // FF /1
6821 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6822 ins_pipe(ialu_reg);
6823 %}
6824
6825 // XXX why does that use AddI
6826 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
6827 %{
6828 predicate(UseIncDec);
6829 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6830 effect(KILL cr);
6831
6832 ins_cost(125); // XXX
6833 format %{ "decl $dst\t# int" %}
6834 opcode(0xFF); /* Opcode FF /1 */
6835 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
6836 ins_pipe(ialu_mem_imm);
6837 %}
6838
6839 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
6840 %{
6841 match(Set dst (AddI src0 src1));
6842
6843 ins_cost(110);
6844 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
6845 opcode(0x8D); /* 0x8D /r */
6846 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
6847 ins_pipe(ialu_reg_reg);
6848 %}
6849
6850 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
6851 %{
6852 match(Set dst (AddL dst src));
6853 effect(KILL cr);
6854
6855 format %{ "addq $dst, $src\t# long" %}
6856 opcode(0x03);
6857 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
6858 ins_pipe(ialu_reg_reg);
6859 %}
6860
6861 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
6862 %{
6863 match(Set dst (AddL dst src));
6864 effect(KILL cr);
6865
6866 format %{ "addq $dst, $src\t# long" %}
6867 opcode(0x81, 0x00); /* /0 id */
6868 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
6869 ins_pipe( ialu_reg );
6870 %}
6871
6872 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
6873 %{
6874 match(Set dst (AddL dst (LoadL src)));
6875 effect(KILL cr);
6876
6877 ins_cost(125); // XXX
6878 format %{ "addq $dst, $src\t# long" %}
6879 opcode(0x03);
6880 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6881 ins_pipe(ialu_reg_mem);
6882 %}
6883
6884 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
6885 %{
6886 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6887 effect(KILL cr);
6888
6889 ins_cost(150); // XXX
6890 format %{ "addq $dst, $src\t# long" %}
6891 opcode(0x01); /* Opcode 01 /r */
6892 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6893 ins_pipe(ialu_mem_reg);
6894 %}
6895
6896 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
6897 %{
6898 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6899 effect(KILL cr);
6900
6901 ins_cost(125); // XXX
6902 format %{ "addq $dst, $src\t# long" %}
6903 opcode(0x81); /* Opcode 81 /0 id */
6904 ins_encode(REX_mem_wide(dst),
6905 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6906 ins_pipe(ialu_mem_imm);
6907 %}
6908
6909 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
6910 %{
6911 predicate(UseIncDec);
6912 match(Set dst (AddL dst src));
6913 effect(KILL cr);
6914
6915 format %{ "incq $dst\t# long" %}
6916 opcode(0xFF, 0x00); // FF /0
6917 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
6918 ins_pipe(ialu_reg);
6919 %}
6920
6921 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
6922 %{
6923 predicate(UseIncDec);
6924 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6925 effect(KILL cr);
6926
6927 ins_cost(125); // XXX
6928 format %{ "incq $dst\t# long" %}
6929 opcode(0xFF); /* Opcode FF /0 */
6930 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
6931 ins_pipe(ialu_mem_imm);
6932 %}
6933
6934 // XXX why does that use AddL
6935 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
6936 %{
6937 predicate(UseIncDec);
6938 match(Set dst (AddL dst src));
6939 effect(KILL cr);
6940
6941 format %{ "decq $dst\t# long" %}
6942 opcode(0xFF, 0x01); // FF /1
6943 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
6944 ins_pipe(ialu_reg);
6945 %}
6946
6947 // XXX why does that use AddL
6948 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
6949 %{
6950 predicate(UseIncDec);
6951 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6952 effect(KILL cr);
6953
6954 ins_cost(125); // XXX
6955 format %{ "decq $dst\t# long" %}
6956 opcode(0xFF); /* Opcode FF /1 */
6957 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
6958 ins_pipe(ialu_mem_imm);
6959 %}
6960
6961 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
6962 %{
6963 match(Set dst (AddL src0 src1));
6964
6965 ins_cost(110);
6966 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
6967 opcode(0x8D); /* 0x8D /r */
6968 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
6969 ins_pipe(ialu_reg_reg);
6970 %}
6971
6972 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
6973 %{
6974 match(Set dst (AddP dst src));
6975 effect(KILL cr);
6976
6977 format %{ "addq $dst, $src\t# ptr" %}
6978 opcode(0x03);
6979 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
6980 ins_pipe(ialu_reg_reg);
6981 %}
6982
6983 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
6984 %{
6985 match(Set dst (AddP dst src));
6986 effect(KILL cr);
6987
6988 format %{ "addq $dst, $src\t# ptr" %}
6989 opcode(0x81, 0x00); /* /0 id */
6990 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
6991 ins_pipe( ialu_reg );
6992 %}
6993
6994 // XXX addP mem ops ????
6995
6996 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
6997 %{
6998 match(Set dst (AddP src0 src1));
6999
7000 ins_cost(110);
7001 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7002 opcode(0x8D); /* 0x8D /r */
7003 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7004 ins_pipe(ialu_reg_reg);
7005 %}
7006
7007 instruct checkCastPP(rRegP dst)
7008 %{
7009 match(Set dst (CheckCastPP dst));
7010
7011 size(0);
7012 format %{ "# checkcastPP of $dst" %}
7013 ins_encode(/* empty encoding */);
7014 ins_pipe(empty);
7015 %}
7016
7017 instruct castPP(rRegP dst)
7018 %{
7019 match(Set dst (CastPP dst));
7020
7021 size(0);
7022 format %{ "# castPP of $dst" %}
7023 ins_encode(/* empty encoding */);
7024 ins_pipe(empty);
7025 %}
7026
7027 instruct castII(rRegI dst)
7028 %{
7029 match(Set dst (CastII dst));
7030
7031 size(0);
7032 format %{ "# castII of $dst" %}
7033 ins_encode(/* empty encoding */);
7034 ins_cost(0);
7035 ins_pipe(empty);
7036 %}
7037
7038 // LoadP-locked same as a regular LoadP when used with compare-swap
7039 instruct loadPLocked(rRegP dst, memory mem)
7040 %{
7041 match(Set dst (LoadPLocked mem));
7042
7043 ins_cost(125); // XXX
7044 format %{ "movq $dst, $mem\t# ptr locked" %}
7045 opcode(0x8B);
7046 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7047 ins_pipe(ialu_reg_mem); // XXX
7048 %}
7049
7050 // Conditional-store of the updated heap-top.
7051 // Used during allocation of the shared heap.
7052 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7053
7054 instruct storePConditional(memory heap_top_ptr,
7055 rax_RegP oldval, rRegP newval,
7056 rFlagsReg cr)
7057 %{
7058 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7059
7060 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7061 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7062 opcode(0x0F, 0xB1);
7063 ins_encode(lock_prefix,
7064 REX_reg_mem_wide(newval, heap_top_ptr),
7065 OpcP, OpcS,
7066 reg_mem(newval, heap_top_ptr));
7067 ins_pipe(pipe_cmpxchg);
7068 %}
7069
7070 // Conditional-store of an int value.
7071 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7072 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7073 %{
7074 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7075 effect(KILL oldval);
7076
7077 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7078 opcode(0x0F, 0xB1);
7079 ins_encode(lock_prefix,
7080 REX_reg_mem(newval, mem),
7081 OpcP, OpcS,
7082 reg_mem(newval, mem));
7083 ins_pipe(pipe_cmpxchg);
7084 %}
7085
7086 // Conditional-store of a long value.
7087 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7088 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7089 %{
7090 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7091 effect(KILL oldval);
7092
7093 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7094 opcode(0x0F, 0xB1);
7095 ins_encode(lock_prefix,
7096 REX_reg_mem_wide(newval, mem),
7097 OpcP, OpcS,
7098 reg_mem(newval, mem));
7099 ins_pipe(pipe_cmpxchg);
7100 %}
7101
7102
7103 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7104 instruct compareAndSwapP(rRegI res,
7105 memory mem_ptr,
7106 rax_RegP oldval, rRegP newval,
7107 rFlagsReg cr)
7108 %{
7109 predicate(VM_Version::supports_cx8());
7110 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7111 effect(KILL cr, KILL oldval);
7112
7113 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7114 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7115 "sete $res\n\t"
7116 "movzbl $res, $res" %}
7117 opcode(0x0F, 0xB1);
7118 ins_encode(lock_prefix,
7119 REX_reg_mem_wide(newval, mem_ptr),
7120 OpcP, OpcS,
7121 reg_mem(newval, mem_ptr),
7122 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7123 REX_reg_breg(res, res), // movzbl
7124 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7125 ins_pipe( pipe_cmpxchg );
7126 %}
7127
7128 instruct compareAndSwapL(rRegI res,
7129 memory mem_ptr,
7130 rax_RegL oldval, rRegL newval,
7131 rFlagsReg cr)
7132 %{
7133 predicate(VM_Version::supports_cx8());
7134 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7135 effect(KILL cr, KILL oldval);
7136
7137 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7138 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7139 "sete $res\n\t"
7140 "movzbl $res, $res" %}
7141 opcode(0x0F, 0xB1);
7142 ins_encode(lock_prefix,
7143 REX_reg_mem_wide(newval, mem_ptr),
7144 OpcP, OpcS,
7145 reg_mem(newval, mem_ptr),
7146 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7147 REX_reg_breg(res, res), // movzbl
7148 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7149 ins_pipe( pipe_cmpxchg );
7150 %}
7151
7152 instruct compareAndSwapI(rRegI res,
7153 memory mem_ptr,
7154 rax_RegI oldval, rRegI newval,
7155 rFlagsReg cr)
7156 %{
7157 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7158 effect(KILL cr, KILL oldval);
7159
7160 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7161 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7162 "sete $res\n\t"
7163 "movzbl $res, $res" %}
7164 opcode(0x0F, 0xB1);
7165 ins_encode(lock_prefix,
7166 REX_reg_mem(newval, mem_ptr),
7167 OpcP, OpcS,
7168 reg_mem(newval, mem_ptr),
7169 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7170 REX_reg_breg(res, res), // movzbl
7171 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7172 ins_pipe( pipe_cmpxchg );
7173 %}
7174
7175
7176 instruct compareAndSwapN(rRegI res,
7177 memory mem_ptr,
7178 rax_RegN oldval, rRegN newval,
7179 rFlagsReg cr) %{
7180 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7181 effect(KILL cr, KILL oldval);
7182
7183 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7184 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7185 "sete $res\n\t"
7186 "movzbl $res, $res" %}
7187 opcode(0x0F, 0xB1);
7188 ins_encode(lock_prefix,
7189 REX_reg_mem(newval, mem_ptr),
7190 OpcP, OpcS,
7191 reg_mem(newval, mem_ptr),
7192 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7193 REX_reg_breg(res, res), // movzbl
7194 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7195 ins_pipe( pipe_cmpxchg );
7196 %}
7197
7198 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7199 predicate(n->as_LoadStore()->result_not_used());
7200 match(Set dummy (GetAndAddI mem add));
7201 effect(KILL cr);
7202 format %{ "ADDL [$mem],$add" %}
7203 ins_encode %{
7204 if (os::is_MP()) { __ lock(); }
7205 __ addl($mem$$Address, $add$$constant);
7206 %}
7207 ins_pipe( pipe_cmpxchg );
7208 %}
7209
7210 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7211 match(Set newval (GetAndAddI mem newval));
7212 effect(KILL cr);
7213 format %{ "XADDL [$mem],$newval" %}
7214 ins_encode %{
7215 if (os::is_MP()) { __ lock(); }
7216 __ xaddl($mem$$Address, $newval$$Register);
7217 %}
7218 ins_pipe( pipe_cmpxchg );
7219 %}
7220
7221 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7222 predicate(n->as_LoadStore()->result_not_used());
7223 match(Set dummy (GetAndAddL mem add));
7224 effect(KILL cr);
7225 format %{ "ADDQ [$mem],$add" %}
7226 ins_encode %{
7227 if (os::is_MP()) { __ lock(); }
7228 __ addq($mem$$Address, $add$$constant);
7229 %}
7230 ins_pipe( pipe_cmpxchg );
7231 %}
7232
7233 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7234 match(Set newval (GetAndAddL mem newval));
7235 effect(KILL cr);
7236 format %{ "XADDQ [$mem],$newval" %}
7237 ins_encode %{
7238 if (os::is_MP()) { __ lock(); }
7239 __ xaddq($mem$$Address, $newval$$Register);
7240 %}
7241 ins_pipe( pipe_cmpxchg );
7242 %}
7243
7244 instruct xchgI( memory mem, rRegI newval) %{
7245 match(Set newval (GetAndSetI mem newval));
7246 format %{ "XCHGL $newval,[$mem]" %}
7247 ins_encode %{
7248 __ xchgl($newval$$Register, $mem$$Address);
7249 %}
7250 ins_pipe( pipe_cmpxchg );
7251 %}
7252
7253 instruct xchgL( memory mem, rRegL newval) %{
7254 match(Set newval (GetAndSetL mem newval));
7255 format %{ "XCHGL $newval,[$mem]" %}
7256 ins_encode %{
7257 __ xchgq($newval$$Register, $mem$$Address);
7258 %}
7259 ins_pipe( pipe_cmpxchg );
7260 %}
7261
7262 instruct xchgP( memory mem, rRegP newval) %{
7263 match(Set newval (GetAndSetP mem newval));
7264 format %{ "XCHGQ $newval,[$mem]" %}
7265 ins_encode %{
7266 __ xchgq($newval$$Register, $mem$$Address);
7267 %}
7268 ins_pipe( pipe_cmpxchg );
7269 %}
7270
7271 instruct xchgN( memory mem, rRegN newval) %{
7272 match(Set newval (GetAndSetN mem newval));
7273 format %{ "XCHGL $newval,$mem]" %}
7274 ins_encode %{
7275 __ xchgl($newval$$Register, $mem$$Address);
7276 %}
7277 ins_pipe( pipe_cmpxchg );
7278 %}
7279
7280 //----------Subtraction Instructions-------------------------------------------
7281
7282 // Integer Subtraction Instructions
7283 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7284 %{
7285 match(Set dst (SubI dst src));
7286 effect(KILL cr);
7287
7288 format %{ "subl $dst, $src\t# int" %}
7289 opcode(0x2B);
7290 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7291 ins_pipe(ialu_reg_reg);
7292 %}
7293
7294 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7295 %{
7296 match(Set dst (SubI dst src));
7297 effect(KILL cr);
7298
7299 format %{ "subl $dst, $src\t# int" %}
7300 opcode(0x81, 0x05); /* Opcode 81 /5 */
7301 ins_encode(OpcSErm(dst, src), Con8or32(src));
7302 ins_pipe(ialu_reg);
7303 %}
7304
7305 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7306 %{
7307 match(Set dst (SubI dst (LoadI src)));
7308 effect(KILL cr);
7309
7310 ins_cost(125);
7311 format %{ "subl $dst, $src\t# int" %}
7312 opcode(0x2B);
7313 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7314 ins_pipe(ialu_reg_mem);
7315 %}
7316
7317 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7318 %{
7319 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7320 effect(KILL cr);
7321
7322 ins_cost(150);
7323 format %{ "subl $dst, $src\t# int" %}
7324 opcode(0x29); /* Opcode 29 /r */
7325 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7326 ins_pipe(ialu_mem_reg);
7327 %}
7328
7329 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7330 %{
7331 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7332 effect(KILL cr);
7333
7334 ins_cost(125); // XXX
7335 format %{ "subl $dst, $src\t# int" %}
7336 opcode(0x81); /* Opcode 81 /5 id */
7337 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7338 ins_pipe(ialu_mem_imm);
7339 %}
7340
7341 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7342 %{
7343 match(Set dst (SubL dst src));
7344 effect(KILL cr);
7345
7346 format %{ "subq $dst, $src\t# long" %}
7347 opcode(0x2B);
7348 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7349 ins_pipe(ialu_reg_reg);
7350 %}
7351
7352 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7353 %{
7354 match(Set dst (SubL dst src));
7355 effect(KILL cr);
7356
7357 format %{ "subq $dst, $src\t# long" %}
7358 opcode(0x81, 0x05); /* Opcode 81 /5 */
7359 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7360 ins_pipe(ialu_reg);
7361 %}
7362
7363 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7364 %{
7365 match(Set dst (SubL dst (LoadL src)));
7366 effect(KILL cr);
7367
7368 ins_cost(125);
7369 format %{ "subq $dst, $src\t# long" %}
7370 opcode(0x2B);
7371 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7372 ins_pipe(ialu_reg_mem);
7373 %}
7374
7375 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7376 %{
7377 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7378 effect(KILL cr);
7379
7380 ins_cost(150);
7381 format %{ "subq $dst, $src\t# long" %}
7382 opcode(0x29); /* Opcode 29 /r */
7383 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7384 ins_pipe(ialu_mem_reg);
7385 %}
7386
7387 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7388 %{
7389 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7390 effect(KILL cr);
7391
7392 ins_cost(125); // XXX
7393 format %{ "subq $dst, $src\t# long" %}
7394 opcode(0x81); /* Opcode 81 /5 id */
7395 ins_encode(REX_mem_wide(dst),
7396 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7397 ins_pipe(ialu_mem_imm);
7398 %}
7399
7400 // Subtract from a pointer
7401 // XXX hmpf???
7402 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7403 %{
7404 match(Set dst (AddP dst (SubI zero src)));
7405 effect(KILL cr);
7406
7407 format %{ "subq $dst, $src\t# ptr - int" %}
7408 opcode(0x2B);
7409 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7410 ins_pipe(ialu_reg_reg);
7411 %}
7412
7413 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7414 %{
7415 match(Set dst (SubI zero dst));
7416 effect(KILL cr);
7417
7418 format %{ "negl $dst\t# int" %}
7419 opcode(0xF7, 0x03); // Opcode F7 /3
7420 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7421 ins_pipe(ialu_reg);
7422 %}
7423
7424 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7425 %{
7426 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7427 effect(KILL cr);
7428
7429 format %{ "negl $dst\t# int" %}
7430 opcode(0xF7, 0x03); // Opcode F7 /3
7431 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7432 ins_pipe(ialu_reg);
7433 %}
7434
7435 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7436 %{
7437 match(Set dst (SubL zero dst));
7438 effect(KILL cr);
7439
7440 format %{ "negq $dst\t# long" %}
7441 opcode(0xF7, 0x03); // Opcode F7 /3
7442 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7443 ins_pipe(ialu_reg);
7444 %}
7445
7446 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7447 %{
7448 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7449 effect(KILL cr);
7450
7451 format %{ "negq $dst\t# long" %}
7452 opcode(0xF7, 0x03); // Opcode F7 /3
7453 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7454 ins_pipe(ialu_reg);
7455 %}
7456
7457 //----------Multiplication/Division Instructions-------------------------------
7458 // Integer Multiplication Instructions
7459 // Multiply Register
7460
7461 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7462 %{
7463 match(Set dst (MulI dst src));
7464 effect(KILL cr);
7465
7466 ins_cost(300);
7467 format %{ "imull $dst, $src\t# int" %}
7468 opcode(0x0F, 0xAF);
7469 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7470 ins_pipe(ialu_reg_reg_alu0);
7471 %}
7472
7473 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7474 %{
7475 match(Set dst (MulI src imm));
7476 effect(KILL cr);
7477
7478 ins_cost(300);
7479 format %{ "imull $dst, $src, $imm\t# int" %}
7480 opcode(0x69); /* 69 /r id */
7481 ins_encode(REX_reg_reg(dst, src),
7482 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7483 ins_pipe(ialu_reg_reg_alu0);
7484 %}
7485
7486 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7487 %{
7488 match(Set dst (MulI dst (LoadI src)));
7489 effect(KILL cr);
7490
7491 ins_cost(350);
7492 format %{ "imull $dst, $src\t# int" %}
7493 opcode(0x0F, 0xAF);
7494 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7495 ins_pipe(ialu_reg_mem_alu0);
7496 %}
7497
7498 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7499 %{
7500 match(Set dst (MulI (LoadI src) imm));
7501 effect(KILL cr);
7502
7503 ins_cost(300);
7504 format %{ "imull $dst, $src, $imm\t# int" %}
7505 opcode(0x69); /* 69 /r id */
7506 ins_encode(REX_reg_mem(dst, src),
7507 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7508 ins_pipe(ialu_reg_mem_alu0);
7509 %}
7510
7511 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7512 %{
7513 match(Set dst (MulL dst src));
7514 effect(KILL cr);
7515
7516 ins_cost(300);
7517 format %{ "imulq $dst, $src\t# long" %}
7518 opcode(0x0F, 0xAF);
7519 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7520 ins_pipe(ialu_reg_reg_alu0);
7521 %}
7522
7523 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7524 %{
7525 match(Set dst (MulL src imm));
7526 effect(KILL cr);
7527
7528 ins_cost(300);
7529 format %{ "imulq $dst, $src, $imm\t# long" %}
7530 opcode(0x69); /* 69 /r id */
7531 ins_encode(REX_reg_reg_wide(dst, src),
7532 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7533 ins_pipe(ialu_reg_reg_alu0);
7534 %}
7535
7536 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7537 %{
7538 match(Set dst (MulL dst (LoadL src)));
7539 effect(KILL cr);
7540
7541 ins_cost(350);
7542 format %{ "imulq $dst, $src\t# long" %}
7543 opcode(0x0F, 0xAF);
7544 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7545 ins_pipe(ialu_reg_mem_alu0);
7546 %}
7547
7548 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7549 %{
7550 match(Set dst (MulL (LoadL src) imm));
7551 effect(KILL cr);
7552
7553 ins_cost(300);
7554 format %{ "imulq $dst, $src, $imm\t# long" %}
7555 opcode(0x69); /* 69 /r id */
7556 ins_encode(REX_reg_mem_wide(dst, src),
7557 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7558 ins_pipe(ialu_reg_mem_alu0);
7559 %}
7560
7561 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7562 %{
7563 match(Set dst (MulHiL src rax));
7564 effect(USE_KILL rax, KILL cr);
7565
7566 ins_cost(300);
7567 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7568 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7569 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7570 ins_pipe(ialu_reg_reg_alu0);
7571 %}
7572
7573 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7574 rFlagsReg cr)
7575 %{
7576 match(Set rax (DivI rax div));
7577 effect(KILL rdx, KILL cr);
7578
7579 ins_cost(30*100+10*100); // XXX
7580 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7581 "jne,s normal\n\t"
7582 "xorl rdx, rdx\n\t"
7583 "cmpl $div, -1\n\t"
7584 "je,s done\n"
7585 "normal: cdql\n\t"
7586 "idivl $div\n"
7587 "done:" %}
7588 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7589 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7590 ins_pipe(ialu_reg_reg_alu0);
7591 %}
7592
7593 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7594 rFlagsReg cr)
7595 %{
7596 match(Set rax (DivL rax div));
7597 effect(KILL rdx, KILL cr);
7598
7599 ins_cost(30*100+10*100); // XXX
7600 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7601 "cmpq rax, rdx\n\t"
7602 "jne,s normal\n\t"
7603 "xorl rdx, rdx\n\t"
7604 "cmpq $div, -1\n\t"
7605 "je,s done\n"
7606 "normal: cdqq\n\t"
7607 "idivq $div\n"
7608 "done:" %}
7609 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7610 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7611 ins_pipe(ialu_reg_reg_alu0);
7612 %}
7613
7614 // Integer DIVMOD with Register, both quotient and mod results
7615 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7616 rFlagsReg cr)
7617 %{
7618 match(DivModI rax div);
7619 effect(KILL cr);
7620
7621 ins_cost(30*100+10*100); // XXX
7622 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7623 "jne,s normal\n\t"
7624 "xorl rdx, rdx\n\t"
7625 "cmpl $div, -1\n\t"
7626 "je,s done\n"
7627 "normal: cdql\n\t"
7628 "idivl $div\n"
7629 "done:" %}
7630 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7631 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7632 ins_pipe(pipe_slow);
7633 %}
7634
7635 // Long DIVMOD with Register, both quotient and mod results
7636 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7637 rFlagsReg cr)
7638 %{
7639 match(DivModL rax div);
7640 effect(KILL cr);
7641
7642 ins_cost(30*100+10*100); // XXX
7643 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7644 "cmpq rax, rdx\n\t"
7645 "jne,s normal\n\t"
7646 "xorl rdx, rdx\n\t"
7647 "cmpq $div, -1\n\t"
7648 "je,s done\n"
7649 "normal: cdqq\n\t"
7650 "idivq $div\n"
7651 "done:" %}
7652 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7653 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7654 ins_pipe(pipe_slow);
7655 %}
7656
7657 //----------- DivL-By-Constant-Expansions--------------------------------------
7658 // DivI cases are handled by the compiler
7659
7660 // Magic constant, reciprocal of 10
7661 instruct loadConL_0x6666666666666667(rRegL dst)
7662 %{
7663 effect(DEF dst);
7664
7665 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
7666 ins_encode(load_immL(dst, 0x6666666666666667));
7667 ins_pipe(ialu_reg);
7668 %}
7669
7670 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7671 %{
7672 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
7673
7674 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
7675 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7676 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7677 ins_pipe(ialu_reg_reg_alu0);
7678 %}
7679
7680 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
7681 %{
7682 effect(USE_DEF dst, KILL cr);
7683
7684 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
7685 opcode(0xC1, 0x7); /* C1 /7 ib */
7686 ins_encode(reg_opc_imm_wide(dst, 0x3F));
7687 ins_pipe(ialu_reg);
7688 %}
7689
7690 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
7691 %{
7692 effect(USE_DEF dst, KILL cr);
7693
7694 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
7695 opcode(0xC1, 0x7); /* C1 /7 ib */
7696 ins_encode(reg_opc_imm_wide(dst, 0x2));
7697 ins_pipe(ialu_reg);
7698 %}
7699
7700 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
7701 %{
7702 match(Set dst (DivL src div));
7703
7704 ins_cost((5+8)*100);
7705 expand %{
7706 rax_RegL rax; // Killed temp
7707 rFlagsReg cr; // Killed
7708 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
7709 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
7710 sarL_rReg_63(src, cr); // sarq src, 63
7711 sarL_rReg_2(dst, cr); // sarq rdx, 2
7712 subL_rReg(dst, src, cr); // subl rdx, src
7713 %}
7714 %}
7715
7716 //-----------------------------------------------------------------------------
7717
7718 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7719 rFlagsReg cr)
7720 %{
7721 match(Set rdx (ModI rax div));
7722 effect(KILL rax, KILL cr);
7723
7724 ins_cost(300); // XXX
7725 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7726 "jne,s normal\n\t"
7727 "xorl rdx, rdx\n\t"
7728 "cmpl $div, -1\n\t"
7729 "je,s done\n"
7730 "normal: cdql\n\t"
7731 "idivl $div\n"
7732 "done:" %}
7733 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7734 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7735 ins_pipe(ialu_reg_reg_alu0);
7736 %}
7737
7738 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7739 rFlagsReg cr)
7740 %{
7741 match(Set rdx (ModL rax div));
7742 effect(KILL rax, KILL cr);
7743
7744 ins_cost(300); // XXX
7745 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
7746 "cmpq rax, rdx\n\t"
7747 "jne,s normal\n\t"
7748 "xorl rdx, rdx\n\t"
7749 "cmpq $div, -1\n\t"
7750 "je,s done\n"
7751 "normal: cdqq\n\t"
7752 "idivq $div\n"
7753 "done:" %}
7754 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7755 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7756 ins_pipe(ialu_reg_reg_alu0);
7757 %}
7758
7759 // Integer Shift Instructions
7760 // Shift Left by one
7761 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7762 %{
7763 match(Set dst (LShiftI dst shift));
7764 effect(KILL cr);
7765
7766 format %{ "sall $dst, $shift" %}
7767 opcode(0xD1, 0x4); /* D1 /4 */
7768 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7769 ins_pipe(ialu_reg);
7770 %}
7771
7772 // Shift Left by one
7773 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7774 %{
7775 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7776 effect(KILL cr);
7777
7778 format %{ "sall $dst, $shift\t" %}
7779 opcode(0xD1, 0x4); /* D1 /4 */
7780 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7781 ins_pipe(ialu_mem_imm);
7782 %}
7783
7784 // Shift Left by 8-bit immediate
7785 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7786 %{
7787 match(Set dst (LShiftI dst shift));
7788 effect(KILL cr);
7789
7790 format %{ "sall $dst, $shift" %}
7791 opcode(0xC1, 0x4); /* C1 /4 ib */
7792 ins_encode(reg_opc_imm(dst, shift));
7793 ins_pipe(ialu_reg);
7794 %}
7795
7796 // Shift Left by 8-bit immediate
7797 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7798 %{
7799 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7800 effect(KILL cr);
7801
7802 format %{ "sall $dst, $shift" %}
7803 opcode(0xC1, 0x4); /* C1 /4 ib */
7804 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7805 ins_pipe(ialu_mem_imm);
7806 %}
7807
7808 // Shift Left by variable
7809 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7810 %{
7811 match(Set dst (LShiftI dst shift));
7812 effect(KILL cr);
7813
7814 format %{ "sall $dst, $shift" %}
7815 opcode(0xD3, 0x4); /* D3 /4 */
7816 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7817 ins_pipe(ialu_reg_reg);
7818 %}
7819
7820 // Shift Left by variable
7821 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7822 %{
7823 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7824 effect(KILL cr);
7825
7826 format %{ "sall $dst, $shift" %}
7827 opcode(0xD3, 0x4); /* D3 /4 */
7828 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7829 ins_pipe(ialu_mem_reg);
7830 %}
7831
7832 // Arithmetic shift right by one
7833 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7834 %{
7835 match(Set dst (RShiftI dst shift));
7836 effect(KILL cr);
7837
7838 format %{ "sarl $dst, $shift" %}
7839 opcode(0xD1, 0x7); /* D1 /7 */
7840 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7841 ins_pipe(ialu_reg);
7842 %}
7843
7844 // Arithmetic shift right by one
7845 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7846 %{
7847 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7848 effect(KILL cr);
7849
7850 format %{ "sarl $dst, $shift" %}
7851 opcode(0xD1, 0x7); /* D1 /7 */
7852 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7853 ins_pipe(ialu_mem_imm);
7854 %}
7855
7856 // Arithmetic Shift Right by 8-bit immediate
7857 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7858 %{
7859 match(Set dst (RShiftI dst shift));
7860 effect(KILL cr);
7861
7862 format %{ "sarl $dst, $shift" %}
7863 opcode(0xC1, 0x7); /* C1 /7 ib */
7864 ins_encode(reg_opc_imm(dst, shift));
7865 ins_pipe(ialu_mem_imm);
7866 %}
7867
7868 // Arithmetic Shift Right by 8-bit immediate
7869 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7870 %{
7871 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7872 effect(KILL cr);
7873
7874 format %{ "sarl $dst, $shift" %}
7875 opcode(0xC1, 0x7); /* C1 /7 ib */
7876 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7877 ins_pipe(ialu_mem_imm);
7878 %}
7879
7880 // Arithmetic Shift Right by variable
7881 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7882 %{
7883 match(Set dst (RShiftI dst shift));
7884 effect(KILL cr);
7885
7886 format %{ "sarl $dst, $shift" %}
7887 opcode(0xD3, 0x7); /* D3 /7 */
7888 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7889 ins_pipe(ialu_reg_reg);
7890 %}
7891
7892 // Arithmetic Shift Right by variable
7893 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7894 %{
7895 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7896 effect(KILL cr);
7897
7898 format %{ "sarl $dst, $shift" %}
7899 opcode(0xD3, 0x7); /* D3 /7 */
7900 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7901 ins_pipe(ialu_mem_reg);
7902 %}
7903
7904 // Logical shift right by one
7905 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7906 %{
7907 match(Set dst (URShiftI dst shift));
7908 effect(KILL cr);
7909
7910 format %{ "shrl $dst, $shift" %}
7911 opcode(0xD1, 0x5); /* D1 /5 */
7912 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7913 ins_pipe(ialu_reg);
7914 %}
7915
7916 // Logical shift right by one
7917 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7918 %{
7919 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
7920 effect(KILL cr);
7921
7922 format %{ "shrl $dst, $shift" %}
7923 opcode(0xD1, 0x5); /* D1 /5 */
7924 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7925 ins_pipe(ialu_mem_imm);
7926 %}
7927
7928 // Logical Shift Right by 8-bit immediate
7929 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7930 %{
7931 match(Set dst (URShiftI dst shift));
7932 effect(KILL cr);
7933
7934 format %{ "shrl $dst, $shift" %}
7935 opcode(0xC1, 0x5); /* C1 /5 ib */
7936 ins_encode(reg_opc_imm(dst, shift));
7937 ins_pipe(ialu_reg);
7938 %}
7939
7940 // Logical Shift Right by 8-bit immediate
7941 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7942 %{
7943 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
7944 effect(KILL cr);
7945
7946 format %{ "shrl $dst, $shift" %}
7947 opcode(0xC1, 0x5); /* C1 /5 ib */
7948 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7949 ins_pipe(ialu_mem_imm);
7950 %}
7951
7952 // Logical Shift Right by variable
7953 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7954 %{
7955 match(Set dst (URShiftI dst shift));
7956 effect(KILL cr);
7957
7958 format %{ "shrl $dst, $shift" %}
7959 opcode(0xD3, 0x5); /* D3 /5 */
7960 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7961 ins_pipe(ialu_reg_reg);
7962 %}
7963
7964 // Logical Shift Right by variable
7965 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7966 %{
7967 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
7968 effect(KILL cr);
7969
7970 format %{ "shrl $dst, $shift" %}
7971 opcode(0xD3, 0x5); /* D3 /5 */
7972 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7973 ins_pipe(ialu_mem_reg);
7974 %}
7975
7976 // Long Shift Instructions
7977 // Shift Left by one
7978 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
7979 %{
7980 match(Set dst (LShiftL dst shift));
7981 effect(KILL cr);
7982
7983 format %{ "salq $dst, $shift" %}
7984 opcode(0xD1, 0x4); /* D1 /4 */
7985 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7986 ins_pipe(ialu_reg);
7987 %}
7988
7989 // Shift Left by one
7990 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7991 %{
7992 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
7993 effect(KILL cr);
7994
7995 format %{ "salq $dst, $shift" %}
7996 opcode(0xD1, 0x4); /* D1 /4 */
7997 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7998 ins_pipe(ialu_mem_imm);
7999 %}
8000
8001 // Shift Left by 8-bit immediate
8002 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8003 %{
8004 match(Set dst (LShiftL dst shift));
8005 effect(KILL cr);
8006
8007 format %{ "salq $dst, $shift" %}
8008 opcode(0xC1, 0x4); /* C1 /4 ib */
8009 ins_encode(reg_opc_imm_wide(dst, shift));
8010 ins_pipe(ialu_reg);
8011 %}
8012
8013 // Shift Left by 8-bit immediate
8014 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8015 %{
8016 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8017 effect(KILL cr);
8018
8019 format %{ "salq $dst, $shift" %}
8020 opcode(0xC1, 0x4); /* C1 /4 ib */
8021 ins_encode(REX_mem_wide(dst), OpcP,
8022 RM_opc_mem(secondary, dst), Con8or32(shift));
8023 ins_pipe(ialu_mem_imm);
8024 %}
8025
8026 // Shift Left by variable
8027 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8028 %{
8029 match(Set dst (LShiftL dst shift));
8030 effect(KILL cr);
8031
8032 format %{ "salq $dst, $shift" %}
8033 opcode(0xD3, 0x4); /* D3 /4 */
8034 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8035 ins_pipe(ialu_reg_reg);
8036 %}
8037
8038 // Shift Left by variable
8039 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8040 %{
8041 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8042 effect(KILL cr);
8043
8044 format %{ "salq $dst, $shift" %}
8045 opcode(0xD3, 0x4); /* D3 /4 */
8046 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8047 ins_pipe(ialu_mem_reg);
8048 %}
8049
8050 // Arithmetic shift right by one
8051 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8052 %{
8053 match(Set dst (RShiftL dst shift));
8054 effect(KILL cr);
8055
8056 format %{ "sarq $dst, $shift" %}
8057 opcode(0xD1, 0x7); /* D1 /7 */
8058 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8059 ins_pipe(ialu_reg);
8060 %}
8061
8062 // Arithmetic shift right by one
8063 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8064 %{
8065 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8066 effect(KILL cr);
8067
8068 format %{ "sarq $dst, $shift" %}
8069 opcode(0xD1, 0x7); /* D1 /7 */
8070 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8071 ins_pipe(ialu_mem_imm);
8072 %}
8073
8074 // Arithmetic Shift Right by 8-bit immediate
8075 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8076 %{
8077 match(Set dst (RShiftL dst shift));
8078 effect(KILL cr);
8079
8080 format %{ "sarq $dst, $shift" %}
8081 opcode(0xC1, 0x7); /* C1 /7 ib */
8082 ins_encode(reg_opc_imm_wide(dst, shift));
8083 ins_pipe(ialu_mem_imm);
8084 %}
8085
8086 // Arithmetic Shift Right by 8-bit immediate
8087 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8088 %{
8089 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8090 effect(KILL cr);
8091
8092 format %{ "sarq $dst, $shift" %}
8093 opcode(0xC1, 0x7); /* C1 /7 ib */
8094 ins_encode(REX_mem_wide(dst), OpcP,
8095 RM_opc_mem(secondary, dst), Con8or32(shift));
8096 ins_pipe(ialu_mem_imm);
8097 %}
8098
8099 // Arithmetic Shift Right by variable
8100 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8101 %{
8102 match(Set dst (RShiftL dst shift));
8103 effect(KILL cr);
8104
8105 format %{ "sarq $dst, $shift" %}
8106 opcode(0xD3, 0x7); /* D3 /7 */
8107 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8108 ins_pipe(ialu_reg_reg);
8109 %}
8110
8111 // Arithmetic Shift Right by variable
8112 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8113 %{
8114 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8115 effect(KILL cr);
8116
8117 format %{ "sarq $dst, $shift" %}
8118 opcode(0xD3, 0x7); /* D3 /7 */
8119 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8120 ins_pipe(ialu_mem_reg);
8121 %}
8122
8123 // Logical shift right by one
8124 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8125 %{
8126 match(Set dst (URShiftL dst shift));
8127 effect(KILL cr);
8128
8129 format %{ "shrq $dst, $shift" %}
8130 opcode(0xD1, 0x5); /* D1 /5 */
8131 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8132 ins_pipe(ialu_reg);
8133 %}
8134
8135 // Logical shift right by one
8136 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8137 %{
8138 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8139 effect(KILL cr);
8140
8141 format %{ "shrq $dst, $shift" %}
8142 opcode(0xD1, 0x5); /* D1 /5 */
8143 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8144 ins_pipe(ialu_mem_imm);
8145 %}
8146
8147 // Logical Shift Right by 8-bit immediate
8148 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8149 %{
8150 match(Set dst (URShiftL dst shift));
8151 effect(KILL cr);
8152
8153 format %{ "shrq $dst, $shift" %}
8154 opcode(0xC1, 0x5); /* C1 /5 ib */
8155 ins_encode(reg_opc_imm_wide(dst, shift));
8156 ins_pipe(ialu_reg);
8157 %}
8158
8159
8160 // Logical Shift Right by 8-bit immediate
8161 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8162 %{
8163 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8164 effect(KILL cr);
8165
8166 format %{ "shrq $dst, $shift" %}
8167 opcode(0xC1, 0x5); /* C1 /5 ib */
8168 ins_encode(REX_mem_wide(dst), OpcP,
8169 RM_opc_mem(secondary, dst), Con8or32(shift));
8170 ins_pipe(ialu_mem_imm);
8171 %}
8172
8173 // Logical Shift Right by variable
8174 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8175 %{
8176 match(Set dst (URShiftL dst shift));
8177 effect(KILL cr);
8178
8179 format %{ "shrq $dst, $shift" %}
8180 opcode(0xD3, 0x5); /* D3 /5 */
8181 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8182 ins_pipe(ialu_reg_reg);
8183 %}
8184
8185 // Logical Shift Right by variable
8186 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8187 %{
8188 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8189 effect(KILL cr);
8190
8191 format %{ "shrq $dst, $shift" %}
8192 opcode(0xD3, 0x5); /* D3 /5 */
8193 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8194 ins_pipe(ialu_mem_reg);
8195 %}
8196
8197 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8198 // This idiom is used by the compiler for the i2b bytecode.
8199 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8200 %{
8201 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8202
8203 format %{ "movsbl $dst, $src\t# i2b" %}
8204 opcode(0x0F, 0xBE);
8205 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8206 ins_pipe(ialu_reg_reg);
8207 %}
8208
8209 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8210 // This idiom is used by the compiler the i2s bytecode.
8211 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8212 %{
8213 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8214
8215 format %{ "movswl $dst, $src\t# i2s" %}
8216 opcode(0x0F, 0xBF);
8217 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8218 ins_pipe(ialu_reg_reg);
8219 %}
8220
8221 // ROL/ROR instructions
8222
8223 // ROL expand
8224 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8225 effect(KILL cr, USE_DEF dst);
8226
8227 format %{ "roll $dst" %}
8228 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8229 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8230 ins_pipe(ialu_reg);
8231 %}
8232
8233 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8234 effect(USE_DEF dst, USE shift, KILL cr);
8235
8236 format %{ "roll $dst, $shift" %}
8237 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8238 ins_encode( reg_opc_imm(dst, shift) );
8239 ins_pipe(ialu_reg);
8240 %}
8241
8242 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8243 %{
8244 effect(USE_DEF dst, USE shift, KILL cr);
8245
8246 format %{ "roll $dst, $shift" %}
8247 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8248 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8249 ins_pipe(ialu_reg_reg);
8250 %}
8251 // end of ROL expand
8252
8253 // Rotate Left by one
8254 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8255 %{
8256 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8257
8258 expand %{
8259 rolI_rReg_imm1(dst, cr);
8260 %}
8261 %}
8262
8263 // Rotate Left by 8-bit immediate
8264 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8265 %{
8266 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8267 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8268
8269 expand %{
8270 rolI_rReg_imm8(dst, lshift, cr);
8271 %}
8272 %}
8273
8274 // Rotate Left by variable
8275 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8276 %{
8277 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8278
8279 expand %{
8280 rolI_rReg_CL(dst, shift, cr);
8281 %}
8282 %}
8283
8284 // Rotate Left by variable
8285 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8286 %{
8287 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8288
8289 expand %{
8290 rolI_rReg_CL(dst, shift, cr);
8291 %}
8292 %}
8293
8294 // ROR expand
8295 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8296 %{
8297 effect(USE_DEF dst, KILL cr);
8298
8299 format %{ "rorl $dst" %}
8300 opcode(0xD1, 0x1); /* D1 /1 */
8301 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8302 ins_pipe(ialu_reg);
8303 %}
8304
8305 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8306 %{
8307 effect(USE_DEF dst, USE shift, KILL cr);
8308
8309 format %{ "rorl $dst, $shift" %}
8310 opcode(0xC1, 0x1); /* C1 /1 ib */
8311 ins_encode(reg_opc_imm(dst, shift));
8312 ins_pipe(ialu_reg);
8313 %}
8314
8315 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8316 %{
8317 effect(USE_DEF dst, USE shift, KILL cr);
8318
8319 format %{ "rorl $dst, $shift" %}
8320 opcode(0xD3, 0x1); /* D3 /1 */
8321 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8322 ins_pipe(ialu_reg_reg);
8323 %}
8324 // end of ROR expand
8325
8326 // Rotate Right by one
8327 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8328 %{
8329 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8330
8331 expand %{
8332 rorI_rReg_imm1(dst, cr);
8333 %}
8334 %}
8335
8336 // Rotate Right by 8-bit immediate
8337 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8338 %{
8339 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8340 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8341
8342 expand %{
8343 rorI_rReg_imm8(dst, rshift, cr);
8344 %}
8345 %}
8346
8347 // Rotate Right by variable
8348 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8349 %{
8350 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8351
8352 expand %{
8353 rorI_rReg_CL(dst, shift, cr);
8354 %}
8355 %}
8356
8357 // Rotate Right by variable
8358 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8359 %{
8360 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8361
8362 expand %{
8363 rorI_rReg_CL(dst, shift, cr);
8364 %}
8365 %}
8366
8367 // for long rotate
8368 // ROL expand
8369 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8370 effect(USE_DEF dst, KILL cr);
8371
8372 format %{ "rolq $dst" %}
8373 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8374 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8375 ins_pipe(ialu_reg);
8376 %}
8377
8378 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8379 effect(USE_DEF dst, USE shift, KILL cr);
8380
8381 format %{ "rolq $dst, $shift" %}
8382 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8383 ins_encode( reg_opc_imm_wide(dst, shift) );
8384 ins_pipe(ialu_reg);
8385 %}
8386
8387 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8388 %{
8389 effect(USE_DEF dst, USE shift, KILL cr);
8390
8391 format %{ "rolq $dst, $shift" %}
8392 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8393 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8394 ins_pipe(ialu_reg_reg);
8395 %}
8396 // end of ROL expand
8397
8398 // Rotate Left by one
8399 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8400 %{
8401 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8402
8403 expand %{
8404 rolL_rReg_imm1(dst, cr);
8405 %}
8406 %}
8407
8408 // Rotate Left by 8-bit immediate
8409 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8410 %{
8411 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8412 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8413
8414 expand %{
8415 rolL_rReg_imm8(dst, lshift, cr);
8416 %}
8417 %}
8418
8419 // Rotate Left by variable
8420 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8421 %{
8422 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8423
8424 expand %{
8425 rolL_rReg_CL(dst, shift, cr);
8426 %}
8427 %}
8428
8429 // Rotate Left by variable
8430 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8431 %{
8432 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8433
8434 expand %{
8435 rolL_rReg_CL(dst, shift, cr);
8436 %}
8437 %}
8438
8439 // ROR expand
8440 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8441 %{
8442 effect(USE_DEF dst, KILL cr);
8443
8444 format %{ "rorq $dst" %}
8445 opcode(0xD1, 0x1); /* D1 /1 */
8446 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8447 ins_pipe(ialu_reg);
8448 %}
8449
8450 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8451 %{
8452 effect(USE_DEF dst, USE shift, KILL cr);
8453
8454 format %{ "rorq $dst, $shift" %}
8455 opcode(0xC1, 0x1); /* C1 /1 ib */
8456 ins_encode(reg_opc_imm_wide(dst, shift));
8457 ins_pipe(ialu_reg);
8458 %}
8459
8460 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8461 %{
8462 effect(USE_DEF dst, USE shift, KILL cr);
8463
8464 format %{ "rorq $dst, $shift" %}
8465 opcode(0xD3, 0x1); /* D3 /1 */
8466 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8467 ins_pipe(ialu_reg_reg);
8468 %}
8469 // end of ROR expand
8470
8471 // Rotate Right by one
8472 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8473 %{
8474 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8475
8476 expand %{
8477 rorL_rReg_imm1(dst, cr);
8478 %}
8479 %}
8480
8481 // Rotate Right by 8-bit immediate
8482 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8483 %{
8484 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8485 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8486
8487 expand %{
8488 rorL_rReg_imm8(dst, rshift, cr);
8489 %}
8490 %}
8491
8492 // Rotate Right by variable
8493 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8494 %{
8495 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8496
8497 expand %{
8498 rorL_rReg_CL(dst, shift, cr);
8499 %}
8500 %}
8501
8502 // Rotate Right by variable
8503 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8504 %{
8505 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8506
8507 expand %{
8508 rorL_rReg_CL(dst, shift, cr);
8509 %}
8510 %}
8511
8512 // Logical Instructions
8513
8514 // Integer Logical Instructions
8515
8516 // And Instructions
8517 // And Register with Register
8518 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8519 %{
8520 match(Set dst (AndI dst src));
8521 effect(KILL cr);
8522
8523 format %{ "andl $dst, $src\t# int" %}
8524 opcode(0x23);
8525 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8526 ins_pipe(ialu_reg_reg);
8527 %}
8528
8529 // And Register with Immediate 255
8530 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8531 %{
8532 match(Set dst (AndI dst src));
8533
8534 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8535 opcode(0x0F, 0xB6);
8536 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8537 ins_pipe(ialu_reg);
8538 %}
8539
8540 // And Register with Immediate 255 and promote to long
8541 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8542 %{
8543 match(Set dst (ConvI2L (AndI src mask)));
8544
8545 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8546 opcode(0x0F, 0xB6);
8547 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8548 ins_pipe(ialu_reg);
8549 %}
8550
8551 // And Register with Immediate 65535
8552 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8553 %{
8554 match(Set dst (AndI dst src));
8555
8556 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8557 opcode(0x0F, 0xB7);
8558 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8559 ins_pipe(ialu_reg);
8560 %}
8561
8562 // And Register with Immediate 65535 and promote to long
8563 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8564 %{
8565 match(Set dst (ConvI2L (AndI src mask)));
8566
8567 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8568 opcode(0x0F, 0xB7);
8569 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8570 ins_pipe(ialu_reg);
8571 %}
8572
8573 // And Register with Immediate
8574 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8575 %{
8576 match(Set dst (AndI dst src));
8577 effect(KILL cr);
8578
8579 format %{ "andl $dst, $src\t# int" %}
8580 opcode(0x81, 0x04); /* Opcode 81 /4 */
8581 ins_encode(OpcSErm(dst, src), Con8or32(src));
8582 ins_pipe(ialu_reg);
8583 %}
8584
8585 // And Register with Memory
8586 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8587 %{
8588 match(Set dst (AndI dst (LoadI src)));
8589 effect(KILL cr);
8590
8591 ins_cost(125);
8592 format %{ "andl $dst, $src\t# int" %}
8593 opcode(0x23);
8594 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8595 ins_pipe(ialu_reg_mem);
8596 %}
8597
8598 // And Memory with Register
8599 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8600 %{
8601 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8602 effect(KILL cr);
8603
8604 ins_cost(150);
8605 format %{ "andl $dst, $src\t# int" %}
8606 opcode(0x21); /* Opcode 21 /r */
8607 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8608 ins_pipe(ialu_mem_reg);
8609 %}
8610
8611 // And Memory with Immediate
8612 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8613 %{
8614 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8615 effect(KILL cr);
8616
8617 ins_cost(125);
8618 format %{ "andl $dst, $src\t# int" %}
8619 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8620 ins_encode(REX_mem(dst), OpcSE(src),
8621 RM_opc_mem(secondary, dst), Con8or32(src));
8622 ins_pipe(ialu_mem_imm);
8623 %}
8624
8625 // Or Instructions
8626 // Or Register with Register
8627 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8628 %{
8629 match(Set dst (OrI dst src));
8630 effect(KILL cr);
8631
8632 format %{ "orl $dst, $src\t# int" %}
8633 opcode(0x0B);
8634 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8635 ins_pipe(ialu_reg_reg);
8636 %}
8637
8638 // Or Register with Immediate
8639 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8640 %{
8641 match(Set dst (OrI dst src));
8642 effect(KILL cr);
8643
8644 format %{ "orl $dst, $src\t# int" %}
8645 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8646 ins_encode(OpcSErm(dst, src), Con8or32(src));
8647 ins_pipe(ialu_reg);
8648 %}
8649
8650 // Or Register with Memory
8651 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8652 %{
8653 match(Set dst (OrI dst (LoadI src)));
8654 effect(KILL cr);
8655
8656 ins_cost(125);
8657 format %{ "orl $dst, $src\t# int" %}
8658 opcode(0x0B);
8659 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8660 ins_pipe(ialu_reg_mem);
8661 %}
8662
8663 // Or Memory with Register
8664 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8665 %{
8666 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8667 effect(KILL cr);
8668
8669 ins_cost(150);
8670 format %{ "orl $dst, $src\t# int" %}
8671 opcode(0x09); /* Opcode 09 /r */
8672 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8673 ins_pipe(ialu_mem_reg);
8674 %}
8675
8676 // Or Memory with Immediate
8677 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
8678 %{
8679 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8680 effect(KILL cr);
8681
8682 ins_cost(125);
8683 format %{ "orl $dst, $src\t# int" %}
8684 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8685 ins_encode(REX_mem(dst), OpcSE(src),
8686 RM_opc_mem(secondary, dst), Con8or32(src));
8687 ins_pipe(ialu_mem_imm);
8688 %}
8689
8690 // Xor Instructions
8691 // Xor Register with Register
8692 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8693 %{
8694 match(Set dst (XorI dst src));
8695 effect(KILL cr);
8696
8697 format %{ "xorl $dst, $src\t# int" %}
8698 opcode(0x33);
8699 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8700 ins_pipe(ialu_reg_reg);
8701 %}
8702
8703 // Xor Register with Immediate -1
8704 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
8705 match(Set dst (XorI dst imm));
8706
8707 format %{ "not $dst" %}
8708 ins_encode %{
8709 __ notl($dst$$Register);
8710 %}
8711 ins_pipe(ialu_reg);
8712 %}
8713
8714 // Xor Register with Immediate
8715 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8716 %{
8717 match(Set dst (XorI dst src));
8718 effect(KILL cr);
8719
8720 format %{ "xorl $dst, $src\t# int" %}
8721 opcode(0x81, 0x06); /* Opcode 81 /6 id */
8722 ins_encode(OpcSErm(dst, src), Con8or32(src));
8723 ins_pipe(ialu_reg);
8724 %}
8725
8726 // Xor Register with Memory
8727 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8728 %{
8729 match(Set dst (XorI dst (LoadI src)));
8730 effect(KILL cr);
8731
8732 ins_cost(125);
8733 format %{ "xorl $dst, $src\t# int" %}
8734 opcode(0x33);
8735 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8736 ins_pipe(ialu_reg_mem);
8737 %}
8738
8739 // Xor Memory with Register
8740 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8741 %{
8742 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8743 effect(KILL cr);
8744
8745 ins_cost(150);
8746 format %{ "xorl $dst, $src\t# int" %}
8747 opcode(0x31); /* Opcode 31 /r */
8748 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8749 ins_pipe(ialu_mem_reg);
8750 %}
8751
8752 // Xor Memory with Immediate
8753 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
8754 %{
8755 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8756 effect(KILL cr);
8757
8758 ins_cost(125);
8759 format %{ "xorl $dst, $src\t# int" %}
8760 opcode(0x81, 0x6); /* Opcode 81 /6 id */
8761 ins_encode(REX_mem(dst), OpcSE(src),
8762 RM_opc_mem(secondary, dst), Con8or32(src));
8763 ins_pipe(ialu_mem_imm);
8764 %}
8765
8766
8767 // Long Logical Instructions
8768
8769 // And Instructions
8770 // And Register with Register
8771 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8772 %{
8773 match(Set dst (AndL dst src));
8774 effect(KILL cr);
8775
8776 format %{ "andq $dst, $src\t# long" %}
8777 opcode(0x23);
8778 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8779 ins_pipe(ialu_reg_reg);
8780 %}
8781
8782 // And Register with Immediate 255
8783 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
8784 %{
8785 match(Set dst (AndL dst src));
8786
8787 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
8788 opcode(0x0F, 0xB6);
8789 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8790 ins_pipe(ialu_reg);
8791 %}
8792
8793 // And Register with Immediate 65535
8794 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
8795 %{
8796 match(Set dst (AndL dst src));
8797
8798 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
8799 opcode(0x0F, 0xB7);
8800 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8801 ins_pipe(ialu_reg);
8802 %}
8803
8804 // And Register with Immediate
8805 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
8806 %{
8807 match(Set dst (AndL dst src));
8808 effect(KILL cr);
8809
8810 format %{ "andq $dst, $src\t# long" %}
8811 opcode(0x81, 0x04); /* Opcode 81 /4 */
8812 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8813 ins_pipe(ialu_reg);
8814 %}
8815
8816 // And Register with Memory
8817 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8818 %{
8819 match(Set dst (AndL dst (LoadL src)));
8820 effect(KILL cr);
8821
8822 ins_cost(125);
8823 format %{ "andq $dst, $src\t# long" %}
8824 opcode(0x23);
8825 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8826 ins_pipe(ialu_reg_mem);
8827 %}
8828
8829 // And Memory with Register
8830 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8831 %{
8832 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
8833 effect(KILL cr);
8834
8835 ins_cost(150);
8836 format %{ "andq $dst, $src\t# long" %}
8837 opcode(0x21); /* Opcode 21 /r */
8838 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8839 ins_pipe(ialu_mem_reg);
8840 %}
8841
8842 // And Memory with Immediate
8843 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8844 %{
8845 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
8846 effect(KILL cr);
8847
8848 ins_cost(125);
8849 format %{ "andq $dst, $src\t# long" %}
8850 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8851 ins_encode(REX_mem_wide(dst), OpcSE(src),
8852 RM_opc_mem(secondary, dst), Con8or32(src));
8853 ins_pipe(ialu_mem_imm);
8854 %}
8855
8856 // Or Instructions
8857 // Or Register with Register
8858 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8859 %{
8860 match(Set dst (OrL dst src));
8861 effect(KILL cr);
8862
8863 format %{ "orq $dst, $src\t# long" %}
8864 opcode(0x0B);
8865 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8866 ins_pipe(ialu_reg_reg);
8867 %}
8868
8869 // Use any_RegP to match R15 (TLS register) without spilling.
8870 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
8871 match(Set dst (OrL dst (CastP2X src)));
8872 effect(KILL cr);
8873
8874 format %{ "orq $dst, $src\t# long" %}
8875 opcode(0x0B);
8876 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8877 ins_pipe(ialu_reg_reg);
8878 %}
8879
8880
8881 // Or Register with Immediate
8882 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
8883 %{
8884 match(Set dst (OrL dst src));
8885 effect(KILL cr);
8886
8887 format %{ "orq $dst, $src\t# long" %}
8888 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8889 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8890 ins_pipe(ialu_reg);
8891 %}
8892
8893 // Or Register with Memory
8894 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8895 %{
8896 match(Set dst (OrL dst (LoadL src)));
8897 effect(KILL cr);
8898
8899 ins_cost(125);
8900 format %{ "orq $dst, $src\t# long" %}
8901 opcode(0x0B);
8902 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8903 ins_pipe(ialu_reg_mem);
8904 %}
8905
8906 // Or Memory with Register
8907 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8908 %{
8909 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
8910 effect(KILL cr);
8911
8912 ins_cost(150);
8913 format %{ "orq $dst, $src\t# long" %}
8914 opcode(0x09); /* Opcode 09 /r */
8915 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8916 ins_pipe(ialu_mem_reg);
8917 %}
8918
8919 // Or Memory with Immediate
8920 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8921 %{
8922 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
8923 effect(KILL cr);
8924
8925 ins_cost(125);
8926 format %{ "orq $dst, $src\t# long" %}
8927 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8928 ins_encode(REX_mem_wide(dst), OpcSE(src),
8929 RM_opc_mem(secondary, dst), Con8or32(src));
8930 ins_pipe(ialu_mem_imm);
8931 %}
8932
8933 // Xor Instructions
8934 // Xor Register with Register
8935 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8936 %{
8937 match(Set dst (XorL dst src));
8938 effect(KILL cr);
8939
8940 format %{ "xorq $dst, $src\t# long" %}
8941 opcode(0x33);
8942 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8943 ins_pipe(ialu_reg_reg);
8944 %}
8945
8946 // Xor Register with Immediate -1
8947 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
8948 match(Set dst (XorL dst imm));
8949
8950 format %{ "notq $dst" %}
8951 ins_encode %{
8952 __ notq($dst$$Register);
8953 %}
8954 ins_pipe(ialu_reg);
8955 %}
8956
8957 // Xor Register with Immediate
8958 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
8959 %{
8960 match(Set dst (XorL dst src));
8961 effect(KILL cr);
8962
8963 format %{ "xorq $dst, $src\t# long" %}
8964 opcode(0x81, 0x06); /* Opcode 81 /6 id */
8965 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8966 ins_pipe(ialu_reg);
8967 %}
8968
8969 // Xor Register with Memory
8970 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8971 %{
8972 match(Set dst (XorL dst (LoadL src)));
8973 effect(KILL cr);
8974
8975 ins_cost(125);
8976 format %{ "xorq $dst, $src\t# long" %}
8977 opcode(0x33);
8978 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8979 ins_pipe(ialu_reg_mem);
8980 %}
8981
8982 // Xor Memory with Register
8983 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8984 %{
8985 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
8986 effect(KILL cr);
8987
8988 ins_cost(150);
8989 format %{ "xorq $dst, $src\t# long" %}
8990 opcode(0x31); /* Opcode 31 /r */
8991 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8992 ins_pipe(ialu_mem_reg);
8993 %}
8994
8995 // Xor Memory with Immediate
8996 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8997 %{
8998 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
8999 effect(KILL cr);
9000
9001 ins_cost(125);
9002 format %{ "xorq $dst, $src\t# long" %}
9003 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9004 ins_encode(REX_mem_wide(dst), OpcSE(src),
9005 RM_opc_mem(secondary, dst), Con8or32(src));
9006 ins_pipe(ialu_mem_imm);
9007 %}
9008
9009 // Convert Int to Boolean
9010 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9011 %{
9012 match(Set dst (Conv2B src));
9013 effect(KILL cr);
9014
9015 format %{ "testl $src, $src\t# ci2b\n\t"
9016 "setnz $dst\n\t"
9017 "movzbl $dst, $dst" %}
9018 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9019 setNZ_reg(dst),
9020 REX_reg_breg(dst, dst), // movzbl
9021 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9022 ins_pipe(pipe_slow); // XXX
9023 %}
9024
9025 // Convert Pointer to Boolean
9026 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9027 %{
9028 match(Set dst (Conv2B src));
9029 effect(KILL cr);
9030
9031 format %{ "testq $src, $src\t# cp2b\n\t"
9032 "setnz $dst\n\t"
9033 "movzbl $dst, $dst" %}
9034 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9035 setNZ_reg(dst),
9036 REX_reg_breg(dst, dst), // movzbl
9037 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9038 ins_pipe(pipe_slow); // XXX
9039 %}
9040
9041 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9042 %{
9043 match(Set dst (CmpLTMask p q));
9044 effect(KILL cr);
9045
9046 ins_cost(400);
9047 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9048 "setlt $dst\n\t"
9049 "movzbl $dst, $dst\n\t"
9050 "negl $dst" %}
9051 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9052 setLT_reg(dst),
9053 REX_reg_breg(dst, dst), // movzbl
9054 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9055 neg_reg(dst));
9056 ins_pipe(pipe_slow);
9057 %}
9058
9059 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9060 %{
9061 match(Set dst (CmpLTMask dst zero));
9062 effect(KILL cr);
9063
9064 ins_cost(100);
9065 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9066 ins_encode %{
9067 __ sarl($dst$$Register, 31);
9068 %}
9069 ins_pipe(ialu_reg);
9070 %}
9071
9072 /* Better to save a register than avoid a branch */
9073 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9074 %{
9075 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9076 effect(KILL cr);
9077 ins_cost(300);
9078 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9079 "jge done\n\t"
9080 "addl $p,$y\n"
9081 "done: " %}
9082 ins_encode %{
9083 Register Rp = $p$$Register;
9084 Register Rq = $q$$Register;
9085 Register Ry = $y$$Register;
9086 Label done;
9087 __ subl(Rp, Rq);
9088 __ jccb(Assembler::greaterEqual, done);
9089 __ addl(Rp, Ry);
9090 __ bind(done);
9091 %}
9092 ins_pipe(pipe_cmplt);
9093 %}
9094
9095 /* Better to save a register than avoid a branch */
9096 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9097 %{
9098 match(Set y (AndI (CmpLTMask p q) y));
9099 effect(KILL cr);
9100
9101 ins_cost(300);
9102
9103 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9104 "jlt done\n\t"
9105 "xorl $y, $y\n"
9106 "done: " %}
9107 ins_encode %{
9108 Register Rp = $p$$Register;
9109 Register Rq = $q$$Register;
9110 Register Ry = $y$$Register;
9111 Label done;
9112 __ cmpl(Rp, Rq);
9113 __ jccb(Assembler::less, done);
9114 __ xorl(Ry, Ry);
9115 __ bind(done);
9116 %}
9117 ins_pipe(pipe_cmplt);
9118 %}
9119
9120
9121 //---------- FP Instructions------------------------------------------------
9122
9123 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9124 %{
9125 match(Set cr (CmpF src1 src2));
9126
9127 ins_cost(145);
9128 format %{ "ucomiss $src1, $src2\n\t"
9129 "jnp,s exit\n\t"
9130 "pushfq\t# saw NaN, set CF\n\t"
9131 "andq [rsp], #0xffffff2b\n\t"
9132 "popfq\n"
9133 "exit:" %}
9134 ins_encode %{
9135 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9136 emit_cmpfp_fixup(_masm);
9137 %}
9138 ins_pipe(pipe_slow);
9139 %}
9140
9141 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9142 match(Set cr (CmpF src1 src2));
9143
9144 ins_cost(100);
9145 format %{ "ucomiss $src1, $src2" %}
9146 ins_encode %{
9147 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9148 %}
9149 ins_pipe(pipe_slow);
9150 %}
9151
9152 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9153 %{
9154 match(Set cr (CmpF src1 (LoadF src2)));
9155
9156 ins_cost(145);
9157 format %{ "ucomiss $src1, $src2\n\t"
9158 "jnp,s exit\n\t"
9159 "pushfq\t# saw NaN, set CF\n\t"
9160 "andq [rsp], #0xffffff2b\n\t"
9161 "popfq\n"
9162 "exit:" %}
9163 ins_encode %{
9164 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9165 emit_cmpfp_fixup(_masm);
9166 %}
9167 ins_pipe(pipe_slow);
9168 %}
9169
9170 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9171 match(Set cr (CmpF src1 (LoadF src2)));
9172
9173 ins_cost(100);
9174 format %{ "ucomiss $src1, $src2" %}
9175 ins_encode %{
9176 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9177 %}
9178 ins_pipe(pipe_slow);
9179 %}
9180
9181 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9182 match(Set cr (CmpF src con));
9183
9184 ins_cost(145);
9185 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9186 "jnp,s exit\n\t"
9187 "pushfq\t# saw NaN, set CF\n\t"
9188 "andq [rsp], #0xffffff2b\n\t"
9189 "popfq\n"
9190 "exit:" %}
9191 ins_encode %{
9192 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9193 emit_cmpfp_fixup(_masm);
9194 %}
9195 ins_pipe(pipe_slow);
9196 %}
9197
9198 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9199 match(Set cr (CmpF src con));
9200 ins_cost(100);
9201 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9202 ins_encode %{
9203 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9204 %}
9205 ins_pipe(pipe_slow);
9206 %}
9207
9208 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9209 %{
9210 match(Set cr (CmpD src1 src2));
9211
9212 ins_cost(145);
9213 format %{ "ucomisd $src1, $src2\n\t"
9214 "jnp,s exit\n\t"
9215 "pushfq\t# saw NaN, set CF\n\t"
9216 "andq [rsp], #0xffffff2b\n\t"
9217 "popfq\n"
9218 "exit:" %}
9219 ins_encode %{
9220 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9221 emit_cmpfp_fixup(_masm);
9222 %}
9223 ins_pipe(pipe_slow);
9224 %}
9225
9226 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9227 match(Set cr (CmpD src1 src2));
9228
9229 ins_cost(100);
9230 format %{ "ucomisd $src1, $src2 test" %}
9231 ins_encode %{
9232 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9233 %}
9234 ins_pipe(pipe_slow);
9235 %}
9236
9237 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9238 %{
9239 match(Set cr (CmpD src1 (LoadD src2)));
9240
9241 ins_cost(145);
9242 format %{ "ucomisd $src1, $src2\n\t"
9243 "jnp,s exit\n\t"
9244 "pushfq\t# saw NaN, set CF\n\t"
9245 "andq [rsp], #0xffffff2b\n\t"
9246 "popfq\n"
9247 "exit:" %}
9248 ins_encode %{
9249 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9250 emit_cmpfp_fixup(_masm);
9251 %}
9252 ins_pipe(pipe_slow);
9253 %}
9254
9255 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9256 match(Set cr (CmpD src1 (LoadD src2)));
9257
9258 ins_cost(100);
9259 format %{ "ucomisd $src1, $src2" %}
9260 ins_encode %{
9261 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9262 %}
9263 ins_pipe(pipe_slow);
9264 %}
9265
9266 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9267 match(Set cr (CmpD src con));
9268
9269 ins_cost(145);
9270 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9271 "jnp,s exit\n\t"
9272 "pushfq\t# saw NaN, set CF\n\t"
9273 "andq [rsp], #0xffffff2b\n\t"
9274 "popfq\n"
9275 "exit:" %}
9276 ins_encode %{
9277 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9278 emit_cmpfp_fixup(_masm);
9279 %}
9280 ins_pipe(pipe_slow);
9281 %}
9282
9283 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9284 match(Set cr (CmpD src con));
9285 ins_cost(100);
9286 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9287 ins_encode %{
9288 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9289 %}
9290 ins_pipe(pipe_slow);
9291 %}
9292
9293 // Compare into -1,0,1
9294 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9295 %{
9296 match(Set dst (CmpF3 src1 src2));
9297 effect(KILL cr);
9298
9299 ins_cost(275);
9300 format %{ "ucomiss $src1, $src2\n\t"
9301 "movl $dst, #-1\n\t"
9302 "jp,s done\n\t"
9303 "jb,s done\n\t"
9304 "setne $dst\n\t"
9305 "movzbl $dst, $dst\n"
9306 "done:" %}
9307 ins_encode %{
9308 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9309 emit_cmpfp3(_masm, $dst$$Register);
9310 %}
9311 ins_pipe(pipe_slow);
9312 %}
9313
9314 // Compare into -1,0,1
9315 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9316 %{
9317 match(Set dst (CmpF3 src1 (LoadF src2)));
9318 effect(KILL cr);
9319
9320 ins_cost(275);
9321 format %{ "ucomiss $src1, $src2\n\t"
9322 "movl $dst, #-1\n\t"
9323 "jp,s done\n\t"
9324 "jb,s done\n\t"
9325 "setne $dst\n\t"
9326 "movzbl $dst, $dst\n"
9327 "done:" %}
9328 ins_encode %{
9329 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9330 emit_cmpfp3(_masm, $dst$$Register);
9331 %}
9332 ins_pipe(pipe_slow);
9333 %}
9334
9335 // Compare into -1,0,1
9336 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9337 match(Set dst (CmpF3 src con));
9338 effect(KILL cr);
9339
9340 ins_cost(275);
9341 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9342 "movl $dst, #-1\n\t"
9343 "jp,s done\n\t"
9344 "jb,s done\n\t"
9345 "setne $dst\n\t"
9346 "movzbl $dst, $dst\n"
9347 "done:" %}
9348 ins_encode %{
9349 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9350 emit_cmpfp3(_masm, $dst$$Register);
9351 %}
9352 ins_pipe(pipe_slow);
9353 %}
9354
9355 // Compare into -1,0,1
9356 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9357 %{
9358 match(Set dst (CmpD3 src1 src2));
9359 effect(KILL cr);
9360
9361 ins_cost(275);
9362 format %{ "ucomisd $src1, $src2\n\t"
9363 "movl $dst, #-1\n\t"
9364 "jp,s done\n\t"
9365 "jb,s done\n\t"
9366 "setne $dst\n\t"
9367 "movzbl $dst, $dst\n"
9368 "done:" %}
9369 ins_encode %{
9370 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9371 emit_cmpfp3(_masm, $dst$$Register);
9372 %}
9373 ins_pipe(pipe_slow);
9374 %}
9375
9376 // Compare into -1,0,1
9377 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9378 %{
9379 match(Set dst (CmpD3 src1 (LoadD src2)));
9380 effect(KILL cr);
9381
9382 ins_cost(275);
9383 format %{ "ucomisd $src1, $src2\n\t"
9384 "movl $dst, #-1\n\t"
9385 "jp,s done\n\t"
9386 "jb,s done\n\t"
9387 "setne $dst\n\t"
9388 "movzbl $dst, $dst\n"
9389 "done:" %}
9390 ins_encode %{
9391 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9392 emit_cmpfp3(_masm, $dst$$Register);
9393 %}
9394 ins_pipe(pipe_slow);
9395 %}
9396
9397 // Compare into -1,0,1
9398 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9399 match(Set dst (CmpD3 src con));
9400 effect(KILL cr);
9401
9402 ins_cost(275);
9403 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9404 "movl $dst, #-1\n\t"
9405 "jp,s done\n\t"
9406 "jb,s done\n\t"
9407 "setne $dst\n\t"
9408 "movzbl $dst, $dst\n"
9409 "done:" %}
9410 ins_encode %{
9411 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9412 emit_cmpfp3(_masm, $dst$$Register);
9413 %}
9414 ins_pipe(pipe_slow);
9415 %}
9416
9417 // -----------Trig and Trancendental Instructions------------------------------
9418 instruct cosD_reg(regD dst) %{
9419 match(Set dst (CosD dst));
9420
9421 format %{ "dcos $dst\n\t" %}
9422 opcode(0xD9, 0xFF);
9423 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9424 ins_pipe( pipe_slow );
9425 %}
9426
9427 instruct sinD_reg(regD dst) %{
9428 match(Set dst (SinD dst));
9429
9430 format %{ "dsin $dst\n\t" %}
9431 opcode(0xD9, 0xFE);
9432 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9433 ins_pipe( pipe_slow );
9434 %}
9435
9436 instruct tanD_reg(regD dst) %{
9437 match(Set dst (TanD dst));
9438
9439 format %{ "dtan $dst\n\t" %}
9440 ins_encode( Push_SrcXD(dst),
9441 Opcode(0xD9), Opcode(0xF2), //fptan
9442 Opcode(0xDD), Opcode(0xD8), //fstp st
9443 Push_ResultXD(dst) );
9444 ins_pipe( pipe_slow );
9445 %}
9446
9447 instruct log10D_reg(regD dst) %{
9448 // The source and result Double operands in XMM registers
9449 match(Set dst (Log10D dst));
9450 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9451 // fyl2x ; compute log_10(2) * log_2(x)
9452 format %{ "fldlg2\t\t\t#Log10\n\t"
9453 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9454 %}
9455 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9456 Push_SrcXD(dst),
9457 Opcode(0xD9), Opcode(0xF1), // fyl2x
9458 Push_ResultXD(dst));
9459
9460 ins_pipe( pipe_slow );
9461 %}
9462
9463 instruct logD_reg(regD dst) %{
9464 // The source and result Double operands in XMM registers
9465 match(Set dst (LogD dst));
9466 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9467 // fyl2x ; compute log_e(2) * log_2(x)
9468 format %{ "fldln2\t\t\t#Log_e\n\t"
9469 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9470 %}
9471 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9472 Push_SrcXD(dst),
9473 Opcode(0xD9), Opcode(0xF1), // fyl2x
9474 Push_ResultXD(dst));
9475 ins_pipe( pipe_slow );
9476 %}
9477
9478 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9479 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9480 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9481 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9482 ins_encode %{
9483 __ subptr(rsp, 8);
9484 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9485 __ fld_d(Address(rsp, 0));
9486 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9487 __ fld_d(Address(rsp, 0));
9488 __ fast_pow();
9489 __ fstp_d(Address(rsp, 0));
9490 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9491 __ addptr(rsp, 8);
9492 %}
9493 ins_pipe( pipe_slow );
9494 %}
9495
9496 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9497 match(Set dst (ExpD src));
9498 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9499 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9500 ins_encode %{
9501 __ subptr(rsp, 8);
9502 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9503 __ fld_d(Address(rsp, 0));
9504 __ fast_exp();
9505 __ fstp_d(Address(rsp, 0));
9506 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9507 __ addptr(rsp, 8);
9508 %}
9509 ins_pipe( pipe_slow );
9510 %}
9511
9512 //----------Arithmetic Conversion Instructions---------------------------------
9513
9514 instruct roundFloat_nop(regF dst)
9515 %{
9516 match(Set dst (RoundFloat dst));
9517
9518 ins_cost(0);
9519 ins_encode();
9520 ins_pipe(empty);
9521 %}
9522
9523 instruct roundDouble_nop(regD dst)
9524 %{
9525 match(Set dst (RoundDouble dst));
9526
9527 ins_cost(0);
9528 ins_encode();
9529 ins_pipe(empty);
9530 %}
9531
9532 instruct convF2D_reg_reg(regD dst, regF src)
9533 %{
9534 match(Set dst (ConvF2D src));
9535
9536 format %{ "cvtss2sd $dst, $src" %}
9537 ins_encode %{
9538 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9539 %}
9540 ins_pipe(pipe_slow); // XXX
9541 %}
9542
9543 instruct convF2D_reg_mem(regD dst, memory src)
9544 %{
9545 match(Set dst (ConvF2D (LoadF src)));
9546
9547 format %{ "cvtss2sd $dst, $src" %}
9548 ins_encode %{
9549 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9550 %}
9551 ins_pipe(pipe_slow); // XXX
9552 %}
9553
9554 instruct convD2F_reg_reg(regF dst, regD src)
9555 %{
9556 match(Set dst (ConvD2F src));
9557
9558 format %{ "cvtsd2ss $dst, $src" %}
9559 ins_encode %{
9560 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9561 %}
9562 ins_pipe(pipe_slow); // XXX
9563 %}
9564
9565 instruct convD2F_reg_mem(regF dst, memory src)
9566 %{
9567 match(Set dst (ConvD2F (LoadD src)));
9568
9569 format %{ "cvtsd2ss $dst, $src" %}
9570 ins_encode %{
9571 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9572 %}
9573 ins_pipe(pipe_slow); // XXX
9574 %}
9575
9576 // XXX do mem variants
9577 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9578 %{
9579 match(Set dst (ConvF2I src));
9580 effect(KILL cr);
9581
9582 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
9583 "cmpl $dst, #0x80000000\n\t"
9584 "jne,s done\n\t"
9585 "subq rsp, #8\n\t"
9586 "movss [rsp], $src\n\t"
9587 "call f2i_fixup\n\t"
9588 "popq $dst\n"
9589 "done: "%}
9590 ins_encode %{
9591 Label done;
9592 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
9593 __ cmpl($dst$$Register, 0x80000000);
9594 __ jccb(Assembler::notEqual, done);
9595 __ subptr(rsp, 8);
9596 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9597 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9598 __ pop($dst$$Register);
9599 __ bind(done);
9600 %}
9601 ins_pipe(pipe_slow);
9602 %}
9603
9604 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
9605 %{
9606 match(Set dst (ConvF2L src));
9607 effect(KILL cr);
9608
9609 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
9610 "cmpq $dst, [0x8000000000000000]\n\t"
9611 "jne,s done\n\t"
9612 "subq rsp, #8\n\t"
9613 "movss [rsp], $src\n\t"
9614 "call f2l_fixup\n\t"
9615 "popq $dst\n"
9616 "done: "%}
9617 ins_encode %{
9618 Label done;
9619 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
9620 __ cmp64($dst$$Register,
9621 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9622 __ jccb(Assembler::notEqual, done);
9623 __ subptr(rsp, 8);
9624 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9625 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9626 __ pop($dst$$Register);
9627 __ bind(done);
9628 %}
9629 ins_pipe(pipe_slow);
9630 %}
9631
9632 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
9633 %{
9634 match(Set dst (ConvD2I src));
9635 effect(KILL cr);
9636
9637 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
9638 "cmpl $dst, #0x80000000\n\t"
9639 "jne,s done\n\t"
9640 "subq rsp, #8\n\t"
9641 "movsd [rsp], $src\n\t"
9642 "call d2i_fixup\n\t"
9643 "popq $dst\n"
9644 "done: "%}
9645 ins_encode %{
9646 Label done;
9647 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
9648 __ cmpl($dst$$Register, 0x80000000);
9649 __ jccb(Assembler::notEqual, done);
9650 __ subptr(rsp, 8);
9651 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9652 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9653 __ pop($dst$$Register);
9654 __ bind(done);
9655 %}
9656 ins_pipe(pipe_slow);
9657 %}
9658
9659 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
9660 %{
9661 match(Set dst (ConvD2L src));
9662 effect(KILL cr);
9663
9664 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
9665 "cmpq $dst, [0x8000000000000000]\n\t"
9666 "jne,s done\n\t"
9667 "subq rsp, #8\n\t"
9668 "movsd [rsp], $src\n\t"
9669 "call d2l_fixup\n\t"
9670 "popq $dst\n"
9671 "done: "%}
9672 ins_encode %{
9673 Label done;
9674 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
9675 __ cmp64($dst$$Register,
9676 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9677 __ jccb(Assembler::notEqual, done);
9678 __ subptr(rsp, 8);
9679 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9680 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9681 __ pop($dst$$Register);
9682 __ bind(done);
9683 %}
9684 ins_pipe(pipe_slow);
9685 %}
9686
9687 instruct convI2F_reg_reg(regF dst, rRegI src)
9688 %{
9689 predicate(!UseXmmI2F);
9690 match(Set dst (ConvI2F src));
9691
9692 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
9693 ins_encode %{
9694 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
9695 %}
9696 ins_pipe(pipe_slow); // XXX
9697 %}
9698
9699 instruct convI2F_reg_mem(regF dst, memory src)
9700 %{
9701 match(Set dst (ConvI2F (LoadI src)));
9702
9703 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
9704 ins_encode %{
9705 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
9706 %}
9707 ins_pipe(pipe_slow); // XXX
9708 %}
9709
9710 instruct convI2D_reg_reg(regD dst, rRegI src)
9711 %{
9712 predicate(!UseXmmI2D);
9713 match(Set dst (ConvI2D src));
9714
9715 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
9716 ins_encode %{
9717 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
9718 %}
9719 ins_pipe(pipe_slow); // XXX
9720 %}
9721
9722 instruct convI2D_reg_mem(regD dst, memory src)
9723 %{
9724 match(Set dst (ConvI2D (LoadI src)));
9725
9726 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
9727 ins_encode %{
9728 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
9729 %}
9730 ins_pipe(pipe_slow); // XXX
9731 %}
9732
9733 instruct convXI2F_reg(regF dst, rRegI src)
9734 %{
9735 predicate(UseXmmI2F);
9736 match(Set dst (ConvI2F src));
9737
9738 format %{ "movdl $dst, $src\n\t"
9739 "cvtdq2psl $dst, $dst\t# i2f" %}
9740 ins_encode %{
9741 __ movdl($dst$$XMMRegister, $src$$Register);
9742 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
9743 %}
9744 ins_pipe(pipe_slow); // XXX
9745 %}
9746
9747 instruct convXI2D_reg(regD dst, rRegI src)
9748 %{
9749 predicate(UseXmmI2D);
9750 match(Set dst (ConvI2D src));
9751
9752 format %{ "movdl $dst, $src\n\t"
9753 "cvtdq2pdl $dst, $dst\t# i2d" %}
9754 ins_encode %{
9755 __ movdl($dst$$XMMRegister, $src$$Register);
9756 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
9757 %}
9758 ins_pipe(pipe_slow); // XXX
9759 %}
9760
9761 instruct convL2F_reg_reg(regF dst, rRegL src)
9762 %{
9763 match(Set dst (ConvL2F src));
9764
9765 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
9766 ins_encode %{
9767 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
9768 %}
9769 ins_pipe(pipe_slow); // XXX
9770 %}
9771
9772 instruct convL2F_reg_mem(regF dst, memory src)
9773 %{
9774 match(Set dst (ConvL2F (LoadL src)));
9775
9776 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
9777 ins_encode %{
9778 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
9779 %}
9780 ins_pipe(pipe_slow); // XXX
9781 %}
9782
9783 instruct convL2D_reg_reg(regD dst, rRegL src)
9784 %{
9785 match(Set dst (ConvL2D src));
9786
9787 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
9788 ins_encode %{
9789 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
9790 %}
9791 ins_pipe(pipe_slow); // XXX
9792 %}
9793
9794 instruct convL2D_reg_mem(regD dst, memory src)
9795 %{
9796 match(Set dst (ConvL2D (LoadL src)));
9797
9798 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
9799 ins_encode %{
9800 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
9801 %}
9802 ins_pipe(pipe_slow); // XXX
9803 %}
9804
9805 instruct convI2L_reg_reg(rRegL dst, rRegI src)
9806 %{
9807 match(Set dst (ConvI2L src));
9808
9809 ins_cost(125);
9810 format %{ "movslq $dst, $src\t# i2l" %}
9811 ins_encode %{
9812 __ movslq($dst$$Register, $src$$Register);
9813 %}
9814 ins_pipe(ialu_reg_reg);
9815 %}
9816
9817 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
9818 // %{
9819 // match(Set dst (ConvI2L src));
9820 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
9821 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
9822 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
9823 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
9824 // ((const TypeNode*) n)->type()->is_long()->_lo ==
9825 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
9826
9827 // format %{ "movl $dst, $src\t# unsigned i2l" %}
9828 // ins_encode(enc_copy(dst, src));
9829 // // opcode(0x63); // needs REX.W
9830 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
9831 // ins_pipe(ialu_reg_reg);
9832 // %}
9833
9834 // Zero-extend convert int to long
9835 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
9836 %{
9837 match(Set dst (AndL (ConvI2L src) mask));
9838
9839 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
9840 ins_encode %{
9841 if ($dst$$reg != $src$$reg) {
9842 __ movl($dst$$Register, $src$$Register);
9843 }
9844 %}
9845 ins_pipe(ialu_reg_reg);
9846 %}
9847
9848 // Zero-extend convert int to long
9849 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
9850 %{
9851 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
9852
9853 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
9854 ins_encode %{
9855 __ movl($dst$$Register, $src$$Address);
9856 %}
9857 ins_pipe(ialu_reg_mem);
9858 %}
9859
9860 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
9861 %{
9862 match(Set dst (AndL src mask));
9863
9864 format %{ "movl $dst, $src\t# zero-extend long" %}
9865 ins_encode %{
9866 __ movl($dst$$Register, $src$$Register);
9867 %}
9868 ins_pipe(ialu_reg_reg);
9869 %}
9870
9871 instruct convL2I_reg_reg(rRegI dst, rRegL src)
9872 %{
9873 match(Set dst (ConvL2I src));
9874
9875 format %{ "movl $dst, $src\t# l2i" %}
9876 ins_encode %{
9877 __ movl($dst$$Register, $src$$Register);
9878 %}
9879 ins_pipe(ialu_reg_reg);
9880 %}
9881
9882
9883 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
9884 match(Set dst (MoveF2I src));
9885 effect(DEF dst, USE src);
9886
9887 ins_cost(125);
9888 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
9889 ins_encode %{
9890 __ movl($dst$$Register, Address(rsp, $src$$disp));
9891 %}
9892 ins_pipe(ialu_reg_mem);
9893 %}
9894
9895 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
9896 match(Set dst (MoveI2F src));
9897 effect(DEF dst, USE src);
9898
9899 ins_cost(125);
9900 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
9901 ins_encode %{
9902 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
9903 %}
9904 ins_pipe(pipe_slow);
9905 %}
9906
9907 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
9908 match(Set dst (MoveD2L src));
9909 effect(DEF dst, USE src);
9910
9911 ins_cost(125);
9912 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
9913 ins_encode %{
9914 __ movq($dst$$Register, Address(rsp, $src$$disp));
9915 %}
9916 ins_pipe(ialu_reg_mem);
9917 %}
9918
9919 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
9920 predicate(!UseXmmLoadAndClearUpper);
9921 match(Set dst (MoveL2D src));
9922 effect(DEF dst, USE src);
9923
9924 ins_cost(125);
9925 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
9926 ins_encode %{
9927 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
9928 %}
9929 ins_pipe(pipe_slow);
9930 %}
9931
9932 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
9933 predicate(UseXmmLoadAndClearUpper);
9934 match(Set dst (MoveL2D src));
9935 effect(DEF dst, USE src);
9936
9937 ins_cost(125);
9938 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
9939 ins_encode %{
9940 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
9941 %}
9942 ins_pipe(pipe_slow);
9943 %}
9944
9945
9946 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
9947 match(Set dst (MoveF2I src));
9948 effect(DEF dst, USE src);
9949
9950 ins_cost(95); // XXX
9951 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
9952 ins_encode %{
9953 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
9954 %}
9955 ins_pipe(pipe_slow);
9956 %}
9957
9958 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
9959 match(Set dst (MoveI2F src));
9960 effect(DEF dst, USE src);
9961
9962 ins_cost(100);
9963 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
9964 ins_encode %{
9965 __ movl(Address(rsp, $dst$$disp), $src$$Register);
9966 %}
9967 ins_pipe( ialu_mem_reg );
9968 %}
9969
9970 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
9971 match(Set dst (MoveD2L src));
9972 effect(DEF dst, USE src);
9973
9974 ins_cost(95); // XXX
9975 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
9976 ins_encode %{
9977 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
9978 %}
9979 ins_pipe(pipe_slow);
9980 %}
9981
9982 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
9983 match(Set dst (MoveL2D src));
9984 effect(DEF dst, USE src);
9985
9986 ins_cost(100);
9987 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
9988 ins_encode %{
9989 __ movq(Address(rsp, $dst$$disp), $src$$Register);
9990 %}
9991 ins_pipe(ialu_mem_reg);
9992 %}
9993
9994 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
9995 match(Set dst (MoveF2I src));
9996 effect(DEF dst, USE src);
9997 ins_cost(85);
9998 format %{ "movd $dst,$src\t# MoveF2I" %}
9999 ins_encode %{
10000 __ movdl($dst$$Register, $src$$XMMRegister);
10001 %}
10002 ins_pipe( pipe_slow );
10003 %}
10004
10005 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10006 match(Set dst (MoveD2L src));
10007 effect(DEF dst, USE src);
10008 ins_cost(85);
10009 format %{ "movd $dst,$src\t# MoveD2L" %}
10010 ins_encode %{
10011 __ movdq($dst$$Register, $src$$XMMRegister);
10012 %}
10013 ins_pipe( pipe_slow );
10014 %}
10015
10016 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10017 match(Set dst (MoveI2F src));
10018 effect(DEF dst, USE src);
10019 ins_cost(100);
10020 format %{ "movd $dst,$src\t# MoveI2F" %}
10021 ins_encode %{
10022 __ movdl($dst$$XMMRegister, $src$$Register);
10023 %}
10024 ins_pipe( pipe_slow );
10025 %}
10026
10027 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10028 match(Set dst (MoveL2D src));
10029 effect(DEF dst, USE src);
10030 ins_cost(100);
10031 format %{ "movd $dst,$src\t# MoveL2D" %}
10032 ins_encode %{
10033 __ movdq($dst$$XMMRegister, $src$$Register);
10034 %}
10035 ins_pipe( pipe_slow );
10036 %}
10037
10038
10039 // =======================================================================
10040 // fast clearing of an array
10041 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10042 rFlagsReg cr)
10043 %{
10044 predicate(!UseFastStosb);
10045 match(Set dummy (ClearArray cnt base));
10046 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10047
10048 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10049 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10050 ins_encode %{
10051 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10052 %}
10053 ins_pipe(pipe_slow);
10054 %}
10055
10056 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10057 rFlagsReg cr)
10058 %{
10059 predicate(UseFastStosb);
10060 match(Set dummy (ClearArray cnt base));
10061 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10062 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10063 "shlq rcx,3\t# Convert doublewords to bytes\n\t"
10064 "rep stosb\t# Store rax to *rdi++ while rcx--" %}
10065 ins_encode %{
10066 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10067 %}
10068 ins_pipe( pipe_slow );
10069 %}
10070
10071 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10072 rax_RegI result, regD tmp1, rFlagsReg cr)
10073 %{
10074 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10075 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10076
10077 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10078 ins_encode %{
10079 __ string_compare($str1$$Register, $str2$$Register,
10080 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10081 $tmp1$$XMMRegister);
10082 %}
10083 ins_pipe( pipe_slow );
10084 %}
10085
10086 // fast search of substring with known size.
10087 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10088 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10089 %{
10090 predicate(UseSSE42Intrinsics);
10091 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10092 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10093
10094 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10095 ins_encode %{
10096 int icnt2 = (int)$int_cnt2$$constant;
10097 if (icnt2 >= 8) {
10098 // IndexOf for constant substrings with size >= 8 elements
10099 // which don't need to be loaded through stack.
10100 __ string_indexofC8($str1$$Register, $str2$$Register,
10101 $cnt1$$Register, $cnt2$$Register,
10102 icnt2, $result$$Register,
10103 $vec$$XMMRegister, $tmp$$Register);
10104 } else {
10105 // Small strings are loaded through stack if they cross page boundary.
10106 __ string_indexof($str1$$Register, $str2$$Register,
10107 $cnt1$$Register, $cnt2$$Register,
10108 icnt2, $result$$Register,
10109 $vec$$XMMRegister, $tmp$$Register);
10110 }
10111 %}
10112 ins_pipe( pipe_slow );
10113 %}
10114
10115 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10116 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10117 %{
10118 predicate(UseSSE42Intrinsics);
10119 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10120 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10121
10122 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10123 ins_encode %{
10124 __ string_indexof($str1$$Register, $str2$$Register,
10125 $cnt1$$Register, $cnt2$$Register,
10126 (-1), $result$$Register,
10127 $vec$$XMMRegister, $tmp$$Register);
10128 %}
10129 ins_pipe( pipe_slow );
10130 %}
10131
10132 // fast string equals
10133 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10134 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10135 %{
10136 match(Set result (StrEquals (Binary str1 str2) cnt));
10137 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10138
10139 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10140 ins_encode %{
10141 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10142 $cnt$$Register, $result$$Register, $tmp3$$Register,
10143 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10144 %}
10145 ins_pipe( pipe_slow );
10146 %}
10147
10148 // fast array equals
10149 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10150 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10151 %{
10152 match(Set result (AryEq ary1 ary2));
10153 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10154 //ins_cost(300);
10155
10156 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10157 ins_encode %{
10158 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10159 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10160 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10161 %}
10162 ins_pipe( pipe_slow );
10163 %}
10164
10165 // encode char[] to byte[] in ISO_8859_1
10166 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10167 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10168 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10169 match(Set result (EncodeISOArray src (Binary dst len)));
10170 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10171
10172 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10173 ins_encode %{
10174 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10175 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10176 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10177 %}
10178 ins_pipe( pipe_slow );
10179 %}
10180
10181 //----------Overflow Math Instructions-----------------------------------------
10182
10183 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10184 %{
10185 match(Set cr (OverflowAddI op1 op2));
10186 effect(DEF cr, USE_KILL op1, USE op2);
10187
10188 format %{ "addl $op1, $op2\t# overflow check int" %}
10189
10190 ins_encode %{
10191 __ addl($op1$$Register, $op2$$Register);
10192 %}
10193 ins_pipe(ialu_reg_reg);
10194 %}
10195
10196 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10197 %{
10198 match(Set cr (OverflowAddI op1 op2));
10199 effect(DEF cr, USE_KILL op1, USE op2);
10200
10201 format %{ "addl $op1, $op2\t# overflow check int" %}
10202
10203 ins_encode %{
10204 __ addl($op1$$Register, $op2$$constant);
10205 %}
10206 ins_pipe(ialu_reg_reg);
10207 %}
10208
10209 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10210 %{
10211 match(Set cr (OverflowAddL op1 op2));
10212 effect(DEF cr, USE_KILL op1, USE op2);
10213
10214 format %{ "addq $op1, $op2\t# overflow check long" %}
10215 ins_encode %{
10216 __ addq($op1$$Register, $op2$$Register);
10217 %}
10218 ins_pipe(ialu_reg_reg);
10219 %}
10220
10221 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10222 %{
10223 match(Set cr (OverflowAddL op1 op2));
10224 effect(DEF cr, USE_KILL op1, USE op2);
10225
10226 format %{ "addq $op1, $op2\t# overflow check long" %}
10227 ins_encode %{
10228 __ addq($op1$$Register, $op2$$constant);
10229 %}
10230 ins_pipe(ialu_reg_reg);
10231 %}
10232
10233 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10234 %{
10235 match(Set cr (OverflowSubI op1 op2));
10236
10237 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10238 ins_encode %{
10239 __ cmpl($op1$$Register, $op2$$Register);
10240 %}
10241 ins_pipe(ialu_reg_reg);
10242 %}
10243
10244 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10245 %{
10246 match(Set cr (OverflowSubI op1 op2));
10247
10248 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10249 ins_encode %{
10250 __ cmpl($op1$$Register, $op2$$constant);
10251 %}
10252 ins_pipe(ialu_reg_reg);
10253 %}
10254
10255 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10256 %{
10257 match(Set cr (OverflowSubL op1 op2));
10258
10259 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10260 ins_encode %{
10261 __ cmpq($op1$$Register, $op2$$Register);
10262 %}
10263 ins_pipe(ialu_reg_reg);
10264 %}
10265
10266 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10267 %{
10268 match(Set cr (OverflowSubL op1 op2));
10269
10270 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10271 ins_encode %{
10272 __ cmpq($op1$$Register, $op2$$constant);
10273 %}
10274 ins_pipe(ialu_reg_reg);
10275 %}
10276
10277 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10278 %{
10279 match(Set cr (OverflowSubI zero op2));
10280 effect(DEF cr, USE_KILL op2);
10281
10282 format %{ "negl $op2\t# overflow check int" %}
10283 ins_encode %{
10284 __ negl($op2$$Register);
10285 %}
10286 ins_pipe(ialu_reg_reg);
10287 %}
10288
10289 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10290 %{
10291 match(Set cr (OverflowSubL zero op2));
10292 effect(DEF cr, USE_KILL op2);
10293
10294 format %{ "negq $op2\t# overflow check long" %}
10295 ins_encode %{
10296 __ negq($op2$$Register);
10297 %}
10298 ins_pipe(ialu_reg_reg);
10299 %}
10300
10301 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10302 %{
10303 match(Set cr (OverflowMulI op1 op2));
10304 effect(DEF cr, USE_KILL op1, USE op2);
10305
10306 format %{ "imull $op1, $op2\t# overflow check int" %}
10307 ins_encode %{
10308 __ imull($op1$$Register, $op2$$Register);
10309 %}
10310 ins_pipe(ialu_reg_reg_alu0);
10311 %}
10312
10313 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
10314 %{
10315 match(Set cr (OverflowMulI op1 op2));
10316 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10317
10318 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
10319 ins_encode %{
10320 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
10321 %}
10322 ins_pipe(ialu_reg_reg_alu0);
10323 %}
10324
10325 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10326 %{
10327 match(Set cr (OverflowMulL op1 op2));
10328 effect(DEF cr, USE_KILL op1, USE op2);
10329
10330 format %{ "imulq $op1, $op2\t# overflow check long" %}
10331 ins_encode %{
10332 __ imulq($op1$$Register, $op2$$Register);
10333 %}
10334 ins_pipe(ialu_reg_reg_alu0);
10335 %}
10336
10337 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
10338 %{
10339 match(Set cr (OverflowMulL op1 op2));
10340 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10341
10342 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
10343 ins_encode %{
10344 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
10345 %}
10346 ins_pipe(ialu_reg_reg_alu0);
10347 %}
10348
10349
10350 //----------Control Flow Instructions------------------------------------------
10351 // Signed compare Instructions
10352
10353 // XXX more variants!!
10354 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10355 %{
10356 match(Set cr (CmpI op1 op2));
10357 effect(DEF cr, USE op1, USE op2);
10358
10359 format %{ "cmpl $op1, $op2" %}
10360 opcode(0x3B); /* Opcode 3B /r */
10361 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10362 ins_pipe(ialu_cr_reg_reg);
10363 %}
10364
10365 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10366 %{
10367 match(Set cr (CmpI op1 op2));
10368
10369 format %{ "cmpl $op1, $op2" %}
10370 opcode(0x81, 0x07); /* Opcode 81 /7 */
10371 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10372 ins_pipe(ialu_cr_reg_imm);
10373 %}
10374
10375 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10376 %{
10377 match(Set cr (CmpI op1 (LoadI op2)));
10378
10379 ins_cost(500); // XXX
10380 format %{ "cmpl $op1, $op2" %}
10381 opcode(0x3B); /* Opcode 3B /r */
10382 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10383 ins_pipe(ialu_cr_reg_mem);
10384 %}
10385
10386 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10387 %{
10388 match(Set cr (CmpI src zero));
10389
10390 format %{ "testl $src, $src" %}
10391 opcode(0x85);
10392 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10393 ins_pipe(ialu_cr_reg_imm);
10394 %}
10395
10396 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10397 %{
10398 match(Set cr (CmpI (AndI src con) zero));
10399
10400 format %{ "testl $src, $con" %}
10401 opcode(0xF7, 0x00);
10402 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10403 ins_pipe(ialu_cr_reg_imm);
10404 %}
10405
10406 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10407 %{
10408 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10409
10410 format %{ "testl $src, $mem" %}
10411 opcode(0x85);
10412 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10413 ins_pipe(ialu_cr_reg_mem);
10414 %}
10415
10416 // Unsigned compare Instructions; really, same as signed except they
10417 // produce an rFlagsRegU instead of rFlagsReg.
10418 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10419 %{
10420 match(Set cr (CmpU op1 op2));
10421
10422 format %{ "cmpl $op1, $op2\t# unsigned" %}
10423 opcode(0x3B); /* Opcode 3B /r */
10424 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10425 ins_pipe(ialu_cr_reg_reg);
10426 %}
10427
10428 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10429 %{
10430 match(Set cr (CmpU op1 op2));
10431
10432 format %{ "cmpl $op1, $op2\t# unsigned" %}
10433 opcode(0x81,0x07); /* Opcode 81 /7 */
10434 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10435 ins_pipe(ialu_cr_reg_imm);
10436 %}
10437
10438 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10439 %{
10440 match(Set cr (CmpU op1 (LoadI op2)));
10441
10442 ins_cost(500); // XXX
10443 format %{ "cmpl $op1, $op2\t# unsigned" %}
10444 opcode(0x3B); /* Opcode 3B /r */
10445 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10446 ins_pipe(ialu_cr_reg_mem);
10447 %}
10448
10449 // // // Cisc-spilled version of cmpU_rReg
10450 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10451 // //%{
10452 // // match(Set cr (CmpU (LoadI op1) op2));
10453 // //
10454 // // format %{ "CMPu $op1,$op2" %}
10455 // // ins_cost(500);
10456 // // opcode(0x39); /* Opcode 39 /r */
10457 // // ins_encode( OpcP, reg_mem( op1, op2) );
10458 // //%}
10459
10460 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10461 %{
10462 match(Set cr (CmpU src zero));
10463
10464 format %{ "testl $src, $src\t# unsigned" %}
10465 opcode(0x85);
10466 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10467 ins_pipe(ialu_cr_reg_imm);
10468 %}
10469
10470 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10471 %{
10472 match(Set cr (CmpP op1 op2));
10473
10474 format %{ "cmpq $op1, $op2\t# ptr" %}
10475 opcode(0x3B); /* Opcode 3B /r */
10476 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10477 ins_pipe(ialu_cr_reg_reg);
10478 %}
10479
10480 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10481 %{
10482 match(Set cr (CmpP op1 (LoadP op2)));
10483
10484 ins_cost(500); // XXX
10485 format %{ "cmpq $op1, $op2\t# ptr" %}
10486 opcode(0x3B); /* Opcode 3B /r */
10487 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10488 ins_pipe(ialu_cr_reg_mem);
10489 %}
10490
10491 // // // Cisc-spilled version of cmpP_rReg
10492 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10493 // //%{
10494 // // match(Set cr (CmpP (LoadP op1) op2));
10495 // //
10496 // // format %{ "CMPu $op1,$op2" %}
10497 // // ins_cost(500);
10498 // // opcode(0x39); /* Opcode 39 /r */
10499 // // ins_encode( OpcP, reg_mem( op1, op2) );
10500 // //%}
10501
10502 // XXX this is generalized by compP_rReg_mem???
10503 // Compare raw pointer (used in out-of-heap check).
10504 // Only works because non-oop pointers must be raw pointers
10505 // and raw pointers have no anti-dependencies.
10506 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10507 %{
10508 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
10509 match(Set cr (CmpP op1 (LoadP op2)));
10510
10511 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10512 opcode(0x3B); /* Opcode 3B /r */
10513 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10514 ins_pipe(ialu_cr_reg_mem);
10515 %}
10516
10517 // This will generate a signed flags result. This should be OK since
10518 // any compare to a zero should be eq/neq.
10519 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10520 %{
10521 match(Set cr (CmpP src zero));
10522
10523 format %{ "testq $src, $src\t# ptr" %}
10524 opcode(0x85);
10525 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10526 ins_pipe(ialu_cr_reg_imm);
10527 %}
10528
10529 // This will generate a signed flags result. This should be OK since
10530 // any compare to a zero should be eq/neq.
10531 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10532 %{
10533 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10534 match(Set cr (CmpP (LoadP op) zero));
10535
10536 ins_cost(500); // XXX
10537 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10538 opcode(0xF7); /* Opcode F7 /0 */
10539 ins_encode(REX_mem_wide(op),
10540 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10541 ins_pipe(ialu_cr_reg_imm);
10542 %}
10543
10544 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10545 %{
10546 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
10547 match(Set cr (CmpP (LoadP mem) zero));
10548
10549 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10550 ins_encode %{
10551 __ cmpq(r12, $mem$$Address);
10552 %}
10553 ins_pipe(ialu_cr_reg_mem);
10554 %}
10555
10556 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10557 %{
10558 match(Set cr (CmpN op1 op2));
10559
10560 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10561 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10562 ins_pipe(ialu_cr_reg_reg);
10563 %}
10564
10565 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10566 %{
10567 match(Set cr (CmpN src (LoadN mem)));
10568
10569 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10570 ins_encode %{
10571 __ cmpl($src$$Register, $mem$$Address);
10572 %}
10573 ins_pipe(ialu_cr_reg_mem);
10574 %}
10575
10576 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10577 match(Set cr (CmpN op1 op2));
10578
10579 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10580 ins_encode %{
10581 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10582 %}
10583 ins_pipe(ialu_cr_reg_imm);
10584 %}
10585
10586 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10587 %{
10588 match(Set cr (CmpN src (LoadN mem)));
10589
10590 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10591 ins_encode %{
10592 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10593 %}
10594 ins_pipe(ialu_cr_reg_mem);
10595 %}
10596
10597 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
10598 match(Set cr (CmpN op1 op2));
10599
10600 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
10601 ins_encode %{
10602 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
10603 %}
10604 ins_pipe(ialu_cr_reg_imm);
10605 %}
10606
10607 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
10608 %{
10609 match(Set cr (CmpN src (LoadNKlass mem)));
10610
10611 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
10612 ins_encode %{
10613 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
10614 %}
10615 ins_pipe(ialu_cr_reg_mem);
10616 %}
10617
10618 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
10619 match(Set cr (CmpN src zero));
10620
10621 format %{ "testl $src, $src\t# compressed ptr" %}
10622 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
10623 ins_pipe(ialu_cr_reg_imm);
10624 %}
10625
10626 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
10627 %{
10628 predicate(Universe::narrow_oop_base() != NULL);
10629 match(Set cr (CmpN (LoadN mem) zero));
10630
10631 ins_cost(500); // XXX
10632 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
10633 ins_encode %{
10634 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
10635 %}
10636 ins_pipe(ialu_cr_reg_mem);
10637 %}
10638
10639 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
10640 %{
10641 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
10642 match(Set cr (CmpN (LoadN mem) zero));
10643
10644 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
10645 ins_encode %{
10646 __ cmpl(r12, $mem$$Address);
10647 %}
10648 ins_pipe(ialu_cr_reg_mem);
10649 %}
10650
10651 // Yanked all unsigned pointer compare operations.
10652 // Pointer compares are done with CmpP which is already unsigned.
10653
10654 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10655 %{
10656 match(Set cr (CmpL op1 op2));
10657
10658 format %{ "cmpq $op1, $op2" %}
10659 opcode(0x3B); /* Opcode 3B /r */
10660 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10661 ins_pipe(ialu_cr_reg_reg);
10662 %}
10663
10664 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10665 %{
10666 match(Set cr (CmpL op1 op2));
10667
10668 format %{ "cmpq $op1, $op2" %}
10669 opcode(0x81, 0x07); /* Opcode 81 /7 */
10670 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
10671 ins_pipe(ialu_cr_reg_imm);
10672 %}
10673
10674 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
10675 %{
10676 match(Set cr (CmpL op1 (LoadL op2)));
10677
10678 format %{ "cmpq $op1, $op2" %}
10679 opcode(0x3B); /* Opcode 3B /r */
10680 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10681 ins_pipe(ialu_cr_reg_mem);
10682 %}
10683
10684 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
10685 %{
10686 match(Set cr (CmpL src zero));
10687
10688 format %{ "testq $src, $src" %}
10689 opcode(0x85);
10690 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10691 ins_pipe(ialu_cr_reg_imm);
10692 %}
10693
10694 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
10695 %{
10696 match(Set cr (CmpL (AndL src con) zero));
10697
10698 format %{ "testq $src, $con\t# long" %}
10699 opcode(0xF7, 0x00);
10700 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
10701 ins_pipe(ialu_cr_reg_imm);
10702 %}
10703
10704 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
10705 %{
10706 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
10707
10708 format %{ "testq $src, $mem" %}
10709 opcode(0x85);
10710 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
10711 ins_pipe(ialu_cr_reg_mem);
10712 %}
10713
10714 // Manifest a CmpL result in an integer register. Very painful.
10715 // This is the test to avoid.
10716 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
10717 %{
10718 match(Set dst (CmpL3 src1 src2));
10719 effect(KILL flags);
10720
10721 ins_cost(275); // XXX
10722 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
10723 "movl $dst, -1\n\t"
10724 "jl,s done\n\t"
10725 "setne $dst\n\t"
10726 "movzbl $dst, $dst\n\t"
10727 "done:" %}
10728 ins_encode(cmpl3_flag(src1, src2, dst));
10729 ins_pipe(pipe_slow);
10730 %}
10731
10732 //----------Max and Min--------------------------------------------------------
10733 // Min Instructions
10734
10735 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
10736 %{
10737 effect(USE_DEF dst, USE src, USE cr);
10738
10739 format %{ "cmovlgt $dst, $src\t# min" %}
10740 opcode(0x0F, 0x4F);
10741 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10742 ins_pipe(pipe_cmov_reg);
10743 %}
10744
10745
10746 instruct minI_rReg(rRegI dst, rRegI src)
10747 %{
10748 match(Set dst (MinI dst src));
10749
10750 ins_cost(200);
10751 expand %{
10752 rFlagsReg cr;
10753 compI_rReg(cr, dst, src);
10754 cmovI_reg_g(dst, src, cr);
10755 %}
10756 %}
10757
10758 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
10759 %{
10760 effect(USE_DEF dst, USE src, USE cr);
10761
10762 format %{ "cmovllt $dst, $src\t# max" %}
10763 opcode(0x0F, 0x4C);
10764 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10765 ins_pipe(pipe_cmov_reg);
10766 %}
10767
10768
10769 instruct maxI_rReg(rRegI dst, rRegI src)
10770 %{
10771 match(Set dst (MaxI dst src));
10772
10773 ins_cost(200);
10774 expand %{
10775 rFlagsReg cr;
10776 compI_rReg(cr, dst, src);
10777 cmovI_reg_l(dst, src, cr);
10778 %}
10779 %}
10780
10781 // ============================================================================
10782 // Branch Instructions
10783
10784 // Jump Direct - Label defines a relative address from JMP+1
10785 instruct jmpDir(label labl)
10786 %{
10787 match(Goto);
10788 effect(USE labl);
10789
10790 ins_cost(300);
10791 format %{ "jmp $labl" %}
10792 size(5);
10793 ins_encode %{
10794 Label* L = $labl$$label;
10795 __ jmp(*L, false); // Always long jump
10796 %}
10797 ins_pipe(pipe_jmp);
10798 %}
10799
10800 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10801 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
10802 %{
10803 match(If cop cr);
10804 effect(USE labl);
10805
10806 ins_cost(300);
10807 format %{ "j$cop $labl" %}
10808 size(6);
10809 ins_encode %{
10810 Label* L = $labl$$label;
10811 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10812 %}
10813 ins_pipe(pipe_jcc);
10814 %}
10815
10816 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10817 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
10818 %{
10819 match(CountedLoopEnd cop cr);
10820 effect(USE labl);
10821
10822 ins_cost(300);
10823 format %{ "j$cop $labl\t# loop end" %}
10824 size(6);
10825 ins_encode %{
10826 Label* L = $labl$$label;
10827 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10828 %}
10829 ins_pipe(pipe_jcc);
10830 %}
10831
10832 // Jump Direct Conditional - Label defines a relative address from Jcc+1
10833 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10834 match(CountedLoopEnd cop cmp);
10835 effect(USE labl);
10836
10837 ins_cost(300);
10838 format %{ "j$cop,u $labl\t# loop end" %}
10839 size(6);
10840 ins_encode %{
10841 Label* L = $labl$$label;
10842 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10843 %}
10844 ins_pipe(pipe_jcc);
10845 %}
10846
10847 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10848 match(CountedLoopEnd cop cmp);
10849 effect(USE labl);
10850
10851 ins_cost(200);
10852 format %{ "j$cop,u $labl\t# loop end" %}
10853 size(6);
10854 ins_encode %{
10855 Label* L = $labl$$label;
10856 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10857 %}
10858 ins_pipe(pipe_jcc);
10859 %}
10860
10861 // Jump Direct Conditional - using unsigned comparison
10862 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
10863 match(If cop cmp);
10864 effect(USE labl);
10865
10866 ins_cost(300);
10867 format %{ "j$cop,u $labl" %}
10868 size(6);
10869 ins_encode %{
10870 Label* L = $labl$$label;
10871 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10872 %}
10873 ins_pipe(pipe_jcc);
10874 %}
10875
10876 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
10877 match(If cop cmp);
10878 effect(USE labl);
10879
10880 ins_cost(200);
10881 format %{ "j$cop,u $labl" %}
10882 size(6);
10883 ins_encode %{
10884 Label* L = $labl$$label;
10885 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
10886 %}
10887 ins_pipe(pipe_jcc);
10888 %}
10889
10890 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
10891 match(If cop cmp);
10892 effect(USE labl);
10893
10894 ins_cost(200);
10895 format %{ $$template
10896 if ($cop$$cmpcode == Assembler::notEqual) {
10897 $$emit$$"jp,u $labl\n\t"
10898 $$emit$$"j$cop,u $labl"
10899 } else {
10900 $$emit$$"jp,u done\n\t"
10901 $$emit$$"j$cop,u $labl\n\t"
10902 $$emit$$"done:"
10903 }
10904 %}
10905 ins_encode %{
10906 Label* l = $labl$$label;
10907 if ($cop$$cmpcode == Assembler::notEqual) {
10908 __ jcc(Assembler::parity, *l, false);
10909 __ jcc(Assembler::notEqual, *l, false);
10910 } else if ($cop$$cmpcode == Assembler::equal) {
10911 Label done;
10912 __ jccb(Assembler::parity, done);
10913 __ jcc(Assembler::equal, *l, false);
10914 __ bind(done);
10915 } else {
10916 ShouldNotReachHere();
10917 }
10918 %}
10919 ins_pipe(pipe_jcc);
10920 %}
10921
10922 // ============================================================================
10923 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
10924 // superklass array for an instance of the superklass. Set a hidden
10925 // internal cache on a hit (cache is checked with exposed code in
10926 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
10927 // encoding ALSO sets flags.
10928
10929 instruct partialSubtypeCheck(rdi_RegP result,
10930 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
10931 rFlagsReg cr)
10932 %{
10933 match(Set result (PartialSubtypeCheck sub super));
10934 effect(KILL rcx, KILL cr);
10935
10936 ins_cost(1100); // slightly larger than the next version
10937 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
10938 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
10939 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
10940 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
10941 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
10942 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
10943 "xorq $result, $result\t\t Hit: rdi zero\n\t"
10944 "miss:\t" %}
10945
10946 opcode(0x1); // Force a XOR of RDI
10947 ins_encode(enc_PartialSubtypeCheck());
10948 ins_pipe(pipe_slow);
10949 %}
10950
10951 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
10952 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
10953 immP0 zero,
10954 rdi_RegP result)
10955 %{
10956 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
10957 effect(KILL rcx, KILL result);
10958
10959 ins_cost(1000);
10960 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
10961 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
10962 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
10963 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
10964 "jne,s miss\t\t# Missed: flags nz\n\t"
10965 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
10966 "miss:\t" %}
10967
10968 opcode(0x0); // No need to XOR RDI
10969 ins_encode(enc_PartialSubtypeCheck());
10970 ins_pipe(pipe_slow);
10971 %}
10972
10973 // ============================================================================
10974 // Branch Instructions -- short offset versions
10975 //
10976 // These instructions are used to replace jumps of a long offset (the default
10977 // match) with jumps of a shorter offset. These instructions are all tagged
10978 // with the ins_short_branch attribute, which causes the ADLC to suppress the
10979 // match rules in general matching. Instead, the ADLC generates a conversion
10980 // method in the MachNode which can be used to do in-place replacement of the
10981 // long variant with the shorter variant. The compiler will determine if a
10982 // branch can be taken by the is_short_branch_offset() predicate in the machine
10983 // specific code section of the file.
10984
10985 // Jump Direct - Label defines a relative address from JMP+1
10986 instruct jmpDir_short(label labl) %{
10987 match(Goto);
10988 effect(USE labl);
10989
10990 ins_cost(300);
10991 format %{ "jmp,s $labl" %}
10992 size(2);
10993 ins_encode %{
10994 Label* L = $labl$$label;
10995 __ jmpb(*L);
10996 %}
10997 ins_pipe(pipe_jmp);
10998 ins_short_branch(1);
10999 %}
11000
11001 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11002 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11003 match(If cop cr);
11004 effect(USE labl);
11005
11006 ins_cost(300);
11007 format %{ "j$cop,s $labl" %}
11008 size(2);
11009 ins_encode %{
11010 Label* L = $labl$$label;
11011 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11012 %}
11013 ins_pipe(pipe_jcc);
11014 ins_short_branch(1);
11015 %}
11016
11017 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11018 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11019 match(CountedLoopEnd cop cr);
11020 effect(USE labl);
11021
11022 ins_cost(300);
11023 format %{ "j$cop,s $labl\t# loop end" %}
11024 size(2);
11025 ins_encode %{
11026 Label* L = $labl$$label;
11027 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11028 %}
11029 ins_pipe(pipe_jcc);
11030 ins_short_branch(1);
11031 %}
11032
11033 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11034 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11035 match(CountedLoopEnd cop cmp);
11036 effect(USE labl);
11037
11038 ins_cost(300);
11039 format %{ "j$cop,us $labl\t# loop end" %}
11040 size(2);
11041 ins_encode %{
11042 Label* L = $labl$$label;
11043 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11044 %}
11045 ins_pipe(pipe_jcc);
11046 ins_short_branch(1);
11047 %}
11048
11049 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11050 match(CountedLoopEnd cop cmp);
11051 effect(USE labl);
11052
11053 ins_cost(300);
11054 format %{ "j$cop,us $labl\t# loop end" %}
11055 size(2);
11056 ins_encode %{
11057 Label* L = $labl$$label;
11058 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11059 %}
11060 ins_pipe(pipe_jcc);
11061 ins_short_branch(1);
11062 %}
11063
11064 // Jump Direct Conditional - using unsigned comparison
11065 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11066 match(If cop cmp);
11067 effect(USE labl);
11068
11069 ins_cost(300);
11070 format %{ "j$cop,us $labl" %}
11071 size(2);
11072 ins_encode %{
11073 Label* L = $labl$$label;
11074 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11075 %}
11076 ins_pipe(pipe_jcc);
11077 ins_short_branch(1);
11078 %}
11079
11080 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11081 match(If cop cmp);
11082 effect(USE labl);
11083
11084 ins_cost(300);
11085 format %{ "j$cop,us $labl" %}
11086 size(2);
11087 ins_encode %{
11088 Label* L = $labl$$label;
11089 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11090 %}
11091 ins_pipe(pipe_jcc);
11092 ins_short_branch(1);
11093 %}
11094
11095 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11096 match(If cop cmp);
11097 effect(USE labl);
11098
11099 ins_cost(300);
11100 format %{ $$template
11101 if ($cop$$cmpcode == Assembler::notEqual) {
11102 $$emit$$"jp,u,s $labl\n\t"
11103 $$emit$$"j$cop,u,s $labl"
11104 } else {
11105 $$emit$$"jp,u,s done\n\t"
11106 $$emit$$"j$cop,u,s $labl\n\t"
11107 $$emit$$"done:"
11108 }
11109 %}
11110 size(4);
11111 ins_encode %{
11112 Label* l = $labl$$label;
11113 if ($cop$$cmpcode == Assembler::notEqual) {
11114 __ jccb(Assembler::parity, *l);
11115 __ jccb(Assembler::notEqual, *l);
11116 } else if ($cop$$cmpcode == Assembler::equal) {
11117 Label done;
11118 __ jccb(Assembler::parity, done);
11119 __ jccb(Assembler::equal, *l);
11120 __ bind(done);
11121 } else {
11122 ShouldNotReachHere();
11123 }
11124 %}
11125 ins_pipe(pipe_jcc);
11126 ins_short_branch(1);
11127 %}
11128
11129 // ============================================================================
11130 // inlined locking and unlocking
11131
11132 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
11133 match(Set cr (FastLock object box));
11134 effect(TEMP tmp, TEMP scr, USE_KILL box);
11135 ins_cost(300);
11136 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11137 ins_encode %{
11138 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register, _counters);
11139 %}
11140 ins_pipe(pipe_slow);
11141 %}
11142
11143 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
11144 match(Set cr (FastUnlock object box));
11145 effect(TEMP tmp, USE_KILL box);
11146 ins_cost(300);
11147 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11148 ins_encode %{
11149 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
11150 %}
11151 ins_pipe(pipe_slow);
11152 %}
11153
11154
11155 // ============================================================================
11156 // Safepoint Instructions
11157 instruct safePoint_poll(rFlagsReg cr)
11158 %{
11159 predicate(!Assembler::is_polling_page_far());
11160 match(SafePoint);
11161 effect(KILL cr);
11162
11163 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11164 "# Safepoint: poll for GC" %}
11165 ins_cost(125);
11166 ins_encode %{
11167 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11168 __ testl(rax, addr);
11169 %}
11170 ins_pipe(ialu_reg_mem);
11171 %}
11172
11173 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11174 %{
11175 predicate(Assembler::is_polling_page_far());
11176 match(SafePoint poll);
11177 effect(KILL cr, USE poll);
11178
11179 format %{ "testl rax, [$poll]\t"
11180 "# Safepoint: poll for GC" %}
11181 ins_cost(125);
11182 ins_encode %{
11183 __ relocate(relocInfo::poll_type);
11184 __ testl(rax, Address($poll$$Register, 0));
11185 %}
11186 ins_pipe(ialu_reg_mem);
11187 %}
11188
11189 // ============================================================================
11190 // Procedure Call/Return Instructions
11191 // Call Java Static Instruction
11192 // Note: If this code changes, the corresponding ret_addr_offset() and
11193 // compute_padding() functions will have to be adjusted.
11194 instruct CallStaticJavaDirect(method meth) %{
11195 match(CallStaticJava);
11196 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
11197 effect(USE meth);
11198
11199 ins_cost(300);
11200 format %{ "call,static " %}
11201 opcode(0xE8); /* E8 cd */
11202 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11203 ins_pipe(pipe_slow);
11204 ins_alignment(4);
11205 %}
11206
11207 // Call Java Static Instruction (method handle version)
11208 // Note: If this code changes, the corresponding ret_addr_offset() and
11209 // compute_padding() functions will have to be adjusted.
11210 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
11211 match(CallStaticJava);
11212 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
11213 effect(USE meth);
11214 // RBP is saved by all callees (for interpreter stack correction).
11215 // We use it here for a similar purpose, in {preserve,restore}_SP.
11216
11217 ins_cost(300);
11218 format %{ "call,static/MethodHandle " %}
11219 opcode(0xE8); /* E8 cd */
11220 ins_encode(clear_avx, preserve_SP,
11221 Java_Static_Call(meth),
11222 restore_SP,
11223 call_epilog);
11224 ins_pipe(pipe_slow);
11225 ins_alignment(4);
11226 %}
11227
11228 // Call Java Dynamic Instruction
11229 // Note: If this code changes, the corresponding ret_addr_offset() and
11230 // compute_padding() functions will have to be adjusted.
11231 instruct CallDynamicJavaDirect(method meth)
11232 %{
11233 match(CallDynamicJava);
11234 effect(USE meth);
11235
11236 ins_cost(300);
11237 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11238 "call,dynamic " %}
11239 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11240 ins_pipe(pipe_slow);
11241 ins_alignment(4);
11242 %}
11243
11244 // Call Runtime Instruction
11245 instruct CallRuntimeDirect(method meth)
11246 %{
11247 match(CallRuntime);
11248 effect(USE meth);
11249
11250 ins_cost(300);
11251 format %{ "call,runtime " %}
11252 ins_encode(clear_avx, Java_To_Runtime(meth));
11253 ins_pipe(pipe_slow);
11254 %}
11255
11256 // Call runtime without safepoint
11257 instruct CallLeafDirect(method meth)
11258 %{
11259 match(CallLeaf);
11260 effect(USE meth);
11261
11262 ins_cost(300);
11263 format %{ "call_leaf,runtime " %}
11264 ins_encode(clear_avx, Java_To_Runtime(meth));
11265 ins_pipe(pipe_slow);
11266 %}
11267
11268 // Call runtime without safepoint
11269 instruct CallLeafNoFPDirect(method meth)
11270 %{
11271 match(CallLeafNoFP);
11272 effect(USE meth);
11273
11274 ins_cost(300);
11275 format %{ "call_leaf_nofp,runtime " %}
11276 ins_encode(Java_To_Runtime(meth));
11277 ins_pipe(pipe_slow);
11278 %}
11279
11280 // Return Instruction
11281 // Remove the return address & jump to it.
11282 // Notice: We always emit a nop after a ret to make sure there is room
11283 // for safepoint patching
11284 instruct Ret()
11285 %{
11286 match(Return);
11287
11288 format %{ "ret" %}
11289 opcode(0xC3);
11290 ins_encode(OpcP);
11291 ins_pipe(pipe_jmp);
11292 %}
11293
11294 // Tail Call; Jump from runtime stub to Java code.
11295 // Also known as an 'interprocedural jump'.
11296 // Target of jump will eventually return to caller.
11297 // TailJump below removes the return address.
11298 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11299 %{
11300 match(TailCall jump_target method_oop);
11301
11302 ins_cost(300);
11303 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11304 opcode(0xFF, 0x4); /* Opcode FF /4 */
11305 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11306 ins_pipe(pipe_jmp);
11307 %}
11308
11309 // Tail Jump; remove the return address; jump to target.
11310 // TailCall above leaves the return address around.
11311 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11312 %{
11313 match(TailJump jump_target ex_oop);
11314
11315 ins_cost(300);
11316 format %{ "popq rdx\t# pop return address\n\t"
11317 "jmp $jump_target" %}
11318 opcode(0xFF, 0x4); /* Opcode FF /4 */
11319 ins_encode(Opcode(0x5a), // popq rdx
11320 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11321 ins_pipe(pipe_jmp);
11322 %}
11323
11324 // Create exception oop: created by stack-crawling runtime code.
11325 // Created exception is now available to this handler, and is setup
11326 // just prior to jumping to this handler. No code emitted.
11327 instruct CreateException(rax_RegP ex_oop)
11328 %{
11329 match(Set ex_oop (CreateEx));
11330
11331 size(0);
11332 // use the following format syntax
11333 format %{ "# exception oop is in rax; no code emitted" %}
11334 ins_encode();
11335 ins_pipe(empty);
11336 %}
11337
11338 // Rethrow exception:
11339 // The exception oop will come in the first argument position.
11340 // Then JUMP (not call) to the rethrow stub code.
11341 instruct RethrowException()
11342 %{
11343 match(Rethrow);
11344
11345 // use the following format syntax
11346 format %{ "jmp rethrow_stub" %}
11347 ins_encode(enc_rethrow);
11348 ins_pipe(pipe_jmp);
11349 %}
11350
11351
11352 // ============================================================================
11353 // This name is KNOWN by the ADLC and cannot be changed.
11354 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11355 // for this guy.
11356 instruct tlsLoadP(r15_RegP dst) %{
11357 match(Set dst (ThreadLocal));
11358 effect(DEF dst);
11359
11360 size(0);
11361 format %{ "# TLS is in R15" %}
11362 ins_encode( /*empty encoding*/ );
11363 ins_pipe(ialu_reg_reg);
11364 %}
11365
11366
11367 //----------PEEPHOLE RULES-----------------------------------------------------
11368 // These must follow all instruction definitions as they use the names
11369 // defined in the instructions definitions.
11370 //
11371 // peepmatch ( root_instr_name [preceding_instruction]* );
11372 //
11373 // peepconstraint %{
11374 // (instruction_number.operand_name relational_op instruction_number.operand_name
11375 // [, ...] );
11376 // // instruction numbers are zero-based using left to right order in peepmatch
11377 //
11378 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11379 // // provide an instruction_number.operand_name for each operand that appears
11380 // // in the replacement instruction's match rule
11381 //
11382 // ---------VM FLAGS---------------------------------------------------------
11383 //
11384 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11385 //
11386 // Each peephole rule is given an identifying number starting with zero and
11387 // increasing by one in the order seen by the parser. An individual peephole
11388 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11389 // on the command-line.
11390 //
11391 // ---------CURRENT LIMITATIONS----------------------------------------------
11392 //
11393 // Only match adjacent instructions in same basic block
11394 // Only equality constraints
11395 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11396 // Only one replacement instruction
11397 //
11398 // ---------EXAMPLE----------------------------------------------------------
11399 //
11400 // // pertinent parts of existing instructions in architecture description
11401 // instruct movI(rRegI dst, rRegI src)
11402 // %{
11403 // match(Set dst (CopyI src));
11404 // %}
11405 //
11406 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11407 // %{
11408 // match(Set dst (AddI dst src));
11409 // effect(KILL cr);
11410 // %}
11411 //
11412 // // Change (inc mov) to lea
11413 // peephole %{
11414 // // increment preceeded by register-register move
11415 // peepmatch ( incI_rReg movI );
11416 // // require that the destination register of the increment
11417 // // match the destination register of the move
11418 // peepconstraint ( 0.dst == 1.dst );
11419 // // construct a replacement instruction that sets
11420 // // the destination to ( move's source register + one )
11421 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11422 // %}
11423 //
11424
11425 // Implementation no longer uses movX instructions since
11426 // machine-independent system no longer uses CopyX nodes.
11427 //
11428 // peephole
11429 // %{
11430 // peepmatch (incI_rReg movI);
11431 // peepconstraint (0.dst == 1.dst);
11432 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11433 // %}
11434
11435 // peephole
11436 // %{
11437 // peepmatch (decI_rReg movI);
11438 // peepconstraint (0.dst == 1.dst);
11439 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11440 // %}
11441
11442 // peephole
11443 // %{
11444 // peepmatch (addI_rReg_imm movI);
11445 // peepconstraint (0.dst == 1.dst);
11446 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11447 // %}
11448
11449 // peephole
11450 // %{
11451 // peepmatch (incL_rReg movL);
11452 // peepconstraint (0.dst == 1.dst);
11453 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11454 // %}
11455
11456 // peephole
11457 // %{
11458 // peepmatch (decL_rReg movL);
11459 // peepconstraint (0.dst == 1.dst);
11460 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11461 // %}
11462
11463 // peephole
11464 // %{
11465 // peepmatch (addL_rReg_imm movL);
11466 // peepconstraint (0.dst == 1.dst);
11467 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11468 // %}
11469
11470 // peephole
11471 // %{
11472 // peepmatch (addP_rReg_imm movP);
11473 // peepconstraint (0.dst == 1.dst);
11474 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11475 // %}
11476
11477 // // Change load of spilled value to only a spill
11478 // instruct storeI(memory mem, rRegI src)
11479 // %{
11480 // match(Set mem (StoreI mem src));
11481 // %}
11482 //
11483 // instruct loadI(rRegI dst, memory mem)
11484 // %{
11485 // match(Set dst (LoadI mem));
11486 // %}
11487 //
11488
11489 peephole
11490 %{
11491 peepmatch (loadI storeI);
11492 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11493 peepreplace (storeI(1.mem 1.mem 1.src));
11494 %}
11495
11496 peephole
11497 %{
11498 peepmatch (loadL storeL);
11499 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11500 peepreplace (storeL(1.mem 1.mem 1.src));
11501 %}
11502
11503 //----------SMARTSPILL RULES---------------------------------------------------
11504 // These must follow all instruction definitions as they use the names
11505 // defined in the instructions definitions.