1 //
2 // Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2013 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
491
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
527
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
538
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
545
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
550
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
559
560 reg_class r19_bits64_reg(R19_H, R19);
561
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
598
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
636
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
674
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
711
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
747
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
764
765
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
768
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
779
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
784
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
788
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
823
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
860
861 %}
862
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
879
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
883
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
888
889
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Returns true if Node n is followed by a MemBar node that
895 // will do an acquire. If so, this node must not do the acquire
896 // operation.
897 bool followed_by_acquire(const Node *n);
898 %}
899
900 source %{
901
902 // Optimize load-acquire.
903 //
904 // Check if acquire is unnecessary due to following operation that does
905 // acquire anyways.
906 // Walk the pattern:
907 //
908 // n: Load.acq
909 // |
910 // MemBarAcquire
911 // | |
912 // Proj(ctrl) Proj(mem)
913 // | |
914 // MemBarRelease/Volatile
915 //
916 bool followed_by_acquire(const Node *load) {
917 assert(load->is_Load(), "So far implemented only for loads.");
918
919 // Find MemBarAcquire.
920 const Node *mba = NULL;
921 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
922 const Node *out = load->fast_out(i);
923 if (out->Opcode() == Op_MemBarAcquire) {
924 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
925 mba = out;
926 break;
927 }
928 }
929 if (!mba) return false;
930
931 // Find following MemBar node.
932 //
933 // The following node must be reachable by control AND memory
934 // edge to assure no other operations are in between the two nodes.
935 //
936 // So first get the Proj node, mem_proj, to use it to iterate forward.
937 Node *mem_proj = NULL;
938 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
939 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
940 assert(mem_proj->is_Proj(), "only projections here");
941 ProjNode *proj = mem_proj->as_Proj();
942 if (proj->_con == TypeFunc::Memory &&
943 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
944 break;
945 }
946 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
947
948 // Search MemBar behind Proj. If there are other memory operations
949 // behind the Proj we lost.
950 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
951 Node *x = mem_proj->fast_out(j);
952 // Proj might have an edge to a store or load node which precedes the membar.
953 if (x->is_Mem()) return false;
954
955 // On PPC64 release and volatile are implemented by an instruction
956 // that also has acquire semantics. I.e. there is no need for an
957 // acquire before these.
958 int xop = x->Opcode();
959 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
960 // Make sure we're not missing Call/Phi/MergeMem by checking
961 // control edges. The control edge must directly lead back
962 // to the MemBarAcquire
963 Node *ctrl_proj = x->in(0);
964 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
965 return true;
966 }
967 }
968 }
969
970 return false;
971 }
972
973 #define __ _masm.
974
975 // Tertiary op of a LoadP or StoreP encoding.
976 #define REGP_OP true
977
978 // ****************************************************************************
979
980 // REQUIRED FUNCTIONALITY
981
982 // !!!!! Special hack to get all type of calls to specify the byte offset
983 // from the start of the call to the point where the return address
984 // will point.
985
986 // PPC port: Removed use of lazy constant construct.
987
988 int MachCallStaticJavaNode::ret_addr_offset() {
989 // It's only a single branch-and-link instruction.
990 return 4;
991 }
992
993 int MachCallDynamicJavaNode::ret_addr_offset() {
994 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
995 // postalloc expanded calls if we use inline caches and do not update method data.
996 if (UseInlineCaches)
997 return 4;
998
999 int vtable_index = this->_vtable_index;
1000 if (vtable_index < 0) {
1001 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1002 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1003 return 12;
1004 } else {
1005 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1006 return 24;
1007 }
1008 }
1009
1010 int MachCallRuntimeNode::ret_addr_offset() {
1011 #if defined(ABI_ELFv2)
1012 return 28;
1013 #else
1014 return 40;
1015 #endif
1016 }
1017
1018 //=============================================================================
1019
1020 // condition code conversions
1021
1022 static int cc_to_boint(int cc) {
1023 return Assembler::bcondCRbiIs0 | (cc & 8);
1024 }
1025
1026 static int cc_to_inverse_boint(int cc) {
1027 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1028 }
1029
1030 static int cc_to_biint(int cc, int flags_reg) {
1031 return (flags_reg << 2) | (cc & 3);
1032 }
1033
1034 //=============================================================================
1035
1036 // Compute padding required for nodes which need alignment. The padding
1037 // is the number of bytes (not instructions) which will be inserted before
1038 // the instruction. The padding must match the size of a NOP instruction.
1039
1040 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1041 return (3*4-current_offset)&31;
1042 }
1043
1044 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1045 return (2*4-current_offset)&31;
1046 }
1047
1048 int string_indexOf_immNode::compute_padding(int current_offset) const {
1049 return (3*4-current_offset)&31;
1050 }
1051
1052 int string_indexOfNode::compute_padding(int current_offset) const {
1053 return (1*4-current_offset)&31;
1054 }
1055
1056 int string_compareNode::compute_padding(int current_offset) const {
1057 return (4*4-current_offset)&31;
1058 }
1059
1060 int string_equals_immNode::compute_padding(int current_offset) const {
1061 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1062 return (2*4-current_offset)&31;
1063 }
1064
1065 int string_equalsNode::compute_padding(int current_offset) const {
1066 return (7*4-current_offset)&31;
1067 }
1068
1069 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1070 return (2*4-current_offset)&31;
1071 }
1072
1073 //=============================================================================
1074
1075 // Indicate if the safepoint node needs the polling page as an input.
1076 bool SafePointNode::needs_polling_address_input() {
1077 // The address is loaded from thread by a seperate node.
1078 return true;
1079 }
1080
1081 //=============================================================================
1082
1083 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1084 void emit_break(CodeBuffer &cbuf) {
1085 MacroAssembler _masm(&cbuf);
1086 __ illtrap();
1087 }
1088
1089 #ifndef PRODUCT
1090 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1091 st->print("BREAKPOINT");
1092 }
1093 #endif
1094
1095 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1096 emit_break(cbuf);
1097 }
1098
1099 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1100 return MachNode::size(ra_);
1101 }
1102
1103 //=============================================================================
1104
1105 void emit_nop(CodeBuffer &cbuf) {
1106 MacroAssembler _masm(&cbuf);
1107 __ nop();
1108 }
1109
1110 static inline void emit_long(CodeBuffer &cbuf, int value) {
1111 *((int*)(cbuf.insts_end())) = value;
1112 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1113 }
1114
1115 //=============================================================================
1116
1117 // Emit a trampoline stub for a call to a target which is too far away.
1118 //
1119 // code sequences:
1120 //
1121 // call-site:
1122 // branch-and-link to <destination> or <trampoline stub>
1123 //
1124 // Related trampoline stub for this call-site in the stub section:
1125 // load the call target from the constant pool
1126 // branch via CTR (LR/link still points to the call-site above)
1127
1128 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1129
1130 void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1131 // Start the stub.
1132 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1133 if (stub == NULL) {
1134 Compile::current()->env()->record_out_of_memory_failure();
1135 return;
1136 }
1137
1138 // For java_to_interp stubs we use R11_scratch1 as scratch register
1139 // and in call trampoline stubs we use R12_scratch2. This way we
1140 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1141 Register reg_scratch = R12_scratch2;
1142
1143 // Create a trampoline stub relocation which relates this trampoline stub
1144 // with the call instruction at insts_call_instruction_offset in the
1145 // instructions code-section.
1146 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1147 const int stub_start_offset = __ offset();
1148
1149 // Now, create the trampoline stub's code:
1150 // - load the TOC
1151 // - load the call target from the constant pool
1152 // - call
1153 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1154 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1155 __ mtctr(reg_scratch);
1156 __ bctr();
1157
1158 const address stub_start_addr = __ addr_at(stub_start_offset);
1159
1160 // FIXME: Assert that the trampoline stub can be identified and patched.
1161
1162 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1163 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1164 "encoded offset into the constant pool must match");
1165 // Trampoline_stub_size should be good.
1166 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1167 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1168
1169 // End the stub.
1170 __ end_a_stub();
1171 }
1172
1173 // Size of trampoline stub, this doesn't need to be accurate but it must
1174 // be larger or equal to the real size of the stub.
1175 // Used for optimization in Compile::Shorten_branches.
1176 uint size_call_trampoline() {
1177 return trampoline_stub_size;
1178 }
1179
1180 // Number of relocation entries needed by trampoline stub.
1181 // Used for optimization in Compile::Shorten_branches.
1182 uint reloc_call_trampoline() {
1183 return 5;
1184 }
1185
1186 //=============================================================================
1187
1188 // Emit an inline branch-and-link call and a related trampoline stub.
1189 //
1190 // code sequences:
1191 //
1192 // call-site:
1193 // branch-and-link to <destination> or <trampoline stub>
1194 //
1195 // Related trampoline stub for this call-site in the stub section:
1196 // load the call target from the constant pool
1197 // branch via CTR (LR/link still points to the call-site above)
1198 //
1199
1200 typedef struct {
1201 int insts_call_instruction_offset;
1202 int ret_addr_offset;
1203 } EmitCallOffsets;
1204
1205 // Emit a branch-and-link instruction that branches to a trampoline.
1206 // - Remember the offset of the branch-and-link instruction.
1207 // - Add a relocation at the branch-and-link instruction.
1208 // - Emit a branch-and-link.
1209 // - Remember the return pc offset.
1210 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1211 EmitCallOffsets offsets = { -1, -1 };
1212 const int start_offset = __ offset();
1213 offsets.insts_call_instruction_offset = __ offset();
1214
1215 // No entry point given, use the current pc.
1216 if (entry_point == NULL) entry_point = __ pc();
1217
1218 if (!Compile::current()->in_scratch_emit_size()) {
1219 // Put the entry point as a constant into the constant pool.
1220 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1221 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1222
1223 // Emit the trampoline stub which will be related to the branch-and-link below.
1224 emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1225 __ relocate(rtype);
1226 }
1227
1228 // Note: At this point we do not have the address of the trampoline
1229 // stub, and the entry point might be too far away for bl, so __ pc()
1230 // serves as dummy and the bl will be patched later.
1231 __ bl((address) __ pc());
1232
1233 offsets.ret_addr_offset = __ offset() - start_offset;
1234
1235 return offsets;
1236 }
1237
1238 //=============================================================================
1239
1240 // Factory for creating loadConL* nodes for large/small constant pool.
1241
1242 static inline jlong replicate_immF(float con) {
1243 // Replicate float con 2 times and pack into vector.
1244 int val = *((int*)&con);
1245 jlong lval = val;
1246 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1247 return lval;
1248 }
1249
1250 //=============================================================================
1251
1252 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1253 int Compile::ConstantTable::calculate_table_base_offset() const {
1254 return 0; // absolute addressing, no offset
1255 }
1256
1257 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1258 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1259 Compile *C = ra_->C;
1260
1261 iRegPdstOper *op_dst = new (C) iRegPdstOper();
1262 MachNode *m1 = new (C) loadToc_hiNode();
1263 MachNode *m2 = new (C) loadToc_loNode();
1264
1265 m1->add_req(NULL);
1266 m2->add_req(NULL, m1);
1267 m1->_opnds[0] = op_dst;
1268 m2->_opnds[0] = op_dst;
1269 m2->_opnds[1] = op_dst;
1270 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1271 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1272 nodes->push(m1);
1273 nodes->push(m2);
1274 }
1275
1276 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1277 // Is postalloc expanded.
1278 ShouldNotReachHere();
1279 }
1280
1281 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1282 return 0;
1283 }
1284
1285 #ifndef PRODUCT
1286 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1287 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1288 }
1289 #endif
1290
1291 //=============================================================================
1292
1293 #ifndef PRODUCT
1294 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1295 Compile* C = ra_->C;
1296 const long framesize = C->frame_slots() << LogBytesPerInt;
1297
1298 st->print("PROLOG\n\t");
1299 if (C->need_stack_bang(framesize)) {
1300 st->print("stack_overflow_check\n\t");
1301 }
1302
1303 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1304 st->print("save return pc\n\t");
1305 st->print("push frame %d\n\t", -framesize);
1306 }
1307 }
1308 #endif
1309
1310 // Macro used instead of the common __ to emulate the pipes of PPC.
1311 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1312 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1313 // still no scheduling of this code is possible, the micro scheduler is aware of the
1314 // code and can update its internal data. The following mechanism is used to achieve this:
1315 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1316 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1317 #if 0 // TODO: PPC port
1318 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1319 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1320 _masm.
1321 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1322 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1323 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1324 C->hb_scheduling()->_pdScheduling->advance_offset
1325 #else
1326 #define ___(op) if (UsePower6SchedulerPPC64) \
1327 Unimplemented(); \
1328 _masm.
1329 #define ___stop if (UsePower6SchedulerPPC64) \
1330 Unimplemented()
1331 #define ___advance if (UsePower6SchedulerPPC64) \
1332 Unimplemented()
1333 #endif
1334
1335 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1336 Compile* C = ra_->C;
1337 MacroAssembler _masm(&cbuf);
1338
1339 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1340 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1341
1342 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1343
1344 const Register return_pc = R20; // Must match return_addr() in frame section.
1345 const Register callers_sp = R21;
1346 const Register push_frame_temp = R22;
1347 const Register toc_temp = R23;
1348 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1349
1350 if (method_is_frameless) {
1351 // Add nop at beginning of all frameless methods to prevent any
1352 // oop instructions from getting overwritten by make_not_entrant
1353 // (patching attempt would fail).
1354 ___(nop) nop();
1355 } else {
1356 // Get return pc.
1357 ___(mflr) mflr(return_pc);
1358 }
1359
1360 // Calls to C2R adapters often do not accept exceptional returns.
1361 // We require that their callers must bang for them. But be
1362 // careful, because some VM calls (such as call site linkage) can
1363 // use several kilobytes of stack. But the stack safety zone should
1364 // account for that. See bugs 4446381, 4468289, 4497237.
1365 if (C->need_stack_bang(framesize) && UseStackBanging) {
1366 // Unfortunately we cannot use the function provided in
1367 // assembler.cpp as we have to emulate the pipes. So I had to
1368 // insert the code of generate_stack_overflow_check(), see
1369 // assembler.cpp for some illuminative comments.
1370 const int page_size = os::vm_page_size();
1371 int bang_end = StackShadowPages*page_size;
1372
1373 // This is how far the previous frame's stack banging extended.
1374 const int bang_end_safe = bang_end;
1375
1376 if (framesize > page_size) {
1377 bang_end += framesize;
1378 }
1379
1380 int bang_offset = bang_end_safe;
1381
1382 while (bang_offset <= bang_end) {
1383 // Need at least one stack bang at end of shadow zone.
1384
1385 // Again I had to copy code, this time from assembler_ppc64.cpp,
1386 // bang_stack_with_offset - see there for comments.
1387
1388 // Stack grows down, caller passes positive offset.
1389 assert(bang_offset > 0, "must bang with positive offset");
1390
1391 long stdoffset = -bang_offset;
1392
1393 if (Assembler::is_simm(stdoffset, 16)) {
1394 // Signed 16 bit offset, a simple std is ok.
1395 if (UseLoadInstructionsForStackBangingPPC64) {
1396 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1397 } else {
1398 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1399 }
1400 } else if (Assembler::is_simm(stdoffset, 31)) {
1401 // Use largeoffset calculations for addis & ld/std.
1402 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1403 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1404
1405 Register tmp = R11;
1406 ___(addis) addis(tmp, R1_SP, hi);
1407 if (UseLoadInstructionsForStackBangingPPC64) {
1408 ___(ld) ld(R0, lo, tmp);
1409 } else {
1410 ___(std) std(R0, lo, tmp);
1411 }
1412 } else {
1413 ShouldNotReachHere();
1414 }
1415
1416 bang_offset += page_size;
1417 }
1418 // R11 trashed
1419 } // C->need_stack_bang(framesize) && UseStackBanging
1420
1421 unsigned int bytes = (unsigned int)framesize;
1422 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1423 ciMethod *currMethod = C -> method();
1424
1425 // Optimized version for most common case.
1426 if (UsePower6SchedulerPPC64 &&
1427 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1428 !(false /* ConstantsALot TODO: PPC port*/)) {
1429 ___(or) mr(callers_sp, R1_SP);
1430 ___(std) std(return_pc, _abi(lr), R1_SP);
1431 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1432 return;
1433 }
1434
1435 if (!method_is_frameless) {
1436 // Get callers sp.
1437 ___(or) mr(callers_sp, R1_SP);
1438
1439 // Push method's frame, modifies SP.
1440 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1441 // The ABI is already accounted for in 'framesize' via the
1442 // 'out_preserve' area.
1443 Register tmp = push_frame_temp;
1444 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1445 if (Assembler::is_simm(-offset, 16)) {
1446 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1447 } else {
1448 long x = -offset;
1449 // Had to insert load_const(tmp, -offset).
1450 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1451 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1452 ___(rldicr) sldi(tmp, tmp, 32);
1453 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1454 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1455
1456 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1457 }
1458 }
1459 #if 0 // TODO: PPC port
1460 // For testing large constant pools, emit a lot of constants to constant pool.
1461 // "Randomize" const_size.
1462 if (ConstantsALot) {
1463 const int num_consts = const_size();
1464 for (int i = 0; i < num_consts; i++) {
1465 __ long_constant(0xB0B5B00BBABE);
1466 }
1467 }
1468 #endif
1469 if (!method_is_frameless) {
1470 // Save return pc.
1471 ___(std) std(return_pc, _abi(lr), callers_sp);
1472 }
1473 }
1474 #undef ___
1475 #undef ___stop
1476 #undef ___advance
1477
1478 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1479 // Variable size. determine dynamically.
1480 return MachNode::size(ra_);
1481 }
1482
1483 int MachPrologNode::reloc() const {
1484 // Return number of relocatable values contained in this instruction.
1485 return 1; // 1 reloc entry for load_const(toc).
1486 }
1487
1488 //=============================================================================
1489
1490 #ifndef PRODUCT
1491 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1492 Compile* C = ra_->C;
1493
1494 st->print("EPILOG\n\t");
1495 st->print("restore return pc\n\t");
1496 st->print("pop frame\n\t");
1497
1498 if (do_polling() && C->is_method_compilation()) {
1499 st->print("touch polling page\n\t");
1500 }
1501 }
1502 #endif
1503
1504 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1505 Compile* C = ra_->C;
1506 MacroAssembler _masm(&cbuf);
1507
1508 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1509 assert(framesize >= 0, "negative frame-size?");
1510
1511 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1512 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1513 const Register return_pc = R11;
1514 const Register polling_page = R12;
1515
1516 if (!method_is_frameless) {
1517 // Restore return pc relative to callers' sp.
1518 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1519 }
1520
1521 if (method_needs_polling) {
1522 if (LoadPollAddressFromThread) {
1523 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1524 Unimplemented();
1525 } else {
1526 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1527 }
1528 }
1529
1530 if (!method_is_frameless) {
1531 // Move return pc to LR.
1532 __ mtlr(return_pc);
1533 // Pop frame (fixed frame-size).
1534 __ addi(R1_SP, R1_SP, (int)framesize);
1535 }
1536
1537 if (method_needs_polling) {
1538 // We need to mark the code position where the load from the safepoint
1539 // polling page was emitted as relocInfo::poll_return_type here.
1540 __ relocate(relocInfo::poll_return_type);
1541 __ load_from_polling_page(polling_page);
1542 }
1543 }
1544
1545 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1546 // Variable size. Determine dynamically.
1547 return MachNode::size(ra_);
1548 }
1549
1550 int MachEpilogNode::reloc() const {
1551 // Return number of relocatable values contained in this instruction.
1552 return 1; // 1 for load_from_polling_page.
1553 }
1554
1555 const Pipeline * MachEpilogNode::pipeline() const {
1556 return MachNode::pipeline_class();
1557 }
1558
1559 // This method seems to be obsolete. It is declared in machnode.hpp
1560 // and defined in all *.ad files, but it is never called. Should we
1561 // get rid of it?
1562 int MachEpilogNode::safepoint_offset() const {
1563 assert(do_polling(), "no return for this epilog node");
1564 return 0;
1565 }
1566
1567 #if 0 // TODO: PPC port
1568 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1569 MacroAssembler _masm(&cbuf);
1570 if (LoadPollAddressFromThread) {
1571 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1572 } else {
1573 _masm.nop();
1574 }
1575 }
1576
1577 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1578 if (LoadPollAddressFromThread) {
1579 return 4;
1580 } else {
1581 return 4;
1582 }
1583 }
1584
1585 #ifndef PRODUCT
1586 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1587 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1588 }
1589 #endif
1590
1591 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1592 return RSCRATCH1_BITS64_REG_mask();
1593 }
1594 #endif // PPC port
1595
1596 // =============================================================================
1597
1598 // Figure out which register class each belongs in: rc_int, rc_float or
1599 // rc_stack.
1600 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1601
1602 static enum RC rc_class(OptoReg::Name reg) {
1603 // Return the register class for the given register. The given register
1604 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1605 // enumeration in adGlobals_ppc64.hpp.
1606
1607 if (reg == OptoReg::Bad) return rc_bad;
1608
1609 // We have 64 integer register halves, starting at index 0.
1610 if (reg < 64) return rc_int;
1611
1612 // We have 64 floating-point register halves, starting at index 64.
1613 if (reg < 64+64) return rc_float;
1614
1615 // Between float regs & stack are the flags regs.
1616 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1617
1618 return rc_stack;
1619 }
1620
1621 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1622 bool do_print, Compile* C, outputStream *st) {
1623
1624 assert(opcode == Assembler::LD_OPCODE ||
1625 opcode == Assembler::STD_OPCODE ||
1626 opcode == Assembler::LWZ_OPCODE ||
1627 opcode == Assembler::STW_OPCODE ||
1628 opcode == Assembler::LFD_OPCODE ||
1629 opcode == Assembler::STFD_OPCODE ||
1630 opcode == Assembler::LFS_OPCODE ||
1631 opcode == Assembler::STFS_OPCODE,
1632 "opcode not supported");
1633
1634 if (cbuf) {
1635 int d =
1636 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1637 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1638 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1639 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1640 }
1641 #ifndef PRODUCT
1642 else if (do_print) {
1643 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1644 op_str,
1645 Matcher::regName[reg],
1646 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1647 }
1648 #endif
1649 return 4; // size
1650 }
1651
1652 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1653 Compile* C = ra_->C;
1654
1655 // Get registers to move.
1656 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1657 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1658 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1659 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1660
1661 enum RC src_hi_rc = rc_class(src_hi);
1662 enum RC src_lo_rc = rc_class(src_lo);
1663 enum RC dst_hi_rc = rc_class(dst_hi);
1664 enum RC dst_lo_rc = rc_class(dst_lo);
1665
1666 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1667 if (src_hi != OptoReg::Bad)
1668 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1669 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1670 "expected aligned-adjacent pairs");
1671 // Generate spill code!
1672 int size = 0;
1673
1674 if (src_lo == dst_lo && src_hi == dst_hi)
1675 return size; // Self copy, no move.
1676
1677 // --------------------------------------
1678 // Memory->Memory Spill. Use R0 to hold the value.
1679 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1680 int src_offset = ra_->reg2offset(src_lo);
1681 int dst_offset = ra_->reg2offset(dst_lo);
1682 if (src_hi != OptoReg::Bad) {
1683 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1684 "expected same type of move for high parts");
1685 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1686 if (!cbuf && !do_size) st->print("\n\t");
1687 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1688 } else {
1689 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1690 if (!cbuf && !do_size) st->print("\n\t");
1691 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1692 }
1693 return size;
1694 }
1695
1696 // --------------------------------------
1697 // Check for float->int copy; requires a trip through memory.
1698 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1699 Unimplemented();
1700 }
1701
1702 // --------------------------------------
1703 // Check for integer reg-reg copy.
1704 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1705 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1706 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1707 size = (Rsrc != Rdst) ? 4 : 0;
1708
1709 if (cbuf) {
1710 MacroAssembler _masm(cbuf);
1711 if (size) {
1712 __ mr(Rdst, Rsrc);
1713 }
1714 }
1715 #ifndef PRODUCT
1716 else if (!do_size) {
1717 if (size) {
1718 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1719 } else {
1720 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1721 }
1722 }
1723 #endif
1724 return size;
1725 }
1726
1727 // Check for integer store.
1728 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1729 int dst_offset = ra_->reg2offset(dst_lo);
1730 if (src_hi != OptoReg::Bad) {
1731 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1732 "expected same type of move for high parts");
1733 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1734 } else {
1735 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1736 }
1737 return size;
1738 }
1739
1740 // Check for integer load.
1741 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1742 int src_offset = ra_->reg2offset(src_lo);
1743 if (src_hi != OptoReg::Bad) {
1744 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1745 "expected same type of move for high parts");
1746 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1747 } else {
1748 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1749 }
1750 return size;
1751 }
1752
1753 // Check for float reg-reg copy.
1754 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1755 if (cbuf) {
1756 MacroAssembler _masm(cbuf);
1757 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1758 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1759 __ fmr(Rdst, Rsrc);
1760 }
1761 #ifndef PRODUCT
1762 else if (!do_size) {
1763 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1764 }
1765 #endif
1766 return 4;
1767 }
1768
1769 // Check for float store.
1770 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1771 int dst_offset = ra_->reg2offset(dst_lo);
1772 if (src_hi != OptoReg::Bad) {
1773 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1774 "expected same type of move for high parts");
1775 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1776 } else {
1777 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1778 }
1779 return size;
1780 }
1781
1782 // Check for float load.
1783 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1784 int src_offset = ra_->reg2offset(src_lo);
1785 if (src_hi != OptoReg::Bad) {
1786 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1787 "expected same type of move for high parts");
1788 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1789 } else {
1790 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1791 }
1792 return size;
1793 }
1794
1795 // --------------------------------------------------------------------
1796 // Check for hi bits still needing moving. Only happens for misaligned
1797 // arguments to native calls.
1798 if (src_hi == dst_hi)
1799 return size; // Self copy; no move.
1800
1801 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1802 ShouldNotReachHere(); // Unimplemented
1803 return 0;
1804 }
1805
1806 #ifndef PRODUCT
1807 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1808 if (!ra_)
1809 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1810 else
1811 implementation(NULL, ra_, false, st);
1812 }
1813 #endif
1814
1815 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1816 implementation(&cbuf, ra_, false, NULL);
1817 }
1818
1819 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1820 return implementation(NULL, ra_, true, NULL);
1821 }
1822
1823 #if 0 // TODO: PPC port
1824 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1825 #ifndef PRODUCT
1826 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1827 #endif
1828 assert(ra_->node_regs_max_index() != 0, "");
1829
1830 // Get registers to move.
1831 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1832 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1833 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1834 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1835
1836 enum RC src_lo_rc = rc_class(src_lo);
1837 enum RC dst_lo_rc = rc_class(dst_lo);
1838
1839 if (src_lo == dst_lo && src_hi == dst_hi)
1840 return ppc64Opcode_none; // Self copy, no move.
1841
1842 // --------------------------------------
1843 // Memory->Memory Spill. Use R0 to hold the value.
1844 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1845 return ppc64Opcode_compound;
1846 }
1847
1848 // --------------------------------------
1849 // Check for float->int copy; requires a trip through memory.
1850 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1851 Unimplemented();
1852 }
1853
1854 // --------------------------------------
1855 // Check for integer reg-reg copy.
1856 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1857 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1858 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1859 if (Rsrc == Rdst) {
1860 return ppc64Opcode_none;
1861 } else {
1862 return ppc64Opcode_or;
1863 }
1864 }
1865
1866 // Check for integer store.
1867 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1868 if (src_hi != OptoReg::Bad) {
1869 return ppc64Opcode_std;
1870 } else {
1871 return ppc64Opcode_stw;
1872 }
1873 }
1874
1875 // Check for integer load.
1876 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1877 if (src_hi != OptoReg::Bad) {
1878 return ppc64Opcode_ld;
1879 } else {
1880 return ppc64Opcode_lwz;
1881 }
1882 }
1883
1884 // Check for float reg-reg copy.
1885 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1886 return ppc64Opcode_fmr;
1887 }
1888
1889 // Check for float store.
1890 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1891 if (src_hi != OptoReg::Bad) {
1892 return ppc64Opcode_stfd;
1893 } else {
1894 return ppc64Opcode_stfs;
1895 }
1896 }
1897
1898 // Check for float load.
1899 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1900 if (src_hi != OptoReg::Bad) {
1901 return ppc64Opcode_lfd;
1902 } else {
1903 return ppc64Opcode_lfs;
1904 }
1905 }
1906
1907 // --------------------------------------------------------------------
1908 // Check for hi bits still needing moving. Only happens for misaligned
1909 // arguments to native calls.
1910 if (src_hi == dst_hi)
1911 return ppc64Opcode_none; // Self copy; no move.
1912
1913 ShouldNotReachHere();
1914 return ppc64Opcode_undefined;
1915 }
1916 #endif // PPC port
1917
1918 #ifndef PRODUCT
1919 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1920 st->print("NOP \t// %d nops to pad for loops.", _count);
1921 }
1922 #endif
1923
1924 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1925 MacroAssembler _masm(&cbuf);
1926 // _count contains the number of nops needed for padding.
1927 for (int i = 0; i < _count; i++) {
1928 __ nop();
1929 }
1930 }
1931
1932 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1933 return _count * 4;
1934 }
1935
1936 #ifndef PRODUCT
1937 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1938 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1939 int reg = ra_->get_reg_first(this);
1940 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset);
1941 }
1942 #endif
1943
1944 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1945 MacroAssembler _masm(&cbuf);
1946
1947 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1948 int reg = ra_->get_encode(this);
1949
1950 if (Assembler::is_simm(offset, 16)) {
1951 __ addi(as_Register(reg), R1, offset);
1952 } else {
1953 ShouldNotReachHere();
1954 }
1955 }
1956
1957 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1958 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1959 return 4;
1960 }
1961
1962 #ifndef PRODUCT
1963 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1964 st->print_cr("---- MachUEPNode ----");
1965 st->print_cr("...");
1966 }
1967 #endif
1968
1969 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1970 // This is the unverified entry point.
1971 MacroAssembler _masm(&cbuf);
1972
1973 // Inline_cache contains a klass.
1974 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1975 Register receiver_klass = R0; // tmp
1976
1977 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1978 assert(R11_scratch1 == R11, "need prologue scratch register");
1979
1980 // Check for NULL argument if we don't have implicit null checks.
1981 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1982 if (TrapBasedNullChecks) {
1983 __ trap_null_check(R3_ARG1);
1984 } else {
1985 Label valid;
1986 __ cmpdi(CCR0, R3_ARG1, 0);
1987 __ bne_predict_taken(CCR0, valid);
1988 // We have a null argument, branch to ic_miss_stub.
1989 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1990 relocInfo::runtime_call_type);
1991 __ bind(valid);
1992 }
1993 }
1994 // Assume argument is not NULL, load klass from receiver.
1995 __ load_klass(receiver_klass, R3_ARG1);
1996
1997 if (TrapBasedICMissChecks) {
1998 __ trap_ic_miss_check(receiver_klass, ic_klass);
1999 } else {
2000 Label valid;
2001 __ cmpd(CCR0, receiver_klass, ic_klass);
2002 __ beq_predict_taken(CCR0, valid);
2003 // We have an unexpected klass, branch to ic_miss_stub.
2004 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2005 relocInfo::runtime_call_type);
2006 __ bind(valid);
2007 }
2008
2009 // Argument is valid and klass is as expected, continue.
2010 }
2011
2012 #if 0 // TODO: PPC port
2013 // Optimize UEP code on z (save a load_const() call in main path).
2014 int MachUEPNode::ep_offset() {
2015 return 0;
2016 }
2017 #endif
2018
2019 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2020 // Variable size. Determine dynamically.
2021 return MachNode::size(ra_);
2022 }
2023
2024 //=============================================================================
2025
2026 uint size_exception_handler() {
2027 // The exception_handler is a b64_patchable.
2028 return MacroAssembler::b64_patchable_size;
2029 }
2030
2031 uint size_deopt_handler() {
2032 // The deopt_handler is a bl64_patchable.
2033 return MacroAssembler::bl64_patchable_size;
2034 }
2035
2036 int emit_exception_handler(CodeBuffer &cbuf) {
2037 MacroAssembler _masm(&cbuf);
2038
2039 address base = __ start_a_stub(size_exception_handler());
2040 if (base == NULL) return 0; // CodeBuffer::expand failed
2041
2042 int offset = __ offset();
2043 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2044 relocInfo::runtime_call_type);
2045 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2046 __ end_a_stub();
2047
2048 return offset;
2049 }
2050
2051 // The deopt_handler is like the exception handler, but it calls to
2052 // the deoptimization blob instead of jumping to the exception blob.
2053 int emit_deopt_handler(CodeBuffer& cbuf) {
2054 MacroAssembler _masm(&cbuf);
2055
2056 address base = __ start_a_stub(size_deopt_handler());
2057 if (base == NULL) return 0; // CodeBuffer::expand failed
2058
2059 int offset = __ offset();
2060 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2061 relocInfo::runtime_call_type);
2062 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2063 __ end_a_stub();
2064
2065 return offset;
2066 }
2067
2068 //=============================================================================
2069
2070 // Use a frame slots bias for frameless methods if accessing the stack.
2071 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2072 if (as_Register(reg_enc) == R1_SP) {
2073 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2074 }
2075 return 0;
2076 }
2077
2078 const bool Matcher::match_rule_supported(int opcode) {
2079 if (!has_match_rule(opcode))
2080 return false;
2081
2082 switch (opcode) {
2083 case Op_SqrtD:
2084 return VM_Version::has_fsqrt();
2085 case Op_CountLeadingZerosI:
2086 case Op_CountLeadingZerosL:
2087 case Op_CountTrailingZerosI:
2088 case Op_CountTrailingZerosL:
2089 if (!UseCountLeadingZerosInstructionsPPC64)
2090 return false;
2091 break;
2092
2093 case Op_PopCountI:
2094 case Op_PopCountL:
2095 return (UsePopCountInstruction && VM_Version::has_popcntw());
2096
2097 case Op_StrComp:
2098 return SpecialStringCompareTo;
2099 case Op_StrEquals:
2100 return SpecialStringEquals;
2101 case Op_StrIndexOf:
2102 return SpecialStringIndexOf;
2103 }
2104
2105 return true; // Per default match rules are supported.
2106 }
2107
2108 int Matcher::regnum_to_fpu_offset(int regnum) {
2109 // No user for this method?
2110 Unimplemented();
2111 return 999;
2112 }
2113
2114 const bool Matcher::convL2FSupported(void) {
2115 // fcfids can do the conversion (>= Power7).
2116 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2117 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2118 }
2119
2120 // Vector width in bytes.
2121 const int Matcher::vector_width_in_bytes(BasicType bt) {
2122 assert(MaxVectorSize == 8, "");
2123 return 8;
2124 }
2125
2126 // Vector ideal reg.
2127 const int Matcher::vector_ideal_reg(int size) {
2128 assert(MaxVectorSize == 8 && size == 8, "");
2129 return Op_RegL;
2130 }
2131
2132 const int Matcher::vector_shift_count_ideal_reg(int size) {
2133 fatal("vector shift is not supported");
2134 return Node::NotAMachineReg;
2135 }
2136
2137 // Limits on vector size (number of elements) loaded into vector.
2138 const int Matcher::max_vector_size(const BasicType bt) {
2139 assert(is_java_primitive(bt), "only primitive type vectors");
2140 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2141 }
2142
2143 const int Matcher::min_vector_size(const BasicType bt) {
2144 return max_vector_size(bt); // Same as max.
2145 }
2146
2147 // PPC doesn't support misaligned vectors store/load.
2148 const bool Matcher::misaligned_vectors_ok() {
2149 return false;
2150 }
2151
2152 // PPC AES support not yet implemented
2153 const bool Matcher::pass_original_key_for_aes() {
2154 return false;
2155 }
2156
2157 // RETURNS: whether this branch offset is short enough that a short
2158 // branch can be used.
2159 //
2160 // If the platform does not provide any short branch variants, then
2161 // this method should return `false' for offset 0.
2162 //
2163 // `Compile::Fill_buffer' will decide on basis of this information
2164 // whether to do the pass `Compile::Shorten_branches' at all.
2165 //
2166 // And `Compile::Shorten_branches' will decide on basis of this
2167 // information whether to replace particular branch sites by short
2168 // ones.
2169 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2170 // Is the offset within the range of a ppc64 pc relative branch?
2171 bool b;
2172
2173 const int safety_zone = 3 * BytesPerInstWord;
2174 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2175 29 - 16 + 1 + 2);
2176 return b;
2177 }
2178
2179 const bool Matcher::isSimpleConstant64(jlong value) {
2180 // Probably always true, even if a temp register is required.
2181 return true;
2182 }
2183 /* TODO: PPC port
2184 // Make a new machine dependent decode node (with its operands).
2185 MachTypeNode *Matcher::make_decode_node(Compile *C) {
2186 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2187 "This method is only implemented for unscaled cOops mode so far");
2188 MachTypeNode *decode = new (C) decodeN_unscaledNode();
2189 decode->set_opnd_array(0, new (C) iRegPdstOper());
2190 decode->set_opnd_array(1, new (C) iRegNsrcOper());
2191 return decode;
2192 }
2193 */
2194 // Threshold size for cleararray.
2195 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2196
2197 // false => size gets scaled to BytesPerLong, ok.
2198 const bool Matcher::init_array_count_is_in_bytes = false;
2199
2200 // Use conditional move (CMOVL) on Power7.
2201 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2202
2203 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2204 // fsel doesn't accept a condition register as input, so this would be slightly different.
2205 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2206
2207 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2208 const bool Matcher::require_postalloc_expand = true;
2209
2210 // Should the Matcher clone shifts on addressing modes, expecting them to
2211 // be subsumed into complex addressing expressions or compute them into
2212 // registers? True for Intel but false for most RISCs.
2213 const bool Matcher::clone_shift_expressions = false;
2214
2215 // Do we need to mask the count passed to shift instructions or does
2216 // the cpu only look at the lower 5/6 bits anyway?
2217 // Off, as masks are generated in expand rules where required.
2218 // Constant shift counts are handled in Ideal phase.
2219 const bool Matcher::need_masked_shift_count = false;
2220
2221 // This affects two different things:
2222 // - how Decode nodes are matched
2223 // - how ImplicitNullCheck opportunities are recognized
2224 // If true, the matcher will try to remove all Decodes and match them
2225 // (as operands) into nodes. NullChecks are not prepared to deal with
2226 // Decodes by final_graph_reshaping().
2227 // If false, final_graph_reshaping() forces the decode behind the Cmp
2228 // for a NullCheck. The matcher matches the Decode node into a register.
2229 // Implicit_null_check optimization moves the Decode along with the
2230 // memory operation back up before the NullCheck.
2231 bool Matcher::narrow_oop_use_complex_address() {
2232 // TODO: PPC port if (MatchDecodeNodes) return true;
2233 return false;
2234 }
2235
2236 bool Matcher::narrow_klass_use_complex_address() {
2237 NOT_LP64(ShouldNotCallThis());
2238 assert(UseCompressedClassPointers, "only for compressed klass code");
2239 // TODO: PPC port if (MatchDecodeNodes) return true;
2240 return false;
2241 }
2242
2243 // Is it better to copy float constants, or load them directly from memory?
2244 // Intel can load a float constant from a direct address, requiring no
2245 // extra registers. Most RISCs will have to materialize an address into a
2246 // register first, so they would do better to copy the constant from stack.
2247 const bool Matcher::rematerialize_float_constants = false;
2248
2249 // If CPU can load and store mis-aligned doubles directly then no fixup is
2250 // needed. Else we split the double into 2 integer pieces and move it
2251 // piece-by-piece. Only happens when passing doubles into C code as the
2252 // Java calling convention forces doubles to be aligned.
2253 const bool Matcher::misaligned_doubles_ok = true;
2254
2255 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2256 Unimplemented();
2257 }
2258
2259 // Advertise here if the CPU requires explicit rounding operations
2260 // to implement the UseStrictFP mode.
2261 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2262
2263 // Do floats take an entire double register or just half?
2264 //
2265 // A float occupies a ppc64 double register. For the allocator, a
2266 // ppc64 double register appears as a pair of float registers.
2267 bool Matcher::float_in_double() { return true; }
2268
2269 // Do ints take an entire long register or just half?
2270 // The relevant question is how the int is callee-saved:
2271 // the whole long is written but de-opt'ing will have to extract
2272 // the relevant 32 bits.
2273 const bool Matcher::int_in_long = true;
2274
2275 // Constants for c2c and c calling conventions.
2276
2277 const MachRegisterNumbers iarg_reg[8] = {
2278 R3_num, R4_num, R5_num, R6_num,
2279 R7_num, R8_num, R9_num, R10_num
2280 };
2281
2282 const MachRegisterNumbers farg_reg[13] = {
2283 F1_num, F2_num, F3_num, F4_num,
2284 F5_num, F6_num, F7_num, F8_num,
2285 F9_num, F10_num, F11_num, F12_num,
2286 F13_num
2287 };
2288
2289 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2290
2291 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2292
2293 // Return whether or not this register is ever used as an argument. This
2294 // function is used on startup to build the trampoline stubs in generateOptoStub.
2295 // Registers not mentioned will be killed by the VM call in the trampoline, and
2296 // arguments in those registers not be available to the callee.
2297 bool Matcher::can_be_java_arg(int reg) {
2298 // We return true for all registers contained in iarg_reg[] and
2299 // farg_reg[] and their virtual halves.
2300 // We must include the virtual halves in order to get STDs and LDs
2301 // instead of STWs and LWs in the trampoline stubs.
2302
2303 if ( reg == R3_num || reg == R3_H_num
2304 || reg == R4_num || reg == R4_H_num
2305 || reg == R5_num || reg == R5_H_num
2306 || reg == R6_num || reg == R6_H_num
2307 || reg == R7_num || reg == R7_H_num
2308 || reg == R8_num || reg == R8_H_num
2309 || reg == R9_num || reg == R9_H_num
2310 || reg == R10_num || reg == R10_H_num)
2311 return true;
2312
2313 if ( reg == F1_num || reg == F1_H_num
2314 || reg == F2_num || reg == F2_H_num
2315 || reg == F3_num || reg == F3_H_num
2316 || reg == F4_num || reg == F4_H_num
2317 || reg == F5_num || reg == F5_H_num
2318 || reg == F6_num || reg == F6_H_num
2319 || reg == F7_num || reg == F7_H_num
2320 || reg == F8_num || reg == F8_H_num
2321 || reg == F9_num || reg == F9_H_num
2322 || reg == F10_num || reg == F10_H_num
2323 || reg == F11_num || reg == F11_H_num
2324 || reg == F12_num || reg == F12_H_num
2325 || reg == F13_num || reg == F13_H_num)
2326 return true;
2327
2328 return false;
2329 }
2330
2331 bool Matcher::is_spillable_arg(int reg) {
2332 return can_be_java_arg(reg);
2333 }
2334
2335 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2336 return false;
2337 }
2338
2339 // Register for DIVI projection of divmodI.
2340 RegMask Matcher::divI_proj_mask() {
2341 ShouldNotReachHere();
2342 return RegMask();
2343 }
2344
2345 // Register for MODI projection of divmodI.
2346 RegMask Matcher::modI_proj_mask() {
2347 ShouldNotReachHere();
2348 return RegMask();
2349 }
2350
2351 // Register for DIVL projection of divmodL.
2352 RegMask Matcher::divL_proj_mask() {
2353 ShouldNotReachHere();
2354 return RegMask();
2355 }
2356
2357 // Register for MODL projection of divmodL.
2358 RegMask Matcher::modL_proj_mask() {
2359 ShouldNotReachHere();
2360 return RegMask();
2361 }
2362
2363 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2364 return RegMask();
2365 }
2366
2367 %}
2368
2369 //----------ENCODING BLOCK-----------------------------------------------------
2370 // This block specifies the encoding classes used by the compiler to output
2371 // byte streams. Encoding classes are parameterized macros used by
2372 // Machine Instruction Nodes in order to generate the bit encoding of the
2373 // instruction. Operands specify their base encoding interface with the
2374 // interface keyword. There are currently supported four interfaces,
2375 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2376 // operand to generate a function which returns its register number when
2377 // queried. CONST_INTER causes an operand to generate a function which
2378 // returns the value of the constant when queried. MEMORY_INTER causes an
2379 // operand to generate four functions which return the Base Register, the
2380 // Index Register, the Scale Value, and the Offset Value of the operand when
2381 // queried. COND_INTER causes an operand to generate six functions which
2382 // return the encoding code (ie - encoding bits for the instruction)
2383 // associated with each basic boolean condition for a conditional instruction.
2384 //
2385 // Instructions specify two basic values for encoding. Again, a function
2386 // is available to check if the constant displacement is an oop. They use the
2387 // ins_encode keyword to specify their encoding classes (which must be
2388 // a sequence of enc_class names, and their parameters, specified in
2389 // the encoding block), and they use the
2390 // opcode keyword to specify, in order, their primary, secondary, and
2391 // tertiary opcode. Only the opcode sections which a particular instruction
2392 // needs for encoding need to be specified.
2393 encode %{
2394 enc_class enc_unimplemented %{
2395 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2396 MacroAssembler _masm(&cbuf);
2397 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2398 %}
2399
2400 enc_class enc_untested %{
2401 #ifdef ASSERT
2402 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2403 MacroAssembler _masm(&cbuf);
2404 __ untested("Untested mach node encoding in AD file.");
2405 #else
2406 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2407 #endif
2408 %}
2409
2410 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2411 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2412 MacroAssembler _masm(&cbuf);
2413 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2414 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2415 %}
2416
2417 // Load acquire.
2418 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2419 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2420 MacroAssembler _masm(&cbuf);
2421 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2422 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2423 __ twi_0($dst$$Register);
2424 __ isync();
2425 %}
2426
2427 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2428 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2429
2430 MacroAssembler _masm(&cbuf);
2431 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2432 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2433 %}
2434
2435 // Load acquire.
2436 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2437 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2438
2439 MacroAssembler _masm(&cbuf);
2440 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2441 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2442 __ twi_0($dst$$Register);
2443 __ isync();
2444 %}
2445
2446 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2447 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2448
2449 MacroAssembler _masm(&cbuf);
2450 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2451 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2452 %}
2453
2454 // Load acquire.
2455 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2456 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2457
2458 MacroAssembler _masm(&cbuf);
2459 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2460 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2461 __ twi_0($dst$$Register);
2462 __ isync();
2463 %}
2464
2465 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2466 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2467 MacroAssembler _masm(&cbuf);
2468 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2469 // Operand 'ds' requires 4-alignment.
2470 assert((Idisp & 0x3) == 0, "unaligned offset");
2471 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2472 %}
2473
2474 // Load acquire.
2475 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2476 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2477 MacroAssembler _masm(&cbuf);
2478 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2479 // Operand 'ds' requires 4-alignment.
2480 assert((Idisp & 0x3) == 0, "unaligned offset");
2481 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2482 __ twi_0($dst$$Register);
2483 __ isync();
2484 %}
2485
2486 enc_class enc_lfd(RegF dst, memory mem) %{
2487 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2488 MacroAssembler _masm(&cbuf);
2489 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2490 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2491 %}
2492
2493 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2494 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2495
2496 MacroAssembler _masm(&cbuf);
2497 int toc_offset = 0;
2498
2499 if (!ra_->C->in_scratch_emit_size()) {
2500 address const_toc_addr;
2501 // Create a non-oop constant, no relocation needed.
2502 // If it is an IC, it has a virtual_call_Relocation.
2503 const_toc_addr = __ long_constant((jlong)$src$$constant);
2504
2505 // Get the constant's TOC offset.
2506 toc_offset = __ offset_to_method_toc(const_toc_addr);
2507
2508 // Keep the current instruction offset in mind.
2509 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2510 }
2511
2512 __ ld($dst$$Register, toc_offset, $toc$$Register);
2513 %}
2514
2515 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2516 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2517
2518 MacroAssembler _masm(&cbuf);
2519
2520 if (!ra_->C->in_scratch_emit_size()) {
2521 address const_toc_addr;
2522 // Create a non-oop constant, no relocation needed.
2523 // If it is an IC, it has a virtual_call_Relocation.
2524 const_toc_addr = __ long_constant((jlong)$src$$constant);
2525
2526 // Get the constant's TOC offset.
2527 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2528 // Store the toc offset of the constant.
2529 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2530
2531 // Also keep the current instruction offset in mind.
2532 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2533 }
2534
2535 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2536 %}
2537
2538 %} // encode
2539
2540 source %{
2541
2542 typedef struct {
2543 loadConL_hiNode *_large_hi;
2544 loadConL_loNode *_large_lo;
2545 loadConLNode *_small;
2546 MachNode *_last;
2547 } loadConLNodesTuple;
2548
2549 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2550 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2551 loadConLNodesTuple nodes;
2552
2553 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2554 if (large_constant_pool) {
2555 // Create new nodes.
2556 loadConL_hiNode *m1 = new (C) loadConL_hiNode();
2557 loadConL_loNode *m2 = new (C) loadConL_loNode();
2558
2559 // inputs for new nodes
2560 m1->add_req(NULL, toc);
2561 m2->add_req(NULL, m1);
2562
2563 // operands for new nodes
2564 m1->_opnds[0] = new (C) iRegLdstOper(); // dst
2565 m1->_opnds[1] = immSrc; // src
2566 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2567 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2568 m2->_opnds[1] = immSrc; // src
2569 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2570
2571 // Initialize ins_attrib TOC fields.
2572 m1->_const_toc_offset = -1;
2573 m2->_const_toc_offset_hi_node = m1;
2574
2575 // Initialize ins_attrib instruction offset.
2576 m1->_cbuf_insts_offset = -1;
2577
2578 // register allocation for new nodes
2579 ra_->set_pair(m1->_idx, reg_second, reg_first);
2580 ra_->set_pair(m2->_idx, reg_second, reg_first);
2581
2582 // Create result.
2583 nodes._large_hi = m1;
2584 nodes._large_lo = m2;
2585 nodes._small = NULL;
2586 nodes._last = nodes._large_lo;
2587 assert(m2->bottom_type()->isa_long(), "must be long");
2588 } else {
2589 loadConLNode *m2 = new (C) loadConLNode();
2590
2591 // inputs for new nodes
2592 m2->add_req(NULL, toc);
2593
2594 // operands for new nodes
2595 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2596 m2->_opnds[1] = immSrc; // src
2597 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2598
2599 // Initialize ins_attrib instruction offset.
2600 m2->_cbuf_insts_offset = -1;
2601
2602 // register allocation for new nodes
2603 ra_->set_pair(m2->_idx, reg_second, reg_first);
2604
2605 // Create result.
2606 nodes._large_hi = NULL;
2607 nodes._large_lo = NULL;
2608 nodes._small = m2;
2609 nodes._last = nodes._small;
2610 assert(m2->bottom_type()->isa_long(), "must be long");
2611 }
2612
2613 return nodes;
2614 }
2615
2616 %} // source
2617
2618 encode %{
2619 // Postalloc expand emitter for loading a long constant from the method's TOC.
2620 // Enc_class needed as consttanttablebase is not supported by postalloc
2621 // expand.
2622 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2623 // Create new nodes.
2624 loadConLNodesTuple loadConLNodes =
2625 loadConLNodesTuple_create(C, ra_, n_toc, op_src,
2626 ra_->get_reg_second(this), ra_->get_reg_first(this));
2627
2628 // Push new nodes.
2629 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2630 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2631
2632 // some asserts
2633 assert(nodes->length() >= 1, "must have created at least 1 node");
2634 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2635 %}
2636
2637 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2638 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2639
2640 MacroAssembler _masm(&cbuf);
2641 int toc_offset = 0;
2642
2643 if (!ra_->C->in_scratch_emit_size()) {
2644 intptr_t val = $src$$constant;
2645 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2646 address const_toc_addr;
2647 if (constant_reloc == relocInfo::oop_type) {
2648 // Create an oop constant and a corresponding relocation.
2649 AddressLiteral a = __ allocate_oop_address((jobject)val);
2650 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2651 __ relocate(a.rspec());
2652 } else if (constant_reloc == relocInfo::metadata_type) {
2653 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2654 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2655 __ relocate(a.rspec());
2656 } else {
2657 // Create a non-oop constant, no relocation needed.
2658 const_toc_addr = __ long_constant((jlong)$src$$constant);
2659 }
2660
2661 // Get the constant's TOC offset.
2662 toc_offset = __ offset_to_method_toc(const_toc_addr);
2663 }
2664
2665 __ ld($dst$$Register, toc_offset, $toc$$Register);
2666 %}
2667
2668 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2669 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2670
2671 MacroAssembler _masm(&cbuf);
2672 if (!ra_->C->in_scratch_emit_size()) {
2673 intptr_t val = $src$$constant;
2674 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2675 address const_toc_addr;
2676 if (constant_reloc == relocInfo::oop_type) {
2677 // Create an oop constant and a corresponding relocation.
2678 AddressLiteral a = __ allocate_oop_address((jobject)val);
2679 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2680 __ relocate(a.rspec());
2681 } else if (constant_reloc == relocInfo::metadata_type) {
2682 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2683 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2684 __ relocate(a.rspec());
2685 } else { // non-oop pointers, e.g. card mark base, heap top
2686 // Create a non-oop constant, no relocation needed.
2687 const_toc_addr = __ long_constant((jlong)$src$$constant);
2688 }
2689
2690 // Get the constant's TOC offset.
2691 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2692 // Store the toc offset of the constant.
2693 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2694 }
2695
2696 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2697 %}
2698
2699 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2700 // Enc_class needed as consttanttablebase is not supported by postalloc
2701 // expand.
2702 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2703 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2704 if (large_constant_pool) {
2705 // Create new nodes.
2706 loadConP_hiNode *m1 = new (C) loadConP_hiNode();
2707 loadConP_loNode *m2 = new (C) loadConP_loNode();
2708
2709 // inputs for new nodes
2710 m1->add_req(NULL, n_toc);
2711 m2->add_req(NULL, m1);
2712
2713 // operands for new nodes
2714 m1->_opnds[0] = new (C) iRegPdstOper(); // dst
2715 m1->_opnds[1] = op_src; // src
2716 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2717 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2718 m2->_opnds[1] = op_src; // src
2719 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2720
2721 // Initialize ins_attrib TOC fields.
2722 m1->_const_toc_offset = -1;
2723 m2->_const_toc_offset_hi_node = m1;
2724
2725 // Register allocation for new nodes.
2726 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2727 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2728
2729 nodes->push(m1);
2730 nodes->push(m2);
2731 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2732 } else {
2733 loadConPNode *m2 = new (C) loadConPNode();
2734
2735 // inputs for new nodes
2736 m2->add_req(NULL, n_toc);
2737
2738 // operands for new nodes
2739 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2740 m2->_opnds[1] = op_src; // src
2741 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2742
2743 // Register allocation for new nodes.
2744 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2745
2746 nodes->push(m2);
2747 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2748 }
2749 %}
2750
2751 // Enc_class needed as consttanttablebase is not supported by postalloc
2752 // expand.
2753 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2754 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2755
2756 MachNode *m2;
2757 if (large_constant_pool) {
2758 m2 = new (C) loadConFCompNode();
2759 } else {
2760 m2 = new (C) loadConFNode();
2761 }
2762 // inputs for new nodes
2763 m2->add_req(NULL, n_toc);
2764
2765 // operands for new nodes
2766 m2->_opnds[0] = op_dst;
2767 m2->_opnds[1] = op_src;
2768 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2769
2770 // register allocation for new nodes
2771 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2772 nodes->push(m2);
2773 %}
2774
2775 // Enc_class needed as consttanttablebase is not supported by postalloc
2776 // expand.
2777 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2778 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2779
2780 MachNode *m2;
2781 if (large_constant_pool) {
2782 m2 = new (C) loadConDCompNode();
2783 } else {
2784 m2 = new (C) loadConDNode();
2785 }
2786 // inputs for new nodes
2787 m2->add_req(NULL, n_toc);
2788
2789 // operands for new nodes
2790 m2->_opnds[0] = op_dst;
2791 m2->_opnds[1] = op_src;
2792 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2793
2794 // register allocation for new nodes
2795 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2796 nodes->push(m2);
2797 %}
2798
2799 enc_class enc_stw(iRegIsrc src, memory mem) %{
2800 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2801 MacroAssembler _masm(&cbuf);
2802 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2803 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2804 %}
2805
2806 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2807 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2808 MacroAssembler _masm(&cbuf);
2809 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2810 // Operand 'ds' requires 4-alignment.
2811 assert((Idisp & 0x3) == 0, "unaligned offset");
2812 __ std($src$$Register, Idisp, $mem$$base$$Register);
2813 %}
2814
2815 enc_class enc_stfs(RegF src, memory mem) %{
2816 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2817 MacroAssembler _masm(&cbuf);
2818 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2819 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2820 %}
2821
2822 enc_class enc_stfd(RegF src, memory mem) %{
2823 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2824 MacroAssembler _masm(&cbuf);
2825 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2826 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2827 %}
2828
2829 // Use release_store for card-marking to ensure that previous
2830 // oop-stores are visible before the card-mark change.
2831 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2832 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2833 // FIXME: Implement this as a cmove and use a fixed condition code
2834 // register which is written on every transition to compiled code,
2835 // e.g. in call-stub and when returning from runtime stubs.
2836 //
2837 // Proposed code sequence for the cmove implementation:
2838 //
2839 // Label skip_release;
2840 // __ beq(CCRfixed, skip_release);
2841 // __ release();
2842 // __ bind(skip_release);
2843 // __ stb(card mark);
2844
2845 MacroAssembler _masm(&cbuf);
2846 Label skip_storestore;
2847
2848 #if 0 // TODO: PPC port
2849 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2850 // StoreStore barrier conditionally.
2851 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2852 __ cmpwi(CCR0, R0, 0);
2853 __ beq_predict_taken(CCR0, skip_storestore);
2854 #endif
2855 __ li(R0, 0);
2856 __ membar(Assembler::StoreStore);
2857 #if 0 // TODO: PPC port
2858 __ bind(skip_storestore);
2859 #endif
2860
2861 // Do the store.
2862 if ($mem$$index == 0) {
2863 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2864 } else {
2865 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2866 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2867 }
2868 %}
2869
2870 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2871
2872 if (VM_Version::has_isel()) {
2873 // use isel instruction with Power 7
2874 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2875 encodeP_subNode *n_sub_base = new (C) encodeP_subNode();
2876 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2877 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode();
2878
2879 n_compare->add_req(n_region, n_src);
2880 n_compare->_opnds[0] = op_crx;
2881 n_compare->_opnds[1] = op_src;
2882 n_compare->_opnds[2] = new (C) immL16Oper(0);
2883
2884 n_sub_base->add_req(n_region, n_src);
2885 n_sub_base->_opnds[0] = op_dst;
2886 n_sub_base->_opnds[1] = op_src;
2887 n_sub_base->_bottom_type = _bottom_type;
2888
2889 n_shift->add_req(n_region, n_sub_base);
2890 n_shift->_opnds[0] = op_dst;
2891 n_shift->_opnds[1] = op_dst;
2892 n_shift->_bottom_type = _bottom_type;
2893
2894 n_cond_set->add_req(n_region, n_compare, n_shift);
2895 n_cond_set->_opnds[0] = op_dst;
2896 n_cond_set->_opnds[1] = op_crx;
2897 n_cond_set->_opnds[2] = op_dst;
2898 n_cond_set->_bottom_type = _bottom_type;
2899
2900 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2901 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2902 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2903 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2904
2905 nodes->push(n_compare);
2906 nodes->push(n_sub_base);
2907 nodes->push(n_shift);
2908 nodes->push(n_cond_set);
2909
2910 } else {
2911 // before Power 7
2912 moveRegNode *n_move = new (C) moveRegNode();
2913 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2914 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2915 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode();
2916
2917 n_move->add_req(n_region, n_src);
2918 n_move->_opnds[0] = op_dst;
2919 n_move->_opnds[1] = op_src;
2920 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2921
2922 n_compare->add_req(n_region, n_src);
2923 n_compare->add_prec(n_move);
2924
2925 n_compare->_opnds[0] = op_crx;
2926 n_compare->_opnds[1] = op_src;
2927 n_compare->_opnds[2] = new (C) immL16Oper(0);
2928
2929 n_sub_base->add_req(n_region, n_compare, n_src);
2930 n_sub_base->_opnds[0] = op_dst;
2931 n_sub_base->_opnds[1] = op_crx;
2932 n_sub_base->_opnds[2] = op_src;
2933 n_sub_base->_bottom_type = _bottom_type;
2934
2935 n_shift->add_req(n_region, n_sub_base);
2936 n_shift->_opnds[0] = op_dst;
2937 n_shift->_opnds[1] = op_dst;
2938 n_shift->_bottom_type = _bottom_type;
2939
2940 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2941 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2942 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2943 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2944
2945 nodes->push(n_move);
2946 nodes->push(n_compare);
2947 nodes->push(n_sub_base);
2948 nodes->push(n_shift);
2949 }
2950
2951 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2952 %}
2953
2954 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2955
2956 encodeP_subNode *n1 = new (C) encodeP_subNode();
2957 n1->add_req(n_region, n_src);
2958 n1->_opnds[0] = op_dst;
2959 n1->_opnds[1] = op_src;
2960 n1->_bottom_type = _bottom_type;
2961
2962 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode();
2963 n2->add_req(n_region, n1);
2964 n2->_opnds[0] = op_dst;
2965 n2->_opnds[1] = op_dst;
2966 n2->_bottom_type = _bottom_type;
2967 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2968 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2969
2970 nodes->push(n1);
2971 nodes->push(n2);
2972 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2973 %}
2974
2975 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2976 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode();
2977 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node();
2978
2979 n_compare->add_req(n_region, n_src);
2980 n_compare->_opnds[0] = op_crx;
2981 n_compare->_opnds[1] = op_src;
2982 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR);
2983
2984 n_shift->add_req(n_region, n_src);
2985 n_shift->_opnds[0] = op_dst;
2986 n_shift->_opnds[1] = op_src;
2987 n_shift->_bottom_type = _bottom_type;
2988
2989 if (VM_Version::has_isel()) {
2990 // use isel instruction with Power 7
2991
2992 decodeN_addNode *n_add_base = new (C) decodeN_addNode();
2993 n_add_base->add_req(n_region, n_shift);
2994 n_add_base->_opnds[0] = op_dst;
2995 n_add_base->_opnds[1] = op_dst;
2996 n_add_base->_bottom_type = _bottom_type;
2997
2998 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode();
2999 n_cond_set->add_req(n_region, n_compare, n_add_base);
3000 n_cond_set->_opnds[0] = op_dst;
3001 n_cond_set->_opnds[1] = op_crx;
3002 n_cond_set->_opnds[2] = op_dst;
3003 n_cond_set->_bottom_type = _bottom_type;
3004
3005 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3006 ra_->set_oop(n_cond_set, true);
3007
3008 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3009 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3010 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3011 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3012
3013 nodes->push(n_compare);
3014 nodes->push(n_shift);
3015 nodes->push(n_add_base);
3016 nodes->push(n_cond_set);
3017
3018 } else {
3019 // before Power 7
3020 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
3021
3022 n_add_base->add_req(n_region, n_compare, n_shift);
3023 n_add_base->_opnds[0] = op_dst;
3024 n_add_base->_opnds[1] = op_crx;
3025 n_add_base->_opnds[2] = op_dst;
3026 n_add_base->_bottom_type = _bottom_type;
3027
3028 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3029 ra_->set_oop(n_add_base, true);
3030
3031 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3032 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3033 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3034
3035 nodes->push(n_compare);
3036 nodes->push(n_shift);
3037 nodes->push(n_add_base);
3038 }
3039 %}
3040
3041 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3042 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode();
3043 n1->add_req(n_region, n_src);
3044 n1->_opnds[0] = op_dst;
3045 n1->_opnds[1] = op_src;
3046 n1->_bottom_type = _bottom_type;
3047
3048 decodeN_addNode *n2 = new (C) decodeN_addNode();
3049 n2->add_req(n_region, n1);
3050 n2->_opnds[0] = op_dst;
3051 n2->_opnds[1] = op_dst;
3052 n2->_bottom_type = _bottom_type;
3053 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3054 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3055
3056 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3057 ra_->set_oop(n2, true);
3058
3059 nodes->push(n1);
3060 nodes->push(n2);
3061 %}
3062
3063 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3064 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3065
3066 MacroAssembler _masm(&cbuf);
3067 int cc = $cmp$$cmpcode;
3068 int flags_reg = $crx$$reg;
3069 Label done;
3070 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3071 // Branch if not (cmp crx).
3072 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3073 __ mr($dst$$Register, $src$$Register);
3074 // TODO PPC port __ endgroup_if_needed(_size == 12);
3075 __ bind(done);
3076 %}
3077
3078 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3079 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3080
3081 MacroAssembler _masm(&cbuf);
3082 Label done;
3083 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3084 // Branch if not (cmp crx).
3085 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3086 __ li($dst$$Register, $src$$constant);
3087 // TODO PPC port __ endgroup_if_needed(_size == 12);
3088 __ bind(done);
3089 %}
3090
3091 // New atomics.
3092 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3093 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3094
3095 MacroAssembler _masm(&cbuf);
3096 Register Rtmp = R0;
3097 Register Rres = $res$$Register;
3098 Register Rsrc = $src$$Register;
3099 Register Rptr = $mem_ptr$$Register;
3100 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3101 Register Rold = RegCollision ? Rtmp : Rres;
3102
3103 Label Lretry;
3104 __ bind(Lretry);
3105 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3106 __ add(Rtmp, Rsrc, Rold);
3107 __ stwcx_(Rtmp, Rptr);
3108 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3109 __ bne_predict_not_taken(CCR0, Lretry);
3110 } else {
3111 __ bne( CCR0, Lretry);
3112 }
3113 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3114 __ fence();
3115 %}
3116
3117 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3118 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3119
3120 MacroAssembler _masm(&cbuf);
3121 Register Rtmp = R0;
3122 Register Rres = $res$$Register;
3123 Register Rsrc = $src$$Register;
3124 Register Rptr = $mem_ptr$$Register;
3125 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3126 Register Rold = RegCollision ? Rtmp : Rres;
3127
3128 Label Lretry;
3129 __ bind(Lretry);
3130 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3131 __ add(Rtmp, Rsrc, Rold);
3132 __ stdcx_(Rtmp, Rptr);
3133 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3134 __ bne_predict_not_taken(CCR0, Lretry);
3135 } else {
3136 __ bne( CCR0, Lretry);
3137 }
3138 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3139 __ fence();
3140 %}
3141
3142 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3143 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3144
3145 MacroAssembler _masm(&cbuf);
3146 Register Rtmp = R0;
3147 Register Rres = $res$$Register;
3148 Register Rsrc = $src$$Register;
3149 Register Rptr = $mem_ptr$$Register;
3150 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3151 Register Rold = RegCollision ? Rtmp : Rres;
3152
3153 Label Lretry;
3154 __ bind(Lretry);
3155 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3156 __ stwcx_(Rsrc, Rptr);
3157 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3158 __ bne_predict_not_taken(CCR0, Lretry);
3159 } else {
3160 __ bne( CCR0, Lretry);
3161 }
3162 if (RegCollision) __ mr(Rres, Rtmp);
3163 __ fence();
3164 %}
3165
3166 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3167 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3168
3169 MacroAssembler _masm(&cbuf);
3170 Register Rtmp = R0;
3171 Register Rres = $res$$Register;
3172 Register Rsrc = $src$$Register;
3173 Register Rptr = $mem_ptr$$Register;
3174 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3175 Register Rold = RegCollision ? Rtmp : Rres;
3176
3177 Label Lretry;
3178 __ bind(Lretry);
3179 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3180 __ stdcx_(Rsrc, Rptr);
3181 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3182 __ bne_predict_not_taken(CCR0, Lretry);
3183 } else {
3184 __ bne( CCR0, Lretry);
3185 }
3186 if (RegCollision) __ mr(Rres, Rtmp);
3187 __ fence();
3188 %}
3189
3190 // This enc_class is needed so that scheduler gets proper
3191 // input mapping for latency computation.
3192 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3193 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3194 MacroAssembler _masm(&cbuf);
3195 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3196 %}
3197
3198 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3199 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3200
3201 MacroAssembler _masm(&cbuf);
3202
3203 Label done;
3204 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3205 __ li($dst$$Register, $zero$$constant);
3206 __ beq($crx$$CondRegister, done);
3207 __ li($dst$$Register, $notzero$$constant);
3208 __ bind(done);
3209 %}
3210
3211 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3212 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3213
3214 MacroAssembler _masm(&cbuf);
3215
3216 Label done;
3217 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3218 __ li($dst$$Register, $zero$$constant);
3219 __ beq($crx$$CondRegister, done);
3220 __ li($dst$$Register, $notzero$$constant);
3221 __ bind(done);
3222 %}
3223
3224 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3225 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3226
3227 MacroAssembler _masm(&cbuf);
3228 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3229 Label done;
3230 __ bso($crx$$CondRegister, done);
3231 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3232 // TODO PPC port __ endgroup_if_needed(_size == 12);
3233 __ bind(done);
3234 %}
3235
3236 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3237 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3238
3239 MacroAssembler _masm(&cbuf);
3240 Label d; // dummy
3241 __ bind(d);
3242 Label* p = ($lbl$$label);
3243 // `p' is `NULL' when this encoding class is used only to
3244 // determine the size of the encoded instruction.
3245 Label& l = (NULL == p)? d : *(p);
3246 int cc = $cmp$$cmpcode;
3247 int flags_reg = $crx$$reg;
3248 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3249 int bhint = Assembler::bhintNoHint;
3250
3251 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3252 if (_prob <= PROB_NEVER) {
3253 bhint = Assembler::bhintIsNotTaken;
3254 } else if (_prob >= PROB_ALWAYS) {
3255 bhint = Assembler::bhintIsTaken;
3256 }
3257 }
3258
3259 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3260 cc_to_biint(cc, flags_reg),
3261 l);
3262 %}
3263
3264 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3265 // The scheduler doesn't know about branch shortening, so we set the opcode
3266 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3267 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3268
3269 MacroAssembler _masm(&cbuf);
3270 Label d; // dummy
3271 __ bind(d);
3272 Label* p = ($lbl$$label);
3273 // `p' is `NULL' when this encoding class is used only to
3274 // determine the size of the encoded instruction.
3275 Label& l = (NULL == p)? d : *(p);
3276 int cc = $cmp$$cmpcode;
3277 int flags_reg = $crx$$reg;
3278 int bhint = Assembler::bhintNoHint;
3279
3280 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3281 if (_prob <= PROB_NEVER) {
3282 bhint = Assembler::bhintIsNotTaken;
3283 } else if (_prob >= PROB_ALWAYS) {
3284 bhint = Assembler::bhintIsTaken;
3285 }
3286 }
3287
3288 // Tell the conditional far branch to optimize itself when being relocated.
3289 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3290 cc_to_biint(cc, flags_reg),
3291 l,
3292 MacroAssembler::bc_far_optimize_on_relocate);
3293 %}
3294
3295 // Branch used with Power6 scheduling (can be shortened without changing the node).
3296 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3297 // The scheduler doesn't know about branch shortening, so we set the opcode
3298 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3299 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3300
3301 MacroAssembler _masm(&cbuf);
3302 Label d; // dummy
3303 __ bind(d);
3304 Label* p = ($lbl$$label);
3305 // `p' is `NULL' when this encoding class is used only to
3306 // determine the size of the encoded instruction.
3307 Label& l = (NULL == p)? d : *(p);
3308 int cc = $cmp$$cmpcode;
3309 int flags_reg = $crx$$reg;
3310 int bhint = Assembler::bhintNoHint;
3311
3312 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3313 if (_prob <= PROB_NEVER) {
3314 bhint = Assembler::bhintIsNotTaken;
3315 } else if (_prob >= PROB_ALWAYS) {
3316 bhint = Assembler::bhintIsTaken;
3317 }
3318 }
3319
3320 #if 0 // TODO: PPC port
3321 if (_size == 8) {
3322 // Tell the conditional far branch to optimize itself when being relocated.
3323 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3324 cc_to_biint(cc, flags_reg),
3325 l,
3326 MacroAssembler::bc_far_optimize_on_relocate);
3327 } else {
3328 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3329 cc_to_biint(cc, flags_reg),
3330 l);
3331 }
3332 #endif
3333 Unimplemented();
3334 %}
3335
3336 // Postalloc expand emitter for loading a replicatef float constant from
3337 // the method's TOC.
3338 // Enc_class needed as consttanttablebase is not supported by postalloc
3339 // expand.
3340 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3341 // Create new nodes.
3342
3343 // Make an operand with the bit pattern to load as float.
3344 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF()));
3345
3346 loadConLNodesTuple loadConLNodes =
3347 loadConLNodesTuple_create(C, ra_, n_toc, op_repl,
3348 ra_->get_reg_second(this), ra_->get_reg_first(this));
3349
3350 // Push new nodes.
3351 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3352 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3353
3354 assert(nodes->length() >= 1, "must have created at least 1 node");
3355 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3356 %}
3357
3358 // This enc_class is needed so that scheduler gets proper
3359 // input mapping for latency computation.
3360 enc_class enc_poll(immI dst, iRegLdst poll) %{
3361 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3362 // Fake operand dst needed for PPC scheduler.
3363 assert($dst$$constant == 0x0, "dst must be 0x0");
3364
3365 MacroAssembler _masm(&cbuf);
3366 // Mark the code position where the load from the safepoint
3367 // polling page was emitted as relocInfo::poll_type.
3368 __ relocate(relocInfo::poll_type);
3369 __ load_from_polling_page($poll$$Register);
3370 %}
3371
3372 // A Java static call or a runtime call.
3373 //
3374 // Branch-and-link relative to a trampoline.
3375 // The trampoline loads the target address and does a long branch to there.
3376 // In case we call java, the trampoline branches to a interpreter_stub
3377 // which loads the inline cache and the real call target from the constant pool.
3378 //
3379 // This basically looks like this:
3380 //
3381 // >>>> consts -+ -+
3382 // | |- offset1
3383 // [call target1] | <-+
3384 // [IC cache] |- offset2
3385 // [call target2] <--+
3386 //
3387 // <<<< consts
3388 // >>>> insts
3389 //
3390 // bl offset16 -+ -+ ??? // How many bits available?
3391 // | |
3392 // <<<< insts | |
3393 // >>>> stubs | |
3394 // | |- trampoline_stub_Reloc
3395 // trampoline stub: | <-+
3396 // r2 = toc |
3397 // r2 = [r2 + offset1] | // Load call target1 from const section
3398 // mtctr r2 |
3399 // bctr |- static_stub_Reloc
3400 // comp_to_interp_stub: <---+
3401 // r1 = toc
3402 // ICreg = [r1 + IC_offset] // Load IC from const section
3403 // r1 = [r1 + offset2] // Load call target2 from const section
3404 // mtctr r1
3405 // bctr
3406 //
3407 // <<<< stubs
3408 //
3409 // The call instruction in the code either
3410 // - Branches directly to a compiled method if the offset is encodable in instruction.
3411 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3412 // - Branches to the compiled_to_interp stub if the target is interpreted.
3413 //
3414 // Further there are three relocations from the loads to the constants in
3415 // the constant section.
3416 //
3417 // Usage of r1 and r2 in the stubs allows to distinguish them.
3418 enc_class enc_java_static_call(method meth) %{
3419 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3420
3421 MacroAssembler _masm(&cbuf);
3422 address entry_point = (address)$meth$$method;
3423
3424 if (!_method) {
3425 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3426 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3427 } else {
3428 // Remember the offset not the address.
3429 const int start_offset = __ offset();
3430 // The trampoline stub.
3431 if (!Compile::current()->in_scratch_emit_size()) {
3432 // No entry point given, use the current pc.
3433 // Make sure branch fits into
3434 if (entry_point == 0) entry_point = __ pc();
3435
3436 // Put the entry point as a constant into the constant pool.
3437 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3438 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3439
3440 // Emit the trampoline stub which will be related to the branch-and-link below.
3441 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3442 __ relocate(_optimized_virtual ?
3443 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3444 }
3445
3446 // The real call.
3447 // Note: At this point we do not have the address of the trampoline
3448 // stub, and the entry point might be too far away for bl, so __ pc()
3449 // serves as dummy and the bl will be patched later.
3450 cbuf.set_insts_mark();
3451 __ bl(__ pc()); // Emits a relocation.
3452
3453 // The stub for call to interpreter.
3454 CompiledStaticCall::emit_to_interp_stub(cbuf);
3455 }
3456 %}
3457
3458 // Emit a method handle call.
3459 //
3460 // Method handle calls from compiled to compiled are going thru a
3461 // c2i -> i2c adapter, extending the frame for their arguments. The
3462 // caller however, returns directly to the compiled callee, that has
3463 // to cope with the extended frame. We restore the original frame by
3464 // loading the callers sp and adding the calculated framesize.
3465 enc_class enc_java_handle_call(method meth) %{
3466 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3467
3468 MacroAssembler _masm(&cbuf);
3469 address entry_point = (address)$meth$$method;
3470
3471 // Remember the offset not the address.
3472 const int start_offset = __ offset();
3473 // The trampoline stub.
3474 if (!ra_->C->in_scratch_emit_size()) {
3475 // No entry point given, use the current pc.
3476 // Make sure branch fits into
3477 if (entry_point == 0) entry_point = __ pc();
3478
3479 // Put the entry point as a constant into the constant pool.
3480 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3481 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3482
3483 // Emit the trampoline stub which will be related to the branch-and-link below.
3484 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3485 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3486 __ relocate(relocInfo::opt_virtual_call_type);
3487 }
3488
3489 // The real call.
3490 // Note: At this point we do not have the address of the trampoline
3491 // stub, and the entry point might be too far away for bl, so __ pc()
3492 // serves as dummy and the bl will be patched later.
3493 cbuf.set_insts_mark();
3494 __ bl(__ pc()); // Emits a relocation.
3495
3496 assert(_method, "execute next statement conditionally");
3497 // The stub for call to interpreter.
3498 CompiledStaticCall::emit_to_interp_stub(cbuf);
3499
3500 // Restore original sp.
3501 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3502 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3503 unsigned int bytes = (unsigned int)framesize;
3504 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3505 if (Assembler::is_simm(-offset, 16)) {
3506 __ addi(R1_SP, R11_scratch1, -offset);
3507 } else {
3508 __ load_const_optimized(R12_scratch2, -offset);
3509 __ add(R1_SP, R11_scratch1, R12_scratch2);
3510 }
3511 #ifdef ASSERT
3512 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3513 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3514 __ asm_assert_eq("backlink changed", 0x8000);
3515 #endif
3516 // If fails should store backlink before unextending.
3517
3518 if (ra_->C->env()->failing()) {
3519 return;
3520 }
3521 %}
3522
3523 // Second node of expanded dynamic call - the call.
3524 enc_class enc_java_dynamic_call_sched(method meth) %{
3525 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3526
3527 MacroAssembler _masm(&cbuf);
3528
3529 if (!ra_->C->in_scratch_emit_size()) {
3530 // Create a call trampoline stub for the given method.
3531 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3532 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3533 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3534 emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3535
3536 if (ra_->C->env()->failing())
3537 return;
3538
3539 // Build relocation at call site with ic position as data.
3540 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3541 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3542 "must have one, but can't have both");
3543 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3544 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3545 "must contain instruction offset");
3546 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3547 ? _load_ic_hi_node->_cbuf_insts_offset
3548 : _load_ic_node->_cbuf_insts_offset;
3549 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3550 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3551 "should be load from TOC");
3552
3553 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3554 }
3555
3556 // At this point I do not have the address of the trampoline stub,
3557 // and the entry point might be too far away for bl. Pc() serves
3558 // as dummy and bl will be patched later.
3559 __ bl((address) __ pc());
3560 %}
3561
3562 // postalloc expand emitter for virtual calls.
3563 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3564
3565 // Create the nodes for loading the IC from the TOC.
3566 loadConLNodesTuple loadConLNodes_IC =
3567 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()),
3568 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3569
3570 // Create the call node.
3571 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode();
3572 call->_method_handle_invoke = _method_handle_invoke;
3573 call->_vtable_index = _vtable_index;
3574 call->_method = _method;
3575 call->_bci = _bci;
3576 call->_optimized_virtual = _optimized_virtual;
3577 call->_tf = _tf;
3578 call->_entry_point = _entry_point;
3579 call->_cnt = _cnt;
3580 call->_argsize = _argsize;
3581 call->_oop_map = _oop_map;
3582 call->_jvms = _jvms;
3583 call->_jvmadj = _jvmadj;
3584 call->_in_rms = _in_rms;
3585 call->_nesting = _nesting;
3586
3587 // New call needs all inputs of old call.
3588 // Req...
3589 for (uint i = 0; i < req(); ++i) {
3590 // The expanded node does not need toc any more.
3591 // Add the inline cache constant here instead. This expresses the
3592 // register of the inline cache must be live at the call.
3593 // Else we would have to adapt JVMState by -1.
3594 if (i == mach_constant_base_node_input()) {
3595 call->add_req(loadConLNodes_IC._last);
3596 } else {
3597 call->add_req(in(i));
3598 }
3599 }
3600 // ...as well as prec
3601 for (uint i = req(); i < len(); ++i) {
3602 call->add_prec(in(i));
3603 }
3604
3605 // Remember nodes loading the inline cache into r19.
3606 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3607 call->_load_ic_node = loadConLNodes_IC._small;
3608
3609 // Operands for new nodes.
3610 call->_opnds[0] = _opnds[0];
3611 call->_opnds[1] = _opnds[1];
3612
3613 // Only the inline cache is associated with a register.
3614 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3615
3616 // Push new nodes.
3617 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3618 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3619 nodes->push(call);
3620 %}
3621
3622 // Compound version of call dynamic
3623 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3624 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3625 MacroAssembler _masm(&cbuf);
3626 int start_offset = __ offset();
3627
3628 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3629 #if 0
3630 if (_vtable_index < 0) {
3631 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3632 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3633 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3634 AddressLiteral meta = __ allocate_metadata_address((Metadata *)Universe::non_oop_word());
3635
3636 address virtual_call_meta_addr = __ pc();
3637 __ load_const_from_method_toc(ic_reg, meta, Rtoc);
3638 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3639 // to determine who we intended to call.
3640 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3641 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3642 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3643 "Fix constant in ret_addr_offset()");
3644 } else {
3645 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3646 // Go thru the vtable. Get receiver klass. Receiver already
3647 // checked for non-null. If we'll go thru a C2I adapter, the
3648 // interpreter expects method in R19_method.
3649
3650 __ load_klass(R11_scratch1, R3);
3651
3652 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3653 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3654 __ li(R19_method, v_off);
3655 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3656 // NOTE: for vtable dispatches, the vtable entry will never be
3657 // null. However it may very well end up in handle_wrong_method
3658 // if the method is abstract for the particular class.
3659 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3660 // Call target. Either compiled code or C2I adapter.
3661 __ mtctr(R11_scratch1);
3662 __ bctrl();
3663 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3664 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3665 }
3666 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3667 "Fix constant in ret_addr_offset()");
3668 }
3669 #endif
3670 guarantee(0, "Fix handling of toc edge: messes up derived/base pairs.");
3671 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3672 %}
3673
3674 // a runtime call
3675 enc_class enc_java_to_runtime_call (method meth) %{
3676 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3677
3678 MacroAssembler _masm(&cbuf);
3679 const address start_pc = __ pc();
3680
3681 #if defined(ABI_ELFv2)
3682 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3683 __ call_c(entry, relocInfo::runtime_call_type);
3684 #else
3685 // The function we're going to call.
3686 FunctionDescriptor fdtemp;
3687 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3688
3689 Register Rtoc = R12_scratch2;
3690 // Calculate the method's TOC.
3691 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3692 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3693 // pool entries; call_c_using_toc will optimize the call.
3694 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3695 #endif
3696
3697 // Check the ret_addr_offset.
3698 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3699 "Fix constant in ret_addr_offset()");
3700 %}
3701
3702 // Move to ctr for leaf call.
3703 // This enc_class is needed so that scheduler gets proper
3704 // input mapping for latency computation.
3705 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3706 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3707 MacroAssembler _masm(&cbuf);
3708 __ mtctr($src$$Register);
3709 %}
3710
3711 // Postalloc expand emitter for runtime leaf calls.
3712 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3713 loadConLNodesTuple loadConLNodes_Entry;
3714 #if defined(ABI_ELFv2)
3715 jlong entry_address = (jlong) this->entry_point();
3716 assert(entry_address, "need address here");
3717 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3718 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3719 #else
3720 // Get the struct that describes the function we are about to call.
3721 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3722 assert(fd, "need fd here");
3723 jlong entry_address = (jlong) fd->entry();
3724 // new nodes
3725 loadConLNodesTuple loadConLNodes_Env;
3726 loadConLNodesTuple loadConLNodes_Toc;
3727
3728 // Create nodes and operands for loading the entry point.
3729 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3730 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3731
3732
3733 // Create nodes and operands for loading the env pointer.
3734 if (fd->env() != NULL) {
3735 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()),
3736 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3737 } else {
3738 loadConLNodes_Env._large_hi = NULL;
3739 loadConLNodes_Env._large_lo = NULL;
3740 loadConLNodes_Env._small = NULL;
3741 loadConLNodes_Env._last = new (C) loadConL16Node();
3742 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper();
3743 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0);
3744 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3745 }
3746
3747 // Create nodes and operands for loading the Toc point.
3748 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()),
3749 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3750 #endif // ABI_ELFv2
3751 // mtctr node
3752 MachNode *mtctr = new (C) CallLeafDirect_mtctrNode();
3753
3754 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3755 mtctr->add_req(0, loadConLNodes_Entry._last);
3756
3757 mtctr->_opnds[0] = new (C) iRegLdstOper();
3758 mtctr->_opnds[1] = new (C) iRegLdstOper();
3759
3760 // call node
3761 MachCallLeafNode *call = new (C) CallLeafDirectNode();
3762
3763 call->_opnds[0] = _opnds[0];
3764 call->_opnds[1] = new (C) methodOper((intptr_t) entry_address); // May get set later.
3765
3766 // Make the new call node look like the old one.
3767 call->_name = _name;
3768 call->_tf = _tf;
3769 call->_entry_point = _entry_point;
3770 call->_cnt = _cnt;
3771 call->_argsize = _argsize;
3772 call->_oop_map = _oop_map;
3773 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3774 call->_jvms = NULL;
3775 call->_jvmadj = _jvmadj;
3776 call->_in_rms = _in_rms;
3777 call->_nesting = _nesting;
3778
3779
3780 // New call needs all inputs of old call.
3781 // Req...
3782 for (uint i = 0; i < req(); ++i) {
3783 if (i != mach_constant_base_node_input()) {
3784 call->add_req(in(i));
3785 }
3786 }
3787
3788 // These must be reqired edges, as the registers are live up to
3789 // the call. Else the constants are handled as kills.
3790 call->add_req(mtctr);
3791 #if !defined(ABI_ELFv2)
3792 call->add_req(loadConLNodes_Env._last);
3793 call->add_req(loadConLNodes_Toc._last);
3794 #endif
3795
3796 // ...as well as prec
3797 for (uint i = req(); i < len(); ++i) {
3798 call->add_prec(in(i));
3799 }
3800
3801 // registers
3802 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3803
3804 // Insert the new nodes.
3805 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3806 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3807 #if !defined(ABI_ELFv2)
3808 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3809 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3810 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3811 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3812 #endif
3813 nodes->push(mtctr);
3814 nodes->push(call);
3815 %}
3816 %}
3817
3818 //----------FRAME--------------------------------------------------------------
3819 // Definition of frame structure and management information.
3820
3821 frame %{
3822 // What direction does stack grow in (assumed to be same for native & Java).
3823 stack_direction(TOWARDS_LOW);
3824
3825 // These two registers define part of the calling convention between
3826 // compiled code and the interpreter.
3827
3828 // Inline Cache Register or method for I2C.
3829 inline_cache_reg(R19); // R19_method
3830
3831 // Method Oop Register when calling interpreter.
3832 interpreter_method_oop_reg(R19); // R19_method
3833
3834 // Optional: name the operand used by cisc-spilling to access
3835 // [stack_pointer + offset].
3836 cisc_spilling_operand_name(indOffset);
3837
3838 // Number of stack slots consumed by a Monitor enter.
3839 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3840
3841 // Compiled code's Frame Pointer.
3842 frame_pointer(R1); // R1_SP
3843
3844 // Interpreter stores its frame pointer in a register which is
3845 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3846 // interpreted java to compiled java.
3847 //
3848 // R14_state holds pointer to caller's cInterpreter.
3849 interpreter_frame_pointer(R14); // R14_state
3850
3851 stack_alignment(frame::alignment_in_bytes);
3852
3853 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3854
3855 // Number of outgoing stack slots killed above the
3856 // out_preserve_stack_slots for calls to C. Supports the var-args
3857 // backing area for register parms.
3858 //
3859 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3860
3861 // The after-PROLOG location of the return address. Location of
3862 // return address specifies a type (REG or STACK) and a number
3863 // representing the register number (i.e. - use a register name) or
3864 // stack slot.
3865 //
3866 // A: Link register is stored in stack slot ...
3867 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3868 // J: Therefore, we make sure that the link register is also in R11_scratch1
3869 // at the end of the prolog.
3870 // B: We use R20, now.
3871 //return_addr(REG R20);
3872
3873 // G: After reading the comments made by all the luminaries on their
3874 // failure to tell the compiler where the return address really is,
3875 // I hardly dare to try myself. However, I'm convinced it's in slot
3876 // 4 what apparently works and saves us some spills.
3877 return_addr(STACK 4);
3878
3879 // This is the body of the function
3880 //
3881 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3882 // uint length, // length of array
3883 // bool is_outgoing)
3884 //
3885 // The `sig' array is to be updated. sig[j] represents the location
3886 // of the j-th argument, either a register or a stack slot.
3887
3888 // Comment taken from i486.ad:
3889 // Body of function which returns an integer array locating
3890 // arguments either in registers or in stack slots. Passed an array
3891 // of ideal registers called "sig" and a "length" count. Stack-slot
3892 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3893 // arguments for a CALLEE. Incoming stack arguments are
3894 // automatically biased by the preserve_stack_slots field above.
3895 calling_convention %{
3896 // No difference between ingoing/outgoing. Just pass false.
3897 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3898 %}
3899
3900 // Comment taken from i486.ad:
3901 // Body of function which returns an integer array locating
3902 // arguments either in registers or in stack slots. Passed an array
3903 // of ideal registers called "sig" and a "length" count. Stack-slot
3904 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3905 // arguments for a CALLEE. Incoming stack arguments are
3906 // automatically biased by the preserve_stack_slots field above.
3907 c_calling_convention %{
3908 // This is obviously always outgoing.
3909 // C argument in register AND stack slot.
3910 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3911 %}
3912
3913 // Location of native (C/C++) and interpreter return values. This
3914 // is specified to be the same as Java. In the 32-bit VM, long
3915 // values are actually returned from native calls in O0:O1 and
3916 // returned to the interpreter in I0:I1. The copying to and from
3917 // the register pairs is done by the appropriate call and epilog
3918 // opcodes. This simplifies the register allocator.
3919 c_return_value %{
3920 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3921 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3922 "only return normal values");
3923 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3924 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3925 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3926 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3927 %}
3928
3929 // Location of compiled Java return values. Same as C
3930 return_value %{
3931 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3932 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3933 "only return normal values");
3934 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3935 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3936 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3937 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3938 %}
3939 %}
3940
3941
3942 //----------ATTRIBUTES---------------------------------------------------------
3943
3944 //----------Operand Attributes-------------------------------------------------
3945 op_attrib op_cost(1); // Required cost attribute.
3946
3947 //----------Instruction Attributes---------------------------------------------
3948
3949 // Cost attribute. required.
3950 ins_attrib ins_cost(DEFAULT_COST);
3951
3952 // Is this instruction a non-matching short branch variant of some
3953 // long branch? Not required.
3954 ins_attrib ins_short_branch(0);
3955
3956 ins_attrib ins_is_TrapBasedCheckNode(true);
3957
3958 // Number of constants.
3959 // This instruction uses the given number of constants
3960 // (optional attribute).
3961 // This is needed to determine in time whether the constant pool will
3962 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3963 // is determined. It's also used to compute the constant pool size
3964 // in Output().
3965 ins_attrib ins_num_consts(0);
3966
3967 // Required alignment attribute (must be a power of 2) specifies the
3968 // alignment that some part of the instruction (not necessarily the
3969 // start) requires. If > 1, a compute_padding() function must be
3970 // provided for the instruction.
3971 ins_attrib ins_alignment(1);
3972
3973 // Enforce/prohibit rematerializations.
3974 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3975 // then rematerialization of that instruction is prohibited and the
3976 // instruction's value will be spilled if necessary.
3977 // Causes that MachNode::rematerialize() returns false.
3978 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3979 // then rematerialization should be enforced and a copy of the instruction
3980 // should be inserted if possible; rematerialization is not guaranteed.
3981 // Note: this may result in rematerializations in front of every use.
3982 // Causes that MachNode::rematerialize() can return true.
3983 // (optional attribute)
3984 ins_attrib ins_cannot_rematerialize(false);
3985 ins_attrib ins_should_rematerialize(false);
3986
3987 // Instruction has variable size depending on alignment.
3988 ins_attrib ins_variable_size_depending_on_alignment(false);
3989
3990 // Instruction is a nop.
3991 ins_attrib ins_is_nop(false);
3992
3993 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3994 ins_attrib ins_use_mach_if_fast_lock_node(false);
3995
3996 // Field for the toc offset of a constant.
3997 //
3998 // This is needed if the toc offset is not encodable as an immediate in
3999 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4000 // added to the toc, and from this a load with immediate is performed.
4001 // With postalloc expand, we get two nodes that require the same offset
4002 // but which don't know about each other. The offset is only known
4003 // when the constant is added to the constant pool during emitting.
4004 // It is generated in the 'hi'-node adding the upper bits, and saved
4005 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
4006 // the offset from there when it gets encoded.
4007 ins_attrib ins_field_const_toc_offset(0);
4008 ins_attrib ins_field_const_toc_offset_hi_node(0);
4009
4010 // A field that can hold the instructions offset in the code buffer.
4011 // Set in the nodes emitter.
4012 ins_attrib ins_field_cbuf_insts_offset(-1);
4013
4014 // Fields for referencing a call's load-IC-node.
4015 // If the toc offset can not be encoded as an immediate in a load, we
4016 // use two nodes.
4017 ins_attrib ins_field_load_ic_hi_node(0);
4018 ins_attrib ins_field_load_ic_node(0);
4019
4020 //----------OPERANDS-----------------------------------------------------------
4021 // Operand definitions must precede instruction definitions for correct
4022 // parsing in the ADLC because operands constitute user defined types
4023 // which are used in instruction definitions.
4024 //
4025 // Formats are generated automatically for constants and base registers.
4026
4027 //----------Simple Operands----------------------------------------------------
4028 // Immediate Operands
4029
4030 // Integer Immediate: 32-bit
4031 operand immI() %{
4032 match(ConI);
4033 op_cost(40);
4034 format %{ %}
4035 interface(CONST_INTER);
4036 %}
4037
4038 operand immI8() %{
4039 predicate(Assembler::is_simm(n->get_int(), 8));
4040 op_cost(0);
4041 match(ConI);
4042 format %{ %}
4043 interface(CONST_INTER);
4044 %}
4045
4046 // Integer Immediate: 16-bit
4047 operand immI16() %{
4048 predicate(Assembler::is_simm(n->get_int(), 16));
4049 op_cost(0);
4050 match(ConI);
4051 format %{ %}
4052 interface(CONST_INTER);
4053 %}
4054
4055 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4056 operand immIhi16() %{
4057 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4058 match(ConI);
4059 op_cost(0);
4060 format %{ %}
4061 interface(CONST_INTER);
4062 %}
4063
4064 operand immInegpow2() %{
4065 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4066 match(ConI);
4067 op_cost(0);
4068 format %{ %}
4069 interface(CONST_INTER);
4070 %}
4071
4072 operand immIpow2minus1() %{
4073 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4074 match(ConI);
4075 op_cost(0);
4076 format %{ %}
4077 interface(CONST_INTER);
4078 %}
4079
4080 operand immIpowerOf2() %{
4081 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4082 match(ConI);
4083 op_cost(0);
4084 format %{ %}
4085 interface(CONST_INTER);
4086 %}
4087
4088 // Unsigned Integer Immediate: the values 0-31
4089 operand uimmI5() %{
4090 predicate(Assembler::is_uimm(n->get_int(), 5));
4091 match(ConI);
4092 op_cost(0);
4093 format %{ %}
4094 interface(CONST_INTER);
4095 %}
4096
4097 // Unsigned Integer Immediate: 6-bit
4098 operand uimmI6() %{
4099 predicate(Assembler::is_uimm(n->get_int(), 6));
4100 match(ConI);
4101 op_cost(0);
4102 format %{ %}
4103 interface(CONST_INTER);
4104 %}
4105
4106 // Unsigned Integer Immediate: 6-bit int, greater than 32
4107 operand uimmI6_ge32() %{
4108 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4109 match(ConI);
4110 op_cost(0);
4111 format %{ %}
4112 interface(CONST_INTER);
4113 %}
4114
4115 // Unsigned Integer Immediate: 15-bit
4116 operand uimmI15() %{
4117 predicate(Assembler::is_uimm(n->get_int(), 15));
4118 match(ConI);
4119 op_cost(0);
4120 format %{ %}
4121 interface(CONST_INTER);
4122 %}
4123
4124 // Unsigned Integer Immediate: 16-bit
4125 operand uimmI16() %{
4126 predicate(Assembler::is_uimm(n->get_int(), 16));
4127 match(ConI);
4128 op_cost(0);
4129 format %{ %}
4130 interface(CONST_INTER);
4131 %}
4132
4133 // constant 'int 0'.
4134 operand immI_0() %{
4135 predicate(n->get_int() == 0);
4136 match(ConI);
4137 op_cost(0);
4138 format %{ %}
4139 interface(CONST_INTER);
4140 %}
4141
4142 // constant 'int 1'.
4143 operand immI_1() %{
4144 predicate(n->get_int() == 1);
4145 match(ConI);
4146 op_cost(0);
4147 format %{ %}
4148 interface(CONST_INTER);
4149 %}
4150
4151 // constant 'int -1'.
4152 operand immI_minus1() %{
4153 predicate(n->get_int() == -1);
4154 match(ConI);
4155 op_cost(0);
4156 format %{ %}
4157 interface(CONST_INTER);
4158 %}
4159
4160 // int value 16.
4161 operand immI_16() %{
4162 predicate(n->get_int() == 16);
4163 match(ConI);
4164 op_cost(0);
4165 format %{ %}
4166 interface(CONST_INTER);
4167 %}
4168
4169 // int value 24.
4170 operand immI_24() %{
4171 predicate(n->get_int() == 24);
4172 match(ConI);
4173 op_cost(0);
4174 format %{ %}
4175 interface(CONST_INTER);
4176 %}
4177
4178 // Compressed oops constants
4179 // Pointer Immediate
4180 operand immN() %{
4181 match(ConN);
4182
4183 op_cost(10);
4184 format %{ %}
4185 interface(CONST_INTER);
4186 %}
4187
4188 // NULL Pointer Immediate
4189 operand immN_0() %{
4190 predicate(n->get_narrowcon() == 0);
4191 match(ConN);
4192
4193 op_cost(0);
4194 format %{ %}
4195 interface(CONST_INTER);
4196 %}
4197
4198 // Compressed klass constants
4199 operand immNKlass() %{
4200 match(ConNKlass);
4201
4202 op_cost(0);
4203 format %{ %}
4204 interface(CONST_INTER);
4205 %}
4206
4207 // This operand can be used to avoid matching of an instruct
4208 // with chain rule.
4209 operand immNKlass_NM() %{
4210 match(ConNKlass);
4211 predicate(false);
4212 op_cost(0);
4213 format %{ %}
4214 interface(CONST_INTER);
4215 %}
4216
4217 // Pointer Immediate: 64-bit
4218 operand immP() %{
4219 match(ConP);
4220 op_cost(0);
4221 format %{ %}
4222 interface(CONST_INTER);
4223 %}
4224
4225 // Operand to avoid match of loadConP.
4226 // This operand can be used to avoid matching of an instruct
4227 // with chain rule.
4228 operand immP_NM() %{
4229 match(ConP);
4230 predicate(false);
4231 op_cost(0);
4232 format %{ %}
4233 interface(CONST_INTER);
4234 %}
4235
4236 // costant 'pointer 0'.
4237 operand immP_0() %{
4238 predicate(n->get_ptr() == 0);
4239 match(ConP);
4240 op_cost(0);
4241 format %{ %}
4242 interface(CONST_INTER);
4243 %}
4244
4245 // pointer 0x0 or 0x1
4246 operand immP_0or1() %{
4247 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4248 match(ConP);
4249 op_cost(0);
4250 format %{ %}
4251 interface(CONST_INTER);
4252 %}
4253
4254 operand immL() %{
4255 match(ConL);
4256 op_cost(40);
4257 format %{ %}
4258 interface(CONST_INTER);
4259 %}
4260
4261 // Long Immediate: 16-bit
4262 operand immL16() %{
4263 predicate(Assembler::is_simm(n->get_long(), 16));
4264 match(ConL);
4265 op_cost(0);
4266 format %{ %}
4267 interface(CONST_INTER);
4268 %}
4269
4270 // Long Immediate: 16-bit, 4-aligned
4271 operand immL16Alg4() %{
4272 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4273 match(ConL);
4274 op_cost(0);
4275 format %{ %}
4276 interface(CONST_INTER);
4277 %}
4278
4279 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4280 operand immL32hi16() %{
4281 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4282 match(ConL);
4283 op_cost(0);
4284 format %{ %}
4285 interface(CONST_INTER);
4286 %}
4287
4288 // Long Immediate: 32-bit
4289 operand immL32() %{
4290 predicate(Assembler::is_simm(n->get_long(), 32));
4291 match(ConL);
4292 op_cost(0);
4293 format %{ %}
4294 interface(CONST_INTER);
4295 %}
4296
4297 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4298 operand immLhighest16() %{
4299 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4300 match(ConL);
4301 op_cost(0);
4302 format %{ %}
4303 interface(CONST_INTER);
4304 %}
4305
4306 operand immLnegpow2() %{
4307 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4308 match(ConL);
4309 op_cost(0);
4310 format %{ %}
4311 interface(CONST_INTER);
4312 %}
4313
4314 operand immLpow2minus1() %{
4315 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4316 (n->get_long() != (jlong)0xffffffffffffffffL));
4317 match(ConL);
4318 op_cost(0);
4319 format %{ %}
4320 interface(CONST_INTER);
4321 %}
4322
4323 // constant 'long 0'.
4324 operand immL_0() %{
4325 predicate(n->get_long() == 0L);
4326 match(ConL);
4327 op_cost(0);
4328 format %{ %}
4329 interface(CONST_INTER);
4330 %}
4331
4332 // constat ' long -1'.
4333 operand immL_minus1() %{
4334 predicate(n->get_long() == -1L);
4335 match(ConL);
4336 op_cost(0);
4337 format %{ %}
4338 interface(CONST_INTER);
4339 %}
4340
4341 // Long Immediate: low 32-bit mask
4342 operand immL_32bits() %{
4343 predicate(n->get_long() == 0xFFFFFFFFL);
4344 match(ConL);
4345 op_cost(0);
4346 format %{ %}
4347 interface(CONST_INTER);
4348 %}
4349
4350 // Unsigned Long Immediate: 16-bit
4351 operand uimmL16() %{
4352 predicate(Assembler::is_uimm(n->get_long(), 16));
4353 match(ConL);
4354 op_cost(0);
4355 format %{ %}
4356 interface(CONST_INTER);
4357 %}
4358
4359 // Float Immediate
4360 operand immF() %{
4361 match(ConF);
4362 op_cost(40);
4363 format %{ %}
4364 interface(CONST_INTER);
4365 %}
4366
4367 // constant 'float +0.0'.
4368 operand immF_0() %{
4369 predicate((n->getf() == 0) &&
4370 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0));
4371 match(ConF);
4372 op_cost(0);
4373 format %{ %}
4374 interface(CONST_INTER);
4375 %}
4376
4377 // Double Immediate
4378 operand immD() %{
4379 match(ConD);
4380 op_cost(40);
4381 format %{ %}
4382 interface(CONST_INTER);
4383 %}
4384
4385 // Integer Register Operands
4386 // Integer Destination Register
4387 // See definition of reg_class bits32_reg_rw.
4388 operand iRegIdst() %{
4389 constraint(ALLOC_IN_RC(bits32_reg_rw));
4390 match(RegI);
4391 match(rscratch1RegI);
4392 match(rscratch2RegI);
4393 match(rarg1RegI);
4394 match(rarg2RegI);
4395 match(rarg3RegI);
4396 match(rarg4RegI);
4397 format %{ %}
4398 interface(REG_INTER);
4399 %}
4400
4401 // Integer Source Register
4402 // See definition of reg_class bits32_reg_ro.
4403 operand iRegIsrc() %{
4404 constraint(ALLOC_IN_RC(bits32_reg_ro));
4405 match(RegI);
4406 match(rscratch1RegI);
4407 match(rscratch2RegI);
4408 match(rarg1RegI);
4409 match(rarg2RegI);
4410 match(rarg3RegI);
4411 match(rarg4RegI);
4412 format %{ %}
4413 interface(REG_INTER);
4414 %}
4415
4416 operand rscratch1RegI() %{
4417 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4418 match(iRegIdst);
4419 format %{ %}
4420 interface(REG_INTER);
4421 %}
4422
4423 operand rscratch2RegI() %{
4424 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4425 match(iRegIdst);
4426 format %{ %}
4427 interface(REG_INTER);
4428 %}
4429
4430 operand rarg1RegI() %{
4431 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4432 match(iRegIdst);
4433 format %{ %}
4434 interface(REG_INTER);
4435 %}
4436
4437 operand rarg2RegI() %{
4438 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4439 match(iRegIdst);
4440 format %{ %}
4441 interface(REG_INTER);
4442 %}
4443
4444 operand rarg3RegI() %{
4445 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4446 match(iRegIdst);
4447 format %{ %}
4448 interface(REG_INTER);
4449 %}
4450
4451 operand rarg4RegI() %{
4452 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4453 match(iRegIdst);
4454 format %{ %}
4455 interface(REG_INTER);
4456 %}
4457
4458 operand rarg1RegL() %{
4459 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4460 match(iRegLdst);
4461 format %{ %}
4462 interface(REG_INTER);
4463 %}
4464
4465 operand rarg2RegL() %{
4466 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4467 match(iRegLdst);
4468 format %{ %}
4469 interface(REG_INTER);
4470 %}
4471
4472 operand rarg3RegL() %{
4473 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4474 match(iRegLdst);
4475 format %{ %}
4476 interface(REG_INTER);
4477 %}
4478
4479 operand rarg4RegL() %{
4480 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4481 match(iRegLdst);
4482 format %{ %}
4483 interface(REG_INTER);
4484 %}
4485
4486 // Pointer Destination Register
4487 // See definition of reg_class bits64_reg_rw.
4488 operand iRegPdst() %{
4489 constraint(ALLOC_IN_RC(bits64_reg_rw));
4490 match(RegP);
4491 match(rscratch1RegP);
4492 match(rscratch2RegP);
4493 match(rarg1RegP);
4494 match(rarg2RegP);
4495 match(rarg3RegP);
4496 match(rarg4RegP);
4497 format %{ %}
4498 interface(REG_INTER);
4499 %}
4500
4501 // Pointer Destination Register
4502 // Operand not using r11 and r12 (killed in epilog).
4503 operand iRegPdstNoScratch() %{
4504 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4505 match(RegP);
4506 match(rarg1RegP);
4507 match(rarg2RegP);
4508 match(rarg3RegP);
4509 match(rarg4RegP);
4510 format %{ %}
4511 interface(REG_INTER);
4512 %}
4513
4514 // Pointer Source Register
4515 // See definition of reg_class bits64_reg_ro.
4516 operand iRegPsrc() %{
4517 constraint(ALLOC_IN_RC(bits64_reg_ro));
4518 match(RegP);
4519 match(iRegPdst);
4520 match(rscratch1RegP);
4521 match(rscratch2RegP);
4522 match(rarg1RegP);
4523 match(rarg2RegP);
4524 match(rarg3RegP);
4525 match(rarg4RegP);
4526 match(threadRegP);
4527 format %{ %}
4528 interface(REG_INTER);
4529 %}
4530
4531 // Thread operand.
4532 operand threadRegP() %{
4533 constraint(ALLOC_IN_RC(thread_bits64_reg));
4534 match(iRegPdst);
4535 format %{ "R16" %}
4536 interface(REG_INTER);
4537 %}
4538
4539 operand rscratch1RegP() %{
4540 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4541 match(iRegPdst);
4542 format %{ "R11" %}
4543 interface(REG_INTER);
4544 %}
4545
4546 operand rscratch2RegP() %{
4547 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4548 match(iRegPdst);
4549 format %{ %}
4550 interface(REG_INTER);
4551 %}
4552
4553 operand rarg1RegP() %{
4554 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4555 match(iRegPdst);
4556 format %{ %}
4557 interface(REG_INTER);
4558 %}
4559
4560 operand rarg2RegP() %{
4561 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4562 match(iRegPdst);
4563 format %{ %}
4564 interface(REG_INTER);
4565 %}
4566
4567 operand rarg3RegP() %{
4568 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4569 match(iRegPdst);
4570 format %{ %}
4571 interface(REG_INTER);
4572 %}
4573
4574 operand rarg4RegP() %{
4575 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4576 match(iRegPdst);
4577 format %{ %}
4578 interface(REG_INTER);
4579 %}
4580
4581 operand iRegNsrc() %{
4582 constraint(ALLOC_IN_RC(bits32_reg_ro));
4583 match(RegN);
4584 match(iRegNdst);
4585
4586 format %{ %}
4587 interface(REG_INTER);
4588 %}
4589
4590 operand iRegNdst() %{
4591 constraint(ALLOC_IN_RC(bits32_reg_rw));
4592 match(RegN);
4593
4594 format %{ %}
4595 interface(REG_INTER);
4596 %}
4597
4598 // Long Destination Register
4599 // See definition of reg_class bits64_reg_rw.
4600 operand iRegLdst() %{
4601 constraint(ALLOC_IN_RC(bits64_reg_rw));
4602 match(RegL);
4603 match(rscratch1RegL);
4604 match(rscratch2RegL);
4605 format %{ %}
4606 interface(REG_INTER);
4607 %}
4608
4609 // Long Source Register
4610 // See definition of reg_class bits64_reg_ro.
4611 operand iRegLsrc() %{
4612 constraint(ALLOC_IN_RC(bits64_reg_ro));
4613 match(RegL);
4614 match(iRegLdst);
4615 match(rscratch1RegL);
4616 match(rscratch2RegL);
4617 format %{ %}
4618 interface(REG_INTER);
4619 %}
4620
4621 // Special operand for ConvL2I.
4622 operand iRegL2Isrc(iRegLsrc reg) %{
4623 constraint(ALLOC_IN_RC(bits64_reg_ro));
4624 match(ConvL2I reg);
4625 format %{ "ConvL2I($reg)" %}
4626 interface(REG_INTER)
4627 %}
4628
4629 operand rscratch1RegL() %{
4630 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4631 match(RegL);
4632 format %{ %}
4633 interface(REG_INTER);
4634 %}
4635
4636 operand rscratch2RegL() %{
4637 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4638 match(RegL);
4639 format %{ %}
4640 interface(REG_INTER);
4641 %}
4642
4643 // Condition Code Flag Registers
4644 operand flagsReg() %{
4645 constraint(ALLOC_IN_RC(int_flags));
4646 match(RegFlags);
4647 format %{ %}
4648 interface(REG_INTER);
4649 %}
4650
4651 // Condition Code Flag Register CR0
4652 operand flagsRegCR0() %{
4653 constraint(ALLOC_IN_RC(int_flags_CR0));
4654 match(RegFlags);
4655 format %{ "CR0" %}
4656 interface(REG_INTER);
4657 %}
4658
4659 operand flagsRegCR1() %{
4660 constraint(ALLOC_IN_RC(int_flags_CR1));
4661 match(RegFlags);
4662 format %{ "CR1" %}
4663 interface(REG_INTER);
4664 %}
4665
4666 operand flagsRegCR6() %{
4667 constraint(ALLOC_IN_RC(int_flags_CR6));
4668 match(RegFlags);
4669 format %{ "CR6" %}
4670 interface(REG_INTER);
4671 %}
4672
4673 operand regCTR() %{
4674 constraint(ALLOC_IN_RC(ctr_reg));
4675 // RegFlags should work. Introducing a RegSpecial type would cause a
4676 // lot of changes.
4677 match(RegFlags);
4678 format %{"SR_CTR" %}
4679 interface(REG_INTER);
4680 %}
4681
4682 operand regD() %{
4683 constraint(ALLOC_IN_RC(dbl_reg));
4684 match(RegD);
4685 format %{ %}
4686 interface(REG_INTER);
4687 %}
4688
4689 operand regF() %{
4690 constraint(ALLOC_IN_RC(flt_reg));
4691 match(RegF);
4692 format %{ %}
4693 interface(REG_INTER);
4694 %}
4695
4696 // Special Registers
4697
4698 // Method Register
4699 operand inline_cache_regP(iRegPdst reg) %{
4700 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4701 match(reg);
4702 format %{ %}
4703 interface(REG_INTER);
4704 %}
4705
4706 operand compiler_method_oop_regP(iRegPdst reg) %{
4707 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4708 match(reg);
4709 format %{ %}
4710 interface(REG_INTER);
4711 %}
4712
4713 operand interpreter_method_oop_regP(iRegPdst reg) %{
4714 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4715 match(reg);
4716 format %{ %}
4717 interface(REG_INTER);
4718 %}
4719
4720 // Operands to remove register moves in unscaled mode.
4721 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4722 operand iRegP2N(iRegPsrc reg) %{
4723 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4724 constraint(ALLOC_IN_RC(bits64_reg_ro));
4725 match(EncodeP reg);
4726 format %{ "$reg" %}
4727 interface(REG_INTER)
4728 %}
4729
4730 operand iRegN2P(iRegNsrc reg) %{
4731 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4732 constraint(ALLOC_IN_RC(bits32_reg_ro));
4733 match(DecodeN reg);
4734 match(DecodeNKlass reg);
4735 format %{ "$reg" %}
4736 interface(REG_INTER)
4737 %}
4738
4739 //----------Complex Operands---------------------------------------------------
4740 // Indirect Memory Reference
4741 operand indirect(iRegPsrc reg) %{
4742 constraint(ALLOC_IN_RC(bits64_reg_ro));
4743 match(reg);
4744 op_cost(100);
4745 format %{ "[$reg]" %}
4746 interface(MEMORY_INTER) %{
4747 base($reg);
4748 index(0x0);
4749 scale(0x0);
4750 disp(0x0);
4751 %}
4752 %}
4753
4754 // Indirect with Offset
4755 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4756 constraint(ALLOC_IN_RC(bits64_reg_ro));
4757 match(AddP reg offset);
4758 op_cost(100);
4759 format %{ "[$reg + $offset]" %}
4760 interface(MEMORY_INTER) %{
4761 base($reg);
4762 index(0x0);
4763 scale(0x0);
4764 disp($offset);
4765 %}
4766 %}
4767
4768 // Indirect with 4-aligned Offset
4769 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4770 constraint(ALLOC_IN_RC(bits64_reg_ro));
4771 match(AddP reg offset);
4772 op_cost(100);
4773 format %{ "[$reg + $offset]" %}
4774 interface(MEMORY_INTER) %{
4775 base($reg);
4776 index(0x0);
4777 scale(0x0);
4778 disp($offset);
4779 %}
4780 %}
4781
4782 //----------Complex Operands for Compressed OOPs-------------------------------
4783 // Compressed OOPs with narrow_oop_shift == 0.
4784
4785 // Indirect Memory Reference, compressed OOP
4786 operand indirectNarrow(iRegNsrc reg) %{
4787 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4788 constraint(ALLOC_IN_RC(bits64_reg_ro));
4789 match(DecodeN reg);
4790 match(DecodeNKlass reg);
4791 op_cost(100);
4792 format %{ "[$reg]" %}
4793 interface(MEMORY_INTER) %{
4794 base($reg);
4795 index(0x0);
4796 scale(0x0);
4797 disp(0x0);
4798 %}
4799 %}
4800
4801 // Indirect with Offset, compressed OOP
4802 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4803 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4804 constraint(ALLOC_IN_RC(bits64_reg_ro));
4805 match(AddP (DecodeN reg) offset);
4806 match(AddP (DecodeNKlass reg) offset);
4807 op_cost(100);
4808 format %{ "[$reg + $offset]" %}
4809 interface(MEMORY_INTER) %{
4810 base($reg);
4811 index(0x0);
4812 scale(0x0);
4813 disp($offset);
4814 %}
4815 %}
4816
4817 // Indirect with 4-aligned Offset, compressed OOP
4818 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4819 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4820 constraint(ALLOC_IN_RC(bits64_reg_ro));
4821 match(AddP (DecodeN reg) offset);
4822 match(AddP (DecodeNKlass reg) offset);
4823 op_cost(100);
4824 format %{ "[$reg + $offset]" %}
4825 interface(MEMORY_INTER) %{
4826 base($reg);
4827 index(0x0);
4828 scale(0x0);
4829 disp($offset);
4830 %}
4831 %}
4832
4833 //----------Special Memory Operands--------------------------------------------
4834 // Stack Slot Operand
4835 //
4836 // This operand is used for loading and storing temporary values on
4837 // the stack where a match requires a value to flow through memory.
4838 operand stackSlotI(sRegI reg) %{
4839 constraint(ALLOC_IN_RC(stack_slots));
4840 op_cost(100);
4841 //match(RegI);
4842 format %{ "[sp+$reg]" %}
4843 interface(MEMORY_INTER) %{
4844 base(0x1); // R1_SP
4845 index(0x0);
4846 scale(0x0);
4847 disp($reg); // Stack Offset
4848 %}
4849 %}
4850
4851 operand stackSlotL(sRegL reg) %{
4852 constraint(ALLOC_IN_RC(stack_slots));
4853 op_cost(100);
4854 //match(RegL);
4855 format %{ "[sp+$reg]" %}
4856 interface(MEMORY_INTER) %{
4857 base(0x1); // R1_SP
4858 index(0x0);
4859 scale(0x0);
4860 disp($reg); // Stack Offset
4861 %}
4862 %}
4863
4864 operand stackSlotP(sRegP reg) %{
4865 constraint(ALLOC_IN_RC(stack_slots));
4866 op_cost(100);
4867 //match(RegP);
4868 format %{ "[sp+$reg]" %}
4869 interface(MEMORY_INTER) %{
4870 base(0x1); // R1_SP
4871 index(0x0);
4872 scale(0x0);
4873 disp($reg); // Stack Offset
4874 %}
4875 %}
4876
4877 operand stackSlotF(sRegF reg) %{
4878 constraint(ALLOC_IN_RC(stack_slots));
4879 op_cost(100);
4880 //match(RegF);
4881 format %{ "[sp+$reg]" %}
4882 interface(MEMORY_INTER) %{
4883 base(0x1); // R1_SP
4884 index(0x0);
4885 scale(0x0);
4886 disp($reg); // Stack Offset
4887 %}
4888 %}
4889
4890 operand stackSlotD(sRegD reg) %{
4891 constraint(ALLOC_IN_RC(stack_slots));
4892 op_cost(100);
4893 //match(RegD);
4894 format %{ "[sp+$reg]" %}
4895 interface(MEMORY_INTER) %{
4896 base(0x1); // R1_SP
4897 index(0x0);
4898 scale(0x0);
4899 disp($reg); // Stack Offset
4900 %}
4901 %}
4902
4903 // Operands for expressing Control Flow
4904 // NOTE: Label is a predefined operand which should not be redefined in
4905 // the AD file. It is generically handled within the ADLC.
4906
4907 //----------Conditional Branch Operands----------------------------------------
4908 // Comparison Op
4909 //
4910 // This is the operation of the comparison, and is limited to the
4911 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4912 // (!=).
4913 //
4914 // Other attributes of the comparison, such as unsignedness, are specified
4915 // by the comparison instruction that sets a condition code flags register.
4916 // That result is represented by a flags operand whose subtype is appropriate
4917 // to the unsignedness (etc.) of the comparison.
4918 //
4919 // Later, the instruction which matches both the Comparison Op (a Bool) and
4920 // the flags (produced by the Cmp) specifies the coding of the comparison op
4921 // by matching a specific subtype of Bool operand below.
4922
4923 // When used for floating point comparisons: unordered same as less.
4924 operand cmpOp() %{
4925 match(Bool);
4926 format %{ "" %}
4927 interface(COND_INTER) %{
4928 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4929 // BO & BI
4930 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4931 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4932 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4933 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4934 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4935 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4936 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4937 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4938 %}
4939 %}
4940
4941 //----------OPERAND CLASSES----------------------------------------------------
4942 // Operand Classes are groups of operands that are used to simplify
4943 // instruction definitions by not requiring the AD writer to specify
4944 // seperate instructions for every form of operand when the
4945 // instruction accepts multiple operand types with the same basic
4946 // encoding and format. The classic case of this is memory operands.
4947 // Indirect is not included since its use is limited to Compare & Swap.
4948
4949 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
4950 // Memory operand where offsets are 4-aligned. Required for ld, std.
4951 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
4952 opclass indirectMemory(indirect, indirectNarrow);
4953
4954 // Special opclass for I and ConvL2I.
4955 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4956
4957 // Operand classes to match encode and decode. iRegN_P2N is only used
4958 // for storeN. I have never seen an encode node elsewhere.
4959 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4960 opclass iRegP_N2P(iRegPsrc, iRegN2P);
4961
4962 //----------PIPELINE-----------------------------------------------------------
4963
4964 pipeline %{
4965
4966 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4967 // J. Res. & Dev., No. 1, Jan. 2002.
4968
4969 //----------ATTRIBUTES---------------------------------------------------------
4970 attributes %{
4971
4972 // Power4 instructions are of fixed length.
4973 fixed_size_instructions;
4974
4975 // TODO: if `bundle' means number of instructions fetched
4976 // per cycle, this is 8. If `bundle' means Power4 `group', that is
4977 // max instructions issued per cycle, this is 5.
4978 max_instructions_per_bundle = 8;
4979
4980 // A Power4 instruction is 4 bytes long.
4981 instruction_unit_size = 4;
4982
4983 // The Power4 processor fetches 64 bytes...
4984 instruction_fetch_unit_size = 64;
4985
4986 // ...in one line
4987 instruction_fetch_units = 1
4988
4989 // Unused, list one so that array generated by adlc is not empty.
4990 // Aix compiler chokes if _nop_count = 0.
4991 nops(fxNop);
4992 %}
4993
4994 //----------RESOURCES----------------------------------------------------------
4995 // Resources are the functional units available to the machine
4996 resources(
4997 PPC_BR, // branch unit
4998 PPC_CR, // condition unit
4999 PPC_FX1, // integer arithmetic unit 1
5000 PPC_FX2, // integer arithmetic unit 2
5001 PPC_LDST1, // load/store unit 1
5002 PPC_LDST2, // load/store unit 2
5003 PPC_FP1, // float arithmetic unit 1
5004 PPC_FP2, // float arithmetic unit 2
5005 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5006 PPC_FX = PPC_FX1 | PPC_FX2,
5007 PPC_FP = PPC_FP1 | PPC_FP2
5008 );
5009
5010 //----------PIPELINE DESCRIPTION-----------------------------------------------
5011 // Pipeline Description specifies the stages in the machine's pipeline
5012 pipe_desc(
5013 // Power4 longest pipeline path
5014 PPC_IF, // instruction fetch
5015 PPC_IC,
5016 //PPC_BP, // branch prediction
5017 PPC_D0, // decode
5018 PPC_D1, // decode
5019 PPC_D2, // decode
5020 PPC_D3, // decode
5021 PPC_Xfer1,
5022 PPC_GD, // group definition
5023 PPC_MP, // map
5024 PPC_ISS, // issue
5025 PPC_RF, // resource fetch
5026 PPC_EX1, // execute (all units)
5027 PPC_EX2, // execute (FP, LDST)
5028 PPC_EX3, // execute (FP, LDST)
5029 PPC_EX4, // execute (FP)
5030 PPC_EX5, // execute (FP)
5031 PPC_EX6, // execute (FP)
5032 PPC_WB, // write back
5033 PPC_Xfer2,
5034 PPC_CP
5035 );
5036
5037 //----------PIPELINE CLASSES---------------------------------------------------
5038 // Pipeline Classes describe the stages in which input and output are
5039 // referenced by the hardware pipeline.
5040
5041 // Simple pipeline classes.
5042
5043 // Default pipeline class.
5044 pipe_class pipe_class_default() %{
5045 single_instruction;
5046 fixed_latency(2);
5047 %}
5048
5049 // Pipeline class for empty instructions.
5050 pipe_class pipe_class_empty() %{
5051 single_instruction;
5052 fixed_latency(0);
5053 %}
5054
5055 // Pipeline class for compares.
5056 pipe_class pipe_class_compare() %{
5057 single_instruction;
5058 fixed_latency(16);
5059 %}
5060
5061 // Pipeline class for traps.
5062 pipe_class pipe_class_trap() %{
5063 single_instruction;
5064 fixed_latency(100);
5065 %}
5066
5067 // Pipeline class for memory operations.
5068 pipe_class pipe_class_memory() %{
5069 single_instruction;
5070 fixed_latency(16);
5071 %}
5072
5073 // Pipeline class for call.
5074 pipe_class pipe_class_call() %{
5075 single_instruction;
5076 fixed_latency(100);
5077 %}
5078
5079 // Define the class for the Nop node.
5080 define %{
5081 MachNop = pipe_class_default;
5082 %}
5083
5084 %}
5085
5086 //----------INSTRUCTIONS-------------------------------------------------------
5087
5088 // Naming of instructions:
5089 // opA_operB / opA_operB_operC:
5090 // Operation 'op' with one or two source operands 'oper'. Result
5091 // type is A, source operand types are B and C.
5092 // Iff A == B == C, B and C are left out.
5093 //
5094 // The instructions are ordered according to the following scheme:
5095 // - loads
5096 // - load constants
5097 // - prefetch
5098 // - store
5099 // - encode/decode
5100 // - membar
5101 // - conditional moves
5102 // - compare & swap
5103 // - arithmetic and logic operations
5104 // * int: Add, Sub, Mul, Div, Mod
5105 // * int: lShift, arShift, urShift, rot
5106 // * float: Add, Sub, Mul, Div
5107 // * and, or, xor ...
5108 // - register moves: float <-> int, reg <-> stack, repl
5109 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5110 // - conv (low level type cast requiring bit changes (sign extend etc)
5111 // - compares, range & zero checks.
5112 // - branches
5113 // - complex operations, intrinsics, min, max, replicate
5114 // - lock
5115 // - Calls
5116 //
5117 // If there are similar instructions with different types they are sorted:
5118 // int before float
5119 // small before big
5120 // signed before unsigned
5121 // e.g., loadS before loadUS before loadI before loadF.
5122
5123
5124 //----------Load/Store Instructions--------------------------------------------
5125
5126 //----------Load Instructions--------------------------------------------------
5127
5128 // Converts byte to int.
5129 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5130 // reuses the 'amount' operand, but adlc expects that operand specification
5131 // and operands in match rule are equivalent.
5132 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5133 effect(DEF dst, USE src);
5134 format %{ "EXTSB $dst, $src \t// byte->int" %}
5135 size(4);
5136 ins_encode %{
5137 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5138 __ extsb($dst$$Register, $src$$Register);
5139 %}
5140 ins_pipe(pipe_class_default);
5141 %}
5142
5143 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5144 // match-rule, false predicate
5145 match(Set dst (LoadB mem));
5146 predicate(false);
5147
5148 format %{ "LBZ $dst, $mem" %}
5149 size(4);
5150 ins_encode( enc_lbz(dst, mem) );
5151 ins_pipe(pipe_class_memory);
5152 %}
5153
5154 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5155 // match-rule, false predicate
5156 match(Set dst (LoadB mem));
5157 predicate(false);
5158
5159 format %{ "LBZ $dst, $mem\n\t"
5160 "TWI $dst\n\t"
5161 "ISYNC" %}
5162 size(12);
5163 ins_encode( enc_lbz_ac(dst, mem) );
5164 ins_pipe(pipe_class_memory);
5165 %}
5166
5167 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5168 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5169 match(Set dst (LoadB mem));
5170 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5171 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5172 expand %{
5173 iRegIdst tmp;
5174 loadUB_indirect(tmp, mem);
5175 convB2I_reg_2(dst, tmp);
5176 %}
5177 %}
5178
5179 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5180 match(Set dst (LoadB mem));
5181 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5182 expand %{
5183 iRegIdst tmp;
5184 loadUB_indirect_ac(tmp, mem);
5185 convB2I_reg_2(dst, tmp);
5186 %}
5187 %}
5188
5189 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5190 // match-rule, false predicate
5191 match(Set dst (LoadB mem));
5192 predicate(false);
5193
5194 format %{ "LBZ $dst, $mem" %}
5195 size(4);
5196 ins_encode( enc_lbz(dst, mem) );
5197 ins_pipe(pipe_class_memory);
5198 %}
5199
5200 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5201 // match-rule, false predicate
5202 match(Set dst (LoadB mem));
5203 predicate(false);
5204
5205 format %{ "LBZ $dst, $mem\n\t"
5206 "TWI $dst\n\t"
5207 "ISYNC" %}
5208 size(12);
5209 ins_encode( enc_lbz_ac(dst, mem) );
5210 ins_pipe(pipe_class_memory);
5211 %}
5212
5213 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5214 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5215 match(Set dst (LoadB mem));
5216 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5217 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5218
5219 expand %{
5220 iRegIdst tmp;
5221 loadUB_indOffset16(tmp, mem);
5222 convB2I_reg_2(dst, tmp);
5223 %}
5224 %}
5225
5226 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5227 match(Set dst (LoadB mem));
5228 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5229
5230 expand %{
5231 iRegIdst tmp;
5232 loadUB_indOffset16_ac(tmp, mem);
5233 convB2I_reg_2(dst, tmp);
5234 %}
5235 %}
5236
5237 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5238 instruct loadUB(iRegIdst dst, memory mem) %{
5239 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5240 match(Set dst (LoadUB mem));
5241 ins_cost(MEMORY_REF_COST);
5242
5243 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5244 size(4);
5245 ins_encode( enc_lbz(dst, mem) );
5246 ins_pipe(pipe_class_memory);
5247 %}
5248
5249 // Load Unsigned Byte (8bit UNsigned) acquire.
5250 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5251 match(Set dst (LoadUB mem));
5252 ins_cost(3*MEMORY_REF_COST);
5253
5254 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5255 "TWI $dst\n\t"
5256 "ISYNC" %}
5257 size(12);
5258 ins_encode( enc_lbz_ac(dst, mem) );
5259 ins_pipe(pipe_class_memory);
5260 %}
5261
5262 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5263 instruct loadUB2L(iRegLdst dst, memory mem) %{
5264 match(Set dst (ConvI2L (LoadUB mem)));
5265 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5266 ins_cost(MEMORY_REF_COST);
5267
5268 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5269 size(4);
5270 ins_encode( enc_lbz(dst, mem) );
5271 ins_pipe(pipe_class_memory);
5272 %}
5273
5274 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5275 match(Set dst (ConvI2L (LoadUB mem)));
5276 ins_cost(3*MEMORY_REF_COST);
5277
5278 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5279 "TWI $dst\n\t"
5280 "ISYNC" %}
5281 size(12);
5282 ins_encode( enc_lbz_ac(dst, mem) );
5283 ins_pipe(pipe_class_memory);
5284 %}
5285
5286 // Load Short (16bit signed)
5287 instruct loadS(iRegIdst dst, memory mem) %{
5288 match(Set dst (LoadS mem));
5289 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5290 ins_cost(MEMORY_REF_COST);
5291
5292 format %{ "LHA $dst, $mem" %}
5293 size(4);
5294 ins_encode %{
5295 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5296 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5297 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5298 %}
5299 ins_pipe(pipe_class_memory);
5300 %}
5301
5302 // Load Short (16bit signed) acquire.
5303 instruct loadS_ac(iRegIdst dst, memory mem) %{
5304 match(Set dst (LoadS mem));
5305 ins_cost(3*MEMORY_REF_COST);
5306
5307 format %{ "LHA $dst, $mem\t acquire\n\t"
5308 "TWI $dst\n\t"
5309 "ISYNC" %}
5310 size(12);
5311 ins_encode %{
5312 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5313 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5314 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5315 __ twi_0($dst$$Register);
5316 __ isync();
5317 %}
5318 ins_pipe(pipe_class_memory);
5319 %}
5320
5321 // Load Char (16bit unsigned)
5322 instruct loadUS(iRegIdst dst, memory mem) %{
5323 match(Set dst (LoadUS mem));
5324 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5325 ins_cost(MEMORY_REF_COST);
5326
5327 format %{ "LHZ $dst, $mem" %}
5328 size(4);
5329 ins_encode( enc_lhz(dst, mem) );
5330 ins_pipe(pipe_class_memory);
5331 %}
5332
5333 // Load Char (16bit unsigned) acquire.
5334 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5335 match(Set dst (LoadUS mem));
5336 ins_cost(3*MEMORY_REF_COST);
5337
5338 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5339 "TWI $dst\n\t"
5340 "ISYNC" %}
5341 size(12);
5342 ins_encode( enc_lhz_ac(dst, mem) );
5343 ins_pipe(pipe_class_memory);
5344 %}
5345
5346 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5347 instruct loadUS2L(iRegLdst dst, memory mem) %{
5348 match(Set dst (ConvI2L (LoadUS mem)));
5349 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5350 ins_cost(MEMORY_REF_COST);
5351
5352 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5353 size(4);
5354 ins_encode( enc_lhz(dst, mem) );
5355 ins_pipe(pipe_class_memory);
5356 %}
5357
5358 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5359 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5360 match(Set dst (ConvI2L (LoadUS mem)));
5361 ins_cost(3*MEMORY_REF_COST);
5362
5363 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5364 "TWI $dst\n\t"
5365 "ISYNC" %}
5366 size(12);
5367 ins_encode( enc_lhz_ac(dst, mem) );
5368 ins_pipe(pipe_class_memory);
5369 %}
5370
5371 // Load Integer.
5372 instruct loadI(iRegIdst dst, memory mem) %{
5373 match(Set dst (LoadI mem));
5374 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5375 ins_cost(MEMORY_REF_COST);
5376
5377 format %{ "LWZ $dst, $mem" %}
5378 size(4);
5379 ins_encode( enc_lwz(dst, mem) );
5380 ins_pipe(pipe_class_memory);
5381 %}
5382
5383 // Load Integer acquire.
5384 instruct loadI_ac(iRegIdst dst, memory mem) %{
5385 match(Set dst (LoadI mem));
5386 ins_cost(3*MEMORY_REF_COST);
5387
5388 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5389 "TWI $dst\n\t"
5390 "ISYNC" %}
5391 size(12);
5392 ins_encode( enc_lwz_ac(dst, mem) );
5393 ins_pipe(pipe_class_memory);
5394 %}
5395
5396 // Match loading integer and casting it to unsigned int in
5397 // long register.
5398 // LoadI + ConvI2L + AndL 0xffffffff.
5399 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5400 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5401 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5402 ins_cost(MEMORY_REF_COST);
5403
5404 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5405 size(4);
5406 ins_encode( enc_lwz(dst, mem) );
5407 ins_pipe(pipe_class_memory);
5408 %}
5409
5410 // Match loading integer and casting it to long.
5411 instruct loadI2L(iRegLdst dst, memory mem) %{
5412 match(Set dst (ConvI2L (LoadI mem)));
5413 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5414 ins_cost(MEMORY_REF_COST);
5415
5416 format %{ "LWA $dst, $mem \t// loadI2L" %}
5417 size(4);
5418 ins_encode %{
5419 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5420 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5421 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5422 %}
5423 ins_pipe(pipe_class_memory);
5424 %}
5425
5426 // Match loading integer and casting it to long - acquire.
5427 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5428 match(Set dst (ConvI2L (LoadI mem)));
5429 ins_cost(3*MEMORY_REF_COST);
5430
5431 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5432 "TWI $dst\n\t"
5433 "ISYNC" %}
5434 size(12);
5435 ins_encode %{
5436 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5437 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5438 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5439 __ twi_0($dst$$Register);
5440 __ isync();
5441 %}
5442 ins_pipe(pipe_class_memory);
5443 %}
5444
5445 // Load Long - aligned
5446 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5447 match(Set dst (LoadL mem));
5448 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5449 ins_cost(MEMORY_REF_COST);
5450
5451 format %{ "LD $dst, $mem \t// long" %}
5452 size(4);
5453 ins_encode( enc_ld(dst, mem) );
5454 ins_pipe(pipe_class_memory);
5455 %}
5456
5457 // Load Long - aligned acquire.
5458 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5459 match(Set dst (LoadL mem));
5460 ins_cost(3*MEMORY_REF_COST);
5461
5462 format %{ "LD $dst, $mem \t// long acquire\n\t"
5463 "TWI $dst\n\t"
5464 "ISYNC" %}
5465 size(12);
5466 ins_encode( enc_ld_ac(dst, mem) );
5467 ins_pipe(pipe_class_memory);
5468 %}
5469
5470 // Load Long - UNaligned
5471 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5472 match(Set dst (LoadL_unaligned mem));
5473 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5474 ins_cost(MEMORY_REF_COST);
5475
5476 format %{ "LD $dst, $mem \t// unaligned long" %}
5477 size(4);
5478 ins_encode( enc_ld(dst, mem) );
5479 ins_pipe(pipe_class_memory);
5480 %}
5481
5482 // Load nodes for superwords
5483
5484 // Load Aligned Packed Byte
5485 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5486 predicate(n->as_LoadVector()->memory_size() == 8);
5487 match(Set dst (LoadVector mem));
5488 ins_cost(MEMORY_REF_COST);
5489
5490 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5491 size(4);
5492 ins_encode( enc_ld(dst, mem) );
5493 ins_pipe(pipe_class_memory);
5494 %}
5495
5496 // Load Range, range = array length (=jint)
5497 instruct loadRange(iRegIdst dst, memory mem) %{
5498 match(Set dst (LoadRange mem));
5499 ins_cost(MEMORY_REF_COST);
5500
5501 format %{ "LWZ $dst, $mem \t// range" %}
5502 size(4);
5503 ins_encode( enc_lwz(dst, mem) );
5504 ins_pipe(pipe_class_memory);
5505 %}
5506
5507 // Load Compressed Pointer
5508 instruct loadN(iRegNdst dst, memory mem) %{
5509 match(Set dst (LoadN mem));
5510 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5511 ins_cost(MEMORY_REF_COST);
5512
5513 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5514 size(4);
5515 ins_encode( enc_lwz(dst, mem) );
5516 ins_pipe(pipe_class_memory);
5517 %}
5518
5519 // Load Compressed Pointer acquire.
5520 instruct loadN_ac(iRegNdst dst, memory mem) %{
5521 match(Set dst (LoadN mem));
5522 ins_cost(3*MEMORY_REF_COST);
5523
5524 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5525 "TWI $dst\n\t"
5526 "ISYNC" %}
5527 size(12);
5528 ins_encode( enc_lwz_ac(dst, mem) );
5529 ins_pipe(pipe_class_memory);
5530 %}
5531
5532 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5533 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5534 match(Set dst (DecodeN (LoadN mem)));
5535 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5536 ins_cost(MEMORY_REF_COST);
5537
5538 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5539 size(4);
5540 ins_encode( enc_lwz(dst, mem) );
5541 ins_pipe(pipe_class_memory);
5542 %}
5543
5544 // Load Pointer
5545 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5546 match(Set dst (LoadP mem));
5547 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5548 ins_cost(MEMORY_REF_COST);
5549
5550 format %{ "LD $dst, $mem \t// ptr" %}
5551 size(4);
5552 ins_encode( enc_ld(dst, mem) );
5553 ins_pipe(pipe_class_memory);
5554 %}
5555
5556 // Load Pointer acquire.
5557 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5558 match(Set dst (LoadP mem));
5559 ins_cost(3*MEMORY_REF_COST);
5560
5561 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5562 "TWI $dst\n\t"
5563 "ISYNC" %}
5564 size(12);
5565 ins_encode( enc_ld_ac(dst, mem) );
5566 ins_pipe(pipe_class_memory);
5567 %}
5568
5569 // LoadP + CastP2L
5570 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5571 match(Set dst (CastP2X (LoadP mem)));
5572 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5573 ins_cost(MEMORY_REF_COST);
5574
5575 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5576 size(4);
5577 ins_encode( enc_ld(dst, mem) );
5578 ins_pipe(pipe_class_memory);
5579 %}
5580
5581 // Load compressed klass pointer.
5582 instruct loadNKlass(iRegNdst dst, memory mem) %{
5583 match(Set dst (LoadNKlass mem));
5584 ins_cost(MEMORY_REF_COST);
5585
5586 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5587 size(4);
5588 ins_encode( enc_lwz(dst, mem) );
5589 ins_pipe(pipe_class_memory);
5590 %}
5591
5592 //// Load compressed klass and decode it if narrow_klass_shift == 0.
5593 //// TODO: will narrow_klass_shift ever be 0?
5594 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{
5595 // match(Set dst (DecodeNKlass (LoadNKlass mem)));
5596 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*);
5597 // ins_cost(MEMORY_REF_COST);
5598 //
5599 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %}
5600 // size(4);
5601 // ins_encode( enc_lwz(dst, mem) );
5602 // ins_pipe(pipe_class_memory);
5603 //%}
5604
5605 // Load Klass Pointer
5606 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5607 match(Set dst (LoadKlass mem));
5608 ins_cost(MEMORY_REF_COST);
5609
5610 format %{ "LD $dst, $mem \t// klass ptr" %}
5611 size(4);
5612 ins_encode( enc_ld(dst, mem) );
5613 ins_pipe(pipe_class_memory);
5614 %}
5615
5616 // Load Float
5617 instruct loadF(regF dst, memory mem) %{
5618 match(Set dst (LoadF mem));
5619 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5620 ins_cost(MEMORY_REF_COST);
5621
5622 format %{ "LFS $dst, $mem" %}
5623 size(4);
5624 ins_encode %{
5625 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5626 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5627 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5628 %}
5629 ins_pipe(pipe_class_memory);
5630 %}
5631
5632 // Load Float acquire.
5633 instruct loadF_ac(regF dst, memory mem) %{
5634 match(Set dst (LoadF mem));
5635 ins_cost(3*MEMORY_REF_COST);
5636
5637 format %{ "LFS $dst, $mem \t// acquire\n\t"
5638 "FCMPU cr0, $dst, $dst\n\t"
5639 "BNE cr0, next\n"
5640 "next:\n\t"
5641 "ISYNC" %}
5642 size(16);
5643 ins_encode %{
5644 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5645 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5646 Label next;
5647 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5648 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5649 __ bne(CCR0, next);
5650 __ bind(next);
5651 __ isync();
5652 %}
5653 ins_pipe(pipe_class_memory);
5654 %}
5655
5656 // Load Double - aligned
5657 instruct loadD(regD dst, memory mem) %{
5658 match(Set dst (LoadD mem));
5659 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5660 ins_cost(MEMORY_REF_COST);
5661
5662 format %{ "LFD $dst, $mem" %}
5663 size(4);
5664 ins_encode( enc_lfd(dst, mem) );
5665 ins_pipe(pipe_class_memory);
5666 %}
5667
5668 // Load Double - aligned acquire.
5669 instruct loadD_ac(regD dst, memory mem) %{
5670 match(Set dst (LoadD mem));
5671 ins_cost(3*MEMORY_REF_COST);
5672
5673 format %{ "LFD $dst, $mem \t// acquire\n\t"
5674 "FCMPU cr0, $dst, $dst\n\t"
5675 "BNE cr0, next\n"
5676 "next:\n\t"
5677 "ISYNC" %}
5678 size(16);
5679 ins_encode %{
5680 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5681 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5682 Label next;
5683 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5684 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5685 __ bne(CCR0, next);
5686 __ bind(next);
5687 __ isync();
5688 %}
5689 ins_pipe(pipe_class_memory);
5690 %}
5691
5692 // Load Double - UNaligned
5693 instruct loadD_unaligned(regD dst, memory mem) %{
5694 match(Set dst (LoadD_unaligned mem));
5695 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5696 ins_cost(MEMORY_REF_COST);
5697
5698 format %{ "LFD $dst, $mem" %}
5699 size(4);
5700 ins_encode( enc_lfd(dst, mem) );
5701 ins_pipe(pipe_class_memory);
5702 %}
5703
5704 //----------Constants--------------------------------------------------------
5705
5706 // Load MachConstantTableBase: add hi offset to global toc.
5707 // TODO: Handle hidden register r29 in bundler!
5708 instruct loadToc_hi(iRegLdst dst) %{
5709 effect(DEF dst);
5710 ins_cost(DEFAULT_COST);
5711
5712 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5713 size(4);
5714 ins_encode %{
5715 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5716 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5717 %}
5718 ins_pipe(pipe_class_default);
5719 %}
5720
5721 // Load MachConstantTableBase: add lo offset to global toc.
5722 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5723 effect(DEF dst, USE src);
5724 ins_cost(DEFAULT_COST);
5725
5726 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5727 size(4);
5728 ins_encode %{
5729 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5730 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5731 %}
5732 ins_pipe(pipe_class_default);
5733 %}
5734
5735 // Load 16-bit integer constant 0xssss????
5736 instruct loadConI16(iRegIdst dst, immI16 src) %{
5737 match(Set dst src);
5738
5739 format %{ "LI $dst, $src" %}
5740 size(4);
5741 ins_encode %{
5742 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5743 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5744 %}
5745 ins_pipe(pipe_class_default);
5746 %}
5747
5748 // Load integer constant 0x????0000
5749 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5750 match(Set dst src);
5751 ins_cost(DEFAULT_COST);
5752
5753 format %{ "LIS $dst, $src.hi" %}
5754 size(4);
5755 ins_encode %{
5756 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5757 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5758 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5759 %}
5760 ins_pipe(pipe_class_default);
5761 %}
5762
5763 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5764 // and sign extended), this adds the low 16 bits.
5765 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5766 // no match-rule, false predicate
5767 effect(DEF dst, USE src1, USE src2);
5768 predicate(false);
5769
5770 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5771 size(4);
5772 ins_encode %{
5773 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5774 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5775 %}
5776 ins_pipe(pipe_class_default);
5777 %}
5778
5779 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5780 match(Set dst src);
5781 ins_cost(DEFAULT_COST*2);
5782
5783 expand %{
5784 // Would like to use $src$$constant.
5785 immI16 srcLo %{ _opnds[1]->constant() %}
5786 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5787 immIhi16 srcHi %{ _opnds[1]->constant() %}
5788 iRegIdst tmpI;
5789 loadConIhi16(tmpI, srcHi);
5790 loadConI32_lo16(dst, tmpI, srcLo);
5791 %}
5792 %}
5793
5794 // No constant pool entries required.
5795 instruct loadConL16(iRegLdst dst, immL16 src) %{
5796 match(Set dst src);
5797
5798 format %{ "LI $dst, $src \t// long" %}
5799 size(4);
5800 ins_encode %{
5801 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5802 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5803 %}
5804 ins_pipe(pipe_class_default);
5805 %}
5806
5807 // Load long constant 0xssssssss????0000
5808 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5809 match(Set dst src);
5810 ins_cost(DEFAULT_COST);
5811
5812 format %{ "LIS $dst, $src.hi \t// long" %}
5813 size(4);
5814 ins_encode %{
5815 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5816 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5817 %}
5818 ins_pipe(pipe_class_default);
5819 %}
5820
5821 // To load a 32 bit constant: merge lower 16 bits into already loaded
5822 // high 16 bits.
5823 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5824 // no match-rule, false predicate
5825 effect(DEF dst, USE src1, USE src2);
5826 predicate(false);
5827
5828 format %{ "ORI $dst, $src1, $src2.lo" %}
5829 size(4);
5830 ins_encode %{
5831 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5832 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5833 %}
5834 ins_pipe(pipe_class_default);
5835 %}
5836
5837 // Load 32-bit long constant
5838 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5839 match(Set dst src);
5840 ins_cost(DEFAULT_COST*2);
5841
5842 expand %{
5843 // Would like to use $src$$constant.
5844 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5845 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5846 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5847 iRegLdst tmpL;
5848 loadConL32hi16(tmpL, srcHi);
5849 loadConL32_lo16(dst, tmpL, srcLo);
5850 %}
5851 %}
5852
5853 // Load long constant 0x????000000000000.
5854 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5855 match(Set dst src);
5856 ins_cost(DEFAULT_COST);
5857
5858 expand %{
5859 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5860 immI shift32 %{ 32 %}
5861 iRegLdst tmpL;
5862 loadConL32hi16(tmpL, srcHi);
5863 lshiftL_regL_immI(dst, tmpL, shift32);
5864 %}
5865 %}
5866
5867 // Expand node for constant pool load: small offset.
5868 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5869 effect(DEF dst, USE src, USE toc);
5870 ins_cost(MEMORY_REF_COST);
5871
5872 ins_num_consts(1);
5873 // Needed so that CallDynamicJavaDirect can compute the address of this
5874 // instruction for relocation.
5875 ins_field_cbuf_insts_offset(int);
5876
5877 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5878 size(4);
5879 ins_encode( enc_load_long_constL(dst, src, toc) );
5880 ins_pipe(pipe_class_memory);
5881 %}
5882
5883 // Expand node for constant pool load: large offset.
5884 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5885 effect(DEF dst, USE src, USE toc);
5886 predicate(false);
5887
5888 ins_num_consts(1);
5889 ins_field_const_toc_offset(int);
5890 // Needed so that CallDynamicJavaDirect can compute the address of this
5891 // instruction for relocation.
5892 ins_field_cbuf_insts_offset(int);
5893
5894 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5895 size(4);
5896 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5897 ins_pipe(pipe_class_default);
5898 %}
5899
5900 // Expand node for constant pool load: large offset.
5901 // No constant pool entries required.
5902 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5903 effect(DEF dst, USE src, USE base);
5904 predicate(false);
5905
5906 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5907
5908 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5909 size(4);
5910 ins_encode %{
5911 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5912 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5913 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5914 %}
5915 ins_pipe(pipe_class_memory);
5916 %}
5917
5918 // Load long constant from constant table. Expand in case of
5919 // offset > 16 bit is needed.
5920 // Adlc adds toc node MachConstantTableBase.
5921 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5922 match(Set dst src);
5923 ins_cost(MEMORY_REF_COST);
5924
5925 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5926 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5927 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5928 %}
5929
5930 // Load NULL as compressed oop.
5931 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5932 match(Set dst src);
5933 ins_cost(DEFAULT_COST);
5934
5935 format %{ "LI $dst, $src \t// compressed ptr" %}
5936 size(4);
5937 ins_encode %{
5938 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5939 __ li($dst$$Register, 0);
5940 %}
5941 ins_pipe(pipe_class_default);
5942 %}
5943
5944 // Load hi part of compressed oop constant.
5945 instruct loadConN_hi(iRegNdst dst, immN src) %{
5946 effect(DEF dst, USE src);
5947 ins_cost(DEFAULT_COST);
5948
5949 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5950 size(4);
5951 ins_encode %{
5952 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5953 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5954 %}
5955 ins_pipe(pipe_class_default);
5956 %}
5957
5958 // Add lo part of compressed oop constant to already loaded hi part.
5959 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5960 effect(DEF dst, USE src1, USE src2);
5961 ins_cost(DEFAULT_COST);
5962
5963 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
5964 size(4);
5965 ins_encode %{
5966 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5967 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5968 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5969 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5970 __ relocate(rspec, 1);
5971 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5972 %}
5973 ins_pipe(pipe_class_default);
5974 %}
5975
5976 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5977 // leaving the upper 32 bits with sign-extension bits.
5978 // This clears these bits: dst = src & 0xFFFFFFFF.
5979 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5980 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
5981 effect(DEF dst, USE src);
5982 predicate(false);
5983
5984 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
5985 size(4);
5986 ins_encode %{
5987 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
5988 __ clrldi($dst$$Register, $src$$Register, 0x20);
5989 %}
5990 ins_pipe(pipe_class_default);
5991 %}
5992
5993 // Loading ConN must be postalloc expanded so that edges between
5994 // the nodes are safe. They may not interfere with a safepoint.
5995 // GL TODO: This needs three instructions: better put this into the constant pool.
5996 instruct loadConN_Ex(iRegNdst dst, immN src) %{
5997 match(Set dst src);
5998 ins_cost(DEFAULT_COST*2);
5999
6000 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6001 postalloc_expand %{
6002 MachNode *m1 = new (C) loadConN_hiNode();
6003 MachNode *m2 = new (C) loadConN_loNode();
6004 MachNode *m3 = new (C) clearMs32bNode();
6005 m1->add_req(NULL);
6006 m2->add_req(NULL, m1);
6007 m3->add_req(NULL, m2);
6008 m1->_opnds[0] = op_dst;
6009 m1->_opnds[1] = op_src;
6010 m2->_opnds[0] = op_dst;
6011 m2->_opnds[1] = op_dst;
6012 m2->_opnds[2] = op_src;
6013 m3->_opnds[0] = op_dst;
6014 m3->_opnds[1] = op_dst;
6015 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6016 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6017 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6018 nodes->push(m1);
6019 nodes->push(m2);
6020 nodes->push(m3);
6021 %}
6022 %}
6023
6024 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
6025 effect(DEF dst, USE src);
6026 ins_cost(DEFAULT_COST);
6027
6028 format %{ "LIS $dst, $src \t// narrow oop hi" %}
6029 size(4);
6030 ins_encode %{
6031 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6032 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6033 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6034 %}
6035 ins_pipe(pipe_class_default);
6036 %}
6037
6038 // This needs a match rule so that build_oop_map knows this is
6039 // not a narrow oop.
6040 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6041 match(Set dst src1);
6042 effect(TEMP src2);
6043 ins_cost(DEFAULT_COST);
6044
6045 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %}
6046 size(4);
6047 ins_encode %{
6048 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6049 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6050 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6051 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6052 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6053
6054 __ relocate(rspec, 1);
6055 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6056 %}
6057 ins_pipe(pipe_class_default);
6058 %}
6059
6060 // Loading ConNKlass must be postalloc expanded so that edges between
6061 // the nodes are safe. They may not interfere with a safepoint.
6062 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6063 match(Set dst src);
6064 ins_cost(DEFAULT_COST*2);
6065
6066 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6067 postalloc_expand %{
6068 // Load high bits into register. Sign extended.
6069 MachNode *m1 = new (C) loadConNKlass_hiNode();
6070 m1->add_req(NULL);
6071 m1->_opnds[0] = op_dst;
6072 m1->_opnds[1] = op_src;
6073 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6074 nodes->push(m1);
6075
6076 MachNode *m2 = m1;
6077 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6078 // Value might be 1-extended. Mask out these bits.
6079 m2 = new (C) clearMs32bNode();
6080 m2->add_req(NULL, m1);
6081 m2->_opnds[0] = op_dst;
6082 m2->_opnds[1] = op_dst;
6083 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6084 nodes->push(m2);
6085 }
6086
6087 MachNode *m3 = new (C) loadConNKlass_loNode();
6088 m3->add_req(NULL, m2);
6089 m3->_opnds[0] = op_dst;
6090 m3->_opnds[1] = op_src;
6091 m3->_opnds[2] = op_dst;
6092 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6093 nodes->push(m3);
6094 %}
6095 %}
6096
6097 // 0x1 is used in object initialization (initial object header).
6098 // No constant pool entries required.
6099 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6100 match(Set dst src);
6101
6102 format %{ "LI $dst, $src \t// ptr" %}
6103 size(4);
6104 ins_encode %{
6105 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6106 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6107 %}
6108 ins_pipe(pipe_class_default);
6109 %}
6110
6111 // Expand node for constant pool load: small offset.
6112 // The match rule is needed to generate the correct bottom_type(),
6113 // however this node should never match. The use of predicate is not
6114 // possible since ADLC forbids predicates for chain rules. The higher
6115 // costs do not prevent matching in this case. For that reason the
6116 // operand immP_NM with predicate(false) is used.
6117 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6118 match(Set dst src);
6119 effect(TEMP toc);
6120
6121 ins_num_consts(1);
6122
6123 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6124 size(4);
6125 ins_encode( enc_load_long_constP(dst, src, toc) );
6126 ins_pipe(pipe_class_memory);
6127 %}
6128
6129 // Expand node for constant pool load: large offset.
6130 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6131 effect(DEF dst, USE src, USE toc);
6132 predicate(false);
6133
6134 ins_num_consts(1);
6135 ins_field_const_toc_offset(int);
6136
6137 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6138 size(4);
6139 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6140 ins_pipe(pipe_class_default);
6141 %}
6142
6143 // Expand node for constant pool load: large offset.
6144 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6145 match(Set dst src);
6146 effect(TEMP base);
6147
6148 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6149
6150 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6151 size(4);
6152 ins_encode %{
6153 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6154 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6155 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6156 %}
6157 ins_pipe(pipe_class_memory);
6158 %}
6159
6160 // Load pointer constant from constant table. Expand in case an
6161 // offset > 16 bit is needed.
6162 // Adlc adds toc node MachConstantTableBase.
6163 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6164 match(Set dst src);
6165 ins_cost(MEMORY_REF_COST);
6166
6167 // This rule does not use "expand" because then
6168 // the result type is not known to be an Oop. An ADLC
6169 // enhancement will be needed to make that work - not worth it!
6170
6171 // If this instruction rematerializes, it prolongs the live range
6172 // of the toc node, causing illegal graphs.
6173 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6174 ins_cannot_rematerialize(true);
6175
6176 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6177 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6178 %}
6179
6180 // Expand node for constant pool load: small offset.
6181 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6182 effect(DEF dst, USE src, USE toc);
6183 ins_cost(MEMORY_REF_COST);
6184
6185 ins_num_consts(1);
6186
6187 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6188 size(4);
6189 ins_encode %{
6190 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6191 address float_address = __ float_constant($src$$constant);
6192 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6193 %}
6194 ins_pipe(pipe_class_memory);
6195 %}
6196
6197 // Expand node for constant pool load: large offset.
6198 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6199 effect(DEF dst, USE src, USE toc);
6200 ins_cost(MEMORY_REF_COST);
6201
6202 ins_num_consts(1);
6203
6204 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6205 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6206 "ADDIS $toc, $toc, -offset_hi"%}
6207 size(12);
6208 ins_encode %{
6209 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6210 FloatRegister Rdst = $dst$$FloatRegister;
6211 Register Rtoc = $toc$$Register;
6212 address float_address = __ float_constant($src$$constant);
6213 int offset = __ offset_to_method_toc(float_address);
6214 int hi = (offset + (1<<15))>>16;
6215 int lo = offset - hi * (1<<16);
6216
6217 __ addis(Rtoc, Rtoc, hi);
6218 __ lfs(Rdst, lo, Rtoc);
6219 __ addis(Rtoc, Rtoc, -hi);
6220 %}
6221 ins_pipe(pipe_class_memory);
6222 %}
6223
6224 // Adlc adds toc node MachConstantTableBase.
6225 instruct loadConF_Ex(regF dst, immF src) %{
6226 match(Set dst src);
6227 ins_cost(MEMORY_REF_COST);
6228
6229 // See loadConP.
6230 ins_cannot_rematerialize(true);
6231
6232 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6233 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6234 %}
6235
6236 // Expand node for constant pool load: small offset.
6237 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6238 effect(DEF dst, USE src, USE toc);
6239 ins_cost(MEMORY_REF_COST);
6240
6241 ins_num_consts(1);
6242
6243 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6244 size(4);
6245 ins_encode %{
6246 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6247 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6248 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6249 %}
6250 ins_pipe(pipe_class_memory);
6251 %}
6252
6253 // Expand node for constant pool load: large offset.
6254 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6255 effect(DEF dst, USE src, USE toc);
6256 ins_cost(MEMORY_REF_COST);
6257
6258 ins_num_consts(1);
6259
6260 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6261 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6262 "ADDIS $toc, $toc, -offset_hi" %}
6263 size(12);
6264 ins_encode %{
6265 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6266 FloatRegister Rdst = $dst$$FloatRegister;
6267 Register Rtoc = $toc$$Register;
6268 address float_address = __ double_constant($src$$constant);
6269 int offset = __ offset_to_method_toc(float_address);
6270 int hi = (offset + (1<<15))>>16;
6271 int lo = offset - hi * (1<<16);
6272
6273 __ addis(Rtoc, Rtoc, hi);
6274 __ lfd(Rdst, lo, Rtoc);
6275 __ addis(Rtoc, Rtoc, -hi);
6276 %}
6277 ins_pipe(pipe_class_memory);
6278 %}
6279
6280 // Adlc adds toc node MachConstantTableBase.
6281 instruct loadConD_Ex(regD dst, immD src) %{
6282 match(Set dst src);
6283 ins_cost(MEMORY_REF_COST);
6284
6285 // See loadConP.
6286 ins_cannot_rematerialize(true);
6287
6288 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6289 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6290 %}
6291
6292 // Prefetch instructions.
6293 // Must be safe to execute with invalid address (cannot fault).
6294
6295 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6296 match(PrefetchRead (AddP mem src));
6297 ins_cost(MEMORY_REF_COST);
6298
6299 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6300 size(4);
6301 ins_encode %{
6302 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6303 __ dcbt($src$$Register, $mem$$base$$Register);
6304 %}
6305 ins_pipe(pipe_class_memory);
6306 %}
6307
6308 instruct prefetchr_no_offset(indirectMemory mem) %{
6309 match(PrefetchRead mem);
6310 ins_cost(MEMORY_REF_COST);
6311
6312 format %{ "PREFETCH $mem" %}
6313 size(4);
6314 ins_encode %{
6315 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6316 __ dcbt($mem$$base$$Register);
6317 %}
6318 ins_pipe(pipe_class_memory);
6319 %}
6320
6321 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6322 match(PrefetchWrite (AddP mem src));
6323 ins_cost(MEMORY_REF_COST);
6324
6325 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6326 size(4);
6327 ins_encode %{
6328 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6329 __ dcbtst($src$$Register, $mem$$base$$Register);
6330 %}
6331 ins_pipe(pipe_class_memory);
6332 %}
6333
6334 instruct prefetchw_no_offset(indirectMemory mem) %{
6335 match(PrefetchWrite mem);
6336 ins_cost(MEMORY_REF_COST);
6337
6338 format %{ "PREFETCH $mem" %}
6339 size(4);
6340 ins_encode %{
6341 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6342 __ dcbtst($mem$$base$$Register);
6343 %}
6344 ins_pipe(pipe_class_memory);
6345 %}
6346
6347 // Special prefetch versions which use the dcbz instruction.
6348 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6349 match(PrefetchAllocation (AddP mem src));
6350 predicate(AllocatePrefetchStyle == 3);
6351 ins_cost(MEMORY_REF_COST);
6352
6353 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6354 size(4);
6355 ins_encode %{
6356 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6357 __ dcbz($src$$Register, $mem$$base$$Register);
6358 %}
6359 ins_pipe(pipe_class_memory);
6360 %}
6361
6362 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6363 match(PrefetchAllocation mem);
6364 predicate(AllocatePrefetchStyle == 3);
6365 ins_cost(MEMORY_REF_COST);
6366
6367 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6368 size(4);
6369 ins_encode %{
6370 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6371 __ dcbz($mem$$base$$Register);
6372 %}
6373 ins_pipe(pipe_class_memory);
6374 %}
6375
6376 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6377 match(PrefetchAllocation (AddP mem src));
6378 predicate(AllocatePrefetchStyle != 3);
6379 ins_cost(MEMORY_REF_COST);
6380
6381 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6382 size(4);
6383 ins_encode %{
6384 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6385 __ dcbtst($src$$Register, $mem$$base$$Register);
6386 %}
6387 ins_pipe(pipe_class_memory);
6388 %}
6389
6390 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6391 match(PrefetchAllocation mem);
6392 predicate(AllocatePrefetchStyle != 3);
6393 ins_cost(MEMORY_REF_COST);
6394
6395 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6396 size(4);
6397 ins_encode %{
6398 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6399 __ dcbtst($mem$$base$$Register);
6400 %}
6401 ins_pipe(pipe_class_memory);
6402 %}
6403
6404 //----------Store Instructions-------------------------------------------------
6405
6406 // Store Byte
6407 instruct storeB(memory mem, iRegIsrc src) %{
6408 match(Set mem (StoreB mem src));
6409 ins_cost(MEMORY_REF_COST);
6410
6411 format %{ "STB $src, $mem \t// byte" %}
6412 size(4);
6413 ins_encode %{
6414 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6415 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6416 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6417 %}
6418 ins_pipe(pipe_class_memory);
6419 %}
6420
6421 // Store Char/Short
6422 instruct storeC(memory mem, iRegIsrc src) %{
6423 match(Set mem (StoreC mem src));
6424 ins_cost(MEMORY_REF_COST);
6425
6426 format %{ "STH $src, $mem \t// short" %}
6427 size(4);
6428 ins_encode %{
6429 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6430 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6431 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6432 %}
6433 ins_pipe(pipe_class_memory);
6434 %}
6435
6436 // Store Integer
6437 instruct storeI(memory mem, iRegIsrc src) %{
6438 match(Set mem (StoreI mem src));
6439 ins_cost(MEMORY_REF_COST);
6440
6441 format %{ "STW $src, $mem" %}
6442 size(4);
6443 ins_encode( enc_stw(src, mem) );
6444 ins_pipe(pipe_class_memory);
6445 %}
6446
6447 // ConvL2I + StoreI.
6448 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6449 match(Set mem (StoreI mem (ConvL2I src)));
6450 ins_cost(MEMORY_REF_COST);
6451
6452 format %{ "STW l2i($src), $mem" %}
6453 size(4);
6454 ins_encode( enc_stw(src, mem) );
6455 ins_pipe(pipe_class_memory);
6456 %}
6457
6458 // Store Long
6459 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6460 match(Set mem (StoreL mem src));
6461 ins_cost(MEMORY_REF_COST);
6462
6463 format %{ "STD $src, $mem \t// long" %}
6464 size(4);
6465 ins_encode( enc_std(src, mem) );
6466 ins_pipe(pipe_class_memory);
6467 %}
6468
6469 // Store super word nodes.
6470
6471 // Store Aligned Packed Byte long register to memory
6472 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6473 predicate(n->as_StoreVector()->memory_size() == 8);
6474 match(Set mem (StoreVector mem src));
6475 ins_cost(MEMORY_REF_COST);
6476
6477 format %{ "STD $mem, $src \t// packed8B" %}
6478 size(4);
6479 ins_encode( enc_std(src, mem) );
6480 ins_pipe(pipe_class_memory);
6481 %}
6482
6483 // Store Compressed Oop
6484 instruct storeN(memory dst, iRegN_P2N src) %{
6485 match(Set dst (StoreN dst src));
6486 ins_cost(MEMORY_REF_COST);
6487
6488 format %{ "STW $src, $dst \t// compressed oop" %}
6489 size(4);
6490 ins_encode( enc_stw(src, dst) );
6491 ins_pipe(pipe_class_memory);
6492 %}
6493
6494 // Store Compressed KLass
6495 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6496 match(Set dst (StoreNKlass dst src));
6497 ins_cost(MEMORY_REF_COST);
6498
6499 format %{ "STW $src, $dst \t// compressed klass" %}
6500 size(4);
6501 ins_encode( enc_stw(src, dst) );
6502 ins_pipe(pipe_class_memory);
6503 %}
6504
6505 // Store Pointer
6506 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6507 match(Set dst (StoreP dst src));
6508 ins_cost(MEMORY_REF_COST);
6509
6510 format %{ "STD $src, $dst \t// ptr" %}
6511 size(4);
6512 ins_encode( enc_std(src, dst) );
6513 ins_pipe(pipe_class_memory);
6514 %}
6515
6516 // Store Float
6517 instruct storeF(memory mem, regF src) %{
6518 match(Set mem (StoreF mem src));
6519 ins_cost(MEMORY_REF_COST);
6520
6521 format %{ "STFS $src, $mem" %}
6522 size(4);
6523 ins_encode( enc_stfs(src, mem) );
6524 ins_pipe(pipe_class_memory);
6525 %}
6526
6527 // Store Double
6528 instruct storeD(memory mem, regD src) %{
6529 match(Set mem (StoreD mem src));
6530 ins_cost(MEMORY_REF_COST);
6531
6532 format %{ "STFD $src, $mem" %}
6533 size(4);
6534 ins_encode( enc_stfd(src, mem) );
6535 ins_pipe(pipe_class_memory);
6536 %}
6537
6538 //----------Store Instructions With Zeros--------------------------------------
6539
6540 // Card-mark for CMS garbage collection.
6541 // This cardmark does an optimization so that it must not always
6542 // do a releasing store. For this, it gets the address of
6543 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6544 // (Using releaseFieldAddr in the match rule is a hack.)
6545 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6546 match(Set mem (StoreCM mem releaseFieldAddr));
6547 predicate(false);
6548 ins_cost(MEMORY_REF_COST);
6549
6550 // See loadConP.
6551 ins_cannot_rematerialize(true);
6552
6553 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6554 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6555 ins_pipe(pipe_class_memory);
6556 %}
6557
6558 // Card-mark for CMS garbage collection.
6559 // This cardmark does an optimization so that it must not always
6560 // do a releasing store. For this, it needs the constant address of
6561 // CMSCollectorCardTableModRefBSExt::_requires_release.
6562 // This constant address is split off here by expand so we can use
6563 // adlc / matcher functionality to load it from the constant section.
6564 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6565 match(Set mem (StoreCM mem zero));
6566 predicate(UseConcMarkSweepGC);
6567
6568 expand %{
6569 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6570 iRegLdst releaseFieldAddress;
6571 loadConL_Ex(releaseFieldAddress, baseImm);
6572 storeCM_CMS(mem, releaseFieldAddress);
6573 %}
6574 %}
6575
6576 instruct storeCM_G1(memory mem, immI_0 zero) %{
6577 match(Set mem (StoreCM mem zero));
6578 predicate(UseG1GC);
6579 ins_cost(MEMORY_REF_COST);
6580
6581 ins_cannot_rematerialize(true);
6582
6583 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6584 size(8);
6585 ins_encode %{
6586 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6587 __ li(R0, 0);
6588 //__ release(); // G1: oops are allowed to get visible after dirty marking
6589 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6590 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6591 %}
6592 ins_pipe(pipe_class_memory);
6593 %}
6594
6595 // Convert oop pointer into compressed form.
6596
6597 // Nodes for postalloc expand.
6598
6599 // Shift node for expand.
6600 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6601 // The match rule is needed to make it a 'MachTypeNode'!
6602 match(Set dst (EncodeP src));
6603 predicate(false);
6604
6605 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6606 size(4);
6607 ins_encode %{
6608 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6609 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6610 %}
6611 ins_pipe(pipe_class_default);
6612 %}
6613
6614 // Add node for expand.
6615 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6616 // The match rule is needed to make it a 'MachTypeNode'!
6617 match(Set dst (EncodeP src));
6618 predicate(false);
6619
6620 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6621 size(4);
6622 ins_encode %{
6623 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6624 __ subf($dst$$Register, R30, $src$$Register);
6625 %}
6626 ins_pipe(pipe_class_default);
6627 %}
6628
6629 // Conditional sub base.
6630 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6631 // The match rule is needed to make it a 'MachTypeNode'!
6632 match(Set dst (EncodeP (Binary crx src1)));
6633 predicate(false);
6634
6635 ins_variable_size_depending_on_alignment(true);
6636
6637 format %{ "BEQ $crx, done\n\t"
6638 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6639 "done:" %}
6640 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6641 ins_encode %{
6642 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6643 Label done;
6644 __ beq($crx$$CondRegister, done);
6645 __ subf($dst$$Register, R30, $src1$$Register);
6646 // TODO PPC port __ endgroup_if_needed(_size == 12);
6647 __ bind(done);
6648 %}
6649 ins_pipe(pipe_class_default);
6650 %}
6651
6652 // Power 7 can use isel instruction
6653 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6654 // The match rule is needed to make it a 'MachTypeNode'!
6655 match(Set dst (EncodeP (Binary crx src1)));
6656 predicate(false);
6657
6658 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6659 size(4);
6660 ins_encode %{
6661 // This is a Power7 instruction for which no machine description exists.
6662 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6663 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6664 %}
6665 ins_pipe(pipe_class_default);
6666 %}
6667
6668 // base != 0
6669 // 32G aligned narrow oop base.
6670 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6671 match(Set dst (EncodeP src));
6672 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6673
6674 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6675 size(4);
6676 ins_encode %{
6677 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6678 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6679 %}
6680 ins_pipe(pipe_class_default);
6681 %}
6682
6683 // shift != 0, base != 0
6684 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6685 match(Set dst (EncodeP src));
6686 effect(TEMP crx);
6687 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6688 Universe::narrow_oop_shift() != 0 &&
6689 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6690
6691 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6692 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6693 %}
6694
6695 // shift != 0, base != 0
6696 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6697 match(Set dst (EncodeP src));
6698 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6699 Universe::narrow_oop_shift() != 0 &&
6700 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6701
6702 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6703 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6704 %}
6705
6706 // shift != 0, base == 0
6707 // TODO: This is the same as encodeP_shift. Merge!
6708 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6709 match(Set dst (EncodeP src));
6710 predicate(Universe::narrow_oop_shift() != 0 &&
6711 Universe::narrow_oop_base() ==0);
6712
6713 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6714 size(4);
6715 ins_encode %{
6716 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6717 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6718 %}
6719 ins_pipe(pipe_class_default);
6720 %}
6721
6722 // Compressed OOPs with narrow_oop_shift == 0.
6723 // shift == 0, base == 0
6724 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6725 match(Set dst (EncodeP src));
6726 predicate(Universe::narrow_oop_shift() == 0);
6727
6728 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6729 // variable size, 0 or 4.
6730 ins_encode %{
6731 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6732 __ mr_if_needed($dst$$Register, $src$$Register);
6733 %}
6734 ins_pipe(pipe_class_default);
6735 %}
6736
6737 // Decode nodes.
6738
6739 // Shift node for expand.
6740 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6741 // The match rule is needed to make it a 'MachTypeNode'!
6742 match(Set dst (DecodeN src));
6743 predicate(false);
6744
6745 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6746 size(4);
6747 ins_encode %{
6748 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6749 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6750 %}
6751 ins_pipe(pipe_class_default);
6752 %}
6753
6754 // Add node for expand.
6755 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6756 // The match rule is needed to make it a 'MachTypeNode'!
6757 match(Set dst (DecodeN src));
6758 predicate(false);
6759
6760 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6761 size(4);
6762 ins_encode %{
6763 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6764 __ add($dst$$Register, $src$$Register, R30);
6765 %}
6766 ins_pipe(pipe_class_default);
6767 %}
6768
6769 // conditianal add base for expand
6770 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6771 // The match rule is needed to make it a 'MachTypeNode'!
6772 // NOTICE that the rule is nonsense - we just have to make sure that:
6773 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6774 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6775 match(Set dst (DecodeN (Binary crx src1)));
6776 predicate(false);
6777
6778 ins_variable_size_depending_on_alignment(true);
6779
6780 format %{ "BEQ $crx, done\n\t"
6781 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6782 "done:" %}
6783 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6784 ins_encode %{
6785 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6786 Label done;
6787 __ beq($crx$$CondRegister, done);
6788 __ add($dst$$Register, $src1$$Register, R30);
6789 // TODO PPC port __ endgroup_if_needed(_size == 12);
6790 __ bind(done);
6791 %}
6792 ins_pipe(pipe_class_default);
6793 %}
6794
6795 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6796 // The match rule is needed to make it a 'MachTypeNode'!
6797 // NOTICE that the rule is nonsense - we just have to make sure that:
6798 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6799 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6800 match(Set dst (DecodeN (Binary crx src1)));
6801 predicate(false);
6802
6803 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6804 size(4);
6805 ins_encode %{
6806 // This is a Power7 instruction for which no machine description exists.
6807 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6808 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6809 %}
6810 ins_pipe(pipe_class_default);
6811 %}
6812
6813 // shift != 0, base != 0
6814 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6815 match(Set dst (DecodeN src));
6816 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6817 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6818 Universe::narrow_oop_shift() != 0 &&
6819 Universe::narrow_oop_base() != 0);
6820 effect(TEMP crx);
6821
6822 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6823 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6824 %}
6825
6826 // shift != 0, base == 0
6827 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6828 match(Set dst (DecodeN src));
6829 predicate(Universe::narrow_oop_shift() != 0 &&
6830 Universe::narrow_oop_base() == 0);
6831
6832 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6833 size(4);
6834 ins_encode %{
6835 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6836 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6837 %}
6838 ins_pipe(pipe_class_default);
6839 %}
6840
6841 // src != 0, shift != 0, base != 0
6842 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6843 match(Set dst (DecodeN src));
6844 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6845 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6846 Universe::narrow_oop_shift() != 0 &&
6847 Universe::narrow_oop_base() != 0);
6848
6849 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6850 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6851 %}
6852
6853 // Compressed OOPs with narrow_oop_shift == 0.
6854 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6855 match(Set dst (DecodeN src));
6856 predicate(Universe::narrow_oop_shift() == 0);
6857 ins_cost(DEFAULT_COST);
6858
6859 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6860 // variable size, 0 or 4.
6861 ins_encode %{
6862 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6863 __ mr_if_needed($dst$$Register, $src$$Register);
6864 %}
6865 ins_pipe(pipe_class_default);
6866 %}
6867
6868 // Convert compressed oop into int for vectors alignment masking.
6869 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6870 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6871 predicate(Universe::narrow_oop_shift() == 0);
6872 ins_cost(DEFAULT_COST);
6873
6874 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6875 // variable size, 0 or 4.
6876 ins_encode %{
6877 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6878 __ mr_if_needed($dst$$Register, $src$$Register);
6879 %}
6880 ins_pipe(pipe_class_default);
6881 %}
6882
6883 // Convert klass pointer into compressed form.
6884
6885 // Nodes for postalloc expand.
6886
6887 // Shift node for expand.
6888 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6889 // The match rule is needed to make it a 'MachTypeNode'!
6890 match(Set dst (EncodePKlass src));
6891 predicate(false);
6892
6893 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6894 size(4);
6895 ins_encode %{
6896 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6897 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6898 %}
6899 ins_pipe(pipe_class_default);
6900 %}
6901
6902 // Add node for expand.
6903 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6904 // The match rule is needed to make it a 'MachTypeNode'!
6905 match(Set dst (EncodePKlass (Binary base src)));
6906 predicate(false);
6907
6908 format %{ "SUB $dst, $base, $src \t// encode" %}
6909 size(4);
6910 ins_encode %{
6911 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6912 __ subf($dst$$Register, $base$$Register, $src$$Register);
6913 %}
6914 ins_pipe(pipe_class_default);
6915 %}
6916
6917 // base != 0
6918 // 32G aligned narrow oop base.
6919 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6920 match(Set dst (EncodePKlass src));
6921 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6922
6923 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6924 size(4);
6925 ins_encode %{
6926 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6927 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6928 %}
6929 ins_pipe(pipe_class_default);
6930 %}
6931
6932 // shift != 0, base != 0
6933 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6934 match(Set dst (EncodePKlass (Binary base src)));
6935 predicate(false);
6936
6937 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6938 postalloc_expand %{
6939 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode();
6940 n1->add_req(n_region, n_base, n_src);
6941 n1->_opnds[0] = op_dst;
6942 n1->_opnds[1] = op_base;
6943 n1->_opnds[2] = op_src;
6944 n1->_bottom_type = _bottom_type;
6945
6946 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode();
6947 n2->add_req(n_region, n1);
6948 n2->_opnds[0] = op_dst;
6949 n2->_opnds[1] = op_dst;
6950 n2->_bottom_type = _bottom_type;
6951 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6952 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6953
6954 nodes->push(n1);
6955 nodes->push(n2);
6956 %}
6957 %}
6958
6959 // shift != 0, base != 0
6960 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
6961 match(Set dst (EncodePKlass src));
6962 //predicate(Universe::narrow_klass_shift() != 0 &&
6963 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
6964
6965 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6966 ins_cost(DEFAULT_COST*2); // Don't count constant.
6967 expand %{
6968 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
6969 iRegLdst base;
6970 loadConL_Ex(base, baseImm);
6971 encodePKlass_not_null_Ex(dst, base, src);
6972 %}
6973 %}
6974
6975 // Decode nodes.
6976
6977 // Shift node for expand.
6978 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
6979 // The match rule is needed to make it a 'MachTypeNode'!
6980 match(Set dst (DecodeNKlass src));
6981 predicate(false);
6982
6983 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
6984 size(4);
6985 ins_encode %{
6986 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6987 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6988 %}
6989 ins_pipe(pipe_class_default);
6990 %}
6991
6992 // Add node for expand.
6993
6994 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6995 // The match rule is needed to make it a 'MachTypeNode'!
6996 match(Set dst (DecodeNKlass (Binary base src)));
6997 predicate(false);
6998
6999 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7000 size(4);
7001 ins_encode %{
7002 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7003 __ add($dst$$Register, $base$$Register, $src$$Register);
7004 %}
7005 ins_pipe(pipe_class_default);
7006 %}
7007
7008 // src != 0, shift != 0, base != 0
7009 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7010 match(Set dst (DecodeNKlass (Binary base src)));
7011 //effect(kill src); // We need a register for the immediate result after shifting.
7012 predicate(false);
7013
7014 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7015 postalloc_expand %{
7016 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode();
7017 n1->add_req(n_region, n_base, n_src);
7018 n1->_opnds[0] = op_dst;
7019 n1->_opnds[1] = op_base;
7020 n1->_opnds[2] = op_src;
7021 n1->_bottom_type = _bottom_type;
7022
7023 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
7024 n2->add_req(n_region, n2);
7025 n2->_opnds[0] = op_dst;
7026 n2->_opnds[1] = op_dst;
7027 n2->_bottom_type = _bottom_type;
7028
7029 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7030 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7031
7032 nodes->push(n1);
7033 nodes->push(n2);
7034 %}
7035 %}
7036
7037 // src != 0, shift != 0, base != 0
7038 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7039 match(Set dst (DecodeNKlass src));
7040 // predicate(Universe::narrow_klass_shift() != 0 &&
7041 // Universe::narrow_klass_base() != 0);
7042
7043 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7044
7045 ins_cost(DEFAULT_COST*2); // Don't count constant.
7046 expand %{
7047 // We add first, then we shift. Like this, we can get along with one register less.
7048 // But we have to load the base pre-shifted.
7049 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7050 iRegLdst base;
7051 loadConL_Ex(base, baseImm);
7052 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7053 %}
7054 %}
7055
7056 //----------MemBar Instructions-----------------------------------------------
7057 // Memory barrier flavors
7058
7059 instruct membar_acquire() %{
7060 match(LoadFence);
7061 ins_cost(4*MEMORY_REF_COST);
7062
7063 format %{ "MEMBAR-acquire" %}
7064 size(4);
7065 ins_encode %{
7066 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7067 __ acquire();
7068 %}
7069 ins_pipe(pipe_class_default);
7070 %}
7071
7072 instruct unnecessary_membar_acquire() %{
7073 match(MemBarAcquire);
7074 ins_cost(0);
7075
7076 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7077 size(0);
7078 ins_encode( /*empty*/ );
7079 ins_pipe(pipe_class_default);
7080 %}
7081
7082 instruct membar_acquire_lock() %{
7083 match(MemBarAcquireLock);
7084 ins_cost(0);
7085
7086 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7087 size(0);
7088 ins_encode( /*empty*/ );
7089 ins_pipe(pipe_class_default);
7090 %}
7091
7092 instruct membar_release() %{
7093 match(MemBarRelease);
7094 match(StoreFence);
7095 ins_cost(4*MEMORY_REF_COST);
7096
7097 format %{ "MEMBAR-release" %}
7098 size(4);
7099 ins_encode %{
7100 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7101 __ release();
7102 %}
7103 ins_pipe(pipe_class_default);
7104 %}
7105
7106 instruct membar_storestore() %{
7107 match(MemBarStoreStore);
7108 ins_cost(4*MEMORY_REF_COST);
7109
7110 format %{ "MEMBAR-store-store" %}
7111 size(4);
7112 ins_encode %{
7113 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7114 __ membar(Assembler::StoreStore);
7115 %}
7116 ins_pipe(pipe_class_default);
7117 %}
7118
7119 instruct membar_release_lock() %{
7120 match(MemBarReleaseLock);
7121 ins_cost(0);
7122
7123 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7124 size(0);
7125 ins_encode( /*empty*/ );
7126 ins_pipe(pipe_class_default);
7127 %}
7128
7129 instruct membar_volatile() %{
7130 match(MemBarVolatile);
7131 ins_cost(4*MEMORY_REF_COST);
7132
7133 format %{ "MEMBAR-volatile" %}
7134 size(4);
7135 ins_encode %{
7136 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7137 __ fence();
7138 %}
7139 ins_pipe(pipe_class_default);
7140 %}
7141
7142 // This optimization is wrong on PPC. The following pattern is not supported:
7143 // MemBarVolatile
7144 // ^ ^
7145 // | |
7146 // CtrlProj MemProj
7147 // ^ ^
7148 // | |
7149 // | Load
7150 // |
7151 // MemBarVolatile
7152 //
7153 // The first MemBarVolatile could get optimized out! According to
7154 // Vladimir, this pattern can not occur on Oracle platforms.
7155 // However, it does occur on PPC64 (because of membars in
7156 // inline_unsafe_load_store).
7157 //
7158 // Add this node again if we found a good solution for inline_unsafe_load_store().
7159 // Don't forget to look at the implementation of post_store_load_barrier again,
7160 // we did other fixes in that method.
7161 //instruct unnecessary_membar_volatile() %{
7162 // match(MemBarVolatile);
7163 // predicate(Matcher::post_store_load_barrier(n));
7164 // ins_cost(0);
7165 //
7166 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7167 // size(0);
7168 // ins_encode( /*empty*/ );
7169 // ins_pipe(pipe_class_default);
7170 //%}
7171
7172 instruct membar_CPUOrder() %{
7173 match(MemBarCPUOrder);
7174 ins_cost(0);
7175
7176 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7177 size(0);
7178 ins_encode( /*empty*/ );
7179 ins_pipe(pipe_class_default);
7180 %}
7181
7182 //----------Conditional Move---------------------------------------------------
7183
7184 // Cmove using isel.
7185 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7186 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7187 predicate(VM_Version::has_isel());
7188 ins_cost(DEFAULT_COST);
7189
7190 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7191 size(4);
7192 ins_encode %{
7193 // This is a Power7 instruction for which no machine description
7194 // exists. Anyways, the scheduler should be off on Power7.
7195 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7196 int cc = $cmp$$cmpcode;
7197 __ isel($dst$$Register, $crx$$CondRegister,
7198 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7199 %}
7200 ins_pipe(pipe_class_default);
7201 %}
7202
7203 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7204 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7205 predicate(!VM_Version::has_isel());
7206 ins_cost(DEFAULT_COST+BRANCH_COST);
7207
7208 ins_variable_size_depending_on_alignment(true);
7209
7210 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7211 // Worst case is branch + move + stop, no stop without scheduler
7212 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7213 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7214 ins_pipe(pipe_class_default);
7215 %}
7216
7217 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7218 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7219 ins_cost(DEFAULT_COST+BRANCH_COST);
7220
7221 ins_variable_size_depending_on_alignment(true);
7222
7223 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7224 // Worst case is branch + move + stop, no stop without scheduler
7225 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7226 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7227 ins_pipe(pipe_class_default);
7228 %}
7229
7230 // Cmove using isel.
7231 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7232 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7233 predicate(VM_Version::has_isel());
7234 ins_cost(DEFAULT_COST);
7235
7236 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7237 size(4);
7238 ins_encode %{
7239 // This is a Power7 instruction for which no machine description
7240 // exists. Anyways, the scheduler should be off on Power7.
7241 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7242 int cc = $cmp$$cmpcode;
7243 __ isel($dst$$Register, $crx$$CondRegister,
7244 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7245 %}
7246 ins_pipe(pipe_class_default);
7247 %}
7248
7249 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7250 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7251 predicate(!VM_Version::has_isel());
7252 ins_cost(DEFAULT_COST+BRANCH_COST);
7253
7254 ins_variable_size_depending_on_alignment(true);
7255
7256 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7257 // Worst case is branch + move + stop, no stop without scheduler.
7258 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7259 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7260 ins_pipe(pipe_class_default);
7261 %}
7262
7263 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7264 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7265 ins_cost(DEFAULT_COST+BRANCH_COST);
7266
7267 ins_variable_size_depending_on_alignment(true);
7268
7269 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7270 // Worst case is branch + move + stop, no stop without scheduler.
7271 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7272 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7273 ins_pipe(pipe_class_default);
7274 %}
7275
7276 // Cmove using isel.
7277 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7278 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7279 predicate(VM_Version::has_isel());
7280 ins_cost(DEFAULT_COST);
7281
7282 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7283 size(4);
7284 ins_encode %{
7285 // This is a Power7 instruction for which no machine description
7286 // exists. Anyways, the scheduler should be off on Power7.
7287 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7288 int cc = $cmp$$cmpcode;
7289 __ isel($dst$$Register, $crx$$CondRegister,
7290 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7291 %}
7292 ins_pipe(pipe_class_default);
7293 %}
7294
7295 // Conditional move for RegN. Only cmov(reg, reg).
7296 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7297 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7298 predicate(!VM_Version::has_isel());
7299 ins_cost(DEFAULT_COST+BRANCH_COST);
7300
7301 ins_variable_size_depending_on_alignment(true);
7302
7303 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7304 // Worst case is branch + move + stop, no stop without scheduler.
7305 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7306 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7307 ins_pipe(pipe_class_default);
7308 %}
7309
7310 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7311 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7312 ins_cost(DEFAULT_COST+BRANCH_COST);
7313
7314 ins_variable_size_depending_on_alignment(true);
7315
7316 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7317 // Worst case is branch + move + stop, no stop without scheduler.
7318 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7319 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7320 ins_pipe(pipe_class_default);
7321 %}
7322
7323 // Cmove using isel.
7324 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7325 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7326 predicate(VM_Version::has_isel());
7327 ins_cost(DEFAULT_COST);
7328
7329 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7330 size(4);
7331 ins_encode %{
7332 // This is a Power7 instruction for which no machine description
7333 // exists. Anyways, the scheduler should be off on Power7.
7334 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7335 int cc = $cmp$$cmpcode;
7336 __ isel($dst$$Register, $crx$$CondRegister,
7337 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7338 %}
7339 ins_pipe(pipe_class_default);
7340 %}
7341
7342 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7343 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7344 predicate(!VM_Version::has_isel());
7345 ins_cost(DEFAULT_COST+BRANCH_COST);
7346
7347 ins_variable_size_depending_on_alignment(true);
7348
7349 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7350 // Worst case is branch + move + stop, no stop without scheduler.
7351 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7352 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7353 ins_pipe(pipe_class_default);
7354 %}
7355
7356 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7357 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7358 ins_cost(DEFAULT_COST+BRANCH_COST);
7359
7360 ins_variable_size_depending_on_alignment(true);
7361
7362 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7363 // Worst case is branch + move + stop, no stop without scheduler.
7364 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7365 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7366 ins_pipe(pipe_class_default);
7367 %}
7368
7369 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7370 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7371 ins_cost(DEFAULT_COST+BRANCH_COST);
7372
7373 ins_variable_size_depending_on_alignment(true);
7374
7375 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7376 // Worst case is branch + move + stop, no stop without scheduler.
7377 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7378 ins_encode %{
7379 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7380 Label done;
7381 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7382 // Branch if not (cmp crx).
7383 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7384 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7385 // TODO PPC port __ endgroup_if_needed(_size == 12);
7386 __ bind(done);
7387 %}
7388 ins_pipe(pipe_class_default);
7389 %}
7390
7391 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7392 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7393 ins_cost(DEFAULT_COST+BRANCH_COST);
7394
7395 ins_variable_size_depending_on_alignment(true);
7396
7397 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7398 // Worst case is branch + move + stop, no stop without scheduler.
7399 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7400 ins_encode %{
7401 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7402 Label done;
7403 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7404 // Branch if not (cmp crx).
7405 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7406 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7407 // TODO PPC port __ endgroup_if_needed(_size == 12);
7408 __ bind(done);
7409 %}
7410 ins_pipe(pipe_class_default);
7411 %}
7412
7413 //----------Conditional_store--------------------------------------------------
7414 // Conditional-store of the updated heap-top.
7415 // Used during allocation of the shared heap.
7416 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7417
7418 // As compareAndSwapL, but return flag register instead of boolean value in
7419 // int register.
7420 // Used by sun/misc/AtomicLongCSImpl.java.
7421 // Mem_ptr must be a memory operand, else this node does not get
7422 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7423 // can be rematerialized which leads to errors.
7424 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7425 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7426 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7427 ins_encode %{
7428 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7429 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7430 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7431 noreg, NULL, true);
7432 %}
7433 ins_pipe(pipe_class_default);
7434 %}
7435
7436 // As compareAndSwapP, but return flag register instead of boolean value in
7437 // int register.
7438 // This instruction is matched if UseTLAB is off.
7439 // Mem_ptr must be a memory operand, else this node does not get
7440 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7441 // can be rematerialized which leads to errors.
7442 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7443 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7444 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7445 ins_encode %{
7446 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7447 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7448 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7449 noreg, NULL, true);
7450 %}
7451 ins_pipe(pipe_class_default);
7452 %}
7453
7454 // Implement LoadPLocked. Must be ordered against changes of the memory location
7455 // by storePConditional.
7456 // Don't know whether this is ever used.
7457 instruct loadPLocked(iRegPdst dst, memory mem) %{
7458 match(Set dst (LoadPLocked mem));
7459 ins_cost(MEMORY_REF_COST);
7460
7461 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7462 "TWI $dst\n\t"
7463 "ISYNC" %}
7464 size(12);
7465 ins_encode( enc_ld_ac(dst, mem) );
7466 ins_pipe(pipe_class_memory);
7467 %}
7468
7469 //----------Compare-And-Swap---------------------------------------------------
7470
7471 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7472 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7473 // matched.
7474
7475 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7476 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7477 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7478 // Variable size: instruction count smaller if regs are disjoint.
7479 ins_encode %{
7480 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7481 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7482 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7483 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7484 $res$$Register, true);
7485 %}
7486 ins_pipe(pipe_class_default);
7487 %}
7488
7489 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7490 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7491 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7492 // Variable size: instruction count smaller if regs are disjoint.
7493 ins_encode %{
7494 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7495 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7496 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7497 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7498 $res$$Register, true);
7499 %}
7500 ins_pipe(pipe_class_default);
7501 %}
7502
7503 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7504 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7505 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7506 // Variable size: instruction count smaller if regs are disjoint.
7507 ins_encode %{
7508 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7509 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7510 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7511 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7512 $res$$Register, NULL, true);
7513 %}
7514 ins_pipe(pipe_class_default);
7515 %}
7516
7517 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7518 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7519 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7520 // Variable size: instruction count smaller if regs are disjoint.
7521 ins_encode %{
7522 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7523 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7524 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7525 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7526 $res$$Register, NULL, true);
7527 %}
7528 ins_pipe(pipe_class_default);
7529 %}
7530
7531 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7532 match(Set res (GetAndAddI mem_ptr src));
7533 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7534 // Variable size: instruction count smaller if regs are disjoint.
7535 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7536 ins_pipe(pipe_class_default);
7537 %}
7538
7539 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7540 match(Set res (GetAndAddL mem_ptr src));
7541 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7542 // Variable size: instruction count smaller if regs are disjoint.
7543 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7544 ins_pipe(pipe_class_default);
7545 %}
7546
7547 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7548 match(Set res (GetAndSetI mem_ptr src));
7549 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7550 // Variable size: instruction count smaller if regs are disjoint.
7551 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7552 ins_pipe(pipe_class_default);
7553 %}
7554
7555 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7556 match(Set res (GetAndSetL mem_ptr src));
7557 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7558 // Variable size: instruction count smaller if regs are disjoint.
7559 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7560 ins_pipe(pipe_class_default);
7561 %}
7562
7563 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7564 match(Set res (GetAndSetP mem_ptr src));
7565 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7566 // Variable size: instruction count smaller if regs are disjoint.
7567 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7568 ins_pipe(pipe_class_default);
7569 %}
7570
7571 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7572 match(Set res (GetAndSetN mem_ptr src));
7573 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7574 // Variable size: instruction count smaller if regs are disjoint.
7575 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7576 ins_pipe(pipe_class_default);
7577 %}
7578
7579 //----------Arithmetic Instructions--------------------------------------------
7580 // Addition Instructions
7581
7582 // Register Addition
7583 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7584 match(Set dst (AddI src1 src2));
7585 format %{ "ADD $dst, $src1, $src2" %}
7586 size(4);
7587 ins_encode %{
7588 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7589 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7590 %}
7591 ins_pipe(pipe_class_default);
7592 %}
7593
7594 // Expand does not work with above instruct. (??)
7595 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7596 // no match-rule
7597 effect(DEF dst, USE src1, USE src2);
7598 format %{ "ADD $dst, $src1, $src2" %}
7599 size(4);
7600 ins_encode %{
7601 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7602 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7603 %}
7604 ins_pipe(pipe_class_default);
7605 %}
7606
7607 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7608 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7609 ins_cost(DEFAULT_COST*3);
7610
7611 expand %{
7612 // FIXME: we should do this in the ideal world.
7613 iRegIdst tmp1;
7614 iRegIdst tmp2;
7615 addI_reg_reg(tmp1, src1, src2);
7616 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7617 addI_reg_reg(dst, tmp1, tmp2);
7618 %}
7619 %}
7620
7621 // Immediate Addition
7622 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7623 match(Set dst (AddI src1 src2));
7624 format %{ "ADDI $dst, $src1, $src2" %}
7625 size(4);
7626 ins_encode %{
7627 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7628 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7629 %}
7630 ins_pipe(pipe_class_default);
7631 %}
7632
7633 // Immediate Addition with 16-bit shifted operand
7634 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7635 match(Set dst (AddI src1 src2));
7636 format %{ "ADDIS $dst, $src1, $src2" %}
7637 size(4);
7638 ins_encode %{
7639 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7640 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7641 %}
7642 ins_pipe(pipe_class_default);
7643 %}
7644
7645 // Long Addition
7646 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7647 match(Set dst (AddL src1 src2));
7648 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7649 size(4);
7650 ins_encode %{
7651 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7652 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7653 %}
7654 ins_pipe(pipe_class_default);
7655 %}
7656
7657 // Expand does not work with above instruct. (??)
7658 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7659 // no match-rule
7660 effect(DEF dst, USE src1, USE src2);
7661 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7662 size(4);
7663 ins_encode %{
7664 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7665 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7666 %}
7667 ins_pipe(pipe_class_default);
7668 %}
7669
7670 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7671 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7672 ins_cost(DEFAULT_COST*3);
7673
7674 expand %{
7675 // FIXME: we should do this in the ideal world.
7676 iRegLdst tmp1;
7677 iRegLdst tmp2;
7678 addL_reg_reg(tmp1, src1, src2);
7679 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7680 addL_reg_reg(dst, tmp1, tmp2);
7681 %}
7682 %}
7683
7684 // AddL + ConvL2I.
7685 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7686 match(Set dst (ConvL2I (AddL src1 src2)));
7687
7688 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7689 size(4);
7690 ins_encode %{
7691 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7692 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7693 %}
7694 ins_pipe(pipe_class_default);
7695 %}
7696
7697 // No constant pool entries required.
7698 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7699 match(Set dst (AddL src1 src2));
7700
7701 format %{ "ADDI $dst, $src1, $src2" %}
7702 size(4);
7703 ins_encode %{
7704 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7705 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7706 %}
7707 ins_pipe(pipe_class_default);
7708 %}
7709
7710 // Long Immediate Addition with 16-bit shifted operand.
7711 // No constant pool entries required.
7712 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7713 match(Set dst (AddL src1 src2));
7714
7715 format %{ "ADDIS $dst, $src1, $src2" %}
7716 size(4);
7717 ins_encode %{
7718 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7719 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7720 %}
7721 ins_pipe(pipe_class_default);
7722 %}
7723
7724 // Pointer Register Addition
7725 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7726 match(Set dst (AddP src1 src2));
7727 format %{ "ADD $dst, $src1, $src2" %}
7728 size(4);
7729 ins_encode %{
7730 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7731 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7732 %}
7733 ins_pipe(pipe_class_default);
7734 %}
7735
7736 // Pointer Immediate Addition
7737 // No constant pool entries required.
7738 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7739 match(Set dst (AddP src1 src2));
7740
7741 format %{ "ADDI $dst, $src1, $src2" %}
7742 size(4);
7743 ins_encode %{
7744 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7745 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7746 %}
7747 ins_pipe(pipe_class_default);
7748 %}
7749
7750 // Pointer Immediate Addition with 16-bit shifted operand.
7751 // No constant pool entries required.
7752 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7753 match(Set dst (AddP src1 src2));
7754
7755 format %{ "ADDIS $dst, $src1, $src2" %}
7756 size(4);
7757 ins_encode %{
7758 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7759 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7760 %}
7761 ins_pipe(pipe_class_default);
7762 %}
7763
7764 //---------------------
7765 // Subtraction Instructions
7766
7767 // Register Subtraction
7768 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7769 match(Set dst (SubI src1 src2));
7770 format %{ "SUBF $dst, $src2, $src1" %}
7771 size(4);
7772 ins_encode %{
7773 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7774 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7775 %}
7776 ins_pipe(pipe_class_default);
7777 %}
7778
7779 // Immediate Subtraction
7780 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7781 // so this rule seems to be unused.
7782 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7783 match(Set dst (SubI src1 src2));
7784 format %{ "SUBI $dst, $src1, $src2" %}
7785 size(4);
7786 ins_encode %{
7787 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7788 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7789 %}
7790 ins_pipe(pipe_class_default);
7791 %}
7792
7793 // SubI from constant (using subfic).
7794 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7795 match(Set dst (SubI src1 src2));
7796 format %{ "SUBI $dst, $src1, $src2" %}
7797
7798 size(4);
7799 ins_encode %{
7800 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7801 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7802 %}
7803 ins_pipe(pipe_class_default);
7804 %}
7805
7806 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7807 // positive integers and 0xF...F for negative ones.
7808 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7809 // no match-rule, false predicate
7810 effect(DEF dst, USE src);
7811 predicate(false);
7812
7813 format %{ "SRAWI $dst, $src, #31" %}
7814 size(4);
7815 ins_encode %{
7816 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7817 __ srawi($dst$$Register, $src$$Register, 0x1f);
7818 %}
7819 ins_pipe(pipe_class_default);
7820 %}
7821
7822 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7823 match(Set dst (AbsI src));
7824 ins_cost(DEFAULT_COST*3);
7825
7826 expand %{
7827 iRegIdst tmp1;
7828 iRegIdst tmp2;
7829 signmask32I_regI(tmp1, src);
7830 xorI_reg_reg(tmp2, tmp1, src);
7831 subI_reg_reg(dst, tmp2, tmp1);
7832 %}
7833 %}
7834
7835 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7836 match(Set dst (SubI zero src2));
7837 format %{ "NEG $dst, $src2" %}
7838 size(4);
7839 ins_encode %{
7840 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7841 __ neg($dst$$Register, $src2$$Register);
7842 %}
7843 ins_pipe(pipe_class_default);
7844 %}
7845
7846 // Long subtraction
7847 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7848 match(Set dst (SubL src1 src2));
7849 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7850 size(4);
7851 ins_encode %{
7852 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7853 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7854 %}
7855 ins_pipe(pipe_class_default);
7856 %}
7857
7858 // SubL + convL2I.
7859 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7860 match(Set dst (ConvL2I (SubL src1 src2)));
7861
7862 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7863 size(4);
7864 ins_encode %{
7865 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7866 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7867 %}
7868 ins_pipe(pipe_class_default);
7869 %}
7870
7871 // Immediate Subtraction
7872 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7873 // so this rule seems to be unused.
7874 // No constant pool entries required.
7875 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7876 match(Set dst (SubL src1 src2));
7877
7878 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7879 size(4);
7880 ins_encode %{
7881 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7882 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7883 %}
7884 ins_pipe(pipe_class_default);
7885 %}
7886
7887 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7888 // positive longs and 0xF...F for negative ones.
7889 instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{
7890 // no match-rule, false predicate
7891 effect(DEF dst, USE src);
7892 predicate(false);
7893
7894 format %{ "SRADI $dst, $src, #63" %}
7895 size(4);
7896 ins_encode %{
7897 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7898 __ sradi($dst$$Register, $src$$Register, 0x3f);
7899 %}
7900 ins_pipe(pipe_class_default);
7901 %}
7902
7903 // Long negation
7904 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7905 match(Set dst (SubL zero src2));
7906 format %{ "NEG $dst, $src2 \t// long" %}
7907 size(4);
7908 ins_encode %{
7909 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7910 __ neg($dst$$Register, $src2$$Register);
7911 %}
7912 ins_pipe(pipe_class_default);
7913 %}
7914
7915 // NegL + ConvL2I.
7916 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7917 match(Set dst (ConvL2I (SubL zero src2)));
7918
7919 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7920 size(4);
7921 ins_encode %{
7922 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7923 __ neg($dst$$Register, $src2$$Register);
7924 %}
7925 ins_pipe(pipe_class_default);
7926 %}
7927
7928 // Multiplication Instructions
7929 // Integer Multiplication
7930
7931 // Register Multiplication
7932 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7933 match(Set dst (MulI src1 src2));
7934 ins_cost(DEFAULT_COST);
7935
7936 format %{ "MULLW $dst, $src1, $src2" %}
7937 size(4);
7938 ins_encode %{
7939 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
7940 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
7941 %}
7942 ins_pipe(pipe_class_default);
7943 %}
7944
7945 // Immediate Multiplication
7946 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7947 match(Set dst (MulI src1 src2));
7948 ins_cost(DEFAULT_COST);
7949
7950 format %{ "MULLI $dst, $src1, $src2" %}
7951 size(4);
7952 ins_encode %{
7953 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
7954 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
7955 %}
7956 ins_pipe(pipe_class_default);
7957 %}
7958
7959 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7960 match(Set dst (MulL src1 src2));
7961 ins_cost(DEFAULT_COST);
7962
7963 format %{ "MULLD $dst $src1, $src2 \t// long" %}
7964 size(4);
7965 ins_encode %{
7966 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
7967 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
7968 %}
7969 ins_pipe(pipe_class_default);
7970 %}
7971
7972 // Multiply high for optimized long division by constant.
7973 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7974 match(Set dst (MulHiL src1 src2));
7975 ins_cost(DEFAULT_COST);
7976
7977 format %{ "MULHD $dst $src1, $src2 \t// long" %}
7978 size(4);
7979 ins_encode %{
7980 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
7981 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
7982 %}
7983 ins_pipe(pipe_class_default);
7984 %}
7985
7986 // Immediate Multiplication
7987 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7988 match(Set dst (MulL src1 src2));
7989 ins_cost(DEFAULT_COST);
7990
7991 format %{ "MULLI $dst, $src1, $src2" %}
7992 size(4);
7993 ins_encode %{
7994 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
7995 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
7996 %}
7997 ins_pipe(pipe_class_default);
7998 %}
7999
8000 // Integer Division with Immediate -1: Negate.
8001 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8002 match(Set dst (DivI src1 src2));
8003 ins_cost(DEFAULT_COST);
8004
8005 format %{ "NEG $dst, $src1 \t// /-1" %}
8006 size(4);
8007 ins_encode %{
8008 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8009 __ neg($dst$$Register, $src1$$Register);
8010 %}
8011 ins_pipe(pipe_class_default);
8012 %}
8013
8014 // Integer Division with constant, but not -1.
8015 // We should be able to improve this by checking the type of src2.
8016 // It might well be that src2 is known to be positive.
8017 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8018 match(Set dst (DivI src1 src2));
8019 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8020 ins_cost(2*DEFAULT_COST);
8021
8022 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8023 size(4);
8024 ins_encode %{
8025 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8026 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8027 %}
8028 ins_pipe(pipe_class_default);
8029 %}
8030
8031 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8032 effect(USE_DEF dst, USE src1, USE crx);
8033 predicate(false);
8034
8035 ins_variable_size_depending_on_alignment(true);
8036
8037 format %{ "CMOVE $dst, neg($src1), $crx" %}
8038 // Worst case is branch + move + stop, no stop without scheduler.
8039 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8040 ins_encode %{
8041 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8042 Label done;
8043 __ bne($crx$$CondRegister, done);
8044 __ neg($dst$$Register, $src1$$Register);
8045 // TODO PPC port __ endgroup_if_needed(_size == 12);
8046 __ bind(done);
8047 %}
8048 ins_pipe(pipe_class_default);
8049 %}
8050
8051 // Integer Division with Registers not containing constants.
8052 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8053 match(Set dst (DivI src1 src2));
8054 ins_cost(10*DEFAULT_COST);
8055
8056 expand %{
8057 immI16 imm %{ (int)-1 %}
8058 flagsReg tmp1;
8059 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8060 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8061 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8062 %}
8063 %}
8064
8065 // Long Division with Immediate -1: Negate.
8066 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8067 match(Set dst (DivL src1 src2));
8068 ins_cost(DEFAULT_COST);
8069
8070 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8071 size(4);
8072 ins_encode %{
8073 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8074 __ neg($dst$$Register, $src1$$Register);
8075 %}
8076 ins_pipe(pipe_class_default);
8077 %}
8078
8079 // Long Division with constant, but not -1.
8080 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8081 match(Set dst (DivL src1 src2));
8082 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8083 ins_cost(2*DEFAULT_COST);
8084
8085 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8086 size(4);
8087 ins_encode %{
8088 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8089 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8090 %}
8091 ins_pipe(pipe_class_default);
8092 %}
8093
8094 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8095 effect(USE_DEF dst, USE src1, USE crx);
8096 predicate(false);
8097
8098 ins_variable_size_depending_on_alignment(true);
8099
8100 format %{ "CMOVE $dst, neg($src1), $crx" %}
8101 // Worst case is branch + move + stop, no stop without scheduler.
8102 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8103 ins_encode %{
8104 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8105 Label done;
8106 __ bne($crx$$CondRegister, done);
8107 __ neg($dst$$Register, $src1$$Register);
8108 // TODO PPC port __ endgroup_if_needed(_size == 12);
8109 __ bind(done);
8110 %}
8111 ins_pipe(pipe_class_default);
8112 %}
8113
8114 // Long Division with Registers not containing constants.
8115 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8116 match(Set dst (DivL src1 src2));
8117 ins_cost(10*DEFAULT_COST);
8118
8119 expand %{
8120 immL16 imm %{ (int)-1 %}
8121 flagsReg tmp1;
8122 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8123 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8124 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8125 %}
8126 %}
8127
8128 // Integer Remainder with registers.
8129 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8130 match(Set dst (ModI src1 src2));
8131 ins_cost(10*DEFAULT_COST);
8132
8133 expand %{
8134 immI16 imm %{ (int)-1 %}
8135 flagsReg tmp1;
8136 iRegIdst tmp2;
8137 iRegIdst tmp3;
8138 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8139 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8140 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8141 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8142 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8143 %}
8144 %}
8145
8146 // Long Remainder with registers
8147 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8148 match(Set dst (ModL src1 src2));
8149 ins_cost(10*DEFAULT_COST);
8150
8151 expand %{
8152 immL16 imm %{ (int)-1 %}
8153 flagsReg tmp1;
8154 iRegLdst tmp2;
8155 iRegLdst tmp3;
8156 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8157 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8158 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8159 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8160 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8161 %}
8162 %}
8163
8164 // Integer Shift Instructions
8165
8166 // Register Shift Left
8167
8168 // Clear all but the lowest #mask bits.
8169 // Used to normalize shift amounts in registers.
8170 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8171 // no match-rule, false predicate
8172 effect(DEF dst, USE src, USE mask);
8173 predicate(false);
8174
8175 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8176 size(4);
8177 ins_encode %{
8178 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8179 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8180 %}
8181 ins_pipe(pipe_class_default);
8182 %}
8183
8184 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8185 // no match-rule, false predicate
8186 effect(DEF dst, USE src1, USE src2);
8187 predicate(false);
8188
8189 format %{ "SLW $dst, $src1, $src2" %}
8190 size(4);
8191 ins_encode %{
8192 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8193 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8194 %}
8195 ins_pipe(pipe_class_default);
8196 %}
8197
8198 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8199 match(Set dst (LShiftI src1 src2));
8200 ins_cost(DEFAULT_COST*2);
8201 expand %{
8202 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8203 iRegIdst tmpI;
8204 maskI_reg_imm(tmpI, src2, mask);
8205 lShiftI_reg_reg(dst, src1, tmpI);
8206 %}
8207 %}
8208
8209 // Register Shift Left Immediate
8210 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8211 match(Set dst (LShiftI src1 src2));
8212
8213 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8214 size(4);
8215 ins_encode %{
8216 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8217 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8218 %}
8219 ins_pipe(pipe_class_default);
8220 %}
8221
8222 // AndI with negpow2-constant + LShiftI
8223 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8224 match(Set dst (LShiftI (AndI src1 src2) src3));
8225 predicate(UseRotateAndMaskInstructionsPPC64);
8226
8227 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8228 size(4);
8229 ins_encode %{
8230 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8231 long src2 = $src2$$constant;
8232 long src3 = $src3$$constant;
8233 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8234 if (maskbits >= 32) {
8235 __ li($dst$$Register, 0); // addi
8236 } else {
8237 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8238 }
8239 %}
8240 ins_pipe(pipe_class_default);
8241 %}
8242
8243 // RShiftI + AndI with negpow2-constant + LShiftI
8244 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8245 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8246 predicate(UseRotateAndMaskInstructionsPPC64);
8247
8248 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8249 size(4);
8250 ins_encode %{
8251 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8252 long src2 = $src2$$constant;
8253 long src3 = $src3$$constant;
8254 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8255 if (maskbits >= 32) {
8256 __ li($dst$$Register, 0); // addi
8257 } else {
8258 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8259 }
8260 %}
8261 ins_pipe(pipe_class_default);
8262 %}
8263
8264 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8265 // no match-rule, false predicate
8266 effect(DEF dst, USE src1, USE src2);
8267 predicate(false);
8268
8269 format %{ "SLD $dst, $src1, $src2" %}
8270 size(4);
8271 ins_encode %{
8272 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8273 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8274 %}
8275 ins_pipe(pipe_class_default);
8276 %}
8277
8278 // Register Shift Left
8279 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8280 match(Set dst (LShiftL src1 src2));
8281 ins_cost(DEFAULT_COST*2);
8282 expand %{
8283 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8284 iRegIdst tmpI;
8285 maskI_reg_imm(tmpI, src2, mask);
8286 lShiftL_regL_regI(dst, src1, tmpI);
8287 %}
8288 %}
8289
8290 // Register Shift Left Immediate
8291 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8292 match(Set dst (LShiftL src1 src2));
8293 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8294 size(4);
8295 ins_encode %{
8296 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8297 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8298 %}
8299 ins_pipe(pipe_class_default);
8300 %}
8301
8302 // If we shift more than 32 bits, we need not convert I2L.
8303 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8304 match(Set dst (LShiftL (ConvI2L src1) src2));
8305 ins_cost(DEFAULT_COST);
8306
8307 size(4);
8308 format %{ "SLDI $dst, i2l($src1), $src2" %}
8309 ins_encode %{
8310 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8311 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8312 %}
8313 ins_pipe(pipe_class_default);
8314 %}
8315
8316 // Shift a postivie int to the left.
8317 // Clrlsldi clears the upper 32 bits and shifts.
8318 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8319 match(Set dst (LShiftL (ConvI2L src1) src2));
8320 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8321
8322 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8323 size(4);
8324 ins_encode %{
8325 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8326 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8327 %}
8328 ins_pipe(pipe_class_default);
8329 %}
8330
8331 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8332 // no match-rule, false predicate
8333 effect(DEF dst, USE src1, USE src2);
8334 predicate(false);
8335
8336 format %{ "SRAW $dst, $src1, $src2" %}
8337 size(4);
8338 ins_encode %{
8339 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8340 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8341 %}
8342 ins_pipe(pipe_class_default);
8343 %}
8344
8345 // Register Arithmetic Shift Right
8346 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8347 match(Set dst (RShiftI src1 src2));
8348 ins_cost(DEFAULT_COST*2);
8349 expand %{
8350 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8351 iRegIdst tmpI;
8352 maskI_reg_imm(tmpI, src2, mask);
8353 arShiftI_reg_reg(dst, src1, tmpI);
8354 %}
8355 %}
8356
8357 // Register Arithmetic Shift Right Immediate
8358 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8359 match(Set dst (RShiftI src1 src2));
8360
8361 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8362 size(4);
8363 ins_encode %{
8364 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8365 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8366 %}
8367 ins_pipe(pipe_class_default);
8368 %}
8369
8370 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8371 // no match-rule, false predicate
8372 effect(DEF dst, USE src1, USE src2);
8373 predicate(false);
8374
8375 format %{ "SRAD $dst, $src1, $src2" %}
8376 size(4);
8377 ins_encode %{
8378 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8379 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8380 %}
8381 ins_pipe(pipe_class_default);
8382 %}
8383
8384 // Register Shift Right Arithmetic Long
8385 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8386 match(Set dst (RShiftL src1 src2));
8387 ins_cost(DEFAULT_COST*2);
8388
8389 expand %{
8390 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8391 iRegIdst tmpI;
8392 maskI_reg_imm(tmpI, src2, mask);
8393 arShiftL_regL_regI(dst, src1, tmpI);
8394 %}
8395 %}
8396
8397 // Register Shift Right Immediate
8398 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8399 match(Set dst (RShiftL src1 src2));
8400
8401 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8402 size(4);
8403 ins_encode %{
8404 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8405 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8406 %}
8407 ins_pipe(pipe_class_default);
8408 %}
8409
8410 // RShiftL + ConvL2I
8411 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8412 match(Set dst (ConvL2I (RShiftL src1 src2)));
8413
8414 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8415 size(4);
8416 ins_encode %{
8417 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8418 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8419 %}
8420 ins_pipe(pipe_class_default);
8421 %}
8422
8423 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8424 // no match-rule, false predicate
8425 effect(DEF dst, USE src1, USE src2);
8426 predicate(false);
8427
8428 format %{ "SRW $dst, $src1, $src2" %}
8429 size(4);
8430 ins_encode %{
8431 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8432 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8433 %}
8434 ins_pipe(pipe_class_default);
8435 %}
8436
8437 // Register Shift Right
8438 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8439 match(Set dst (URShiftI src1 src2));
8440 ins_cost(DEFAULT_COST*2);
8441
8442 expand %{
8443 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8444 iRegIdst tmpI;
8445 maskI_reg_imm(tmpI, src2, mask);
8446 urShiftI_reg_reg(dst, src1, tmpI);
8447 %}
8448 %}
8449
8450 // Register Shift Right Immediate
8451 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8452 match(Set dst (URShiftI src1 src2));
8453
8454 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8455 size(4);
8456 ins_encode %{
8457 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8458 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8459 %}
8460 ins_pipe(pipe_class_default);
8461 %}
8462
8463 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8464 // no match-rule, false predicate
8465 effect(DEF dst, USE src1, USE src2);
8466 predicate(false);
8467
8468 format %{ "SRD $dst, $src1, $src2" %}
8469 size(4);
8470 ins_encode %{
8471 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8472 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8473 %}
8474 ins_pipe(pipe_class_default);
8475 %}
8476
8477 // Register Shift Right
8478 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8479 match(Set dst (URShiftL src1 src2));
8480 ins_cost(DEFAULT_COST*2);
8481
8482 expand %{
8483 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8484 iRegIdst tmpI;
8485 maskI_reg_imm(tmpI, src2, mask);
8486 urShiftL_regL_regI(dst, src1, tmpI);
8487 %}
8488 %}
8489
8490 // Register Shift Right Immediate
8491 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8492 match(Set dst (URShiftL src1 src2));
8493
8494 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8495 size(4);
8496 ins_encode %{
8497 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8498 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8499 %}
8500 ins_pipe(pipe_class_default);
8501 %}
8502
8503 // URShiftL + ConvL2I.
8504 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8505 match(Set dst (ConvL2I (URShiftL src1 src2)));
8506
8507 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8508 size(4);
8509 ins_encode %{
8510 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8511 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8512 %}
8513 ins_pipe(pipe_class_default);
8514 %}
8515
8516 // Register Shift Right Immediate with a CastP2X
8517 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8518 match(Set dst (URShiftL (CastP2X src1) src2));
8519
8520 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8521 size(4);
8522 ins_encode %{
8523 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8524 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8525 %}
8526 ins_pipe(pipe_class_default);
8527 %}
8528
8529 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8530 match(Set dst (ConvL2I (ConvI2L src)));
8531
8532 format %{ "EXTSW $dst, $src \t// int->int" %}
8533 size(4);
8534 ins_encode %{
8535 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8536 __ extsw($dst$$Register, $src$$Register);
8537 %}
8538 ins_pipe(pipe_class_default);
8539 %}
8540
8541 //----------Rotate Instructions------------------------------------------------
8542
8543 // Rotate Left by 8-bit immediate
8544 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8545 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8546 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8547
8548 format %{ "ROTLWI $dst, $src, $lshift" %}
8549 size(4);
8550 ins_encode %{
8551 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8552 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8553 %}
8554 ins_pipe(pipe_class_default);
8555 %}
8556
8557 // Rotate Right by 8-bit immediate
8558 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8559 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8560 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8561
8562 format %{ "ROTRWI $dst, $rshift" %}
8563 size(4);
8564 ins_encode %{
8565 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8566 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8567 %}
8568 ins_pipe(pipe_class_default);
8569 %}
8570
8571 //----------Floating Point Arithmetic Instructions-----------------------------
8572
8573 // Add float single precision
8574 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8575 match(Set dst (AddF src1 src2));
8576
8577 format %{ "FADDS $dst, $src1, $src2" %}
8578 size(4);
8579 ins_encode %{
8580 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8581 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8582 %}
8583 ins_pipe(pipe_class_default);
8584 %}
8585
8586 // Add float double precision
8587 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8588 match(Set dst (AddD src1 src2));
8589
8590 format %{ "FADD $dst, $src1, $src2" %}
8591 size(4);
8592 ins_encode %{
8593 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8594 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8595 %}
8596 ins_pipe(pipe_class_default);
8597 %}
8598
8599 // Sub float single precision
8600 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8601 match(Set dst (SubF src1 src2));
8602
8603 format %{ "FSUBS $dst, $src1, $src2" %}
8604 size(4);
8605 ins_encode %{
8606 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8607 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8608 %}
8609 ins_pipe(pipe_class_default);
8610 %}
8611
8612 // Sub float double precision
8613 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8614 match(Set dst (SubD src1 src2));
8615 format %{ "FSUB $dst, $src1, $src2" %}
8616 size(4);
8617 ins_encode %{
8618 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8619 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8620 %}
8621 ins_pipe(pipe_class_default);
8622 %}
8623
8624 // Mul float single precision
8625 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8626 match(Set dst (MulF src1 src2));
8627 format %{ "FMULS $dst, $src1, $src2" %}
8628 size(4);
8629 ins_encode %{
8630 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8631 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8632 %}
8633 ins_pipe(pipe_class_default);
8634 %}
8635
8636 // Mul float double precision
8637 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8638 match(Set dst (MulD src1 src2));
8639 format %{ "FMUL $dst, $src1, $src2" %}
8640 size(4);
8641 ins_encode %{
8642 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8643 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8644 %}
8645 ins_pipe(pipe_class_default);
8646 %}
8647
8648 // Div float single precision
8649 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8650 match(Set dst (DivF src1 src2));
8651 format %{ "FDIVS $dst, $src1, $src2" %}
8652 size(4);
8653 ins_encode %{
8654 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8655 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8656 %}
8657 ins_pipe(pipe_class_default);
8658 %}
8659
8660 // Div float double precision
8661 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8662 match(Set dst (DivD src1 src2));
8663 format %{ "FDIV $dst, $src1, $src2" %}
8664 size(4);
8665 ins_encode %{
8666 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8667 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8668 %}
8669 ins_pipe(pipe_class_default);
8670 %}
8671
8672 // Absolute float single precision
8673 instruct absF_reg(regF dst, regF src) %{
8674 match(Set dst (AbsF src));
8675 format %{ "FABS $dst, $src \t// float" %}
8676 size(4);
8677 ins_encode %{
8678 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8679 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8680 %}
8681 ins_pipe(pipe_class_default);
8682 %}
8683
8684 // Absolute float double precision
8685 instruct absD_reg(regD dst, regD src) %{
8686 match(Set dst (AbsD src));
8687 format %{ "FABS $dst, $src \t// double" %}
8688 size(4);
8689 ins_encode %{
8690 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8691 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8692 %}
8693 ins_pipe(pipe_class_default);
8694 %}
8695
8696 instruct negF_reg(regF dst, regF src) %{
8697 match(Set dst (NegF src));
8698 format %{ "FNEG $dst, $src \t// float" %}
8699 size(4);
8700 ins_encode %{
8701 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8702 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8703 %}
8704 ins_pipe(pipe_class_default);
8705 %}
8706
8707 instruct negD_reg(regD dst, regD src) %{
8708 match(Set dst (NegD src));
8709 format %{ "FNEG $dst, $src \t// double" %}
8710 size(4);
8711 ins_encode %{
8712 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8713 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8714 %}
8715 ins_pipe(pipe_class_default);
8716 %}
8717
8718 // AbsF + NegF.
8719 instruct negF_absF_reg(regF dst, regF src) %{
8720 match(Set dst (NegF (AbsF src)));
8721 format %{ "FNABS $dst, $src \t// float" %}
8722 size(4);
8723 ins_encode %{
8724 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8725 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8726 %}
8727 ins_pipe(pipe_class_default);
8728 %}
8729
8730 // AbsD + NegD.
8731 instruct negD_absD_reg(regD dst, regD src) %{
8732 match(Set dst (NegD (AbsD src)));
8733 format %{ "FNABS $dst, $src \t// double" %}
8734 size(4);
8735 ins_encode %{
8736 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8737 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8738 %}
8739 ins_pipe(pipe_class_default);
8740 %}
8741
8742 // VM_Version::has_fsqrt() decides if this node will be used.
8743 // Sqrt float double precision
8744 instruct sqrtD_reg(regD dst, regD src) %{
8745 match(Set dst (SqrtD src));
8746 format %{ "FSQRT $dst, $src" %}
8747 size(4);
8748 ins_encode %{
8749 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8750 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8751 %}
8752 ins_pipe(pipe_class_default);
8753 %}
8754
8755 // Single-precision sqrt.
8756 instruct sqrtF_reg(regF dst, regF src) %{
8757 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8758 ins_cost(DEFAULT_COST);
8759
8760 format %{ "FSQRTS $dst, $src" %}
8761 size(4);
8762 ins_encode %{
8763 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8764 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8765 %}
8766 ins_pipe(pipe_class_default);
8767 %}
8768
8769 instruct roundDouble_nop(regD dst) %{
8770 match(Set dst (RoundDouble dst));
8771 ins_cost(0);
8772
8773 format %{ " -- \t// RoundDouble not needed - empty" %}
8774 size(0);
8775 // PPC results are already "rounded" (i.e., normal-format IEEE).
8776 ins_encode( /*empty*/ );
8777 ins_pipe(pipe_class_default);
8778 %}
8779
8780 instruct roundFloat_nop(regF dst) %{
8781 match(Set dst (RoundFloat dst));
8782 ins_cost(0);
8783
8784 format %{ " -- \t// RoundFloat not needed - empty" %}
8785 size(0);
8786 // PPC results are already "rounded" (i.e., normal-format IEEE).
8787 ins_encode( /*empty*/ );
8788 ins_pipe(pipe_class_default);
8789 %}
8790
8791 //----------Logical Instructions-----------------------------------------------
8792
8793 // And Instructions
8794
8795 // Register And
8796 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8797 match(Set dst (AndI src1 src2));
8798 format %{ "AND $dst, $src1, $src2" %}
8799 size(4);
8800 ins_encode %{
8801 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8802 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8803 %}
8804 ins_pipe(pipe_class_default);
8805 %}
8806
8807 // Immediate And
8808 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8809 match(Set dst (AndI src1 src2));
8810 effect(KILL cr0);
8811
8812 format %{ "ANDI $dst, $src1, $src2" %}
8813 size(4);
8814 ins_encode %{
8815 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8816 // FIXME: avoid andi_ ?
8817 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8818 %}
8819 ins_pipe(pipe_class_default);
8820 %}
8821
8822 // Immediate And where the immediate is a negative power of 2.
8823 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8824 match(Set dst (AndI src1 src2));
8825 format %{ "ANDWI $dst, $src1, $src2" %}
8826 size(4);
8827 ins_encode %{
8828 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8829 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8830 %}
8831 ins_pipe(pipe_class_default);
8832 %}
8833
8834 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8835 match(Set dst (AndI src1 src2));
8836 format %{ "ANDWI $dst, $src1, $src2" %}
8837 size(4);
8838 ins_encode %{
8839 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8840 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8841 %}
8842 ins_pipe(pipe_class_default);
8843 %}
8844
8845 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8846 match(Set dst (AndI src1 src2));
8847 predicate(UseRotateAndMaskInstructionsPPC64);
8848 format %{ "ANDWI $dst, $src1, $src2" %}
8849 size(4);
8850 ins_encode %{
8851 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8852 __ rlwinm($dst$$Register, $src1$$Register, 0,
8853 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8854 %}
8855 ins_pipe(pipe_class_default);
8856 %}
8857
8858 // Register And Long
8859 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8860 match(Set dst (AndL src1 src2));
8861 ins_cost(DEFAULT_COST);
8862
8863 format %{ "AND $dst, $src1, $src2 \t// long" %}
8864 size(4);
8865 ins_encode %{
8866 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8867 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8868 %}
8869 ins_pipe(pipe_class_default);
8870 %}
8871
8872 // Immediate And long
8873 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8874 match(Set dst (AndL src1 src2));
8875 effect(KILL cr0);
8876 ins_cost(DEFAULT_COST);
8877
8878 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8879 size(4);
8880 ins_encode %{
8881 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8882 // FIXME: avoid andi_ ?
8883 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8884 %}
8885 ins_pipe(pipe_class_default);
8886 %}
8887
8888 // Immediate And Long where the immediate is a negative power of 2.
8889 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8890 match(Set dst (AndL src1 src2));
8891 format %{ "ANDDI $dst, $src1, $src2" %}
8892 size(4);
8893 ins_encode %{
8894 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8895 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8896 %}
8897 ins_pipe(pipe_class_default);
8898 %}
8899
8900 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8901 match(Set dst (AndL src1 src2));
8902 format %{ "ANDDI $dst, $src1, $src2" %}
8903 size(4);
8904 ins_encode %{
8905 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8906 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8907 %}
8908 ins_pipe(pipe_class_default);
8909 %}
8910
8911 // AndL + ConvL2I.
8912 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8913 match(Set dst (ConvL2I (AndL src1 src2)));
8914 ins_cost(DEFAULT_COST);
8915
8916 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8917 size(4);
8918 ins_encode %{
8919 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8920 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8921 %}
8922 ins_pipe(pipe_class_default);
8923 %}
8924
8925 // Or Instructions
8926
8927 // Register Or
8928 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8929 match(Set dst (OrI src1 src2));
8930 format %{ "OR $dst, $src1, $src2" %}
8931 size(4);
8932 ins_encode %{
8933 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8934 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8935 %}
8936 ins_pipe(pipe_class_default);
8937 %}
8938
8939 // Expand does not work with above instruct. (??)
8940 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8941 // no match-rule
8942 effect(DEF dst, USE src1, USE src2);
8943 format %{ "OR $dst, $src1, $src2" %}
8944 size(4);
8945 ins_encode %{
8946 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8947 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8948 %}
8949 ins_pipe(pipe_class_default);
8950 %}
8951
8952 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
8953 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
8954 ins_cost(DEFAULT_COST*3);
8955
8956 expand %{
8957 // FIXME: we should do this in the ideal world.
8958 iRegIdst tmp1;
8959 iRegIdst tmp2;
8960 orI_reg_reg(tmp1, src1, src2);
8961 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
8962 orI_reg_reg(dst, tmp1, tmp2);
8963 %}
8964 %}
8965
8966 // Immediate Or
8967 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
8968 match(Set dst (OrI src1 src2));
8969 format %{ "ORI $dst, $src1, $src2" %}
8970 size(4);
8971 ins_encode %{
8972 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
8973 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
8974 %}
8975 ins_pipe(pipe_class_default);
8976 %}
8977
8978 // Register Or Long
8979 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8980 match(Set dst (OrL src1 src2));
8981 ins_cost(DEFAULT_COST);
8982
8983 size(4);
8984 format %{ "OR $dst, $src1, $src2 \t// long" %}
8985 ins_encode %{
8986 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8987 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
8988 %}
8989 ins_pipe(pipe_class_default);
8990 %}
8991
8992 // OrL + ConvL2I.
8993 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
8994 match(Set dst (ConvL2I (OrL src1 src2)));
8995 ins_cost(DEFAULT_COST);
8996
8997 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
8998 size(4);
8999 ins_encode %{
9000 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9001 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9002 %}
9003 ins_pipe(pipe_class_default);
9004 %}
9005
9006 // Immediate Or long
9007 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9008 match(Set dst (OrL src1 con));
9009 ins_cost(DEFAULT_COST);
9010
9011 format %{ "ORI $dst, $src1, $con \t// long" %}
9012 size(4);
9013 ins_encode %{
9014 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9015 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9016 %}
9017 ins_pipe(pipe_class_default);
9018 %}
9019
9020 // Xor Instructions
9021
9022 // Register Xor
9023 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9024 match(Set dst (XorI src1 src2));
9025 format %{ "XOR $dst, $src1, $src2" %}
9026 size(4);
9027 ins_encode %{
9028 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9029 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9030 %}
9031 ins_pipe(pipe_class_default);
9032 %}
9033
9034 // Expand does not work with above instruct. (??)
9035 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9036 // no match-rule
9037 effect(DEF dst, USE src1, USE src2);
9038 format %{ "XOR $dst, $src1, $src2" %}
9039 size(4);
9040 ins_encode %{
9041 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9042 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9043 %}
9044 ins_pipe(pipe_class_default);
9045 %}
9046
9047 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9048 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9049 ins_cost(DEFAULT_COST*3);
9050
9051 expand %{
9052 // FIXME: we should do this in the ideal world.
9053 iRegIdst tmp1;
9054 iRegIdst tmp2;
9055 xorI_reg_reg(tmp1, src1, src2);
9056 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9057 xorI_reg_reg(dst, tmp1, tmp2);
9058 %}
9059 %}
9060
9061 // Immediate Xor
9062 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9063 match(Set dst (XorI src1 src2));
9064 format %{ "XORI $dst, $src1, $src2" %}
9065 size(4);
9066 ins_encode %{
9067 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9068 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9069 %}
9070 ins_pipe(pipe_class_default);
9071 %}
9072
9073 // Register Xor Long
9074 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9075 match(Set dst (XorL src1 src2));
9076 ins_cost(DEFAULT_COST);
9077
9078 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9079 size(4);
9080 ins_encode %{
9081 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9082 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9083 %}
9084 ins_pipe(pipe_class_default);
9085 %}
9086
9087 // XorL + ConvL2I.
9088 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9089 match(Set dst (ConvL2I (XorL src1 src2)));
9090 ins_cost(DEFAULT_COST);
9091
9092 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9093 size(4);
9094 ins_encode %{
9095 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9096 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9097 %}
9098 ins_pipe(pipe_class_default);
9099 %}
9100
9101 // Immediate Xor Long
9102 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9103 match(Set dst (XorL src1 src2));
9104 ins_cost(DEFAULT_COST);
9105
9106 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9107 size(4);
9108 ins_encode %{
9109 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9110 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9111 %}
9112 ins_pipe(pipe_class_default);
9113 %}
9114
9115 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9116 match(Set dst (XorI src1 src2));
9117 ins_cost(DEFAULT_COST);
9118
9119 format %{ "NOT $dst, $src1 ($src2)" %}
9120 size(4);
9121 ins_encode %{
9122 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9123 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9124 %}
9125 ins_pipe(pipe_class_default);
9126 %}
9127
9128 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9129 match(Set dst (XorL src1 src2));
9130 ins_cost(DEFAULT_COST);
9131
9132 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9133 size(4);
9134 ins_encode %{
9135 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9136 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9137 %}
9138 ins_pipe(pipe_class_default);
9139 %}
9140
9141 // And-complement
9142 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9143 match(Set dst (AndI (XorI src1 src2) src3));
9144 ins_cost(DEFAULT_COST);
9145
9146 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9147 size(4);
9148 ins_encode( enc_andc(dst, src3, src1) );
9149 ins_pipe(pipe_class_default);
9150 %}
9151
9152 // And-complement
9153 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9154 // no match-rule, false predicate
9155 effect(DEF dst, USE src1, USE src2);
9156 predicate(false);
9157
9158 format %{ "ANDC $dst, $src1, $src2" %}
9159 size(4);
9160 ins_encode %{
9161 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9162 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9163 %}
9164 ins_pipe(pipe_class_default);
9165 %}
9166
9167 //----------Moves between int/long and float/double----------------------------
9168 //
9169 // The following rules move values from int/long registers/stack-locations
9170 // to float/double registers/stack-locations and vice versa, without doing any
9171 // conversions. These rules are used to implement the bit-conversion methods
9172 // of java.lang.Float etc., e.g.
9173 // int floatToIntBits(float value)
9174 // float intBitsToFloat(int bits)
9175 //
9176 // Notes on the implementation on ppc64:
9177 // We only provide rules which move between a register and a stack-location,
9178 // because we always have to go through memory when moving between a float
9179 // register and an integer register.
9180
9181 //---------- Chain stack slots between similar types --------
9182
9183 // These are needed so that the rules below can match.
9184
9185 // Load integer from stack slot
9186 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9187 match(Set dst src);
9188 ins_cost(MEMORY_REF_COST);
9189
9190 format %{ "LWZ $dst, $src" %}
9191 size(4);
9192 ins_encode( enc_lwz(dst, src) );
9193 ins_pipe(pipe_class_memory);
9194 %}
9195
9196 // Store integer to stack slot
9197 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9198 match(Set dst src);
9199 ins_cost(MEMORY_REF_COST);
9200
9201 format %{ "STW $src, $dst \t// stk" %}
9202 size(4);
9203 ins_encode( enc_stw(src, dst) ); // rs=rt
9204 ins_pipe(pipe_class_memory);
9205 %}
9206
9207 // Load long from stack slot
9208 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9209 match(Set dst src);
9210 ins_cost(MEMORY_REF_COST);
9211
9212 format %{ "LD $dst, $src \t// long" %}
9213 size(4);
9214 ins_encode( enc_ld(dst, src) );
9215 ins_pipe(pipe_class_memory);
9216 %}
9217
9218 // Store long to stack slot
9219 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9220 match(Set dst src);
9221 ins_cost(MEMORY_REF_COST);
9222
9223 format %{ "STD $src, $dst \t// long" %}
9224 size(4);
9225 ins_encode( enc_std(src, dst) ); // rs=rt
9226 ins_pipe(pipe_class_memory);
9227 %}
9228
9229 //----------Moves between int and float
9230
9231 // Move float value from float stack-location to integer register.
9232 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9233 match(Set dst (MoveF2I src));
9234 ins_cost(MEMORY_REF_COST);
9235
9236 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9237 size(4);
9238 ins_encode( enc_lwz(dst, src) );
9239 ins_pipe(pipe_class_memory);
9240 %}
9241
9242 // Move float value from float register to integer stack-location.
9243 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9244 match(Set dst (MoveF2I src));
9245 ins_cost(MEMORY_REF_COST);
9246
9247 format %{ "STFS $src, $dst \t// MoveF2I" %}
9248 size(4);
9249 ins_encode( enc_stfs(src, dst) );
9250 ins_pipe(pipe_class_memory);
9251 %}
9252
9253 // Move integer value from integer stack-location to float register.
9254 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9255 match(Set dst (MoveI2F src));
9256 ins_cost(MEMORY_REF_COST);
9257
9258 format %{ "LFS $dst, $src \t// MoveI2F" %}
9259 size(4);
9260 ins_encode %{
9261 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9262 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9263 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9264 %}
9265 ins_pipe(pipe_class_memory);
9266 %}
9267
9268 // Move integer value from integer register to float stack-location.
9269 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9270 match(Set dst (MoveI2F src));
9271 ins_cost(MEMORY_REF_COST);
9272
9273 format %{ "STW $src, $dst \t// MoveI2F" %}
9274 size(4);
9275 ins_encode( enc_stw(src, dst) );
9276 ins_pipe(pipe_class_memory);
9277 %}
9278
9279 //----------Moves between long and float
9280
9281 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9282 // no match-rule, false predicate
9283 effect(DEF dst, USE src);
9284 predicate(false);
9285
9286 format %{ "storeD $src, $dst \t// STACK" %}
9287 size(4);
9288 ins_encode( enc_stfd(src, dst) );
9289 ins_pipe(pipe_class_default);
9290 %}
9291
9292 //----------Moves between long and double
9293
9294 // Move double value from double stack-location to long register.
9295 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9296 match(Set dst (MoveD2L src));
9297 ins_cost(MEMORY_REF_COST);
9298 size(4);
9299 format %{ "LD $dst, $src \t// MoveD2L" %}
9300 ins_encode( enc_ld(dst, src) );
9301 ins_pipe(pipe_class_memory);
9302 %}
9303
9304 // Move double value from double register to long stack-location.
9305 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9306 match(Set dst (MoveD2L src));
9307 effect(DEF dst, USE src);
9308 ins_cost(MEMORY_REF_COST);
9309
9310 format %{ "STFD $src, $dst \t// MoveD2L" %}
9311 size(4);
9312 ins_encode( enc_stfd(src, dst) );
9313 ins_pipe(pipe_class_memory);
9314 %}
9315
9316 // Move long value from long stack-location to double register.
9317 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9318 match(Set dst (MoveL2D src));
9319 ins_cost(MEMORY_REF_COST);
9320
9321 format %{ "LFD $dst, $src \t// MoveL2D" %}
9322 size(4);
9323 ins_encode( enc_lfd(dst, src) );
9324 ins_pipe(pipe_class_memory);
9325 %}
9326
9327 // Move long value from long register to double stack-location.
9328 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9329 match(Set dst (MoveL2D src));
9330 ins_cost(MEMORY_REF_COST);
9331
9332 format %{ "STD $src, $dst \t// MoveL2D" %}
9333 size(4);
9334 ins_encode( enc_std(src, dst) );
9335 ins_pipe(pipe_class_memory);
9336 %}
9337
9338 //----------Register Move Instructions-----------------------------------------
9339
9340 // Replicate for Superword
9341
9342 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9343 predicate(false);
9344 effect(DEF dst, USE src);
9345
9346 format %{ "MR $dst, $src \t// replicate " %}
9347 // variable size, 0 or 4.
9348 ins_encode %{
9349 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9350 __ mr_if_needed($dst$$Register, $src$$Register);
9351 %}
9352 ins_pipe(pipe_class_default);
9353 %}
9354
9355 //----------Cast instructions (Java-level type cast)---------------------------
9356
9357 // Cast Long to Pointer for unsafe natives.
9358 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9359 match(Set dst (CastX2P src));
9360
9361 format %{ "MR $dst, $src \t// Long->Ptr" %}
9362 // variable size, 0 or 4.
9363 ins_encode %{
9364 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9365 __ mr_if_needed($dst$$Register, $src$$Register);
9366 %}
9367 ins_pipe(pipe_class_default);
9368 %}
9369
9370 // Cast Pointer to Long for unsafe natives.
9371 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9372 match(Set dst (CastP2X src));
9373
9374 format %{ "MR $dst, $src \t// Ptr->Long" %}
9375 // variable size, 0 or 4.
9376 ins_encode %{
9377 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9378 __ mr_if_needed($dst$$Register, $src$$Register);
9379 %}
9380 ins_pipe(pipe_class_default);
9381 %}
9382
9383 instruct castPP(iRegPdst dst) %{
9384 match(Set dst (CastPP dst));
9385 format %{ " -- \t// castPP of $dst" %}
9386 size(0);
9387 ins_encode( /*empty*/ );
9388 ins_pipe(pipe_class_default);
9389 %}
9390
9391 instruct castII(iRegIdst dst) %{
9392 match(Set dst (CastII dst));
9393 format %{ " -- \t// castII of $dst" %}
9394 size(0);
9395 ins_encode( /*empty*/ );
9396 ins_pipe(pipe_class_default);
9397 %}
9398
9399 instruct checkCastPP(iRegPdst dst) %{
9400 match(Set dst (CheckCastPP dst));
9401 format %{ " -- \t// checkcastPP of $dst" %}
9402 size(0);
9403 ins_encode( /*empty*/ );
9404 ins_pipe(pipe_class_default);
9405 %}
9406
9407 //----------Convert instructions-----------------------------------------------
9408
9409 // Convert to boolean.
9410
9411 // int_to_bool(src) : { 1 if src != 0
9412 // { 0 else
9413 //
9414 // strategy:
9415 // 1) Count leading zeros of 32 bit-value src,
9416 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9417 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9418 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9419
9420 // convI2Bool
9421 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9422 match(Set dst (Conv2B src));
9423 predicate(UseCountLeadingZerosInstructionsPPC64);
9424 ins_cost(DEFAULT_COST);
9425
9426 expand %{
9427 immI shiftAmount %{ 0x5 %}
9428 uimmI16 mask %{ 0x1 %}
9429 iRegIdst tmp1;
9430 iRegIdst tmp2;
9431 countLeadingZerosI(tmp1, src);
9432 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9433 xorI_reg_uimm16(dst, tmp2, mask);
9434 %}
9435 %}
9436
9437 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9438 match(Set dst (Conv2B src));
9439 effect(TEMP crx);
9440 predicate(!UseCountLeadingZerosInstructionsPPC64);
9441 ins_cost(DEFAULT_COST);
9442
9443 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9444 "LI $dst, #0\n\t"
9445 "BEQ $crx, done\n\t"
9446 "LI $dst, #1\n"
9447 "done:" %}
9448 size(16);
9449 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9450 ins_pipe(pipe_class_compare);
9451 %}
9452
9453 // ConvI2B + XorI
9454 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9455 match(Set dst (XorI (Conv2B src) mask));
9456 predicate(UseCountLeadingZerosInstructionsPPC64);
9457 ins_cost(DEFAULT_COST);
9458
9459 expand %{
9460 immI shiftAmount %{ 0x5 %}
9461 iRegIdst tmp1;
9462 countLeadingZerosI(tmp1, src);
9463 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9464 %}
9465 %}
9466
9467 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9468 match(Set dst (XorI (Conv2B src) mask));
9469 effect(TEMP crx);
9470 predicate(!UseCountLeadingZerosInstructionsPPC64);
9471 ins_cost(DEFAULT_COST);
9472
9473 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9474 "LI $dst, #1\n\t"
9475 "BEQ $crx, done\n\t"
9476 "LI $dst, #0\n"
9477 "done:" %}
9478 size(16);
9479 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9480 ins_pipe(pipe_class_compare);
9481 %}
9482
9483 // AndI 0b0..010..0 + ConvI2B
9484 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9485 match(Set dst (Conv2B (AndI src mask)));
9486 predicate(UseRotateAndMaskInstructionsPPC64);
9487 ins_cost(DEFAULT_COST);
9488
9489 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9490 size(4);
9491 ins_encode %{
9492 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9493 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9494 %}
9495 ins_pipe(pipe_class_default);
9496 %}
9497
9498 // Convert pointer to boolean.
9499 //
9500 // ptr_to_bool(src) : { 1 if src != 0
9501 // { 0 else
9502 //
9503 // strategy:
9504 // 1) Count leading zeros of 64 bit-value src,
9505 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9506 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9507 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9508
9509 // ConvP2B
9510 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9511 match(Set dst (Conv2B src));
9512 predicate(UseCountLeadingZerosInstructionsPPC64);
9513 ins_cost(DEFAULT_COST);
9514
9515 expand %{
9516 immI shiftAmount %{ 0x6 %}
9517 uimmI16 mask %{ 0x1 %}
9518 iRegIdst tmp1;
9519 iRegIdst tmp2;
9520 countLeadingZerosP(tmp1, src);
9521 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9522 xorI_reg_uimm16(dst, tmp2, mask);
9523 %}
9524 %}
9525
9526 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9527 match(Set dst (Conv2B src));
9528 effect(TEMP crx);
9529 predicate(!UseCountLeadingZerosInstructionsPPC64);
9530 ins_cost(DEFAULT_COST);
9531
9532 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9533 "LI $dst, #0\n\t"
9534 "BEQ $crx, done\n\t"
9535 "LI $dst, #1\n"
9536 "done:" %}
9537 size(16);
9538 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9539 ins_pipe(pipe_class_compare);
9540 %}
9541
9542 // ConvP2B + XorI
9543 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9544 match(Set dst (XorI (Conv2B src) mask));
9545 predicate(UseCountLeadingZerosInstructionsPPC64);
9546 ins_cost(DEFAULT_COST);
9547
9548 expand %{
9549 immI shiftAmount %{ 0x6 %}
9550 iRegIdst tmp1;
9551 countLeadingZerosP(tmp1, src);
9552 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9553 %}
9554 %}
9555
9556 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9557 match(Set dst (XorI (Conv2B src) mask));
9558 effect(TEMP crx);
9559 predicate(!UseCountLeadingZerosInstructionsPPC64);
9560 ins_cost(DEFAULT_COST);
9561
9562 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9563 "LI $dst, #1\n\t"
9564 "BEQ $crx, done\n\t"
9565 "LI $dst, #0\n"
9566 "done:" %}
9567 size(16);
9568 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9569 ins_pipe(pipe_class_compare);
9570 %}
9571
9572 // if src1 < src2, return -1 else return 0
9573 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9574 match(Set dst (CmpLTMask src1 src2));
9575 ins_cost(DEFAULT_COST*4);
9576
9577 expand %{
9578 iRegIdst src1s;
9579 iRegIdst src2s;
9580 iRegIdst diff;
9581 sxtI_reg(src1s, src1); // ensure proper sign extention
9582 sxtI_reg(src2s, src2); // ensure proper sign extention
9583 subI_reg_reg(diff, src1s, src2s);
9584 // Need to consider >=33 bit result, therefore we need signmaskL.
9585 signmask64I_regI(dst, diff);
9586 %}
9587 %}
9588
9589 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9590 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9591 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9592 size(4);
9593 ins_encode %{
9594 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9595 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9596 %}
9597 ins_pipe(pipe_class_default);
9598 %}
9599
9600 //----------Arithmetic Conversion Instructions---------------------------------
9601
9602 // Convert to Byte -- nop
9603 // Convert to Short -- nop
9604
9605 // Convert to Int
9606
9607 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9608 match(Set dst (RShiftI (LShiftI src amount) amount));
9609 format %{ "EXTSB $dst, $src \t// byte->int" %}
9610 size(4);
9611 ins_encode %{
9612 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9613 __ extsb($dst$$Register, $src$$Register);
9614 %}
9615 ins_pipe(pipe_class_default);
9616 %}
9617
9618 // LShiftI 16 + RShiftI 16 converts short to int.
9619 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9620 match(Set dst (RShiftI (LShiftI src amount) amount));
9621 format %{ "EXTSH $dst, $src \t// short->int" %}
9622 size(4);
9623 ins_encode %{
9624 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9625 __ extsh($dst$$Register, $src$$Register);
9626 %}
9627 ins_pipe(pipe_class_default);
9628 %}
9629
9630 // ConvL2I + ConvI2L: Sign extend int in long register.
9631 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9632 match(Set dst (ConvI2L (ConvL2I src)));
9633
9634 format %{ "EXTSW $dst, $src \t// long->long" %}
9635 size(4);
9636 ins_encode %{
9637 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9638 __ extsw($dst$$Register, $src$$Register);
9639 %}
9640 ins_pipe(pipe_class_default);
9641 %}
9642
9643 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9644 match(Set dst (ConvL2I src));
9645 format %{ "MR $dst, $src \t// long->int" %}
9646 // variable size, 0 or 4
9647 ins_encode %{
9648 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9649 __ mr_if_needed($dst$$Register, $src$$Register);
9650 %}
9651 ins_pipe(pipe_class_default);
9652 %}
9653
9654 instruct convD2IRaw_regD(regD dst, regD src) %{
9655 // no match-rule, false predicate
9656 effect(DEF dst, USE src);
9657 predicate(false);
9658
9659 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9660 size(4);
9661 ins_encode %{
9662 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9663 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9664 %}
9665 ins_pipe(pipe_class_default);
9666 %}
9667
9668 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9669 // no match-rule, false predicate
9670 effect(DEF dst, USE crx, USE src);
9671 predicate(false);
9672
9673 ins_variable_size_depending_on_alignment(true);
9674
9675 format %{ "cmovI $crx, $dst, $src" %}
9676 // Worst case is branch + move + stop, no stop without scheduler.
9677 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9678 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9679 ins_pipe(pipe_class_default);
9680 %}
9681
9682 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9683 // no match-rule, false predicate
9684 effect(DEF dst, USE crx, USE mem);
9685 predicate(false);
9686
9687 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9688 postalloc_expand %{
9689 //
9690 // replaces
9691 //
9692 // region dst crx mem
9693 // \ | | /
9694 // dst=cmovI_bso_stackSlotL_conLvalue0
9695 //
9696 // with
9697 //
9698 // region dst
9699 // \ /
9700 // dst=loadConI16(0)
9701 // |
9702 // ^ region dst crx mem
9703 // | \ | | /
9704 // dst=cmovI_bso_stackSlotL
9705 //
9706
9707 // Create new nodes.
9708 MachNode *m1 = new (C) loadConI16Node();
9709 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode();
9710
9711 // inputs for new nodes
9712 m1->add_req(n_region);
9713 m2->add_req(n_region, n_crx, n_mem);
9714
9715 // precedences for new nodes
9716 m2->add_prec(m1);
9717
9718 // operands for new nodes
9719 m1->_opnds[0] = op_dst;
9720 m1->_opnds[1] = new (C) immI16Oper(0);
9721
9722 m2->_opnds[0] = op_dst;
9723 m2->_opnds[1] = op_crx;
9724 m2->_opnds[2] = op_mem;
9725
9726 // registers for new nodes
9727 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9728 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9729
9730 // Insert new nodes.
9731 nodes->push(m1);
9732 nodes->push(m2);
9733 %}
9734 %}
9735
9736 // Double to Int conversion, NaN is mapped to 0.
9737 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9738 match(Set dst (ConvD2I src));
9739 ins_cost(DEFAULT_COST);
9740
9741 expand %{
9742 regD tmpD;
9743 stackSlotL tmpS;
9744 flagsReg crx;
9745 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9746 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9747 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9748 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9749 %}
9750 %}
9751
9752 instruct convF2IRaw_regF(regF dst, regF src) %{
9753 // no match-rule, false predicate
9754 effect(DEF dst, USE src);
9755 predicate(false);
9756
9757 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9758 size(4);
9759 ins_encode %{
9760 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9761 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9762 %}
9763 ins_pipe(pipe_class_default);
9764 %}
9765
9766 // Float to Int conversion, NaN is mapped to 0.
9767 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9768 match(Set dst (ConvF2I src));
9769 ins_cost(DEFAULT_COST);
9770
9771 expand %{
9772 regF tmpF;
9773 stackSlotL tmpS;
9774 flagsReg crx;
9775 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9776 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9777 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9778 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9779 %}
9780 %}
9781
9782 // Convert to Long
9783
9784 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9785 match(Set dst (ConvI2L src));
9786 format %{ "EXTSW $dst, $src \t// int->long" %}
9787 size(4);
9788 ins_encode %{
9789 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9790 __ extsw($dst$$Register, $src$$Register);
9791 %}
9792 ins_pipe(pipe_class_default);
9793 %}
9794
9795 // Zero-extend: convert unsigned int to long (convUI2L).
9796 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9797 match(Set dst (AndL (ConvI2L src) mask));
9798 ins_cost(DEFAULT_COST);
9799
9800 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9801 size(4);
9802 ins_encode %{
9803 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9804 __ clrldi($dst$$Register, $src$$Register, 32);
9805 %}
9806 ins_pipe(pipe_class_default);
9807 %}
9808
9809 // Zero-extend: convert unsigned int to long in long register.
9810 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9811 match(Set dst (AndL src mask));
9812 ins_cost(DEFAULT_COST);
9813
9814 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9815 size(4);
9816 ins_encode %{
9817 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9818 __ clrldi($dst$$Register, $src$$Register, 32);
9819 %}
9820 ins_pipe(pipe_class_default);
9821 %}
9822
9823 instruct convF2LRaw_regF(regF dst, regF src) %{
9824 // no match-rule, false predicate
9825 effect(DEF dst, USE src);
9826 predicate(false);
9827
9828 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9829 size(4);
9830 ins_encode %{
9831 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9832 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9833 %}
9834 ins_pipe(pipe_class_default);
9835 %}
9836
9837 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9838 // no match-rule, false predicate
9839 effect(DEF dst, USE crx, USE src);
9840 predicate(false);
9841
9842 ins_variable_size_depending_on_alignment(true);
9843
9844 format %{ "cmovL $crx, $dst, $src" %}
9845 // Worst case is branch + move + stop, no stop without scheduler.
9846 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9847 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9848 ins_pipe(pipe_class_default);
9849 %}
9850
9851 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9852 // no match-rule, false predicate
9853 effect(DEF dst, USE crx, USE mem);
9854 predicate(false);
9855
9856 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9857 postalloc_expand %{
9858 //
9859 // replaces
9860 //
9861 // region dst crx mem
9862 // \ | | /
9863 // dst=cmovL_bso_stackSlotL_conLvalue0
9864 //
9865 // with
9866 //
9867 // region dst
9868 // \ /
9869 // dst=loadConL16(0)
9870 // |
9871 // ^ region dst crx mem
9872 // | \ | | /
9873 // dst=cmovL_bso_stackSlotL
9874 //
9875
9876 // Create new nodes.
9877 MachNode *m1 = new (C) loadConL16Node();
9878 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode();
9879
9880 // inputs for new nodes
9881 m1->add_req(n_region);
9882 m2->add_req(n_region, n_crx, n_mem);
9883 m2->add_prec(m1);
9884
9885 // operands for new nodes
9886 m1->_opnds[0] = op_dst;
9887 m1->_opnds[1] = new (C) immL16Oper(0);
9888 m2->_opnds[0] = op_dst;
9889 m2->_opnds[1] = op_crx;
9890 m2->_opnds[2] = op_mem;
9891
9892 // registers for new nodes
9893 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9894 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9895
9896 // Insert new nodes.
9897 nodes->push(m1);
9898 nodes->push(m2);
9899 %}
9900 %}
9901
9902 // Float to Long conversion, NaN is mapped to 0.
9903 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9904 match(Set dst (ConvF2L src));
9905 ins_cost(DEFAULT_COST);
9906
9907 expand %{
9908 regF tmpF;
9909 stackSlotL tmpS;
9910 flagsReg crx;
9911 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9912 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9913 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9914 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9915 %}
9916 %}
9917
9918 instruct convD2LRaw_regD(regD dst, regD src) %{
9919 // no match-rule, false predicate
9920 effect(DEF dst, USE src);
9921 predicate(false);
9922
9923 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
9924 size(4);
9925 ins_encode %{
9926 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9927 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9928 %}
9929 ins_pipe(pipe_class_default);
9930 %}
9931
9932 // Double to Long conversion, NaN is mapped to 0.
9933 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
9934 match(Set dst (ConvD2L src));
9935 ins_cost(DEFAULT_COST);
9936
9937 expand %{
9938 regD tmpD;
9939 stackSlotL tmpS;
9940 flagsReg crx;
9941 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9942 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
9943 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9944 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9945 %}
9946 %}
9947
9948 // Convert to Float
9949
9950 // Placed here as needed in expand.
9951 instruct convL2DRaw_regD(regD dst, regD src) %{
9952 // no match-rule, false predicate
9953 effect(DEF dst, USE src);
9954 predicate(false);
9955
9956 format %{ "FCFID $dst, $src \t// convL2D" %}
9957 size(4);
9958 ins_encode %{
9959 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
9960 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
9961 %}
9962 ins_pipe(pipe_class_default);
9963 %}
9964
9965 // Placed here as needed in expand.
9966 instruct convD2F_reg(regF dst, regD src) %{
9967 match(Set dst (ConvD2F src));
9968 format %{ "FRSP $dst, $src \t// convD2F" %}
9969 size(4);
9970 ins_encode %{
9971 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
9972 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
9973 %}
9974 ins_pipe(pipe_class_default);
9975 %}
9976
9977 // Integer to Float conversion.
9978 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
9979 match(Set dst (ConvI2F src));
9980 predicate(!VM_Version::has_fcfids());
9981 ins_cost(DEFAULT_COST);
9982
9983 expand %{
9984 iRegLdst tmpL;
9985 stackSlotL tmpS;
9986 regD tmpD;
9987 regD tmpD2;
9988 convI2L_reg(tmpL, src); // Sign-extension int to long.
9989 regL_to_stkL(tmpS, tmpL); // Store long to stack.
9990 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
9991 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
9992 convD2F_reg(dst, tmpD2); // Convert double to float.
9993 %}
9994 %}
9995
9996 instruct convL2FRaw_regF(regF dst, regD src) %{
9997 // no match-rule, false predicate
9998 effect(DEF dst, USE src);
9999 predicate(false);
10000
10001 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10002 size(4);
10003 ins_encode %{
10004 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10005 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10006 %}
10007 ins_pipe(pipe_class_default);
10008 %}
10009
10010 // Integer to Float conversion. Special version for Power7.
10011 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10012 match(Set dst (ConvI2F src));
10013 predicate(VM_Version::has_fcfids());
10014 ins_cost(DEFAULT_COST);
10015
10016 expand %{
10017 iRegLdst tmpL;
10018 stackSlotL tmpS;
10019 regD tmpD;
10020 convI2L_reg(tmpL, src); // Sign-extension int to long.
10021 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10022 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10023 convL2FRaw_regF(dst, tmpD); // Convert to float.
10024 %}
10025 %}
10026
10027 // L2F to avoid runtime call.
10028 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10029 match(Set dst (ConvL2F src));
10030 predicate(VM_Version::has_fcfids());
10031 ins_cost(DEFAULT_COST);
10032
10033 expand %{
10034 stackSlotL tmpS;
10035 regD tmpD;
10036 regL_to_stkL(tmpS, src); // Store long to stack.
10037 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10038 convL2FRaw_regF(dst, tmpD); // Convert to float.
10039 %}
10040 %}
10041
10042 // Moved up as used in expand.
10043 //instruct convD2F_reg(regF dst, regD src) %{%}
10044
10045 // Convert to Double
10046
10047 // Integer to Double conversion.
10048 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10049 match(Set dst (ConvI2D src));
10050 ins_cost(DEFAULT_COST);
10051
10052 expand %{
10053 iRegLdst tmpL;
10054 stackSlotL tmpS;
10055 regD tmpD;
10056 convI2L_reg(tmpL, src); // Sign-extension int to long.
10057 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10058 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10059 convL2DRaw_regD(dst, tmpD); // Convert to double.
10060 %}
10061 %}
10062
10063 // Long to Double conversion
10064 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10065 match(Set dst (ConvL2D src));
10066 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10067
10068 expand %{
10069 regD tmpD;
10070 moveL2D_stack_reg(tmpD, src);
10071 convL2DRaw_regD(dst, tmpD);
10072 %}
10073 %}
10074
10075 instruct convF2D_reg(regD dst, regF src) %{
10076 match(Set dst (ConvF2D src));
10077 format %{ "FMR $dst, $src \t// float->double" %}
10078 // variable size, 0 or 4
10079 ins_encode %{
10080 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10081 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10082 %}
10083 ins_pipe(pipe_class_default);
10084 %}
10085
10086 //----------Control Flow Instructions------------------------------------------
10087 // Compare Instructions
10088
10089 // Compare Integers
10090 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10091 match(Set crx (CmpI src1 src2));
10092 size(4);
10093 format %{ "CMPW $crx, $src1, $src2" %}
10094 ins_encode %{
10095 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10096 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10097 %}
10098 ins_pipe(pipe_class_compare);
10099 %}
10100
10101 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10102 match(Set crx (CmpI src1 src2));
10103 format %{ "CMPWI $crx, $src1, $src2" %}
10104 size(4);
10105 ins_encode %{
10106 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10107 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10108 %}
10109 ins_pipe(pipe_class_compare);
10110 %}
10111
10112 // (src1 & src2) == 0?
10113 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10114 match(Set cr0 (CmpI (AndI src1 src2) zero));
10115 // r0 is killed
10116 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10117 size(4);
10118 ins_encode %{
10119 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10120 // FIXME: avoid andi_ ?
10121 __ andi_(R0, $src1$$Register, $src2$$constant);
10122 %}
10123 ins_pipe(pipe_class_compare);
10124 %}
10125
10126 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10127 match(Set crx (CmpL src1 src2));
10128 format %{ "CMPD $crx, $src1, $src2" %}
10129 size(4);
10130 ins_encode %{
10131 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10132 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10133 %}
10134 ins_pipe(pipe_class_compare);
10135 %}
10136
10137 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10138 match(Set crx (CmpL src1 src2));
10139 format %{ "CMPDI $crx, $src1, $src2" %}
10140 size(4);
10141 ins_encode %{
10142 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10143 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10144 %}
10145 ins_pipe(pipe_class_compare);
10146 %}
10147
10148 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10149 match(Set cr0 (CmpL (AndL src1 src2) zero));
10150 // r0 is killed
10151 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10152 size(4);
10153 ins_encode %{
10154 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10155 __ and_(R0, $src1$$Register, $src2$$Register);
10156 %}
10157 ins_pipe(pipe_class_compare);
10158 %}
10159
10160 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10161 match(Set cr0 (CmpL (AndL src1 src2) zero));
10162 // r0 is killed
10163 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10164 size(4);
10165 ins_encode %{
10166 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10167 // FIXME: avoid andi_ ?
10168 __ andi_(R0, $src1$$Register, $src2$$constant);
10169 %}
10170 ins_pipe(pipe_class_compare);
10171 %}
10172
10173 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10174 // no match-rule, false predicate
10175 effect(DEF dst, USE crx);
10176 predicate(false);
10177
10178 ins_variable_size_depending_on_alignment(true);
10179
10180 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10181 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10182 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10183 ins_encode %{
10184 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10185 Label done;
10186 // li(Rdst, 0); // equal -> 0
10187 __ beq($crx$$CondRegister, done);
10188 __ li($dst$$Register, 1); // greater -> +1
10189 __ bgt($crx$$CondRegister, done);
10190 __ li($dst$$Register, -1); // unordered or less -> -1
10191 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10192 __ bind(done);
10193 %}
10194 ins_pipe(pipe_class_compare);
10195 %}
10196
10197 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10198 // no match-rule, false predicate
10199 effect(DEF dst, USE crx);
10200 predicate(false);
10201
10202 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10203 postalloc_expand %{
10204 //
10205 // replaces
10206 //
10207 // region crx
10208 // \ |
10209 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10210 //
10211 // with
10212 //
10213 // region
10214 // \
10215 // dst=loadConI16(0)
10216 // |
10217 // ^ region crx
10218 // | \ |
10219 // dst=cmovI_conIvalueMinus1_conIvalue1
10220 //
10221
10222 // Create new nodes.
10223 MachNode *m1 = new (C) loadConI16Node();
10224 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node();
10225
10226 // inputs for new nodes
10227 m1->add_req(n_region);
10228 m2->add_req(n_region, n_crx);
10229 m2->add_prec(m1);
10230
10231 // operands for new nodes
10232 m1->_opnds[0] = op_dst;
10233 m1->_opnds[1] = new (C) immI16Oper(0);
10234 m2->_opnds[0] = op_dst;
10235 m2->_opnds[1] = op_crx;
10236
10237 // registers for new nodes
10238 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10239 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10240
10241 // Insert new nodes.
10242 nodes->push(m1);
10243 nodes->push(m2);
10244 %}
10245 %}
10246
10247 // Manifest a CmpL3 result in an integer register. Very painful.
10248 // This is the test to avoid.
10249 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10250 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10251 match(Set dst (CmpL3 src1 src2));
10252 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10253
10254 expand %{
10255 flagsReg tmp1;
10256 cmpL_reg_reg(tmp1, src1, src2);
10257 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10258 %}
10259 %}
10260
10261 // Implicit range checks.
10262 // A range check in the ideal world has one of the following shapes:
10263 // - (If le (CmpU length index)), (IfTrue throw exception)
10264 // - (If lt (CmpU index length)), (IfFalse throw exception)
10265 //
10266 // Match range check 'If le (CmpU length index)'.
10267 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10268 match(If cmp (CmpU src_length index));
10269 effect(USE labl);
10270 predicate(TrapBasedRangeChecks &&
10271 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10272 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10273 (Matcher::branches_to_uncommon_trap(_leaf)));
10274
10275 ins_is_TrapBasedCheckNode(true);
10276
10277 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10278 size(4);
10279 ins_encode %{
10280 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10281 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10282 __ trap_range_check_le($src_length$$Register, $index$$constant);
10283 } else {
10284 // Both successors are uncommon traps, probability is 0.
10285 // Node got flipped during fixup flow.
10286 assert($cmp$$cmpcode == 0x9, "must be greater");
10287 __ trap_range_check_g($src_length$$Register, $index$$constant);
10288 }
10289 %}
10290 ins_pipe(pipe_class_trap);
10291 %}
10292
10293 // Match range check 'If lt (CmpU index length)'.
10294 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10295 match(If cmp (CmpU src_index src_length));
10296 effect(USE labl);
10297 predicate(TrapBasedRangeChecks &&
10298 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10299 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10300 (Matcher::branches_to_uncommon_trap(_leaf)));
10301
10302 ins_is_TrapBasedCheckNode(true);
10303
10304 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10305 size(4);
10306 ins_encode %{
10307 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10308 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10309 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10310 } else {
10311 // Both successors are uncommon traps, probability is 0.
10312 // Node got flipped during fixup flow.
10313 assert($cmp$$cmpcode == 0x8, "must be less");
10314 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10315 }
10316 %}
10317 ins_pipe(pipe_class_trap);
10318 %}
10319
10320 // Match range check 'If lt (CmpU index length)'.
10321 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10322 match(If cmp (CmpU src_index length));
10323 effect(USE labl);
10324 predicate(TrapBasedRangeChecks &&
10325 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10326 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10327 (Matcher::branches_to_uncommon_trap(_leaf)));
10328
10329 ins_is_TrapBasedCheckNode(true);
10330
10331 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10332 size(4);
10333 ins_encode %{
10334 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10335 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10336 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10337 } else {
10338 // Both successors are uncommon traps, probability is 0.
10339 // Node got flipped during fixup flow.
10340 assert($cmp$$cmpcode == 0x8, "must be less");
10341 __ trap_range_check_l($src_index$$Register, $length$$constant);
10342 }
10343 %}
10344 ins_pipe(pipe_class_trap);
10345 %}
10346
10347 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10348 match(Set crx (CmpU src1 src2));
10349 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10350 size(4);
10351 ins_encode %{
10352 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10353 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10354 %}
10355 ins_pipe(pipe_class_compare);
10356 %}
10357
10358 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10359 match(Set crx (CmpU src1 src2));
10360 size(4);
10361 format %{ "CMPLWI $crx, $src1, $src2" %}
10362 ins_encode %{
10363 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10364 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10365 %}
10366 ins_pipe(pipe_class_compare);
10367 %}
10368
10369 // Implicit zero checks (more implicit null checks).
10370 // No constant pool entries required.
10371 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10372 match(If cmp (CmpN value zero));
10373 effect(USE labl);
10374 predicate(TrapBasedNullChecks &&
10375 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10376 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10377 Matcher::branches_to_uncommon_trap(_leaf));
10378 ins_cost(1);
10379
10380 ins_is_TrapBasedCheckNode(true);
10381
10382 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10383 size(4);
10384 ins_encode %{
10385 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10386 if ($cmp$$cmpcode == 0xA) {
10387 __ trap_null_check($value$$Register);
10388 } else {
10389 // Both successors are uncommon traps, probability is 0.
10390 // Node got flipped during fixup flow.
10391 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10392 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10393 }
10394 %}
10395 ins_pipe(pipe_class_trap);
10396 %}
10397
10398 // Compare narrow oops.
10399 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10400 match(Set crx (CmpN src1 src2));
10401
10402 size(4);
10403 ins_cost(DEFAULT_COST);
10404 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10405 ins_encode %{
10406 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10407 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10408 %}
10409 ins_pipe(pipe_class_compare);
10410 %}
10411
10412 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10413 match(Set crx (CmpN src1 src2));
10414 // Make this more expensive than zeroCheckN_iReg_imm0.
10415 ins_cost(DEFAULT_COST);
10416
10417 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10418 size(4);
10419 ins_encode %{
10420 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10421 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10422 %}
10423 ins_pipe(pipe_class_compare);
10424 %}
10425
10426 // Implicit zero checks (more implicit null checks).
10427 // No constant pool entries required.
10428 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10429 match(If cmp (CmpP value zero));
10430 effect(USE labl);
10431 predicate(TrapBasedNullChecks &&
10432 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10433 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10434 Matcher::branches_to_uncommon_trap(_leaf));
10435
10436 ins_is_TrapBasedCheckNode(true);
10437
10438 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10439 size(4);
10440 ins_encode %{
10441 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10442 if ($cmp$$cmpcode == 0xA) {
10443 __ trap_null_check($value$$Register);
10444 } else {
10445 // Both successors are uncommon traps, probability is 0.
10446 // Node got flipped during fixup flow.
10447 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10448 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10449 }
10450 %}
10451 ins_pipe(pipe_class_trap);
10452 %}
10453
10454 // Compare Pointers
10455 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10456 match(Set crx (CmpP src1 src2));
10457 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10458 size(4);
10459 ins_encode %{
10460 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10461 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10462 %}
10463 ins_pipe(pipe_class_compare);
10464 %}
10465
10466 // Used in postalloc expand.
10467 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10468 // This match rule prevents reordering of node before a safepoint.
10469 // This only makes sense if this instructions is used exclusively
10470 // for the expansion of EncodeP!
10471 match(Set crx (CmpP src1 src2));
10472 predicate(false);
10473
10474 format %{ "CMPDI $crx, $src1, $src2" %}
10475 size(4);
10476 ins_encode %{
10477 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10478 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10479 %}
10480 ins_pipe(pipe_class_compare);
10481 %}
10482
10483 //----------Float Compares----------------------------------------------------
10484
10485 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10486 // no match-rule, false predicate
10487 effect(DEF crx, USE src1, USE src2);
10488 predicate(false);
10489
10490 format %{ "cmpFUrd $crx, $src1, $src2" %}
10491 size(4);
10492 ins_encode %{
10493 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10494 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10495 %}
10496 ins_pipe(pipe_class_default);
10497 %}
10498
10499 instruct cmov_bns_less(flagsReg crx) %{
10500 // no match-rule, false predicate
10501 effect(DEF crx);
10502 predicate(false);
10503
10504 ins_variable_size_depending_on_alignment(true);
10505
10506 format %{ "cmov $crx" %}
10507 // Worst case is branch + move + stop, no stop without scheduler.
10508 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10509 ins_encode %{
10510 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10511 Label done;
10512 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10513 __ li(R0, 0);
10514 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10515 // TODO PPC port __ endgroup_if_needed(_size == 16);
10516 __ bind(done);
10517 %}
10518 ins_pipe(pipe_class_default);
10519 %}
10520
10521 // Compare floating, generate condition code.
10522 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10523 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10524 //
10525 // The following code sequence occurs a lot in mpegaudio:
10526 //
10527 // block BXX:
10528 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10529 // cmpFUrd CCR6, F11, F9
10530 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10531 // cmov CCR6
10532 // 8: instruct branchConSched:
10533 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10534 match(Set crx (CmpF src1 src2));
10535 ins_cost(DEFAULT_COST+BRANCH_COST);
10536
10537 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10538 postalloc_expand %{
10539 //
10540 // replaces
10541 //
10542 // region src1 src2
10543 // \ | |
10544 // crx=cmpF_reg_reg
10545 //
10546 // with
10547 //
10548 // region src1 src2
10549 // \ | |
10550 // crx=cmpFUnordered_reg_reg
10551 // |
10552 // ^ region
10553 // | \
10554 // crx=cmov_bns_less
10555 //
10556
10557 // Create new nodes.
10558 MachNode *m1 = new (C) cmpFUnordered_reg_regNode();
10559 MachNode *m2 = new (C) cmov_bns_lessNode();
10560
10561 // inputs for new nodes
10562 m1->add_req(n_region, n_src1, n_src2);
10563 m2->add_req(n_region);
10564 m2->add_prec(m1);
10565
10566 // operands for new nodes
10567 m1->_opnds[0] = op_crx;
10568 m1->_opnds[1] = op_src1;
10569 m1->_opnds[2] = op_src2;
10570 m2->_opnds[0] = op_crx;
10571
10572 // registers for new nodes
10573 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10574 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10575
10576 // Insert new nodes.
10577 nodes->push(m1);
10578 nodes->push(m2);
10579 %}
10580 %}
10581
10582 // Compare float, generate -1,0,1
10583 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10584 match(Set dst (CmpF3 src1 src2));
10585 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10586
10587 expand %{
10588 flagsReg tmp1;
10589 cmpFUnordered_reg_reg(tmp1, src1, src2);
10590 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10591 %}
10592 %}
10593
10594 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10595 // no match-rule, false predicate
10596 effect(DEF crx, USE src1, USE src2);
10597 predicate(false);
10598
10599 format %{ "cmpFUrd $crx, $src1, $src2" %}
10600 size(4);
10601 ins_encode %{
10602 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10603 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10604 %}
10605 ins_pipe(pipe_class_default);
10606 %}
10607
10608 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10609 match(Set crx (CmpD src1 src2));
10610 ins_cost(DEFAULT_COST+BRANCH_COST);
10611
10612 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10613 postalloc_expand %{
10614 //
10615 // replaces
10616 //
10617 // region src1 src2
10618 // \ | |
10619 // crx=cmpD_reg_reg
10620 //
10621 // with
10622 //
10623 // region src1 src2
10624 // \ | |
10625 // crx=cmpDUnordered_reg_reg
10626 // |
10627 // ^ region
10628 // | \
10629 // crx=cmov_bns_less
10630 //
10631
10632 // create new nodes
10633 MachNode *m1 = new (C) cmpDUnordered_reg_regNode();
10634 MachNode *m2 = new (C) cmov_bns_lessNode();
10635
10636 // inputs for new nodes
10637 m1->add_req(n_region, n_src1, n_src2);
10638 m2->add_req(n_region);
10639 m2->add_prec(m1);
10640
10641 // operands for new nodes
10642 m1->_opnds[0] = op_crx;
10643 m1->_opnds[1] = op_src1;
10644 m1->_opnds[2] = op_src2;
10645 m2->_opnds[0] = op_crx;
10646
10647 // registers for new nodes
10648 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10649 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10650
10651 // Insert new nodes.
10652 nodes->push(m1);
10653 nodes->push(m2);
10654 %}
10655 %}
10656
10657 // Compare double, generate -1,0,1
10658 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10659 match(Set dst (CmpD3 src1 src2));
10660 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10661
10662 expand %{
10663 flagsReg tmp1;
10664 cmpDUnordered_reg_reg(tmp1, src1, src2);
10665 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10666 %}
10667 %}
10668
10669 //----------Branches---------------------------------------------------------
10670 // Jump
10671
10672 // Direct Branch.
10673 instruct branch(label labl) %{
10674 match(Goto);
10675 effect(USE labl);
10676 ins_cost(BRANCH_COST);
10677
10678 format %{ "B $labl" %}
10679 size(4);
10680 ins_encode %{
10681 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10682 Label d; // dummy
10683 __ bind(d);
10684 Label* p = $labl$$label;
10685 // `p' is `NULL' when this encoding class is used only to
10686 // determine the size of the encoded instruction.
10687 Label& l = (NULL == p)? d : *(p);
10688 __ b(l);
10689 %}
10690 ins_pipe(pipe_class_default);
10691 %}
10692
10693 // Conditional Near Branch
10694 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10695 // Same match rule as `branchConFar'.
10696 match(If cmp crx);
10697 effect(USE lbl);
10698 ins_cost(BRANCH_COST);
10699
10700 // If set to 1 this indicates that the current instruction is a
10701 // short variant of a long branch. This avoids using this
10702 // instruction in first-pass matching. It will then only be used in
10703 // the `Shorten_branches' pass.
10704 ins_short_branch(1);
10705
10706 format %{ "B$cmp $crx, $lbl" %}
10707 size(4);
10708 ins_encode( enc_bc(crx, cmp, lbl) );
10709 ins_pipe(pipe_class_default);
10710 %}
10711
10712 // This is for cases when the ppc64 `bc' instruction does not
10713 // reach far enough. So we emit a far branch here, which is more
10714 // expensive.
10715 //
10716 // Conditional Far Branch
10717 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10718 // Same match rule as `branchCon'.
10719 match(If cmp crx);
10720 effect(USE crx, USE lbl);
10721 predicate(!false /* TODO: PPC port HB_Schedule*/);
10722 // Higher cost than `branchCon'.
10723 ins_cost(5*BRANCH_COST);
10724
10725 // This is not a short variant of a branch, but the long variant.
10726 ins_short_branch(0);
10727
10728 format %{ "B_FAR$cmp $crx, $lbl" %}
10729 size(8);
10730 ins_encode( enc_bc_far(crx, cmp, lbl) );
10731 ins_pipe(pipe_class_default);
10732 %}
10733
10734 // Conditional Branch used with Power6 scheduler (can be far or short).
10735 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10736 // Same match rule as `branchCon'.
10737 match(If cmp crx);
10738 effect(USE crx, USE lbl);
10739 predicate(false /* TODO: PPC port HB_Schedule*/);
10740 // Higher cost than `branchCon'.
10741 ins_cost(5*BRANCH_COST);
10742
10743 // Actually size doesn't depend on alignment but on shortening.
10744 ins_variable_size_depending_on_alignment(true);
10745 // long variant.
10746 ins_short_branch(0);
10747
10748 format %{ "B_FAR$cmp $crx, $lbl" %}
10749 size(8); // worst case
10750 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10751 ins_pipe(pipe_class_default);
10752 %}
10753
10754 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10755 match(CountedLoopEnd cmp crx);
10756 effect(USE labl);
10757 ins_cost(BRANCH_COST);
10758
10759 // short variant.
10760 ins_short_branch(1);
10761
10762 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10763 size(4);
10764 ins_encode( enc_bc(crx, cmp, labl) );
10765 ins_pipe(pipe_class_default);
10766 %}
10767
10768 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10769 match(CountedLoopEnd cmp crx);
10770 effect(USE labl);
10771 predicate(!false /* TODO: PPC port HB_Schedule */);
10772 ins_cost(BRANCH_COST);
10773
10774 // Long variant.
10775 ins_short_branch(0);
10776
10777 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10778 size(8);
10779 ins_encode( enc_bc_far(crx, cmp, labl) );
10780 ins_pipe(pipe_class_default);
10781 %}
10782
10783 // Conditional Branch used with Power6 scheduler (can be far or short).
10784 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10785 match(CountedLoopEnd cmp crx);
10786 effect(USE labl);
10787 predicate(false /* TODO: PPC port HB_Schedule */);
10788 // Higher cost than `branchCon'.
10789 ins_cost(5*BRANCH_COST);
10790
10791 // Actually size doesn't depend on alignment but on shortening.
10792 ins_variable_size_depending_on_alignment(true);
10793 // Long variant.
10794 ins_short_branch(0);
10795
10796 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10797 size(8); // worst case
10798 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10799 ins_pipe(pipe_class_default);
10800 %}
10801
10802 // ============================================================================
10803 // Java runtime operations, intrinsics and other complex operations.
10804
10805 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10806 // array for an instance of the superklass. Set a hidden internal cache on a
10807 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10808 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10809 //
10810 // GL TODO: Improve this.
10811 // - result should not be a TEMP
10812 // - Add match rule as on sparc avoiding additional Cmp.
10813 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10814 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10815 match(Set result (PartialSubtypeCheck subklass superklass));
10816 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10817 ins_cost(DEFAULT_COST*10);
10818
10819 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10820 ins_encode %{
10821 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10822 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10823 $tmp_klass$$Register, NULL, $result$$Register);
10824 %}
10825 ins_pipe(pipe_class_default);
10826 %}
10827
10828 // inlined locking and unlocking
10829
10830 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10831 match(Set crx (FastLock oop box));
10832 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10833 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10834
10835 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10836 ins_encode %{
10837 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10838 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10839 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10840 // If locking was successfull, crx should indicate 'EQ'.
10841 // The compiler generates a branch to the runtime call to
10842 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10843 %}
10844 ins_pipe(pipe_class_compare);
10845 %}
10846
10847 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10848 match(Set crx (FastUnlock oop box));
10849 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10850
10851 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10852 ins_encode %{
10853 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10854 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10855 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10856 // If unlocking was successfull, crx should indicate 'EQ'.
10857 // The compiler generates a branch to the runtime call to
10858 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10859 %}
10860 ins_pipe(pipe_class_compare);
10861 %}
10862
10863 // Align address.
10864 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10865 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10866
10867 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10868 size(4);
10869 ins_encode %{
10870 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10871 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10872 %}
10873 ins_pipe(pipe_class_default);
10874 %}
10875
10876 // Array size computation.
10877 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10878 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10879
10880 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10881 size(4);
10882 ins_encode %{
10883 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10884 __ subf($dst$$Register, $start$$Register, $end$$Register);
10885 %}
10886 ins_pipe(pipe_class_default);
10887 %}
10888
10889 // Clear-array with dynamic array-size.
10890 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10891 match(Set dummy (ClearArray cnt base));
10892 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10893 ins_cost(MEMORY_REF_COST);
10894
10895 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10896
10897 format %{ "ClearArray $cnt, $base" %}
10898 ins_encode %{
10899 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10900 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10901 %}
10902 ins_pipe(pipe_class_default);
10903 %}
10904
10905 // String_IndexOf for needle of length 1.
10906 //
10907 // Match needle into immediate operands: no loadConP node needed. Saves one
10908 // register and two instructions over string_indexOf_imm1Node.
10909 //
10910 // Assumes register result differs from all input registers.
10911 //
10912 // Preserves registers haystack, haycnt
10913 // Kills registers tmp1, tmp2
10914 // Defines registers result
10915 //
10916 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10917 //
10918 // Unfortunately this does not match too often. In many situations the AddP is used
10919 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10920 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10921 immP needleImm, immL offsetImm, immI_1 needlecntImm,
10922 iRegIdst tmp1, iRegIdst tmp2,
10923 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10924 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
10925 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
10926
10927 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
10928
10929 ins_cost(150);
10930 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
10931 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
10932
10933 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
10934 ins_encode %{
10935 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10936 immPOper *needleOper = (immPOper *)$needleImm;
10937 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10938 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
10939
10940 __ string_indexof_1($result$$Register,
10941 $haystack$$Register, $haycnt$$Register,
10942 R0, needle_values->char_at(0),
10943 $tmp1$$Register, $tmp2$$Register);
10944 %}
10945 ins_pipe(pipe_class_compare);
10946 %}
10947
10948 // String_IndexOf for needle of length 1.
10949 //
10950 // Special case requires less registers and emits less instructions.
10951 //
10952 // Assumes register result differs from all input registers.
10953 //
10954 // Preserves registers haystack, haycnt
10955 // Kills registers tmp1, tmp2, needle
10956 // Defines registers result
10957 //
10958 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10959 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10960 rscratch2RegP needle, immI_1 needlecntImm,
10961 iRegIdst tmp1, iRegIdst tmp2,
10962 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10963 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10964 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
10965 TEMP tmp1, TEMP tmp2);
10966 // Required for EA: check if it is still a type_array.
10967 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
10968 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
10969 ins_cost(180);
10970
10971 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10972
10973 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
10974 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
10975 ins_encode %{
10976 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10977 Node *ndl = in(operand_index($needle)); // The node that defines needle.
10978 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
10979 guarantee(needle_values, "sanity");
10980 if (needle_values != NULL) {
10981 __ string_indexof_1($result$$Register,
10982 $haystack$$Register, $haycnt$$Register,
10983 R0, needle_values->char_at(0),
10984 $tmp1$$Register, $tmp2$$Register);
10985 } else {
10986 __ string_indexof_1($result$$Register,
10987 $haystack$$Register, $haycnt$$Register,
10988 $needle$$Register, 0,
10989 $tmp1$$Register, $tmp2$$Register);
10990 }
10991 %}
10992 ins_pipe(pipe_class_compare);
10993 %}
10994
10995 // String_IndexOf.
10996 //
10997 // Length of needle as immediate. This saves instruction loading constant needle
10998 // length.
10999 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11000 // completely or do it in vector instruction. This should save registers for
11001 // needlecnt and needle.
11002 //
11003 // Assumes register result differs from all input registers.
11004 // Overwrites haycnt, needlecnt.
11005 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11006 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11007 iRegPsrc needle, uimmI15 needlecntImm,
11008 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11009 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11010 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11011 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11012 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11013 // Required for EA: check if it is still a type_array.
11014 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11015 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11016 ins_cost(250);
11017
11018 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11019
11020 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11021 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11022 ins_encode %{
11023 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11024 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11025 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11026
11027 __ string_indexof($result$$Register,
11028 $haystack$$Register, $haycnt$$Register,
11029 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11030 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11031 %}
11032 ins_pipe(pipe_class_compare);
11033 %}
11034
11035 // StrIndexOf node.
11036 //
11037 // Assumes register result differs from all input registers.
11038 // Overwrites haycnt, needlecnt.
11039 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11040 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11041 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11042 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11043 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11044 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11045 TEMP result,
11046 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11047 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11048 ins_cost(300);
11049
11050 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11051
11052 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11053 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11054 ins_encode %{
11055 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11056 __ string_indexof($result$$Register,
11057 $haystack$$Register, $haycnt$$Register,
11058 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11059 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11060 %}
11061 ins_pipe(pipe_class_compare);
11062 %}
11063
11064 // String equals with immediate.
11065 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11066 iRegPdst tmp1, iRegPdst tmp2,
11067 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11068 match(Set result (StrEquals (Binary str1 str2) cntImm));
11069 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11070 KILL cr0, KILL cr6, KILL ctr);
11071 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11072 ins_cost(250);
11073
11074 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11075
11076 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11077 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11078 ins_encode %{
11079 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11080 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11081 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11082 %}
11083 ins_pipe(pipe_class_compare);
11084 %}
11085
11086 // String equals.
11087 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11088 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11089 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11090 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11091 match(Set result (StrEquals (Binary str1 str2) cnt));
11092 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11093 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11094 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11095 ins_cost(300);
11096
11097 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11098
11099 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11100 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11101 ins_encode %{
11102 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11103 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11104 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11105 %}
11106 ins_pipe(pipe_class_compare);
11107 %}
11108
11109 // String compare.
11110 // Char[] pointers are passed in.
11111 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11112 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11113 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11114 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11115 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11116 ins_cost(300);
11117
11118 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11119
11120 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11121 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11122 ins_encode %{
11123 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11124 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11125 $result$$Register, $tmp$$Register);
11126 %}
11127 ins_pipe(pipe_class_compare);
11128 %}
11129
11130 //---------- Min/Max Instructions ---------------------------------------------
11131
11132 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11133 match(Set dst (MinI src1 src2));
11134 ins_cost(DEFAULT_COST*6);
11135
11136 expand %{
11137 iRegIdst src1s;
11138 iRegIdst src2s;
11139 iRegIdst diff;
11140 iRegIdst sm;
11141 iRegIdst doz; // difference or zero
11142 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11143 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11144 subI_reg_reg(diff, src2s, src1s);
11145 // Need to consider >=33 bit result, therefore we need signmaskL.
11146 signmask64I_regI(sm, diff);
11147 andI_reg_reg(doz, diff, sm); // <=0
11148 addI_reg_reg(dst, doz, src1s);
11149 %}
11150 %}
11151
11152 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11153 match(Set dst (MaxI src1 src2));
11154 ins_cost(DEFAULT_COST*6);
11155
11156 expand %{
11157 immI_minus1 m1 %{ -1 %}
11158 iRegIdst src1s;
11159 iRegIdst src2s;
11160 iRegIdst diff;
11161 iRegIdst sm;
11162 iRegIdst doz; // difference or zero
11163 sxtI_reg(src1s, src1); // Ensure proper sign extention.
11164 sxtI_reg(src2s, src2); // Ensure proper sign extention.
11165 subI_reg_reg(diff, src2s, src1s);
11166 // Need to consider >=33 bit result, therefore we need signmaskL.
11167 signmask64I_regI(sm, diff);
11168 andcI_reg_reg(doz, sm, m1, diff); // >=0
11169 addI_reg_reg(dst, doz, src1s);
11170 %}
11171 %}
11172
11173 //---------- Population Count Instructions ------------------------------------
11174
11175 // Popcnt for Power7.
11176 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11177 match(Set dst (PopCountI src));
11178 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11179 ins_cost(DEFAULT_COST);
11180
11181 format %{ "POPCNTW $dst, $src" %}
11182 size(4);
11183 ins_encode %{
11184 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11185 __ popcntw($dst$$Register, $src$$Register);
11186 %}
11187 ins_pipe(pipe_class_default);
11188 %}
11189
11190 // Popcnt for Power7.
11191 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11192 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11193 match(Set dst (PopCountL src));
11194 ins_cost(DEFAULT_COST);
11195
11196 format %{ "POPCNTD $dst, $src" %}
11197 size(4);
11198 ins_encode %{
11199 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11200 __ popcntd($dst$$Register, $src$$Register);
11201 %}
11202 ins_pipe(pipe_class_default);
11203 %}
11204
11205 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11206 match(Set dst (CountLeadingZerosI src));
11207 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11208 ins_cost(DEFAULT_COST);
11209
11210 format %{ "CNTLZW $dst, $src" %}
11211 size(4);
11212 ins_encode %{
11213 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11214 __ cntlzw($dst$$Register, $src$$Register);
11215 %}
11216 ins_pipe(pipe_class_default);
11217 %}
11218
11219 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11220 match(Set dst (CountLeadingZerosL src));
11221 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11222 ins_cost(DEFAULT_COST);
11223
11224 format %{ "CNTLZD $dst, $src" %}
11225 size(4);
11226 ins_encode %{
11227 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11228 __ cntlzd($dst$$Register, $src$$Register);
11229 %}
11230 ins_pipe(pipe_class_default);
11231 %}
11232
11233 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11234 // no match-rule, false predicate
11235 effect(DEF dst, USE src);
11236 predicate(false);
11237
11238 format %{ "CNTLZD $dst, $src" %}
11239 size(4);
11240 ins_encode %{
11241 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11242 __ cntlzd($dst$$Register, $src$$Register);
11243 %}
11244 ins_pipe(pipe_class_default);
11245 %}
11246
11247 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11248 match(Set dst (CountTrailingZerosI src));
11249 predicate(UseCountLeadingZerosInstructionsPPC64);
11250 ins_cost(DEFAULT_COST);
11251
11252 expand %{
11253 immI16 imm1 %{ (int)-1 %}
11254 immI16 imm2 %{ (int)32 %}
11255 immI_minus1 m1 %{ -1 %}
11256 iRegIdst tmpI1;
11257 iRegIdst tmpI2;
11258 iRegIdst tmpI3;
11259 addI_reg_imm16(tmpI1, src, imm1);
11260 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11261 countLeadingZerosI(tmpI3, tmpI2);
11262 subI_imm16_reg(dst, imm2, tmpI3);
11263 %}
11264 %}
11265
11266 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11267 match(Set dst (CountTrailingZerosL src));
11268 predicate(UseCountLeadingZerosInstructionsPPC64);
11269 ins_cost(DEFAULT_COST);
11270
11271 expand %{
11272 immL16 imm1 %{ (long)-1 %}
11273 immI16 imm2 %{ (int)64 %}
11274 iRegLdst tmpL1;
11275 iRegLdst tmpL2;
11276 iRegIdst tmpL3;
11277 addL_reg_imm16(tmpL1, src, imm1);
11278 andcL_reg_reg(tmpL2, tmpL1, src);
11279 countLeadingZerosL(tmpL3, tmpL2);
11280 subI_imm16_reg(dst, imm2, tmpL3);
11281 %}
11282 %}
11283
11284 // Expand nodes for byte_reverse_int.
11285 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11286 effect(DEF dst, USE src, USE pos, USE shift);
11287 predicate(false);
11288
11289 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11290 size(4);
11291 ins_encode %{
11292 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11293 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11294 %}
11295 ins_pipe(pipe_class_default);
11296 %}
11297
11298 // As insrwi_a, but with USE_DEF.
11299 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11300 effect(USE_DEF dst, USE src, USE pos, USE shift);
11301 predicate(false);
11302
11303 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11304 size(4);
11305 ins_encode %{
11306 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11307 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11308 %}
11309 ins_pipe(pipe_class_default);
11310 %}
11311
11312 // Just slightly faster than java implementation.
11313 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11314 match(Set dst (ReverseBytesI src));
11315 predicate(UseCountLeadingZerosInstructionsPPC64);
11316 ins_cost(DEFAULT_COST);
11317
11318 expand %{
11319 immI16 imm24 %{ (int) 24 %}
11320 immI16 imm16 %{ (int) 16 %}
11321 immI16 imm8 %{ (int) 8 %}
11322 immI16 imm4 %{ (int) 4 %}
11323 immI16 imm0 %{ (int) 0 %}
11324 iRegLdst tmpI1;
11325 iRegLdst tmpI2;
11326 iRegLdst tmpI3;
11327
11328 urShiftI_reg_imm(tmpI1, src, imm24);
11329 insrwi_a(dst, tmpI1, imm24, imm8);
11330 urShiftI_reg_imm(tmpI2, src, imm16);
11331 insrwi(dst, tmpI2, imm8, imm16);
11332 urShiftI_reg_imm(tmpI3, src, imm8);
11333 insrwi(dst, tmpI3, imm8, imm8);
11334 insrwi(dst, src, imm0, imm8);
11335 %}
11336 %}
11337
11338 //---------- Replicate Vector Instructions ------------------------------------
11339
11340 // Insrdi does replicate if src == dst.
11341 instruct repl32(iRegLdst dst) %{
11342 predicate(false);
11343 effect(USE_DEF dst);
11344
11345 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11346 size(4);
11347 ins_encode %{
11348 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11349 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11350 %}
11351 ins_pipe(pipe_class_default);
11352 %}
11353
11354 // Insrdi does replicate if src == dst.
11355 instruct repl48(iRegLdst dst) %{
11356 predicate(false);
11357 effect(USE_DEF dst);
11358
11359 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11360 size(4);
11361 ins_encode %{
11362 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11363 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11364 %}
11365 ins_pipe(pipe_class_default);
11366 %}
11367
11368 // Insrdi does replicate if src == dst.
11369 instruct repl56(iRegLdst dst) %{
11370 predicate(false);
11371 effect(USE_DEF dst);
11372
11373 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11374 size(4);
11375 ins_encode %{
11376 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11377 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11378 %}
11379 ins_pipe(pipe_class_default);
11380 %}
11381
11382 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11383 match(Set dst (ReplicateB src));
11384 predicate(n->as_Vector()->length() == 8);
11385 expand %{
11386 moveReg(dst, src);
11387 repl56(dst);
11388 repl48(dst);
11389 repl32(dst);
11390 %}
11391 %}
11392
11393 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11394 match(Set dst (ReplicateB zero));
11395 predicate(n->as_Vector()->length() == 8);
11396 format %{ "LI $dst, #0 \t// replicate8B" %}
11397 size(4);
11398 ins_encode %{
11399 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11400 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11401 %}
11402 ins_pipe(pipe_class_default);
11403 %}
11404
11405 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11406 match(Set dst (ReplicateB src));
11407 predicate(n->as_Vector()->length() == 8);
11408 format %{ "LI $dst, #-1 \t// replicate8B" %}
11409 size(4);
11410 ins_encode %{
11411 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11412 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11413 %}
11414 ins_pipe(pipe_class_default);
11415 %}
11416
11417 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11418 match(Set dst (ReplicateS src));
11419 predicate(n->as_Vector()->length() == 4);
11420 expand %{
11421 moveReg(dst, src);
11422 repl48(dst);
11423 repl32(dst);
11424 %}
11425 %}
11426
11427 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11428 match(Set dst (ReplicateS zero));
11429 predicate(n->as_Vector()->length() == 4);
11430 format %{ "LI $dst, #0 \t// replicate4C" %}
11431 size(4);
11432 ins_encode %{
11433 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11434 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11435 %}
11436 ins_pipe(pipe_class_default);
11437 %}
11438
11439 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11440 match(Set dst (ReplicateS src));
11441 predicate(n->as_Vector()->length() == 4);
11442 format %{ "LI $dst, -1 \t// replicate4C" %}
11443 size(4);
11444 ins_encode %{
11445 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11446 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11447 %}
11448 ins_pipe(pipe_class_default);
11449 %}
11450
11451 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11452 match(Set dst (ReplicateI src));
11453 predicate(n->as_Vector()->length() == 2);
11454 ins_cost(2 * DEFAULT_COST);
11455 expand %{
11456 moveReg(dst, src);
11457 repl32(dst);
11458 %}
11459 %}
11460
11461 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11462 match(Set dst (ReplicateI zero));
11463 predicate(n->as_Vector()->length() == 2);
11464 format %{ "LI $dst, #0 \t// replicate4C" %}
11465 size(4);
11466 ins_encode %{
11467 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11468 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11469 %}
11470 ins_pipe(pipe_class_default);
11471 %}
11472
11473 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11474 match(Set dst (ReplicateI src));
11475 predicate(n->as_Vector()->length() == 2);
11476 format %{ "LI $dst, -1 \t// replicate4C" %}
11477 size(4);
11478 ins_encode %{
11479 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11480 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11481 %}
11482 ins_pipe(pipe_class_default);
11483 %}
11484
11485 // Move float to int register via stack, replicate.
11486 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11487 match(Set dst (ReplicateF src));
11488 predicate(n->as_Vector()->length() == 2);
11489 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11490 expand %{
11491 stackSlotL tmpS;
11492 iRegIdst tmpI;
11493 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11494 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11495 moveReg(dst, tmpI); // Move int to long reg.
11496 repl32(dst); // Replicate bitpattern.
11497 %}
11498 %}
11499
11500 // Replicate scalar constant to packed float values in Double register
11501 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11502 match(Set dst (ReplicateF src));
11503 predicate(n->as_Vector()->length() == 2);
11504 ins_cost(5 * DEFAULT_COST);
11505
11506 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11507 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11508 %}
11509
11510 // Replicate scalar zero constant to packed float values in Double register
11511 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11512 match(Set dst (ReplicateF zero));
11513 predicate(n->as_Vector()->length() == 2);
11514
11515 format %{ "LI $dst, #0 \t// replicate2F" %}
11516 ins_encode %{
11517 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11518 __ li($dst$$Register, 0x0);
11519 %}
11520 ins_pipe(pipe_class_default);
11521 %}
11522
11523 // ============================================================================
11524 // Safepoint Instruction
11525
11526 instruct safePoint_poll(iRegPdst poll) %{
11527 match(SafePoint poll);
11528 predicate(LoadPollAddressFromThread);
11529
11530 // It caused problems to add the effect that r0 is killed, but this
11531 // effect no longer needs to be mentioned, since r0 is not contained
11532 // in a reg_class.
11533
11534 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11535 size(4);
11536 ins_encode( enc_poll(0x0, poll) );
11537 ins_pipe(pipe_class_default);
11538 %}
11539
11540 // Safepoint without per-thread support. Load address of page to poll
11541 // as constant.
11542 // Rscratch2RegP is R12.
11543 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11544 // a seperate node so that the oop map is at the right location.
11545 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11546 match(SafePoint poll);
11547 predicate(!LoadPollAddressFromThread);
11548
11549 // It caused problems to add the effect that r0 is killed, but this
11550 // effect no longer needs to be mentioned, since r0 is not contained
11551 // in a reg_class.
11552
11553 format %{ "LD R12, addr of polling page\n\t"
11554 "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11555 ins_encode( enc_poll(0x0, poll) );
11556 ins_pipe(pipe_class_default);
11557 %}
11558
11559 // ============================================================================
11560 // Call Instructions
11561
11562 // Call Java Static Instruction
11563
11564 // Schedulable version of call static node.
11565 instruct CallStaticJavaDirect(method meth) %{
11566 match(CallStaticJava);
11567 effect(USE meth);
11568 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11569 ins_cost(CALL_COST);
11570
11571 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11572
11573 format %{ "CALL,static $meth \t// ==> " %}
11574 size(4);
11575 ins_encode( enc_java_static_call(meth) );
11576 ins_pipe(pipe_class_call);
11577 %}
11578
11579 // Schedulable version of call static node.
11580 instruct CallStaticJavaDirectHandle(method meth) %{
11581 match(CallStaticJava);
11582 effect(USE meth);
11583 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11584 ins_cost(CALL_COST);
11585
11586 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11587
11588 format %{ "CALL,static $meth \t// ==> " %}
11589 ins_encode( enc_java_handle_call(meth) );
11590 ins_pipe(pipe_class_call);
11591 %}
11592
11593 // Call Java Dynamic Instruction
11594
11595 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11596 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11597 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11598 // The call destination must still be placed in the constant pool.
11599 instruct CallDynamicJavaDirectSched(method meth) %{
11600 match(CallDynamicJava); // To get all the data fields we need ...
11601 effect(USE meth);
11602 predicate(false); // ... but never match.
11603
11604 ins_field_load_ic_hi_node(loadConL_hiNode*);
11605 ins_field_load_ic_node(loadConLNode*);
11606 ins_num_consts(1 /* 1 patchable constant: call destination */);
11607
11608 format %{ "BL \t// dynamic $meth ==> " %}
11609 size(4);
11610 ins_encode( enc_java_dynamic_call_sched(meth) );
11611 ins_pipe(pipe_class_call);
11612 %}
11613
11614 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11615 // We use postalloc expanded calls if we use inline caches
11616 // and do not update method data.
11617 //
11618 // This instruction has two constants: inline cache (IC) and call destination.
11619 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11620 // one constant.
11621 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11622 match(CallDynamicJava);
11623 effect(USE meth);
11624 predicate(UseInlineCaches);
11625 ins_cost(CALL_COST);
11626
11627 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11628
11629 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11630 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11631 %}
11632
11633 // Compound version of call dynamic java
11634 // We use postalloc expanded calls if we use inline caches
11635 // and do not update method data.
11636 instruct CallDynamicJavaDirect(method meth) %{
11637 match(CallDynamicJava);
11638 effect(USE meth);
11639 predicate(!UseInlineCaches);
11640 ins_cost(CALL_COST);
11641
11642 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11643 ins_num_consts(4);
11644
11645 format %{ "CALL,dynamic $meth \t// ==> " %}
11646 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11647 ins_pipe(pipe_class_call);
11648 %}
11649
11650 // Call Runtime Instruction
11651
11652 instruct CallRuntimeDirect(method meth) %{
11653 match(CallRuntime);
11654 effect(USE meth);
11655 ins_cost(CALL_COST);
11656
11657 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11658 // env for callee, C-toc.
11659 ins_num_consts(3);
11660
11661 format %{ "CALL,runtime" %}
11662 ins_encode( enc_java_to_runtime_call(meth) );
11663 ins_pipe(pipe_class_call);
11664 %}
11665
11666 // Call Leaf
11667
11668 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11669 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11670 effect(DEF dst, USE src);
11671
11672 ins_num_consts(1);
11673
11674 format %{ "MTCTR $src" %}
11675 size(4);
11676 ins_encode( enc_leaf_call_mtctr(src) );
11677 ins_pipe(pipe_class_default);
11678 %}
11679
11680 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11681 instruct CallLeafDirect(method meth) %{
11682 match(CallLeaf); // To get the data all the data fields we need ...
11683 effect(USE meth);
11684 predicate(false); // but never match.
11685
11686 format %{ "BCTRL \t// leaf call $meth ==> " %}
11687 size(4);
11688 ins_encode %{
11689 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11690 __ bctrl();
11691 %}
11692 ins_pipe(pipe_class_call);
11693 %}
11694
11695 // postalloc expand of CallLeafDirect.
11696 // Load adress to call from TOC, then bl to it.
11697 instruct CallLeafDirect_Ex(method meth) %{
11698 match(CallLeaf);
11699 effect(USE meth);
11700 ins_cost(CALL_COST);
11701
11702 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11703 // env for callee, C-toc.
11704 ins_num_consts(3);
11705
11706 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11707 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11708 %}
11709
11710 // Call runtime without safepoint - same as CallLeaf.
11711 // postalloc expand of CallLeafNoFPDirect.
11712 // Load adress to call from TOC, then bl to it.
11713 instruct CallLeafNoFPDirect_Ex(method meth) %{
11714 match(CallLeafNoFP);
11715 effect(USE meth);
11716 ins_cost(CALL_COST);
11717
11718 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11719 // env for callee, C-toc.
11720 ins_num_consts(3);
11721
11722 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11723 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11724 %}
11725
11726 // Tail Call; Jump from runtime stub to Java code.
11727 // Also known as an 'interprocedural jump'.
11728 // Target of jump will eventually return to caller.
11729 // TailJump below removes the return address.
11730 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11731 match(TailCall jump_target method_oop);
11732 ins_cost(CALL_COST);
11733
11734 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11735 "BCTR \t// tail call" %}
11736 size(8);
11737 ins_encode %{
11738 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11739 __ mtctr($jump_target$$Register);
11740 __ bctr();
11741 %}
11742 ins_pipe(pipe_class_call);
11743 %}
11744
11745 // Return Instruction
11746 instruct Ret() %{
11747 match(Return);
11748 format %{ "BLR \t// branch to link register" %}
11749 size(4);
11750 ins_encode %{
11751 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11752 // LR is restored in MachEpilogNode. Just do the RET here.
11753 __ blr();
11754 %}
11755 ins_pipe(pipe_class_default);
11756 %}
11757
11758 // Tail Jump; remove the return address; jump to target.
11759 // TailCall above leaves the return address around.
11760 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11761 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11762 // "restore" before this instruction (in Epilogue), we need to materialize it
11763 // in %i0.
11764 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11765 match(TailJump jump_target ex_oop);
11766 ins_cost(CALL_COST);
11767
11768 format %{ "LD R4_ARG2 = LR\n\t"
11769 "MTCTR $jump_target\n\t"
11770 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11771 size(12);
11772 ins_encode %{
11773 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11774 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11775 __ mtctr($jump_target$$Register);
11776 __ bctr();
11777 %}
11778 ins_pipe(pipe_class_call);
11779 %}
11780
11781 // Create exception oop: created by stack-crawling runtime code.
11782 // Created exception is now available to this handler, and is setup
11783 // just prior to jumping to this handler. No code emitted.
11784 instruct CreateException(rarg1RegP ex_oop) %{
11785 match(Set ex_oop (CreateEx));
11786 ins_cost(0);
11787
11788 format %{ " -- \t// exception oop; no code emitted" %}
11789 size(0);
11790 ins_encode( /*empty*/ );
11791 ins_pipe(pipe_class_default);
11792 %}
11793
11794 // Rethrow exception: The exception oop will come in the first
11795 // argument position. Then JUMP (not call) to the rethrow stub code.
11796 instruct RethrowException() %{
11797 match(Rethrow);
11798 ins_cost(CALL_COST);
11799
11800 format %{ "Jmp rethrow_stub" %}
11801 ins_encode %{
11802 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11803 cbuf.set_insts_mark();
11804 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11805 %}
11806 ins_pipe(pipe_class_call);
11807 %}
11808
11809 // Die now.
11810 instruct ShouldNotReachHere() %{
11811 match(Halt);
11812 ins_cost(CALL_COST);
11813
11814 format %{ "ShouldNotReachHere" %}
11815 size(4);
11816 ins_encode %{
11817 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11818 __ trap_should_not_reach_here();
11819 %}
11820 ins_pipe(pipe_class_default);
11821 %}
11822
11823 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11824 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11825 // Get a DEF on threadRegP, no costs, no encoding, use
11826 // 'ins_should_rematerialize(true)' to avoid spilling.
11827 instruct tlsLoadP(threadRegP dst) %{
11828 match(Set dst (ThreadLocal));
11829 ins_cost(0);
11830
11831 ins_should_rematerialize(true);
11832
11833 format %{ " -- \t// $dst=Thread::current(), empty" %}
11834 size(0);
11835 ins_encode( /*empty*/ );
11836 ins_pipe(pipe_class_empty);
11837 %}
11838
11839 //---Some PPC specific nodes---------------------------------------------------
11840
11841 // Stop a group.
11842 instruct endGroup() %{
11843 ins_cost(0);
11844
11845 ins_is_nop(true);
11846
11847 format %{ "End Bundle (ori r1, r1, 0)" %}
11848 size(4);
11849 ins_encode %{
11850 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11851 __ endgroup();
11852 %}
11853 ins_pipe(pipe_class_default);
11854 %}
11855
11856 // Nop instructions
11857
11858 instruct fxNop() %{
11859 ins_cost(0);
11860
11861 ins_is_nop(true);
11862
11863 format %{ "fxNop" %}
11864 size(4);
11865 ins_encode %{
11866 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11867 __ nop();
11868 %}
11869 ins_pipe(pipe_class_default);
11870 %}
11871
11872 instruct fpNop0() %{
11873 ins_cost(0);
11874
11875 ins_is_nop(true);
11876
11877 format %{ "fpNop0" %}
11878 size(4);
11879 ins_encode %{
11880 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11881 __ fpnop0();
11882 %}
11883 ins_pipe(pipe_class_default);
11884 %}
11885
11886 instruct fpNop1() %{
11887 ins_cost(0);
11888
11889 ins_is_nop(true);
11890
11891 format %{ "fpNop1" %}
11892 size(4);
11893 ins_encode %{
11894 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11895 __ fpnop1();
11896 %}
11897 ins_pipe(pipe_class_default);
11898 %}
11899
11900 instruct brNop0() %{
11901 ins_cost(0);
11902 size(4);
11903 format %{ "brNop0" %}
11904 ins_encode %{
11905 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11906 __ brnop0();
11907 %}
11908 ins_is_nop(true);
11909 ins_pipe(pipe_class_default);
11910 %}
11911
11912 instruct brNop1() %{
11913 ins_cost(0);
11914
11915 ins_is_nop(true);
11916
11917 format %{ "brNop1" %}
11918 size(4);
11919 ins_encode %{
11920 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11921 __ brnop1();
11922 %}
11923 ins_pipe(pipe_class_default);
11924 %}
11925
11926 instruct brNop2() %{
11927 ins_cost(0);
11928
11929 ins_is_nop(true);
11930
11931 format %{ "brNop2" %}
11932 size(4);
11933 ins_encode %{
11934 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11935 __ brnop2();
11936 %}
11937 ins_pipe(pipe_class_default);
11938 %}
11939
11940 //----------PEEPHOLE RULES-----------------------------------------------------
11941 // These must follow all instruction definitions as they use the names
11942 // defined in the instructions definitions.
11943 //
11944 // peepmatch ( root_instr_name [preceeding_instruction]* );
11945 //
11946 // peepconstraint %{
11947 // (instruction_number.operand_name relational_op instruction_number.operand_name
11948 // [, ...] );
11949 // // instruction numbers are zero-based using left to right order in peepmatch
11950 //
11951 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11952 // // provide an instruction_number.operand_name for each operand that appears
11953 // // in the replacement instruction's match rule
11954 //
11955 // ---------VM FLAGS---------------------------------------------------------
11956 //
11957 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11958 //
11959 // Each peephole rule is given an identifying number starting with zero and
11960 // increasing by one in the order seen by the parser. An individual peephole
11961 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11962 // on the command-line.
11963 //
11964 // ---------CURRENT LIMITATIONS----------------------------------------------
11965 //
11966 // Only match adjacent instructions in same basic block
11967 // Only equality constraints
11968 // Only constraints between operands, not (0.dest_reg == EAX_enc)
11969 // Only one replacement instruction
11970 //
11971 // ---------EXAMPLE----------------------------------------------------------
11972 //
11973 // // pertinent parts of existing instructions in architecture description
11974 // instruct movI(eRegI dst, eRegI src) %{
11975 // match(Set dst (CopyI src));
11976 // %}
11977 //
11978 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
11979 // match(Set dst (AddI dst src));
11980 // effect(KILL cr);
11981 // %}
11982 //
11983 // // Change (inc mov) to lea
11984 // peephole %{
11985 // // increment preceeded by register-register move
11986 // peepmatch ( incI_eReg movI );
11987 // // require that the destination register of the increment
11988 // // match the destination register of the move
11989 // peepconstraint ( 0.dst == 1.dst );
11990 // // construct a replacement instruction that sets
11991 // // the destination to ( move's source register + one )
11992 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
11993 // %}
11994 //
11995 // Implementation no longer uses movX instructions since
11996 // machine-independent system no longer uses CopyX nodes.
11997 //
11998 // peephole %{
11999 // peepmatch ( incI_eReg movI );
12000 // peepconstraint ( 0.dst == 1.dst );
12001 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12002 // %}
12003 //
12004 // peephole %{
12005 // peepmatch ( decI_eReg movI );
12006 // peepconstraint ( 0.dst == 1.dst );
12007 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12008 // %}
12009 //
12010 // peephole %{
12011 // peepmatch ( addI_eReg_imm movI );
12012 // peepconstraint ( 0.dst == 1.dst );
12013 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12014 // %}
12015 //
12016 // peephole %{
12017 // peepmatch ( addP_eReg_imm movP );
12018 // peepconstraint ( 0.dst == 1.dst );
12019 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12020 // %}
12021
12022 // // Change load of spilled value to only a spill
12023 // instruct storeI(memory mem, eRegI src) %{
12024 // match(Set mem (StoreI mem src));
12025 // %}
12026 //
12027 // instruct loadI(eRegI dst, memory mem) %{
12028 // match(Set dst (LoadI mem));
12029 // %}
12030 //
12031 peephole %{
12032 peepmatch ( loadI storeI );
12033 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12034 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12035 %}
12036
12037 peephole %{
12038 peepmatch ( loadL storeL );
12039 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12040 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12041 %}
12042
12043 peephole %{
12044 peepmatch ( loadP storeP );
12045 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12046 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12047 %}
12048
12049 //----------SMARTSPILL RULES---------------------------------------------------
12050 // These must follow all instruction definitions as they use the names
12051 // defined in the instructions definitions.