1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
492 ShouldNotReachHere();
493 }
494
495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
496 // Empty encoding
497 }
498
499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
500 return 0;
501 }
502
503 #ifndef PRODUCT
504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
505 st->print("# MachConstantBaseNode (empty encoding)");
506 }
507 #endif
508
509
510 //=============================================================================
511 #ifndef PRODUCT
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
513 Compile* C = ra_->C;
514
515 int framesize = C->frame_slots() << LogBytesPerInt;
516 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
517 // Remove wordSize for return addr which is already pushed.
518 framesize -= wordSize;
519
520 if (C->need_stack_bang(framesize)) {
521 framesize -= wordSize;
522 st->print("# stack bang");
523 st->print("\n\t");
524 st->print("PUSH EBP\t# Save EBP");
525 if (framesize) {
526 st->print("\n\t");
527 st->print("SUB ESP, #%d\t# Create frame",framesize);
528 }
529 } else {
530 st->print("SUB ESP, #%d\t# Create frame",framesize);
531 st->print("\n\t");
532 framesize -= wordSize;
533 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
534 }
535
536 if (VerifyStackAtCalls) {
537 st->print("\n\t");
538 framesize -= wordSize;
539 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
540 }
541
542 if( C->in_24_bit_fp_mode() ) {
543 st->print("\n\t");
544 st->print("FLDCW \t# load 24 bit fpu control word");
545 }
546 if (UseSSE >= 2 && VerifyFPU) {
547 st->print("\n\t");
548 st->print("# verify FPU stack (must be clean on entry)");
549 }
550
551 #ifdef ASSERT
552 if (VerifyStackAtCalls) {
553 st->print("\n\t");
554 st->print("# stack alignment check");
555 }
556 #endif
557 st->cr();
558 }
559 #endif
560
561
562 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
563 Compile* C = ra_->C;
564 MacroAssembler _masm(&cbuf);
565
566 int framesize = C->frame_slots() << LogBytesPerInt;
567
568 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
569
570 C->set_frame_complete(cbuf.insts_size());
571
572 if (C->has_mach_constant_base_node()) {
573 // NOTE: We set the table base offset here because users might be
574 // emitted before MachConstantBaseNode.
575 Compile::ConstantTable& constant_table = C->constant_table();
576 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
577 }
578 }
579
580 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
581 return MachNode::size(ra_); // too many variables; just compute it the hard way
582 }
583
584 int MachPrologNode::reloc() const {
585 return 0; // a large enough number
586 }
587
588 //=============================================================================
589 #ifndef PRODUCT
590 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
591 Compile *C = ra_->C;
592 int framesize = C->frame_slots() << LogBytesPerInt;
593 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
594 // Remove two words for return addr and rbp,
595 framesize -= 2*wordSize;
596
597 if (C->max_vector_size() > 16) {
598 st->print("VZEROUPPER");
599 st->cr(); st->print("\t");
600 }
601 if (C->in_24_bit_fp_mode()) {
602 st->print("FLDCW standard control word");
603 st->cr(); st->print("\t");
604 }
605 if (framesize) {
606 st->print("ADD ESP,%d\t# Destroy frame",framesize);
607 st->cr(); st->print("\t");
608 }
609 st->print_cr("POPL EBP"); st->print("\t");
610 if (do_polling() && C->is_method_compilation()) {
611 st->print("TEST PollPage,EAX\t! Poll Safepoint");
612 st->cr(); st->print("\t");
613 }
614 }
615 #endif
616
617 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
618 Compile *C = ra_->C;
619
620 if (C->max_vector_size() > 16) {
621 // Clear upper bits of YMM registers when current compiled code uses
622 // wide vectors to avoid AVX <-> SSE transition penalty during call.
623 MacroAssembler masm(&cbuf);
624 masm.vzeroupper();
625 }
626 // If method set FPU control word, restore to standard control word
627 if (C->in_24_bit_fp_mode()) {
628 MacroAssembler masm(&cbuf);
629 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
630 }
631
632 int framesize = C->frame_slots() << LogBytesPerInt;
633 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
634 // Remove two words for return addr and rbp,
635 framesize -= 2*wordSize;
636
637 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
638
639 if (framesize >= 128) {
640 emit_opcode(cbuf, 0x81); // add SP, #framesize
641 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
642 emit_d32(cbuf, framesize);
643 } else if (framesize) {
644 emit_opcode(cbuf, 0x83); // add SP, #framesize
645 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
646 emit_d8(cbuf, framesize);
647 }
648
649 emit_opcode(cbuf, 0x58 | EBP_enc);
650
651 if (do_polling() && C->is_method_compilation()) {
652 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
653 emit_opcode(cbuf,0x85);
654 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
655 emit_d32(cbuf, (intptr_t)os::get_polling_page());
656 }
657 }
658
659 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
660 Compile *C = ra_->C;
661 // If method set FPU control word, restore to standard control word
662 int size = C->in_24_bit_fp_mode() ? 6 : 0;
663 if (C->max_vector_size() > 16) size += 3; // vzeroupper
664 if (do_polling() && C->is_method_compilation()) size += 6;
665
666 int framesize = C->frame_slots() << LogBytesPerInt;
667 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
668 // Remove two words for return addr and rbp,
669 framesize -= 2*wordSize;
670
671 size++; // popl rbp,
672
673 if (framesize >= 128) {
674 size += 6;
675 } else {
676 size += framesize ? 3 : 0;
677 }
678 return size;
679 }
680
681 int MachEpilogNode::reloc() const {
682 return 0; // a large enough number
683 }
684
685 const Pipeline * MachEpilogNode::pipeline() const {
686 return MachNode::pipeline_class();
687 }
688
689 int MachEpilogNode::safepoint_offset() const { return 0; }
690
691 //=============================================================================
692
693 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
694 static enum RC rc_class( OptoReg::Name reg ) {
695
696 if( !OptoReg::is_valid(reg) ) return rc_bad;
697 if (OptoReg::is_stack(reg)) return rc_stack;
698
699 VMReg r = OptoReg::as_VMReg(reg);
700 if (r->is_Register()) return rc_int;
701 if (r->is_FloatRegister()) {
702 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
703 return rc_float;
704 }
705 assert(r->is_XMMRegister(), "must be");
706 return rc_xmm;
707 }
708
709 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
710 int opcode, const char *op_str, int size, outputStream* st ) {
711 if( cbuf ) {
712 emit_opcode (*cbuf, opcode );
713 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
714 #ifndef PRODUCT
715 } else if( !do_size ) {
716 if( size != 0 ) st->print("\n\t");
717 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
718 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
719 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
720 } else { // FLD, FST, PUSH, POP
721 st->print("%s [ESP + #%d]",op_str,offset);
722 }
723 #endif
724 }
725 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
726 return size+3+offset_size;
727 }
728
729 // Helper for XMM registers. Extra opcode bits, limited syntax.
730 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
731 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
732 if (cbuf) {
733 MacroAssembler _masm(cbuf);
734 if (reg_lo+1 == reg_hi) { // double move?
735 if (is_load) {
736 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
737 } else {
738 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
739 }
740 } else {
741 if (is_load) {
742 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
743 } else {
744 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
745 }
746 }
747 #ifndef PRODUCT
748 } else if (!do_size) {
749 if (size != 0) st->print("\n\t");
750 if (reg_lo+1 == reg_hi) { // double move?
751 if (is_load) st->print("%s %s,[ESP + #%d]",
752 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSD [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 } else {
757 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
758 Matcher::regName[reg_lo], offset);
759 else st->print("MOVSS [ESP + #%d],%s",
760 offset, Matcher::regName[reg_lo]);
761 }
762 #endif
763 }
764 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
765 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
766 return size+5+offset_size;
767 }
768
769
770 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
771 int src_hi, int dst_hi, int size, outputStream* st ) {
772 if (cbuf) {
773 MacroAssembler _masm(cbuf);
774 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
775 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
776 as_XMMRegister(Matcher::_regEncode[src_lo]));
777 } else {
778 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
779 as_XMMRegister(Matcher::_regEncode[src_lo]));
780 }
781 #ifndef PRODUCT
782 } else if (!do_size) {
783 if (size != 0) st->print("\n\t");
784 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
785 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
786 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
787 } else {
788 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
789 }
790 } else {
791 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
792 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
793 } else {
794 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
795 }
796 }
797 #endif
798 }
799 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
800 // Only MOVAPS SSE prefix uses 1 byte.
801 int sz = 4;
802 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
803 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
804 return size + sz;
805 }
806
807 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
808 int src_hi, int dst_hi, int size, outputStream* st ) {
809 // 32-bit
810 if (cbuf) {
811 MacroAssembler _masm(cbuf);
812 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
813 as_Register(Matcher::_regEncode[src_lo]));
814 #ifndef PRODUCT
815 } else if (!do_size) {
816 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
817 #endif
818 }
819 return 4;
820 }
821
822
823 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
824 int src_hi, int dst_hi, int size, outputStream* st ) {
825 // 32-bit
826 if (cbuf) {
827 MacroAssembler _masm(cbuf);
828 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
829 as_XMMRegister(Matcher::_regEncode[src_lo]));
830 #ifndef PRODUCT
831 } else if (!do_size) {
832 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
833 #endif
834 }
835 return 4;
836 }
837
838 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
839 if( cbuf ) {
840 emit_opcode(*cbuf, 0x8B );
841 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
842 #ifndef PRODUCT
843 } else if( !do_size ) {
844 if( size != 0 ) st->print("\n\t");
845 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
846 #endif
847 }
848 return size+2;
849 }
850
851 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
852 int offset, int size, outputStream* st ) {
853 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
854 if( cbuf ) {
855 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
856 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
857 #ifndef PRODUCT
858 } else if( !do_size ) {
859 if( size != 0 ) st->print("\n\t");
860 st->print("FLD %s",Matcher::regName[src_lo]);
861 #endif
862 }
863 size += 2;
864 }
865
866 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
867 const char *op_str;
868 int op;
869 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
870 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
871 op = 0xDD;
872 } else { // 32-bit store
873 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
874 op = 0xD9;
875 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
876 }
877
878 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
879 }
880
881 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
882 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
883 int src_hi, int dst_hi, uint ireg, outputStream* st);
884
885 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
886 int stack_offset, int reg, uint ireg, outputStream* st);
887
888 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
889 int dst_offset, uint ireg, outputStream* st) {
890 int calc_size = 0;
891 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
892 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
893 switch (ireg) {
894 case Op_VecS:
895 calc_size = 3+src_offset_size + 3+dst_offset_size;
896 break;
897 case Op_VecD:
898 calc_size = 3+src_offset_size + 3+dst_offset_size;
899 src_offset += 4;
900 dst_offset += 4;
901 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
902 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
903 calc_size += 3+src_offset_size + 3+dst_offset_size;
904 break;
905 case Op_VecX:
906 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
907 break;
908 case Op_VecY:
909 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
910 break;
911 default:
912 ShouldNotReachHere();
913 }
914 if (cbuf) {
915 MacroAssembler _masm(cbuf);
916 int offset = __ offset();
917 switch (ireg) {
918 case Op_VecS:
919 __ pushl(Address(rsp, src_offset));
920 __ popl (Address(rsp, dst_offset));
921 break;
922 case Op_VecD:
923 __ pushl(Address(rsp, src_offset));
924 __ popl (Address(rsp, dst_offset));
925 __ pushl(Address(rsp, src_offset+4));
926 __ popl (Address(rsp, dst_offset+4));
927 break;
928 case Op_VecX:
929 __ movdqu(Address(rsp, -16), xmm0);
930 __ movdqu(xmm0, Address(rsp, src_offset));
931 __ movdqu(Address(rsp, dst_offset), xmm0);
932 __ movdqu(xmm0, Address(rsp, -16));
933 break;
934 case Op_VecY:
935 __ vmovdqu(Address(rsp, -32), xmm0);
936 __ vmovdqu(xmm0, Address(rsp, src_offset));
937 __ vmovdqu(Address(rsp, dst_offset), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, -32));
939 break;
940 default:
941 ShouldNotReachHere();
942 }
943 int size = __ offset() - offset;
944 assert(size == calc_size, "incorrect size calculattion");
945 return size;
946 #ifndef PRODUCT
947 } else if (!do_size) {
948 switch (ireg) {
949 case Op_VecS:
950 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
951 "popl [rsp + #%d]",
952 src_offset, dst_offset);
953 break;
954 case Op_VecD:
955 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
956 "popq [rsp + #%d]\n\t"
957 "pushl [rsp + #%d]\n\t"
958 "popq [rsp + #%d]",
959 src_offset, dst_offset, src_offset+4, dst_offset+4);
960 break;
961 case Op_VecX:
962 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
963 "movdqu xmm0, [rsp + #%d]\n\t"
964 "movdqu [rsp + #%d], xmm0\n\t"
965 "movdqu xmm0, [rsp - #16]",
966 src_offset, dst_offset);
967 break;
968 case Op_VecY:
969 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
970 "vmovdqu xmm0, [rsp + #%d]\n\t"
971 "vmovdqu [rsp + #%d], xmm0\n\t"
972 "vmovdqu xmm0, [rsp - #32]",
973 src_offset, dst_offset);
974 break;
975 default:
976 ShouldNotReachHere();
977 }
978 #endif
979 }
980 return calc_size;
981 }
982
983 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
984 // Get registers to move
985 OptoReg::Name src_second = ra_->get_reg_second(in(1));
986 OptoReg::Name src_first = ra_->get_reg_first(in(1));
987 OptoReg::Name dst_second = ra_->get_reg_second(this );
988 OptoReg::Name dst_first = ra_->get_reg_first(this );
989
990 enum RC src_second_rc = rc_class(src_second);
991 enum RC src_first_rc = rc_class(src_first);
992 enum RC dst_second_rc = rc_class(dst_second);
993 enum RC dst_first_rc = rc_class(dst_first);
994
995 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
996
997 // Generate spill code!
998 int size = 0;
999
1000 if( src_first == dst_first && src_second == dst_second )
1001 return size; // Self copy, no move
1002
1003 if (bottom_type()->isa_vect() != NULL) {
1004 uint ireg = ideal_reg();
1005 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1006 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1009 // mem -> mem
1010 int src_offset = ra_->reg2offset(src_first);
1011 int dst_offset = ra_->reg2offset(dst_first);
1012 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1013 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1014 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1016 int stack_offset = ra_->reg2offset(dst_first);
1017 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1019 int stack_offset = ra_->reg2offset(src_first);
1020 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1021 } else {
1022 ShouldNotReachHere();
1023 }
1024 }
1025
1026 // --------------------------------------
1027 // Check for mem-mem move. push/pop to move.
1028 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1029 if( src_second == dst_first ) { // overlapping stack copy ranges
1030 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1033 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1034 }
1035 // move low bits
1036 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1037 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1038 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1039 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1040 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1041 }
1042 return size;
1043 }
1044
1045 // --------------------------------------
1046 // Check for integer reg-reg copy
1047 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1048 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1049
1050 // Check for integer store
1051 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1052 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1053
1054 // Check for integer load
1055 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1056 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1057
1058 // Check for integer reg-xmm reg copy
1059 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1060 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1061 "no 64 bit integer-float reg moves" );
1062 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1063 }
1064 // --------------------------------------
1065 // Check for float reg-reg copy
1066 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1067 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1068 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1069 if( cbuf ) {
1070
1071 // Note the mucking with the register encode to compensate for the 0/1
1072 // indexing issue mentioned in a comment in the reg_def sections
1073 // for FPR registers many lines above here.
1074
1075 if( src_first != FPR1L_num ) {
1076 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1077 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1078 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1079 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1080 } else {
1081 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1082 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1083 }
1084 #ifndef PRODUCT
1085 } else if( !do_size ) {
1086 if( size != 0 ) st->print("\n\t");
1087 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1088 else st->print( "FST %s", Matcher::regName[dst_first]);
1089 #endif
1090 }
1091 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1092 }
1093
1094 // Check for float store
1095 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1096 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1097 }
1098
1099 // Check for float load
1100 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1101 int offset = ra_->reg2offset(src_first);
1102 const char *op_str;
1103 int op;
1104 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1105 op_str = "FLD_D";
1106 op = 0xDD;
1107 } else { // 32-bit load
1108 op_str = "FLD_S";
1109 op = 0xD9;
1110 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1111 }
1112 if( cbuf ) {
1113 emit_opcode (*cbuf, op );
1114 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1115 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1116 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1117 #ifndef PRODUCT
1118 } else if( !do_size ) {
1119 if( size != 0 ) st->print("\n\t");
1120 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1121 #endif
1122 }
1123 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1124 return size + 3+offset_size+2;
1125 }
1126
1127 // Check for xmm reg-reg copy
1128 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1129 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1130 (src_first+1 == src_second && dst_first+1 == dst_second),
1131 "no non-adjacent float-moves" );
1132 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1133 }
1134
1135 // Check for xmm reg-integer reg copy
1136 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1137 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1138 "no 64 bit float-integer reg moves" );
1139 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1140 }
1141
1142 // Check for xmm store
1143 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1145 }
1146
1147 // Check for float xmm load
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1149 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1150 }
1151
1152 // Copy from float reg to xmm reg
1153 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1154 // copy to the top of stack from floating point reg
1155 // and use LEA to preserve flags
1156 if( cbuf ) {
1157 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1158 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1159 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1160 emit_d8(*cbuf,0xF8);
1161 #ifndef PRODUCT
1162 } else if( !do_size ) {
1163 if( size != 0 ) st->print("\n\t");
1164 st->print("LEA ESP,[ESP-8]");
1165 #endif
1166 }
1167 size += 4;
1168
1169 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1170
1171 // Copy from the temp memory to the xmm reg.
1172 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1173
1174 if( cbuf ) {
1175 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1176 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1177 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1178 emit_d8(*cbuf,0x08);
1179 #ifndef PRODUCT
1180 } else if( !do_size ) {
1181 if( size != 0 ) st->print("\n\t");
1182 st->print("LEA ESP,[ESP+8]");
1183 #endif
1184 }
1185 size += 4;
1186 return size;
1187 }
1188
1189 assert( size > 0, "missed a case" );
1190
1191 // --------------------------------------------------------------------
1192 // Check for second bits still needing moving.
1193 if( src_second == dst_second )
1194 return size; // Self copy; no move
1195 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1196
1197 // Check for second word int-int move
1198 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1199 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1200
1201 // Check for second word integer store
1202 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1203 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1204
1205 // Check for second word integer load
1206 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1207 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1208
1209
1210 Unimplemented();
1211 }
1212
1213 #ifndef PRODUCT
1214 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1215 implementation( NULL, ra_, false, st );
1216 }
1217 #endif
1218
1219 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220 implementation( &cbuf, ra_, false, NULL );
1221 }
1222
1223 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1224 return implementation( NULL, ra_, true, NULL );
1225 }
1226
1227
1228 //=============================================================================
1229 #ifndef PRODUCT
1230 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1231 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1232 int reg = ra_->get_reg_first(this);
1233 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1234 }
1235 #endif
1236
1237 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1238 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1239 int reg = ra_->get_encode(this);
1240 if( offset >= 128 ) {
1241 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1242 emit_rm(cbuf, 0x2, reg, 0x04);
1243 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1244 emit_d32(cbuf, offset);
1245 }
1246 else {
1247 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1248 emit_rm(cbuf, 0x1, reg, 0x04);
1249 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1250 emit_d8(cbuf, offset);
1251 }
1252 }
1253
1254 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1255 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1256 if( offset >= 128 ) {
1257 return 7;
1258 }
1259 else {
1260 return 4;
1261 }
1262 }
1263
1264 //=============================================================================
1265 #ifndef PRODUCT
1266 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1267 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1268 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1269 st->print_cr("\tNOP");
1270 st->print_cr("\tNOP");
1271 if( !OptoBreakpoint )
1272 st->print_cr("\tNOP");
1273 }
1274 #endif
1275
1276 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1277 MacroAssembler masm(&cbuf);
1278 #ifdef ASSERT
1279 uint insts_size = cbuf.insts_size();
1280 #endif
1281 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1282 masm.jump_cc(Assembler::notEqual,
1283 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1284 /* WARNING these NOPs are critical so that verified entry point is properly
1285 aligned for patching by NativeJump::patch_verified_entry() */
1286 int nops_cnt = 2;
1287 if( !OptoBreakpoint ) // Leave space for int3
1288 nops_cnt += 1;
1289 masm.nop(nops_cnt);
1290
1291 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1292 }
1293
1294 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1295 return OptoBreakpoint ? 11 : 12;
1296 }
1297
1298
1299 //=============================================================================
1300 uint size_exception_handler() {
1301 // NativeCall instruction size is the same as NativeJump.
1302 // exception handler starts out as jump and can be patched to
1303 // a call be deoptimization. (4932387)
1304 // Note that this value is also credited (in output.cpp) to
1305 // the size of the code section.
1306 return NativeJump::instruction_size;
1307 }
1308
1309 // Emit exception handler code. Stuff framesize into a register
1310 // and call a VM stub routine.
1311 int emit_exception_handler(CodeBuffer& cbuf) {
1312
1313 // Note that the code buffer's insts_mark is always relative to insts.
1314 // That's why we must use the macroassembler to generate a handler.
1315 MacroAssembler _masm(&cbuf);
1316 address base =
1317 __ start_a_stub(size_exception_handler());
1318 if (base == NULL) return 0; // CodeBuffer::expand failed
1319 int offset = __ offset();
1320 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1321 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1322 __ end_a_stub();
1323 return offset;
1324 }
1325
1326 uint size_deopt_handler() {
1327 // NativeCall instruction size is the same as NativeJump.
1328 // exception handler starts out as jump and can be patched to
1329 // a call be deoptimization. (4932387)
1330 // Note that this value is also credited (in output.cpp) to
1331 // the size of the code section.
1332 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1333 }
1334
1335 // Emit deopt handler code.
1336 int emit_deopt_handler(CodeBuffer& cbuf) {
1337
1338 // Note that the code buffer's insts_mark is always relative to insts.
1339 // That's why we must use the macroassembler to generate a handler.
1340 MacroAssembler _masm(&cbuf);
1341 address base =
1342 __ start_a_stub(size_exception_handler());
1343 if (base == NULL) return 0; // CodeBuffer::expand failed
1344 int offset = __ offset();
1345 InternalAddress here(__ pc());
1346 __ pushptr(here.addr());
1347
1348 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1349 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1350 __ end_a_stub();
1351 return offset;
1352 }
1353
1354 int Matcher::regnum_to_fpu_offset(int regnum) {
1355 return regnum - 32; // The FP registers are in the second chunk
1356 }
1357
1358 // This is UltraSparc specific, true just means we have fast l2f conversion
1359 const bool Matcher::convL2FSupported(void) {
1360 return true;
1361 }
1362
1363 // Is this branch offset short enough that a short branch can be used?
1364 //
1365 // NOTE: If the platform does not provide any short branch variants, then
1366 // this method should return false for offset 0.
1367 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1368 // The passed offset is relative to address of the branch.
1369 // On 86 a branch displacement is calculated relative to address
1370 // of a next instruction.
1371 offset -= br_size;
1372
1373 // the short version of jmpConUCF2 contains multiple branches,
1374 // making the reach slightly less
1375 if (rule == jmpConUCF2_rule)
1376 return (-126 <= offset && offset <= 125);
1377 return (-128 <= offset && offset <= 127);
1378 }
1379
1380 const bool Matcher::isSimpleConstant64(jlong value) {
1381 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1382 return false;
1383 }
1384
1385 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1386 const bool Matcher::init_array_count_is_in_bytes = false;
1387
1388 // Threshold size for cleararray.
1389 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1390
1391 // Needs 2 CMOV's for longs.
1392 const int Matcher::long_cmove_cost() { return 1; }
1393
1394 // No CMOVF/CMOVD with SSE/SSE2
1395 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1396
1397 // Does the CPU require late expand (see block.cpp for description of late expand)?
1398 const bool Matcher::require_postalloc_expand = false;
1399
1400 // Should the Matcher clone shifts on addressing modes, expecting them to
1401 // be subsumed into complex addressing expressions or compute them into
1402 // registers? True for Intel but false for most RISCs
1403 const bool Matcher::clone_shift_expressions = true;
1404
1405 // Do we need to mask the count passed to shift instructions or does
1406 // the cpu only look at the lower 5/6 bits anyway?
1407 const bool Matcher::need_masked_shift_count = false;
1408
1409 bool Matcher::narrow_oop_use_complex_address() {
1410 ShouldNotCallThis();
1411 return true;
1412 }
1413
1414 bool Matcher::narrow_klass_use_complex_address() {
1415 ShouldNotCallThis();
1416 return true;
1417 }
1418
1419
1420 // Is it better to copy float constants, or load them directly from memory?
1421 // Intel can load a float constant from a direct address, requiring no
1422 // extra registers. Most RISCs will have to materialize an address into a
1423 // register first, so they would do better to copy the constant from stack.
1424 const bool Matcher::rematerialize_float_constants = true;
1425
1426 // If CPU can load and store mis-aligned doubles directly then no fixup is
1427 // needed. Else we split the double into 2 integer pieces and move it
1428 // piece-by-piece. Only happens when passing doubles into C code as the
1429 // Java calling convention forces doubles to be aligned.
1430 const bool Matcher::misaligned_doubles_ok = true;
1431
1432
1433 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1434 // Get the memory operand from the node
1435 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1436 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1437 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1438 uint opcnt = 1; // First operand
1439 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1440 while( idx >= skipped+num_edges ) {
1441 skipped += num_edges;
1442 opcnt++; // Bump operand count
1443 assert( opcnt < numopnds, "Accessing non-existent operand" );
1444 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1445 }
1446
1447 MachOper *memory = node->_opnds[opcnt];
1448 MachOper *new_memory = NULL;
1449 switch (memory->opcode()) {
1450 case DIRECT:
1451 case INDOFFSET32X:
1452 // No transformation necessary.
1453 return;
1454 case INDIRECT:
1455 new_memory = new (C) indirect_win95_safeOper( );
1456 break;
1457 case INDOFFSET8:
1458 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1459 break;
1460 case INDOFFSET32:
1461 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1462 break;
1463 case INDINDEXOFFSET:
1464 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1465 break;
1466 case INDINDEXSCALE:
1467 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1468 break;
1469 case INDINDEXSCALEOFFSET:
1470 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1471 break;
1472 case LOAD_LONG_INDIRECT:
1473 case LOAD_LONG_INDOFFSET32:
1474 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1475 return;
1476 default:
1477 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1478 return;
1479 }
1480 node->_opnds[opcnt] = new_memory;
1481 }
1482
1483 // Advertise here if the CPU requires explicit rounding operations
1484 // to implement the UseStrictFP mode.
1485 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1486
1487 // Are floats conerted to double when stored to stack during deoptimization?
1488 // On x32 it is stored with convertion only when FPU is used for floats.
1489 bool Matcher::float_in_double() { return (UseSSE == 0); }
1490
1491 // Do ints take an entire long register or just half?
1492 const bool Matcher::int_in_long = false;
1493
1494 // Return whether or not this register is ever used as an argument. This
1495 // function is used on startup to build the trampoline stubs in generateOptoStub.
1496 // Registers not mentioned will be killed by the VM call in the trampoline, and
1497 // arguments in those registers not be available to the callee.
1498 bool Matcher::can_be_java_arg( int reg ) {
1499 if( reg == ECX_num || reg == EDX_num ) return true;
1500 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1501 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1502 return false;
1503 }
1504
1505 bool Matcher::is_spillable_arg( int reg ) {
1506 return can_be_java_arg(reg);
1507 }
1508
1509 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1510 // Use hardware integer DIV instruction when
1511 // it is faster than a code which use multiply.
1512 // Only when constant divisor fits into 32 bit
1513 // (min_jint is excluded to get only correct
1514 // positive 32 bit values from negative).
1515 return VM_Version::has_fast_idiv() &&
1516 (divisor == (int)divisor && divisor != min_jint);
1517 }
1518
1519 // Register for DIVI projection of divmodI
1520 RegMask Matcher::divI_proj_mask() {
1521 return EAX_REG_mask();
1522 }
1523
1524 // Register for MODI projection of divmodI
1525 RegMask Matcher::modI_proj_mask() {
1526 return EDX_REG_mask();
1527 }
1528
1529 // Register for DIVL projection of divmodL
1530 RegMask Matcher::divL_proj_mask() {
1531 ShouldNotReachHere();
1532 return RegMask();
1533 }
1534
1535 // Register for MODL projection of divmodL
1536 RegMask Matcher::modL_proj_mask() {
1537 ShouldNotReachHere();
1538 return RegMask();
1539 }
1540
1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1542 return EBP_REG_mask();
1543 }
1544
1545 // Returns true if the high 32 bits of the value is known to be zero.
1546 bool is_operand_hi32_zero(Node* n) {
1547 int opc = n->Opcode();
1548 if (opc == Op_AndL) {
1549 Node* o2 = n->in(2);
1550 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1551 return true;
1552 }
1553 }
1554 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1555 return true;
1556 }
1557 return false;
1558 }
1559
1560 %}
1561
1562 //----------ENCODING BLOCK-----------------------------------------------------
1563 // This block specifies the encoding classes used by the compiler to output
1564 // byte streams. Encoding classes generate functions which are called by
1565 // Machine Instruction Nodes in order to generate the bit encoding of the
1566 // instruction. Operands specify their base encoding interface with the
1567 // interface keyword. There are currently supported four interfaces,
1568 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1569 // operand to generate a function which returns its register number when
1570 // queried. CONST_INTER causes an operand to generate a function which
1571 // returns the value of the constant when queried. MEMORY_INTER causes an
1572 // operand to generate four functions which return the Base Register, the
1573 // Index Register, the Scale Value, and the Offset Value of the operand when
1574 // queried. COND_INTER causes an operand to generate six functions which
1575 // return the encoding code (ie - encoding bits for the instruction)
1576 // associated with each basic boolean condition for a conditional instruction.
1577 // Instructions specify two basic values for encoding. They use the
1578 // ins_encode keyword to specify their encoding class (which must be one of
1579 // the class names specified in the encoding block), and they use the
1580 // opcode keyword to specify, in order, their primary, secondary, and
1581 // tertiary opcode. Only the opcode sections which a particular instruction
1582 // needs for encoding need to be specified.
1583 encode %{
1584 // Build emit functions for each basic byte or larger field in the intel
1585 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1586 // code in the enc_class source block. Emit functions will live in the
1587 // main source block for now. In future, we can generalize this by
1588 // adding a syntax that specifies the sizes of fields in an order,
1589 // so that the adlc can build the emit functions automagically
1590
1591 // Emit primary opcode
1592 enc_class OpcP %{
1593 emit_opcode(cbuf, $primary);
1594 %}
1595
1596 // Emit secondary opcode
1597 enc_class OpcS %{
1598 emit_opcode(cbuf, $secondary);
1599 %}
1600
1601 // Emit opcode directly
1602 enc_class Opcode(immI d8) %{
1603 emit_opcode(cbuf, $d8$$constant);
1604 %}
1605
1606 enc_class SizePrefix %{
1607 emit_opcode(cbuf,0x66);
1608 %}
1609
1610 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1611 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1612 %}
1613
1614 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1615 emit_opcode(cbuf,$opcode$$constant);
1616 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1617 %}
1618
1619 enc_class mov_r32_imm0( rRegI dst ) %{
1620 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1621 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1622 %}
1623
1624 enc_class cdq_enc %{
1625 // Full implementation of Java idiv and irem; checks for
1626 // special case as described in JVM spec., p.243 & p.271.
1627 //
1628 // normal case special case
1629 //
1630 // input : rax,: dividend min_int
1631 // reg: divisor -1
1632 //
1633 // output: rax,: quotient (= rax, idiv reg) min_int
1634 // rdx: remainder (= rax, irem reg) 0
1635 //
1636 // Code sequnce:
1637 //
1638 // 81 F8 00 00 00 80 cmp rax,80000000h
1639 // 0F 85 0B 00 00 00 jne normal_case
1640 // 33 D2 xor rdx,edx
1641 // 83 F9 FF cmp rcx,0FFh
1642 // 0F 84 03 00 00 00 je done
1643 // normal_case:
1644 // 99 cdq
1645 // F7 F9 idiv rax,ecx
1646 // done:
1647 //
1648 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1649 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1650 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1651 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1652 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1653 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1654 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1655 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1656 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1657 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1658 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1659 // normal_case:
1660 emit_opcode(cbuf,0x99); // cdq
1661 // idiv (note: must be emitted by the user of this rule)
1662 // normal:
1663 %}
1664
1665 // Dense encoding for older common ops
1666 enc_class Opc_plus(immI opcode, rRegI reg) %{
1667 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1668 %}
1669
1670
1671 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1672 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1673 // Check for 8-bit immediate, and set sign extend bit in opcode
1674 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1675 emit_opcode(cbuf, $primary | 0x02);
1676 }
1677 else { // If 32-bit immediate
1678 emit_opcode(cbuf, $primary);
1679 }
1680 %}
1681
1682 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1683 // Emit primary opcode and set sign-extend bit
1684 // Check for 8-bit immediate, and set sign extend bit in opcode
1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1686 emit_opcode(cbuf, $primary | 0x02); }
1687 else { // If 32-bit immediate
1688 emit_opcode(cbuf, $primary);
1689 }
1690 // Emit r/m byte with secondary opcode, after primary opcode.
1691 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1692 %}
1693
1694 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1695 // Check for 8-bit immediate, and set sign extend bit in opcode
1696 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1697 $$$emit8$imm$$constant;
1698 }
1699 else { // If 32-bit immediate
1700 // Output immediate
1701 $$$emit32$imm$$constant;
1702 }
1703 %}
1704
1705 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1706 // Emit primary opcode and set sign-extend bit
1707 // Check for 8-bit immediate, and set sign extend bit in opcode
1708 int con = (int)$imm$$constant; // Throw away top bits
1709 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1710 // Emit r/m byte with secondary opcode, after primary opcode.
1711 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1712 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1713 else emit_d32(cbuf,con);
1714 %}
1715
1716 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1717 // Emit primary opcode and set sign-extend bit
1718 // Check for 8-bit immediate, and set sign extend bit in opcode
1719 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1720 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1721 // Emit r/m byte with tertiary opcode, after primary opcode.
1722 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1723 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1724 else emit_d32(cbuf,con);
1725 %}
1726
1727 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1728 emit_cc(cbuf, $secondary, $dst$$reg );
1729 %}
1730
1731 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1732 int destlo = $dst$$reg;
1733 int desthi = HIGH_FROM_LOW(destlo);
1734 // bswap lo
1735 emit_opcode(cbuf, 0x0F);
1736 emit_cc(cbuf, 0xC8, destlo);
1737 // bswap hi
1738 emit_opcode(cbuf, 0x0F);
1739 emit_cc(cbuf, 0xC8, desthi);
1740 // xchg lo and hi
1741 emit_opcode(cbuf, 0x87);
1742 emit_rm(cbuf, 0x3, destlo, desthi);
1743 %}
1744
1745 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1746 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1747 %}
1748
1749 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1750 $$$emit8$primary;
1751 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1752 %}
1753
1754 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1755 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1756 emit_d8(cbuf, op >> 8 );
1757 emit_d8(cbuf, op & 255);
1758 %}
1759
1760 // emulate a CMOV with a conditional branch around a MOV
1761 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1762 // Invert sense of branch from sense of CMOV
1763 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1764 emit_d8( cbuf, $brOffs$$constant );
1765 %}
1766
1767 enc_class enc_PartialSubtypeCheck( ) %{
1768 Register Redi = as_Register(EDI_enc); // result register
1769 Register Reax = as_Register(EAX_enc); // super class
1770 Register Recx = as_Register(ECX_enc); // killed
1771 Register Resi = as_Register(ESI_enc); // sub class
1772 Label miss;
1773
1774 MacroAssembler _masm(&cbuf);
1775 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1776 NULL, &miss,
1777 /*set_cond_codes:*/ true);
1778 if ($primary) {
1779 __ xorptr(Redi, Redi);
1780 }
1781 __ bind(miss);
1782 %}
1783
1784 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1785 MacroAssembler masm(&cbuf);
1786 int start = masm.offset();
1787 if (UseSSE >= 2) {
1788 if (VerifyFPU) {
1789 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1790 }
1791 } else {
1792 // External c_calling_convention expects the FPU stack to be 'clean'.
1793 // Compiled code leaves it dirty. Do cleanup now.
1794 masm.empty_FPU_stack();
1795 }
1796 if (sizeof_FFree_Float_Stack_All == -1) {
1797 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1798 } else {
1799 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1800 }
1801 %}
1802
1803 enc_class Verify_FPU_For_Leaf %{
1804 if( VerifyFPU ) {
1805 MacroAssembler masm(&cbuf);
1806 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1807 }
1808 %}
1809
1810 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1811 // This is the instruction starting address for relocation info.
1812 cbuf.set_insts_mark();
1813 $$$emit8$primary;
1814 // CALL directly to the runtime
1815 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1816 runtime_call_Relocation::spec(), RELOC_IMM32 );
1817
1818 if (UseSSE >= 2) {
1819 MacroAssembler _masm(&cbuf);
1820 BasicType rt = tf()->return_type();
1821
1822 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1823 // A C runtime call where the return value is unused. In SSE2+
1824 // mode the result needs to be removed from the FPU stack. It's
1825 // likely that this function call could be removed by the
1826 // optimizer if the C function is a pure function.
1827 __ ffree(0);
1828 } else if (rt == T_FLOAT) {
1829 __ lea(rsp, Address(rsp, -4));
1830 __ fstp_s(Address(rsp, 0));
1831 __ movflt(xmm0, Address(rsp, 0));
1832 __ lea(rsp, Address(rsp, 4));
1833 } else if (rt == T_DOUBLE) {
1834 __ lea(rsp, Address(rsp, -8));
1835 __ fstp_d(Address(rsp, 0));
1836 __ movdbl(xmm0, Address(rsp, 0));
1837 __ lea(rsp, Address(rsp, 8));
1838 }
1839 }
1840 %}
1841
1842
1843 enc_class pre_call_resets %{
1844 // If method sets FPU control word restore it here
1845 debug_only(int off0 = cbuf.insts_size());
1846 if (ra_->C->in_24_bit_fp_mode()) {
1847 MacroAssembler _masm(&cbuf);
1848 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1849 }
1850 if (ra_->C->max_vector_size() > 16) {
1851 // Clear upper bits of YMM registers when current compiled code uses
1852 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1853 MacroAssembler _masm(&cbuf);
1854 __ vzeroupper();
1855 }
1856 debug_only(int off1 = cbuf.insts_size());
1857 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1858 %}
1859
1860 enc_class post_call_FPU %{
1861 // If method sets FPU control word do it here also
1862 if (Compile::current()->in_24_bit_fp_mode()) {
1863 MacroAssembler masm(&cbuf);
1864 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1865 }
1866 %}
1867
1868 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1869 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1870 // who we intended to call.
1871 cbuf.set_insts_mark();
1872 $$$emit8$primary;
1873 if (!_method) {
1874 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1875 runtime_call_Relocation::spec(), RELOC_IMM32 );
1876 } else if (_optimized_virtual) {
1877 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1878 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1879 } else {
1880 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1881 static_call_Relocation::spec(), RELOC_IMM32 );
1882 }
1883 if (_method) { // Emit stub for static call.
1884 CompiledStaticCall::emit_to_interp_stub(cbuf);
1885 }
1886 %}
1887
1888 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1889 MacroAssembler _masm(&cbuf);
1890 __ ic_call((address)$meth$$method);
1891 %}
1892
1893 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1894 int disp = in_bytes(Method::from_compiled_offset());
1895 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1896
1897 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1898 cbuf.set_insts_mark();
1899 $$$emit8$primary;
1900 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1901 emit_d8(cbuf, disp); // Displacement
1902
1903 %}
1904
1905 // Following encoding is no longer used, but may be restored if calling
1906 // convention changes significantly.
1907 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1908 //
1909 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1910 // // int ic_reg = Matcher::inline_cache_reg();
1911 // // int ic_encode = Matcher::_regEncode[ic_reg];
1912 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1913 // // int imo_encode = Matcher::_regEncode[imo_reg];
1914 //
1915 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1916 // // // so we load it immediately before the call
1917 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1918 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1919 //
1920 // // xor rbp,ebp
1921 // emit_opcode(cbuf, 0x33);
1922 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1923 //
1924 // // CALL to interpreter.
1925 // cbuf.set_insts_mark();
1926 // $$$emit8$primary;
1927 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1928 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1929 // %}
1930
1931 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1932 $$$emit8$primary;
1933 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1934 $$$emit8$shift$$constant;
1935 %}
1936
1937 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1938 // Load immediate does not have a zero or sign extended version
1939 // for 8-bit immediates
1940 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1941 $$$emit32$src$$constant;
1942 %}
1943
1944 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1945 // Load immediate does not have a zero or sign extended version
1946 // for 8-bit immediates
1947 emit_opcode(cbuf, $primary + $dst$$reg);
1948 $$$emit32$src$$constant;
1949 %}
1950
1951 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1952 // Load immediate does not have a zero or sign extended version
1953 // for 8-bit immediates
1954 int dst_enc = $dst$$reg;
1955 int src_con = $src$$constant & 0x0FFFFFFFFL;
1956 if (src_con == 0) {
1957 // xor dst, dst
1958 emit_opcode(cbuf, 0x33);
1959 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1960 } else {
1961 emit_opcode(cbuf, $primary + dst_enc);
1962 emit_d32(cbuf, src_con);
1963 }
1964 %}
1965
1966 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1967 // Load immediate does not have a zero or sign extended version
1968 // for 8-bit immediates
1969 int dst_enc = $dst$$reg + 2;
1970 int src_con = ((julong)($src$$constant)) >> 32;
1971 if (src_con == 0) {
1972 // xor dst, dst
1973 emit_opcode(cbuf, 0x33);
1974 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1975 } else {
1976 emit_opcode(cbuf, $primary + dst_enc);
1977 emit_d32(cbuf, src_con);
1978 }
1979 %}
1980
1981
1982 // Encode a reg-reg copy. If it is useless, then empty encoding.
1983 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1984 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1985 %}
1986
1987 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1988 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1989 %}
1990
1991 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1992 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1993 %}
1994
1995 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
1996 $$$emit8$primary;
1997 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1998 %}
1999
2000 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2001 $$$emit8$secondary;
2002 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2003 %}
2004
2005 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2006 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2007 %}
2008
2009 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2010 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2011 %}
2012
2013 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2014 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2015 %}
2016
2017 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2018 // Output immediate
2019 $$$emit32$src$$constant;
2020 %}
2021
2022 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2023 // Output Float immediate bits
2024 jfloat jf = $src$$constant;
2025 int jf_as_bits = jint_cast( jf );
2026 emit_d32(cbuf, jf_as_bits);
2027 %}
2028
2029 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2030 // Output Float immediate bits
2031 jfloat jf = $src$$constant;
2032 int jf_as_bits = jint_cast( jf );
2033 emit_d32(cbuf, jf_as_bits);
2034 %}
2035
2036 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2037 // Output immediate
2038 $$$emit16$src$$constant;
2039 %}
2040
2041 enc_class Con_d32(immI src) %{
2042 emit_d32(cbuf,$src$$constant);
2043 %}
2044
2045 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2046 // Output immediate memory reference
2047 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2048 emit_d32(cbuf, 0x00);
2049 %}
2050
2051 enc_class lock_prefix( ) %{
2052 if( os::is_MP() )
2053 emit_opcode(cbuf,0xF0); // [Lock]
2054 %}
2055
2056 // Cmp-xchg long value.
2057 // Note: we need to swap rbx, and rcx before and after the
2058 // cmpxchg8 instruction because the instruction uses
2059 // rcx as the high order word of the new value to store but
2060 // our register encoding uses rbx,.
2061 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2062
2063 // XCHG rbx,ecx
2064 emit_opcode(cbuf,0x87);
2065 emit_opcode(cbuf,0xD9);
2066 // [Lock]
2067 if( os::is_MP() )
2068 emit_opcode(cbuf,0xF0);
2069 // CMPXCHG8 [Eptr]
2070 emit_opcode(cbuf,0x0F);
2071 emit_opcode(cbuf,0xC7);
2072 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2073 // XCHG rbx,ecx
2074 emit_opcode(cbuf,0x87);
2075 emit_opcode(cbuf,0xD9);
2076 %}
2077
2078 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2079 // [Lock]
2080 if( os::is_MP() )
2081 emit_opcode(cbuf,0xF0);
2082
2083 // CMPXCHG [Eptr]
2084 emit_opcode(cbuf,0x0F);
2085 emit_opcode(cbuf,0xB1);
2086 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2087 %}
2088
2089 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2090 int res_encoding = $res$$reg;
2091
2092 // MOV res,0
2093 emit_opcode( cbuf, 0xB8 + res_encoding);
2094 emit_d32( cbuf, 0 );
2095 // JNE,s fail
2096 emit_opcode(cbuf,0x75);
2097 emit_d8(cbuf, 5 );
2098 // MOV res,1
2099 emit_opcode( cbuf, 0xB8 + res_encoding);
2100 emit_d32( cbuf, 1 );
2101 // fail:
2102 %}
2103
2104 enc_class set_instruction_start( ) %{
2105 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2106 %}
2107
2108 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2109 int reg_encoding = $ereg$$reg;
2110 int base = $mem$$base;
2111 int index = $mem$$index;
2112 int scale = $mem$$scale;
2113 int displace = $mem$$disp;
2114 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2115 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2116 %}
2117
2118 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2119 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2120 int base = $mem$$base;
2121 int index = $mem$$index;
2122 int scale = $mem$$scale;
2123 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2124 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2125 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2126 %}
2127
2128 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2129 int r1, r2;
2130 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2131 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2132 emit_opcode(cbuf,0x0F);
2133 emit_opcode(cbuf,$tertiary);
2134 emit_rm(cbuf, 0x3, r1, r2);
2135 emit_d8(cbuf,$cnt$$constant);
2136 emit_d8(cbuf,$primary);
2137 emit_rm(cbuf, 0x3, $secondary, r1);
2138 emit_d8(cbuf,$cnt$$constant);
2139 %}
2140
2141 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2142 emit_opcode( cbuf, 0x8B ); // Move
2143 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2144 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2145 emit_d8(cbuf,$primary);
2146 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2147 emit_d8(cbuf,$cnt$$constant-32);
2148 }
2149 emit_d8(cbuf,$primary);
2150 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2151 emit_d8(cbuf,31);
2152 %}
2153
2154 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2155 int r1, r2;
2156 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2157 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2158
2159 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2160 emit_rm(cbuf, 0x3, r1, r2);
2161 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2162 emit_opcode(cbuf,$primary);
2163 emit_rm(cbuf, 0x3, $secondary, r1);
2164 emit_d8(cbuf,$cnt$$constant-32);
2165 }
2166 emit_opcode(cbuf,0x33); // XOR r2,r2
2167 emit_rm(cbuf, 0x3, r2, r2);
2168 %}
2169
2170 // Clone of RegMem but accepts an extra parameter to access each
2171 // half of a double in memory; it never needs relocation info.
2172 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2173 emit_opcode(cbuf,$opcode$$constant);
2174 int reg_encoding = $rm_reg$$reg;
2175 int base = $mem$$base;
2176 int index = $mem$$index;
2177 int scale = $mem$$scale;
2178 int displace = $mem$$disp + $disp_for_half$$constant;
2179 relocInfo::relocType disp_reloc = relocInfo::none;
2180 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2181 %}
2182
2183 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2184 //
2185 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2186 // and it never needs relocation information.
2187 // Frequently used to move data between FPU's Stack Top and memory.
2188 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2189 int rm_byte_opcode = $rm_opcode$$constant;
2190 int base = $mem$$base;
2191 int index = $mem$$index;
2192 int scale = $mem$$scale;
2193 int displace = $mem$$disp;
2194 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2195 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2196 %}
2197
2198 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2199 int rm_byte_opcode = $rm_opcode$$constant;
2200 int base = $mem$$base;
2201 int index = $mem$$index;
2202 int scale = $mem$$scale;
2203 int displace = $mem$$disp;
2204 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2205 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2206 %}
2207
2208 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2209 int reg_encoding = $dst$$reg;
2210 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2211 int index = 0x04; // 0x04 indicates no index
2212 int scale = 0x00; // 0x00 indicates no scale
2213 int displace = $src1$$constant; // 0x00 indicates no displacement
2214 relocInfo::relocType disp_reloc = relocInfo::none;
2215 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2216 %}
2217
2218 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2219 // Compare dst,src
2220 emit_opcode(cbuf,0x3B);
2221 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2222 // jmp dst < src around move
2223 emit_opcode(cbuf,0x7C);
2224 emit_d8(cbuf,2);
2225 // move dst,src
2226 emit_opcode(cbuf,0x8B);
2227 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2228 %}
2229
2230 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2231 // Compare dst,src
2232 emit_opcode(cbuf,0x3B);
2233 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2234 // jmp dst > src around move
2235 emit_opcode(cbuf,0x7F);
2236 emit_d8(cbuf,2);
2237 // move dst,src
2238 emit_opcode(cbuf,0x8B);
2239 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2240 %}
2241
2242 enc_class enc_FPR_store(memory mem, regDPR src) %{
2243 // If src is FPR1, we can just FST to store it.
2244 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2245 int reg_encoding = 0x2; // Just store
2246 int base = $mem$$base;
2247 int index = $mem$$index;
2248 int scale = $mem$$scale;
2249 int displace = $mem$$disp;
2250 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2251 if( $src$$reg != FPR1L_enc ) {
2252 reg_encoding = 0x3; // Store & pop
2253 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2254 emit_d8( cbuf, 0xC0-1+$src$$reg );
2255 }
2256 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2257 emit_opcode(cbuf,$primary);
2258 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2259 %}
2260
2261 enc_class neg_reg(rRegI dst) %{
2262 // NEG $dst
2263 emit_opcode(cbuf,0xF7);
2264 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2265 %}
2266
2267 enc_class setLT_reg(eCXRegI dst) %{
2268 // SETLT $dst
2269 emit_opcode(cbuf,0x0F);
2270 emit_opcode(cbuf,0x9C);
2271 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2272 %}
2273
2274 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2275 int tmpReg = $tmp$$reg;
2276
2277 // SUB $p,$q
2278 emit_opcode(cbuf,0x2B);
2279 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2280 // SBB $tmp,$tmp
2281 emit_opcode(cbuf,0x1B);
2282 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2283 // AND $tmp,$y
2284 emit_opcode(cbuf,0x23);
2285 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2286 // ADD $p,$tmp
2287 emit_opcode(cbuf,0x03);
2288 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2289 %}
2290
2291 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2292 // TEST shift,32
2293 emit_opcode(cbuf,0xF7);
2294 emit_rm(cbuf, 0x3, 0, ECX_enc);
2295 emit_d32(cbuf,0x20);
2296 // JEQ,s small
2297 emit_opcode(cbuf, 0x74);
2298 emit_d8(cbuf, 0x04);
2299 // MOV $dst.hi,$dst.lo
2300 emit_opcode( cbuf, 0x8B );
2301 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2302 // CLR $dst.lo
2303 emit_opcode(cbuf, 0x33);
2304 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2305 // small:
2306 // SHLD $dst.hi,$dst.lo,$shift
2307 emit_opcode(cbuf,0x0F);
2308 emit_opcode(cbuf,0xA5);
2309 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2310 // SHL $dst.lo,$shift"
2311 emit_opcode(cbuf,0xD3);
2312 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2313 %}
2314
2315 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2316 // TEST shift,32
2317 emit_opcode(cbuf,0xF7);
2318 emit_rm(cbuf, 0x3, 0, ECX_enc);
2319 emit_d32(cbuf,0x20);
2320 // JEQ,s small
2321 emit_opcode(cbuf, 0x74);
2322 emit_d8(cbuf, 0x04);
2323 // MOV $dst.lo,$dst.hi
2324 emit_opcode( cbuf, 0x8B );
2325 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2326 // CLR $dst.hi
2327 emit_opcode(cbuf, 0x33);
2328 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2329 // small:
2330 // SHRD $dst.lo,$dst.hi,$shift
2331 emit_opcode(cbuf,0x0F);
2332 emit_opcode(cbuf,0xAD);
2333 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2334 // SHR $dst.hi,$shift"
2335 emit_opcode(cbuf,0xD3);
2336 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2337 %}
2338
2339 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2340 // TEST shift,32
2341 emit_opcode(cbuf,0xF7);
2342 emit_rm(cbuf, 0x3, 0, ECX_enc);
2343 emit_d32(cbuf,0x20);
2344 // JEQ,s small
2345 emit_opcode(cbuf, 0x74);
2346 emit_d8(cbuf, 0x05);
2347 // MOV $dst.lo,$dst.hi
2348 emit_opcode( cbuf, 0x8B );
2349 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2350 // SAR $dst.hi,31
2351 emit_opcode(cbuf, 0xC1);
2352 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2353 emit_d8(cbuf, 0x1F );
2354 // small:
2355 // SHRD $dst.lo,$dst.hi,$shift
2356 emit_opcode(cbuf,0x0F);
2357 emit_opcode(cbuf,0xAD);
2358 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2359 // SAR $dst.hi,$shift"
2360 emit_opcode(cbuf,0xD3);
2361 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2362 %}
2363
2364
2365 // ----------------- Encodings for floating point unit -----------------
2366 // May leave result in FPU-TOS or FPU reg depending on opcodes
2367 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2368 $$$emit8$primary;
2369 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2370 %}
2371
2372 // Pop argument in FPR0 with FSTP ST(0)
2373 enc_class PopFPU() %{
2374 emit_opcode( cbuf, 0xDD );
2375 emit_d8( cbuf, 0xD8 );
2376 %}
2377
2378 // !!!!! equivalent to Pop_Reg_F
2379 enc_class Pop_Reg_DPR( regDPR dst ) %{
2380 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2381 emit_d8( cbuf, 0xD8+$dst$$reg );
2382 %}
2383
2384 enc_class Push_Reg_DPR( regDPR dst ) %{
2385 emit_opcode( cbuf, 0xD9 );
2386 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2387 %}
2388
2389 enc_class strictfp_bias1( regDPR dst ) %{
2390 emit_opcode( cbuf, 0xDB ); // FLD m80real
2391 emit_opcode( cbuf, 0x2D );
2392 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2393 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2394 emit_opcode( cbuf, 0xC8+$dst$$reg );
2395 %}
2396
2397 enc_class strictfp_bias2( regDPR dst ) %{
2398 emit_opcode( cbuf, 0xDB ); // FLD m80real
2399 emit_opcode( cbuf, 0x2D );
2400 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2401 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2402 emit_opcode( cbuf, 0xC8+$dst$$reg );
2403 %}
2404
2405 // Special case for moving an integer register to a stack slot.
2406 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2407 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2408 %}
2409
2410 // Special case for moving a register to a stack slot.
2411 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2412 // Opcode already emitted
2413 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2414 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2415 emit_d32(cbuf, $dst$$disp); // Displacement
2416 %}
2417
2418 // Push the integer in stackSlot 'src' onto FP-stack
2419 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2420 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2421 %}
2422
2423 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2424 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2425 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2426 %}
2427
2428 // Same as Pop_Mem_F except for opcode
2429 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2430 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2431 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2432 %}
2433
2434 enc_class Pop_Reg_FPR( regFPR dst ) %{
2435 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2436 emit_d8( cbuf, 0xD8+$dst$$reg );
2437 %}
2438
2439 enc_class Push_Reg_FPR( regFPR dst ) %{
2440 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2441 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2442 %}
2443
2444 // Push FPU's float to a stack-slot, and pop FPU-stack
2445 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2446 int pop = 0x02;
2447 if ($src$$reg != FPR1L_enc) {
2448 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2449 emit_d8( cbuf, 0xC0-1+$src$$reg );
2450 pop = 0x03;
2451 }
2452 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2453 %}
2454
2455 // Push FPU's double to a stack-slot, and pop FPU-stack
2456 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2457 int pop = 0x02;
2458 if ($src$$reg != FPR1L_enc) {
2459 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2460 emit_d8( cbuf, 0xC0-1+$src$$reg );
2461 pop = 0x03;
2462 }
2463 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2464 %}
2465
2466 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2467 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2468 int pop = 0xD0 - 1; // -1 since we skip FLD
2469 if ($src$$reg != FPR1L_enc) {
2470 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2471 emit_d8( cbuf, 0xC0-1+$src$$reg );
2472 pop = 0xD8;
2473 }
2474 emit_opcode( cbuf, 0xDD );
2475 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2476 %}
2477
2478
2479 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2480 // load dst in FPR0
2481 emit_opcode( cbuf, 0xD9 );
2482 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2483 if ($src$$reg != FPR1L_enc) {
2484 // fincstp
2485 emit_opcode (cbuf, 0xD9);
2486 emit_opcode (cbuf, 0xF7);
2487 // swap src with FPR1:
2488 // FXCH FPR1 with src
2489 emit_opcode(cbuf, 0xD9);
2490 emit_d8(cbuf, 0xC8-1+$src$$reg );
2491 // fdecstp
2492 emit_opcode (cbuf, 0xD9);
2493 emit_opcode (cbuf, 0xF6);
2494 }
2495 %}
2496
2497 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2498 MacroAssembler _masm(&cbuf);
2499 __ subptr(rsp, 8);
2500 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2501 __ fld_d(Address(rsp, 0));
2502 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2503 __ fld_d(Address(rsp, 0));
2504 %}
2505
2506 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2507 MacroAssembler _masm(&cbuf);
2508 __ subptr(rsp, 4);
2509 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2510 __ fld_s(Address(rsp, 0));
2511 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2512 __ fld_s(Address(rsp, 0));
2513 %}
2514
2515 enc_class Push_ResultD(regD dst) %{
2516 MacroAssembler _masm(&cbuf);
2517 __ fstp_d(Address(rsp, 0));
2518 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2519 __ addptr(rsp, 8);
2520 %}
2521
2522 enc_class Push_ResultF(regF dst, immI d8) %{
2523 MacroAssembler _masm(&cbuf);
2524 __ fstp_s(Address(rsp, 0));
2525 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2526 __ addptr(rsp, $d8$$constant);
2527 %}
2528
2529 enc_class Push_SrcD(regD src) %{
2530 MacroAssembler _masm(&cbuf);
2531 __ subptr(rsp, 8);
2532 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2533 __ fld_d(Address(rsp, 0));
2534 %}
2535
2536 enc_class push_stack_temp_qword() %{
2537 MacroAssembler _masm(&cbuf);
2538 __ subptr(rsp, 8);
2539 %}
2540
2541 enc_class pop_stack_temp_qword() %{
2542 MacroAssembler _masm(&cbuf);
2543 __ addptr(rsp, 8);
2544 %}
2545
2546 enc_class push_xmm_to_fpr1(regD src) %{
2547 MacroAssembler _masm(&cbuf);
2548 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2549 __ fld_d(Address(rsp, 0));
2550 %}
2551
2552 enc_class Push_Result_Mod_DPR( regDPR src) %{
2553 if ($src$$reg != FPR1L_enc) {
2554 // fincstp
2555 emit_opcode (cbuf, 0xD9);
2556 emit_opcode (cbuf, 0xF7);
2557 // FXCH FPR1 with src
2558 emit_opcode(cbuf, 0xD9);
2559 emit_d8(cbuf, 0xC8-1+$src$$reg );
2560 // fdecstp
2561 emit_opcode (cbuf, 0xD9);
2562 emit_opcode (cbuf, 0xF6);
2563 }
2564 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2565 // // FSTP FPR$dst$$reg
2566 // emit_opcode( cbuf, 0xDD );
2567 // emit_d8( cbuf, 0xD8+$dst$$reg );
2568 %}
2569
2570 enc_class fnstsw_sahf_skip_parity() %{
2571 // fnstsw ax
2572 emit_opcode( cbuf, 0xDF );
2573 emit_opcode( cbuf, 0xE0 );
2574 // sahf
2575 emit_opcode( cbuf, 0x9E );
2576 // jnp ::skip
2577 emit_opcode( cbuf, 0x7B );
2578 emit_opcode( cbuf, 0x05 );
2579 %}
2580
2581 enc_class emitModDPR() %{
2582 // fprem must be iterative
2583 // :: loop
2584 // fprem
2585 emit_opcode( cbuf, 0xD9 );
2586 emit_opcode( cbuf, 0xF8 );
2587 // wait
2588 emit_opcode( cbuf, 0x9b );
2589 // fnstsw ax
2590 emit_opcode( cbuf, 0xDF );
2591 emit_opcode( cbuf, 0xE0 );
2592 // sahf
2593 emit_opcode( cbuf, 0x9E );
2594 // jp ::loop
2595 emit_opcode( cbuf, 0x0F );
2596 emit_opcode( cbuf, 0x8A );
2597 emit_opcode( cbuf, 0xF4 );
2598 emit_opcode( cbuf, 0xFF );
2599 emit_opcode( cbuf, 0xFF );
2600 emit_opcode( cbuf, 0xFF );
2601 %}
2602
2603 enc_class fpu_flags() %{
2604 // fnstsw_ax
2605 emit_opcode( cbuf, 0xDF);
2606 emit_opcode( cbuf, 0xE0);
2607 // test ax,0x0400
2608 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2609 emit_opcode( cbuf, 0xA9 );
2610 emit_d16 ( cbuf, 0x0400 );
2611 // // // This sequence works, but stalls for 12-16 cycles on PPro
2612 // // test rax,0x0400
2613 // emit_opcode( cbuf, 0xA9 );
2614 // emit_d32 ( cbuf, 0x00000400 );
2615 //
2616 // jz exit (no unordered comparison)
2617 emit_opcode( cbuf, 0x74 );
2618 emit_d8 ( cbuf, 0x02 );
2619 // mov ah,1 - treat as LT case (set carry flag)
2620 emit_opcode( cbuf, 0xB4 );
2621 emit_d8 ( cbuf, 0x01 );
2622 // sahf
2623 emit_opcode( cbuf, 0x9E);
2624 %}
2625
2626 enc_class cmpF_P6_fixup() %{
2627 // Fixup the integer flags in case comparison involved a NaN
2628 //
2629 // JNP exit (no unordered comparison, P-flag is set by NaN)
2630 emit_opcode( cbuf, 0x7B );
2631 emit_d8 ( cbuf, 0x03 );
2632 // MOV AH,1 - treat as LT case (set carry flag)
2633 emit_opcode( cbuf, 0xB4 );
2634 emit_d8 ( cbuf, 0x01 );
2635 // SAHF
2636 emit_opcode( cbuf, 0x9E);
2637 // NOP // target for branch to avoid branch to branch
2638 emit_opcode( cbuf, 0x90);
2639 %}
2640
2641 // fnstsw_ax();
2642 // sahf();
2643 // movl(dst, nan_result);
2644 // jcc(Assembler::parity, exit);
2645 // movl(dst, less_result);
2646 // jcc(Assembler::below, exit);
2647 // movl(dst, equal_result);
2648 // jcc(Assembler::equal, exit);
2649 // movl(dst, greater_result);
2650
2651 // less_result = 1;
2652 // greater_result = -1;
2653 // equal_result = 0;
2654 // nan_result = -1;
2655
2656 enc_class CmpF_Result(rRegI dst) %{
2657 // fnstsw_ax();
2658 emit_opcode( cbuf, 0xDF);
2659 emit_opcode( cbuf, 0xE0);
2660 // sahf
2661 emit_opcode( cbuf, 0x9E);
2662 // movl(dst, nan_result);
2663 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2664 emit_d32( cbuf, -1 );
2665 // jcc(Assembler::parity, exit);
2666 emit_opcode( cbuf, 0x7A );
2667 emit_d8 ( cbuf, 0x13 );
2668 // movl(dst, less_result);
2669 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2670 emit_d32( cbuf, -1 );
2671 // jcc(Assembler::below, exit);
2672 emit_opcode( cbuf, 0x72 );
2673 emit_d8 ( cbuf, 0x0C );
2674 // movl(dst, equal_result);
2675 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2676 emit_d32( cbuf, 0 );
2677 // jcc(Assembler::equal, exit);
2678 emit_opcode( cbuf, 0x74 );
2679 emit_d8 ( cbuf, 0x05 );
2680 // movl(dst, greater_result);
2681 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2682 emit_d32( cbuf, 1 );
2683 %}
2684
2685
2686 // Compare the longs and set flags
2687 // BROKEN! Do Not use as-is
2688 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2689 // CMP $src1.hi,$src2.hi
2690 emit_opcode( cbuf, 0x3B );
2691 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2692 // JNE,s done
2693 emit_opcode(cbuf,0x75);
2694 emit_d8(cbuf, 2 );
2695 // CMP $src1.lo,$src2.lo
2696 emit_opcode( cbuf, 0x3B );
2697 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2698 // done:
2699 %}
2700
2701 enc_class convert_int_long( regL dst, rRegI src ) %{
2702 // mov $dst.lo,$src
2703 int dst_encoding = $dst$$reg;
2704 int src_encoding = $src$$reg;
2705 encode_Copy( cbuf, dst_encoding , src_encoding );
2706 // mov $dst.hi,$src
2707 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2708 // sar $dst.hi,31
2709 emit_opcode( cbuf, 0xC1 );
2710 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2711 emit_d8(cbuf, 0x1F );
2712 %}
2713
2714 enc_class convert_long_double( eRegL src ) %{
2715 // push $src.hi
2716 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2717 // push $src.lo
2718 emit_opcode(cbuf, 0x50+$src$$reg );
2719 // fild 64-bits at [SP]
2720 emit_opcode(cbuf,0xdf);
2721 emit_d8(cbuf, 0x6C);
2722 emit_d8(cbuf, 0x24);
2723 emit_d8(cbuf, 0x00);
2724 // pop stack
2725 emit_opcode(cbuf, 0x83); // add SP, #8
2726 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2727 emit_d8(cbuf, 0x8);
2728 %}
2729
2730 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2731 // IMUL EDX:EAX,$src1
2732 emit_opcode( cbuf, 0xF7 );
2733 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2734 // SAR EDX,$cnt-32
2735 int shift_count = ((int)$cnt$$constant) - 32;
2736 if (shift_count > 0) {
2737 emit_opcode(cbuf, 0xC1);
2738 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2739 emit_d8(cbuf, shift_count);
2740 }
2741 %}
2742
2743 // this version doesn't have add sp, 8
2744 enc_class convert_long_double2( eRegL src ) %{
2745 // push $src.hi
2746 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2747 // push $src.lo
2748 emit_opcode(cbuf, 0x50+$src$$reg );
2749 // fild 64-bits at [SP]
2750 emit_opcode(cbuf,0xdf);
2751 emit_d8(cbuf, 0x6C);
2752 emit_d8(cbuf, 0x24);
2753 emit_d8(cbuf, 0x00);
2754 %}
2755
2756 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2757 // Basic idea: long = (long)int * (long)int
2758 // IMUL EDX:EAX, src
2759 emit_opcode( cbuf, 0xF7 );
2760 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2761 %}
2762
2763 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2764 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2765 // MUL EDX:EAX, src
2766 emit_opcode( cbuf, 0xF7 );
2767 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2768 %}
2769
2770 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2771 // Basic idea: lo(result) = lo(x_lo * y_lo)
2772 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2773 // MOV $tmp,$src.lo
2774 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2775 // IMUL $tmp,EDX
2776 emit_opcode( cbuf, 0x0F );
2777 emit_opcode( cbuf, 0xAF );
2778 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2779 // MOV EDX,$src.hi
2780 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2781 // IMUL EDX,EAX
2782 emit_opcode( cbuf, 0x0F );
2783 emit_opcode( cbuf, 0xAF );
2784 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2785 // ADD $tmp,EDX
2786 emit_opcode( cbuf, 0x03 );
2787 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2788 // MUL EDX:EAX,$src.lo
2789 emit_opcode( cbuf, 0xF7 );
2790 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2791 // ADD EDX,ESI
2792 emit_opcode( cbuf, 0x03 );
2793 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2794 %}
2795
2796 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2797 // Basic idea: lo(result) = lo(src * y_lo)
2798 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2799 // IMUL $tmp,EDX,$src
2800 emit_opcode( cbuf, 0x6B );
2801 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2802 emit_d8( cbuf, (int)$src$$constant );
2803 // MOV EDX,$src
2804 emit_opcode(cbuf, 0xB8 + EDX_enc);
2805 emit_d32( cbuf, (int)$src$$constant );
2806 // MUL EDX:EAX,EDX
2807 emit_opcode( cbuf, 0xF7 );
2808 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2809 // ADD EDX,ESI
2810 emit_opcode( cbuf, 0x03 );
2811 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2812 %}
2813
2814 enc_class long_div( eRegL src1, eRegL src2 ) %{
2815 // PUSH src1.hi
2816 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2817 // PUSH src1.lo
2818 emit_opcode(cbuf, 0x50+$src1$$reg );
2819 // PUSH src2.hi
2820 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2821 // PUSH src2.lo
2822 emit_opcode(cbuf, 0x50+$src2$$reg );
2823 // CALL directly to the runtime
2824 cbuf.set_insts_mark();
2825 emit_opcode(cbuf,0xE8); // Call into runtime
2826 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2827 // Restore stack
2828 emit_opcode(cbuf, 0x83); // add SP, #framesize
2829 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2830 emit_d8(cbuf, 4*4);
2831 %}
2832
2833 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2834 // PUSH src1.hi
2835 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2836 // PUSH src1.lo
2837 emit_opcode(cbuf, 0x50+$src1$$reg );
2838 // PUSH src2.hi
2839 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2840 // PUSH src2.lo
2841 emit_opcode(cbuf, 0x50+$src2$$reg );
2842 // CALL directly to the runtime
2843 cbuf.set_insts_mark();
2844 emit_opcode(cbuf,0xE8); // Call into runtime
2845 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2846 // Restore stack
2847 emit_opcode(cbuf, 0x83); // add SP, #framesize
2848 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2849 emit_d8(cbuf, 4*4);
2850 %}
2851
2852 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2853 // MOV $tmp,$src.lo
2854 emit_opcode(cbuf, 0x8B);
2855 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2856 // OR $tmp,$src.hi
2857 emit_opcode(cbuf, 0x0B);
2858 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2859 %}
2860
2861 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2862 // CMP $src1.lo,$src2.lo
2863 emit_opcode( cbuf, 0x3B );
2864 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2865 // JNE,s skip
2866 emit_cc(cbuf, 0x70, 0x5);
2867 emit_d8(cbuf,2);
2868 // CMP $src1.hi,$src2.hi
2869 emit_opcode( cbuf, 0x3B );
2870 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2871 %}
2872
2873 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2874 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2875 emit_opcode( cbuf, 0x3B );
2876 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2877 // MOV $tmp,$src1.hi
2878 emit_opcode( cbuf, 0x8B );
2879 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2880 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2881 emit_opcode( cbuf, 0x1B );
2882 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2883 %}
2884
2885 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2886 // XOR $tmp,$tmp
2887 emit_opcode(cbuf,0x33); // XOR
2888 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2889 // CMP $tmp,$src.lo
2890 emit_opcode( cbuf, 0x3B );
2891 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2892 // SBB $tmp,$src.hi
2893 emit_opcode( cbuf, 0x1B );
2894 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2895 %}
2896
2897 // Sniff, sniff... smells like Gnu Superoptimizer
2898 enc_class neg_long( eRegL dst ) %{
2899 emit_opcode(cbuf,0xF7); // NEG hi
2900 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2901 emit_opcode(cbuf,0xF7); // NEG lo
2902 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2903 emit_opcode(cbuf,0x83); // SBB hi,0
2904 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2905 emit_d8 (cbuf,0 );
2906 %}
2907
2908 enc_class enc_pop_rdx() %{
2909 emit_opcode(cbuf,0x5A);
2910 %}
2911
2912 enc_class enc_rethrow() %{
2913 cbuf.set_insts_mark();
2914 emit_opcode(cbuf, 0xE9); // jmp entry
2915 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
2916 runtime_call_Relocation::spec(), RELOC_IMM32 );
2917 %}
2918
2919
2920 // Convert a double to an int. Java semantics require we do complex
2921 // manglelations in the corner cases. So we set the rounding mode to
2922 // 'zero', store the darned double down as an int, and reset the
2923 // rounding mode to 'nearest'. The hardware throws an exception which
2924 // patches up the correct value directly to the stack.
2925 enc_class DPR2I_encoding( regDPR src ) %{
2926 // Flip to round-to-zero mode. We attempted to allow invalid-op
2927 // exceptions here, so that a NAN or other corner-case value will
2928 // thrown an exception (but normal values get converted at full speed).
2929 // However, I2C adapters and other float-stack manglers leave pending
2930 // invalid-op exceptions hanging. We would have to clear them before
2931 // enabling them and that is more expensive than just testing for the
2932 // invalid value Intel stores down in the corner cases.
2933 emit_opcode(cbuf,0xD9); // FLDCW trunc
2934 emit_opcode(cbuf,0x2D);
2935 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2936 // Allocate a word
2937 emit_opcode(cbuf,0x83); // SUB ESP,4
2938 emit_opcode(cbuf,0xEC);
2939 emit_d8(cbuf,0x04);
2940 // Encoding assumes a double has been pushed into FPR0.
2941 // Store down the double as an int, popping the FPU stack
2942 emit_opcode(cbuf,0xDB); // FISTP [ESP]
2943 emit_opcode(cbuf,0x1C);
2944 emit_d8(cbuf,0x24);
2945 // Restore the rounding mode; mask the exception
2946 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2947 emit_opcode(cbuf,0x2D);
2948 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2949 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2950 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2951
2952 // Load the converted int; adjust CPU stack
2953 emit_opcode(cbuf,0x58); // POP EAX
2954 emit_opcode(cbuf,0x3D); // CMP EAX,imm
2955 emit_d32 (cbuf,0x80000000); // 0x80000000
2956 emit_opcode(cbuf,0x75); // JNE around_slow_call
2957 emit_d8 (cbuf,0x07); // Size of slow_call
2958 // Push src onto stack slow-path
2959 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
2960 emit_d8 (cbuf,0xC0-1+$src$$reg );
2961 // CALL directly to the runtime
2962 cbuf.set_insts_mark();
2963 emit_opcode(cbuf,0xE8); // Call into runtime
2964 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2965 // Carry on here...
2966 %}
2967
2968 enc_class DPR2L_encoding( regDPR src ) %{
2969 emit_opcode(cbuf,0xD9); // FLDCW trunc
2970 emit_opcode(cbuf,0x2D);
2971 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2972 // Allocate a word
2973 emit_opcode(cbuf,0x83); // SUB ESP,8
2974 emit_opcode(cbuf,0xEC);
2975 emit_d8(cbuf,0x08);
2976 // Encoding assumes a double has been pushed into FPR0.
2977 // Store down the double as a long, popping the FPU stack
2978 emit_opcode(cbuf,0xDF); // FISTP [ESP]
2979 emit_opcode(cbuf,0x3C);
2980 emit_d8(cbuf,0x24);
2981 // Restore the rounding mode; mask the exception
2982 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2983 emit_opcode(cbuf,0x2D);
2984 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2985 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2986 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2987
2988 // Load the converted int; adjust CPU stack
2989 emit_opcode(cbuf,0x58); // POP EAX
2990 emit_opcode(cbuf,0x5A); // POP EDX
2991 emit_opcode(cbuf,0x81); // CMP EDX,imm
2992 emit_d8 (cbuf,0xFA); // rdx
2993 emit_d32 (cbuf,0x80000000); // 0x80000000
2994 emit_opcode(cbuf,0x75); // JNE around_slow_call
2995 emit_d8 (cbuf,0x07+4); // Size of slow_call
2996 emit_opcode(cbuf,0x85); // TEST EAX,EAX
2997 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
2998 emit_opcode(cbuf,0x75); // JNE around_slow_call
2999 emit_d8 (cbuf,0x07); // Size of slow_call
3000 // Push src onto stack slow-path
3001 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3002 emit_d8 (cbuf,0xC0-1+$src$$reg );
3003 // CALL directly to the runtime
3004 cbuf.set_insts_mark();
3005 emit_opcode(cbuf,0xE8); // Call into runtime
3006 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3007 // Carry on here...
3008 %}
3009
3010 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3011 // Operand was loaded from memory into fp ST (stack top)
3012 // FMUL ST,$src /* D8 C8+i */
3013 emit_opcode(cbuf, 0xD8);
3014 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3015 %}
3016
3017 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3018 // FADDP ST,src2 /* D8 C0+i */
3019 emit_opcode(cbuf, 0xD8);
3020 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3021 //could use FADDP src2,fpST /* DE C0+i */
3022 %}
3023
3024 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3025 // FADDP src2,ST /* DE C0+i */
3026 emit_opcode(cbuf, 0xDE);
3027 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3028 %}
3029
3030 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3031 // Operand has been loaded into fp ST (stack top)
3032 // FSUB ST,$src1
3033 emit_opcode(cbuf, 0xD8);
3034 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3035
3036 // FDIV
3037 emit_opcode(cbuf, 0xD8);
3038 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3039 %}
3040
3041 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3042 // Operand was loaded from memory into fp ST (stack top)
3043 // FADD ST,$src /* D8 C0+i */
3044 emit_opcode(cbuf, 0xD8);
3045 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3046
3047 // FMUL ST,src2 /* D8 C*+i */
3048 emit_opcode(cbuf, 0xD8);
3049 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3050 %}
3051
3052
3053 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3054 // Operand was loaded from memory into fp ST (stack top)
3055 // FADD ST,$src /* D8 C0+i */
3056 emit_opcode(cbuf, 0xD8);
3057 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3058
3059 // FMULP src2,ST /* DE C8+i */
3060 emit_opcode(cbuf, 0xDE);
3061 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3062 %}
3063
3064 // Atomically load the volatile long
3065 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3066 emit_opcode(cbuf,0xDF);
3067 int rm_byte_opcode = 0x05;
3068 int base = $mem$$base;
3069 int index = $mem$$index;
3070 int scale = $mem$$scale;
3071 int displace = $mem$$disp;
3072 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3073 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3074 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3075 %}
3076
3077 // Volatile Store Long. Must be atomic, so move it into
3078 // the FP TOS and then do a 64-bit FIST. Has to probe the
3079 // target address before the store (for null-ptr checks)
3080 // so the memory operand is used twice in the encoding.
3081 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3082 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3083 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3084 emit_opcode(cbuf,0xDF);
3085 int rm_byte_opcode = 0x07;
3086 int base = $mem$$base;
3087 int index = $mem$$index;
3088 int scale = $mem$$scale;
3089 int displace = $mem$$disp;
3090 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3091 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3092 %}
3093
3094 // Safepoint Poll. This polls the safepoint page, and causes an
3095 // exception if it is not readable. Unfortunately, it kills the condition code
3096 // in the process
3097 // We current use TESTL [spp],EDI
3098 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3099
3100 enc_class Safepoint_Poll() %{
3101 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3102 emit_opcode(cbuf,0x85);
3103 emit_rm (cbuf, 0x0, 0x7, 0x5);
3104 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3105 %}
3106 %}
3107
3108
3109 //----------FRAME--------------------------------------------------------------
3110 // Definition of frame structure and management information.
3111 //
3112 // S T A C K L A Y O U T Allocators stack-slot number
3113 // | (to get allocators register number
3114 // G Owned by | | v add OptoReg::stack0())
3115 // r CALLER | |
3116 // o | +--------+ pad to even-align allocators stack-slot
3117 // w V | pad0 | numbers; owned by CALLER
3118 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3119 // h ^ | in | 5
3120 // | | args | 4 Holes in incoming args owned by SELF
3121 // | | | | 3
3122 // | | +--------+
3123 // V | | old out| Empty on Intel, window on Sparc
3124 // | old |preserve| Must be even aligned.
3125 // | SP-+--------+----> Matcher::_old_SP, even aligned
3126 // | | in | 3 area for Intel ret address
3127 // Owned by |preserve| Empty on Sparc.
3128 // SELF +--------+
3129 // | | pad2 | 2 pad to align old SP
3130 // | +--------+ 1
3131 // | | locks | 0
3132 // | +--------+----> OptoReg::stack0(), even aligned
3133 // | | pad1 | 11 pad to align new SP
3134 // | +--------+
3135 // | | | 10
3136 // | | spills | 9 spills
3137 // V | | 8 (pad0 slot for callee)
3138 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3139 // ^ | out | 7
3140 // | | args | 6 Holes in outgoing args owned by CALLEE
3141 // Owned by +--------+
3142 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3143 // | new |preserve| Must be even-aligned.
3144 // | SP-+--------+----> Matcher::_new_SP, even aligned
3145 // | | |
3146 //
3147 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3148 // known from SELF's arguments and the Java calling convention.
3149 // Region 6-7 is determined per call site.
3150 // Note 2: If the calling convention leaves holes in the incoming argument
3151 // area, those holes are owned by SELF. Holes in the outgoing area
3152 // are owned by the CALLEE. Holes should not be nessecary in the
3153 // incoming area, as the Java calling convention is completely under
3154 // the control of the AD file. Doubles can be sorted and packed to
3155 // avoid holes. Holes in the outgoing arguments may be nessecary for
3156 // varargs C calling conventions.
3157 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3158 // even aligned with pad0 as needed.
3159 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3160 // region 6-11 is even aligned; it may be padded out more so that
3161 // the region from SP to FP meets the minimum stack alignment.
3162
3163 frame %{
3164 // What direction does stack grow in (assumed to be same for C & Java)
3165 stack_direction(TOWARDS_LOW);
3166
3167 // These three registers define part of the calling convention
3168 // between compiled code and the interpreter.
3169 inline_cache_reg(EAX); // Inline Cache Register
3170 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3171
3172 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3173 cisc_spilling_operand_name(indOffset32);
3174
3175 // Number of stack slots consumed by locking an object
3176 sync_stack_slots(1);
3177
3178 // Compiled code's Frame Pointer
3179 frame_pointer(ESP);
3180 // Interpreter stores its frame pointer in a register which is
3181 // stored to the stack by I2CAdaptors.
3182 // I2CAdaptors convert from interpreted java to compiled java.
3183 interpreter_frame_pointer(EBP);
3184
3185 // Stack alignment requirement
3186 // Alignment size in bytes (128-bit -> 16 bytes)
3187 stack_alignment(StackAlignmentInBytes);
3188
3189 // Number of stack slots between incoming argument block and the start of
3190 // a new frame. The PROLOG must add this many slots to the stack. The
3191 // EPILOG must remove this many slots. Intel needs one slot for
3192 // return address and one for rbp, (must save rbp)
3193 in_preserve_stack_slots(2+VerifyStackAtCalls);
3194
3195 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3196 // for calls to C. Supports the var-args backing area for register parms.
3197 varargs_C_out_slots_killed(0);
3198
3199 // The after-PROLOG location of the return address. Location of
3200 // return address specifies a type (REG or STACK) and a number
3201 // representing the register number (i.e. - use a register name) or
3202 // stack slot.
3203 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3204 // Otherwise, it is above the locks and verification slot and alignment word
3205 return_addr(STACK - 1 +
3206 round_to((Compile::current()->in_preserve_stack_slots() +
3207 Compile::current()->fixed_slots()),
3208 stack_alignment_in_slots()));
3209
3210 // Body of function which returns an integer array locating
3211 // arguments either in registers or in stack slots. Passed an array
3212 // of ideal registers called "sig" and a "length" count. Stack-slot
3213 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3214 // arguments for a CALLEE. Incoming stack arguments are
3215 // automatically biased by the preserve_stack_slots field above.
3216 calling_convention %{
3217 // No difference between ingoing/outgoing just pass false
3218 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3219 %}
3220
3221
3222 // Body of function which returns an integer array locating
3223 // arguments either in registers or in stack slots. Passed an array
3224 // of ideal registers called "sig" and a "length" count. Stack-slot
3225 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3226 // arguments for a CALLEE. Incoming stack arguments are
3227 // automatically biased by the preserve_stack_slots field above.
3228 c_calling_convention %{
3229 // This is obviously always outgoing
3230 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3231 %}
3232
3233 // Location of C & interpreter return values
3234 c_return_value %{
3235 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3236 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3237 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3238
3239 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3240 // that C functions return float and double results in XMM0.
3241 if( ideal_reg == Op_RegD && UseSSE>=2 )
3242 return OptoRegPair(XMM0b_num,XMM0_num);
3243 if( ideal_reg == Op_RegF && UseSSE>=2 )
3244 return OptoRegPair(OptoReg::Bad,XMM0_num);
3245
3246 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3247 %}
3248
3249 // Location of return values
3250 return_value %{
3251 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3252 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3253 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3254 if( ideal_reg == Op_RegD && UseSSE>=2 )
3255 return OptoRegPair(XMM0b_num,XMM0_num);
3256 if( ideal_reg == Op_RegF && UseSSE>=1 )
3257 return OptoRegPair(OptoReg::Bad,XMM0_num);
3258 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3259 %}
3260
3261 %}
3262
3263 //----------ATTRIBUTES---------------------------------------------------------
3264 //----------Operand Attributes-------------------------------------------------
3265 op_attrib op_cost(0); // Required cost attribute
3266
3267 //----------Instruction Attributes---------------------------------------------
3268 ins_attrib ins_cost(100); // Required cost attribute
3269 ins_attrib ins_size(8); // Required size attribute (in bits)
3270 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3271 // non-matching short branch variant of some
3272 // long branch?
3273 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3274 // specifies the alignment that some part of the instruction (not
3275 // necessarily the start) requires. If > 1, a compute_padding()
3276 // function must be provided for the instruction
3277
3278 //----------OPERANDS-----------------------------------------------------------
3279 // Operand definitions must precede instruction definitions for correct parsing
3280 // in the ADLC because operands constitute user defined types which are used in
3281 // instruction definitions.
3282
3283 //----------Simple Operands----------------------------------------------------
3284 // Immediate Operands
3285 // Integer Immediate
3286 operand immI() %{
3287 match(ConI);
3288
3289 op_cost(10);
3290 format %{ %}
3291 interface(CONST_INTER);
3292 %}
3293
3294 // Constant for test vs zero
3295 operand immI0() %{
3296 predicate(n->get_int() == 0);
3297 match(ConI);
3298
3299 op_cost(0);
3300 format %{ %}
3301 interface(CONST_INTER);
3302 %}
3303
3304 // Constant for increment
3305 operand immI1() %{
3306 predicate(n->get_int() == 1);
3307 match(ConI);
3308
3309 op_cost(0);
3310 format %{ %}
3311 interface(CONST_INTER);
3312 %}
3313
3314 // Constant for decrement
3315 operand immI_M1() %{
3316 predicate(n->get_int() == -1);
3317 match(ConI);
3318
3319 op_cost(0);
3320 format %{ %}
3321 interface(CONST_INTER);
3322 %}
3323
3324 // Valid scale values for addressing modes
3325 operand immI2() %{
3326 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3327 match(ConI);
3328
3329 format %{ %}
3330 interface(CONST_INTER);
3331 %}
3332
3333 operand immI8() %{
3334 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3335 match(ConI);
3336
3337 op_cost(5);
3338 format %{ %}
3339 interface(CONST_INTER);
3340 %}
3341
3342 operand immI16() %{
3343 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3344 match(ConI);
3345
3346 op_cost(10);
3347 format %{ %}
3348 interface(CONST_INTER);
3349 %}
3350
3351 // Int Immediate non-negative
3352 operand immU31()
3353 %{
3354 predicate(n->get_int() >= 0);
3355 match(ConI);
3356
3357 op_cost(0);
3358 format %{ %}
3359 interface(CONST_INTER);
3360 %}
3361
3362 // Constant for long shifts
3363 operand immI_32() %{
3364 predicate( n->get_int() == 32 );
3365 match(ConI);
3366
3367 op_cost(0);
3368 format %{ %}
3369 interface(CONST_INTER);
3370 %}
3371
3372 operand immI_1_31() %{
3373 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3374 match(ConI);
3375
3376 op_cost(0);
3377 format %{ %}
3378 interface(CONST_INTER);
3379 %}
3380
3381 operand immI_32_63() %{
3382 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3383 match(ConI);
3384 op_cost(0);
3385
3386 format %{ %}
3387 interface(CONST_INTER);
3388 %}
3389
3390 operand immI_1() %{
3391 predicate( n->get_int() == 1 );
3392 match(ConI);
3393
3394 op_cost(0);
3395 format %{ %}
3396 interface(CONST_INTER);
3397 %}
3398
3399 operand immI_2() %{
3400 predicate( n->get_int() == 2 );
3401 match(ConI);
3402
3403 op_cost(0);
3404 format %{ %}
3405 interface(CONST_INTER);
3406 %}
3407
3408 operand immI_3() %{
3409 predicate( n->get_int() == 3 );
3410 match(ConI);
3411
3412 op_cost(0);
3413 format %{ %}
3414 interface(CONST_INTER);
3415 %}
3416
3417 // Pointer Immediate
3418 operand immP() %{
3419 match(ConP);
3420
3421 op_cost(10);
3422 format %{ %}
3423 interface(CONST_INTER);
3424 %}
3425
3426 // NULL Pointer Immediate
3427 operand immP0() %{
3428 predicate( n->get_ptr() == 0 );
3429 match(ConP);
3430 op_cost(0);
3431
3432 format %{ %}
3433 interface(CONST_INTER);
3434 %}
3435
3436 // Long Immediate
3437 operand immL() %{
3438 match(ConL);
3439
3440 op_cost(20);
3441 format %{ %}
3442 interface(CONST_INTER);
3443 %}
3444
3445 // Long Immediate zero
3446 operand immL0() %{
3447 predicate( n->get_long() == 0L );
3448 match(ConL);
3449 op_cost(0);
3450
3451 format %{ %}
3452 interface(CONST_INTER);
3453 %}
3454
3455 // Long Immediate zero
3456 operand immL_M1() %{
3457 predicate( n->get_long() == -1L );
3458 match(ConL);
3459 op_cost(0);
3460
3461 format %{ %}
3462 interface(CONST_INTER);
3463 %}
3464
3465 // Long immediate from 0 to 127.
3466 // Used for a shorter form of long mul by 10.
3467 operand immL_127() %{
3468 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3469 match(ConL);
3470 op_cost(0);
3471
3472 format %{ %}
3473 interface(CONST_INTER);
3474 %}
3475
3476 // Long Immediate: low 32-bit mask
3477 operand immL_32bits() %{
3478 predicate(n->get_long() == 0xFFFFFFFFL);
3479 match(ConL);
3480 op_cost(0);
3481
3482 format %{ %}
3483 interface(CONST_INTER);
3484 %}
3485
3486 // Long Immediate: low 32-bit mask
3487 operand immL32() %{
3488 predicate(n->get_long() == (int)(n->get_long()));
3489 match(ConL);
3490 op_cost(20);
3491
3492 format %{ %}
3493 interface(CONST_INTER);
3494 %}
3495
3496 //Double Immediate zero
3497 operand immDPR0() %{
3498 // Do additional (and counter-intuitive) test against NaN to work around VC++
3499 // bug that generates code such that NaNs compare equal to 0.0
3500 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
3501 match(ConD);
3502
3503 op_cost(5);
3504 format %{ %}
3505 interface(CONST_INTER);
3506 %}
3507
3508 // Double Immediate one
3509 operand immDPR1() %{
3510 predicate( UseSSE<=1 && n->getd() == 1.0 );
3511 match(ConD);
3512
3513 op_cost(5);
3514 format %{ %}
3515 interface(CONST_INTER);
3516 %}
3517
3518 // Double Immediate
3519 operand immDPR() %{
3520 predicate(UseSSE<=1);
3521 match(ConD);
3522
3523 op_cost(5);
3524 format %{ %}
3525 interface(CONST_INTER);
3526 %}
3527
3528 operand immD() %{
3529 predicate(UseSSE>=2);
3530 match(ConD);
3531
3532 op_cost(5);
3533 format %{ %}
3534 interface(CONST_INTER);
3535 %}
3536
3537 // Double Immediate zero
3538 operand immD0() %{
3539 // Do additional (and counter-intuitive) test against NaN to work around VC++
3540 // bug that generates code such that NaNs compare equal to 0.0 AND do not
3541 // compare equal to -0.0.
3542 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
3543 match(ConD);
3544
3545 format %{ %}
3546 interface(CONST_INTER);
3547 %}
3548
3549 // Float Immediate zero
3550 operand immFPR0() %{
3551 predicate(UseSSE == 0 && n->getf() == 0.0F);
3552 match(ConF);
3553
3554 op_cost(5);
3555 format %{ %}
3556 interface(CONST_INTER);
3557 %}
3558
3559 // Float Immediate one
3560 operand immFPR1() %{
3561 predicate(UseSSE == 0 && n->getf() == 1.0F);
3562 match(ConF);
3563
3564 op_cost(5);
3565 format %{ %}
3566 interface(CONST_INTER);
3567 %}
3568
3569 // Float Immediate
3570 operand immFPR() %{
3571 predicate( UseSSE == 0 );
3572 match(ConF);
3573
3574 op_cost(5);
3575 format %{ %}
3576 interface(CONST_INTER);
3577 %}
3578
3579 // Float Immediate
3580 operand immF() %{
3581 predicate(UseSSE >= 1);
3582 match(ConF);
3583
3584 op_cost(5);
3585 format %{ %}
3586 interface(CONST_INTER);
3587 %}
3588
3589 // Float Immediate zero. Zero and not -0.0
3590 operand immF0() %{
3591 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
3592 match(ConF);
3593
3594 op_cost(5);
3595 format %{ %}
3596 interface(CONST_INTER);
3597 %}
3598
3599 // Immediates for special shifts (sign extend)
3600
3601 // Constants for increment
3602 operand immI_16() %{
3603 predicate( n->get_int() == 16 );
3604 match(ConI);
3605
3606 format %{ %}
3607 interface(CONST_INTER);
3608 %}
3609
3610 operand immI_24() %{
3611 predicate( n->get_int() == 24 );
3612 match(ConI);
3613
3614 format %{ %}
3615 interface(CONST_INTER);
3616 %}
3617
3618 // Constant for byte-wide masking
3619 operand immI_255() %{
3620 predicate( n->get_int() == 255 );
3621 match(ConI);
3622
3623 format %{ %}
3624 interface(CONST_INTER);
3625 %}
3626
3627 // Constant for short-wide masking
3628 operand immI_65535() %{
3629 predicate(n->get_int() == 65535);
3630 match(ConI);
3631
3632 format %{ %}
3633 interface(CONST_INTER);
3634 %}
3635
3636 // Register Operands
3637 // Integer Register
3638 operand rRegI() %{
3639 constraint(ALLOC_IN_RC(int_reg));
3640 match(RegI);
3641 match(xRegI);
3642 match(eAXRegI);
3643 match(eBXRegI);
3644 match(eCXRegI);
3645 match(eDXRegI);
3646 match(eDIRegI);
3647 match(eSIRegI);
3648
3649 format %{ %}
3650 interface(REG_INTER);
3651 %}
3652
3653 // Subset of Integer Register
3654 operand xRegI(rRegI reg) %{
3655 constraint(ALLOC_IN_RC(int_x_reg));
3656 match(reg);
3657 match(eAXRegI);
3658 match(eBXRegI);
3659 match(eCXRegI);
3660 match(eDXRegI);
3661
3662 format %{ %}
3663 interface(REG_INTER);
3664 %}
3665
3666 // Special Registers
3667 operand eAXRegI(xRegI reg) %{
3668 constraint(ALLOC_IN_RC(eax_reg));
3669 match(reg);
3670 match(rRegI);
3671
3672 format %{ "EAX" %}
3673 interface(REG_INTER);
3674 %}
3675
3676 // Special Registers
3677 operand eBXRegI(xRegI reg) %{
3678 constraint(ALLOC_IN_RC(ebx_reg));
3679 match(reg);
3680 match(rRegI);
3681
3682 format %{ "EBX" %}
3683 interface(REG_INTER);
3684 %}
3685
3686 operand eCXRegI(xRegI reg) %{
3687 constraint(ALLOC_IN_RC(ecx_reg));
3688 match(reg);
3689 match(rRegI);
3690
3691 format %{ "ECX" %}
3692 interface(REG_INTER);
3693 %}
3694
3695 operand eDXRegI(xRegI reg) %{
3696 constraint(ALLOC_IN_RC(edx_reg));
3697 match(reg);
3698 match(rRegI);
3699
3700 format %{ "EDX" %}
3701 interface(REG_INTER);
3702 %}
3703
3704 operand eDIRegI(xRegI reg) %{
3705 constraint(ALLOC_IN_RC(edi_reg));
3706 match(reg);
3707 match(rRegI);
3708
3709 format %{ "EDI" %}
3710 interface(REG_INTER);
3711 %}
3712
3713 operand naxRegI() %{
3714 constraint(ALLOC_IN_RC(nax_reg));
3715 match(RegI);
3716 match(eCXRegI);
3717 match(eDXRegI);
3718 match(eSIRegI);
3719 match(eDIRegI);
3720
3721 format %{ %}
3722 interface(REG_INTER);
3723 %}
3724
3725 operand nadxRegI() %{
3726 constraint(ALLOC_IN_RC(nadx_reg));
3727 match(RegI);
3728 match(eBXRegI);
3729 match(eCXRegI);
3730 match(eSIRegI);
3731 match(eDIRegI);
3732
3733 format %{ %}
3734 interface(REG_INTER);
3735 %}
3736
3737 operand ncxRegI() %{
3738 constraint(ALLOC_IN_RC(ncx_reg));
3739 match(RegI);
3740 match(eAXRegI);
3741 match(eDXRegI);
3742 match(eSIRegI);
3743 match(eDIRegI);
3744
3745 format %{ %}
3746 interface(REG_INTER);
3747 %}
3748
3749 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
3750 // //
3751 operand eSIRegI(xRegI reg) %{
3752 constraint(ALLOC_IN_RC(esi_reg));
3753 match(reg);
3754 match(rRegI);
3755
3756 format %{ "ESI" %}
3757 interface(REG_INTER);
3758 %}
3759
3760 // Pointer Register
3761 operand anyRegP() %{
3762 constraint(ALLOC_IN_RC(any_reg));
3763 match(RegP);
3764 match(eAXRegP);
3765 match(eBXRegP);
3766 match(eCXRegP);
3767 match(eDIRegP);
3768 match(eRegP);
3769
3770 format %{ %}
3771 interface(REG_INTER);
3772 %}
3773
3774 operand eRegP() %{
3775 constraint(ALLOC_IN_RC(int_reg));
3776 match(RegP);
3777 match(eAXRegP);
3778 match(eBXRegP);
3779 match(eCXRegP);
3780 match(eDIRegP);
3781
3782 format %{ %}
3783 interface(REG_INTER);
3784 %}
3785
3786 // On windows95, EBP is not safe to use for implicit null tests.
3787 operand eRegP_no_EBP() %{
3788 constraint(ALLOC_IN_RC(int_reg_no_rbp));
3789 match(RegP);
3790 match(eAXRegP);
3791 match(eBXRegP);
3792 match(eCXRegP);
3793 match(eDIRegP);
3794
3795 op_cost(100);
3796 format %{ %}
3797 interface(REG_INTER);
3798 %}
3799
3800 operand naxRegP() %{
3801 constraint(ALLOC_IN_RC(nax_reg));
3802 match(RegP);
3803 match(eBXRegP);
3804 match(eDXRegP);
3805 match(eCXRegP);
3806 match(eSIRegP);
3807 match(eDIRegP);
3808
3809 format %{ %}
3810 interface(REG_INTER);
3811 %}
3812
3813 operand nabxRegP() %{
3814 constraint(ALLOC_IN_RC(nabx_reg));
3815 match(RegP);
3816 match(eCXRegP);
3817 match(eDXRegP);
3818 match(eSIRegP);
3819 match(eDIRegP);
3820
3821 format %{ %}
3822 interface(REG_INTER);
3823 %}
3824
3825 operand pRegP() %{
3826 constraint(ALLOC_IN_RC(p_reg));
3827 match(RegP);
3828 match(eBXRegP);
3829 match(eDXRegP);
3830 match(eSIRegP);
3831 match(eDIRegP);
3832
3833 format %{ %}
3834 interface(REG_INTER);
3835 %}
3836
3837 // Special Registers
3838 // Return a pointer value
3839 operand eAXRegP(eRegP reg) %{
3840 constraint(ALLOC_IN_RC(eax_reg));
3841 match(reg);
3842 format %{ "EAX" %}
3843 interface(REG_INTER);
3844 %}
3845
3846 // Used in AtomicAdd
3847 operand eBXRegP(eRegP reg) %{
3848 constraint(ALLOC_IN_RC(ebx_reg));
3849 match(reg);
3850 format %{ "EBX" %}
3851 interface(REG_INTER);
3852 %}
3853
3854 // Tail-call (interprocedural jump) to interpreter
3855 operand eCXRegP(eRegP reg) %{
3856 constraint(ALLOC_IN_RC(ecx_reg));
3857 match(reg);
3858 format %{ "ECX" %}
3859 interface(REG_INTER);
3860 %}
3861
3862 operand eSIRegP(eRegP reg) %{
3863 constraint(ALLOC_IN_RC(esi_reg));
3864 match(reg);
3865 format %{ "ESI" %}
3866 interface(REG_INTER);
3867 %}
3868
3869 // Used in rep stosw
3870 operand eDIRegP(eRegP reg) %{
3871 constraint(ALLOC_IN_RC(edi_reg));
3872 match(reg);
3873 format %{ "EDI" %}
3874 interface(REG_INTER);
3875 %}
3876
3877 operand eBPRegP() %{
3878 constraint(ALLOC_IN_RC(ebp_reg));
3879 match(RegP);
3880 format %{ "EBP" %}
3881 interface(REG_INTER);
3882 %}
3883
3884 operand eRegL() %{
3885 constraint(ALLOC_IN_RC(long_reg));
3886 match(RegL);
3887 match(eADXRegL);
3888
3889 format %{ %}
3890 interface(REG_INTER);
3891 %}
3892
3893 operand eADXRegL( eRegL reg ) %{
3894 constraint(ALLOC_IN_RC(eadx_reg));
3895 match(reg);
3896
3897 format %{ "EDX:EAX" %}
3898 interface(REG_INTER);
3899 %}
3900
3901 operand eBCXRegL( eRegL reg ) %{
3902 constraint(ALLOC_IN_RC(ebcx_reg));
3903 match(reg);
3904
3905 format %{ "EBX:ECX" %}
3906 interface(REG_INTER);
3907 %}
3908
3909 // Special case for integer high multiply
3910 operand eADXRegL_low_only() %{
3911 constraint(ALLOC_IN_RC(eadx_reg));
3912 match(RegL);
3913
3914 format %{ "EAX" %}
3915 interface(REG_INTER);
3916 %}
3917
3918 // Flags register, used as output of compare instructions
3919 operand eFlagsReg() %{
3920 constraint(ALLOC_IN_RC(int_flags));
3921 match(RegFlags);
3922
3923 format %{ "EFLAGS" %}
3924 interface(REG_INTER);
3925 %}
3926
3927 // Flags register, used as output of FLOATING POINT compare instructions
3928 operand eFlagsRegU() %{
3929 constraint(ALLOC_IN_RC(int_flags));
3930 match(RegFlags);
3931
3932 format %{ "EFLAGS_U" %}
3933 interface(REG_INTER);
3934 %}
3935
3936 operand eFlagsRegUCF() %{
3937 constraint(ALLOC_IN_RC(int_flags));
3938 match(RegFlags);
3939 predicate(false);
3940
3941 format %{ "EFLAGS_U_CF" %}
3942 interface(REG_INTER);
3943 %}
3944
3945 // Condition Code Register used by long compare
3946 operand flagsReg_long_LTGE() %{
3947 constraint(ALLOC_IN_RC(int_flags));
3948 match(RegFlags);
3949 format %{ "FLAGS_LTGE" %}
3950 interface(REG_INTER);
3951 %}
3952 operand flagsReg_long_EQNE() %{
3953 constraint(ALLOC_IN_RC(int_flags));
3954 match(RegFlags);
3955 format %{ "FLAGS_EQNE" %}
3956 interface(REG_INTER);
3957 %}
3958 operand flagsReg_long_LEGT() %{
3959 constraint(ALLOC_IN_RC(int_flags));
3960 match(RegFlags);
3961 format %{ "FLAGS_LEGT" %}
3962 interface(REG_INTER);
3963 %}
3964
3965 // Float register operands
3966 operand regDPR() %{
3967 predicate( UseSSE < 2 );
3968 constraint(ALLOC_IN_RC(fp_dbl_reg));
3969 match(RegD);
3970 match(regDPR1);
3971 match(regDPR2);
3972 format %{ %}
3973 interface(REG_INTER);
3974 %}
3975
3976 operand regDPR1(regDPR reg) %{
3977 predicate( UseSSE < 2 );
3978 constraint(ALLOC_IN_RC(fp_dbl_reg0));
3979 match(reg);
3980 format %{ "FPR1" %}
3981 interface(REG_INTER);
3982 %}
3983
3984 operand regDPR2(regDPR reg) %{
3985 predicate( UseSSE < 2 );
3986 constraint(ALLOC_IN_RC(fp_dbl_reg1));
3987 match(reg);
3988 format %{ "FPR2" %}
3989 interface(REG_INTER);
3990 %}
3991
3992 operand regnotDPR1(regDPR reg) %{
3993 predicate( UseSSE < 2 );
3994 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
3995 match(reg);
3996 format %{ %}
3997 interface(REG_INTER);
3998 %}
3999
4000 // Float register operands
4001 operand regFPR() %{
4002 predicate( UseSSE < 2 );
4003 constraint(ALLOC_IN_RC(fp_flt_reg));
4004 match(RegF);
4005 match(regFPR1);
4006 format %{ %}
4007 interface(REG_INTER);
4008 %}
4009
4010 // Float register operands
4011 operand regFPR1(regFPR reg) %{
4012 predicate( UseSSE < 2 );
4013 constraint(ALLOC_IN_RC(fp_flt_reg0));
4014 match(reg);
4015 format %{ "FPR1" %}
4016 interface(REG_INTER);
4017 %}
4018
4019 // XMM Float register operands
4020 operand regF() %{
4021 predicate( UseSSE>=1 );
4022 constraint(ALLOC_IN_RC(float_reg));
4023 match(RegF);
4024 format %{ %}
4025 interface(REG_INTER);
4026 %}
4027
4028 // XMM Double register operands
4029 operand regD() %{
4030 predicate( UseSSE>=2 );
4031 constraint(ALLOC_IN_RC(double_reg));
4032 match(RegD);
4033 format %{ %}
4034 interface(REG_INTER);
4035 %}
4036
4037
4038 //----------Memory Operands----------------------------------------------------
4039 // Direct Memory Operand
4040 operand direct(immP addr) %{
4041 match(addr);
4042
4043 format %{ "[$addr]" %}
4044 interface(MEMORY_INTER) %{
4045 base(0xFFFFFFFF);
4046 index(0x4);
4047 scale(0x0);
4048 disp($addr);
4049 %}
4050 %}
4051
4052 // Indirect Memory Operand
4053 operand indirect(eRegP reg) %{
4054 constraint(ALLOC_IN_RC(int_reg));
4055 match(reg);
4056
4057 format %{ "[$reg]" %}
4058 interface(MEMORY_INTER) %{
4059 base($reg);
4060 index(0x4);
4061 scale(0x0);
4062 disp(0x0);
4063 %}
4064 %}
4065
4066 // Indirect Memory Plus Short Offset Operand
4067 operand indOffset8(eRegP reg, immI8 off) %{
4068 match(AddP reg off);
4069
4070 format %{ "[$reg + $off]" %}
4071 interface(MEMORY_INTER) %{
4072 base($reg);
4073 index(0x4);
4074 scale(0x0);
4075 disp($off);
4076 %}
4077 %}
4078
4079 // Indirect Memory Plus Long Offset Operand
4080 operand indOffset32(eRegP reg, immI off) %{
4081 match(AddP reg off);
4082
4083 format %{ "[$reg + $off]" %}
4084 interface(MEMORY_INTER) %{
4085 base($reg);
4086 index(0x4);
4087 scale(0x0);
4088 disp($off);
4089 %}
4090 %}
4091
4092 // Indirect Memory Plus Long Offset Operand
4093 operand indOffset32X(rRegI reg, immP off) %{
4094 match(AddP off reg);
4095
4096 format %{ "[$reg + $off]" %}
4097 interface(MEMORY_INTER) %{
4098 base($reg);
4099 index(0x4);
4100 scale(0x0);
4101 disp($off);
4102 %}
4103 %}
4104
4105 // Indirect Memory Plus Index Register Plus Offset Operand
4106 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4107 match(AddP (AddP reg ireg) off);
4108
4109 op_cost(10);
4110 format %{"[$reg + $off + $ireg]" %}
4111 interface(MEMORY_INTER) %{
4112 base($reg);
4113 index($ireg);
4114 scale(0x0);
4115 disp($off);
4116 %}
4117 %}
4118
4119 // Indirect Memory Plus Index Register Plus Offset Operand
4120 operand indIndex(eRegP reg, rRegI ireg) %{
4121 match(AddP reg ireg);
4122
4123 op_cost(10);
4124 format %{"[$reg + $ireg]" %}
4125 interface(MEMORY_INTER) %{
4126 base($reg);
4127 index($ireg);
4128 scale(0x0);
4129 disp(0x0);
4130 %}
4131 %}
4132
4133 // // -------------------------------------------------------------------------
4134 // // 486 architecture doesn't support "scale * index + offset" with out a base
4135 // // -------------------------------------------------------------------------
4136 // // Scaled Memory Operands
4137 // // Indirect Memory Times Scale Plus Offset Operand
4138 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4139 // match(AddP off (LShiftI ireg scale));
4140 //
4141 // op_cost(10);
4142 // format %{"[$off + $ireg << $scale]" %}
4143 // interface(MEMORY_INTER) %{
4144 // base(0x4);
4145 // index($ireg);
4146 // scale($scale);
4147 // disp($off);
4148 // %}
4149 // %}
4150
4151 // Indirect Memory Times Scale Plus Index Register
4152 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4153 match(AddP reg (LShiftI ireg scale));
4154
4155 op_cost(10);
4156 format %{"[$reg + $ireg << $scale]" %}
4157 interface(MEMORY_INTER) %{
4158 base($reg);
4159 index($ireg);
4160 scale($scale);
4161 disp(0x0);
4162 %}
4163 %}
4164
4165 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4166 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4167 match(AddP (AddP reg (LShiftI ireg scale)) off);
4168
4169 op_cost(10);
4170 format %{"[$reg + $off + $ireg << $scale]" %}
4171 interface(MEMORY_INTER) %{
4172 base($reg);
4173 index($ireg);
4174 scale($scale);
4175 disp($off);
4176 %}
4177 %}
4178
4179 //----------Load Long Memory Operands------------------------------------------
4180 // The load-long idiom will use it's address expression again after loading
4181 // the first word of the long. If the load-long destination overlaps with
4182 // registers used in the addressing expression, the 2nd half will be loaded
4183 // from a clobbered address. Fix this by requiring that load-long use
4184 // address registers that do not overlap with the load-long target.
4185
4186 // load-long support
4187 operand load_long_RegP() %{
4188 constraint(ALLOC_IN_RC(esi_reg));
4189 match(RegP);
4190 match(eSIRegP);
4191 op_cost(100);
4192 format %{ %}
4193 interface(REG_INTER);
4194 %}
4195
4196 // Indirect Memory Operand Long
4197 operand load_long_indirect(load_long_RegP reg) %{
4198 constraint(ALLOC_IN_RC(esi_reg));
4199 match(reg);
4200
4201 format %{ "[$reg]" %}
4202 interface(MEMORY_INTER) %{
4203 base($reg);
4204 index(0x4);
4205 scale(0x0);
4206 disp(0x0);
4207 %}
4208 %}
4209
4210 // Indirect Memory Plus Long Offset Operand
4211 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4212 match(AddP reg off);
4213
4214 format %{ "[$reg + $off]" %}
4215 interface(MEMORY_INTER) %{
4216 base($reg);
4217 index(0x4);
4218 scale(0x0);
4219 disp($off);
4220 %}
4221 %}
4222
4223 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4224
4225
4226 //----------Special Memory Operands--------------------------------------------
4227 // Stack Slot Operand - This operand is used for loading and storing temporary
4228 // values on the stack where a match requires a value to
4229 // flow through memory.
4230 operand stackSlotP(sRegP reg) %{
4231 constraint(ALLOC_IN_RC(stack_slots));
4232 // No match rule because this operand is only generated in matching
4233 format %{ "[$reg]" %}
4234 interface(MEMORY_INTER) %{
4235 base(0x4); // ESP
4236 index(0x4); // No Index
4237 scale(0x0); // No Scale
4238 disp($reg); // Stack Offset
4239 %}
4240 %}
4241
4242 operand stackSlotI(sRegI reg) %{
4243 constraint(ALLOC_IN_RC(stack_slots));
4244 // No match rule because this operand is only generated in matching
4245 format %{ "[$reg]" %}
4246 interface(MEMORY_INTER) %{
4247 base(0x4); // ESP
4248 index(0x4); // No Index
4249 scale(0x0); // No Scale
4250 disp($reg); // Stack Offset
4251 %}
4252 %}
4253
4254 operand stackSlotF(sRegF reg) %{
4255 constraint(ALLOC_IN_RC(stack_slots));
4256 // No match rule because this operand is only generated in matching
4257 format %{ "[$reg]" %}
4258 interface(MEMORY_INTER) %{
4259 base(0x4); // ESP
4260 index(0x4); // No Index
4261 scale(0x0); // No Scale
4262 disp($reg); // Stack Offset
4263 %}
4264 %}
4265
4266 operand stackSlotD(sRegD reg) %{
4267 constraint(ALLOC_IN_RC(stack_slots));
4268 // No match rule because this operand is only generated in matching
4269 format %{ "[$reg]" %}
4270 interface(MEMORY_INTER) %{
4271 base(0x4); // ESP
4272 index(0x4); // No Index
4273 scale(0x0); // No Scale
4274 disp($reg); // Stack Offset
4275 %}
4276 %}
4277
4278 operand stackSlotL(sRegL reg) %{
4279 constraint(ALLOC_IN_RC(stack_slots));
4280 // No match rule because this operand is only generated in matching
4281 format %{ "[$reg]" %}
4282 interface(MEMORY_INTER) %{
4283 base(0x4); // ESP
4284 index(0x4); // No Index
4285 scale(0x0); // No Scale
4286 disp($reg); // Stack Offset
4287 %}
4288 %}
4289
4290 //----------Memory Operands - Win95 Implicit Null Variants----------------
4291 // Indirect Memory Operand
4292 operand indirect_win95_safe(eRegP_no_EBP reg)
4293 %{
4294 constraint(ALLOC_IN_RC(int_reg));
4295 match(reg);
4296
4297 op_cost(100);
4298 format %{ "[$reg]" %}
4299 interface(MEMORY_INTER) %{
4300 base($reg);
4301 index(0x4);
4302 scale(0x0);
4303 disp(0x0);
4304 %}
4305 %}
4306
4307 // Indirect Memory Plus Short Offset Operand
4308 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4309 %{
4310 match(AddP reg off);
4311
4312 op_cost(100);
4313 format %{ "[$reg + $off]" %}
4314 interface(MEMORY_INTER) %{
4315 base($reg);
4316 index(0x4);
4317 scale(0x0);
4318 disp($off);
4319 %}
4320 %}
4321
4322 // Indirect Memory Plus Long Offset Operand
4323 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4324 %{
4325 match(AddP reg off);
4326
4327 op_cost(100);
4328 format %{ "[$reg + $off]" %}
4329 interface(MEMORY_INTER) %{
4330 base($reg);
4331 index(0x4);
4332 scale(0x0);
4333 disp($off);
4334 %}
4335 %}
4336
4337 // Indirect Memory Plus Index Register Plus Offset Operand
4338 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4339 %{
4340 match(AddP (AddP reg ireg) off);
4341
4342 op_cost(100);
4343 format %{"[$reg + $off + $ireg]" %}
4344 interface(MEMORY_INTER) %{
4345 base($reg);
4346 index($ireg);
4347 scale(0x0);
4348 disp($off);
4349 %}
4350 %}
4351
4352 // Indirect Memory Times Scale Plus Index Register
4353 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4354 %{
4355 match(AddP reg (LShiftI ireg scale));
4356
4357 op_cost(100);
4358 format %{"[$reg + $ireg << $scale]" %}
4359 interface(MEMORY_INTER) %{
4360 base($reg);
4361 index($ireg);
4362 scale($scale);
4363 disp(0x0);
4364 %}
4365 %}
4366
4367 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4368 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4369 %{
4370 match(AddP (AddP reg (LShiftI ireg scale)) off);
4371
4372 op_cost(100);
4373 format %{"[$reg + $off + $ireg << $scale]" %}
4374 interface(MEMORY_INTER) %{
4375 base($reg);
4376 index($ireg);
4377 scale($scale);
4378 disp($off);
4379 %}
4380 %}
4381
4382 //----------Conditional Branch Operands----------------------------------------
4383 // Comparison Op - This is the operation of the comparison, and is limited to
4384 // the following set of codes:
4385 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4386 //
4387 // Other attributes of the comparison, such as unsignedness, are specified
4388 // by the comparison instruction that sets a condition code flags register.
4389 // That result is represented by a flags operand whose subtype is appropriate
4390 // to the unsignedness (etc.) of the comparison.
4391 //
4392 // Later, the instruction which matches both the Comparison Op (a Bool) and
4393 // the flags (produced by the Cmp) specifies the coding of the comparison op
4394 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4395
4396 // Comparision Code
4397 operand cmpOp() %{
4398 match(Bool);
4399
4400 format %{ "" %}
4401 interface(COND_INTER) %{
4402 equal(0x4, "e");
4403 not_equal(0x5, "ne");
4404 less(0xC, "l");
4405 greater_equal(0xD, "ge");
4406 less_equal(0xE, "le");
4407 greater(0xF, "g");
4408 overflow(0x0, "o");
4409 no_overflow(0x1, "no");
4410 %}
4411 %}
4412
4413 // Comparison Code, unsigned compare. Used by FP also, with
4414 // C2 (unordered) turned into GT or LT already. The other bits
4415 // C0 and C3 are turned into Carry & Zero flags.
4416 operand cmpOpU() %{
4417 match(Bool);
4418
4419 format %{ "" %}
4420 interface(COND_INTER) %{
4421 equal(0x4, "e");
4422 not_equal(0x5, "ne");
4423 less(0x2, "b");
4424 greater_equal(0x3, "nb");
4425 less_equal(0x6, "be");
4426 greater(0x7, "nbe");
4427 overflow(0x0, "o");
4428 no_overflow(0x1, "no");
4429 %}
4430 %}
4431
4432 // Floating comparisons that don't require any fixup for the unordered case
4433 operand cmpOpUCF() %{
4434 match(Bool);
4435 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4436 n->as_Bool()->_test._test == BoolTest::ge ||
4437 n->as_Bool()->_test._test == BoolTest::le ||
4438 n->as_Bool()->_test._test == BoolTest::gt);
4439 format %{ "" %}
4440 interface(COND_INTER) %{
4441 equal(0x4, "e");
4442 not_equal(0x5, "ne");
4443 less(0x2, "b");
4444 greater_equal(0x3, "nb");
4445 less_equal(0x6, "be");
4446 greater(0x7, "nbe");
4447 overflow(0x0, "o");
4448 no_overflow(0x1, "no");
4449 %}
4450 %}
4451
4452
4453 // Floating comparisons that can be fixed up with extra conditional jumps
4454 operand cmpOpUCF2() %{
4455 match(Bool);
4456 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4457 n->as_Bool()->_test._test == BoolTest::eq);
4458 format %{ "" %}
4459 interface(COND_INTER) %{
4460 equal(0x4, "e");
4461 not_equal(0x5, "ne");
4462 less(0x2, "b");
4463 greater_equal(0x3, "nb");
4464 less_equal(0x6, "be");
4465 greater(0x7, "nbe");
4466 overflow(0x0, "o");
4467 no_overflow(0x1, "no");
4468 %}
4469 %}
4470
4471 // Comparison Code for FP conditional move
4472 operand cmpOp_fcmov() %{
4473 match(Bool);
4474
4475 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4476 n->as_Bool()->_test._test != BoolTest::no_overflow);
4477 format %{ "" %}
4478 interface(COND_INTER) %{
4479 equal (0x0C8);
4480 not_equal (0x1C8);
4481 less (0x0C0);
4482 greater_equal(0x1C0);
4483 less_equal (0x0D0);
4484 greater (0x1D0);
4485 overflow(0x0, "o"); // not really supported by the instruction
4486 no_overflow(0x1, "no"); // not really supported by the instruction
4487 %}
4488 %}
4489
4490 // Comparision Code used in long compares
4491 operand cmpOp_commute() %{
4492 match(Bool);
4493
4494 format %{ "" %}
4495 interface(COND_INTER) %{
4496 equal(0x4, "e");
4497 not_equal(0x5, "ne");
4498 less(0xF, "g");
4499 greater_equal(0xE, "le");
4500 less_equal(0xD, "ge");
4501 greater(0xC, "l");
4502 overflow(0x0, "o");
4503 no_overflow(0x1, "no");
4504 %}
4505 %}
4506
4507 //----------OPERAND CLASSES----------------------------------------------------
4508 // Operand Classes are groups of operands that are used as to simplify
4509 // instruction definitions by not requiring the AD writer to specify separate
4510 // instructions for every form of operand when the instruction accepts
4511 // multiple operand types with the same basic encoding and format. The classic
4512 // case of this is memory operands.
4513
4514 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
4515 indIndex, indIndexScale, indIndexScaleOffset);
4516
4517 // Long memory operations are encoded in 2 instructions and a +4 offset.
4518 // This means some kind of offset is always required and you cannot use
4519 // an oop as the offset (done when working on static globals).
4520 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
4521 indIndex, indIndexScale, indIndexScaleOffset);
4522
4523
4524 //----------PIPELINE-----------------------------------------------------------
4525 // Rules which define the behavior of the target architectures pipeline.
4526 pipeline %{
4527
4528 //----------ATTRIBUTES---------------------------------------------------------
4529 attributes %{
4530 variable_size_instructions; // Fixed size instructions
4531 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4532 instruction_unit_size = 1; // An instruction is 1 bytes long
4533 instruction_fetch_unit_size = 16; // The processor fetches one line
4534 instruction_fetch_units = 1; // of 16 bytes
4535
4536 // List of nop instructions
4537 nops( MachNop );
4538 %}
4539
4540 //----------RESOURCES----------------------------------------------------------
4541 // Resources are the functional units available to the machine
4542
4543 // Generic P2/P3 pipeline
4544 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4545 // 3 instructions decoded per cycle.
4546 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4547 // 2 ALU op, only ALU0 handles mul/div instructions.
4548 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4549 MS0, MS1, MEM = MS0 | MS1,
4550 BR, FPU,
4551 ALU0, ALU1, ALU = ALU0 | ALU1 );
4552
4553 //----------PIPELINE DESCRIPTION-----------------------------------------------
4554 // Pipeline Description specifies the stages in the machine's pipeline
4555
4556 // Generic P2/P3 pipeline
4557 pipe_desc(S0, S1, S2, S3, S4, S5);
4558
4559 //----------PIPELINE CLASSES---------------------------------------------------
4560 // Pipeline Classes describe the stages in which input and output are
4561 // referenced by the hardware pipeline.
4562
4563 // Naming convention: ialu or fpu
4564 // Then: _reg
4565 // Then: _reg if there is a 2nd register
4566 // Then: _long if it's a pair of instructions implementing a long
4567 // Then: _fat if it requires the big decoder
4568 // Or: _mem if it requires the big decoder and a memory unit.
4569
4570 // Integer ALU reg operation
4571 pipe_class ialu_reg(rRegI dst) %{
4572 single_instruction;
4573 dst : S4(write);
4574 dst : S3(read);
4575 DECODE : S0; // any decoder
4576 ALU : S3; // any alu
4577 %}
4578
4579 // Long ALU reg operation
4580 pipe_class ialu_reg_long(eRegL dst) %{
4581 instruction_count(2);
4582 dst : S4(write);
4583 dst : S3(read);
4584 DECODE : S0(2); // any 2 decoders
4585 ALU : S3(2); // both alus
4586 %}
4587
4588 // Integer ALU reg operation using big decoder
4589 pipe_class ialu_reg_fat(rRegI dst) %{
4590 single_instruction;
4591 dst : S4(write);
4592 dst : S3(read);
4593 D0 : S0; // big decoder only
4594 ALU : S3; // any alu
4595 %}
4596
4597 // Long ALU reg operation using big decoder
4598 pipe_class ialu_reg_long_fat(eRegL dst) %{
4599 instruction_count(2);
4600 dst : S4(write);
4601 dst : S3(read);
4602 D0 : S0(2); // big decoder only; twice
4603 ALU : S3(2); // any 2 alus
4604 %}
4605
4606 // Integer ALU reg-reg operation
4607 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
4608 single_instruction;
4609 dst : S4(write);
4610 src : S3(read);
4611 DECODE : S0; // any decoder
4612 ALU : S3; // any alu
4613 %}
4614
4615 // Long ALU reg-reg operation
4616 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
4617 instruction_count(2);
4618 dst : S4(write);
4619 src : S3(read);
4620 DECODE : S0(2); // any 2 decoders
4621 ALU : S3(2); // both alus
4622 %}
4623
4624 // Integer ALU reg-reg operation
4625 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
4626 single_instruction;
4627 dst : S4(write);
4628 src : S3(read);
4629 D0 : S0; // big decoder only
4630 ALU : S3; // any alu
4631 %}
4632
4633 // Long ALU reg-reg operation
4634 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
4635 instruction_count(2);
4636 dst : S4(write);
4637 src : S3(read);
4638 D0 : S0(2); // big decoder only; twice
4639 ALU : S3(2); // both alus
4640 %}
4641
4642 // Integer ALU reg-mem operation
4643 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
4644 single_instruction;
4645 dst : S5(write);
4646 mem : S3(read);
4647 D0 : S0; // big decoder only
4648 ALU : S4; // any alu
4649 MEM : S3; // any mem
4650 %}
4651
4652 // Long ALU reg-mem operation
4653 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
4654 instruction_count(2);
4655 dst : S5(write);
4656 mem : S3(read);
4657 D0 : S0(2); // big decoder only; twice
4658 ALU : S4(2); // any 2 alus
4659 MEM : S3(2); // both mems
4660 %}
4661
4662 // Integer mem operation (prefetch)
4663 pipe_class ialu_mem(memory mem)
4664 %{
4665 single_instruction;
4666 mem : S3(read);
4667 D0 : S0; // big decoder only
4668 MEM : S3; // any mem
4669 %}
4670
4671 // Integer Store to Memory
4672 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
4673 single_instruction;
4674 mem : S3(read);
4675 src : S5(read);
4676 D0 : S0; // big decoder only
4677 ALU : S4; // any alu
4678 MEM : S3;
4679 %}
4680
4681 // Long Store to Memory
4682 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
4683 instruction_count(2);
4684 mem : S3(read);
4685 src : S5(read);
4686 D0 : S0(2); // big decoder only; twice
4687 ALU : S4(2); // any 2 alus
4688 MEM : S3(2); // Both mems
4689 %}
4690
4691 // Integer Store to Memory
4692 pipe_class ialu_mem_imm(memory mem) %{
4693 single_instruction;
4694 mem : S3(read);
4695 D0 : S0; // big decoder only
4696 ALU : S4; // any alu
4697 MEM : S3;
4698 %}
4699
4700 // Integer ALU0 reg-reg operation
4701 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
4702 single_instruction;
4703 dst : S4(write);
4704 src : S3(read);
4705 D0 : S0; // Big decoder only
4706 ALU0 : S3; // only alu0
4707 %}
4708
4709 // Integer ALU0 reg-mem operation
4710 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
4711 single_instruction;
4712 dst : S5(write);
4713 mem : S3(read);
4714 D0 : S0; // big decoder only
4715 ALU0 : S4; // ALU0 only
4716 MEM : S3; // any mem
4717 %}
4718
4719 // Integer ALU reg-reg operation
4720 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
4721 single_instruction;
4722 cr : S4(write);
4723 src1 : S3(read);
4724 src2 : S3(read);
4725 DECODE : S0; // any decoder
4726 ALU : S3; // any alu
4727 %}
4728
4729 // Integer ALU reg-imm operation
4730 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
4731 single_instruction;
4732 cr : S4(write);
4733 src1 : S3(read);
4734 DECODE : S0; // any decoder
4735 ALU : S3; // any alu
4736 %}
4737
4738 // Integer ALU reg-mem operation
4739 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
4740 single_instruction;
4741 cr : S4(write);
4742 src1 : S3(read);
4743 src2 : S3(read);
4744 D0 : S0; // big decoder only
4745 ALU : S4; // any alu
4746 MEM : S3;
4747 %}
4748
4749 // Conditional move reg-reg
4750 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
4751 instruction_count(4);
4752 y : S4(read);
4753 q : S3(read);
4754 p : S3(read);
4755 DECODE : S0(4); // any decoder
4756 %}
4757
4758 // Conditional move reg-reg
4759 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
4760 single_instruction;
4761 dst : S4(write);
4762 src : S3(read);
4763 cr : S3(read);
4764 DECODE : S0; // any decoder
4765 %}
4766
4767 // Conditional move reg-mem
4768 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
4769 single_instruction;
4770 dst : S4(write);
4771 src : S3(read);
4772 cr : S3(read);
4773 DECODE : S0; // any decoder
4774 MEM : S3;
4775 %}
4776
4777 // Conditional move reg-reg long
4778 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
4779 single_instruction;
4780 dst : S4(write);
4781 src : S3(read);
4782 cr : S3(read);
4783 DECODE : S0(2); // any 2 decoders
4784 %}
4785
4786 // Conditional move double reg-reg
4787 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
4788 single_instruction;
4789 dst : S4(write);
4790 src : S3(read);
4791 cr : S3(read);
4792 DECODE : S0; // any decoder
4793 %}
4794
4795 // Float reg-reg operation
4796 pipe_class fpu_reg(regDPR dst) %{
4797 instruction_count(2);
4798 dst : S3(read);
4799 DECODE : S0(2); // any 2 decoders
4800 FPU : S3;
4801 %}
4802
4803 // Float reg-reg operation
4804 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
4805 instruction_count(2);
4806 dst : S4(write);
4807 src : S3(read);
4808 DECODE : S0(2); // any 2 decoders
4809 FPU : S3;
4810 %}
4811
4812 // Float reg-reg operation
4813 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
4814 instruction_count(3);
4815 dst : S4(write);
4816 src1 : S3(read);
4817 src2 : S3(read);
4818 DECODE : S0(3); // any 3 decoders
4819 FPU : S3(2);
4820 %}
4821
4822 // Float reg-reg operation
4823 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
4824 instruction_count(4);
4825 dst : S4(write);
4826 src1 : S3(read);
4827 src2 : S3(read);
4828 src3 : S3(read);
4829 DECODE : S0(4); // any 3 decoders
4830 FPU : S3(2);
4831 %}
4832
4833 // Float reg-reg operation
4834 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
4835 instruction_count(4);
4836 dst : S4(write);
4837 src1 : S3(read);
4838 src2 : S3(read);
4839 src3 : S3(read);
4840 DECODE : S1(3); // any 3 decoders
4841 D0 : S0; // Big decoder only
4842 FPU : S3(2);
4843 MEM : S3;
4844 %}
4845
4846 // Float reg-mem operation
4847 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
4848 instruction_count(2);
4849 dst : S5(write);
4850 mem : S3(read);
4851 D0 : S0; // big decoder only
4852 DECODE : S1; // any decoder for FPU POP
4853 FPU : S4;
4854 MEM : S3; // any mem
4855 %}
4856
4857 // Float reg-mem operation
4858 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
4859 instruction_count(3);
4860 dst : S5(write);
4861 src1 : S3(read);
4862 mem : S3(read);
4863 D0 : S0; // big decoder only
4864 DECODE : S1(2); // any decoder for FPU POP
4865 FPU : S4;
4866 MEM : S3; // any mem
4867 %}
4868
4869 // Float mem-reg operation
4870 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
4871 instruction_count(2);
4872 src : S5(read);
4873 mem : S3(read);
4874 DECODE : S0; // any decoder for FPU PUSH
4875 D0 : S1; // big decoder only
4876 FPU : S4;
4877 MEM : S3; // any mem
4878 %}
4879
4880 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
4881 instruction_count(3);
4882 src1 : S3(read);
4883 src2 : S3(read);
4884 mem : S3(read);
4885 DECODE : S0(2); // any decoder for FPU PUSH
4886 D0 : S1; // big decoder only
4887 FPU : S4;
4888 MEM : S3; // any mem
4889 %}
4890
4891 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
4892 instruction_count(3);
4893 src1 : S3(read);
4894 src2 : S3(read);
4895 mem : S4(read);
4896 DECODE : S0; // any decoder for FPU PUSH
4897 D0 : S0(2); // big decoder only
4898 FPU : S4;
4899 MEM : S3(2); // any mem
4900 %}
4901
4902 pipe_class fpu_mem_mem(memory dst, memory src1) %{
4903 instruction_count(2);
4904 src1 : S3(read);
4905 dst : S4(read);
4906 D0 : S0(2); // big decoder only
4907 MEM : S3(2); // any mem
4908 %}
4909
4910 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
4911 instruction_count(3);
4912 src1 : S3(read);
4913 src2 : S3(read);
4914 dst : S4(read);
4915 D0 : S0(3); // big decoder only
4916 FPU : S4;
4917 MEM : S3(3); // any mem
4918 %}
4919
4920 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
4921 instruction_count(3);
4922 src1 : S4(read);
4923 mem : S4(read);
4924 DECODE : S0; // any decoder for FPU PUSH
4925 D0 : S0(2); // big decoder only
4926 FPU : S4;
4927 MEM : S3(2); // any mem
4928 %}
4929
4930 // Float load constant
4931 pipe_class fpu_reg_con(regDPR dst) %{
4932 instruction_count(2);
4933 dst : S5(write);
4934 D0 : S0; // big decoder only for the load
4935 DECODE : S1; // any decoder for FPU POP
4936 FPU : S4;
4937 MEM : S3; // any mem
4938 %}
4939
4940 // Float load constant
4941 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
4942 instruction_count(3);
4943 dst : S5(write);
4944 src : S3(read);
4945 D0 : S0; // big decoder only for the load
4946 DECODE : S1(2); // any decoder for FPU POP
4947 FPU : S4;
4948 MEM : S3; // any mem
4949 %}
4950
4951 // UnConditional branch
4952 pipe_class pipe_jmp( label labl ) %{
4953 single_instruction;
4954 BR : S3;
4955 %}
4956
4957 // Conditional branch
4958 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
4959 single_instruction;
4960 cr : S1(read);
4961 BR : S3;
4962 %}
4963
4964 // Allocation idiom
4965 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
4966 instruction_count(1); force_serialization;
4967 fixed_latency(6);
4968 heap_ptr : S3(read);
4969 DECODE : S0(3);
4970 D0 : S2;
4971 MEM : S3;
4972 ALU : S3(2);
4973 dst : S5(write);
4974 BR : S5;
4975 %}
4976
4977 // Generic big/slow expanded idiom
4978 pipe_class pipe_slow( ) %{
4979 instruction_count(10); multiple_bundles; force_serialization;
4980 fixed_latency(100);
4981 D0 : S0(2);
4982 MEM : S3(2);
4983 %}
4984
4985 // The real do-nothing guy
4986 pipe_class empty( ) %{
4987 instruction_count(0);
4988 %}
4989
4990 // Define the class for the Nop node
4991 define %{
4992 MachNop = empty;
4993 %}
4994
4995 %}
4996
4997 //----------INSTRUCTIONS-------------------------------------------------------
4998 //
4999 // match -- States which machine-independent subtree may be replaced
5000 // by this instruction.
5001 // ins_cost -- The estimated cost of this instruction is used by instruction
5002 // selection to identify a minimum cost tree of machine
5003 // instructions that matches a tree of machine-independent
5004 // instructions.
5005 // format -- A string providing the disassembly for this instruction.
5006 // The value of an instruction's operand may be inserted
5007 // by referring to it with a '$' prefix.
5008 // opcode -- Three instruction opcodes may be provided. These are referred
5009 // to within an encode class as $primary, $secondary, and $tertiary
5010 // respectively. The primary opcode is commonly used to
5011 // indicate the type of machine instruction, while secondary
5012 // and tertiary are often used for prefix options or addressing
5013 // modes.
5014 // ins_encode -- A list of encode classes with parameters. The encode class
5015 // name must have been defined in an 'enc_class' specification
5016 // in the encode section of the architecture description.
5017
5018 //----------BSWAP-Instruction--------------------------------------------------
5019 instruct bytes_reverse_int(rRegI dst) %{
5020 match(Set dst (ReverseBytesI dst));
5021
5022 format %{ "BSWAP $dst" %}
5023 opcode(0x0F, 0xC8);
5024 ins_encode( OpcP, OpcSReg(dst) );
5025 ins_pipe( ialu_reg );
5026 %}
5027
5028 instruct bytes_reverse_long(eRegL dst) %{
5029 match(Set dst (ReverseBytesL dst));
5030
5031 format %{ "BSWAP $dst.lo\n\t"
5032 "BSWAP $dst.hi\n\t"
5033 "XCHG $dst.lo $dst.hi" %}
5034
5035 ins_cost(125);
5036 ins_encode( bswap_long_bytes(dst) );
5037 ins_pipe( ialu_reg_reg);
5038 %}
5039
5040 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5041 match(Set dst (ReverseBytesUS dst));
5042 effect(KILL cr);
5043
5044 format %{ "BSWAP $dst\n\t"
5045 "SHR $dst,16\n\t" %}
5046 ins_encode %{
5047 __ bswapl($dst$$Register);
5048 __ shrl($dst$$Register, 16);
5049 %}
5050 ins_pipe( ialu_reg );
5051 %}
5052
5053 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5054 match(Set dst (ReverseBytesS dst));
5055 effect(KILL cr);
5056
5057 format %{ "BSWAP $dst\n\t"
5058 "SAR $dst,16\n\t" %}
5059 ins_encode %{
5060 __ bswapl($dst$$Register);
5061 __ sarl($dst$$Register, 16);
5062 %}
5063 ins_pipe( ialu_reg );
5064 %}
5065
5066
5067 //---------- Zeros Count Instructions ------------------------------------------
5068
5069 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5070 predicate(UseCountLeadingZerosInstruction);
5071 match(Set dst (CountLeadingZerosI src));
5072 effect(KILL cr);
5073
5074 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5075 ins_encode %{
5076 __ lzcntl($dst$$Register, $src$$Register);
5077 %}
5078 ins_pipe(ialu_reg);
5079 %}
5080
5081 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5082 predicate(!UseCountLeadingZerosInstruction);
5083 match(Set dst (CountLeadingZerosI src));
5084 effect(KILL cr);
5085
5086 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5087 "JNZ skip\n\t"
5088 "MOV $dst, -1\n"
5089 "skip:\n\t"
5090 "NEG $dst\n\t"
5091 "ADD $dst, 31" %}
5092 ins_encode %{
5093 Register Rdst = $dst$$Register;
5094 Register Rsrc = $src$$Register;
5095 Label skip;
5096 __ bsrl(Rdst, Rsrc);
5097 __ jccb(Assembler::notZero, skip);
5098 __ movl(Rdst, -1);
5099 __ bind(skip);
5100 __ negl(Rdst);
5101 __ addl(Rdst, BitsPerInt - 1);
5102 %}
5103 ins_pipe(ialu_reg);
5104 %}
5105
5106 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5107 predicate(UseCountLeadingZerosInstruction);
5108 match(Set dst (CountLeadingZerosL src));
5109 effect(TEMP dst, KILL cr);
5110
5111 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5112 "JNC done\n\t"
5113 "LZCNT $dst, $src.lo\n\t"
5114 "ADD $dst, 32\n"
5115 "done:" %}
5116 ins_encode %{
5117 Register Rdst = $dst$$Register;
5118 Register Rsrc = $src$$Register;
5119 Label done;
5120 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5121 __ jccb(Assembler::carryClear, done);
5122 __ lzcntl(Rdst, Rsrc);
5123 __ addl(Rdst, BitsPerInt);
5124 __ bind(done);
5125 %}
5126 ins_pipe(ialu_reg);
5127 %}
5128
5129 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5130 predicate(!UseCountLeadingZerosInstruction);
5131 match(Set dst (CountLeadingZerosL src));
5132 effect(TEMP dst, KILL cr);
5133
5134 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5135 "JZ msw_is_zero\n\t"
5136 "ADD $dst, 32\n\t"
5137 "JMP not_zero\n"
5138 "msw_is_zero:\n\t"
5139 "BSR $dst, $src.lo\n\t"
5140 "JNZ not_zero\n\t"
5141 "MOV $dst, -1\n"
5142 "not_zero:\n\t"
5143 "NEG $dst\n\t"
5144 "ADD $dst, 63\n" %}
5145 ins_encode %{
5146 Register Rdst = $dst$$Register;
5147 Register Rsrc = $src$$Register;
5148 Label msw_is_zero;
5149 Label not_zero;
5150 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5151 __ jccb(Assembler::zero, msw_is_zero);
5152 __ addl(Rdst, BitsPerInt);
5153 __ jmpb(not_zero);
5154 __ bind(msw_is_zero);
5155 __ bsrl(Rdst, Rsrc);
5156 __ jccb(Assembler::notZero, not_zero);
5157 __ movl(Rdst, -1);
5158 __ bind(not_zero);
5159 __ negl(Rdst);
5160 __ addl(Rdst, BitsPerLong - 1);
5161 %}
5162 ins_pipe(ialu_reg);
5163 %}
5164
5165 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5166 predicate(UseCountTrailingZerosInstruction);
5167 match(Set dst (CountTrailingZerosI src));
5168 effect(KILL cr);
5169
5170 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)" %}
5171 ins_encode %{
5172 __ tzcntl($dst$$Register, $src$$Register);
5173 %}
5174 ins_pipe(ialu_reg);
5175 %}
5176
5177 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{
5178 predicate(!UseCountTrailingZerosInstruction);
5179 match(Set dst (CountTrailingZerosI src));
5180 effect(KILL cr);
5181
5182 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5183 "JNZ done\n\t"
5184 "MOV $dst, 32\n"
5185 "done:" %}
5186 ins_encode %{
5187 Register Rdst = $dst$$Register;
5188 Label done;
5189 __ bsfl(Rdst, $src$$Register);
5190 __ jccb(Assembler::notZero, done);
5191 __ movl(Rdst, BitsPerInt);
5192 __ bind(done);
5193 %}
5194 ins_pipe(ialu_reg);
5195 %}
5196
5197 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5198 predicate(UseCountTrailingZerosInstruction);
5199 match(Set dst (CountTrailingZerosL src));
5200 effect(TEMP dst, KILL cr);
5201
5202 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t"
5203 "JNC done\n\t"
5204 "TZCNT $dst, $src.hi\n\t"
5205 "ADD $dst, 32\n"
5206 "done:" %}
5207 ins_encode %{
5208 Register Rdst = $dst$$Register;
5209 Register Rsrc = $src$$Register;
5210 Label done;
5211 __ tzcntl(Rdst, Rsrc);
5212 __ jccb(Assembler::carryClear, done);
5213 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5214 __ addl(Rdst, BitsPerInt);
5215 __ bind(done);
5216 %}
5217 ins_pipe(ialu_reg);
5218 %}
5219
5220 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{
5221 predicate(!UseCountTrailingZerosInstruction);
5222 match(Set dst (CountTrailingZerosL src));
5223 effect(TEMP dst, KILL cr);
5224
5225 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5226 "JNZ done\n\t"
5227 "BSF $dst, $src.hi\n\t"
5228 "JNZ msw_not_zero\n\t"
5229 "MOV $dst, 32\n"
5230 "msw_not_zero:\n\t"
5231 "ADD $dst, 32\n"
5232 "done:" %}
5233 ins_encode %{
5234 Register Rdst = $dst$$Register;
5235 Register Rsrc = $src$$Register;
5236 Label msw_not_zero;
5237 Label done;
5238 __ bsfl(Rdst, Rsrc);
5239 __ jccb(Assembler::notZero, done);
5240 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5241 __ jccb(Assembler::notZero, msw_not_zero);
5242 __ movl(Rdst, BitsPerInt);
5243 __ bind(msw_not_zero);
5244 __ addl(Rdst, BitsPerInt);
5245 __ bind(done);
5246 %}
5247 ins_pipe(ialu_reg);
5248 %}
5249
5250
5251 //---------- Population Count Instructions -------------------------------------
5252
5253 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5254 predicate(UsePopCountInstruction);
5255 match(Set dst (PopCountI src));
5256 effect(KILL cr);
5257
5258 format %{ "POPCNT $dst, $src" %}
5259 ins_encode %{
5260 __ popcntl($dst$$Register, $src$$Register);
5261 %}
5262 ins_pipe(ialu_reg);
5263 %}
5264
5265 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5266 predicate(UsePopCountInstruction);
5267 match(Set dst (PopCountI (LoadI mem)));
5268 effect(KILL cr);
5269
5270 format %{ "POPCNT $dst, $mem" %}
5271 ins_encode %{
5272 __ popcntl($dst$$Register, $mem$$Address);
5273 %}
5274 ins_pipe(ialu_reg);
5275 %}
5276
5277 // Note: Long.bitCount(long) returns an int.
5278 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5279 predicate(UsePopCountInstruction);
5280 match(Set dst (PopCountL src));
5281 effect(KILL cr, TEMP tmp, TEMP dst);
5282
5283 format %{ "POPCNT $dst, $src.lo\n\t"
5284 "POPCNT $tmp, $src.hi\n\t"
5285 "ADD $dst, $tmp" %}
5286 ins_encode %{
5287 __ popcntl($dst$$Register, $src$$Register);
5288 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5289 __ addl($dst$$Register, $tmp$$Register);
5290 %}
5291 ins_pipe(ialu_reg);
5292 %}
5293
5294 // Note: Long.bitCount(long) returns an int.
5295 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5296 predicate(UsePopCountInstruction);
5297 match(Set dst (PopCountL (LoadL mem)));
5298 effect(KILL cr, TEMP tmp, TEMP dst);
5299
5300 format %{ "POPCNT $dst, $mem\n\t"
5301 "POPCNT $tmp, $mem+4\n\t"
5302 "ADD $dst, $tmp" %}
5303 ins_encode %{
5304 //__ popcntl($dst$$Register, $mem$$Address$$first);
5305 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5306 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5307 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5308 __ addl($dst$$Register, $tmp$$Register);
5309 %}
5310 ins_pipe(ialu_reg);
5311 %}
5312
5313
5314 //----------Load/Store/Move Instructions---------------------------------------
5315 //----------Load Instructions--------------------------------------------------
5316 // Load Byte (8bit signed)
5317 instruct loadB(xRegI dst, memory mem) %{
5318 match(Set dst (LoadB mem));
5319
5320 ins_cost(125);
5321 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5322
5323 ins_encode %{
5324 __ movsbl($dst$$Register, $mem$$Address);
5325 %}
5326
5327 ins_pipe(ialu_reg_mem);
5328 %}
5329
5330 // Load Byte (8bit signed) into Long Register
5331 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5332 match(Set dst (ConvI2L (LoadB mem)));
5333 effect(KILL cr);
5334
5335 ins_cost(375);
5336 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5337 "MOV $dst.hi,$dst.lo\n\t"
5338 "SAR $dst.hi,7" %}
5339
5340 ins_encode %{
5341 __ movsbl($dst$$Register, $mem$$Address);
5342 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5343 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5344 %}
5345
5346 ins_pipe(ialu_reg_mem);
5347 %}
5348
5349 // Load Unsigned Byte (8bit UNsigned)
5350 instruct loadUB(xRegI dst, memory mem) %{
5351 match(Set dst (LoadUB mem));
5352
5353 ins_cost(125);
5354 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5355
5356 ins_encode %{
5357 __ movzbl($dst$$Register, $mem$$Address);
5358 %}
5359
5360 ins_pipe(ialu_reg_mem);
5361 %}
5362
5363 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5364 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5365 match(Set dst (ConvI2L (LoadUB mem)));
5366 effect(KILL cr);
5367
5368 ins_cost(250);
5369 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5370 "XOR $dst.hi,$dst.hi" %}
5371
5372 ins_encode %{
5373 Register Rdst = $dst$$Register;
5374 __ movzbl(Rdst, $mem$$Address);
5375 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5376 %}
5377
5378 ins_pipe(ialu_reg_mem);
5379 %}
5380
5381 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5382 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5383 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5384 effect(KILL cr);
5385
5386 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5387 "XOR $dst.hi,$dst.hi\n\t"
5388 "AND $dst.lo,$mask" %}
5389 ins_encode %{
5390 Register Rdst = $dst$$Register;
5391 __ movzbl(Rdst, $mem$$Address);
5392 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5393 __ andl(Rdst, $mask$$constant);
5394 %}
5395 ins_pipe(ialu_reg_mem);
5396 %}
5397
5398 // Load Short (16bit signed)
5399 instruct loadS(rRegI dst, memory mem) %{
5400 match(Set dst (LoadS mem));
5401
5402 ins_cost(125);
5403 format %{ "MOVSX $dst,$mem\t# short" %}
5404
5405 ins_encode %{
5406 __ movswl($dst$$Register, $mem$$Address);
5407 %}
5408
5409 ins_pipe(ialu_reg_mem);
5410 %}
5411
5412 // Load Short (16 bit signed) to Byte (8 bit signed)
5413 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5414 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5415
5416 ins_cost(125);
5417 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5418 ins_encode %{
5419 __ movsbl($dst$$Register, $mem$$Address);
5420 %}
5421 ins_pipe(ialu_reg_mem);
5422 %}
5423
5424 // Load Short (16bit signed) into Long Register
5425 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5426 match(Set dst (ConvI2L (LoadS mem)));
5427 effect(KILL cr);
5428
5429 ins_cost(375);
5430 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5431 "MOV $dst.hi,$dst.lo\n\t"
5432 "SAR $dst.hi,15" %}
5433
5434 ins_encode %{
5435 __ movswl($dst$$Register, $mem$$Address);
5436 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5437 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5438 %}
5439
5440 ins_pipe(ialu_reg_mem);
5441 %}
5442
5443 // Load Unsigned Short/Char (16bit unsigned)
5444 instruct loadUS(rRegI dst, memory mem) %{
5445 match(Set dst (LoadUS mem));
5446
5447 ins_cost(125);
5448 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5449
5450 ins_encode %{
5451 __ movzwl($dst$$Register, $mem$$Address);
5452 %}
5453
5454 ins_pipe(ialu_reg_mem);
5455 %}
5456
5457 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5458 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5459 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5460
5461 ins_cost(125);
5462 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5463 ins_encode %{
5464 __ movsbl($dst$$Register, $mem$$Address);
5465 %}
5466 ins_pipe(ialu_reg_mem);
5467 %}
5468
5469 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5470 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5471 match(Set dst (ConvI2L (LoadUS mem)));
5472 effect(KILL cr);
5473
5474 ins_cost(250);
5475 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5476 "XOR $dst.hi,$dst.hi" %}
5477
5478 ins_encode %{
5479 __ movzwl($dst$$Register, $mem$$Address);
5480 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5481 %}
5482
5483 ins_pipe(ialu_reg_mem);
5484 %}
5485
5486 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5487 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5488 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5489 effect(KILL cr);
5490
5491 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5492 "XOR $dst.hi,$dst.hi" %}
5493 ins_encode %{
5494 Register Rdst = $dst$$Register;
5495 __ movzbl(Rdst, $mem$$Address);
5496 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5497 %}
5498 ins_pipe(ialu_reg_mem);
5499 %}
5500
5501 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5502 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5503 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5504 effect(KILL cr);
5505
5506 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5507 "XOR $dst.hi,$dst.hi\n\t"
5508 "AND $dst.lo,$mask" %}
5509 ins_encode %{
5510 Register Rdst = $dst$$Register;
5511 __ movzwl(Rdst, $mem$$Address);
5512 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5513 __ andl(Rdst, $mask$$constant);
5514 %}
5515 ins_pipe(ialu_reg_mem);
5516 %}
5517
5518 // Load Integer
5519 instruct loadI(rRegI dst, memory mem) %{
5520 match(Set dst (LoadI mem));
5521
5522 ins_cost(125);
5523 format %{ "MOV $dst,$mem\t# int" %}
5524
5525 ins_encode %{
5526 __ movl($dst$$Register, $mem$$Address);
5527 %}
5528
5529 ins_pipe(ialu_reg_mem);
5530 %}
5531
5532 // Load Integer (32 bit signed) to Byte (8 bit signed)
5533 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5534 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5535
5536 ins_cost(125);
5537 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
5538 ins_encode %{
5539 __ movsbl($dst$$Register, $mem$$Address);
5540 %}
5541 ins_pipe(ialu_reg_mem);
5542 %}
5543
5544 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5545 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5546 match(Set dst (AndI (LoadI mem) mask));
5547
5548 ins_cost(125);
5549 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
5550 ins_encode %{
5551 __ movzbl($dst$$Register, $mem$$Address);
5552 %}
5553 ins_pipe(ialu_reg_mem);
5554 %}
5555
5556 // Load Integer (32 bit signed) to Short (16 bit signed)
5557 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5558 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5559
5560 ins_cost(125);
5561 format %{ "MOVSX $dst, $mem\t# int -> short" %}
5562 ins_encode %{
5563 __ movswl($dst$$Register, $mem$$Address);
5564 %}
5565 ins_pipe(ialu_reg_mem);
5566 %}
5567
5568 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5569 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5570 match(Set dst (AndI (LoadI mem) mask));
5571
5572 ins_cost(125);
5573 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
5574 ins_encode %{
5575 __ movzwl($dst$$Register, $mem$$Address);
5576 %}
5577 ins_pipe(ialu_reg_mem);
5578 %}
5579
5580 // Load Integer into Long Register
5581 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
5582 match(Set dst (ConvI2L (LoadI mem)));
5583 effect(KILL cr);
5584
5585 ins_cost(375);
5586 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
5587 "MOV $dst.hi,$dst.lo\n\t"
5588 "SAR $dst.hi,31" %}
5589
5590 ins_encode %{
5591 __ movl($dst$$Register, $mem$$Address);
5592 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5593 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
5594 %}
5595
5596 ins_pipe(ialu_reg_mem);
5597 %}
5598
5599 // Load Integer with mask 0xFF into Long Register
5600 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5601 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5602 effect(KILL cr);
5603
5604 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
5605 "XOR $dst.hi,$dst.hi" %}
5606 ins_encode %{
5607 Register Rdst = $dst$$Register;
5608 __ movzbl(Rdst, $mem$$Address);
5609 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5610 %}
5611 ins_pipe(ialu_reg_mem);
5612 %}
5613
5614 // Load Integer with mask 0xFFFF into Long Register
5615 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
5616 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5617 effect(KILL cr);
5618
5619 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
5620 "XOR $dst.hi,$dst.hi" %}
5621 ins_encode %{
5622 Register Rdst = $dst$$Register;
5623 __ movzwl(Rdst, $mem$$Address);
5624 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5625 %}
5626 ins_pipe(ialu_reg_mem);
5627 %}
5628
5629 // Load Integer with 31-bit mask into Long Register
5630 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
5631 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5632 effect(KILL cr);
5633
5634 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
5635 "XOR $dst.hi,$dst.hi\n\t"
5636 "AND $dst.lo,$mask" %}
5637 ins_encode %{
5638 Register Rdst = $dst$$Register;
5639 __ movl(Rdst, $mem$$Address);
5640 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5641 __ andl(Rdst, $mask$$constant);
5642 %}
5643 ins_pipe(ialu_reg_mem);
5644 %}
5645
5646 // Load Unsigned Integer into Long Register
5647 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
5648 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5649 effect(KILL cr);
5650
5651 ins_cost(250);
5652 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
5653 "XOR $dst.hi,$dst.hi" %}
5654
5655 ins_encode %{
5656 __ movl($dst$$Register, $mem$$Address);
5657 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5658 %}
5659
5660 ins_pipe(ialu_reg_mem);
5661 %}
5662
5663 // Load Long. Cannot clobber address while loading, so restrict address
5664 // register to ESI
5665 instruct loadL(eRegL dst, load_long_memory mem) %{
5666 predicate(!((LoadLNode*)n)->require_atomic_access());
5667 match(Set dst (LoadL mem));
5668
5669 ins_cost(250);
5670 format %{ "MOV $dst.lo,$mem\t# long\n\t"
5671 "MOV $dst.hi,$mem+4" %}
5672
5673 ins_encode %{
5674 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
5675 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
5676 __ movl($dst$$Register, Amemlo);
5677 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
5678 %}
5679
5680 ins_pipe(ialu_reg_long_mem);
5681 %}
5682
5683 // Volatile Load Long. Must be atomic, so do 64-bit FILD
5684 // then store it down to the stack and reload on the int
5685 // side.
5686 instruct loadL_volatile(stackSlotL dst, memory mem) %{
5687 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
5688 match(Set dst (LoadL mem));
5689
5690 ins_cost(200);
5691 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
5692 "FISTp $dst" %}
5693 ins_encode(enc_loadL_volatile(mem,dst));
5694 ins_pipe( fpu_reg_mem );
5695 %}
5696
5697 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
5698 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5699 match(Set dst (LoadL mem));
5700 effect(TEMP tmp);
5701 ins_cost(180);
5702 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5703 "MOVSD $dst,$tmp" %}
5704 ins_encode %{
5705 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5706 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
5707 %}
5708 ins_pipe( pipe_slow );
5709 %}
5710
5711 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
5712 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5713 match(Set dst (LoadL mem));
5714 effect(TEMP tmp);
5715 ins_cost(160);
5716 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5717 "MOVD $dst.lo,$tmp\n\t"
5718 "PSRLQ $tmp,32\n\t"
5719 "MOVD $dst.hi,$tmp" %}
5720 ins_encode %{
5721 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5722 __ movdl($dst$$Register, $tmp$$XMMRegister);
5723 __ psrlq($tmp$$XMMRegister, 32);
5724 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
5725 %}
5726 ins_pipe( pipe_slow );
5727 %}
5728
5729 // Load Range
5730 instruct loadRange(rRegI dst, memory mem) %{
5731 match(Set dst (LoadRange mem));
5732
5733 ins_cost(125);
5734 format %{ "MOV $dst,$mem" %}
5735 opcode(0x8B);
5736 ins_encode( OpcP, RegMem(dst,mem));
5737 ins_pipe( ialu_reg_mem );
5738 %}
5739
5740
5741 // Load Pointer
5742 instruct loadP(eRegP dst, memory mem) %{
5743 match(Set dst (LoadP mem));
5744
5745 ins_cost(125);
5746 format %{ "MOV $dst,$mem" %}
5747 opcode(0x8B);
5748 ins_encode( OpcP, RegMem(dst,mem));
5749 ins_pipe( ialu_reg_mem );
5750 %}
5751
5752 // Load Klass Pointer
5753 instruct loadKlass(eRegP dst, memory mem) %{
5754 match(Set dst (LoadKlass mem));
5755
5756 ins_cost(125);
5757 format %{ "MOV $dst,$mem" %}
5758 opcode(0x8B);
5759 ins_encode( OpcP, RegMem(dst,mem));
5760 ins_pipe( ialu_reg_mem );
5761 %}
5762
5763 // Load Double
5764 instruct loadDPR(regDPR dst, memory mem) %{
5765 predicate(UseSSE<=1);
5766 match(Set dst (LoadD mem));
5767
5768 ins_cost(150);
5769 format %{ "FLD_D ST,$mem\n\t"
5770 "FSTP $dst" %}
5771 opcode(0xDD); /* DD /0 */
5772 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5773 Pop_Reg_DPR(dst) );
5774 ins_pipe( fpu_reg_mem );
5775 %}
5776
5777 // Load Double to XMM
5778 instruct loadD(regD dst, memory mem) %{
5779 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
5780 match(Set dst (LoadD mem));
5781 ins_cost(145);
5782 format %{ "MOVSD $dst,$mem" %}
5783 ins_encode %{
5784 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5785 %}
5786 ins_pipe( pipe_slow );
5787 %}
5788
5789 instruct loadD_partial(regD dst, memory mem) %{
5790 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
5791 match(Set dst (LoadD mem));
5792 ins_cost(145);
5793 format %{ "MOVLPD $dst,$mem" %}
5794 ins_encode %{
5795 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5796 %}
5797 ins_pipe( pipe_slow );
5798 %}
5799
5800 // Load to XMM register (single-precision floating point)
5801 // MOVSS instruction
5802 instruct loadF(regF dst, memory mem) %{
5803 predicate(UseSSE>=1);
5804 match(Set dst (LoadF mem));
5805 ins_cost(145);
5806 format %{ "MOVSS $dst,$mem" %}
5807 ins_encode %{
5808 __ movflt ($dst$$XMMRegister, $mem$$Address);
5809 %}
5810 ins_pipe( pipe_slow );
5811 %}
5812
5813 // Load Float
5814 instruct loadFPR(regFPR dst, memory mem) %{
5815 predicate(UseSSE==0);
5816 match(Set dst (LoadF mem));
5817
5818 ins_cost(150);
5819 format %{ "FLD_S ST,$mem\n\t"
5820 "FSTP $dst" %}
5821 opcode(0xD9); /* D9 /0 */
5822 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5823 Pop_Reg_FPR(dst) );
5824 ins_pipe( fpu_reg_mem );
5825 %}
5826
5827 // Load Effective Address
5828 instruct leaP8(eRegP dst, indOffset8 mem) %{
5829 match(Set dst mem);
5830
5831 ins_cost(110);
5832 format %{ "LEA $dst,$mem" %}
5833 opcode(0x8D);
5834 ins_encode( OpcP, RegMem(dst,mem));
5835 ins_pipe( ialu_reg_reg_fat );
5836 %}
5837
5838 instruct leaP32(eRegP dst, indOffset32 mem) %{
5839 match(Set dst mem);
5840
5841 ins_cost(110);
5842 format %{ "LEA $dst,$mem" %}
5843 opcode(0x8D);
5844 ins_encode( OpcP, RegMem(dst,mem));
5845 ins_pipe( ialu_reg_reg_fat );
5846 %}
5847
5848 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
5849 match(Set dst mem);
5850
5851 ins_cost(110);
5852 format %{ "LEA $dst,$mem" %}
5853 opcode(0x8D);
5854 ins_encode( OpcP, RegMem(dst,mem));
5855 ins_pipe( ialu_reg_reg_fat );
5856 %}
5857
5858 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
5859 match(Set dst mem);
5860
5861 ins_cost(110);
5862 format %{ "LEA $dst,$mem" %}
5863 opcode(0x8D);
5864 ins_encode( OpcP, RegMem(dst,mem));
5865 ins_pipe( ialu_reg_reg_fat );
5866 %}
5867
5868 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
5869 match(Set dst mem);
5870
5871 ins_cost(110);
5872 format %{ "LEA $dst,$mem" %}
5873 opcode(0x8D);
5874 ins_encode( OpcP, RegMem(dst,mem));
5875 ins_pipe( ialu_reg_reg_fat );
5876 %}
5877
5878 // Load Constant
5879 instruct loadConI(rRegI dst, immI src) %{
5880 match(Set dst src);
5881
5882 format %{ "MOV $dst,$src" %}
5883 ins_encode( LdImmI(dst, src) );
5884 ins_pipe( ialu_reg_fat );
5885 %}
5886
5887 // Load Constant zero
5888 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
5889 match(Set dst src);
5890 effect(KILL cr);
5891
5892 ins_cost(50);
5893 format %{ "XOR $dst,$dst" %}
5894 opcode(0x33); /* + rd */
5895 ins_encode( OpcP, RegReg( dst, dst ) );
5896 ins_pipe( ialu_reg );
5897 %}
5898
5899 instruct loadConP(eRegP dst, immP src) %{
5900 match(Set dst src);
5901
5902 format %{ "MOV $dst,$src" %}
5903 opcode(0xB8); /* + rd */
5904 ins_encode( LdImmP(dst, src) );
5905 ins_pipe( ialu_reg_fat );
5906 %}
5907
5908 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
5909 match(Set dst src);
5910 effect(KILL cr);
5911 ins_cost(200);
5912 format %{ "MOV $dst.lo,$src.lo\n\t"
5913 "MOV $dst.hi,$src.hi" %}
5914 opcode(0xB8);
5915 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
5916 ins_pipe( ialu_reg_long_fat );
5917 %}
5918
5919 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
5920 match(Set dst src);
5921 effect(KILL cr);
5922 ins_cost(150);
5923 format %{ "XOR $dst.lo,$dst.lo\n\t"
5924 "XOR $dst.hi,$dst.hi" %}
5925 opcode(0x33,0x33);
5926 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
5927 ins_pipe( ialu_reg_long );
5928 %}
5929
5930 // The instruction usage is guarded by predicate in operand immFPR().
5931 instruct loadConFPR(regFPR dst, immFPR con) %{
5932 match(Set dst con);
5933 ins_cost(125);
5934 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
5935 "FSTP $dst" %}
5936 ins_encode %{
5937 __ fld_s($constantaddress($con));
5938 __ fstp_d($dst$$reg);
5939 %}
5940 ins_pipe(fpu_reg_con);
5941 %}
5942
5943 // The instruction usage is guarded by predicate in operand immFPR0().
5944 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
5945 match(Set dst con);
5946 ins_cost(125);
5947 format %{ "FLDZ ST\n\t"
5948 "FSTP $dst" %}
5949 ins_encode %{
5950 __ fldz();
5951 __ fstp_d($dst$$reg);
5952 %}
5953 ins_pipe(fpu_reg_con);
5954 %}
5955
5956 // The instruction usage is guarded by predicate in operand immFPR1().
5957 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
5958 match(Set dst con);
5959 ins_cost(125);
5960 format %{ "FLD1 ST\n\t"
5961 "FSTP $dst" %}
5962 ins_encode %{
5963 __ fld1();
5964 __ fstp_d($dst$$reg);
5965 %}
5966 ins_pipe(fpu_reg_con);
5967 %}
5968
5969 // The instruction usage is guarded by predicate in operand immF().
5970 instruct loadConF(regF dst, immF con) %{
5971 match(Set dst con);
5972 ins_cost(125);
5973 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
5974 ins_encode %{
5975 __ movflt($dst$$XMMRegister, $constantaddress($con));
5976 %}
5977 ins_pipe(pipe_slow);
5978 %}
5979
5980 // The instruction usage is guarded by predicate in operand immF0().
5981 instruct loadConF0(regF dst, immF0 src) %{
5982 match(Set dst src);
5983 ins_cost(100);
5984 format %{ "XORPS $dst,$dst\t# float 0.0" %}
5985 ins_encode %{
5986 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5987 %}
5988 ins_pipe(pipe_slow);
5989 %}
5990
5991 // The instruction usage is guarded by predicate in operand immDPR().
5992 instruct loadConDPR(regDPR dst, immDPR con) %{
5993 match(Set dst con);
5994 ins_cost(125);
5995
5996 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
5997 "FSTP $dst" %}
5998 ins_encode %{
5999 __ fld_d($constantaddress($con));
6000 __ fstp_d($dst$$reg);
6001 %}
6002 ins_pipe(fpu_reg_con);
6003 %}
6004
6005 // The instruction usage is guarded by predicate in operand immDPR0().
6006 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6007 match(Set dst con);
6008 ins_cost(125);
6009
6010 format %{ "FLDZ ST\n\t"
6011 "FSTP $dst" %}
6012 ins_encode %{
6013 __ fldz();
6014 __ fstp_d($dst$$reg);
6015 %}
6016 ins_pipe(fpu_reg_con);
6017 %}
6018
6019 // The instruction usage is guarded by predicate in operand immDPR1().
6020 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6021 match(Set dst con);
6022 ins_cost(125);
6023
6024 format %{ "FLD1 ST\n\t"
6025 "FSTP $dst" %}
6026 ins_encode %{
6027 __ fld1();
6028 __ fstp_d($dst$$reg);
6029 %}
6030 ins_pipe(fpu_reg_con);
6031 %}
6032
6033 // The instruction usage is guarded by predicate in operand immD().
6034 instruct loadConD(regD dst, immD con) %{
6035 match(Set dst con);
6036 ins_cost(125);
6037 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6038 ins_encode %{
6039 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6040 %}
6041 ins_pipe(pipe_slow);
6042 %}
6043
6044 // The instruction usage is guarded by predicate in operand immD0().
6045 instruct loadConD0(regD dst, immD0 src) %{
6046 match(Set dst src);
6047 ins_cost(100);
6048 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6049 ins_encode %{
6050 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6051 %}
6052 ins_pipe( pipe_slow );
6053 %}
6054
6055 // Load Stack Slot
6056 instruct loadSSI(rRegI dst, stackSlotI src) %{
6057 match(Set dst src);
6058 ins_cost(125);
6059
6060 format %{ "MOV $dst,$src" %}
6061 opcode(0x8B);
6062 ins_encode( OpcP, RegMem(dst,src));
6063 ins_pipe( ialu_reg_mem );
6064 %}
6065
6066 instruct loadSSL(eRegL dst, stackSlotL src) %{
6067 match(Set dst src);
6068
6069 ins_cost(200);
6070 format %{ "MOV $dst,$src.lo\n\t"
6071 "MOV $dst+4,$src.hi" %}
6072 opcode(0x8B, 0x8B);
6073 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6074 ins_pipe( ialu_mem_long_reg );
6075 %}
6076
6077 // Load Stack Slot
6078 instruct loadSSP(eRegP dst, stackSlotP src) %{
6079 match(Set dst src);
6080 ins_cost(125);
6081
6082 format %{ "MOV $dst,$src" %}
6083 opcode(0x8B);
6084 ins_encode( OpcP, RegMem(dst,src));
6085 ins_pipe( ialu_reg_mem );
6086 %}
6087
6088 // Load Stack Slot
6089 instruct loadSSF(regFPR dst, stackSlotF src) %{
6090 match(Set dst src);
6091 ins_cost(125);
6092
6093 format %{ "FLD_S $src\n\t"
6094 "FSTP $dst" %}
6095 opcode(0xD9); /* D9 /0, FLD m32real */
6096 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6097 Pop_Reg_FPR(dst) );
6098 ins_pipe( fpu_reg_mem );
6099 %}
6100
6101 // Load Stack Slot
6102 instruct loadSSD(regDPR dst, stackSlotD src) %{
6103 match(Set dst src);
6104 ins_cost(125);
6105
6106 format %{ "FLD_D $src\n\t"
6107 "FSTP $dst" %}
6108 opcode(0xDD); /* DD /0, FLD m64real */
6109 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6110 Pop_Reg_DPR(dst) );
6111 ins_pipe( fpu_reg_mem );
6112 %}
6113
6114 // Prefetch instructions.
6115 // Must be safe to execute with invalid address (cannot fault).
6116
6117 instruct prefetchr0( memory mem ) %{
6118 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6119 match(PrefetchRead mem);
6120 ins_cost(0);
6121 size(0);
6122 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6123 ins_encode();
6124 ins_pipe(empty);
6125 %}
6126
6127 instruct prefetchr( memory mem ) %{
6128 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6129 match(PrefetchRead mem);
6130 ins_cost(100);
6131
6132 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6133 ins_encode %{
6134 __ prefetchr($mem$$Address);
6135 %}
6136 ins_pipe(ialu_mem);
6137 %}
6138
6139 instruct prefetchrNTA( memory mem ) %{
6140 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6141 match(PrefetchRead mem);
6142 ins_cost(100);
6143
6144 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6145 ins_encode %{
6146 __ prefetchnta($mem$$Address);
6147 %}
6148 ins_pipe(ialu_mem);
6149 %}
6150
6151 instruct prefetchrT0( memory mem ) %{
6152 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6153 match(PrefetchRead mem);
6154 ins_cost(100);
6155
6156 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6157 ins_encode %{
6158 __ prefetcht0($mem$$Address);
6159 %}
6160 ins_pipe(ialu_mem);
6161 %}
6162
6163 instruct prefetchrT2( memory mem ) %{
6164 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6165 match(PrefetchRead mem);
6166 ins_cost(100);
6167
6168 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6169 ins_encode %{
6170 __ prefetcht2($mem$$Address);
6171 %}
6172 ins_pipe(ialu_mem);
6173 %}
6174
6175 instruct prefetchw0( memory mem ) %{
6176 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6177 match(PrefetchWrite mem);
6178 ins_cost(0);
6179 size(0);
6180 format %{ "Prefetch (non-SSE is empty encoding)" %}
6181 ins_encode();
6182 ins_pipe(empty);
6183 %}
6184
6185 instruct prefetchw( memory mem ) %{
6186 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6187 match( PrefetchWrite mem );
6188 ins_cost(100);
6189
6190 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6191 ins_encode %{
6192 __ prefetchw($mem$$Address);
6193 %}
6194 ins_pipe(ialu_mem);
6195 %}
6196
6197 instruct prefetchwNTA( memory mem ) %{
6198 predicate(UseSSE>=1);
6199 match(PrefetchWrite mem);
6200 ins_cost(100);
6201
6202 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6203 ins_encode %{
6204 __ prefetchnta($mem$$Address);
6205 %}
6206 ins_pipe(ialu_mem);
6207 %}
6208
6209 // Prefetch instructions for allocation.
6210
6211 instruct prefetchAlloc0( memory mem ) %{
6212 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6213 match(PrefetchAllocation mem);
6214 ins_cost(0);
6215 size(0);
6216 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6217 ins_encode();
6218 ins_pipe(empty);
6219 %}
6220
6221 instruct prefetchAlloc( memory mem ) %{
6222 predicate(AllocatePrefetchInstr==3);
6223 match( PrefetchAllocation mem );
6224 ins_cost(100);
6225
6226 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6227 ins_encode %{
6228 __ prefetchw($mem$$Address);
6229 %}
6230 ins_pipe(ialu_mem);
6231 %}
6232
6233 instruct prefetchAllocNTA( memory mem ) %{
6234 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6235 match(PrefetchAllocation mem);
6236 ins_cost(100);
6237
6238 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6239 ins_encode %{
6240 __ prefetchnta($mem$$Address);
6241 %}
6242 ins_pipe(ialu_mem);
6243 %}
6244
6245 instruct prefetchAllocT0( memory mem ) %{
6246 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6247 match(PrefetchAllocation mem);
6248 ins_cost(100);
6249
6250 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6251 ins_encode %{
6252 __ prefetcht0($mem$$Address);
6253 %}
6254 ins_pipe(ialu_mem);
6255 %}
6256
6257 instruct prefetchAllocT2( memory mem ) %{
6258 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6259 match(PrefetchAllocation mem);
6260 ins_cost(100);
6261
6262 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6263 ins_encode %{
6264 __ prefetcht2($mem$$Address);
6265 %}
6266 ins_pipe(ialu_mem);
6267 %}
6268
6269 //----------Store Instructions-------------------------------------------------
6270
6271 // Store Byte
6272 instruct storeB(memory mem, xRegI src) %{
6273 match(Set mem (StoreB mem src));
6274
6275 ins_cost(125);
6276 format %{ "MOV8 $mem,$src" %}
6277 opcode(0x88);
6278 ins_encode( OpcP, RegMem( src, mem ) );
6279 ins_pipe( ialu_mem_reg );
6280 %}
6281
6282 // Store Char/Short
6283 instruct storeC(memory mem, rRegI src) %{
6284 match(Set mem (StoreC mem src));
6285
6286 ins_cost(125);
6287 format %{ "MOV16 $mem,$src" %}
6288 opcode(0x89, 0x66);
6289 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6290 ins_pipe( ialu_mem_reg );
6291 %}
6292
6293 // Store Integer
6294 instruct storeI(memory mem, rRegI src) %{
6295 match(Set mem (StoreI mem src));
6296
6297 ins_cost(125);
6298 format %{ "MOV $mem,$src" %}
6299 opcode(0x89);
6300 ins_encode( OpcP, RegMem( src, mem ) );
6301 ins_pipe( ialu_mem_reg );
6302 %}
6303
6304 // Store Long
6305 instruct storeL(long_memory mem, eRegL src) %{
6306 predicate(!((StoreLNode*)n)->require_atomic_access());
6307 match(Set mem (StoreL mem src));
6308
6309 ins_cost(200);
6310 format %{ "MOV $mem,$src.lo\n\t"
6311 "MOV $mem+4,$src.hi" %}
6312 opcode(0x89, 0x89);
6313 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6314 ins_pipe( ialu_mem_long_reg );
6315 %}
6316
6317 // Store Long to Integer
6318 instruct storeL2I(memory mem, eRegL src) %{
6319 match(Set mem (StoreI mem (ConvL2I src)));
6320
6321 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6322 ins_encode %{
6323 __ movl($mem$$Address, $src$$Register);
6324 %}
6325 ins_pipe(ialu_mem_reg);
6326 %}
6327
6328 // Volatile Store Long. Must be atomic, so move it into
6329 // the FP TOS and then do a 64-bit FIST. Has to probe the
6330 // target address before the store (for null-ptr checks)
6331 // so the memory operand is used twice in the encoding.
6332 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6333 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6334 match(Set mem (StoreL mem src));
6335 effect( KILL cr );
6336 ins_cost(400);
6337 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6338 "FILD $src\n\t"
6339 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6340 opcode(0x3B);
6341 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6342 ins_pipe( fpu_reg_mem );
6343 %}
6344
6345 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6346 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6347 match(Set mem (StoreL mem src));
6348 effect( TEMP tmp, KILL cr );
6349 ins_cost(380);
6350 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6351 "MOVSD $tmp,$src\n\t"
6352 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6353 ins_encode %{
6354 __ cmpl(rax, $mem$$Address);
6355 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6356 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6357 %}
6358 ins_pipe( pipe_slow );
6359 %}
6360
6361 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6362 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6363 match(Set mem (StoreL mem src));
6364 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6365 ins_cost(360);
6366 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6367 "MOVD $tmp,$src.lo\n\t"
6368 "MOVD $tmp2,$src.hi\n\t"
6369 "PUNPCKLDQ $tmp,$tmp2\n\t"
6370 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6371 ins_encode %{
6372 __ cmpl(rax, $mem$$Address);
6373 __ movdl($tmp$$XMMRegister, $src$$Register);
6374 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6375 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6376 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6377 %}
6378 ins_pipe( pipe_slow );
6379 %}
6380
6381 // Store Pointer; for storing unknown oops and raw pointers
6382 instruct storeP(memory mem, anyRegP src) %{
6383 match(Set mem (StoreP mem src));
6384
6385 ins_cost(125);
6386 format %{ "MOV $mem,$src" %}
6387 opcode(0x89);
6388 ins_encode( OpcP, RegMem( src, mem ) );
6389 ins_pipe( ialu_mem_reg );
6390 %}
6391
6392 // Store Integer Immediate
6393 instruct storeImmI(memory mem, immI src) %{
6394 match(Set mem (StoreI mem src));
6395
6396 ins_cost(150);
6397 format %{ "MOV $mem,$src" %}
6398 opcode(0xC7); /* C7 /0 */
6399 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6400 ins_pipe( ialu_mem_imm );
6401 %}
6402
6403 // Store Short/Char Immediate
6404 instruct storeImmI16(memory mem, immI16 src) %{
6405 predicate(UseStoreImmI16);
6406 match(Set mem (StoreC mem src));
6407
6408 ins_cost(150);
6409 format %{ "MOV16 $mem,$src" %}
6410 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6411 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6412 ins_pipe( ialu_mem_imm );
6413 %}
6414
6415 // Store Pointer Immediate; null pointers or constant oops that do not
6416 // need card-mark barriers.
6417 instruct storeImmP(memory mem, immP src) %{
6418 match(Set mem (StoreP mem src));
6419
6420 ins_cost(150);
6421 format %{ "MOV $mem,$src" %}
6422 opcode(0xC7); /* C7 /0 */
6423 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6424 ins_pipe( ialu_mem_imm );
6425 %}
6426
6427 // Store Byte Immediate
6428 instruct storeImmB(memory mem, immI8 src) %{
6429 match(Set mem (StoreB mem src));
6430
6431 ins_cost(150);
6432 format %{ "MOV8 $mem,$src" %}
6433 opcode(0xC6); /* C6 /0 */
6434 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6435 ins_pipe( ialu_mem_imm );
6436 %}
6437
6438 // Store CMS card-mark Immediate
6439 instruct storeImmCM(memory mem, immI8 src) %{
6440 match(Set mem (StoreCM mem src));
6441
6442 ins_cost(150);
6443 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6444 opcode(0xC6); /* C6 /0 */
6445 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6446 ins_pipe( ialu_mem_imm );
6447 %}
6448
6449 // Store Double
6450 instruct storeDPR( memory mem, regDPR1 src) %{
6451 predicate(UseSSE<=1);
6452 match(Set mem (StoreD mem src));
6453
6454 ins_cost(100);
6455 format %{ "FST_D $mem,$src" %}
6456 opcode(0xDD); /* DD /2 */
6457 ins_encode( enc_FPR_store(mem,src) );
6458 ins_pipe( fpu_mem_reg );
6459 %}
6460
6461 // Store double does rounding on x86
6462 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6463 predicate(UseSSE<=1);
6464 match(Set mem (StoreD mem (RoundDouble src)));
6465
6466 ins_cost(100);
6467 format %{ "FST_D $mem,$src\t# round" %}
6468 opcode(0xDD); /* DD /2 */
6469 ins_encode( enc_FPR_store(mem,src) );
6470 ins_pipe( fpu_mem_reg );
6471 %}
6472
6473 // Store XMM register to memory (double-precision floating points)
6474 // MOVSD instruction
6475 instruct storeD(memory mem, regD src) %{
6476 predicate(UseSSE>=2);
6477 match(Set mem (StoreD mem src));
6478 ins_cost(95);
6479 format %{ "MOVSD $mem,$src" %}
6480 ins_encode %{
6481 __ movdbl($mem$$Address, $src$$XMMRegister);
6482 %}
6483 ins_pipe( pipe_slow );
6484 %}
6485
6486 // Store XMM register to memory (single-precision floating point)
6487 // MOVSS instruction
6488 instruct storeF(memory mem, regF src) %{
6489 predicate(UseSSE>=1);
6490 match(Set mem (StoreF mem src));
6491 ins_cost(95);
6492 format %{ "MOVSS $mem,$src" %}
6493 ins_encode %{
6494 __ movflt($mem$$Address, $src$$XMMRegister);
6495 %}
6496 ins_pipe( pipe_slow );
6497 %}
6498
6499 // Store Float
6500 instruct storeFPR( memory mem, regFPR1 src) %{
6501 predicate(UseSSE==0);
6502 match(Set mem (StoreF mem src));
6503
6504 ins_cost(100);
6505 format %{ "FST_S $mem,$src" %}
6506 opcode(0xD9); /* D9 /2 */
6507 ins_encode( enc_FPR_store(mem,src) );
6508 ins_pipe( fpu_mem_reg );
6509 %}
6510
6511 // Store Float does rounding on x86
6512 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
6513 predicate(UseSSE==0);
6514 match(Set mem (StoreF mem (RoundFloat src)));
6515
6516 ins_cost(100);
6517 format %{ "FST_S $mem,$src\t# round" %}
6518 opcode(0xD9); /* D9 /2 */
6519 ins_encode( enc_FPR_store(mem,src) );
6520 ins_pipe( fpu_mem_reg );
6521 %}
6522
6523 // Store Float does rounding on x86
6524 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
6525 predicate(UseSSE<=1);
6526 match(Set mem (StoreF mem (ConvD2F src)));
6527
6528 ins_cost(100);
6529 format %{ "FST_S $mem,$src\t# D-round" %}
6530 opcode(0xD9); /* D9 /2 */
6531 ins_encode( enc_FPR_store(mem,src) );
6532 ins_pipe( fpu_mem_reg );
6533 %}
6534
6535 // Store immediate Float value (it is faster than store from FPU register)
6536 // The instruction usage is guarded by predicate in operand immFPR().
6537 instruct storeFPR_imm( memory mem, immFPR src) %{
6538 match(Set mem (StoreF mem src));
6539
6540 ins_cost(50);
6541 format %{ "MOV $mem,$src\t# store float" %}
6542 opcode(0xC7); /* C7 /0 */
6543 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
6544 ins_pipe( ialu_mem_imm );
6545 %}
6546
6547 // Store immediate Float value (it is faster than store from XMM register)
6548 // The instruction usage is guarded by predicate in operand immF().
6549 instruct storeF_imm( memory mem, immF src) %{
6550 match(Set mem (StoreF mem src));
6551
6552 ins_cost(50);
6553 format %{ "MOV $mem,$src\t# store float" %}
6554 opcode(0xC7); /* C7 /0 */
6555 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
6556 ins_pipe( ialu_mem_imm );
6557 %}
6558
6559 // Store Integer to stack slot
6560 instruct storeSSI(stackSlotI dst, rRegI src) %{
6561 match(Set dst src);
6562
6563 ins_cost(100);
6564 format %{ "MOV $dst,$src" %}
6565 opcode(0x89);
6566 ins_encode( OpcPRegSS( dst, src ) );
6567 ins_pipe( ialu_mem_reg );
6568 %}
6569
6570 // Store Integer to stack slot
6571 instruct storeSSP(stackSlotP dst, eRegP src) %{
6572 match(Set dst src);
6573
6574 ins_cost(100);
6575 format %{ "MOV $dst,$src" %}
6576 opcode(0x89);
6577 ins_encode( OpcPRegSS( dst, src ) );
6578 ins_pipe( ialu_mem_reg );
6579 %}
6580
6581 // Store Long to stack slot
6582 instruct storeSSL(stackSlotL dst, eRegL src) %{
6583 match(Set dst src);
6584
6585 ins_cost(200);
6586 format %{ "MOV $dst,$src.lo\n\t"
6587 "MOV $dst+4,$src.hi" %}
6588 opcode(0x89, 0x89);
6589 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
6590 ins_pipe( ialu_mem_long_reg );
6591 %}
6592
6593 //----------MemBar Instructions-----------------------------------------------
6594 // Memory barrier flavors
6595
6596 instruct membar_acquire() %{
6597 match(MemBarAcquire);
6598 match(LoadFence);
6599 ins_cost(400);
6600
6601 size(0);
6602 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6603 ins_encode();
6604 ins_pipe(empty);
6605 %}
6606
6607 instruct membar_acquire_lock() %{
6608 match(MemBarAcquireLock);
6609 ins_cost(0);
6610
6611 size(0);
6612 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6613 ins_encode( );
6614 ins_pipe(empty);
6615 %}
6616
6617 instruct membar_release() %{
6618 match(MemBarRelease);
6619 match(StoreFence);
6620 ins_cost(400);
6621
6622 size(0);
6623 format %{ "MEMBAR-release ! (empty encoding)" %}
6624 ins_encode( );
6625 ins_pipe(empty);
6626 %}
6627
6628 instruct membar_release_lock() %{
6629 match(MemBarReleaseLock);
6630 ins_cost(0);
6631
6632 size(0);
6633 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6634 ins_encode( );
6635 ins_pipe(empty);
6636 %}
6637
6638 instruct membar_volatile(eFlagsReg cr) %{
6639 match(MemBarVolatile);
6640 effect(KILL cr);
6641 ins_cost(400);
6642
6643 format %{
6644 $$template
6645 if (os::is_MP()) {
6646 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
6647 } else {
6648 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6649 }
6650 %}
6651 ins_encode %{
6652 __ membar(Assembler::StoreLoad);
6653 %}
6654 ins_pipe(pipe_slow);
6655 %}
6656
6657 instruct unnecessary_membar_volatile() %{
6658 match(MemBarVolatile);
6659 predicate(Matcher::post_store_load_barrier(n));
6660 ins_cost(0);
6661
6662 size(0);
6663 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6664 ins_encode( );
6665 ins_pipe(empty);
6666 %}
6667
6668 instruct membar_storestore() %{
6669 match(MemBarStoreStore);
6670 ins_cost(0);
6671
6672 size(0);
6673 format %{ "MEMBAR-storestore (empty encoding)" %}
6674 ins_encode( );
6675 ins_pipe(empty);
6676 %}
6677
6678 //----------Move Instructions--------------------------------------------------
6679 instruct castX2P(eAXRegP dst, eAXRegI src) %{
6680 match(Set dst (CastX2P src));
6681 format %{ "# X2P $dst, $src" %}
6682 ins_encode( /*empty encoding*/ );
6683 ins_cost(0);
6684 ins_pipe(empty);
6685 %}
6686
6687 instruct castP2X(rRegI dst, eRegP src ) %{
6688 match(Set dst (CastP2X src));
6689 ins_cost(50);
6690 format %{ "MOV $dst, $src\t# CastP2X" %}
6691 ins_encode( enc_Copy( dst, src) );
6692 ins_pipe( ialu_reg_reg );
6693 %}
6694
6695 //----------Conditional Move---------------------------------------------------
6696 // Conditional move
6697 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
6698 predicate(!VM_Version::supports_cmov() );
6699 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6700 ins_cost(200);
6701 format %{ "J$cop,us skip\t# signed cmove\n\t"
6702 "MOV $dst,$src\n"
6703 "skip:" %}
6704 ins_encode %{
6705 Label Lskip;
6706 // Invert sense of branch from sense of CMOV
6707 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6708 __ movl($dst$$Register, $src$$Register);
6709 __ bind(Lskip);
6710 %}
6711 ins_pipe( pipe_cmov_reg );
6712 %}
6713
6714 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
6715 predicate(!VM_Version::supports_cmov() );
6716 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6717 ins_cost(200);
6718 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
6719 "MOV $dst,$src\n"
6720 "skip:" %}
6721 ins_encode %{
6722 Label Lskip;
6723 // Invert sense of branch from sense of CMOV
6724 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6725 __ movl($dst$$Register, $src$$Register);
6726 __ bind(Lskip);
6727 %}
6728 ins_pipe( pipe_cmov_reg );
6729 %}
6730
6731 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
6732 predicate(VM_Version::supports_cmov() );
6733 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6734 ins_cost(200);
6735 format %{ "CMOV$cop $dst,$src" %}
6736 opcode(0x0F,0x40);
6737 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6738 ins_pipe( pipe_cmov_reg );
6739 %}
6740
6741 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
6742 predicate(VM_Version::supports_cmov() );
6743 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6744 ins_cost(200);
6745 format %{ "CMOV$cop $dst,$src" %}
6746 opcode(0x0F,0x40);
6747 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6748 ins_pipe( pipe_cmov_reg );
6749 %}
6750
6751 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
6752 predicate(VM_Version::supports_cmov() );
6753 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6754 ins_cost(200);
6755 expand %{
6756 cmovI_regU(cop, cr, dst, src);
6757 %}
6758 %}
6759
6760 // Conditional move
6761 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
6762 predicate(VM_Version::supports_cmov() );
6763 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6764 ins_cost(250);
6765 format %{ "CMOV$cop $dst,$src" %}
6766 opcode(0x0F,0x40);
6767 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6768 ins_pipe( pipe_cmov_mem );
6769 %}
6770
6771 // Conditional move
6772 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
6773 predicate(VM_Version::supports_cmov() );
6774 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6775 ins_cost(250);
6776 format %{ "CMOV$cop $dst,$src" %}
6777 opcode(0x0F,0x40);
6778 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6779 ins_pipe( pipe_cmov_mem );
6780 %}
6781
6782 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
6783 predicate(VM_Version::supports_cmov() );
6784 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6785 ins_cost(250);
6786 expand %{
6787 cmovI_memU(cop, cr, dst, src);
6788 %}
6789 %}
6790
6791 // Conditional move
6792 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6793 predicate(VM_Version::supports_cmov() );
6794 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6795 ins_cost(200);
6796 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6797 opcode(0x0F,0x40);
6798 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6799 ins_pipe( pipe_cmov_reg );
6800 %}
6801
6802 // Conditional move (non-P6 version)
6803 // Note: a CMoveP is generated for stubs and native wrappers
6804 // regardless of whether we are on a P6, so we
6805 // emulate a cmov here
6806 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6807 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6808 ins_cost(300);
6809 format %{ "Jn$cop skip\n\t"
6810 "MOV $dst,$src\t# pointer\n"
6811 "skip:" %}
6812 opcode(0x8b);
6813 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
6814 ins_pipe( pipe_cmov_reg );
6815 %}
6816
6817 // Conditional move
6818 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
6819 predicate(VM_Version::supports_cmov() );
6820 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6821 ins_cost(200);
6822 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6823 opcode(0x0F,0x40);
6824 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6825 ins_pipe( pipe_cmov_reg );
6826 %}
6827
6828 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
6829 predicate(VM_Version::supports_cmov() );
6830 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6831 ins_cost(200);
6832 expand %{
6833 cmovP_regU(cop, cr, dst, src);
6834 %}
6835 %}
6836
6837 // DISABLED: Requires the ADLC to emit a bottom_type call that
6838 // correctly meets the two pointer arguments; one is an incoming
6839 // register but the other is a memory operand. ALSO appears to
6840 // be buggy with implicit null checks.
6841 //
6842 //// Conditional move
6843 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
6844 // predicate(VM_Version::supports_cmov() );
6845 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6846 // ins_cost(250);
6847 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6848 // opcode(0x0F,0x40);
6849 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6850 // ins_pipe( pipe_cmov_mem );
6851 //%}
6852 //
6853 //// Conditional move
6854 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
6855 // predicate(VM_Version::supports_cmov() );
6856 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6857 // ins_cost(250);
6858 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6859 // opcode(0x0F,0x40);
6860 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6861 // ins_pipe( pipe_cmov_mem );
6862 //%}
6863
6864 // Conditional move
6865 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
6866 predicate(UseSSE<=1);
6867 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6868 ins_cost(200);
6869 format %{ "FCMOV$cop $dst,$src\t# double" %}
6870 opcode(0xDA);
6871 ins_encode( enc_cmov_dpr(cop,src) );
6872 ins_pipe( pipe_cmovDPR_reg );
6873 %}
6874
6875 // Conditional move
6876 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
6877 predicate(UseSSE==0);
6878 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6879 ins_cost(200);
6880 format %{ "FCMOV$cop $dst,$src\t# float" %}
6881 opcode(0xDA);
6882 ins_encode( enc_cmov_dpr(cop,src) );
6883 ins_pipe( pipe_cmovDPR_reg );
6884 %}
6885
6886 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6887 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
6888 predicate(UseSSE<=1);
6889 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6890 ins_cost(200);
6891 format %{ "Jn$cop skip\n\t"
6892 "MOV $dst,$src\t# double\n"
6893 "skip:" %}
6894 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6895 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
6896 ins_pipe( pipe_cmovDPR_reg );
6897 %}
6898
6899 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6900 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
6901 predicate(UseSSE==0);
6902 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6903 ins_cost(200);
6904 format %{ "Jn$cop skip\n\t"
6905 "MOV $dst,$src\t# float\n"
6906 "skip:" %}
6907 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6908 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
6909 ins_pipe( pipe_cmovDPR_reg );
6910 %}
6911
6912 // No CMOVE with SSE/SSE2
6913 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
6914 predicate (UseSSE>=1);
6915 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6916 ins_cost(200);
6917 format %{ "Jn$cop skip\n\t"
6918 "MOVSS $dst,$src\t# float\n"
6919 "skip:" %}
6920 ins_encode %{
6921 Label skip;
6922 // Invert sense of branch from sense of CMOV
6923 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6924 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6925 __ bind(skip);
6926 %}
6927 ins_pipe( pipe_slow );
6928 %}
6929
6930 // No CMOVE with SSE/SSE2
6931 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
6932 predicate (UseSSE>=2);
6933 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6934 ins_cost(200);
6935 format %{ "Jn$cop skip\n\t"
6936 "MOVSD $dst,$src\t# float\n"
6937 "skip:" %}
6938 ins_encode %{
6939 Label skip;
6940 // Invert sense of branch from sense of CMOV
6941 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6942 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6943 __ bind(skip);
6944 %}
6945 ins_pipe( pipe_slow );
6946 %}
6947
6948 // unsigned version
6949 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
6950 predicate (UseSSE>=1);
6951 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6952 ins_cost(200);
6953 format %{ "Jn$cop skip\n\t"
6954 "MOVSS $dst,$src\t# float\n"
6955 "skip:" %}
6956 ins_encode %{
6957 Label skip;
6958 // Invert sense of branch from sense of CMOV
6959 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6960 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6961 __ bind(skip);
6962 %}
6963 ins_pipe( pipe_slow );
6964 %}
6965
6966 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
6967 predicate (UseSSE>=1);
6968 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6969 ins_cost(200);
6970 expand %{
6971 fcmovF_regU(cop, cr, dst, src);
6972 %}
6973 %}
6974
6975 // unsigned version
6976 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
6977 predicate (UseSSE>=2);
6978 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6979 ins_cost(200);
6980 format %{ "Jn$cop skip\n\t"
6981 "MOVSD $dst,$src\t# float\n"
6982 "skip:" %}
6983 ins_encode %{
6984 Label skip;
6985 // Invert sense of branch from sense of CMOV
6986 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6987 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6988 __ bind(skip);
6989 %}
6990 ins_pipe( pipe_slow );
6991 %}
6992
6993 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
6994 predicate (UseSSE>=2);
6995 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6996 ins_cost(200);
6997 expand %{
6998 fcmovD_regU(cop, cr, dst, src);
6999 %}
7000 %}
7001
7002 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7003 predicate(VM_Version::supports_cmov() );
7004 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7005 ins_cost(200);
7006 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7007 "CMOV$cop $dst.hi,$src.hi" %}
7008 opcode(0x0F,0x40);
7009 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7010 ins_pipe( pipe_cmov_reg_long );
7011 %}
7012
7013 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7014 predicate(VM_Version::supports_cmov() );
7015 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7016 ins_cost(200);
7017 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7018 "CMOV$cop $dst.hi,$src.hi" %}
7019 opcode(0x0F,0x40);
7020 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7021 ins_pipe( pipe_cmov_reg_long );
7022 %}
7023
7024 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7025 predicate(VM_Version::supports_cmov() );
7026 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7027 ins_cost(200);
7028 expand %{
7029 cmovL_regU(cop, cr, dst, src);
7030 %}
7031 %}
7032
7033 //----------Arithmetic Instructions--------------------------------------------
7034 //----------Addition Instructions----------------------------------------------
7035
7036 // Integer Addition Instructions
7037 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7038 match(Set dst (AddI dst src));
7039 effect(KILL cr);
7040
7041 size(2);
7042 format %{ "ADD $dst,$src" %}
7043 opcode(0x03);
7044 ins_encode( OpcP, RegReg( dst, src) );
7045 ins_pipe( ialu_reg_reg );
7046 %}
7047
7048 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7049 match(Set dst (AddI dst src));
7050 effect(KILL cr);
7051
7052 format %{ "ADD $dst,$src" %}
7053 opcode(0x81, 0x00); /* /0 id */
7054 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7055 ins_pipe( ialu_reg );
7056 %}
7057
7058 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7059 predicate(UseIncDec);
7060 match(Set dst (AddI dst src));
7061 effect(KILL cr);
7062
7063 size(1);
7064 format %{ "INC $dst" %}
7065 opcode(0x40); /* */
7066 ins_encode( Opc_plus( primary, dst ) );
7067 ins_pipe( ialu_reg );
7068 %}
7069
7070 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7071 match(Set dst (AddI src0 src1));
7072 ins_cost(110);
7073
7074 format %{ "LEA $dst,[$src0 + $src1]" %}
7075 opcode(0x8D); /* 0x8D /r */
7076 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7077 ins_pipe( ialu_reg_reg );
7078 %}
7079
7080 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7081 match(Set dst (AddP src0 src1));
7082 ins_cost(110);
7083
7084 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7085 opcode(0x8D); /* 0x8D /r */
7086 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7087 ins_pipe( ialu_reg_reg );
7088 %}
7089
7090 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7091 predicate(UseIncDec);
7092 match(Set dst (AddI dst src));
7093 effect(KILL cr);
7094
7095 size(1);
7096 format %{ "DEC $dst" %}
7097 opcode(0x48); /* */
7098 ins_encode( Opc_plus( primary, dst ) );
7099 ins_pipe( ialu_reg );
7100 %}
7101
7102 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7103 match(Set dst (AddP dst src));
7104 effect(KILL cr);
7105
7106 size(2);
7107 format %{ "ADD $dst,$src" %}
7108 opcode(0x03);
7109 ins_encode( OpcP, RegReg( dst, src) );
7110 ins_pipe( ialu_reg_reg );
7111 %}
7112
7113 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7114 match(Set dst (AddP dst src));
7115 effect(KILL cr);
7116
7117 format %{ "ADD $dst,$src" %}
7118 opcode(0x81,0x00); /* Opcode 81 /0 id */
7119 // ins_encode( RegImm( dst, src) );
7120 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7121 ins_pipe( ialu_reg );
7122 %}
7123
7124 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7125 match(Set dst (AddI dst (LoadI src)));
7126 effect(KILL cr);
7127
7128 ins_cost(125);
7129 format %{ "ADD $dst,$src" %}
7130 opcode(0x03);
7131 ins_encode( OpcP, RegMem( dst, src) );
7132 ins_pipe( ialu_reg_mem );
7133 %}
7134
7135 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7136 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7137 effect(KILL cr);
7138
7139 ins_cost(150);
7140 format %{ "ADD $dst,$src" %}
7141 opcode(0x01); /* Opcode 01 /r */
7142 ins_encode( OpcP, RegMem( src, dst ) );
7143 ins_pipe( ialu_mem_reg );
7144 %}
7145
7146 // Add Memory with Immediate
7147 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7148 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7149 effect(KILL cr);
7150
7151 ins_cost(125);
7152 format %{ "ADD $dst,$src" %}
7153 opcode(0x81); /* Opcode 81 /0 id */
7154 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7155 ins_pipe( ialu_mem_imm );
7156 %}
7157
7158 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7159 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7160 effect(KILL cr);
7161
7162 ins_cost(125);
7163 format %{ "INC $dst" %}
7164 opcode(0xFF); /* Opcode FF /0 */
7165 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7166 ins_pipe( ialu_mem_imm );
7167 %}
7168
7169 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7170 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7171 effect(KILL cr);
7172
7173 ins_cost(125);
7174 format %{ "DEC $dst" %}
7175 opcode(0xFF); /* Opcode FF /1 */
7176 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7177 ins_pipe( ialu_mem_imm );
7178 %}
7179
7180
7181 instruct checkCastPP( eRegP dst ) %{
7182 match(Set dst (CheckCastPP dst));
7183
7184 size(0);
7185 format %{ "#checkcastPP of $dst" %}
7186 ins_encode( /*empty encoding*/ );
7187 ins_pipe( empty );
7188 %}
7189
7190 instruct castPP( eRegP dst ) %{
7191 match(Set dst (CastPP dst));
7192 format %{ "#castPP of $dst" %}
7193 ins_encode( /*empty encoding*/ );
7194 ins_pipe( empty );
7195 %}
7196
7197 instruct castII( rRegI dst ) %{
7198 match(Set dst (CastII dst));
7199 format %{ "#castII of $dst" %}
7200 ins_encode( /*empty encoding*/ );
7201 ins_cost(0);
7202 ins_pipe( empty );
7203 %}
7204
7205
7206 // Load-locked - same as a regular pointer load when used with compare-swap
7207 instruct loadPLocked(eRegP dst, memory mem) %{
7208 match(Set dst (LoadPLocked mem));
7209
7210 ins_cost(125);
7211 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7212 opcode(0x8B);
7213 ins_encode( OpcP, RegMem(dst,mem));
7214 ins_pipe( ialu_reg_mem );
7215 %}
7216
7217 // Conditional-store of the updated heap-top.
7218 // Used during allocation of the shared heap.
7219 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7220 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7221 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7222 // EAX is killed if there is contention, but then it's also unused.
7223 // In the common case of no contention, EAX holds the new oop address.
7224 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7225 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7226 ins_pipe( pipe_cmpxchg );
7227 %}
7228
7229 // Conditional-store of an int value.
7230 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7231 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7232 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7233 effect(KILL oldval);
7234 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7235 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7236 ins_pipe( pipe_cmpxchg );
7237 %}
7238
7239 // Conditional-store of a long value.
7240 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7241 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7242 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7243 effect(KILL oldval);
7244 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7245 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7246 "XCHG EBX,ECX"
7247 %}
7248 ins_encode %{
7249 // Note: we need to swap rbx, and rcx before and after the
7250 // cmpxchg8 instruction because the instruction uses
7251 // rcx as the high order word of the new value to store but
7252 // our register encoding uses rbx.
7253 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7254 if( os::is_MP() )
7255 __ lock();
7256 __ cmpxchg8($mem$$Address);
7257 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7258 %}
7259 ins_pipe( pipe_cmpxchg );
7260 %}
7261
7262 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7263
7264 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7265 predicate(VM_Version::supports_cx8());
7266 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7267 effect(KILL cr, KILL oldval);
7268 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7269 "MOV $res,0\n\t"
7270 "JNE,s fail\n\t"
7271 "MOV $res,1\n"
7272 "fail:" %}
7273 ins_encode( enc_cmpxchg8(mem_ptr),
7274 enc_flags_ne_to_boolean(res) );
7275 ins_pipe( pipe_cmpxchg );
7276 %}
7277
7278 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7279 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7280 effect(KILL cr, KILL oldval);
7281 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7282 "MOV $res,0\n\t"
7283 "JNE,s fail\n\t"
7284 "MOV $res,1\n"
7285 "fail:" %}
7286 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7287 ins_pipe( pipe_cmpxchg );
7288 %}
7289
7290 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7291 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7292 effect(KILL cr, KILL oldval);
7293 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7294 "MOV $res,0\n\t"
7295 "JNE,s fail\n\t"
7296 "MOV $res,1\n"
7297 "fail:" %}
7298 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7299 ins_pipe( pipe_cmpxchg );
7300 %}
7301
7302 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7303 predicate(n->as_LoadStore()->result_not_used());
7304 match(Set dummy (GetAndAddI mem add));
7305 effect(KILL cr);
7306 format %{ "ADDL [$mem],$add" %}
7307 ins_encode %{
7308 if (os::is_MP()) { __ lock(); }
7309 __ addl($mem$$Address, $add$$constant);
7310 %}
7311 ins_pipe( pipe_cmpxchg );
7312 %}
7313
7314 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7315 match(Set newval (GetAndAddI mem newval));
7316 effect(KILL cr);
7317 format %{ "XADDL [$mem],$newval" %}
7318 ins_encode %{
7319 if (os::is_MP()) { __ lock(); }
7320 __ xaddl($mem$$Address, $newval$$Register);
7321 %}
7322 ins_pipe( pipe_cmpxchg );
7323 %}
7324
7325 instruct xchgI( memory mem, rRegI newval) %{
7326 match(Set newval (GetAndSetI mem newval));
7327 format %{ "XCHGL $newval,[$mem]" %}
7328 ins_encode %{
7329 __ xchgl($newval$$Register, $mem$$Address);
7330 %}
7331 ins_pipe( pipe_cmpxchg );
7332 %}
7333
7334 instruct xchgP( memory mem, pRegP newval) %{
7335 match(Set newval (GetAndSetP mem newval));
7336 format %{ "XCHGL $newval,[$mem]" %}
7337 ins_encode %{
7338 __ xchgl($newval$$Register, $mem$$Address);
7339 %}
7340 ins_pipe( pipe_cmpxchg );
7341 %}
7342
7343 //----------Subtraction Instructions-------------------------------------------
7344
7345 // Integer Subtraction Instructions
7346 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7347 match(Set dst (SubI dst src));
7348 effect(KILL cr);
7349
7350 size(2);
7351 format %{ "SUB $dst,$src" %}
7352 opcode(0x2B);
7353 ins_encode( OpcP, RegReg( dst, src) );
7354 ins_pipe( ialu_reg_reg );
7355 %}
7356
7357 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7358 match(Set dst (SubI dst src));
7359 effect(KILL cr);
7360
7361 format %{ "SUB $dst,$src" %}
7362 opcode(0x81,0x05); /* Opcode 81 /5 */
7363 // ins_encode( RegImm( dst, src) );
7364 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7365 ins_pipe( ialu_reg );
7366 %}
7367
7368 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7369 match(Set dst (SubI dst (LoadI src)));
7370 effect(KILL cr);
7371
7372 ins_cost(125);
7373 format %{ "SUB $dst,$src" %}
7374 opcode(0x2B);
7375 ins_encode( OpcP, RegMem( dst, src) );
7376 ins_pipe( ialu_reg_mem );
7377 %}
7378
7379 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7380 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7381 effect(KILL cr);
7382
7383 ins_cost(150);
7384 format %{ "SUB $dst,$src" %}
7385 opcode(0x29); /* Opcode 29 /r */
7386 ins_encode( OpcP, RegMem( src, dst ) );
7387 ins_pipe( ialu_mem_reg );
7388 %}
7389
7390 // Subtract from a pointer
7391 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7392 match(Set dst (AddP dst (SubI zero src)));
7393 effect(KILL cr);
7394
7395 size(2);
7396 format %{ "SUB $dst,$src" %}
7397 opcode(0x2B);
7398 ins_encode( OpcP, RegReg( dst, src) );
7399 ins_pipe( ialu_reg_reg );
7400 %}
7401
7402 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7403 match(Set dst (SubI zero dst));
7404 effect(KILL cr);
7405
7406 size(2);
7407 format %{ "NEG $dst" %}
7408 opcode(0xF7,0x03); // Opcode F7 /3
7409 ins_encode( OpcP, RegOpc( dst ) );
7410 ins_pipe( ialu_reg );
7411 %}
7412
7413 //----------Multiplication/Division Instructions-------------------------------
7414 // Integer Multiplication Instructions
7415 // Multiply Register
7416 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7417 match(Set dst (MulI dst src));
7418 effect(KILL cr);
7419
7420 size(3);
7421 ins_cost(300);
7422 format %{ "IMUL $dst,$src" %}
7423 opcode(0xAF, 0x0F);
7424 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7425 ins_pipe( ialu_reg_reg_alu0 );
7426 %}
7427
7428 // Multiply 32-bit Immediate
7429 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7430 match(Set dst (MulI src imm));
7431 effect(KILL cr);
7432
7433 ins_cost(300);
7434 format %{ "IMUL $dst,$src,$imm" %}
7435 opcode(0x69); /* 69 /r id */
7436 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7437 ins_pipe( ialu_reg_reg_alu0 );
7438 %}
7439
7440 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7441 match(Set dst src);
7442 effect(KILL cr);
7443
7444 // Note that this is artificially increased to make it more expensive than loadConL
7445 ins_cost(250);
7446 format %{ "MOV EAX,$src\t// low word only" %}
7447 opcode(0xB8);
7448 ins_encode( LdImmL_Lo(dst, src) );
7449 ins_pipe( ialu_reg_fat );
7450 %}
7451
7452 // Multiply by 32-bit Immediate, taking the shifted high order results
7453 // (special case for shift by 32)
7454 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7455 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7456 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7457 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7458 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7459 effect(USE src1, KILL cr);
7460
7461 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7462 ins_cost(0*100 + 1*400 - 150);
7463 format %{ "IMUL EDX:EAX,$src1" %}
7464 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7465 ins_pipe( pipe_slow );
7466 %}
7467
7468 // Multiply by 32-bit Immediate, taking the shifted high order results
7469 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7470 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7471 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7472 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7473 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7474 effect(USE src1, KILL cr);
7475
7476 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7477 ins_cost(1*100 + 1*400 - 150);
7478 format %{ "IMUL EDX:EAX,$src1\n\t"
7479 "SAR EDX,$cnt-32" %}
7480 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7481 ins_pipe( pipe_slow );
7482 %}
7483
7484 // Multiply Memory 32-bit Immediate
7485 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7486 match(Set dst (MulI (LoadI src) imm));
7487 effect(KILL cr);
7488
7489 ins_cost(300);
7490 format %{ "IMUL $dst,$src,$imm" %}
7491 opcode(0x69); /* 69 /r id */
7492 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7493 ins_pipe( ialu_reg_mem_alu0 );
7494 %}
7495
7496 // Multiply Memory
7497 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7498 match(Set dst (MulI dst (LoadI src)));
7499 effect(KILL cr);
7500
7501 ins_cost(350);
7502 format %{ "IMUL $dst,$src" %}
7503 opcode(0xAF, 0x0F);
7504 ins_encode( OpcS, OpcP, RegMem( dst, src) );
7505 ins_pipe( ialu_reg_mem_alu0 );
7506 %}
7507
7508 // Multiply Register Int to Long
7509 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7510 // Basic Idea: long = (long)int * (long)int
7511 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7512 effect(DEF dst, USE src, USE src1, KILL flags);
7513
7514 ins_cost(300);
7515 format %{ "IMUL $dst,$src1" %}
7516
7517 ins_encode( long_int_multiply( dst, src1 ) );
7518 ins_pipe( ialu_reg_reg_alu0 );
7519 %}
7520
7521 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
7522 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
7523 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
7524 effect(KILL flags);
7525
7526 ins_cost(300);
7527 format %{ "MUL $dst,$src1" %}
7528
7529 ins_encode( long_uint_multiply(dst, src1) );
7530 ins_pipe( ialu_reg_reg_alu0 );
7531 %}
7532
7533 // Multiply Register Long
7534 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7535 match(Set dst (MulL dst src));
7536 effect(KILL cr, TEMP tmp);
7537 ins_cost(4*100+3*400);
7538 // Basic idea: lo(result) = lo(x_lo * y_lo)
7539 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
7540 format %{ "MOV $tmp,$src.lo\n\t"
7541 "IMUL $tmp,EDX\n\t"
7542 "MOV EDX,$src.hi\n\t"
7543 "IMUL EDX,EAX\n\t"
7544 "ADD $tmp,EDX\n\t"
7545 "MUL EDX:EAX,$src.lo\n\t"
7546 "ADD EDX,$tmp" %}
7547 ins_encode( long_multiply( dst, src, tmp ) );
7548 ins_pipe( pipe_slow );
7549 %}
7550
7551 // Multiply Register Long where the left operand's high 32 bits are zero
7552 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7553 predicate(is_operand_hi32_zero(n->in(1)));
7554 match(Set dst (MulL dst src));
7555 effect(KILL cr, TEMP tmp);
7556 ins_cost(2*100+2*400);
7557 // Basic idea: lo(result) = lo(x_lo * y_lo)
7558 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
7559 format %{ "MOV $tmp,$src.hi\n\t"
7560 "IMUL $tmp,EAX\n\t"
7561 "MUL EDX:EAX,$src.lo\n\t"
7562 "ADD EDX,$tmp" %}
7563 ins_encode %{
7564 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
7565 __ imull($tmp$$Register, rax);
7566 __ mull($src$$Register);
7567 __ addl(rdx, $tmp$$Register);
7568 %}
7569 ins_pipe( pipe_slow );
7570 %}
7571
7572 // Multiply Register Long where the right operand's high 32 bits are zero
7573 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7574 predicate(is_operand_hi32_zero(n->in(2)));
7575 match(Set dst (MulL dst src));
7576 effect(KILL cr, TEMP tmp);
7577 ins_cost(2*100+2*400);
7578 // Basic idea: lo(result) = lo(x_lo * y_lo)
7579 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
7580 format %{ "MOV $tmp,$src.lo\n\t"
7581 "IMUL $tmp,EDX\n\t"
7582 "MUL EDX:EAX,$src.lo\n\t"
7583 "ADD EDX,$tmp" %}
7584 ins_encode %{
7585 __ movl($tmp$$Register, $src$$Register);
7586 __ imull($tmp$$Register, rdx);
7587 __ mull($src$$Register);
7588 __ addl(rdx, $tmp$$Register);
7589 %}
7590 ins_pipe( pipe_slow );
7591 %}
7592
7593 // Multiply Register Long where the left and the right operands' high 32 bits are zero
7594 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
7595 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
7596 match(Set dst (MulL dst src));
7597 effect(KILL cr);
7598 ins_cost(1*400);
7599 // Basic idea: lo(result) = lo(x_lo * y_lo)
7600 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
7601 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
7602 ins_encode %{
7603 __ mull($src$$Register);
7604 %}
7605 ins_pipe( pipe_slow );
7606 %}
7607
7608 // Multiply Register Long by small constant
7609 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
7610 match(Set dst (MulL dst src));
7611 effect(KILL cr, TEMP tmp);
7612 ins_cost(2*100+2*400);
7613 size(12);
7614 // Basic idea: lo(result) = lo(src * EAX)
7615 // hi(result) = hi(src * EAX) + lo(src * EDX)
7616 format %{ "IMUL $tmp,EDX,$src\n\t"
7617 "MOV EDX,$src\n\t"
7618 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
7619 "ADD EDX,$tmp" %}
7620 ins_encode( long_multiply_con( dst, src, tmp ) );
7621 ins_pipe( pipe_slow );
7622 %}
7623
7624 // Integer DIV with Register
7625 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7626 match(Set rax (DivI rax div));
7627 effect(KILL rdx, KILL cr);
7628 size(26);
7629 ins_cost(30*100+10*100);
7630 format %{ "CMP EAX,0x80000000\n\t"
7631 "JNE,s normal\n\t"
7632 "XOR EDX,EDX\n\t"
7633 "CMP ECX,-1\n\t"
7634 "JE,s done\n"
7635 "normal: CDQ\n\t"
7636 "IDIV $div\n\t"
7637 "done:" %}
7638 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7639 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7640 ins_pipe( ialu_reg_reg_alu0 );
7641 %}
7642
7643 // Divide Register Long
7644 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7645 match(Set dst (DivL src1 src2));
7646 effect( KILL cr, KILL cx, KILL bx );
7647 ins_cost(10000);
7648 format %{ "PUSH $src1.hi\n\t"
7649 "PUSH $src1.lo\n\t"
7650 "PUSH $src2.hi\n\t"
7651 "PUSH $src2.lo\n\t"
7652 "CALL SharedRuntime::ldiv\n\t"
7653 "ADD ESP,16" %}
7654 ins_encode( long_div(src1,src2) );
7655 ins_pipe( pipe_slow );
7656 %}
7657
7658 // Integer DIVMOD with Register, both quotient and mod results
7659 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7660 match(DivModI rax div);
7661 effect(KILL cr);
7662 size(26);
7663 ins_cost(30*100+10*100);
7664 format %{ "CMP EAX,0x80000000\n\t"
7665 "JNE,s normal\n\t"
7666 "XOR EDX,EDX\n\t"
7667 "CMP ECX,-1\n\t"
7668 "JE,s done\n"
7669 "normal: CDQ\n\t"
7670 "IDIV $div\n\t"
7671 "done:" %}
7672 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7673 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7674 ins_pipe( pipe_slow );
7675 %}
7676
7677 // Integer MOD with Register
7678 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
7679 match(Set rdx (ModI rax div));
7680 effect(KILL rax, KILL cr);
7681
7682 size(26);
7683 ins_cost(300);
7684 format %{ "CDQ\n\t"
7685 "IDIV $div" %}
7686 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7687 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7688 ins_pipe( ialu_reg_reg_alu0 );
7689 %}
7690
7691 // Remainder Register Long
7692 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7693 match(Set dst (ModL src1 src2));
7694 effect( KILL cr, KILL cx, KILL bx );
7695 ins_cost(10000);
7696 format %{ "PUSH $src1.hi\n\t"
7697 "PUSH $src1.lo\n\t"
7698 "PUSH $src2.hi\n\t"
7699 "PUSH $src2.lo\n\t"
7700 "CALL SharedRuntime::lrem\n\t"
7701 "ADD ESP,16" %}
7702 ins_encode( long_mod(src1,src2) );
7703 ins_pipe( pipe_slow );
7704 %}
7705
7706 // Divide Register Long (no special case since divisor != -1)
7707 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7708 match(Set dst (DivL dst imm));
7709 effect( TEMP tmp, TEMP tmp2, KILL cr );
7710 ins_cost(1000);
7711 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
7712 "XOR $tmp2,$tmp2\n\t"
7713 "CMP $tmp,EDX\n\t"
7714 "JA,s fast\n\t"
7715 "MOV $tmp2,EAX\n\t"
7716 "MOV EAX,EDX\n\t"
7717 "MOV EDX,0\n\t"
7718 "JLE,s pos\n\t"
7719 "LNEG EAX : $tmp2\n\t"
7720 "DIV $tmp # unsigned division\n\t"
7721 "XCHG EAX,$tmp2\n\t"
7722 "DIV $tmp\n\t"
7723 "LNEG $tmp2 : EAX\n\t"
7724 "JMP,s done\n"
7725 "pos:\n\t"
7726 "DIV $tmp\n\t"
7727 "XCHG EAX,$tmp2\n"
7728 "fast:\n\t"
7729 "DIV $tmp\n"
7730 "done:\n\t"
7731 "MOV EDX,$tmp2\n\t"
7732 "NEG EDX:EAX # if $imm < 0" %}
7733 ins_encode %{
7734 int con = (int)$imm$$constant;
7735 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7736 int pcon = (con > 0) ? con : -con;
7737 Label Lfast, Lpos, Ldone;
7738
7739 __ movl($tmp$$Register, pcon);
7740 __ xorl($tmp2$$Register,$tmp2$$Register);
7741 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7742 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
7743
7744 __ movl($tmp2$$Register, $dst$$Register); // save
7745 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7746 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7747 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7748
7749 // Negative dividend.
7750 // convert value to positive to use unsigned division
7751 __ lneg($dst$$Register, $tmp2$$Register);
7752 __ divl($tmp$$Register);
7753 __ xchgl($dst$$Register, $tmp2$$Register);
7754 __ divl($tmp$$Register);
7755 // revert result back to negative
7756 __ lneg($tmp2$$Register, $dst$$Register);
7757 __ jmpb(Ldone);
7758
7759 __ bind(Lpos);
7760 __ divl($tmp$$Register); // Use unsigned division
7761 __ xchgl($dst$$Register, $tmp2$$Register);
7762 // Fallthrow for final divide, tmp2 has 32 bit hi result
7763
7764 __ bind(Lfast);
7765 // fast path: src is positive
7766 __ divl($tmp$$Register); // Use unsigned division
7767
7768 __ bind(Ldone);
7769 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
7770 if (con < 0) {
7771 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
7772 }
7773 %}
7774 ins_pipe( pipe_slow );
7775 %}
7776
7777 // Remainder Register Long (remainder fit into 32 bits)
7778 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7779 match(Set dst (ModL dst imm));
7780 effect( TEMP tmp, TEMP tmp2, KILL cr );
7781 ins_cost(1000);
7782 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
7783 "CMP $tmp,EDX\n\t"
7784 "JA,s fast\n\t"
7785 "MOV $tmp2,EAX\n\t"
7786 "MOV EAX,EDX\n\t"
7787 "MOV EDX,0\n\t"
7788 "JLE,s pos\n\t"
7789 "LNEG EAX : $tmp2\n\t"
7790 "DIV $tmp # unsigned division\n\t"
7791 "MOV EAX,$tmp2\n\t"
7792 "DIV $tmp\n\t"
7793 "NEG EDX\n\t"
7794 "JMP,s done\n"
7795 "pos:\n\t"
7796 "DIV $tmp\n\t"
7797 "MOV EAX,$tmp2\n"
7798 "fast:\n\t"
7799 "DIV $tmp\n"
7800 "done:\n\t"
7801 "MOV EAX,EDX\n\t"
7802 "SAR EDX,31\n\t" %}
7803 ins_encode %{
7804 int con = (int)$imm$$constant;
7805 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7806 int pcon = (con > 0) ? con : -con;
7807 Label Lfast, Lpos, Ldone;
7808
7809 __ movl($tmp$$Register, pcon);
7810 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7811 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
7812
7813 __ movl($tmp2$$Register, $dst$$Register); // save
7814 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7815 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7816 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7817
7818 // Negative dividend.
7819 // convert value to positive to use unsigned division
7820 __ lneg($dst$$Register, $tmp2$$Register);
7821 __ divl($tmp$$Register);
7822 __ movl($dst$$Register, $tmp2$$Register);
7823 __ divl($tmp$$Register);
7824 // revert remainder back to negative
7825 __ negl(HIGH_FROM_LOW($dst$$Register));
7826 __ jmpb(Ldone);
7827
7828 __ bind(Lpos);
7829 __ divl($tmp$$Register);
7830 __ movl($dst$$Register, $tmp2$$Register);
7831
7832 __ bind(Lfast);
7833 // fast path: src is positive
7834 __ divl($tmp$$Register);
7835
7836 __ bind(Ldone);
7837 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7838 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
7839
7840 %}
7841 ins_pipe( pipe_slow );
7842 %}
7843
7844 // Integer Shift Instructions
7845 // Shift Left by one
7846 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7847 match(Set dst (LShiftI dst shift));
7848 effect(KILL cr);
7849
7850 size(2);
7851 format %{ "SHL $dst,$shift" %}
7852 opcode(0xD1, 0x4); /* D1 /4 */
7853 ins_encode( OpcP, RegOpc( dst ) );
7854 ins_pipe( ialu_reg );
7855 %}
7856
7857 // Shift Left by 8-bit immediate
7858 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7859 match(Set dst (LShiftI dst shift));
7860 effect(KILL cr);
7861
7862 size(3);
7863 format %{ "SHL $dst,$shift" %}
7864 opcode(0xC1, 0x4); /* C1 /4 ib */
7865 ins_encode( RegOpcImm( dst, shift) );
7866 ins_pipe( ialu_reg );
7867 %}
7868
7869 // Shift Left by variable
7870 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7871 match(Set dst (LShiftI dst shift));
7872 effect(KILL cr);
7873
7874 size(2);
7875 format %{ "SHL $dst,$shift" %}
7876 opcode(0xD3, 0x4); /* D3 /4 */
7877 ins_encode( OpcP, RegOpc( dst ) );
7878 ins_pipe( ialu_reg_reg );
7879 %}
7880
7881 // Arithmetic shift right by one
7882 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7883 match(Set dst (RShiftI dst shift));
7884 effect(KILL cr);
7885
7886 size(2);
7887 format %{ "SAR $dst,$shift" %}
7888 opcode(0xD1, 0x7); /* D1 /7 */
7889 ins_encode( OpcP, RegOpc( dst ) );
7890 ins_pipe( ialu_reg );
7891 %}
7892
7893 // Arithmetic shift right by one
7894 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
7895 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7896 effect(KILL cr);
7897 format %{ "SAR $dst,$shift" %}
7898 opcode(0xD1, 0x7); /* D1 /7 */
7899 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
7900 ins_pipe( ialu_mem_imm );
7901 %}
7902
7903 // Arithmetic Shift Right by 8-bit immediate
7904 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7905 match(Set dst (RShiftI dst shift));
7906 effect(KILL cr);
7907
7908 size(3);
7909 format %{ "SAR $dst,$shift" %}
7910 opcode(0xC1, 0x7); /* C1 /7 ib */
7911 ins_encode( RegOpcImm( dst, shift ) );
7912 ins_pipe( ialu_mem_imm );
7913 %}
7914
7915 // Arithmetic Shift Right by 8-bit immediate
7916 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
7917 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7918 effect(KILL cr);
7919
7920 format %{ "SAR $dst,$shift" %}
7921 opcode(0xC1, 0x7); /* C1 /7 ib */
7922 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
7923 ins_pipe( ialu_mem_imm );
7924 %}
7925
7926 // Arithmetic Shift Right by variable
7927 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7928 match(Set dst (RShiftI dst shift));
7929 effect(KILL cr);
7930
7931 size(2);
7932 format %{ "SAR $dst,$shift" %}
7933 opcode(0xD3, 0x7); /* D3 /7 */
7934 ins_encode( OpcP, RegOpc( dst ) );
7935 ins_pipe( ialu_reg_reg );
7936 %}
7937
7938 // Logical shift right by one
7939 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7940 match(Set dst (URShiftI dst shift));
7941 effect(KILL cr);
7942
7943 size(2);
7944 format %{ "SHR $dst,$shift" %}
7945 opcode(0xD1, 0x5); /* D1 /5 */
7946 ins_encode( OpcP, RegOpc( dst ) );
7947 ins_pipe( ialu_reg );
7948 %}
7949
7950 // Logical Shift Right by 8-bit immediate
7951 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7952 match(Set dst (URShiftI dst shift));
7953 effect(KILL cr);
7954
7955 size(3);
7956 format %{ "SHR $dst,$shift" %}
7957 opcode(0xC1, 0x5); /* C1 /5 ib */
7958 ins_encode( RegOpcImm( dst, shift) );
7959 ins_pipe( ialu_reg );
7960 %}
7961
7962
7963 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
7964 // This idiom is used by the compiler for the i2b bytecode.
7965 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
7966 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
7967
7968 size(3);
7969 format %{ "MOVSX $dst,$src :8" %}
7970 ins_encode %{
7971 __ movsbl($dst$$Register, $src$$Register);
7972 %}
7973 ins_pipe(ialu_reg_reg);
7974 %}
7975
7976 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
7977 // This idiom is used by the compiler the i2s bytecode.
7978 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
7979 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
7980
7981 size(3);
7982 format %{ "MOVSX $dst,$src :16" %}
7983 ins_encode %{
7984 __ movswl($dst$$Register, $src$$Register);
7985 %}
7986 ins_pipe(ialu_reg_reg);
7987 %}
7988
7989
7990 // Logical Shift Right by variable
7991 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7992 match(Set dst (URShiftI dst shift));
7993 effect(KILL cr);
7994
7995 size(2);
7996 format %{ "SHR $dst,$shift" %}
7997 opcode(0xD3, 0x5); /* D3 /5 */
7998 ins_encode( OpcP, RegOpc( dst ) );
7999 ins_pipe( ialu_reg_reg );
8000 %}
8001
8002
8003 //----------Logical Instructions-----------------------------------------------
8004 //----------Integer Logical Instructions---------------------------------------
8005 // And Instructions
8006 // And Register with Register
8007 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8008 match(Set dst (AndI dst src));
8009 effect(KILL cr);
8010
8011 size(2);
8012 format %{ "AND $dst,$src" %}
8013 opcode(0x23);
8014 ins_encode( OpcP, RegReg( dst, src) );
8015 ins_pipe( ialu_reg_reg );
8016 %}
8017
8018 // And Register with Immediate
8019 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8020 match(Set dst (AndI dst src));
8021 effect(KILL cr);
8022
8023 format %{ "AND $dst,$src" %}
8024 opcode(0x81,0x04); /* Opcode 81 /4 */
8025 // ins_encode( RegImm( dst, src) );
8026 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8027 ins_pipe( ialu_reg );
8028 %}
8029
8030 // And Register with Memory
8031 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8032 match(Set dst (AndI dst (LoadI src)));
8033 effect(KILL cr);
8034
8035 ins_cost(125);
8036 format %{ "AND $dst,$src" %}
8037 opcode(0x23);
8038 ins_encode( OpcP, RegMem( dst, src) );
8039 ins_pipe( ialu_reg_mem );
8040 %}
8041
8042 // And Memory with Register
8043 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8044 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8045 effect(KILL cr);
8046
8047 ins_cost(150);
8048 format %{ "AND $dst,$src" %}
8049 opcode(0x21); /* Opcode 21 /r */
8050 ins_encode( OpcP, RegMem( src, dst ) );
8051 ins_pipe( ialu_mem_reg );
8052 %}
8053
8054 // And Memory with Immediate
8055 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8056 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8057 effect(KILL cr);
8058
8059 ins_cost(125);
8060 format %{ "AND $dst,$src" %}
8061 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8062 // ins_encode( MemImm( dst, src) );
8063 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8064 ins_pipe( ialu_mem_imm );
8065 %}
8066
8067 // BMI1 instructions
8068 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{
8069 match(Set dst (AndI (XorI src1 minus_1) src2));
8070 predicate(UseBMI1Instructions);
8071 effect(KILL cr);
8072
8073 format %{ "ANDNL $dst, $src1, $src2" %}
8074
8075 ins_encode %{
8076 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8077 %}
8078 ins_pipe(ialu_reg);
8079 %}
8080
8081 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{
8082 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));
8083 predicate(UseBMI1Instructions);
8084 effect(KILL cr);
8085
8086 ins_cost(125);
8087 format %{ "ANDNL $dst, $src1, $src2" %}
8088
8089 ins_encode %{
8090 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8091 %}
8092 ins_pipe(ialu_reg_mem);
8093 %}
8094
8095 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{
8096 match(Set dst (AndI (SubI imm_zero src) src));
8097 predicate(UseBMI1Instructions);
8098 effect(KILL cr);
8099
8100 format %{ "BLSIL $dst, $src" %}
8101
8102 ins_encode %{
8103 __ blsil($dst$$Register, $src$$Register);
8104 %}
8105 ins_pipe(ialu_reg);
8106 %}
8107
8108 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{
8109 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8110 predicate(UseBMI1Instructions);
8111 effect(KILL cr);
8112
8113 ins_cost(125);
8114 format %{ "BLSIL $dst, $src" %}
8115
8116 ins_encode %{
8117 __ blsil($dst$$Register, $src$$Address);
8118 %}
8119 ins_pipe(ialu_reg_mem);
8120 %}
8121
8122 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8123 %{
8124 match(Set dst (XorI (AddI src minus_1) src));
8125 predicate(UseBMI1Instructions);
8126 effect(KILL cr);
8127
8128 format %{ "BLSMSKL $dst, $src" %}
8129
8130 ins_encode %{
8131 __ blsmskl($dst$$Register, $src$$Register);
8132 %}
8133
8134 ins_pipe(ialu_reg);
8135 %}
8136
8137 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8138 %{
8139 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ));
8140 predicate(UseBMI1Instructions);
8141 effect(KILL cr);
8142
8143 ins_cost(125);
8144 format %{ "BLSMSKL $dst, $src" %}
8145
8146 ins_encode %{
8147 __ blsmskl($dst$$Register, $src$$Address);
8148 %}
8149
8150 ins_pipe(ialu_reg_mem);
8151 %}
8152
8153 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8154 %{
8155 match(Set dst (AndI (AddI src minus_1) src) );
8156 predicate(UseBMI1Instructions);
8157 effect(KILL cr);
8158
8159 format %{ "BLSRL $dst, $src" %}
8160
8161 ins_encode %{
8162 __ blsrl($dst$$Register, $src$$Register);
8163 %}
8164
8165 ins_pipe(ialu_reg);
8166 %}
8167
8168 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8169 %{
8170 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ));
8171 predicate(UseBMI1Instructions);
8172 effect(KILL cr);
8173
8174 ins_cost(125);
8175 format %{ "BLSRL $dst, $src" %}
8176
8177 ins_encode %{
8178 __ blsrl($dst$$Register, $src$$Address);
8179 %}
8180
8181 ins_pipe(ialu_reg_mem);
8182 %}
8183
8184 // Or Instructions
8185 // Or Register with Register
8186 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8187 match(Set dst (OrI dst src));
8188 effect(KILL cr);
8189
8190 size(2);
8191 format %{ "OR $dst,$src" %}
8192 opcode(0x0B);
8193 ins_encode( OpcP, RegReg( dst, src) );
8194 ins_pipe( ialu_reg_reg );
8195 %}
8196
8197 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8198 match(Set dst (OrI dst (CastP2X src)));
8199 effect(KILL cr);
8200
8201 size(2);
8202 format %{ "OR $dst,$src" %}
8203 opcode(0x0B);
8204 ins_encode( OpcP, RegReg( dst, src) );
8205 ins_pipe( ialu_reg_reg );
8206 %}
8207
8208
8209 // Or Register with Immediate
8210 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8211 match(Set dst (OrI dst src));
8212 effect(KILL cr);
8213
8214 format %{ "OR $dst,$src" %}
8215 opcode(0x81,0x01); /* Opcode 81 /1 id */
8216 // ins_encode( RegImm( dst, src) );
8217 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8218 ins_pipe( ialu_reg );
8219 %}
8220
8221 // Or Register with Memory
8222 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8223 match(Set dst (OrI dst (LoadI src)));
8224 effect(KILL cr);
8225
8226 ins_cost(125);
8227 format %{ "OR $dst,$src" %}
8228 opcode(0x0B);
8229 ins_encode( OpcP, RegMem( dst, src) );
8230 ins_pipe( ialu_reg_mem );
8231 %}
8232
8233 // Or Memory with Register
8234 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8235 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8236 effect(KILL cr);
8237
8238 ins_cost(150);
8239 format %{ "OR $dst,$src" %}
8240 opcode(0x09); /* Opcode 09 /r */
8241 ins_encode( OpcP, RegMem( src, dst ) );
8242 ins_pipe( ialu_mem_reg );
8243 %}
8244
8245 // Or Memory with Immediate
8246 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8247 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8248 effect(KILL cr);
8249
8250 ins_cost(125);
8251 format %{ "OR $dst,$src" %}
8252 opcode(0x81,0x1); /* Opcode 81 /1 id */
8253 // ins_encode( MemImm( dst, src) );
8254 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8255 ins_pipe( ialu_mem_imm );
8256 %}
8257
8258 // ROL/ROR
8259 // ROL expand
8260 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8261 effect(USE_DEF dst, USE shift, KILL cr);
8262
8263 format %{ "ROL $dst, $shift" %}
8264 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8265 ins_encode( OpcP, RegOpc( dst ));
8266 ins_pipe( ialu_reg );
8267 %}
8268
8269 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8270 effect(USE_DEF dst, USE shift, KILL cr);
8271
8272 format %{ "ROL $dst, $shift" %}
8273 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8274 ins_encode( RegOpcImm(dst, shift) );
8275 ins_pipe(ialu_reg);
8276 %}
8277
8278 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8279 effect(USE_DEF dst, USE shift, KILL cr);
8280
8281 format %{ "ROL $dst, $shift" %}
8282 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8283 ins_encode(OpcP, RegOpc(dst));
8284 ins_pipe( ialu_reg_reg );
8285 %}
8286 // end of ROL expand
8287
8288 // ROL 32bit by one once
8289 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8290 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8291
8292 expand %{
8293 rolI_eReg_imm1(dst, lshift, cr);
8294 %}
8295 %}
8296
8297 // ROL 32bit var by imm8 once
8298 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8299 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8300 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8301
8302 expand %{
8303 rolI_eReg_imm8(dst, lshift, cr);
8304 %}
8305 %}
8306
8307 // ROL 32bit var by var once
8308 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8309 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8310
8311 expand %{
8312 rolI_eReg_CL(dst, shift, cr);
8313 %}
8314 %}
8315
8316 // ROL 32bit var by var once
8317 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8318 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8319
8320 expand %{
8321 rolI_eReg_CL(dst, shift, cr);
8322 %}
8323 %}
8324
8325 // ROR expand
8326 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8327 effect(USE_DEF dst, USE shift, KILL cr);
8328
8329 format %{ "ROR $dst, $shift" %}
8330 opcode(0xD1,0x1); /* Opcode D1 /1 */
8331 ins_encode( OpcP, RegOpc( dst ) );
8332 ins_pipe( ialu_reg );
8333 %}
8334
8335 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8336 effect (USE_DEF dst, USE shift, KILL cr);
8337
8338 format %{ "ROR $dst, $shift" %}
8339 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8340 ins_encode( RegOpcImm(dst, shift) );
8341 ins_pipe( ialu_reg );
8342 %}
8343
8344 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8345 effect(USE_DEF dst, USE shift, KILL cr);
8346
8347 format %{ "ROR $dst, $shift" %}
8348 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8349 ins_encode(OpcP, RegOpc(dst));
8350 ins_pipe( ialu_reg_reg );
8351 %}
8352 // end of ROR expand
8353
8354 // ROR right once
8355 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8356 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8357
8358 expand %{
8359 rorI_eReg_imm1(dst, rshift, cr);
8360 %}
8361 %}
8362
8363 // ROR 32bit by immI8 once
8364 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8365 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8366 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8367
8368 expand %{
8369 rorI_eReg_imm8(dst, rshift, cr);
8370 %}
8371 %}
8372
8373 // ROR 32bit var by var once
8374 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8375 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8376
8377 expand %{
8378 rorI_eReg_CL(dst, shift, cr);
8379 %}
8380 %}
8381
8382 // ROR 32bit var by var once
8383 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8384 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8385
8386 expand %{
8387 rorI_eReg_CL(dst, shift, cr);
8388 %}
8389 %}
8390
8391 // Xor Instructions
8392 // Xor Register with Register
8393 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8394 match(Set dst (XorI dst src));
8395 effect(KILL cr);
8396
8397 size(2);
8398 format %{ "XOR $dst,$src" %}
8399 opcode(0x33);
8400 ins_encode( OpcP, RegReg( dst, src) );
8401 ins_pipe( ialu_reg_reg );
8402 %}
8403
8404 // Xor Register with Immediate -1
8405 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8406 match(Set dst (XorI dst imm));
8407
8408 size(2);
8409 format %{ "NOT $dst" %}
8410 ins_encode %{
8411 __ notl($dst$$Register);
8412 %}
8413 ins_pipe( ialu_reg );
8414 %}
8415
8416 // Xor Register with Immediate
8417 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8418 match(Set dst (XorI dst src));
8419 effect(KILL cr);
8420
8421 format %{ "XOR $dst,$src" %}
8422 opcode(0x81,0x06); /* Opcode 81 /6 id */
8423 // ins_encode( RegImm( dst, src) );
8424 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8425 ins_pipe( ialu_reg );
8426 %}
8427
8428 // Xor Register with Memory
8429 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8430 match(Set dst (XorI dst (LoadI src)));
8431 effect(KILL cr);
8432
8433 ins_cost(125);
8434 format %{ "XOR $dst,$src" %}
8435 opcode(0x33);
8436 ins_encode( OpcP, RegMem(dst, src) );
8437 ins_pipe( ialu_reg_mem );
8438 %}
8439
8440 // Xor Memory with Register
8441 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8442 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8443 effect(KILL cr);
8444
8445 ins_cost(150);
8446 format %{ "XOR $dst,$src" %}
8447 opcode(0x31); /* Opcode 31 /r */
8448 ins_encode( OpcP, RegMem( src, dst ) );
8449 ins_pipe( ialu_mem_reg );
8450 %}
8451
8452 // Xor Memory with Immediate
8453 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8454 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8455 effect(KILL cr);
8456
8457 ins_cost(125);
8458 format %{ "XOR $dst,$src" %}
8459 opcode(0x81,0x6); /* Opcode 81 /6 id */
8460 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8461 ins_pipe( ialu_mem_imm );
8462 %}
8463
8464 //----------Convert Int to Boolean---------------------------------------------
8465
8466 instruct movI_nocopy(rRegI dst, rRegI src) %{
8467 effect( DEF dst, USE src );
8468 format %{ "MOV $dst,$src" %}
8469 ins_encode( enc_Copy( dst, src) );
8470 ins_pipe( ialu_reg_reg );
8471 %}
8472
8473 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8474 effect( USE_DEF dst, USE src, KILL cr );
8475
8476 size(4);
8477 format %{ "NEG $dst\n\t"
8478 "ADC $dst,$src" %}
8479 ins_encode( neg_reg(dst),
8480 OpcRegReg(0x13,dst,src) );
8481 ins_pipe( ialu_reg_reg_long );
8482 %}
8483
8484 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8485 match(Set dst (Conv2B src));
8486
8487 expand %{
8488 movI_nocopy(dst,src);
8489 ci2b(dst,src,cr);
8490 %}
8491 %}
8492
8493 instruct movP_nocopy(rRegI dst, eRegP src) %{
8494 effect( DEF dst, USE src );
8495 format %{ "MOV $dst,$src" %}
8496 ins_encode( enc_Copy( dst, src) );
8497 ins_pipe( ialu_reg_reg );
8498 %}
8499
8500 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8501 effect( USE_DEF dst, USE src, KILL cr );
8502 format %{ "NEG $dst\n\t"
8503 "ADC $dst,$src" %}
8504 ins_encode( neg_reg(dst),
8505 OpcRegReg(0x13,dst,src) );
8506 ins_pipe( ialu_reg_reg_long );
8507 %}
8508
8509 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8510 match(Set dst (Conv2B src));
8511
8512 expand %{
8513 movP_nocopy(dst,src);
8514 cp2b(dst,src,cr);
8515 %}
8516 %}
8517
8518 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8519 match(Set dst (CmpLTMask p q));
8520 effect(KILL cr);
8521 ins_cost(400);
8522
8523 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8524 format %{ "XOR $dst,$dst\n\t"
8525 "CMP $p,$q\n\t"
8526 "SETlt $dst\n\t"
8527 "NEG $dst" %}
8528 ins_encode %{
8529 Register Rp = $p$$Register;
8530 Register Rq = $q$$Register;
8531 Register Rd = $dst$$Register;
8532 Label done;
8533 __ xorl(Rd, Rd);
8534 __ cmpl(Rp, Rq);
8535 __ setb(Assembler::less, Rd);
8536 __ negl(Rd);
8537 %}
8538
8539 ins_pipe(pipe_slow);
8540 %}
8541
8542 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8543 match(Set dst (CmpLTMask dst zero));
8544 effect(DEF dst, KILL cr);
8545 ins_cost(100);
8546
8547 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8548 ins_encode %{
8549 __ sarl($dst$$Register, 31);
8550 %}
8551 ins_pipe(ialu_reg);
8552 %}
8553
8554 /* better to save a register than avoid a branch */
8555 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8556 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8557 effect(KILL cr);
8558 ins_cost(400);
8559 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8560 "JGE done\n\t"
8561 "ADD $p,$y\n"
8562 "done: " %}
8563 ins_encode %{
8564 Register Rp = $p$$Register;
8565 Register Rq = $q$$Register;
8566 Register Ry = $y$$Register;
8567 Label done;
8568 __ subl(Rp, Rq);
8569 __ jccb(Assembler::greaterEqual, done);
8570 __ addl(Rp, Ry);
8571 __ bind(done);
8572 %}
8573
8574 ins_pipe(pipe_cmplt);
8575 %}
8576
8577 /* better to save a register than avoid a branch */
8578 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8579 match(Set y (AndI (CmpLTMask p q) y));
8580 effect(KILL cr);
8581
8582 ins_cost(300);
8583
8584 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
8585 "JLT done\n\t"
8586 "XORL $y, $y\n"
8587 "done: " %}
8588 ins_encode %{
8589 Register Rp = $p$$Register;
8590 Register Rq = $q$$Register;
8591 Register Ry = $y$$Register;
8592 Label done;
8593 __ cmpl(Rp, Rq);
8594 __ jccb(Assembler::less, done);
8595 __ xorl(Ry, Ry);
8596 __ bind(done);
8597 %}
8598
8599 ins_pipe(pipe_cmplt);
8600 %}
8601
8602 /* If I enable this, I encourage spilling in the inner loop of compress.
8603 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8604 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8605 */
8606 //----------Overflow Math Instructions-----------------------------------------
8607
8608 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8609 %{
8610 match(Set cr (OverflowAddI op1 op2));
8611 effect(DEF cr, USE_KILL op1, USE op2);
8612
8613 format %{ "ADD $op1, $op2\t# overflow check int" %}
8614
8615 ins_encode %{
8616 __ addl($op1$$Register, $op2$$Register);
8617 %}
8618 ins_pipe(ialu_reg_reg);
8619 %}
8620
8621 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
8622 %{
8623 match(Set cr (OverflowAddI op1 op2));
8624 effect(DEF cr, USE_KILL op1, USE op2);
8625
8626 format %{ "ADD $op1, $op2\t# overflow check int" %}
8627
8628 ins_encode %{
8629 __ addl($op1$$Register, $op2$$constant);
8630 %}
8631 ins_pipe(ialu_reg_reg);
8632 %}
8633
8634 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2)
8635 %{
8636 match(Set cr (OverflowSubI op1 op2));
8637
8638 format %{ "CMP $op1, $op2\t# overflow check int" %}
8639 ins_encode %{
8640 __ cmpl($op1$$Register, $op2$$Register);
8641 %}
8642 ins_pipe(ialu_reg_reg);
8643 %}
8644
8645 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2)
8646 %{
8647 match(Set cr (OverflowSubI op1 op2));
8648
8649 format %{ "CMP $op1, $op2\t# overflow check int" %}
8650 ins_encode %{
8651 __ cmpl($op1$$Register, $op2$$constant);
8652 %}
8653 ins_pipe(ialu_reg_reg);
8654 %}
8655
8656 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
8657 %{
8658 match(Set cr (OverflowSubI zero op2));
8659 effect(DEF cr, USE_KILL op2);
8660
8661 format %{ "NEG $op2\t# overflow check int" %}
8662 ins_encode %{
8663 __ negl($op2$$Register);
8664 %}
8665 ins_pipe(ialu_reg_reg);
8666 %}
8667
8668 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8669 %{
8670 match(Set cr (OverflowMulI op1 op2));
8671 effect(DEF cr, USE_KILL op1, USE op2);
8672
8673 format %{ "IMUL $op1, $op2\t# overflow check int" %}
8674 ins_encode %{
8675 __ imull($op1$$Register, $op2$$Register);
8676 %}
8677 ins_pipe(ialu_reg_reg_alu0);
8678 %}
8679
8680 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
8681 %{
8682 match(Set cr (OverflowMulI op1 op2));
8683 effect(DEF cr, TEMP tmp, USE op1, USE op2);
8684
8685 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %}
8686 ins_encode %{
8687 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
8688 %}
8689 ins_pipe(ialu_reg_reg_alu0);
8690 %}
8691
8692 //----------Long Instructions------------------------------------------------
8693 // Add Long Register with Register
8694 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8695 match(Set dst (AddL dst src));
8696 effect(KILL cr);
8697 ins_cost(200);
8698 format %{ "ADD $dst.lo,$src.lo\n\t"
8699 "ADC $dst.hi,$src.hi" %}
8700 opcode(0x03, 0x13);
8701 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8702 ins_pipe( ialu_reg_reg_long );
8703 %}
8704
8705 // Add Long Register with Immediate
8706 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8707 match(Set dst (AddL dst src));
8708 effect(KILL cr);
8709 format %{ "ADD $dst.lo,$src.lo\n\t"
8710 "ADC $dst.hi,$src.hi" %}
8711 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8712 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8713 ins_pipe( ialu_reg_long );
8714 %}
8715
8716 // Add Long Register with Memory
8717 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8718 match(Set dst (AddL dst (LoadL mem)));
8719 effect(KILL cr);
8720 ins_cost(125);
8721 format %{ "ADD $dst.lo,$mem\n\t"
8722 "ADC $dst.hi,$mem+4" %}
8723 opcode(0x03, 0x13);
8724 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8725 ins_pipe( ialu_reg_long_mem );
8726 %}
8727
8728 // Subtract Long Register with Register.
8729 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8730 match(Set dst (SubL dst src));
8731 effect(KILL cr);
8732 ins_cost(200);
8733 format %{ "SUB $dst.lo,$src.lo\n\t"
8734 "SBB $dst.hi,$src.hi" %}
8735 opcode(0x2B, 0x1B);
8736 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8737 ins_pipe( ialu_reg_reg_long );
8738 %}
8739
8740 // Subtract Long Register with Immediate
8741 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8742 match(Set dst (SubL dst src));
8743 effect(KILL cr);
8744 format %{ "SUB $dst.lo,$src.lo\n\t"
8745 "SBB $dst.hi,$src.hi" %}
8746 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8747 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8748 ins_pipe( ialu_reg_long );
8749 %}
8750
8751 // Subtract Long Register with Memory
8752 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8753 match(Set dst (SubL dst (LoadL mem)));
8754 effect(KILL cr);
8755 ins_cost(125);
8756 format %{ "SUB $dst.lo,$mem\n\t"
8757 "SBB $dst.hi,$mem+4" %}
8758 opcode(0x2B, 0x1B);
8759 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8760 ins_pipe( ialu_reg_long_mem );
8761 %}
8762
8763 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8764 match(Set dst (SubL zero dst));
8765 effect(KILL cr);
8766 ins_cost(300);
8767 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
8768 ins_encode( neg_long(dst) );
8769 ins_pipe( ialu_reg_reg_long );
8770 %}
8771
8772 // And Long Register with Register
8773 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8774 match(Set dst (AndL dst src));
8775 effect(KILL cr);
8776 format %{ "AND $dst.lo,$src.lo\n\t"
8777 "AND $dst.hi,$src.hi" %}
8778 opcode(0x23,0x23);
8779 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8780 ins_pipe( ialu_reg_reg_long );
8781 %}
8782
8783 // And Long Register with Immediate
8784 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8785 match(Set dst (AndL dst src));
8786 effect(KILL cr);
8787 format %{ "AND $dst.lo,$src.lo\n\t"
8788 "AND $dst.hi,$src.hi" %}
8789 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
8790 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8791 ins_pipe( ialu_reg_long );
8792 %}
8793
8794 // And Long Register with Memory
8795 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8796 match(Set dst (AndL dst (LoadL mem)));
8797 effect(KILL cr);
8798 ins_cost(125);
8799 format %{ "AND $dst.lo,$mem\n\t"
8800 "AND $dst.hi,$mem+4" %}
8801 opcode(0x23, 0x23);
8802 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8803 ins_pipe( ialu_reg_long_mem );
8804 %}
8805
8806 // BMI1 instructions
8807 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{
8808 match(Set dst (AndL (XorL src1 minus_1) src2));
8809 predicate(UseBMI1Instructions);
8810 effect(KILL cr, TEMP dst);
8811
8812 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t"
8813 "ANDNL $dst.hi, $src1.hi, $src2.hi"
8814 %}
8815
8816 ins_encode %{
8817 Register Rdst = $dst$$Register;
8818 Register Rsrc1 = $src1$$Register;
8819 Register Rsrc2 = $src2$$Register;
8820 __ andnl(Rdst, Rsrc1, Rsrc2);
8821 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2));
8822 %}
8823 ins_pipe(ialu_reg_reg_long);
8824 %}
8825
8826 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{
8827 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) ));
8828 predicate(UseBMI1Instructions);
8829 effect(KILL cr, TEMP dst);
8830
8831 ins_cost(125);
8832 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t"
8833 "ANDNL $dst.hi, $src1.hi, $src2+4"
8834 %}
8835
8836 ins_encode %{
8837 Register Rdst = $dst$$Register;
8838 Register Rsrc1 = $src1$$Register;
8839 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none);
8840
8841 __ andnl(Rdst, Rsrc1, $src2$$Address);
8842 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi);
8843 %}
8844 ins_pipe(ialu_reg_mem);
8845 %}
8846
8847 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{
8848 match(Set dst (AndL (SubL imm_zero src) src));
8849 predicate(UseBMI1Instructions);
8850 effect(KILL cr, TEMP dst);
8851
8852 format %{ "MOVL $dst.hi, 0\n\t"
8853 "BLSIL $dst.lo, $src.lo\n\t"
8854 "JNZ done\n\t"
8855 "BLSIL $dst.hi, $src.hi\n"
8856 "done:"
8857 %}
8858
8859 ins_encode %{
8860 Label done;
8861 Register Rdst = $dst$$Register;
8862 Register Rsrc = $src$$Register;
8863 __ movl(HIGH_FROM_LOW(Rdst), 0);
8864 __ blsil(Rdst, Rsrc);
8865 __ jccb(Assembler::notZero, done);
8866 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8867 __ bind(done);
8868 %}
8869 ins_pipe(ialu_reg);
8870 %}
8871
8872 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{
8873 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
8874 predicate(UseBMI1Instructions);
8875 effect(KILL cr, TEMP dst);
8876
8877 ins_cost(125);
8878 format %{ "MOVL $dst.hi, 0\n\t"
8879 "BLSIL $dst.lo, $src\n\t"
8880 "JNZ done\n\t"
8881 "BLSIL $dst.hi, $src+4\n"
8882 "done:"
8883 %}
8884
8885 ins_encode %{
8886 Label done;
8887 Register Rdst = $dst$$Register;
8888 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8889
8890 __ movl(HIGH_FROM_LOW(Rdst), 0);
8891 __ blsil(Rdst, $src$$Address);
8892 __ jccb(Assembler::notZero, done);
8893 __ blsil(HIGH_FROM_LOW(Rdst), src_hi);
8894 __ bind(done);
8895 %}
8896 ins_pipe(ialu_reg_mem);
8897 %}
8898
8899 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8900 %{
8901 match(Set dst (XorL (AddL src minus_1) src));
8902 predicate(UseBMI1Instructions);
8903 effect(KILL cr, TEMP dst);
8904
8905 format %{ "MOVL $dst.hi, 0\n\t"
8906 "BLSMSKL $dst.lo, $src.lo\n\t"
8907 "JNC done\n\t"
8908 "BLSMSKL $dst.hi, $src.hi\n"
8909 "done:"
8910 %}
8911
8912 ins_encode %{
8913 Label done;
8914 Register Rdst = $dst$$Register;
8915 Register Rsrc = $src$$Register;
8916 __ movl(HIGH_FROM_LOW(Rdst), 0);
8917 __ blsmskl(Rdst, Rsrc);
8918 __ jccb(Assembler::carryClear, done);
8919 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8920 __ bind(done);
8921 %}
8922
8923 ins_pipe(ialu_reg);
8924 %}
8925
8926 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8927 %{
8928 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ));
8929 predicate(UseBMI1Instructions);
8930 effect(KILL cr, TEMP dst);
8931
8932 ins_cost(125);
8933 format %{ "MOVL $dst.hi, 0\n\t"
8934 "BLSMSKL $dst.lo, $src\n\t"
8935 "JNC done\n\t"
8936 "BLSMSKL $dst.hi, $src+4\n"
8937 "done:"
8938 %}
8939
8940 ins_encode %{
8941 Label done;
8942 Register Rdst = $dst$$Register;
8943 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8944
8945 __ movl(HIGH_FROM_LOW(Rdst), 0);
8946 __ blsmskl(Rdst, $src$$Address);
8947 __ jccb(Assembler::carryClear, done);
8948 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi);
8949 __ bind(done);
8950 %}
8951
8952 ins_pipe(ialu_reg_mem);
8953 %}
8954
8955 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8956 %{
8957 match(Set dst (AndL (AddL src minus_1) src) );
8958 predicate(UseBMI1Instructions);
8959 effect(KILL cr, TEMP dst);
8960
8961 format %{ "MOVL $dst.hi, $src.hi\n\t"
8962 "BLSRL $dst.lo, $src.lo\n\t"
8963 "JNC done\n\t"
8964 "BLSRL $dst.hi, $src.hi\n"
8965 "done:"
8966 %}
8967
8968 ins_encode %{
8969 Label done;
8970 Register Rdst = $dst$$Register;
8971 Register Rsrc = $src$$Register;
8972 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8973 __ blsrl(Rdst, Rsrc);
8974 __ jccb(Assembler::carryClear, done);
8975 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8976 __ bind(done);
8977 %}
8978
8979 ins_pipe(ialu_reg);
8980 %}
8981
8982 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8983 %{
8984 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) ));
8985 predicate(UseBMI1Instructions);
8986 effect(KILL cr, TEMP dst);
8987
8988 ins_cost(125);
8989 format %{ "MOVL $dst.hi, $src+4\n\t"
8990 "BLSRL $dst.lo, $src\n\t"
8991 "JNC done\n\t"
8992 "BLSRL $dst.hi, $src+4\n"
8993 "done:"
8994 %}
8995
8996 ins_encode %{
8997 Label done;
8998 Register Rdst = $dst$$Register;
8999 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
9000 __ movl(HIGH_FROM_LOW(Rdst), src_hi);
9001 __ blsrl(Rdst, $src$$Address);
9002 __ jccb(Assembler::carryClear, done);
9003 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi);
9004 __ bind(done);
9005 %}
9006
9007 ins_pipe(ialu_reg_mem);
9008 %}
9009
9010 // Or Long Register with Register
9011 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9012 match(Set dst (OrL dst src));
9013 effect(KILL cr);
9014 format %{ "OR $dst.lo,$src.lo\n\t"
9015 "OR $dst.hi,$src.hi" %}
9016 opcode(0x0B,0x0B);
9017 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9018 ins_pipe( ialu_reg_reg_long );
9019 %}
9020
9021 // Or Long Register with Immediate
9022 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9023 match(Set dst (OrL dst src));
9024 effect(KILL cr);
9025 format %{ "OR $dst.lo,$src.lo\n\t"
9026 "OR $dst.hi,$src.hi" %}
9027 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9028 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9029 ins_pipe( ialu_reg_long );
9030 %}
9031
9032 // Or Long Register with Memory
9033 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9034 match(Set dst (OrL dst (LoadL mem)));
9035 effect(KILL cr);
9036 ins_cost(125);
9037 format %{ "OR $dst.lo,$mem\n\t"
9038 "OR $dst.hi,$mem+4" %}
9039 opcode(0x0B,0x0B);
9040 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9041 ins_pipe( ialu_reg_long_mem );
9042 %}
9043
9044 // Xor Long Register with Register
9045 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9046 match(Set dst (XorL dst src));
9047 effect(KILL cr);
9048 format %{ "XOR $dst.lo,$src.lo\n\t"
9049 "XOR $dst.hi,$src.hi" %}
9050 opcode(0x33,0x33);
9051 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9052 ins_pipe( ialu_reg_reg_long );
9053 %}
9054
9055 // Xor Long Register with Immediate -1
9056 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9057 match(Set dst (XorL dst imm));
9058 format %{ "NOT $dst.lo\n\t"
9059 "NOT $dst.hi" %}
9060 ins_encode %{
9061 __ notl($dst$$Register);
9062 __ notl(HIGH_FROM_LOW($dst$$Register));
9063 %}
9064 ins_pipe( ialu_reg_long );
9065 %}
9066
9067 // Xor Long Register with Immediate
9068 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9069 match(Set dst (XorL dst src));
9070 effect(KILL cr);
9071 format %{ "XOR $dst.lo,$src.lo\n\t"
9072 "XOR $dst.hi,$src.hi" %}
9073 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9074 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9075 ins_pipe( ialu_reg_long );
9076 %}
9077
9078 // Xor Long Register with Memory
9079 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9080 match(Set dst (XorL dst (LoadL mem)));
9081 effect(KILL cr);
9082 ins_cost(125);
9083 format %{ "XOR $dst.lo,$mem\n\t"
9084 "XOR $dst.hi,$mem+4" %}
9085 opcode(0x33,0x33);
9086 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9087 ins_pipe( ialu_reg_long_mem );
9088 %}
9089
9090 // Shift Left Long by 1
9091 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9092 predicate(UseNewLongLShift);
9093 match(Set dst (LShiftL dst cnt));
9094 effect(KILL cr);
9095 ins_cost(100);
9096 format %{ "ADD $dst.lo,$dst.lo\n\t"
9097 "ADC $dst.hi,$dst.hi" %}
9098 ins_encode %{
9099 __ addl($dst$$Register,$dst$$Register);
9100 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9101 %}
9102 ins_pipe( ialu_reg_long );
9103 %}
9104
9105 // Shift Left Long by 2
9106 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9107 predicate(UseNewLongLShift);
9108 match(Set dst (LShiftL dst cnt));
9109 effect(KILL cr);
9110 ins_cost(100);
9111 format %{ "ADD $dst.lo,$dst.lo\n\t"
9112 "ADC $dst.hi,$dst.hi\n\t"
9113 "ADD $dst.lo,$dst.lo\n\t"
9114 "ADC $dst.hi,$dst.hi" %}
9115 ins_encode %{
9116 __ addl($dst$$Register,$dst$$Register);
9117 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9118 __ addl($dst$$Register,$dst$$Register);
9119 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9120 %}
9121 ins_pipe( ialu_reg_long );
9122 %}
9123
9124 // Shift Left Long by 3
9125 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9126 predicate(UseNewLongLShift);
9127 match(Set dst (LShiftL dst cnt));
9128 effect(KILL cr);
9129 ins_cost(100);
9130 format %{ "ADD $dst.lo,$dst.lo\n\t"
9131 "ADC $dst.hi,$dst.hi\n\t"
9132 "ADD $dst.lo,$dst.lo\n\t"
9133 "ADC $dst.hi,$dst.hi\n\t"
9134 "ADD $dst.lo,$dst.lo\n\t"
9135 "ADC $dst.hi,$dst.hi" %}
9136 ins_encode %{
9137 __ addl($dst$$Register,$dst$$Register);
9138 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9139 __ addl($dst$$Register,$dst$$Register);
9140 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9141 __ addl($dst$$Register,$dst$$Register);
9142 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9143 %}
9144 ins_pipe( ialu_reg_long );
9145 %}
9146
9147 // Shift Left Long by 1-31
9148 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9149 match(Set dst (LShiftL dst cnt));
9150 effect(KILL cr);
9151 ins_cost(200);
9152 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9153 "SHL $dst.lo,$cnt" %}
9154 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9155 ins_encode( move_long_small_shift(dst,cnt) );
9156 ins_pipe( ialu_reg_long );
9157 %}
9158
9159 // Shift Left Long by 32-63
9160 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9161 match(Set dst (LShiftL dst cnt));
9162 effect(KILL cr);
9163 ins_cost(300);
9164 format %{ "MOV $dst.hi,$dst.lo\n"
9165 "\tSHL $dst.hi,$cnt-32\n"
9166 "\tXOR $dst.lo,$dst.lo" %}
9167 opcode(0xC1, 0x4); /* C1 /4 ib */
9168 ins_encode( move_long_big_shift_clr(dst,cnt) );
9169 ins_pipe( ialu_reg_long );
9170 %}
9171
9172 // Shift Left Long by variable
9173 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9174 match(Set dst (LShiftL dst shift));
9175 effect(KILL cr);
9176 ins_cost(500+200);
9177 size(17);
9178 format %{ "TEST $shift,32\n\t"
9179 "JEQ,s small\n\t"
9180 "MOV $dst.hi,$dst.lo\n\t"
9181 "XOR $dst.lo,$dst.lo\n"
9182 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9183 "SHL $dst.lo,$shift" %}
9184 ins_encode( shift_left_long( dst, shift ) );
9185 ins_pipe( pipe_slow );
9186 %}
9187
9188 // Shift Right Long by 1-31
9189 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9190 match(Set dst (URShiftL dst cnt));
9191 effect(KILL cr);
9192 ins_cost(200);
9193 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9194 "SHR $dst.hi,$cnt" %}
9195 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9196 ins_encode( move_long_small_shift(dst,cnt) );
9197 ins_pipe( ialu_reg_long );
9198 %}
9199
9200 // Shift Right Long by 32-63
9201 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9202 match(Set dst (URShiftL dst cnt));
9203 effect(KILL cr);
9204 ins_cost(300);
9205 format %{ "MOV $dst.lo,$dst.hi\n"
9206 "\tSHR $dst.lo,$cnt-32\n"
9207 "\tXOR $dst.hi,$dst.hi" %}
9208 opcode(0xC1, 0x5); /* C1 /5 ib */
9209 ins_encode( move_long_big_shift_clr(dst,cnt) );
9210 ins_pipe( ialu_reg_long );
9211 %}
9212
9213 // Shift Right Long by variable
9214 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9215 match(Set dst (URShiftL dst shift));
9216 effect(KILL cr);
9217 ins_cost(600);
9218 size(17);
9219 format %{ "TEST $shift,32\n\t"
9220 "JEQ,s small\n\t"
9221 "MOV $dst.lo,$dst.hi\n\t"
9222 "XOR $dst.hi,$dst.hi\n"
9223 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9224 "SHR $dst.hi,$shift" %}
9225 ins_encode( shift_right_long( dst, shift ) );
9226 ins_pipe( pipe_slow );
9227 %}
9228
9229 // Shift Right Long by 1-31
9230 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9231 match(Set dst (RShiftL dst cnt));
9232 effect(KILL cr);
9233 ins_cost(200);
9234 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9235 "SAR $dst.hi,$cnt" %}
9236 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9237 ins_encode( move_long_small_shift(dst,cnt) );
9238 ins_pipe( ialu_reg_long );
9239 %}
9240
9241 // Shift Right Long by 32-63
9242 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9243 match(Set dst (RShiftL dst cnt));
9244 effect(KILL cr);
9245 ins_cost(300);
9246 format %{ "MOV $dst.lo,$dst.hi\n"
9247 "\tSAR $dst.lo,$cnt-32\n"
9248 "\tSAR $dst.hi,31" %}
9249 opcode(0xC1, 0x7); /* C1 /7 ib */
9250 ins_encode( move_long_big_shift_sign(dst,cnt) );
9251 ins_pipe( ialu_reg_long );
9252 %}
9253
9254 // Shift Right arithmetic Long by variable
9255 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9256 match(Set dst (RShiftL dst shift));
9257 effect(KILL cr);
9258 ins_cost(600);
9259 size(18);
9260 format %{ "TEST $shift,32\n\t"
9261 "JEQ,s small\n\t"
9262 "MOV $dst.lo,$dst.hi\n\t"
9263 "SAR $dst.hi,31\n"
9264 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9265 "SAR $dst.hi,$shift" %}
9266 ins_encode( shift_right_arith_long( dst, shift ) );
9267 ins_pipe( pipe_slow );
9268 %}
9269
9270
9271 //----------Double Instructions------------------------------------------------
9272 // Double Math
9273
9274 // Compare & branch
9275
9276 // P6 version of float compare, sets condition codes in EFLAGS
9277 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9278 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9279 match(Set cr (CmpD src1 src2));
9280 effect(KILL rax);
9281 ins_cost(150);
9282 format %{ "FLD $src1\n\t"
9283 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9284 "JNP exit\n\t"
9285 "MOV ah,1 // saw a NaN, set CF\n\t"
9286 "SAHF\n"
9287 "exit:\tNOP // avoid branch to branch" %}
9288 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9289 ins_encode( Push_Reg_DPR(src1),
9290 OpcP, RegOpc(src2),
9291 cmpF_P6_fixup );
9292 ins_pipe( pipe_slow );
9293 %}
9294
9295 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9296 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9297 match(Set cr (CmpD src1 src2));
9298 ins_cost(150);
9299 format %{ "FLD $src1\n\t"
9300 "FUCOMIP ST,$src2 // P6 instruction" %}
9301 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9302 ins_encode( Push_Reg_DPR(src1),
9303 OpcP, RegOpc(src2));
9304 ins_pipe( pipe_slow );
9305 %}
9306
9307 // Compare & branch
9308 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9309 predicate(UseSSE<=1);
9310 match(Set cr (CmpD src1 src2));
9311 effect(KILL rax);
9312 ins_cost(200);
9313 format %{ "FLD $src1\n\t"
9314 "FCOMp $src2\n\t"
9315 "FNSTSW AX\n\t"
9316 "TEST AX,0x400\n\t"
9317 "JZ,s flags\n\t"
9318 "MOV AH,1\t# unordered treat as LT\n"
9319 "flags:\tSAHF" %}
9320 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9321 ins_encode( Push_Reg_DPR(src1),
9322 OpcP, RegOpc(src2),
9323 fpu_flags);
9324 ins_pipe( pipe_slow );
9325 %}
9326
9327 // Compare vs zero into -1,0,1
9328 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9329 predicate(UseSSE<=1);
9330 match(Set dst (CmpD3 src1 zero));
9331 effect(KILL cr, KILL rax);
9332 ins_cost(280);
9333 format %{ "FTSTD $dst,$src1" %}
9334 opcode(0xE4, 0xD9);
9335 ins_encode( Push_Reg_DPR(src1),
9336 OpcS, OpcP, PopFPU,
9337 CmpF_Result(dst));
9338 ins_pipe( pipe_slow );
9339 %}
9340
9341 // Compare into -1,0,1
9342 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9343 predicate(UseSSE<=1);
9344 match(Set dst (CmpD3 src1 src2));
9345 effect(KILL cr, KILL rax);
9346 ins_cost(300);
9347 format %{ "FCMPD $dst,$src1,$src2" %}
9348 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9349 ins_encode( Push_Reg_DPR(src1),
9350 OpcP, RegOpc(src2),
9351 CmpF_Result(dst));
9352 ins_pipe( pipe_slow );
9353 %}
9354
9355 // float compare and set condition codes in EFLAGS by XMM regs
9356 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9357 predicate(UseSSE>=2);
9358 match(Set cr (CmpD src1 src2));
9359 ins_cost(145);
9360 format %{ "UCOMISD $src1,$src2\n\t"
9361 "JNP,s exit\n\t"
9362 "PUSHF\t# saw NaN, set CF\n\t"
9363 "AND [rsp], #0xffffff2b\n\t"
9364 "POPF\n"
9365 "exit:" %}
9366 ins_encode %{
9367 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9368 emit_cmpfp_fixup(_masm);
9369 %}
9370 ins_pipe( pipe_slow );
9371 %}
9372
9373 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9374 predicate(UseSSE>=2);
9375 match(Set cr (CmpD src1 src2));
9376 ins_cost(100);
9377 format %{ "UCOMISD $src1,$src2" %}
9378 ins_encode %{
9379 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9380 %}
9381 ins_pipe( pipe_slow );
9382 %}
9383
9384 // float compare and set condition codes in EFLAGS by XMM regs
9385 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9386 predicate(UseSSE>=2);
9387 match(Set cr (CmpD src1 (LoadD src2)));
9388 ins_cost(145);
9389 format %{ "UCOMISD $src1,$src2\n\t"
9390 "JNP,s exit\n\t"
9391 "PUSHF\t# saw NaN, set CF\n\t"
9392 "AND [rsp], #0xffffff2b\n\t"
9393 "POPF\n"
9394 "exit:" %}
9395 ins_encode %{
9396 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9397 emit_cmpfp_fixup(_masm);
9398 %}
9399 ins_pipe( pipe_slow );
9400 %}
9401
9402 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9403 predicate(UseSSE>=2);
9404 match(Set cr (CmpD src1 (LoadD src2)));
9405 ins_cost(100);
9406 format %{ "UCOMISD $src1,$src2" %}
9407 ins_encode %{
9408 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9409 %}
9410 ins_pipe( pipe_slow );
9411 %}
9412
9413 // Compare into -1,0,1 in XMM
9414 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9415 predicate(UseSSE>=2);
9416 match(Set dst (CmpD3 src1 src2));
9417 effect(KILL cr);
9418 ins_cost(255);
9419 format %{ "UCOMISD $src1, $src2\n\t"
9420 "MOV $dst, #-1\n\t"
9421 "JP,s done\n\t"
9422 "JB,s done\n\t"
9423 "SETNE $dst\n\t"
9424 "MOVZB $dst, $dst\n"
9425 "done:" %}
9426 ins_encode %{
9427 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9428 emit_cmpfp3(_masm, $dst$$Register);
9429 %}
9430 ins_pipe( pipe_slow );
9431 %}
9432
9433 // Compare into -1,0,1 in XMM and memory
9434 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9435 predicate(UseSSE>=2);
9436 match(Set dst (CmpD3 src1 (LoadD src2)));
9437 effect(KILL cr);
9438 ins_cost(275);
9439 format %{ "UCOMISD $src1, $src2\n\t"
9440 "MOV $dst, #-1\n\t"
9441 "JP,s done\n\t"
9442 "JB,s done\n\t"
9443 "SETNE $dst\n\t"
9444 "MOVZB $dst, $dst\n"
9445 "done:" %}
9446 ins_encode %{
9447 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9448 emit_cmpfp3(_masm, $dst$$Register);
9449 %}
9450 ins_pipe( pipe_slow );
9451 %}
9452
9453
9454 instruct subDPR_reg(regDPR dst, regDPR src) %{
9455 predicate (UseSSE <=1);
9456 match(Set dst (SubD dst src));
9457
9458 format %{ "FLD $src\n\t"
9459 "DSUBp $dst,ST" %}
9460 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9461 ins_cost(150);
9462 ins_encode( Push_Reg_DPR(src),
9463 OpcP, RegOpc(dst) );
9464 ins_pipe( fpu_reg_reg );
9465 %}
9466
9467 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9468 predicate (UseSSE <=1);
9469 match(Set dst (RoundDouble (SubD src1 src2)));
9470 ins_cost(250);
9471
9472 format %{ "FLD $src2\n\t"
9473 "DSUB ST,$src1\n\t"
9474 "FSTP_D $dst\t# D-round" %}
9475 opcode(0xD8, 0x5);
9476 ins_encode( Push_Reg_DPR(src2),
9477 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9478 ins_pipe( fpu_mem_reg_reg );
9479 %}
9480
9481
9482 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9483 predicate (UseSSE <=1);
9484 match(Set dst (SubD dst (LoadD src)));
9485 ins_cost(150);
9486
9487 format %{ "FLD $src\n\t"
9488 "DSUBp $dst,ST" %}
9489 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9490 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9491 OpcP, RegOpc(dst) );
9492 ins_pipe( fpu_reg_mem );
9493 %}
9494
9495 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9496 predicate (UseSSE<=1);
9497 match(Set dst (AbsD src));
9498 ins_cost(100);
9499 format %{ "FABS" %}
9500 opcode(0xE1, 0xD9);
9501 ins_encode( OpcS, OpcP );
9502 ins_pipe( fpu_reg_reg );
9503 %}
9504
9505 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9506 predicate(UseSSE<=1);
9507 match(Set dst (NegD src));
9508 ins_cost(100);
9509 format %{ "FCHS" %}
9510 opcode(0xE0, 0xD9);
9511 ins_encode( OpcS, OpcP );
9512 ins_pipe( fpu_reg_reg );
9513 %}
9514
9515 instruct addDPR_reg(regDPR dst, regDPR src) %{
9516 predicate(UseSSE<=1);
9517 match(Set dst (AddD dst src));
9518 format %{ "FLD $src\n\t"
9519 "DADD $dst,ST" %}
9520 size(4);
9521 ins_cost(150);
9522 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9523 ins_encode( Push_Reg_DPR(src),
9524 OpcP, RegOpc(dst) );
9525 ins_pipe( fpu_reg_reg );
9526 %}
9527
9528
9529 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9530 predicate(UseSSE<=1);
9531 match(Set dst (RoundDouble (AddD src1 src2)));
9532 ins_cost(250);
9533
9534 format %{ "FLD $src2\n\t"
9535 "DADD ST,$src1\n\t"
9536 "FSTP_D $dst\t# D-round" %}
9537 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9538 ins_encode( Push_Reg_DPR(src2),
9539 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9540 ins_pipe( fpu_mem_reg_reg );
9541 %}
9542
9543
9544 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9545 predicate(UseSSE<=1);
9546 match(Set dst (AddD dst (LoadD src)));
9547 ins_cost(150);
9548
9549 format %{ "FLD $src\n\t"
9550 "DADDp $dst,ST" %}
9551 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9552 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9553 OpcP, RegOpc(dst) );
9554 ins_pipe( fpu_reg_mem );
9555 %}
9556
9557 // add-to-memory
9558 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9559 predicate(UseSSE<=1);
9560 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9561 ins_cost(150);
9562
9563 format %{ "FLD_D $dst\n\t"
9564 "DADD ST,$src\n\t"
9565 "FST_D $dst" %}
9566 opcode(0xDD, 0x0);
9567 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9568 Opcode(0xD8), RegOpc(src),
9569 set_instruction_start,
9570 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9571 ins_pipe( fpu_reg_mem );
9572 %}
9573
9574 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9575 predicate(UseSSE<=1);
9576 match(Set dst (AddD dst con));
9577 ins_cost(125);
9578 format %{ "FLD1\n\t"
9579 "DADDp $dst,ST" %}
9580 ins_encode %{
9581 __ fld1();
9582 __ faddp($dst$$reg);
9583 %}
9584 ins_pipe(fpu_reg);
9585 %}
9586
9587 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9588 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9589 match(Set dst (AddD dst con));
9590 ins_cost(200);
9591 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9592 "DADDp $dst,ST" %}
9593 ins_encode %{
9594 __ fld_d($constantaddress($con));
9595 __ faddp($dst$$reg);
9596 %}
9597 ins_pipe(fpu_reg_mem);
9598 %}
9599
9600 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9601 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9602 match(Set dst (RoundDouble (AddD src con)));
9603 ins_cost(200);
9604 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9605 "DADD ST,$src\n\t"
9606 "FSTP_D $dst\t# D-round" %}
9607 ins_encode %{
9608 __ fld_d($constantaddress($con));
9609 __ fadd($src$$reg);
9610 __ fstp_d(Address(rsp, $dst$$disp));
9611 %}
9612 ins_pipe(fpu_mem_reg_con);
9613 %}
9614
9615 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9616 predicate(UseSSE<=1);
9617 match(Set dst (MulD dst src));
9618 format %{ "FLD $src\n\t"
9619 "DMULp $dst,ST" %}
9620 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9621 ins_cost(150);
9622 ins_encode( Push_Reg_DPR(src),
9623 OpcP, RegOpc(dst) );
9624 ins_pipe( fpu_reg_reg );
9625 %}
9626
9627 // Strict FP instruction biases argument before multiply then
9628 // biases result to avoid double rounding of subnormals.
9629 //
9630 // scale arg1 by multiplying arg1 by 2^(-15360)
9631 // load arg2
9632 // multiply scaled arg1 by arg2
9633 // rescale product by 2^(15360)
9634 //
9635 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9636 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9637 match(Set dst (MulD dst src));
9638 ins_cost(1); // Select this instruction for all strict FP double multiplies
9639
9640 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9641 "DMULp $dst,ST\n\t"
9642 "FLD $src\n\t"
9643 "DMULp $dst,ST\n\t"
9644 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9645 "DMULp $dst,ST\n\t" %}
9646 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9647 ins_encode( strictfp_bias1(dst),
9648 Push_Reg_DPR(src),
9649 OpcP, RegOpc(dst),
9650 strictfp_bias2(dst) );
9651 ins_pipe( fpu_reg_reg );
9652 %}
9653
9654 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9655 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9656 match(Set dst (MulD dst con));
9657 ins_cost(200);
9658 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9659 "DMULp $dst,ST" %}
9660 ins_encode %{
9661 __ fld_d($constantaddress($con));
9662 __ fmulp($dst$$reg);
9663 %}
9664 ins_pipe(fpu_reg_mem);
9665 %}
9666
9667
9668 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9669 predicate( UseSSE<=1 );
9670 match(Set dst (MulD dst (LoadD src)));
9671 ins_cost(200);
9672 format %{ "FLD_D $src\n\t"
9673 "DMULp $dst,ST" %}
9674 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9675 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9676 OpcP, RegOpc(dst) );
9677 ins_pipe( fpu_reg_mem );
9678 %}
9679
9680 //
9681 // Cisc-alternate to reg-reg multiply
9682 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9683 predicate( UseSSE<=1 );
9684 match(Set dst (MulD src (LoadD mem)));
9685 ins_cost(250);
9686 format %{ "FLD_D $mem\n\t"
9687 "DMUL ST,$src\n\t"
9688 "FSTP_D $dst" %}
9689 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9690 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9691 OpcReg_FPR(src),
9692 Pop_Reg_DPR(dst) );
9693 ins_pipe( fpu_reg_reg_mem );
9694 %}
9695
9696
9697 // MACRO3 -- addDPR a mulDPR
9698 // This instruction is a '2-address' instruction in that the result goes
9699 // back to src2. This eliminates a move from the macro; possibly the
9700 // register allocator will have to add it back (and maybe not).
9701 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9702 predicate( UseSSE<=1 );
9703 match(Set src2 (AddD (MulD src0 src1) src2));
9704 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9705 "DMUL ST,$src1\n\t"
9706 "DADDp $src2,ST" %}
9707 ins_cost(250);
9708 opcode(0xDD); /* LoadD DD /0 */
9709 ins_encode( Push_Reg_FPR(src0),
9710 FMul_ST_reg(src1),
9711 FAddP_reg_ST(src2) );
9712 ins_pipe( fpu_reg_reg_reg );
9713 %}
9714
9715
9716 // MACRO3 -- subDPR a mulDPR
9717 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9718 predicate( UseSSE<=1 );
9719 match(Set src2 (SubD (MulD src0 src1) src2));
9720 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9721 "DMUL ST,$src1\n\t"
9722 "DSUBRp $src2,ST" %}
9723 ins_cost(250);
9724 ins_encode( Push_Reg_FPR(src0),
9725 FMul_ST_reg(src1),
9726 Opcode(0xDE), Opc_plus(0xE0,src2));
9727 ins_pipe( fpu_reg_reg_reg );
9728 %}
9729
9730
9731 instruct divDPR_reg(regDPR dst, regDPR src) %{
9732 predicate( UseSSE<=1 );
9733 match(Set dst (DivD dst src));
9734
9735 format %{ "FLD $src\n\t"
9736 "FDIVp $dst,ST" %}
9737 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9738 ins_cost(150);
9739 ins_encode( Push_Reg_DPR(src),
9740 OpcP, RegOpc(dst) );
9741 ins_pipe( fpu_reg_reg );
9742 %}
9743
9744 // Strict FP instruction biases argument before division then
9745 // biases result, to avoid double rounding of subnormals.
9746 //
9747 // scale dividend by multiplying dividend by 2^(-15360)
9748 // load divisor
9749 // divide scaled dividend by divisor
9750 // rescale quotient by 2^(15360)
9751 //
9752 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9753 predicate (UseSSE<=1);
9754 match(Set dst (DivD dst src));
9755 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9756 ins_cost(01);
9757
9758 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9759 "DMULp $dst,ST\n\t"
9760 "FLD $src\n\t"
9761 "FDIVp $dst,ST\n\t"
9762 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9763 "DMULp $dst,ST\n\t" %}
9764 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9765 ins_encode( strictfp_bias1(dst),
9766 Push_Reg_DPR(src),
9767 OpcP, RegOpc(dst),
9768 strictfp_bias2(dst) );
9769 ins_pipe( fpu_reg_reg );
9770 %}
9771
9772 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9773 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9774 match(Set dst (RoundDouble (DivD src1 src2)));
9775
9776 format %{ "FLD $src1\n\t"
9777 "FDIV ST,$src2\n\t"
9778 "FSTP_D $dst\t# D-round" %}
9779 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9780 ins_encode( Push_Reg_DPR(src1),
9781 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9782 ins_pipe( fpu_mem_reg_reg );
9783 %}
9784
9785
9786 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9787 predicate(UseSSE<=1);
9788 match(Set dst (ModD dst src));
9789 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9790
9791 format %{ "DMOD $dst,$src" %}
9792 ins_cost(250);
9793 ins_encode(Push_Reg_Mod_DPR(dst, src),
9794 emitModDPR(),
9795 Push_Result_Mod_DPR(src),
9796 Pop_Reg_DPR(dst));
9797 ins_pipe( pipe_slow );
9798 %}
9799
9800 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9801 predicate(UseSSE>=2);
9802 match(Set dst (ModD src0 src1));
9803 effect(KILL rax, KILL cr);
9804
9805 format %{ "SUB ESP,8\t # DMOD\n"
9806 "\tMOVSD [ESP+0],$src1\n"
9807 "\tFLD_D [ESP+0]\n"
9808 "\tMOVSD [ESP+0],$src0\n"
9809 "\tFLD_D [ESP+0]\n"
9810 "loop:\tFPREM\n"
9811 "\tFWAIT\n"
9812 "\tFNSTSW AX\n"
9813 "\tSAHF\n"
9814 "\tJP loop\n"
9815 "\tFSTP_D [ESP+0]\n"
9816 "\tMOVSD $dst,[ESP+0]\n"
9817 "\tADD ESP,8\n"
9818 "\tFSTP ST0\t # Restore FPU Stack"
9819 %}
9820 ins_cost(250);
9821 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9822 ins_pipe( pipe_slow );
9823 %}
9824
9825 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9826 predicate (UseSSE<=1);
9827 match(Set dst (SinD src));
9828 ins_cost(1800);
9829 format %{ "DSIN $dst" %}
9830 opcode(0xD9, 0xFE);
9831 ins_encode( OpcP, OpcS );
9832 ins_pipe( pipe_slow );
9833 %}
9834
9835 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9836 predicate (UseSSE>=2);
9837 match(Set dst (SinD dst));
9838 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9839 ins_cost(1800);
9840 format %{ "DSIN $dst" %}
9841 opcode(0xD9, 0xFE);
9842 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9843 ins_pipe( pipe_slow );
9844 %}
9845
9846 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9847 predicate (UseSSE<=1);
9848 match(Set dst (CosD src));
9849 ins_cost(1800);
9850 format %{ "DCOS $dst" %}
9851 opcode(0xD9, 0xFF);
9852 ins_encode( OpcP, OpcS );
9853 ins_pipe( pipe_slow );
9854 %}
9855
9856 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9857 predicate (UseSSE>=2);
9858 match(Set dst (CosD dst));
9859 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9860 ins_cost(1800);
9861 format %{ "DCOS $dst" %}
9862 opcode(0xD9, 0xFF);
9863 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9864 ins_pipe( pipe_slow );
9865 %}
9866
9867 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9868 predicate (UseSSE<=1);
9869 match(Set dst(TanD src));
9870 format %{ "DTAN $dst" %}
9871 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9872 Opcode(0xDD), Opcode(0xD8)); // fstp st
9873 ins_pipe( pipe_slow );
9874 %}
9875
9876 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9877 predicate (UseSSE>=2);
9878 match(Set dst(TanD dst));
9879 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9880 format %{ "DTAN $dst" %}
9881 ins_encode( Push_SrcD(dst),
9882 Opcode(0xD9), Opcode(0xF2), // fptan
9883 Opcode(0xDD), Opcode(0xD8), // fstp st
9884 Push_ResultD(dst) );
9885 ins_pipe( pipe_slow );
9886 %}
9887
9888 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9889 predicate (UseSSE<=1);
9890 match(Set dst(AtanD dst src));
9891 format %{ "DATA $dst,$src" %}
9892 opcode(0xD9, 0xF3);
9893 ins_encode( Push_Reg_DPR(src),
9894 OpcP, OpcS, RegOpc(dst) );
9895 ins_pipe( pipe_slow );
9896 %}
9897
9898 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9899 predicate (UseSSE>=2);
9900 match(Set dst(AtanD dst src));
9901 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9902 format %{ "DATA $dst,$src" %}
9903 opcode(0xD9, 0xF3);
9904 ins_encode( Push_SrcD(src),
9905 OpcP, OpcS, Push_ResultD(dst) );
9906 ins_pipe( pipe_slow );
9907 %}
9908
9909 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9910 predicate (UseSSE<=1);
9911 match(Set dst (SqrtD src));
9912 format %{ "DSQRT $dst,$src" %}
9913 opcode(0xFA, 0xD9);
9914 ins_encode( Push_Reg_DPR(src),
9915 OpcS, OpcP, Pop_Reg_DPR(dst) );
9916 ins_pipe( pipe_slow );
9917 %}
9918
9919 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9920 predicate (UseSSE<=1);
9921 match(Set Y (PowD X Y)); // Raise X to the Yth power
9922 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9923 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9924 ins_encode %{
9925 __ subptr(rsp, 8);
9926 __ fld_s($X$$reg - 1);
9927 __ fast_pow();
9928 __ addptr(rsp, 8);
9929 %}
9930 ins_pipe( pipe_slow );
9931 %}
9932
9933 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9934 predicate (UseSSE>=2);
9935 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9936 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9937 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9938 ins_encode %{
9939 __ subptr(rsp, 8);
9940 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9941 __ fld_d(Address(rsp, 0));
9942 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9943 __ fld_d(Address(rsp, 0));
9944 __ fast_pow();
9945 __ fstp_d(Address(rsp, 0));
9946 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9947 __ addptr(rsp, 8);
9948 %}
9949 ins_pipe( pipe_slow );
9950 %}
9951
9952
9953 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9954 predicate (UseSSE<=1);
9955 match(Set dpr1 (ExpD dpr1));
9956 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9957 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
9958 ins_encode %{
9959 __ fast_exp();
9960 %}
9961 ins_pipe( pipe_slow );
9962 %}
9963
9964 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9965 predicate (UseSSE>=2);
9966 match(Set dst (ExpD src));
9967 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9968 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9969 ins_encode %{
9970 __ subptr(rsp, 8);
9971 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9972 __ fld_d(Address(rsp, 0));
9973 __ fast_exp();
9974 __ fstp_d(Address(rsp, 0));
9975 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9976 __ addptr(rsp, 8);
9977 %}
9978 ins_pipe( pipe_slow );
9979 %}
9980
9981 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9982 predicate (UseSSE<=1);
9983 // The source Double operand on FPU stack
9984 match(Set dst (Log10D src));
9985 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9986 // fxch ; swap ST(0) with ST(1)
9987 // fyl2x ; compute log_10(2) * log_2(x)
9988 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9989 "FXCH \n\t"
9990 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9991 %}
9992 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9993 Opcode(0xD9), Opcode(0xC9), // fxch
9994 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9995
9996 ins_pipe( pipe_slow );
9997 %}
9998
9999 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10000 predicate (UseSSE>=2);
10001 effect(KILL cr);
10002 match(Set dst (Log10D src));
10003 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10004 // fyl2x ; compute log_10(2) * log_2(x)
10005 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10006 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10007 %}
10008 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10009 Push_SrcD(src),
10010 Opcode(0xD9), Opcode(0xF1), // fyl2x
10011 Push_ResultD(dst));
10012
10013 ins_pipe( pipe_slow );
10014 %}
10015
10016 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10017 predicate (UseSSE<=1);
10018 // The source Double operand on FPU stack
10019 match(Set dst (LogD src));
10020 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10021 // fxch ; swap ST(0) with ST(1)
10022 // fyl2x ; compute log_e(2) * log_2(x)
10023 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10024 "FXCH \n\t"
10025 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10026 %}
10027 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10028 Opcode(0xD9), Opcode(0xC9), // fxch
10029 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10030
10031 ins_pipe( pipe_slow );
10032 %}
10033
10034 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10035 predicate (UseSSE>=2);
10036 effect(KILL cr);
10037 // The source and result Double operands in XMM registers
10038 match(Set dst (LogD src));
10039 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10040 // fyl2x ; compute log_e(2) * log_2(x)
10041 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10042 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10043 %}
10044 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10045 Push_SrcD(src),
10046 Opcode(0xD9), Opcode(0xF1), // fyl2x
10047 Push_ResultD(dst));
10048 ins_pipe( pipe_slow );
10049 %}
10050
10051 //-------------Float Instructions-------------------------------
10052 // Float Math
10053
10054 // Code for float compare:
10055 // fcompp();
10056 // fwait(); fnstsw_ax();
10057 // sahf();
10058 // movl(dst, unordered_result);
10059 // jcc(Assembler::parity, exit);
10060 // movl(dst, less_result);
10061 // jcc(Assembler::below, exit);
10062 // movl(dst, equal_result);
10063 // jcc(Assembler::equal, exit);
10064 // movl(dst, greater_result);
10065 // exit:
10066
10067 // P6 version of float compare, sets condition codes in EFLAGS
10068 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10069 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10070 match(Set cr (CmpF src1 src2));
10071 effect(KILL rax);
10072 ins_cost(150);
10073 format %{ "FLD $src1\n\t"
10074 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10075 "JNP exit\n\t"
10076 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10077 "SAHF\n"
10078 "exit:\tNOP // avoid branch to branch" %}
10079 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10080 ins_encode( Push_Reg_DPR(src1),
10081 OpcP, RegOpc(src2),
10082 cmpF_P6_fixup );
10083 ins_pipe( pipe_slow );
10084 %}
10085
10086 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10087 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10088 match(Set cr (CmpF src1 src2));
10089 ins_cost(100);
10090 format %{ "FLD $src1\n\t"
10091 "FUCOMIP ST,$src2 // P6 instruction" %}
10092 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10093 ins_encode( Push_Reg_DPR(src1),
10094 OpcP, RegOpc(src2));
10095 ins_pipe( pipe_slow );
10096 %}
10097
10098
10099 // Compare & branch
10100 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10101 predicate(UseSSE == 0);
10102 match(Set cr (CmpF src1 src2));
10103 effect(KILL rax);
10104 ins_cost(200);
10105 format %{ "FLD $src1\n\t"
10106 "FCOMp $src2\n\t"
10107 "FNSTSW AX\n\t"
10108 "TEST AX,0x400\n\t"
10109 "JZ,s flags\n\t"
10110 "MOV AH,1\t# unordered treat as LT\n"
10111 "flags:\tSAHF" %}
10112 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10113 ins_encode( Push_Reg_DPR(src1),
10114 OpcP, RegOpc(src2),
10115 fpu_flags);
10116 ins_pipe( pipe_slow );
10117 %}
10118
10119 // Compare vs zero into -1,0,1
10120 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10121 predicate(UseSSE == 0);
10122 match(Set dst (CmpF3 src1 zero));
10123 effect(KILL cr, KILL rax);
10124 ins_cost(280);
10125 format %{ "FTSTF $dst,$src1" %}
10126 opcode(0xE4, 0xD9);
10127 ins_encode( Push_Reg_DPR(src1),
10128 OpcS, OpcP, PopFPU,
10129 CmpF_Result(dst));
10130 ins_pipe( pipe_slow );
10131 %}
10132
10133 // Compare into -1,0,1
10134 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10135 predicate(UseSSE == 0);
10136 match(Set dst (CmpF3 src1 src2));
10137 effect(KILL cr, KILL rax);
10138 ins_cost(300);
10139 format %{ "FCMPF $dst,$src1,$src2" %}
10140 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10141 ins_encode( Push_Reg_DPR(src1),
10142 OpcP, RegOpc(src2),
10143 CmpF_Result(dst));
10144 ins_pipe( pipe_slow );
10145 %}
10146
10147 // float compare and set condition codes in EFLAGS by XMM regs
10148 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10149 predicate(UseSSE>=1);
10150 match(Set cr (CmpF src1 src2));
10151 ins_cost(145);
10152 format %{ "UCOMISS $src1,$src2\n\t"
10153 "JNP,s exit\n\t"
10154 "PUSHF\t# saw NaN, set CF\n\t"
10155 "AND [rsp], #0xffffff2b\n\t"
10156 "POPF\n"
10157 "exit:" %}
10158 ins_encode %{
10159 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10160 emit_cmpfp_fixup(_masm);
10161 %}
10162 ins_pipe( pipe_slow );
10163 %}
10164
10165 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10166 predicate(UseSSE>=1);
10167 match(Set cr (CmpF src1 src2));
10168 ins_cost(100);
10169 format %{ "UCOMISS $src1,$src2" %}
10170 ins_encode %{
10171 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10172 %}
10173 ins_pipe( pipe_slow );
10174 %}
10175
10176 // float compare and set condition codes in EFLAGS by XMM regs
10177 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10178 predicate(UseSSE>=1);
10179 match(Set cr (CmpF src1 (LoadF src2)));
10180 ins_cost(165);
10181 format %{ "UCOMISS $src1,$src2\n\t"
10182 "JNP,s exit\n\t"
10183 "PUSHF\t# saw NaN, set CF\n\t"
10184 "AND [rsp], #0xffffff2b\n\t"
10185 "POPF\n"
10186 "exit:" %}
10187 ins_encode %{
10188 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10189 emit_cmpfp_fixup(_masm);
10190 %}
10191 ins_pipe( pipe_slow );
10192 %}
10193
10194 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10195 predicate(UseSSE>=1);
10196 match(Set cr (CmpF src1 (LoadF src2)));
10197 ins_cost(100);
10198 format %{ "UCOMISS $src1,$src2" %}
10199 ins_encode %{
10200 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10201 %}
10202 ins_pipe( pipe_slow );
10203 %}
10204
10205 // Compare into -1,0,1 in XMM
10206 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10207 predicate(UseSSE>=1);
10208 match(Set dst (CmpF3 src1 src2));
10209 effect(KILL cr);
10210 ins_cost(255);
10211 format %{ "UCOMISS $src1, $src2\n\t"
10212 "MOV $dst, #-1\n\t"
10213 "JP,s done\n\t"
10214 "JB,s done\n\t"
10215 "SETNE $dst\n\t"
10216 "MOVZB $dst, $dst\n"
10217 "done:" %}
10218 ins_encode %{
10219 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10220 emit_cmpfp3(_masm, $dst$$Register);
10221 %}
10222 ins_pipe( pipe_slow );
10223 %}
10224
10225 // Compare into -1,0,1 in XMM and memory
10226 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10227 predicate(UseSSE>=1);
10228 match(Set dst (CmpF3 src1 (LoadF src2)));
10229 effect(KILL cr);
10230 ins_cost(275);
10231 format %{ "UCOMISS $src1, $src2\n\t"
10232 "MOV $dst, #-1\n\t"
10233 "JP,s done\n\t"
10234 "JB,s done\n\t"
10235 "SETNE $dst\n\t"
10236 "MOVZB $dst, $dst\n"
10237 "done:" %}
10238 ins_encode %{
10239 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10240 emit_cmpfp3(_masm, $dst$$Register);
10241 %}
10242 ins_pipe( pipe_slow );
10243 %}
10244
10245 // Spill to obtain 24-bit precision
10246 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10247 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10248 match(Set dst (SubF src1 src2));
10249
10250 format %{ "FSUB $dst,$src1 - $src2" %}
10251 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10252 ins_encode( Push_Reg_FPR(src1),
10253 OpcReg_FPR(src2),
10254 Pop_Mem_FPR(dst) );
10255 ins_pipe( fpu_mem_reg_reg );
10256 %}
10257 //
10258 // This instruction does not round to 24-bits
10259 instruct subFPR_reg(regFPR dst, regFPR src) %{
10260 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10261 match(Set dst (SubF dst src));
10262
10263 format %{ "FSUB $dst,$src" %}
10264 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10265 ins_encode( Push_Reg_FPR(src),
10266 OpcP, RegOpc(dst) );
10267 ins_pipe( fpu_reg_reg );
10268 %}
10269
10270 // Spill to obtain 24-bit precision
10271 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10272 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10273 match(Set dst (AddF src1 src2));
10274
10275 format %{ "FADD $dst,$src1,$src2" %}
10276 opcode(0xD8, 0x0); /* D8 C0+i */
10277 ins_encode( Push_Reg_FPR(src2),
10278 OpcReg_FPR(src1),
10279 Pop_Mem_FPR(dst) );
10280 ins_pipe( fpu_mem_reg_reg );
10281 %}
10282 //
10283 // This instruction does not round to 24-bits
10284 instruct addFPR_reg(regFPR dst, regFPR src) %{
10285 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10286 match(Set dst (AddF dst src));
10287
10288 format %{ "FLD $src\n\t"
10289 "FADDp $dst,ST" %}
10290 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10291 ins_encode( Push_Reg_FPR(src),
10292 OpcP, RegOpc(dst) );
10293 ins_pipe( fpu_reg_reg );
10294 %}
10295
10296 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10297 predicate(UseSSE==0);
10298 match(Set dst (AbsF src));
10299 ins_cost(100);
10300 format %{ "FABS" %}
10301 opcode(0xE1, 0xD9);
10302 ins_encode( OpcS, OpcP );
10303 ins_pipe( fpu_reg_reg );
10304 %}
10305
10306 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10307 predicate(UseSSE==0);
10308 match(Set dst (NegF src));
10309 ins_cost(100);
10310 format %{ "FCHS" %}
10311 opcode(0xE0, 0xD9);
10312 ins_encode( OpcS, OpcP );
10313 ins_pipe( fpu_reg_reg );
10314 %}
10315
10316 // Cisc-alternate to addFPR_reg
10317 // Spill to obtain 24-bit precision
10318 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10319 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10320 match(Set dst (AddF src1 (LoadF src2)));
10321
10322 format %{ "FLD $src2\n\t"
10323 "FADD ST,$src1\n\t"
10324 "FSTP_S $dst" %}
10325 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10326 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10327 OpcReg_FPR(src1),
10328 Pop_Mem_FPR(dst) );
10329 ins_pipe( fpu_mem_reg_mem );
10330 %}
10331 //
10332 // Cisc-alternate to addFPR_reg
10333 // This instruction does not round to 24-bits
10334 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10335 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10336 match(Set dst (AddF dst (LoadF src)));
10337
10338 format %{ "FADD $dst,$src" %}
10339 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10340 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10341 OpcP, RegOpc(dst) );
10342 ins_pipe( fpu_reg_mem );
10343 %}
10344
10345 // // Following two instructions for _222_mpegaudio
10346 // Spill to obtain 24-bit precision
10347 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10348 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10349 match(Set dst (AddF src1 src2));
10350
10351 format %{ "FADD $dst,$src1,$src2" %}
10352 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10353 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10354 OpcReg_FPR(src2),
10355 Pop_Mem_FPR(dst) );
10356 ins_pipe( fpu_mem_reg_mem );
10357 %}
10358
10359 // Cisc-spill variant
10360 // Spill to obtain 24-bit precision
10361 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10362 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10363 match(Set dst (AddF src1 (LoadF src2)));
10364
10365 format %{ "FADD $dst,$src1,$src2 cisc" %}
10366 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10367 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10368 set_instruction_start,
10369 OpcP, RMopc_Mem(secondary,src1),
10370 Pop_Mem_FPR(dst) );
10371 ins_pipe( fpu_mem_mem_mem );
10372 %}
10373
10374 // Spill to obtain 24-bit precision
10375 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10376 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10377 match(Set dst (AddF src1 src2));
10378
10379 format %{ "FADD $dst,$src1,$src2" %}
10380 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10381 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10382 set_instruction_start,
10383 OpcP, RMopc_Mem(secondary,src1),
10384 Pop_Mem_FPR(dst) );
10385 ins_pipe( fpu_mem_mem_mem );
10386 %}
10387
10388
10389 // Spill to obtain 24-bit precision
10390 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10391 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10392 match(Set dst (AddF src con));
10393 format %{ "FLD $src\n\t"
10394 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10395 "FSTP_S $dst" %}
10396 ins_encode %{
10397 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10398 __ fadd_s($constantaddress($con));
10399 __ fstp_s(Address(rsp, $dst$$disp));
10400 %}
10401 ins_pipe(fpu_mem_reg_con);
10402 %}
10403 //
10404 // This instruction does not round to 24-bits
10405 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10406 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10407 match(Set dst (AddF src con));
10408 format %{ "FLD $src\n\t"
10409 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10410 "FSTP $dst" %}
10411 ins_encode %{
10412 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10413 __ fadd_s($constantaddress($con));
10414 __ fstp_d($dst$$reg);
10415 %}
10416 ins_pipe(fpu_reg_reg_con);
10417 %}
10418
10419 // Spill to obtain 24-bit precision
10420 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10421 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10422 match(Set dst (MulF src1 src2));
10423
10424 format %{ "FLD $src1\n\t"
10425 "FMUL $src2\n\t"
10426 "FSTP_S $dst" %}
10427 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10428 ins_encode( Push_Reg_FPR(src1),
10429 OpcReg_FPR(src2),
10430 Pop_Mem_FPR(dst) );
10431 ins_pipe( fpu_mem_reg_reg );
10432 %}
10433 //
10434 // This instruction does not round to 24-bits
10435 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10436 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10437 match(Set dst (MulF src1 src2));
10438
10439 format %{ "FLD $src1\n\t"
10440 "FMUL $src2\n\t"
10441 "FSTP_S $dst" %}
10442 opcode(0xD8, 0x1); /* D8 C8+i */
10443 ins_encode( Push_Reg_FPR(src2),
10444 OpcReg_FPR(src1),
10445 Pop_Reg_FPR(dst) );
10446 ins_pipe( fpu_reg_reg_reg );
10447 %}
10448
10449
10450 // Spill to obtain 24-bit precision
10451 // Cisc-alternate to reg-reg multiply
10452 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10453 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10454 match(Set dst (MulF src1 (LoadF src2)));
10455
10456 format %{ "FLD_S $src2\n\t"
10457 "FMUL $src1\n\t"
10458 "FSTP_S $dst" %}
10459 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10460 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10461 OpcReg_FPR(src1),
10462 Pop_Mem_FPR(dst) );
10463 ins_pipe( fpu_mem_reg_mem );
10464 %}
10465 //
10466 // This instruction does not round to 24-bits
10467 // Cisc-alternate to reg-reg multiply
10468 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10469 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10470 match(Set dst (MulF src1 (LoadF src2)));
10471
10472 format %{ "FMUL $dst,$src1,$src2" %}
10473 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10474 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10475 OpcReg_FPR(src1),
10476 Pop_Reg_FPR(dst) );
10477 ins_pipe( fpu_reg_reg_mem );
10478 %}
10479
10480 // Spill to obtain 24-bit precision
10481 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10482 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10483 match(Set dst (MulF src1 src2));
10484
10485 format %{ "FMUL $dst,$src1,$src2" %}
10486 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10487 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10488 set_instruction_start,
10489 OpcP, RMopc_Mem(secondary,src1),
10490 Pop_Mem_FPR(dst) );
10491 ins_pipe( fpu_mem_mem_mem );
10492 %}
10493
10494 // Spill to obtain 24-bit precision
10495 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10496 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10497 match(Set dst (MulF src con));
10498
10499 format %{ "FLD $src\n\t"
10500 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10501 "FSTP_S $dst" %}
10502 ins_encode %{
10503 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10504 __ fmul_s($constantaddress($con));
10505 __ fstp_s(Address(rsp, $dst$$disp));
10506 %}
10507 ins_pipe(fpu_mem_reg_con);
10508 %}
10509 //
10510 // This instruction does not round to 24-bits
10511 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10512 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10513 match(Set dst (MulF src con));
10514
10515 format %{ "FLD $src\n\t"
10516 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10517 "FSTP $dst" %}
10518 ins_encode %{
10519 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10520 __ fmul_s($constantaddress($con));
10521 __ fstp_d($dst$$reg);
10522 %}
10523 ins_pipe(fpu_reg_reg_con);
10524 %}
10525
10526
10527 //
10528 // MACRO1 -- subsume unshared load into mulFPR
10529 // This instruction does not round to 24-bits
10530 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10531 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10532 match(Set dst (MulF (LoadF mem1) src));
10533
10534 format %{ "FLD $mem1 ===MACRO1===\n\t"
10535 "FMUL ST,$src\n\t"
10536 "FSTP $dst" %}
10537 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10538 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10539 OpcReg_FPR(src),
10540 Pop_Reg_FPR(dst) );
10541 ins_pipe( fpu_reg_reg_mem );
10542 %}
10543 //
10544 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10545 // This instruction does not round to 24-bits
10546 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10547 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10548 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10549 ins_cost(95);
10550
10551 format %{ "FLD $mem1 ===MACRO2===\n\t"
10552 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10553 "FADD ST,$src2\n\t"
10554 "FSTP $dst" %}
10555 opcode(0xD9); /* LoadF D9 /0 */
10556 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10557 FMul_ST_reg(src1),
10558 FAdd_ST_reg(src2),
10559 Pop_Reg_FPR(dst) );
10560 ins_pipe( fpu_reg_mem_reg_reg );
10561 %}
10562
10563 // MACRO3 -- addFPR a mulFPR
10564 // This instruction does not round to 24-bits. It is a '2-address'
10565 // instruction in that the result goes back to src2. This eliminates
10566 // a move from the macro; possibly the register allocator will have
10567 // to add it back (and maybe not).
10568 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10569 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10570 match(Set src2 (AddF (MulF src0 src1) src2));
10571
10572 format %{ "FLD $src0 ===MACRO3===\n\t"
10573 "FMUL ST,$src1\n\t"
10574 "FADDP $src2,ST" %}
10575 opcode(0xD9); /* LoadF D9 /0 */
10576 ins_encode( Push_Reg_FPR(src0),
10577 FMul_ST_reg(src1),
10578 FAddP_reg_ST(src2) );
10579 ins_pipe( fpu_reg_reg_reg );
10580 %}
10581
10582 // MACRO4 -- divFPR subFPR
10583 // This instruction does not round to 24-bits
10584 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10585 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10586 match(Set dst (DivF (SubF src2 src1) src3));
10587
10588 format %{ "FLD $src2 ===MACRO4===\n\t"
10589 "FSUB ST,$src1\n\t"
10590 "FDIV ST,$src3\n\t"
10591 "FSTP $dst" %}
10592 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10593 ins_encode( Push_Reg_FPR(src2),
10594 subFPR_divFPR_encode(src1,src3),
10595 Pop_Reg_FPR(dst) );
10596 ins_pipe( fpu_reg_reg_reg_reg );
10597 %}
10598
10599 // Spill to obtain 24-bit precision
10600 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10601 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10602 match(Set dst (DivF src1 src2));
10603
10604 format %{ "FDIV $dst,$src1,$src2" %}
10605 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10606 ins_encode( Push_Reg_FPR(src1),
10607 OpcReg_FPR(src2),
10608 Pop_Mem_FPR(dst) );
10609 ins_pipe( fpu_mem_reg_reg );
10610 %}
10611 //
10612 // This instruction does not round to 24-bits
10613 instruct divFPR_reg(regFPR dst, regFPR src) %{
10614 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10615 match(Set dst (DivF dst src));
10616
10617 format %{ "FDIV $dst,$src" %}
10618 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10619 ins_encode( Push_Reg_FPR(src),
10620 OpcP, RegOpc(dst) );
10621 ins_pipe( fpu_reg_reg );
10622 %}
10623
10624
10625 // Spill to obtain 24-bit precision
10626 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10627 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10628 match(Set dst (ModF src1 src2));
10629 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10630
10631 format %{ "FMOD $dst,$src1,$src2" %}
10632 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10633 emitModDPR(),
10634 Push_Result_Mod_DPR(src2),
10635 Pop_Mem_FPR(dst));
10636 ins_pipe( pipe_slow );
10637 %}
10638 //
10639 // This instruction does not round to 24-bits
10640 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10641 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10642 match(Set dst (ModF dst src));
10643 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10644
10645 format %{ "FMOD $dst,$src" %}
10646 ins_encode(Push_Reg_Mod_DPR(dst, src),
10647 emitModDPR(),
10648 Push_Result_Mod_DPR(src),
10649 Pop_Reg_FPR(dst));
10650 ins_pipe( pipe_slow );
10651 %}
10652
10653 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10654 predicate(UseSSE>=1);
10655 match(Set dst (ModF src0 src1));
10656 effect(KILL rax, KILL cr);
10657 format %{ "SUB ESP,4\t # FMOD\n"
10658 "\tMOVSS [ESP+0],$src1\n"
10659 "\tFLD_S [ESP+0]\n"
10660 "\tMOVSS [ESP+0],$src0\n"
10661 "\tFLD_S [ESP+0]\n"
10662 "loop:\tFPREM\n"
10663 "\tFWAIT\n"
10664 "\tFNSTSW AX\n"
10665 "\tSAHF\n"
10666 "\tJP loop\n"
10667 "\tFSTP_S [ESP+0]\n"
10668 "\tMOVSS $dst,[ESP+0]\n"
10669 "\tADD ESP,4\n"
10670 "\tFSTP ST0\t # Restore FPU Stack"
10671 %}
10672 ins_cost(250);
10673 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10674 ins_pipe( pipe_slow );
10675 %}
10676
10677
10678 //----------Arithmetic Conversion Instructions---------------------------------
10679 // The conversions operations are all Alpha sorted. Please keep it that way!
10680
10681 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10682 predicate(UseSSE==0);
10683 match(Set dst (RoundFloat src));
10684 ins_cost(125);
10685 format %{ "FST_S $dst,$src\t# F-round" %}
10686 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10687 ins_pipe( fpu_mem_reg );
10688 %}
10689
10690 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10691 predicate(UseSSE<=1);
10692 match(Set dst (RoundDouble src));
10693 ins_cost(125);
10694 format %{ "FST_D $dst,$src\t# D-round" %}
10695 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10696 ins_pipe( fpu_mem_reg );
10697 %}
10698
10699 // Force rounding to 24-bit precision and 6-bit exponent
10700 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10701 predicate(UseSSE==0);
10702 match(Set dst (ConvD2F src));
10703 format %{ "FST_S $dst,$src\t# F-round" %}
10704 expand %{
10705 roundFloat_mem_reg(dst,src);
10706 %}
10707 %}
10708
10709 // Force rounding to 24-bit precision and 6-bit exponent
10710 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10711 predicate(UseSSE==1);
10712 match(Set dst (ConvD2F src));
10713 effect( KILL cr );
10714 format %{ "SUB ESP,4\n\t"
10715 "FST_S [ESP],$src\t# F-round\n\t"
10716 "MOVSS $dst,[ESP]\n\t"
10717 "ADD ESP,4" %}
10718 ins_encode %{
10719 __ subptr(rsp, 4);
10720 if ($src$$reg != FPR1L_enc) {
10721 __ fld_s($src$$reg-1);
10722 __ fstp_s(Address(rsp, 0));
10723 } else {
10724 __ fst_s(Address(rsp, 0));
10725 }
10726 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10727 __ addptr(rsp, 4);
10728 %}
10729 ins_pipe( pipe_slow );
10730 %}
10731
10732 // Force rounding double precision to single precision
10733 instruct convD2F_reg(regF dst, regD src) %{
10734 predicate(UseSSE>=2);
10735 match(Set dst (ConvD2F src));
10736 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10737 ins_encode %{
10738 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10739 %}
10740 ins_pipe( pipe_slow );
10741 %}
10742
10743 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10744 predicate(UseSSE==0);
10745 match(Set dst (ConvF2D src));
10746 format %{ "FST_S $dst,$src\t# D-round" %}
10747 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10748 ins_pipe( fpu_reg_reg );
10749 %}
10750
10751 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10752 predicate(UseSSE==1);
10753 match(Set dst (ConvF2D src));
10754 format %{ "FST_D $dst,$src\t# D-round" %}
10755 expand %{
10756 roundDouble_mem_reg(dst,src);
10757 %}
10758 %}
10759
10760 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10761 predicate(UseSSE==1);
10762 match(Set dst (ConvF2D src));
10763 effect( KILL cr );
10764 format %{ "SUB ESP,4\n\t"
10765 "MOVSS [ESP] $src\n\t"
10766 "FLD_S [ESP]\n\t"
10767 "ADD ESP,4\n\t"
10768 "FSTP $dst\t# D-round" %}
10769 ins_encode %{
10770 __ subptr(rsp, 4);
10771 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10772 __ fld_s(Address(rsp, 0));
10773 __ addptr(rsp, 4);
10774 __ fstp_d($dst$$reg);
10775 %}
10776 ins_pipe( pipe_slow );
10777 %}
10778
10779 instruct convF2D_reg(regD dst, regF src) %{
10780 predicate(UseSSE>=2);
10781 match(Set dst (ConvF2D src));
10782 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10783 ins_encode %{
10784 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10785 %}
10786 ins_pipe( pipe_slow );
10787 %}
10788
10789 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10790 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10791 predicate(UseSSE<=1);
10792 match(Set dst (ConvD2I src));
10793 effect( KILL tmp, KILL cr );
10794 format %{ "FLD $src\t# Convert double to int \n\t"
10795 "FLDCW trunc mode\n\t"
10796 "SUB ESP,4\n\t"
10797 "FISTp [ESP + #0]\n\t"
10798 "FLDCW std/24-bit mode\n\t"
10799 "POP EAX\n\t"
10800 "CMP EAX,0x80000000\n\t"
10801 "JNE,s fast\n\t"
10802 "FLD_D $src\n\t"
10803 "CALL d2i_wrapper\n"
10804 "fast:" %}
10805 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10806 ins_pipe( pipe_slow );
10807 %}
10808
10809 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10810 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10811 predicate(UseSSE>=2);
10812 match(Set dst (ConvD2I src));
10813 effect( KILL tmp, KILL cr );
10814 format %{ "CVTTSD2SI $dst, $src\n\t"
10815 "CMP $dst,0x80000000\n\t"
10816 "JNE,s fast\n\t"
10817 "SUB ESP, 8\n\t"
10818 "MOVSD [ESP], $src\n\t"
10819 "FLD_D [ESP]\n\t"
10820 "ADD ESP, 8\n\t"
10821 "CALL d2i_wrapper\n"
10822 "fast:" %}
10823 ins_encode %{
10824 Label fast;
10825 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10826 __ cmpl($dst$$Register, 0x80000000);
10827 __ jccb(Assembler::notEqual, fast);
10828 __ subptr(rsp, 8);
10829 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10830 __ fld_d(Address(rsp, 0));
10831 __ addptr(rsp, 8);
10832 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10833 __ bind(fast);
10834 %}
10835 ins_pipe( pipe_slow );
10836 %}
10837
10838 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10839 predicate(UseSSE<=1);
10840 match(Set dst (ConvD2L src));
10841 effect( KILL cr );
10842 format %{ "FLD $src\t# Convert double to long\n\t"
10843 "FLDCW trunc mode\n\t"
10844 "SUB ESP,8\n\t"
10845 "FISTp [ESP + #0]\n\t"
10846 "FLDCW std/24-bit mode\n\t"
10847 "POP EAX\n\t"
10848 "POP EDX\n\t"
10849 "CMP EDX,0x80000000\n\t"
10850 "JNE,s fast\n\t"
10851 "TEST EAX,EAX\n\t"
10852 "JNE,s fast\n\t"
10853 "FLD $src\n\t"
10854 "CALL d2l_wrapper\n"
10855 "fast:" %}
10856 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10857 ins_pipe( pipe_slow );
10858 %}
10859
10860 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10861 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10862 predicate (UseSSE>=2);
10863 match(Set dst (ConvD2L src));
10864 effect( KILL cr );
10865 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10866 "MOVSD [ESP],$src\n\t"
10867 "FLD_D [ESP]\n\t"
10868 "FLDCW trunc mode\n\t"
10869 "FISTp [ESP + #0]\n\t"
10870 "FLDCW std/24-bit mode\n\t"
10871 "POP EAX\n\t"
10872 "POP EDX\n\t"
10873 "CMP EDX,0x80000000\n\t"
10874 "JNE,s fast\n\t"
10875 "TEST EAX,EAX\n\t"
10876 "JNE,s fast\n\t"
10877 "SUB ESP,8\n\t"
10878 "MOVSD [ESP],$src\n\t"
10879 "FLD_D [ESP]\n\t"
10880 "ADD ESP,8\n\t"
10881 "CALL d2l_wrapper\n"
10882 "fast:" %}
10883 ins_encode %{
10884 Label fast;
10885 __ subptr(rsp, 8);
10886 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10887 __ fld_d(Address(rsp, 0));
10888 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10889 __ fistp_d(Address(rsp, 0));
10890 // Restore the rounding mode, mask the exception
10891 if (Compile::current()->in_24_bit_fp_mode()) {
10892 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10893 } else {
10894 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10895 }
10896 // Load the converted long, adjust CPU stack
10897 __ pop(rax);
10898 __ pop(rdx);
10899 __ cmpl(rdx, 0x80000000);
10900 __ jccb(Assembler::notEqual, fast);
10901 __ testl(rax, rax);
10902 __ jccb(Assembler::notEqual, fast);
10903 __ subptr(rsp, 8);
10904 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10905 __ fld_d(Address(rsp, 0));
10906 __ addptr(rsp, 8);
10907 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10908 __ bind(fast);
10909 %}
10910 ins_pipe( pipe_slow );
10911 %}
10912
10913 // Convert a double to an int. Java semantics require we do complex
10914 // manglations in the corner cases. So we set the rounding mode to
10915 // 'zero', store the darned double down as an int, and reset the
10916 // rounding mode to 'nearest'. The hardware stores a flag value down
10917 // if we would overflow or converted a NAN; we check for this and
10918 // and go the slow path if needed.
10919 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10920 predicate(UseSSE==0);
10921 match(Set dst (ConvF2I src));
10922 effect( KILL tmp, KILL cr );
10923 format %{ "FLD $src\t# Convert float to int \n\t"
10924 "FLDCW trunc mode\n\t"
10925 "SUB ESP,4\n\t"
10926 "FISTp [ESP + #0]\n\t"
10927 "FLDCW std/24-bit mode\n\t"
10928 "POP EAX\n\t"
10929 "CMP EAX,0x80000000\n\t"
10930 "JNE,s fast\n\t"
10931 "FLD $src\n\t"
10932 "CALL d2i_wrapper\n"
10933 "fast:" %}
10934 // DPR2I_encoding works for FPR2I
10935 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10936 ins_pipe( pipe_slow );
10937 %}
10938
10939 // Convert a float in xmm to an int reg.
10940 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10941 predicate(UseSSE>=1);
10942 match(Set dst (ConvF2I src));
10943 effect( KILL tmp, KILL cr );
10944 format %{ "CVTTSS2SI $dst, $src\n\t"
10945 "CMP $dst,0x80000000\n\t"
10946 "JNE,s fast\n\t"
10947 "SUB ESP, 4\n\t"
10948 "MOVSS [ESP], $src\n\t"
10949 "FLD [ESP]\n\t"
10950 "ADD ESP, 4\n\t"
10951 "CALL d2i_wrapper\n"
10952 "fast:" %}
10953 ins_encode %{
10954 Label fast;
10955 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10956 __ cmpl($dst$$Register, 0x80000000);
10957 __ jccb(Assembler::notEqual, fast);
10958 __ subptr(rsp, 4);
10959 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10960 __ fld_s(Address(rsp, 0));
10961 __ addptr(rsp, 4);
10962 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10963 __ bind(fast);
10964 %}
10965 ins_pipe( pipe_slow );
10966 %}
10967
10968 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
10969 predicate(UseSSE==0);
10970 match(Set dst (ConvF2L src));
10971 effect( KILL cr );
10972 format %{ "FLD $src\t# Convert float to long\n\t"
10973 "FLDCW trunc mode\n\t"
10974 "SUB ESP,8\n\t"
10975 "FISTp [ESP + #0]\n\t"
10976 "FLDCW std/24-bit mode\n\t"
10977 "POP EAX\n\t"
10978 "POP EDX\n\t"
10979 "CMP EDX,0x80000000\n\t"
10980 "JNE,s fast\n\t"
10981 "TEST EAX,EAX\n\t"
10982 "JNE,s fast\n\t"
10983 "FLD $src\n\t"
10984 "CALL d2l_wrapper\n"
10985 "fast:" %}
10986 // DPR2L_encoding works for FPR2L
10987 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
10988 ins_pipe( pipe_slow );
10989 %}
10990
10991 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10992 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
10993 predicate (UseSSE>=1);
10994 match(Set dst (ConvF2L src));
10995 effect( KILL cr );
10996 format %{ "SUB ESP,8\t# Convert float to long\n\t"
10997 "MOVSS [ESP],$src\n\t"
10998 "FLD_S [ESP]\n\t"
10999 "FLDCW trunc mode\n\t"
11000 "FISTp [ESP + #0]\n\t"
11001 "FLDCW std/24-bit mode\n\t"
11002 "POP EAX\n\t"
11003 "POP EDX\n\t"
11004 "CMP EDX,0x80000000\n\t"
11005 "JNE,s fast\n\t"
11006 "TEST EAX,EAX\n\t"
11007 "JNE,s fast\n\t"
11008 "SUB ESP,4\t# Convert float to long\n\t"
11009 "MOVSS [ESP],$src\n\t"
11010 "FLD_S [ESP]\n\t"
11011 "ADD ESP,4\n\t"
11012 "CALL d2l_wrapper\n"
11013 "fast:" %}
11014 ins_encode %{
11015 Label fast;
11016 __ subptr(rsp, 8);
11017 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11018 __ fld_s(Address(rsp, 0));
11019 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11020 __ fistp_d(Address(rsp, 0));
11021 // Restore the rounding mode, mask the exception
11022 if (Compile::current()->in_24_bit_fp_mode()) {
11023 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11024 } else {
11025 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11026 }
11027 // Load the converted long, adjust CPU stack
11028 __ pop(rax);
11029 __ pop(rdx);
11030 __ cmpl(rdx, 0x80000000);
11031 __ jccb(Assembler::notEqual, fast);
11032 __ testl(rax, rax);
11033 __ jccb(Assembler::notEqual, fast);
11034 __ subptr(rsp, 4);
11035 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11036 __ fld_s(Address(rsp, 0));
11037 __ addptr(rsp, 4);
11038 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11039 __ bind(fast);
11040 %}
11041 ins_pipe( pipe_slow );
11042 %}
11043
11044 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11045 predicate( UseSSE<=1 );
11046 match(Set dst (ConvI2D src));
11047 format %{ "FILD $src\n\t"
11048 "FSTP $dst" %}
11049 opcode(0xDB, 0x0); /* DB /0 */
11050 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11051 ins_pipe( fpu_reg_mem );
11052 %}
11053
11054 instruct convI2D_reg(regD dst, rRegI src) %{
11055 predicate( UseSSE>=2 && !UseXmmI2D );
11056 match(Set dst (ConvI2D src));
11057 format %{ "CVTSI2SD $dst,$src" %}
11058 ins_encode %{
11059 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11060 %}
11061 ins_pipe( pipe_slow );
11062 %}
11063
11064 instruct convI2D_mem(regD dst, memory mem) %{
11065 predicate( UseSSE>=2 );
11066 match(Set dst (ConvI2D (LoadI mem)));
11067 format %{ "CVTSI2SD $dst,$mem" %}
11068 ins_encode %{
11069 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11070 %}
11071 ins_pipe( pipe_slow );
11072 %}
11073
11074 instruct convXI2D_reg(regD dst, rRegI src)
11075 %{
11076 predicate( UseSSE>=2 && UseXmmI2D );
11077 match(Set dst (ConvI2D src));
11078
11079 format %{ "MOVD $dst,$src\n\t"
11080 "CVTDQ2PD $dst,$dst\t# i2d" %}
11081 ins_encode %{
11082 __ movdl($dst$$XMMRegister, $src$$Register);
11083 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11084 %}
11085 ins_pipe(pipe_slow); // XXX
11086 %}
11087
11088 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11089 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11090 match(Set dst (ConvI2D (LoadI mem)));
11091 format %{ "FILD $mem\n\t"
11092 "FSTP $dst" %}
11093 opcode(0xDB); /* DB /0 */
11094 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11095 Pop_Reg_DPR(dst));
11096 ins_pipe( fpu_reg_mem );
11097 %}
11098
11099 // Convert a byte to a float; no rounding step needed.
11100 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11101 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11102 match(Set dst (ConvI2F src));
11103 format %{ "FILD $src\n\t"
11104 "FSTP $dst" %}
11105
11106 opcode(0xDB, 0x0); /* DB /0 */
11107 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11108 ins_pipe( fpu_reg_mem );
11109 %}
11110
11111 // In 24-bit mode, force exponent rounding by storing back out
11112 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11113 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11114 match(Set dst (ConvI2F src));
11115 ins_cost(200);
11116 format %{ "FILD $src\n\t"
11117 "FSTP_S $dst" %}
11118 opcode(0xDB, 0x0); /* DB /0 */
11119 ins_encode( Push_Mem_I(src),
11120 Pop_Mem_FPR(dst));
11121 ins_pipe( fpu_mem_mem );
11122 %}
11123
11124 // In 24-bit mode, force exponent rounding by storing back out
11125 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11126 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11127 match(Set dst (ConvI2F (LoadI mem)));
11128 ins_cost(200);
11129 format %{ "FILD $mem\n\t"
11130 "FSTP_S $dst" %}
11131 opcode(0xDB); /* DB /0 */
11132 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11133 Pop_Mem_FPR(dst));
11134 ins_pipe( fpu_mem_mem );
11135 %}
11136
11137 // This instruction does not round to 24-bits
11138 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11139 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11140 match(Set dst (ConvI2F src));
11141 format %{ "FILD $src\n\t"
11142 "FSTP $dst" %}
11143 opcode(0xDB, 0x0); /* DB /0 */
11144 ins_encode( Push_Mem_I(src),
11145 Pop_Reg_FPR(dst));
11146 ins_pipe( fpu_reg_mem );
11147 %}
11148
11149 // This instruction does not round to 24-bits
11150 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11151 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11152 match(Set dst (ConvI2F (LoadI mem)));
11153 format %{ "FILD $mem\n\t"
11154 "FSTP $dst" %}
11155 opcode(0xDB); /* DB /0 */
11156 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11157 Pop_Reg_FPR(dst));
11158 ins_pipe( fpu_reg_mem );
11159 %}
11160
11161 // Convert an int to a float in xmm; no rounding step needed.
11162 instruct convI2F_reg(regF dst, rRegI src) %{
11163 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11164 match(Set dst (ConvI2F src));
11165 format %{ "CVTSI2SS $dst, $src" %}
11166 ins_encode %{
11167 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11168 %}
11169 ins_pipe( pipe_slow );
11170 %}
11171
11172 instruct convXI2F_reg(regF dst, rRegI src)
11173 %{
11174 predicate( UseSSE>=2 && UseXmmI2F );
11175 match(Set dst (ConvI2F src));
11176
11177 format %{ "MOVD $dst,$src\n\t"
11178 "CVTDQ2PS $dst,$dst\t# i2f" %}
11179 ins_encode %{
11180 __ movdl($dst$$XMMRegister, $src$$Register);
11181 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11182 %}
11183 ins_pipe(pipe_slow); // XXX
11184 %}
11185
11186 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11187 match(Set dst (ConvI2L src));
11188 effect(KILL cr);
11189 ins_cost(375);
11190 format %{ "MOV $dst.lo,$src\n\t"
11191 "MOV $dst.hi,$src\n\t"
11192 "SAR $dst.hi,31" %}
11193 ins_encode(convert_int_long(dst,src));
11194 ins_pipe( ialu_reg_reg_long );
11195 %}
11196
11197 // Zero-extend convert int to long
11198 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11199 match(Set dst (AndL (ConvI2L src) mask) );
11200 effect( KILL flags );
11201 ins_cost(250);
11202 format %{ "MOV $dst.lo,$src\n\t"
11203 "XOR $dst.hi,$dst.hi" %}
11204 opcode(0x33); // XOR
11205 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11206 ins_pipe( ialu_reg_reg_long );
11207 %}
11208
11209 // Zero-extend long
11210 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11211 match(Set dst (AndL src mask) );
11212 effect( KILL flags );
11213 ins_cost(250);
11214 format %{ "MOV $dst.lo,$src.lo\n\t"
11215 "XOR $dst.hi,$dst.hi\n\t" %}
11216 opcode(0x33); // XOR
11217 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11218 ins_pipe( ialu_reg_reg_long );
11219 %}
11220
11221 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11222 predicate (UseSSE<=1);
11223 match(Set dst (ConvL2D src));
11224 effect( KILL cr );
11225 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11226 "PUSH $src.lo\n\t"
11227 "FILD ST,[ESP + #0]\n\t"
11228 "ADD ESP,8\n\t"
11229 "FSTP_D $dst\t# D-round" %}
11230 opcode(0xDF, 0x5); /* DF /5 */
11231 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11232 ins_pipe( pipe_slow );
11233 %}
11234
11235 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11236 predicate (UseSSE>=2);
11237 match(Set dst (ConvL2D src));
11238 effect( KILL cr );
11239 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11240 "PUSH $src.lo\n\t"
11241 "FILD_D [ESP]\n\t"
11242 "FSTP_D [ESP]\n\t"
11243 "MOVSD $dst,[ESP]\n\t"
11244 "ADD ESP,8" %}
11245 opcode(0xDF, 0x5); /* DF /5 */
11246 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11247 ins_pipe( pipe_slow );
11248 %}
11249
11250 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11251 predicate (UseSSE>=1);
11252 match(Set dst (ConvL2F src));
11253 effect( KILL cr );
11254 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11255 "PUSH $src.lo\n\t"
11256 "FILD_D [ESP]\n\t"
11257 "FSTP_S [ESP]\n\t"
11258 "MOVSS $dst,[ESP]\n\t"
11259 "ADD ESP,8" %}
11260 opcode(0xDF, 0x5); /* DF /5 */
11261 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11262 ins_pipe( pipe_slow );
11263 %}
11264
11265 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11266 match(Set dst (ConvL2F src));
11267 effect( KILL cr );
11268 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11269 "PUSH $src.lo\n\t"
11270 "FILD ST,[ESP + #0]\n\t"
11271 "ADD ESP,8\n\t"
11272 "FSTP_S $dst\t# F-round" %}
11273 opcode(0xDF, 0x5); /* DF /5 */
11274 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11275 ins_pipe( pipe_slow );
11276 %}
11277
11278 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11279 match(Set dst (ConvL2I src));
11280 effect( DEF dst, USE src );
11281 format %{ "MOV $dst,$src.lo" %}
11282 ins_encode(enc_CopyL_Lo(dst,src));
11283 ins_pipe( ialu_reg_reg );
11284 %}
11285
11286
11287 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11288 match(Set dst (MoveF2I src));
11289 effect( DEF dst, USE src );
11290 ins_cost(100);
11291 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11292 ins_encode %{
11293 __ movl($dst$$Register, Address(rsp, $src$$disp));
11294 %}
11295 ins_pipe( ialu_reg_mem );
11296 %}
11297
11298 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11299 predicate(UseSSE==0);
11300 match(Set dst (MoveF2I src));
11301 effect( DEF dst, USE src );
11302
11303 ins_cost(125);
11304 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11305 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11306 ins_pipe( fpu_mem_reg );
11307 %}
11308
11309 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11310 predicate(UseSSE>=1);
11311 match(Set dst (MoveF2I src));
11312 effect( DEF dst, USE src );
11313
11314 ins_cost(95);
11315 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11316 ins_encode %{
11317 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11318 %}
11319 ins_pipe( pipe_slow );
11320 %}
11321
11322 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11323 predicate(UseSSE>=2);
11324 match(Set dst (MoveF2I src));
11325 effect( DEF dst, USE src );
11326 ins_cost(85);
11327 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11328 ins_encode %{
11329 __ movdl($dst$$Register, $src$$XMMRegister);
11330 %}
11331 ins_pipe( pipe_slow );
11332 %}
11333
11334 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11335 match(Set dst (MoveI2F src));
11336 effect( DEF dst, USE src );
11337
11338 ins_cost(100);
11339 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11340 ins_encode %{
11341 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11342 %}
11343 ins_pipe( ialu_mem_reg );
11344 %}
11345
11346
11347 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11348 predicate(UseSSE==0);
11349 match(Set dst (MoveI2F src));
11350 effect(DEF dst, USE src);
11351
11352 ins_cost(125);
11353 format %{ "FLD_S $src\n\t"
11354 "FSTP $dst\t# MoveI2F_stack_reg" %}
11355 opcode(0xD9); /* D9 /0, FLD m32real */
11356 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11357 Pop_Reg_FPR(dst) );
11358 ins_pipe( fpu_reg_mem );
11359 %}
11360
11361 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11362 predicate(UseSSE>=1);
11363 match(Set dst (MoveI2F src));
11364 effect( DEF dst, USE src );
11365
11366 ins_cost(95);
11367 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11368 ins_encode %{
11369 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11370 %}
11371 ins_pipe( pipe_slow );
11372 %}
11373
11374 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11375 predicate(UseSSE>=2);
11376 match(Set dst (MoveI2F src));
11377 effect( DEF dst, USE src );
11378
11379 ins_cost(85);
11380 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11381 ins_encode %{
11382 __ movdl($dst$$XMMRegister, $src$$Register);
11383 %}
11384 ins_pipe( pipe_slow );
11385 %}
11386
11387 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11388 match(Set dst (MoveD2L src));
11389 effect(DEF dst, USE src);
11390
11391 ins_cost(250);
11392 format %{ "MOV $dst.lo,$src\n\t"
11393 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11394 opcode(0x8B, 0x8B);
11395 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11396 ins_pipe( ialu_mem_long_reg );
11397 %}
11398
11399 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11400 predicate(UseSSE<=1);
11401 match(Set dst (MoveD2L src));
11402 effect(DEF dst, USE src);
11403
11404 ins_cost(125);
11405 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11406 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11407 ins_pipe( fpu_mem_reg );
11408 %}
11409
11410 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11411 predicate(UseSSE>=2);
11412 match(Set dst (MoveD2L src));
11413 effect(DEF dst, USE src);
11414 ins_cost(95);
11415 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11416 ins_encode %{
11417 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11418 %}
11419 ins_pipe( pipe_slow );
11420 %}
11421
11422 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11423 predicate(UseSSE>=2);
11424 match(Set dst (MoveD2L src));
11425 effect(DEF dst, USE src, TEMP tmp);
11426 ins_cost(85);
11427 format %{ "MOVD $dst.lo,$src\n\t"
11428 "PSHUFLW $tmp,$src,0x4E\n\t"
11429 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11430 ins_encode %{
11431 __ movdl($dst$$Register, $src$$XMMRegister);
11432 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11433 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11434 %}
11435 ins_pipe( pipe_slow );
11436 %}
11437
11438 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11439 match(Set dst (MoveL2D src));
11440 effect(DEF dst, USE src);
11441
11442 ins_cost(200);
11443 format %{ "MOV $dst,$src.lo\n\t"
11444 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11445 opcode(0x89, 0x89);
11446 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11447 ins_pipe( ialu_mem_long_reg );
11448 %}
11449
11450
11451 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11452 predicate(UseSSE<=1);
11453 match(Set dst (MoveL2D src));
11454 effect(DEF dst, USE src);
11455 ins_cost(125);
11456
11457 format %{ "FLD_D $src\n\t"
11458 "FSTP $dst\t# MoveL2D_stack_reg" %}
11459 opcode(0xDD); /* DD /0, FLD m64real */
11460 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11461 Pop_Reg_DPR(dst) );
11462 ins_pipe( fpu_reg_mem );
11463 %}
11464
11465
11466 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11467 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11468 match(Set dst (MoveL2D src));
11469 effect(DEF dst, USE src);
11470
11471 ins_cost(95);
11472 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11473 ins_encode %{
11474 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11475 %}
11476 ins_pipe( pipe_slow );
11477 %}
11478
11479 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11480 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11481 match(Set dst (MoveL2D src));
11482 effect(DEF dst, USE src);
11483
11484 ins_cost(95);
11485 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11486 ins_encode %{
11487 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11488 %}
11489 ins_pipe( pipe_slow );
11490 %}
11491
11492 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11493 predicate(UseSSE>=2);
11494 match(Set dst (MoveL2D src));
11495 effect(TEMP dst, USE src, TEMP tmp);
11496 ins_cost(85);
11497 format %{ "MOVD $dst,$src.lo\n\t"
11498 "MOVD $tmp,$src.hi\n\t"
11499 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11500 ins_encode %{
11501 __ movdl($dst$$XMMRegister, $src$$Register);
11502 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11503 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11504 %}
11505 ins_pipe( pipe_slow );
11506 %}
11507
11508
11509 // =======================================================================
11510 // fast clearing of an array
11511 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11512 predicate(!UseFastStosb);
11513 match(Set dummy (ClearArray cnt base));
11514 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11515 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11516 "SHL ECX,1\t# Convert doublewords to words\n\t"
11517 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11518 ins_encode %{
11519 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11520 %}
11521 ins_pipe( pipe_slow );
11522 %}
11523
11524 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11525 predicate(UseFastStosb);
11526 match(Set dummy (ClearArray cnt base));
11527 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11528 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11529 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11530 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11531 ins_encode %{
11532 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11533 %}
11534 ins_pipe( pipe_slow );
11535 %}
11536
11537 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11538 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11539 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11540 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11541
11542 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11543 ins_encode %{
11544 __ string_compare($str1$$Register, $str2$$Register,
11545 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11546 $tmp1$$XMMRegister);
11547 %}
11548 ins_pipe( pipe_slow );
11549 %}
11550
11551 // fast string equals
11552 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11553 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11554 match(Set result (StrEquals (Binary str1 str2) cnt));
11555 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11556
11557 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11558 ins_encode %{
11559 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11560 $cnt$$Register, $result$$Register, $tmp3$$Register,
11561 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11562 %}
11563 ins_pipe( pipe_slow );
11564 %}
11565
11566 // fast search of substring with known size.
11567 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11568 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11569 predicate(UseSSE42Intrinsics);
11570 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11571 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11572
11573 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11574 ins_encode %{
11575 int icnt2 = (int)$int_cnt2$$constant;
11576 if (icnt2 >= 8) {
11577 // IndexOf for constant substrings with size >= 8 elements
11578 // which don't need to be loaded through stack.
11579 __ string_indexofC8($str1$$Register, $str2$$Register,
11580 $cnt1$$Register, $cnt2$$Register,
11581 icnt2, $result$$Register,
11582 $vec$$XMMRegister, $tmp$$Register);
11583 } else {
11584 // Small strings are loaded through stack if they cross page boundary.
11585 __ string_indexof($str1$$Register, $str2$$Register,
11586 $cnt1$$Register, $cnt2$$Register,
11587 icnt2, $result$$Register,
11588 $vec$$XMMRegister, $tmp$$Register);
11589 }
11590 %}
11591 ins_pipe( pipe_slow );
11592 %}
11593
11594 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11595 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11596 predicate(UseSSE42Intrinsics);
11597 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11598 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11599
11600 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11601 ins_encode %{
11602 __ string_indexof($str1$$Register, $str2$$Register,
11603 $cnt1$$Register, $cnt2$$Register,
11604 (-1), $result$$Register,
11605 $vec$$XMMRegister, $tmp$$Register);
11606 %}
11607 ins_pipe( pipe_slow );
11608 %}
11609
11610 // fast array equals
11611 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11612 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11613 %{
11614 match(Set result (AryEq ary1 ary2));
11615 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11616 //ins_cost(300);
11617
11618 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11619 ins_encode %{
11620 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11621 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11622 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11623 %}
11624 ins_pipe( pipe_slow );
11625 %}
11626
11627 // encode char[] to byte[] in ISO_8859_1
11628 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11629 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11630 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11631 match(Set result (EncodeISOArray src (Binary dst len)));
11632 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11633
11634 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11635 ins_encode %{
11636 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11637 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11638 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11639 %}
11640 ins_pipe( pipe_slow );
11641 %}
11642
11643
11644 //----------Control Flow Instructions------------------------------------------
11645 // Signed compare Instructions
11646 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11647 match(Set cr (CmpI op1 op2));
11648 effect( DEF cr, USE op1, USE op2 );
11649 format %{ "CMP $op1,$op2" %}
11650 opcode(0x3B); /* Opcode 3B /r */
11651 ins_encode( OpcP, RegReg( op1, op2) );
11652 ins_pipe( ialu_cr_reg_reg );
11653 %}
11654
11655 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11656 match(Set cr (CmpI op1 op2));
11657 effect( DEF cr, USE op1 );
11658 format %{ "CMP $op1,$op2" %}
11659 opcode(0x81,0x07); /* Opcode 81 /7 */
11660 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11661 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11662 ins_pipe( ialu_cr_reg_imm );
11663 %}
11664
11665 // Cisc-spilled version of cmpI_eReg
11666 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11667 match(Set cr (CmpI op1 (LoadI op2)));
11668
11669 format %{ "CMP $op1,$op2" %}
11670 ins_cost(500);
11671 opcode(0x3B); /* Opcode 3B /r */
11672 ins_encode( OpcP, RegMem( op1, op2) );
11673 ins_pipe( ialu_cr_reg_mem );
11674 %}
11675
11676 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11677 match(Set cr (CmpI src zero));
11678 effect( DEF cr, USE src );
11679
11680 format %{ "TEST $src,$src" %}
11681 opcode(0x85);
11682 ins_encode( OpcP, RegReg( src, src ) );
11683 ins_pipe( ialu_cr_reg_imm );
11684 %}
11685
11686 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11687 match(Set cr (CmpI (AndI src con) zero));
11688
11689 format %{ "TEST $src,$con" %}
11690 opcode(0xF7,0x00);
11691 ins_encode( OpcP, RegOpc(src), Con32(con) );
11692 ins_pipe( ialu_cr_reg_imm );
11693 %}
11694
11695 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11696 match(Set cr (CmpI (AndI src mem) zero));
11697
11698 format %{ "TEST $src,$mem" %}
11699 opcode(0x85);
11700 ins_encode( OpcP, RegMem( src, mem ) );
11701 ins_pipe( ialu_cr_reg_mem );
11702 %}
11703
11704 // Unsigned compare Instructions; really, same as signed except they
11705 // produce an eFlagsRegU instead of eFlagsReg.
11706 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11707 match(Set cr (CmpU op1 op2));
11708
11709 format %{ "CMPu $op1,$op2" %}
11710 opcode(0x3B); /* Opcode 3B /r */
11711 ins_encode( OpcP, RegReg( op1, op2) );
11712 ins_pipe( ialu_cr_reg_reg );
11713 %}
11714
11715 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11716 match(Set cr (CmpU op1 op2));
11717
11718 format %{ "CMPu $op1,$op2" %}
11719 opcode(0x81,0x07); /* Opcode 81 /7 */
11720 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11721 ins_pipe( ialu_cr_reg_imm );
11722 %}
11723
11724 // // Cisc-spilled version of cmpU_eReg
11725 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11726 match(Set cr (CmpU op1 (LoadI op2)));
11727
11728 format %{ "CMPu $op1,$op2" %}
11729 ins_cost(500);
11730 opcode(0x3B); /* Opcode 3B /r */
11731 ins_encode( OpcP, RegMem( op1, op2) );
11732 ins_pipe( ialu_cr_reg_mem );
11733 %}
11734
11735 // // Cisc-spilled version of cmpU_eReg
11736 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11737 // match(Set cr (CmpU (LoadI op1) op2));
11738 //
11739 // format %{ "CMPu $op1,$op2" %}
11740 // ins_cost(500);
11741 // opcode(0x39); /* Opcode 39 /r */
11742 // ins_encode( OpcP, RegMem( op1, op2) );
11743 //%}
11744
11745 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11746 match(Set cr (CmpU src zero));
11747
11748 format %{ "TESTu $src,$src" %}
11749 opcode(0x85);
11750 ins_encode( OpcP, RegReg( src, src ) );
11751 ins_pipe( ialu_cr_reg_imm );
11752 %}
11753
11754 // Unsigned pointer compare Instructions
11755 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11756 match(Set cr (CmpP op1 op2));
11757
11758 format %{ "CMPu $op1,$op2" %}
11759 opcode(0x3B); /* Opcode 3B /r */
11760 ins_encode( OpcP, RegReg( op1, op2) );
11761 ins_pipe( ialu_cr_reg_reg );
11762 %}
11763
11764 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11765 match(Set cr (CmpP op1 op2));
11766
11767 format %{ "CMPu $op1,$op2" %}
11768 opcode(0x81,0x07); /* Opcode 81 /7 */
11769 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11770 ins_pipe( ialu_cr_reg_imm );
11771 %}
11772
11773 // // Cisc-spilled version of cmpP_eReg
11774 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11775 match(Set cr (CmpP op1 (LoadP op2)));
11776
11777 format %{ "CMPu $op1,$op2" %}
11778 ins_cost(500);
11779 opcode(0x3B); /* Opcode 3B /r */
11780 ins_encode( OpcP, RegMem( op1, op2) );
11781 ins_pipe( ialu_cr_reg_mem );
11782 %}
11783
11784 // // Cisc-spilled version of cmpP_eReg
11785 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11786 // match(Set cr (CmpP (LoadP op1) op2));
11787 //
11788 // format %{ "CMPu $op1,$op2" %}
11789 // ins_cost(500);
11790 // opcode(0x39); /* Opcode 39 /r */
11791 // ins_encode( OpcP, RegMem( op1, op2) );
11792 //%}
11793
11794 // Compare raw pointer (used in out-of-heap check).
11795 // Only works because non-oop pointers must be raw pointers
11796 // and raw pointers have no anti-dependencies.
11797 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11798 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11799 match(Set cr (CmpP op1 (LoadP op2)));
11800
11801 format %{ "CMPu $op1,$op2" %}
11802 opcode(0x3B); /* Opcode 3B /r */
11803 ins_encode( OpcP, RegMem( op1, op2) );
11804 ins_pipe( ialu_cr_reg_mem );
11805 %}
11806
11807 //
11808 // This will generate a signed flags result. This should be ok
11809 // since any compare to a zero should be eq/neq.
11810 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11811 match(Set cr (CmpP src zero));
11812
11813 format %{ "TEST $src,$src" %}
11814 opcode(0x85);
11815 ins_encode( OpcP, RegReg( src, src ) );
11816 ins_pipe( ialu_cr_reg_imm );
11817 %}
11818
11819 // Cisc-spilled version of testP_reg
11820 // This will generate a signed flags result. This should be ok
11821 // since any compare to a zero should be eq/neq.
11822 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11823 match(Set cr (CmpP (LoadP op) zero));
11824
11825 format %{ "TEST $op,0xFFFFFFFF" %}
11826 ins_cost(500);
11827 opcode(0xF7); /* Opcode F7 /0 */
11828 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11829 ins_pipe( ialu_cr_reg_imm );
11830 %}
11831
11832 // Yanked all unsigned pointer compare operations.
11833 // Pointer compares are done with CmpP which is already unsigned.
11834
11835 //----------Max and Min--------------------------------------------------------
11836 // Min Instructions
11837 ////
11838 // *** Min and Max using the conditional move are slower than the
11839 // *** branch version on a Pentium III.
11840 // // Conditional move for min
11841 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11842 // effect( USE_DEF op2, USE op1, USE cr );
11843 // format %{ "CMOVlt $op2,$op1\t! min" %}
11844 // opcode(0x4C,0x0F);
11845 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11846 // ins_pipe( pipe_cmov_reg );
11847 //%}
11848 //
11849 //// Min Register with Register (P6 version)
11850 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11851 // predicate(VM_Version::supports_cmov() );
11852 // match(Set op2 (MinI op1 op2));
11853 // ins_cost(200);
11854 // expand %{
11855 // eFlagsReg cr;
11856 // compI_eReg(cr,op1,op2);
11857 // cmovI_reg_lt(op2,op1,cr);
11858 // %}
11859 //%}
11860
11861 // Min Register with Register (generic version)
11862 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11863 match(Set dst (MinI dst src));
11864 effect(KILL flags);
11865 ins_cost(300);
11866
11867 format %{ "MIN $dst,$src" %}
11868 opcode(0xCC);
11869 ins_encode( min_enc(dst,src) );
11870 ins_pipe( pipe_slow );
11871 %}
11872
11873 // Max Register with Register
11874 // *** Min and Max using the conditional move are slower than the
11875 // *** branch version on a Pentium III.
11876 // // Conditional move for max
11877 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11878 // effect( USE_DEF op2, USE op1, USE cr );
11879 // format %{ "CMOVgt $op2,$op1\t! max" %}
11880 // opcode(0x4F,0x0F);
11881 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11882 // ins_pipe( pipe_cmov_reg );
11883 //%}
11884 //
11885 // // Max Register with Register (P6 version)
11886 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11887 // predicate(VM_Version::supports_cmov() );
11888 // match(Set op2 (MaxI op1 op2));
11889 // ins_cost(200);
11890 // expand %{
11891 // eFlagsReg cr;
11892 // compI_eReg(cr,op1,op2);
11893 // cmovI_reg_gt(op2,op1,cr);
11894 // %}
11895 //%}
11896
11897 // Max Register with Register (generic version)
11898 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11899 match(Set dst (MaxI dst src));
11900 effect(KILL flags);
11901 ins_cost(300);
11902
11903 format %{ "MAX $dst,$src" %}
11904 opcode(0xCC);
11905 ins_encode( max_enc(dst,src) );
11906 ins_pipe( pipe_slow );
11907 %}
11908
11909 // ============================================================================
11910 // Counted Loop limit node which represents exact final iterator value.
11911 // Note: the resulting value should fit into integer range since
11912 // counted loops have limit check on overflow.
11913 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11914 match(Set limit (LoopLimit (Binary init limit) stride));
11915 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11916 ins_cost(300);
11917
11918 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11919 ins_encode %{
11920 int strd = (int)$stride$$constant;
11921 assert(strd != 1 && strd != -1, "sanity");
11922 int m1 = (strd > 0) ? 1 : -1;
11923 // Convert limit to long (EAX:EDX)
11924 __ cdql();
11925 // Convert init to long (init:tmp)
11926 __ movl($tmp$$Register, $init$$Register);
11927 __ sarl($tmp$$Register, 31);
11928 // $limit - $init
11929 __ subl($limit$$Register, $init$$Register);
11930 __ sbbl($limit_hi$$Register, $tmp$$Register);
11931 // + ($stride - 1)
11932 if (strd > 0) {
11933 __ addl($limit$$Register, (strd - 1));
11934 __ adcl($limit_hi$$Register, 0);
11935 __ movl($tmp$$Register, strd);
11936 } else {
11937 __ addl($limit$$Register, (strd + 1));
11938 __ adcl($limit_hi$$Register, -1);
11939 __ lneg($limit_hi$$Register, $limit$$Register);
11940 __ movl($tmp$$Register, -strd);
11941 }
11942 // signed devision: (EAX:EDX) / pos_stride
11943 __ idivl($tmp$$Register);
11944 if (strd < 0) {
11945 // restore sign
11946 __ negl($tmp$$Register);
11947 }
11948 // (EAX) * stride
11949 __ mull($tmp$$Register);
11950 // + init (ignore upper bits)
11951 __ addl($limit$$Register, $init$$Register);
11952 %}
11953 ins_pipe( pipe_slow );
11954 %}
11955
11956 // ============================================================================
11957 // Branch Instructions
11958 // Jump Table
11959 instruct jumpXtnd(rRegI switch_val) %{
11960 match(Jump switch_val);
11961 ins_cost(350);
11962 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
11963 ins_encode %{
11964 // Jump to Address(table_base + switch_reg)
11965 Address index(noreg, $switch_val$$Register, Address::times_1);
11966 __ jump(ArrayAddress($constantaddress, index));
11967 %}
11968 ins_pipe(pipe_jmp);
11969 %}
11970
11971 // Jump Direct - Label defines a relative address from JMP+1
11972 instruct jmpDir(label labl) %{
11973 match(Goto);
11974 effect(USE labl);
11975
11976 ins_cost(300);
11977 format %{ "JMP $labl" %}
11978 size(5);
11979 ins_encode %{
11980 Label* L = $labl$$label;
11981 __ jmp(*L, false); // Always long jump
11982 %}
11983 ins_pipe( pipe_jmp );
11984 %}
11985
11986 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11987 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
11988 match(If cop cr);
11989 effect(USE labl);
11990
11991 ins_cost(300);
11992 format %{ "J$cop $labl" %}
11993 size(6);
11994 ins_encode %{
11995 Label* L = $labl$$label;
11996 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11997 %}
11998 ins_pipe( pipe_jcc );
11999 %}
12000
12001 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12002 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12003 match(CountedLoopEnd cop cr);
12004 effect(USE labl);
12005
12006 ins_cost(300);
12007 format %{ "J$cop $labl\t# Loop end" %}
12008 size(6);
12009 ins_encode %{
12010 Label* L = $labl$$label;
12011 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12012 %}
12013 ins_pipe( pipe_jcc );
12014 %}
12015
12016 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12017 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12018 match(CountedLoopEnd cop cmp);
12019 effect(USE labl);
12020
12021 ins_cost(300);
12022 format %{ "J$cop,u $labl\t# Loop end" %}
12023 size(6);
12024 ins_encode %{
12025 Label* L = $labl$$label;
12026 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12027 %}
12028 ins_pipe( pipe_jcc );
12029 %}
12030
12031 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12032 match(CountedLoopEnd cop cmp);
12033 effect(USE labl);
12034
12035 ins_cost(200);
12036 format %{ "J$cop,u $labl\t# Loop end" %}
12037 size(6);
12038 ins_encode %{
12039 Label* L = $labl$$label;
12040 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12041 %}
12042 ins_pipe( pipe_jcc );
12043 %}
12044
12045 // Jump Direct Conditional - using unsigned comparison
12046 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12047 match(If cop cmp);
12048 effect(USE labl);
12049
12050 ins_cost(300);
12051 format %{ "J$cop,u $labl" %}
12052 size(6);
12053 ins_encode %{
12054 Label* L = $labl$$label;
12055 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12056 %}
12057 ins_pipe(pipe_jcc);
12058 %}
12059
12060 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12061 match(If cop cmp);
12062 effect(USE labl);
12063
12064 ins_cost(200);
12065 format %{ "J$cop,u $labl" %}
12066 size(6);
12067 ins_encode %{
12068 Label* L = $labl$$label;
12069 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12070 %}
12071 ins_pipe(pipe_jcc);
12072 %}
12073
12074 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12075 match(If cop cmp);
12076 effect(USE labl);
12077
12078 ins_cost(200);
12079 format %{ $$template
12080 if ($cop$$cmpcode == Assembler::notEqual) {
12081 $$emit$$"JP,u $labl\n\t"
12082 $$emit$$"J$cop,u $labl"
12083 } else {
12084 $$emit$$"JP,u done\n\t"
12085 $$emit$$"J$cop,u $labl\n\t"
12086 $$emit$$"done:"
12087 }
12088 %}
12089 ins_encode %{
12090 Label* l = $labl$$label;
12091 if ($cop$$cmpcode == Assembler::notEqual) {
12092 __ jcc(Assembler::parity, *l, false);
12093 __ jcc(Assembler::notEqual, *l, false);
12094 } else if ($cop$$cmpcode == Assembler::equal) {
12095 Label done;
12096 __ jccb(Assembler::parity, done);
12097 __ jcc(Assembler::equal, *l, false);
12098 __ bind(done);
12099 } else {
12100 ShouldNotReachHere();
12101 }
12102 %}
12103 ins_pipe(pipe_jcc);
12104 %}
12105
12106 // ============================================================================
12107 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12108 // array for an instance of the superklass. Set a hidden internal cache on a
12109 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12110 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12111 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12112 match(Set result (PartialSubtypeCheck sub super));
12113 effect( KILL rcx, KILL cr );
12114
12115 ins_cost(1100); // slightly larger than the next version
12116 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12117 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12118 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12119 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12120 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12121 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12122 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12123 "miss:\t" %}
12124
12125 opcode(0x1); // Force a XOR of EDI
12126 ins_encode( enc_PartialSubtypeCheck() );
12127 ins_pipe( pipe_slow );
12128 %}
12129
12130 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12131 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12132 effect( KILL rcx, KILL result );
12133
12134 ins_cost(1000);
12135 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12136 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12137 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12138 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12139 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12140 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12141 "miss:\t" %}
12142
12143 opcode(0x0); // No need to XOR EDI
12144 ins_encode( enc_PartialSubtypeCheck() );
12145 ins_pipe( pipe_slow );
12146 %}
12147
12148 // ============================================================================
12149 // Branch Instructions -- short offset versions
12150 //
12151 // These instructions are used to replace jumps of a long offset (the default
12152 // match) with jumps of a shorter offset. These instructions are all tagged
12153 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12154 // match rules in general matching. Instead, the ADLC generates a conversion
12155 // method in the MachNode which can be used to do in-place replacement of the
12156 // long variant with the shorter variant. The compiler will determine if a
12157 // branch can be taken by the is_short_branch_offset() predicate in the machine
12158 // specific code section of the file.
12159
12160 // Jump Direct - Label defines a relative address from JMP+1
12161 instruct jmpDir_short(label labl) %{
12162 match(Goto);
12163 effect(USE labl);
12164
12165 ins_cost(300);
12166 format %{ "JMP,s $labl" %}
12167 size(2);
12168 ins_encode %{
12169 Label* L = $labl$$label;
12170 __ jmpb(*L);
12171 %}
12172 ins_pipe( pipe_jmp );
12173 ins_short_branch(1);
12174 %}
12175
12176 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12177 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12178 match(If cop cr);
12179 effect(USE labl);
12180
12181 ins_cost(300);
12182 format %{ "J$cop,s $labl" %}
12183 size(2);
12184 ins_encode %{
12185 Label* L = $labl$$label;
12186 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12187 %}
12188 ins_pipe( pipe_jcc );
12189 ins_short_branch(1);
12190 %}
12191
12192 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12193 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12194 match(CountedLoopEnd cop cr);
12195 effect(USE labl);
12196
12197 ins_cost(300);
12198 format %{ "J$cop,s $labl\t# Loop end" %}
12199 size(2);
12200 ins_encode %{
12201 Label* L = $labl$$label;
12202 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12203 %}
12204 ins_pipe( pipe_jcc );
12205 ins_short_branch(1);
12206 %}
12207
12208 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12209 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12210 match(CountedLoopEnd cop cmp);
12211 effect(USE labl);
12212
12213 ins_cost(300);
12214 format %{ "J$cop,us $labl\t# Loop end" %}
12215 size(2);
12216 ins_encode %{
12217 Label* L = $labl$$label;
12218 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12219 %}
12220 ins_pipe( pipe_jcc );
12221 ins_short_branch(1);
12222 %}
12223
12224 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12225 match(CountedLoopEnd cop cmp);
12226 effect(USE labl);
12227
12228 ins_cost(300);
12229 format %{ "J$cop,us $labl\t# Loop end" %}
12230 size(2);
12231 ins_encode %{
12232 Label* L = $labl$$label;
12233 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12234 %}
12235 ins_pipe( pipe_jcc );
12236 ins_short_branch(1);
12237 %}
12238
12239 // Jump Direct Conditional - using unsigned comparison
12240 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12241 match(If cop cmp);
12242 effect(USE labl);
12243
12244 ins_cost(300);
12245 format %{ "J$cop,us $labl" %}
12246 size(2);
12247 ins_encode %{
12248 Label* L = $labl$$label;
12249 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12250 %}
12251 ins_pipe( pipe_jcc );
12252 ins_short_branch(1);
12253 %}
12254
12255 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12256 match(If cop cmp);
12257 effect(USE labl);
12258
12259 ins_cost(300);
12260 format %{ "J$cop,us $labl" %}
12261 size(2);
12262 ins_encode %{
12263 Label* L = $labl$$label;
12264 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12265 %}
12266 ins_pipe( pipe_jcc );
12267 ins_short_branch(1);
12268 %}
12269
12270 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12271 match(If cop cmp);
12272 effect(USE labl);
12273
12274 ins_cost(300);
12275 format %{ $$template
12276 if ($cop$$cmpcode == Assembler::notEqual) {
12277 $$emit$$"JP,u,s $labl\n\t"
12278 $$emit$$"J$cop,u,s $labl"
12279 } else {
12280 $$emit$$"JP,u,s done\n\t"
12281 $$emit$$"J$cop,u,s $labl\n\t"
12282 $$emit$$"done:"
12283 }
12284 %}
12285 size(4);
12286 ins_encode %{
12287 Label* l = $labl$$label;
12288 if ($cop$$cmpcode == Assembler::notEqual) {
12289 __ jccb(Assembler::parity, *l);
12290 __ jccb(Assembler::notEqual, *l);
12291 } else if ($cop$$cmpcode == Assembler::equal) {
12292 Label done;
12293 __ jccb(Assembler::parity, done);
12294 __ jccb(Assembler::equal, *l);
12295 __ bind(done);
12296 } else {
12297 ShouldNotReachHere();
12298 }
12299 %}
12300 ins_pipe(pipe_jcc);
12301 ins_short_branch(1);
12302 %}
12303
12304 // ============================================================================
12305 // Long Compare
12306 //
12307 // Currently we hold longs in 2 registers. Comparing such values efficiently
12308 // is tricky. The flavor of compare used depends on whether we are testing
12309 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12310 // The GE test is the negated LT test. The LE test can be had by commuting
12311 // the operands (yielding a GE test) and then negating; negate again for the
12312 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12313 // NE test is negated from that.
12314
12315 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12316 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12317 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12318 // are collapsed internally in the ADLC's dfa-gen code. The match for
12319 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12320 // foo match ends up with the wrong leaf. One fix is to not match both
12321 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12322 // both forms beat the trinary form of long-compare and both are very useful
12323 // on Intel which has so few registers.
12324
12325 // Manifest a CmpL result in an integer register. Very painful.
12326 // This is the test to avoid.
12327 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12328 match(Set dst (CmpL3 src1 src2));
12329 effect( KILL flags );
12330 ins_cost(1000);
12331 format %{ "XOR $dst,$dst\n\t"
12332 "CMP $src1.hi,$src2.hi\n\t"
12333 "JLT,s m_one\n\t"
12334 "JGT,s p_one\n\t"
12335 "CMP $src1.lo,$src2.lo\n\t"
12336 "JB,s m_one\n\t"
12337 "JEQ,s done\n"
12338 "p_one:\tINC $dst\n\t"
12339 "JMP,s done\n"
12340 "m_one:\tDEC $dst\n"
12341 "done:" %}
12342 ins_encode %{
12343 Label p_one, m_one, done;
12344 __ xorptr($dst$$Register, $dst$$Register);
12345 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12346 __ jccb(Assembler::less, m_one);
12347 __ jccb(Assembler::greater, p_one);
12348 __ cmpl($src1$$Register, $src2$$Register);
12349 __ jccb(Assembler::below, m_one);
12350 __ jccb(Assembler::equal, done);
12351 __ bind(p_one);
12352 __ incrementl($dst$$Register);
12353 __ jmpb(done);
12354 __ bind(m_one);
12355 __ decrementl($dst$$Register);
12356 __ bind(done);
12357 %}
12358 ins_pipe( pipe_slow );
12359 %}
12360
12361 //======
12362 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12363 // compares. Can be used for LE or GT compares by reversing arguments.
12364 // NOT GOOD FOR EQ/NE tests.
12365 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12366 match( Set flags (CmpL src zero ));
12367 ins_cost(100);
12368 format %{ "TEST $src.hi,$src.hi" %}
12369 opcode(0x85);
12370 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12371 ins_pipe( ialu_cr_reg_reg );
12372 %}
12373
12374 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12375 // compares. Can be used for LE or GT compares by reversing arguments.
12376 // NOT GOOD FOR EQ/NE tests.
12377 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12378 match( Set flags (CmpL src1 src2 ));
12379 effect( TEMP tmp );
12380 ins_cost(300);
12381 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12382 "MOV $tmp,$src1.hi\n\t"
12383 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12384 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12385 ins_pipe( ialu_cr_reg_reg );
12386 %}
12387
12388 // Long compares reg < zero/req OR reg >= zero/req.
12389 // Just a wrapper for a normal branch, plus the predicate test.
12390 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12391 match(If cmp flags);
12392 effect(USE labl);
12393 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12394 expand %{
12395 jmpCon(cmp,flags,labl); // JLT or JGE...
12396 %}
12397 %}
12398
12399 // Compare 2 longs and CMOVE longs.
12400 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12401 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12402 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12403 ins_cost(400);
12404 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12405 "CMOV$cmp $dst.hi,$src.hi" %}
12406 opcode(0x0F,0x40);
12407 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12408 ins_pipe( pipe_cmov_reg_long );
12409 %}
12410
12411 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12412 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12413 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12414 ins_cost(500);
12415 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12416 "CMOV$cmp $dst.hi,$src.hi" %}
12417 opcode(0x0F,0x40);
12418 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12419 ins_pipe( pipe_cmov_reg_long );
12420 %}
12421
12422 // Compare 2 longs and CMOVE ints.
12423 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12424 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12425 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12426 ins_cost(200);
12427 format %{ "CMOV$cmp $dst,$src" %}
12428 opcode(0x0F,0x40);
12429 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12430 ins_pipe( pipe_cmov_reg );
12431 %}
12432
12433 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12434 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12435 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12436 ins_cost(250);
12437 format %{ "CMOV$cmp $dst,$src" %}
12438 opcode(0x0F,0x40);
12439 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12440 ins_pipe( pipe_cmov_mem );
12441 %}
12442
12443 // Compare 2 longs and CMOVE ints.
12444 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12445 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12446 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12447 ins_cost(200);
12448 format %{ "CMOV$cmp $dst,$src" %}
12449 opcode(0x0F,0x40);
12450 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12451 ins_pipe( pipe_cmov_reg );
12452 %}
12453
12454 // Compare 2 longs and CMOVE doubles
12455 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12456 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12457 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12458 ins_cost(200);
12459 expand %{
12460 fcmovDPR_regS(cmp,flags,dst,src);
12461 %}
12462 %}
12463
12464 // Compare 2 longs and CMOVE doubles
12465 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12466 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12467 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12468 ins_cost(200);
12469 expand %{
12470 fcmovD_regS(cmp,flags,dst,src);
12471 %}
12472 %}
12473
12474 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12475 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12476 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12477 ins_cost(200);
12478 expand %{
12479 fcmovFPR_regS(cmp,flags,dst,src);
12480 %}
12481 %}
12482
12483 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12484 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12485 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12486 ins_cost(200);
12487 expand %{
12488 fcmovF_regS(cmp,flags,dst,src);
12489 %}
12490 %}
12491
12492 //======
12493 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12494 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12495 match( Set flags (CmpL src zero ));
12496 effect(TEMP tmp);
12497 ins_cost(200);
12498 format %{ "MOV $tmp,$src.lo\n\t"
12499 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12500 ins_encode( long_cmp_flags0( src, tmp ) );
12501 ins_pipe( ialu_reg_reg_long );
12502 %}
12503
12504 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12505 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12506 match( Set flags (CmpL src1 src2 ));
12507 ins_cost(200+300);
12508 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12509 "JNE,s skip\n\t"
12510 "CMP $src1.hi,$src2.hi\n\t"
12511 "skip:\t" %}
12512 ins_encode( long_cmp_flags1( src1, src2 ) );
12513 ins_pipe( ialu_cr_reg_reg );
12514 %}
12515
12516 // Long compare reg == zero/reg OR reg != zero/reg
12517 // Just a wrapper for a normal branch, plus the predicate test.
12518 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12519 match(If cmp flags);
12520 effect(USE labl);
12521 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12522 expand %{
12523 jmpCon(cmp,flags,labl); // JEQ or JNE...
12524 %}
12525 %}
12526
12527 // Compare 2 longs and CMOVE longs.
12528 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12529 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12530 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12531 ins_cost(400);
12532 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12533 "CMOV$cmp $dst.hi,$src.hi" %}
12534 opcode(0x0F,0x40);
12535 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12536 ins_pipe( pipe_cmov_reg_long );
12537 %}
12538
12539 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12540 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12541 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12542 ins_cost(500);
12543 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12544 "CMOV$cmp $dst.hi,$src.hi" %}
12545 opcode(0x0F,0x40);
12546 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12547 ins_pipe( pipe_cmov_reg_long );
12548 %}
12549
12550 // Compare 2 longs and CMOVE ints.
12551 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12552 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12553 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12554 ins_cost(200);
12555 format %{ "CMOV$cmp $dst,$src" %}
12556 opcode(0x0F,0x40);
12557 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12558 ins_pipe( pipe_cmov_reg );
12559 %}
12560
12561 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12562 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12563 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12564 ins_cost(250);
12565 format %{ "CMOV$cmp $dst,$src" %}
12566 opcode(0x0F,0x40);
12567 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12568 ins_pipe( pipe_cmov_mem );
12569 %}
12570
12571 // Compare 2 longs and CMOVE ints.
12572 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12573 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12574 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12575 ins_cost(200);
12576 format %{ "CMOV$cmp $dst,$src" %}
12577 opcode(0x0F,0x40);
12578 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12579 ins_pipe( pipe_cmov_reg );
12580 %}
12581
12582 // Compare 2 longs and CMOVE doubles
12583 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12584 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12585 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12586 ins_cost(200);
12587 expand %{
12588 fcmovDPR_regS(cmp,flags,dst,src);
12589 %}
12590 %}
12591
12592 // Compare 2 longs and CMOVE doubles
12593 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12594 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12595 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12596 ins_cost(200);
12597 expand %{
12598 fcmovD_regS(cmp,flags,dst,src);
12599 %}
12600 %}
12601
12602 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12603 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12604 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12605 ins_cost(200);
12606 expand %{
12607 fcmovFPR_regS(cmp,flags,dst,src);
12608 %}
12609 %}
12610
12611 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12612 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12613 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12614 ins_cost(200);
12615 expand %{
12616 fcmovF_regS(cmp,flags,dst,src);
12617 %}
12618 %}
12619
12620 //======
12621 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12622 // Same as cmpL_reg_flags_LEGT except must negate src
12623 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12624 match( Set flags (CmpL src zero ));
12625 effect( TEMP tmp );
12626 ins_cost(300);
12627 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12628 "CMP $tmp,$src.lo\n\t"
12629 "SBB $tmp,$src.hi\n\t" %}
12630 ins_encode( long_cmp_flags3(src, tmp) );
12631 ins_pipe( ialu_reg_reg_long );
12632 %}
12633
12634 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12635 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12636 // requires a commuted test to get the same result.
12637 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12638 match( Set flags (CmpL src1 src2 ));
12639 effect( TEMP tmp );
12640 ins_cost(300);
12641 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12642 "MOV $tmp,$src2.hi\n\t"
12643 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12644 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12645 ins_pipe( ialu_cr_reg_reg );
12646 %}
12647
12648 // Long compares reg < zero/req OR reg >= zero/req.
12649 // Just a wrapper for a normal branch, plus the predicate test
12650 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12651 match(If cmp flags);
12652 effect(USE labl);
12653 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12654 ins_cost(300);
12655 expand %{
12656 jmpCon(cmp,flags,labl); // JGT or JLE...
12657 %}
12658 %}
12659
12660 // Compare 2 longs and CMOVE longs.
12661 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12662 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12663 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12664 ins_cost(400);
12665 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12666 "CMOV$cmp $dst.hi,$src.hi" %}
12667 opcode(0x0F,0x40);
12668 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12669 ins_pipe( pipe_cmov_reg_long );
12670 %}
12671
12672 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12673 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12674 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12675 ins_cost(500);
12676 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12677 "CMOV$cmp $dst.hi,$src.hi+4" %}
12678 opcode(0x0F,0x40);
12679 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12680 ins_pipe( pipe_cmov_reg_long );
12681 %}
12682
12683 // Compare 2 longs and CMOVE ints.
12684 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12685 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12686 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12687 ins_cost(200);
12688 format %{ "CMOV$cmp $dst,$src" %}
12689 opcode(0x0F,0x40);
12690 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12691 ins_pipe( pipe_cmov_reg );
12692 %}
12693
12694 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12695 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12696 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12697 ins_cost(250);
12698 format %{ "CMOV$cmp $dst,$src" %}
12699 opcode(0x0F,0x40);
12700 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12701 ins_pipe( pipe_cmov_mem );
12702 %}
12703
12704 // Compare 2 longs and CMOVE ptrs.
12705 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12706 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12707 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12708 ins_cost(200);
12709 format %{ "CMOV$cmp $dst,$src" %}
12710 opcode(0x0F,0x40);
12711 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12712 ins_pipe( pipe_cmov_reg );
12713 %}
12714
12715 // Compare 2 longs and CMOVE doubles
12716 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12717 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12718 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12719 ins_cost(200);
12720 expand %{
12721 fcmovDPR_regS(cmp,flags,dst,src);
12722 %}
12723 %}
12724
12725 // Compare 2 longs and CMOVE doubles
12726 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12727 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12728 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12729 ins_cost(200);
12730 expand %{
12731 fcmovD_regS(cmp,flags,dst,src);
12732 %}
12733 %}
12734
12735 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12736 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12737 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12738 ins_cost(200);
12739 expand %{
12740 fcmovFPR_regS(cmp,flags,dst,src);
12741 %}
12742 %}
12743
12744
12745 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12746 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12747 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12748 ins_cost(200);
12749 expand %{
12750 fcmovF_regS(cmp,flags,dst,src);
12751 %}
12752 %}
12753
12754
12755 // ============================================================================
12756 // Procedure Call/Return Instructions
12757 // Call Java Static Instruction
12758 // Note: If this code changes, the corresponding ret_addr_offset() and
12759 // compute_padding() functions will have to be adjusted.
12760 instruct CallStaticJavaDirect(method meth) %{
12761 match(CallStaticJava);
12762 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12763 effect(USE meth);
12764
12765 ins_cost(300);
12766 format %{ "CALL,static " %}
12767 opcode(0xE8); /* E8 cd */
12768 ins_encode( pre_call_resets,
12769 Java_Static_Call( meth ),
12770 call_epilog,
12771 post_call_FPU );
12772 ins_pipe( pipe_slow );
12773 ins_alignment(4);
12774 %}
12775
12776 // Call Java Static Instruction (method handle version)
12777 // Note: If this code changes, the corresponding ret_addr_offset() and
12778 // compute_padding() functions will have to be adjusted.
12779 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12780 match(CallStaticJava);
12781 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12782 effect(USE meth);
12783 // EBP is saved by all callees (for interpreter stack correction).
12784 // We use it here for a similar purpose, in {preserve,restore}_SP.
12785
12786 ins_cost(300);
12787 format %{ "CALL,static/MethodHandle " %}
12788 opcode(0xE8); /* E8 cd */
12789 ins_encode( pre_call_resets,
12790 preserve_SP,
12791 Java_Static_Call( meth ),
12792 restore_SP,
12793 call_epilog,
12794 post_call_FPU );
12795 ins_pipe( pipe_slow );
12796 ins_alignment(4);
12797 %}
12798
12799 // Call Java Dynamic Instruction
12800 // Note: If this code changes, the corresponding ret_addr_offset() and
12801 // compute_padding() functions will have to be adjusted.
12802 instruct CallDynamicJavaDirect(method meth) %{
12803 match(CallDynamicJava);
12804 effect(USE meth);
12805
12806 ins_cost(300);
12807 format %{ "MOV EAX,(oop)-1\n\t"
12808 "CALL,dynamic" %}
12809 opcode(0xE8); /* E8 cd */
12810 ins_encode( pre_call_resets,
12811 Java_Dynamic_Call( meth ),
12812 call_epilog,
12813 post_call_FPU );
12814 ins_pipe( pipe_slow );
12815 ins_alignment(4);
12816 %}
12817
12818 // Call Runtime Instruction
12819 instruct CallRuntimeDirect(method meth) %{
12820 match(CallRuntime );
12821 effect(USE meth);
12822
12823 ins_cost(300);
12824 format %{ "CALL,runtime " %}
12825 opcode(0xE8); /* E8 cd */
12826 // Use FFREEs to clear entries in float stack
12827 ins_encode( pre_call_resets,
12828 FFree_Float_Stack_All,
12829 Java_To_Runtime( meth ),
12830 post_call_FPU );
12831 ins_pipe( pipe_slow );
12832 %}
12833
12834 // Call runtime without safepoint
12835 instruct CallLeafDirect(method meth) %{
12836 match(CallLeaf);
12837 effect(USE meth);
12838
12839 ins_cost(300);
12840 format %{ "CALL_LEAF,runtime " %}
12841 opcode(0xE8); /* E8 cd */
12842 ins_encode( pre_call_resets,
12843 FFree_Float_Stack_All,
12844 Java_To_Runtime( meth ),
12845 Verify_FPU_For_Leaf, post_call_FPU );
12846 ins_pipe( pipe_slow );
12847 %}
12848
12849 instruct CallLeafNoFPDirect(method meth) %{
12850 match(CallLeafNoFP);
12851 effect(USE meth);
12852
12853 ins_cost(300);
12854 format %{ "CALL_LEAF_NOFP,runtime " %}
12855 opcode(0xE8); /* E8 cd */
12856 ins_encode(Java_To_Runtime(meth));
12857 ins_pipe( pipe_slow );
12858 %}
12859
12860
12861 // Return Instruction
12862 // Remove the return address & jump to it.
12863 instruct Ret() %{
12864 match(Return);
12865 format %{ "RET" %}
12866 opcode(0xC3);
12867 ins_encode(OpcP);
12868 ins_pipe( pipe_jmp );
12869 %}
12870
12871 // Tail Call; Jump from runtime stub to Java code.
12872 // Also known as an 'interprocedural jump'.
12873 // Target of jump will eventually return to caller.
12874 // TailJump below removes the return address.
12875 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12876 match(TailCall jump_target method_oop );
12877 ins_cost(300);
12878 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12879 opcode(0xFF, 0x4); /* Opcode FF /4 */
12880 ins_encode( OpcP, RegOpc(jump_target) );
12881 ins_pipe( pipe_jmp );
12882 %}
12883
12884
12885 // Tail Jump; remove the return address; jump to target.
12886 // TailCall above leaves the return address around.
12887 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12888 match( TailJump jump_target ex_oop );
12889 ins_cost(300);
12890 format %{ "POP EDX\t# pop return address into dummy\n\t"
12891 "JMP $jump_target " %}
12892 opcode(0xFF, 0x4); /* Opcode FF /4 */
12893 ins_encode( enc_pop_rdx,
12894 OpcP, RegOpc(jump_target) );
12895 ins_pipe( pipe_jmp );
12896 %}
12897
12898 // Create exception oop: created by stack-crawling runtime code.
12899 // Created exception is now available to this handler, and is setup
12900 // just prior to jumping to this handler. No code emitted.
12901 instruct CreateException( eAXRegP ex_oop )
12902 %{
12903 match(Set ex_oop (CreateEx));
12904
12905 size(0);
12906 // use the following format syntax
12907 format %{ "# exception oop is in EAX; no code emitted" %}
12908 ins_encode();
12909 ins_pipe( empty );
12910 %}
12911
12912
12913 // Rethrow exception:
12914 // The exception oop will come in the first argument position.
12915 // Then JUMP (not call) to the rethrow stub code.
12916 instruct RethrowException()
12917 %{
12918 match(Rethrow);
12919
12920 // use the following format syntax
12921 format %{ "JMP rethrow_stub" %}
12922 ins_encode(enc_rethrow);
12923 ins_pipe( pipe_jmp );
12924 %}
12925
12926 // inlined locking and unlocking
12927
12928 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12929 match(Set cr (FastLock object box));
12930 effect(TEMP tmp, TEMP scr, USE_KILL box);
12931 ins_cost(300);
12932 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12933 ins_encode %{
12934 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register, _counters);
12935 %}
12936 ins_pipe(pipe_slow);
12937 %}
12938
12939 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12940 match(Set cr (FastUnlock object box));
12941 effect(TEMP tmp, USE_KILL box);
12942 ins_cost(300);
12943 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12944 ins_encode %{
12945 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
12946 %}
12947 ins_pipe(pipe_slow);
12948 %}
12949
12950
12951
12952 // ============================================================================
12953 // Safepoint Instruction
12954 instruct safePoint_poll(eFlagsReg cr) %{
12955 match(SafePoint);
12956 effect(KILL cr);
12957
12958 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12959 // On SPARC that might be acceptable as we can generate the address with
12960 // just a sethi, saving an or. By polling at offset 0 we can end up
12961 // putting additional pressure on the index-0 in the D$. Because of
12962 // alignment (just like the situation at hand) the lower indices tend
12963 // to see more traffic. It'd be better to change the polling address
12964 // to offset 0 of the last $line in the polling page.
12965
12966 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12967 ins_cost(125);
12968 size(6) ;
12969 ins_encode( Safepoint_Poll() );
12970 ins_pipe( ialu_reg_mem );
12971 %}
12972
12973
12974 // ============================================================================
12975 // This name is KNOWN by the ADLC and cannot be changed.
12976 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12977 // for this guy.
12978 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
12979 match(Set dst (ThreadLocal));
12980 effect(DEF dst, KILL cr);
12981
12982 format %{ "MOV $dst, Thread::current()" %}
12983 ins_encode %{
12984 Register dstReg = as_Register($dst$$reg);
12985 __ get_thread(dstReg);
12986 %}
12987 ins_pipe( ialu_reg_fat );
12988 %}
12989
12990
12991
12992 //----------PEEPHOLE RULES-----------------------------------------------------
12993 // These must follow all instruction definitions as they use the names
12994 // defined in the instructions definitions.
12995 //
12996 // peepmatch ( root_instr_name [preceding_instruction]* );
12997 //
12998 // peepconstraint %{
12999 // (instruction_number.operand_name relational_op instruction_number.operand_name
13000 // [, ...] );
13001 // // instruction numbers are zero-based using left to right order in peepmatch
13002 //
13003 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13004 // // provide an instruction_number.operand_name for each operand that appears
13005 // // in the replacement instruction's match rule
13006 //
13007 // ---------VM FLAGS---------------------------------------------------------
13008 //
13009 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13010 //
13011 // Each peephole rule is given an identifying number starting with zero and
13012 // increasing by one in the order seen by the parser. An individual peephole
13013 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13014 // on the command-line.
13015 //
13016 // ---------CURRENT LIMITATIONS----------------------------------------------
13017 //
13018 // Only match adjacent instructions in same basic block
13019 // Only equality constraints
13020 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13021 // Only one replacement instruction
13022 //
13023 // ---------EXAMPLE----------------------------------------------------------
13024 //
13025 // // pertinent parts of existing instructions in architecture description
13026 // instruct movI(rRegI dst, rRegI src) %{
13027 // match(Set dst (CopyI src));
13028 // %}
13029 //
13030 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13031 // match(Set dst (AddI dst src));
13032 // effect(KILL cr);
13033 // %}
13034 //
13035 // // Change (inc mov) to lea
13036 // peephole %{
13037 // // increment preceeded by register-register move
13038 // peepmatch ( incI_eReg movI );
13039 // // require that the destination register of the increment
13040 // // match the destination register of the move
13041 // peepconstraint ( 0.dst == 1.dst );
13042 // // construct a replacement instruction that sets
13043 // // the destination to ( move's source register + one )
13044 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13045 // %}
13046 //
13047 // Implementation no longer uses movX instructions since
13048 // machine-independent system no longer uses CopyX nodes.
13049 //
13050 // peephole %{
13051 // peepmatch ( incI_eReg movI );
13052 // peepconstraint ( 0.dst == 1.dst );
13053 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13054 // %}
13055 //
13056 // peephole %{
13057 // peepmatch ( decI_eReg movI );
13058 // peepconstraint ( 0.dst == 1.dst );
13059 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13060 // %}
13061 //
13062 // peephole %{
13063 // peepmatch ( addI_eReg_imm movI );
13064 // peepconstraint ( 0.dst == 1.dst );
13065 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13066 // %}
13067 //
13068 // peephole %{
13069 // peepmatch ( addP_eReg_imm movP );
13070 // peepconstraint ( 0.dst == 1.dst );
13071 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13072 // %}
13073
13074 // // Change load of spilled value to only a spill
13075 // instruct storeI(memory mem, rRegI src) %{
13076 // match(Set mem (StoreI mem src));
13077 // %}
13078 //
13079 // instruct loadI(rRegI dst, memory mem) %{
13080 // match(Set dst (LoadI mem));
13081 // %}
13082 //
13083 peephole %{
13084 peepmatch ( loadI storeI );
13085 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13086 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13087 %}
13088
13089 //----------SMARTSPILL RULES---------------------------------------------------
13090 // These must follow all instruction definitions as they use the names
13091 // defined in the instructions definitions.