1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc_interface/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/cardTableModRefBS.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "prims/methodHandles.hpp"
35 #include "runtime/biasedLocking.hpp"
36 #include "runtime/interfaceSupport.hpp"
37 #include "runtime/objectMonitor.hpp"
38 #include "runtime/os.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/macros.hpp"
42 #if INCLUDE_ALL_GCS
43 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
44 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
45 #include "gc_implementation/g1/heapRegion.hpp"
46 #endif // INCLUDE_ALL_GCS
47
48 #ifdef PRODUCT
49 #define BLOCK_COMMENT(str) /* nothing */
50 #define STOP(error) stop(error)
51 #else
52 #define BLOCK_COMMENT(str) block_comment(str)
53 #define STOP(error) block_comment(error); stop(error)
54 #endif
55
56 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
57
58 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
59
60 #ifdef ASSERT
61 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
62 #endif
63
64 static Assembler::Condition reverse[] = {
65 Assembler::noOverflow /* overflow = 0x0 */ ,
66 Assembler::overflow /* noOverflow = 0x1 */ ,
67 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
68 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
69 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
70 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
71 Assembler::above /* belowEqual = 0x6 */ ,
72 Assembler::belowEqual /* above = 0x7 */ ,
73 Assembler::positive /* negative = 0x8 */ ,
74 Assembler::negative /* positive = 0x9 */ ,
75 Assembler::noParity /* parity = 0xa */ ,
76 Assembler::parity /* noParity = 0xb */ ,
77 Assembler::greaterEqual /* less = 0xc */ ,
78 Assembler::less /* greaterEqual = 0xd */ ,
79 Assembler::greater /* lessEqual = 0xe */ ,
80 Assembler::lessEqual /* greater = 0xf, */
81
82 };
83
84
85 // Implementation of MacroAssembler
86
87 // First all the versions that have distinct versions depending on 32/64 bit
88 // Unless the difference is trivial (1 line or so).
89
90 #ifndef _LP64
91
92 // 32bit versions
93
94 Address MacroAssembler::as_Address(AddressLiteral adr) {
95 return Address(adr.target(), adr.rspec());
96 }
97
98 Address MacroAssembler::as_Address(ArrayAddress adr) {
99 return Address::make_array(adr);
100 }
101
102 void MacroAssembler::call_VM_leaf_base(address entry_point,
103 int number_of_arguments) {
104 call(RuntimeAddress(entry_point));
105 increment(rsp, number_of_arguments * wordSize);
106 }
107
108 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
109 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
110 }
111
112 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpoop(Address src1, jobject obj) {
117 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Register src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::extend_sign(Register hi, Register lo) {
125 // According to Intel Doc. AP-526, "Integer Divide", p.18.
126 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
127 cdql();
128 } else {
129 movl(hi, lo);
130 sarl(hi, 31);
131 }
132 }
133
134 void MacroAssembler::jC2(Register tmp, Label& L) {
135 // set parity bit if FPU flag C2 is set (via rax)
136 save_rax(tmp);
137 fwait(); fnstsw_ax();
138 sahf();
139 restore_rax(tmp);
140 // branch
141 jcc(Assembler::parity, L);
142 }
143
144 void MacroAssembler::jnC2(Register tmp, Label& L) {
145 // set parity bit if FPU flag C2 is set (via rax)
146 save_rax(tmp);
147 fwait(); fnstsw_ax();
148 sahf();
149 restore_rax(tmp);
150 // branch
151 jcc(Assembler::noParity, L);
152 }
153
154 // 32bit can do a case table jump in one instruction but we no longer allow the base
155 // to be installed in the Address class
156 void MacroAssembler::jump(ArrayAddress entry) {
157 jmp(as_Address(entry));
158 }
159
160 // Note: y_lo will be destroyed
161 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
162 // Long compare for Java (semantics as described in JVM spec.)
163 Label high, low, done;
164
165 cmpl(x_hi, y_hi);
166 jcc(Assembler::less, low);
167 jcc(Assembler::greater, high);
168 // x_hi is the return register
169 xorl(x_hi, x_hi);
170 cmpl(x_lo, y_lo);
171 jcc(Assembler::below, low);
172 jcc(Assembler::equal, done);
173
174 bind(high);
175 xorl(x_hi, x_hi);
176 increment(x_hi);
177 jmp(done);
178
179 bind(low);
180 xorl(x_hi, x_hi);
181 decrementl(x_hi);
182
183 bind(done);
184 }
185
186 void MacroAssembler::lea(Register dst, AddressLiteral src) {
187 mov_literal32(dst, (int32_t)src.target(), src.rspec());
188 }
189
190 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
191 // leal(dst, as_Address(adr));
192 // see note in movl as to why we must use a move
193 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
194 }
195
196 void MacroAssembler::leave() {
197 mov(rsp, rbp);
198 pop(rbp);
199 }
200
201 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
202 // Multiplication of two Java long values stored on the stack
203 // as illustrated below. Result is in rdx:rax.
204 //
205 // rsp ---> [ ?? ] \ \
206 // .... | y_rsp_offset |
207 // [ y_lo ] / (in bytes) | x_rsp_offset
208 // [ y_hi ] | (in bytes)
209 // .... |
210 // [ x_lo ] /
211 // [ x_hi ]
212 // ....
213 //
214 // Basic idea: lo(result) = lo(x_lo * y_lo)
215 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
216 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
217 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
218 Label quick;
219 // load x_hi, y_hi and check if quick
220 // multiplication is possible
221 movl(rbx, x_hi);
222 movl(rcx, y_hi);
223 movl(rax, rbx);
224 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
225 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
226 // do full multiplication
227 // 1st step
228 mull(y_lo); // x_hi * y_lo
229 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
230 // 2nd step
231 movl(rax, x_lo);
232 mull(rcx); // x_lo * y_hi
233 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
234 // 3rd step
235 bind(quick); // note: rbx, = 0 if quick multiply!
236 movl(rax, x_lo);
237 mull(y_lo); // x_lo * y_lo
238 addl(rdx, rbx); // correct hi(x_lo * y_lo)
239 }
240
241 void MacroAssembler::lneg(Register hi, Register lo) {
242 negl(lo);
243 adcl(hi, 0);
244 negl(hi);
245 }
246
247 void MacroAssembler::lshl(Register hi, Register lo) {
248 // Java shift left long support (semantics as described in JVM spec., p.305)
249 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
250 // shift value is in rcx !
251 assert(hi != rcx, "must not use rcx");
252 assert(lo != rcx, "must not use rcx");
253 const Register s = rcx; // shift count
254 const int n = BitsPerWord;
255 Label L;
256 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
257 cmpl(s, n); // if (s < n)
258 jcc(Assembler::less, L); // else (s >= n)
259 movl(hi, lo); // x := x << n
260 xorl(lo, lo);
261 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
262 bind(L); // s (mod n) < n
263 shldl(hi, lo); // x := x << s
264 shll(lo);
265 }
266
267
268 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
269 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
270 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
271 assert(hi != rcx, "must not use rcx");
272 assert(lo != rcx, "must not use rcx");
273 const Register s = rcx; // shift count
274 const int n = BitsPerWord;
275 Label L;
276 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
277 cmpl(s, n); // if (s < n)
278 jcc(Assembler::less, L); // else (s >= n)
279 movl(lo, hi); // x := x >> n
280 if (sign_extension) sarl(hi, 31);
281 else xorl(hi, hi);
282 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
283 bind(L); // s (mod n) < n
284 shrdl(lo, hi); // x := x >> s
285 if (sign_extension) sarl(hi);
286 else shrl(hi);
287 }
288
289 void MacroAssembler::movoop(Register dst, jobject obj) {
290 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
291 }
292
293 void MacroAssembler::movoop(Address dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
298 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
306 // scratch register is not used,
307 // it is defined to match parameters of 64-bit version of this method.
308 if (src.is_lval()) {
309 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
310 } else {
311 movl(dst, as_Address(src));
312 }
313 }
314
315 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
316 movl(as_Address(dst), src);
317 }
318
319 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
320 movl(dst, as_Address(src));
321 }
322
323 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
324 void MacroAssembler::movptr(Address dst, intptr_t src) {
325 movl(dst, src);
326 }
327
328
329 void MacroAssembler::pop_callee_saved_registers() {
330 pop(rcx);
331 pop(rdx);
332 pop(rdi);
333 pop(rsi);
334 }
335
336 void MacroAssembler::pop_fTOS() {
337 fld_d(Address(rsp, 0));
338 addl(rsp, 2 * wordSize);
339 }
340
341 void MacroAssembler::push_callee_saved_registers() {
342 push(rsi);
343 push(rdi);
344 push(rdx);
345 push(rcx);
346 }
347
348 void MacroAssembler::push_fTOS() {
349 subl(rsp, 2 * wordSize);
350 fstp_d(Address(rsp, 0));
351 }
352
353
354 void MacroAssembler::pushoop(jobject obj) {
355 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
356 }
357
358 void MacroAssembler::pushklass(Metadata* obj) {
359 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushptr(AddressLiteral src) {
363 if (src.is_lval()) {
364 push_literal32((int32_t)src.target(), src.rspec());
365 } else {
366 pushl(as_Address(src));
367 }
368 }
369
370 void MacroAssembler::set_word_if_not_zero(Register dst) {
371 xorl(dst, dst);
372 set_byte_if_not_zero(dst);
373 }
374
375 static void pass_arg0(MacroAssembler* masm, Register arg) {
376 masm->push(arg);
377 }
378
379 static void pass_arg1(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg2(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg3(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 #ifndef PRODUCT
392 extern "C" void findpc(intptr_t x);
393 #endif
394
395 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
396 // In order to get locks to work, we need to fake a in_VM state
397 JavaThread* thread = JavaThread::current();
398 JavaThreadState saved_state = thread->thread_state();
399 thread->set_thread_state(_thread_in_vm);
400 if (ShowMessageBoxOnError) {
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
405 ttyLocker ttyl;
406 BytecodeCounter::print();
407 }
408 // To see where a verify_oop failed, get $ebx+40/X for this frame.
409 // This is the value of eip which points to where verify_oop will return.
410 if (os::message_box(msg, "Execution stopped, print registers?")) {
411 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
412 BREAKPOINT;
413 }
414 } else {
415 ttyLocker ttyl;
416 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
417 }
418 // Don't assert holding the ttyLock
419 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
420 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
421 }
422
423 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
424 ttyLocker ttyl;
425 FlagSetting fs(Debugging, true);
426 tty->print_cr("eip = 0x%08x", eip);
427 #ifndef PRODUCT
428 if ((WizardMode || Verbose) && PrintMiscellaneous) {
429 tty->cr();
430 findpc(eip);
431 tty->cr();
432 }
433 #endif
434 #define PRINT_REG(rax) \
435 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
436 PRINT_REG(rax);
437 PRINT_REG(rbx);
438 PRINT_REG(rcx);
439 PRINT_REG(rdx);
440 PRINT_REG(rdi);
441 PRINT_REG(rsi);
442 PRINT_REG(rbp);
443 PRINT_REG(rsp);
444 #undef PRINT_REG
445 // Print some words near top of staack.
446 int* dump_sp = (int*) rsp;
447 for (int col1 = 0; col1 < 8; col1++) {
448 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
449 os::print_location(tty, *dump_sp++);
450 }
451 for (int row = 0; row < 16; row++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 for (int col = 0; col < 8; col++) {
454 tty->print(" 0x%08x", *dump_sp++);
455 }
456 tty->cr();
457 }
458 // Print some instructions around pc:
459 Disassembler::decode((address)eip-64, (address)eip);
460 tty->print_cr("--------");
461 Disassembler::decode((address)eip, (address)eip+32);
462 }
463
464 void MacroAssembler::stop(const char* msg) {
465 ExternalAddress message((address)msg);
466 // push address of message
467 pushptr(message.addr());
468 { Label L; call(L, relocInfo::none); bind(L); } // push eip
469 pusha(); // push registers
470 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
471 hlt();
472 }
473
474 void MacroAssembler::warn(const char* msg) {
475 push_CPU_state();
476
477 ExternalAddress message((address) msg);
478 // push address of message
479 pushptr(message.addr());
480
481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
482 addl(rsp, wordSize); // discard argument
483 pop_CPU_state();
484 }
485
486 void MacroAssembler::print_state() {
487 { Label L; call(L, relocInfo::none); bind(L); } // push eip
488 pusha(); // push registers
489
490 push_CPU_state();
491 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
492 pop_CPU_state();
493
494 popa();
495 addl(rsp, wordSize);
496 }
497
498 #else // _LP64
499
500 // 64 bit versions
501
502 Address MacroAssembler::as_Address(AddressLiteral adr) {
503 // amd64 always does this as a pc-rel
504 // we can be absolute or disp based on the instruction type
505 // jmp/call are displacements others are absolute
506 assert(!adr.is_lval(), "must be rval");
507 assert(reachable(adr), "must be");
508 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
509
510 }
511
512 Address MacroAssembler::as_Address(ArrayAddress adr) {
513 AddressLiteral base = adr.base();
514 lea(rscratch1, base);
515 Address index = adr.index();
516 assert(index._disp == 0, "must not have disp"); // maybe it can?
517 Address array(rscratch1, index._index, index._scale, index._disp);
518 return array;
519 }
520
521 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
522 Label L, E;
523
524 #ifdef _WIN64
525 // Windows always allocates space for it's register args
526 assert(num_args <= 4, "only register arguments supported");
527 subq(rsp, frame::arg_reg_save_area_bytes);
528 #endif
529
530 // Align stack if necessary
531 testl(rsp, 15);
532 jcc(Assembler::zero, L);
533
534 subq(rsp, 8);
535 {
536 call(RuntimeAddress(entry_point));
537 }
538 addq(rsp, 8);
539 jmp(E);
540
541 bind(L);
542 {
543 call(RuntimeAddress(entry_point));
544 }
545
546 bind(E);
547
548 #ifdef _WIN64
549 // restore stack pointer
550 addq(rsp, frame::arg_reg_save_area_bytes);
551 #endif
552
553 }
554
555 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
556 assert(!src2.is_lval(), "should use cmpptr");
557
558 if (reachable(src2)) {
559 cmpq(src1, as_Address(src2));
560 } else {
561 lea(rscratch1, src2);
562 Assembler::cmpq(src1, Address(rscratch1, 0));
563 }
564 }
565
566 int MacroAssembler::corrected_idivq(Register reg) {
567 // Full implementation of Java ldiv and lrem; checks for special
568 // case as described in JVM spec., p.243 & p.271. The function
569 // returns the (pc) offset of the idivl instruction - may be needed
570 // for implicit exceptions.
571 //
572 // normal case special case
573 //
574 // input : rax: dividend min_long
575 // reg: divisor (may not be eax/edx) -1
576 //
577 // output: rax: quotient (= rax idiv reg) min_long
578 // rdx: remainder (= rax irem reg) 0
579 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
580 static const int64_t min_long = 0x8000000000000000;
581 Label normal_case, special_case;
582
583 // check for special case
584 cmp64(rax, ExternalAddress((address) &min_long));
585 jcc(Assembler::notEqual, normal_case);
586 xorl(rdx, rdx); // prepare rdx for possible special case (where
587 // remainder = 0)
588 cmpq(reg, -1);
589 jcc(Assembler::equal, special_case);
590
591 // handle normal case
592 bind(normal_case);
593 cdqq();
594 int idivq_offset = offset();
595 idivq(reg);
596
597 // normal and special case exit
598 bind(special_case);
599
600 return idivq_offset;
601 }
602
603 void MacroAssembler::decrementq(Register reg, int value) {
604 if (value == min_jint) { subq(reg, value); return; }
605 if (value < 0) { incrementq(reg, -value); return; }
606 if (value == 0) { ; return; }
607 if (value == 1 && UseIncDec) { decq(reg) ; return; }
608 /* else */ { subq(reg, value) ; return; }
609 }
610
611 void MacroAssembler::decrementq(Address dst, int value) {
612 if (value == min_jint) { subq(dst, value); return; }
613 if (value < 0) { incrementq(dst, -value); return; }
614 if (value == 0) { ; return; }
615 if (value == 1 && UseIncDec) { decq(dst) ; return; }
616 /* else */ { subq(dst, value) ; return; }
617 }
618
619 void MacroAssembler::incrementq(AddressLiteral dst) {
620 if (reachable(dst)) {
621 incrementq(as_Address(dst));
622 } else {
623 lea(rscratch1, dst);
624 incrementq(Address(rscratch1, 0));
625 }
626 }
627
628 void MacroAssembler::incrementq(Register reg, int value) {
629 if (value == min_jint) { addq(reg, value); return; }
630 if (value < 0) { decrementq(reg, -value); return; }
631 if (value == 0) { ; return; }
632 if (value == 1 && UseIncDec) { incq(reg) ; return; }
633 /* else */ { addq(reg, value) ; return; }
634 }
635
636 void MacroAssembler::incrementq(Address dst, int value) {
637 if (value == min_jint) { addq(dst, value); return; }
638 if (value < 0) { decrementq(dst, -value); return; }
639 if (value == 0) { ; return; }
640 if (value == 1 && UseIncDec) { incq(dst) ; return; }
641 /* else */ { addq(dst, value) ; return; }
642 }
643
644 // 32bit can do a case table jump in one instruction but we no longer allow the base
645 // to be installed in the Address class
646 void MacroAssembler::jump(ArrayAddress entry) {
647 lea(rscratch1, entry.base());
648 Address dispatch = entry.index();
649 assert(dispatch._base == noreg, "must be");
650 dispatch._base = rscratch1;
651 jmp(dispatch);
652 }
653
654 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
655 ShouldNotReachHere(); // 64bit doesn't use two regs
656 cmpq(x_lo, y_lo);
657 }
658
659 void MacroAssembler::lea(Register dst, AddressLiteral src) {
660 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
661 }
662
663 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
664 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
665 movptr(dst, rscratch1);
666 }
667
668 void MacroAssembler::leave() {
669 // %%% is this really better? Why not on 32bit too?
670 emit_int8((unsigned char)0xC9); // LEAVE
671 }
672
673 void MacroAssembler::lneg(Register hi, Register lo) {
674 ShouldNotReachHere(); // 64bit doesn't use two regs
675 negq(lo);
676 }
677
678 void MacroAssembler::movoop(Register dst, jobject obj) {
679 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
680 }
681
682 void MacroAssembler::movoop(Address dst, jobject obj) {
683 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 movq(dst, rscratch1);
685 }
686
687 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
688 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
689 }
690
691 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
692 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 movq(dst, rscratch1);
694 }
695
696 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
697 if (src.is_lval()) {
698 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
699 } else {
700 if (reachable(src)) {
701 movq(dst, as_Address(src));
702 } else {
703 lea(scratch, src);
704 movq(dst, Address(scratch, 0));
705 }
706 }
707 }
708
709 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
710 movq(as_Address(dst), src);
711 }
712
713 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
714 movq(dst, as_Address(src));
715 }
716
717 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
718 void MacroAssembler::movptr(Address dst, intptr_t src) {
719 mov64(rscratch1, src);
720 movq(dst, rscratch1);
721 }
722
723 // These are mostly for initializing NULL
724 void MacroAssembler::movptr(Address dst, int32_t src) {
725 movslq(dst, src);
726 }
727
728 void MacroAssembler::movptr(Register dst, int32_t src) {
729 mov64(dst, (intptr_t)src);
730 }
731
732 void MacroAssembler::pushoop(jobject obj) {
733 movoop(rscratch1, obj);
734 push(rscratch1);
735 }
736
737 void MacroAssembler::pushklass(Metadata* obj) {
738 mov_metadata(rscratch1, obj);
739 push(rscratch1);
740 }
741
742 void MacroAssembler::pushptr(AddressLiteral src) {
743 lea(rscratch1, src);
744 if (src.is_lval()) {
745 push(rscratch1);
746 } else {
747 pushq(Address(rscratch1, 0));
748 }
749 }
750
751 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
752 bool clear_pc) {
753 // we must set sp to zero to clear frame
754 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
755 // must clear fp, so that compiled frames are not confused; it is
756 // possible that we need it only for debugging
757 if (clear_fp) {
758 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
759 }
760
761 if (clear_pc) {
762 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
763 }
764 }
765
766 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
767 Register last_java_fp,
768 address last_java_pc) {
769 // determine last_java_sp register
770 if (!last_java_sp->is_valid()) {
771 last_java_sp = rsp;
772 }
773
774 // last_java_fp is optional
775 if (last_java_fp->is_valid()) {
776 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
777 last_java_fp);
778 }
779
780 // last_java_pc is optional
781 if (last_java_pc != NULL) {
782 Address java_pc(r15_thread,
783 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
784 lea(rscratch1, InternalAddress(last_java_pc));
785 movptr(java_pc, rscratch1);
786 }
787
788 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
789 }
790
791 static void pass_arg0(MacroAssembler* masm, Register arg) {
792 if (c_rarg0 != arg ) {
793 masm->mov(c_rarg0, arg);
794 }
795 }
796
797 static void pass_arg1(MacroAssembler* masm, Register arg) {
798 if (c_rarg1 != arg ) {
799 masm->mov(c_rarg1, arg);
800 }
801 }
802
803 static void pass_arg2(MacroAssembler* masm, Register arg) {
804 if (c_rarg2 != arg ) {
805 masm->mov(c_rarg2, arg);
806 }
807 }
808
809 static void pass_arg3(MacroAssembler* masm, Register arg) {
810 if (c_rarg3 != arg ) {
811 masm->mov(c_rarg3, arg);
812 }
813 }
814
815 void MacroAssembler::stop(const char* msg) {
816 address rip = pc();
817 pusha(); // get regs on stack
818 lea(c_rarg0, ExternalAddress((address) msg));
819 lea(c_rarg1, InternalAddress(rip));
820 movq(c_rarg2, rsp); // pass pointer to regs array
821 andq(rsp, -16); // align stack as required by ABI
822 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
823 hlt();
824 }
825
826 void MacroAssembler::warn(const char* msg) {
827 push(rbp);
828 movq(rbp, rsp);
829 andq(rsp, -16); // align stack as required by push_CPU_state and call
830 push_CPU_state(); // keeps alignment at 16 bytes
831 lea(c_rarg0, ExternalAddress((address) msg));
832 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
833 pop_CPU_state();
834 mov(rsp, rbp);
835 pop(rbp);
836 }
837
838 void MacroAssembler::print_state() {
839 address rip = pc();
840 pusha(); // get regs on stack
841 push(rbp);
842 movq(rbp, rsp);
843 andq(rsp, -16); // align stack as required by push_CPU_state and call
844 push_CPU_state(); // keeps alignment at 16 bytes
845
846 lea(c_rarg0, InternalAddress(rip));
847 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
848 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
849
850 pop_CPU_state();
851 mov(rsp, rbp);
852 pop(rbp);
853 popa();
854 }
855
856 #ifndef PRODUCT
857 extern "C" void findpc(intptr_t x);
858 #endif
859
860 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
861 // In order to get locks to work, we need to fake a in_VM state
862 if (ShowMessageBoxOnError) {
863 JavaThread* thread = JavaThread::current();
864 JavaThreadState saved_state = thread->thread_state();
865 thread->set_thread_state(_thread_in_vm);
866 #ifndef PRODUCT
867 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
868 ttyLocker ttyl;
869 BytecodeCounter::print();
870 }
871 #endif
872 // To see where a verify_oop failed, get $ebx+40/X for this frame.
873 // XXX correct this offset for amd64
874 // This is the value of eip which points to where verify_oop will return.
875 if (os::message_box(msg, "Execution stopped, print registers?")) {
876 print_state64(pc, regs);
877 BREAKPOINT;
878 assert(false, "start up GDB");
879 }
880 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
881 } else {
882 ttyLocker ttyl;
883 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
884 msg);
885 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
886 }
887 }
888
889 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
890 ttyLocker ttyl;
891 FlagSetting fs(Debugging, true);
892 tty->print_cr("rip = 0x%016lx", pc);
893 #ifndef PRODUCT
894 tty->cr();
895 findpc(pc);
896 tty->cr();
897 #endif
898 #define PRINT_REG(rax, value) \
899 { tty->print("%s = ", #rax); os::print_location(tty, value); }
900 PRINT_REG(rax, regs[15]);
901 PRINT_REG(rbx, regs[12]);
902 PRINT_REG(rcx, regs[14]);
903 PRINT_REG(rdx, regs[13]);
904 PRINT_REG(rdi, regs[8]);
905 PRINT_REG(rsi, regs[9]);
906 PRINT_REG(rbp, regs[10]);
907 PRINT_REG(rsp, regs[11]);
908 PRINT_REG(r8 , regs[7]);
909 PRINT_REG(r9 , regs[6]);
910 PRINT_REG(r10, regs[5]);
911 PRINT_REG(r11, regs[4]);
912 PRINT_REG(r12, regs[3]);
913 PRINT_REG(r13, regs[2]);
914 PRINT_REG(r14, regs[1]);
915 PRINT_REG(r15, regs[0]);
916 #undef PRINT_REG
917 // Print some words near top of staack.
918 int64_t* rsp = (int64_t*) regs[11];
919 int64_t* dump_sp = rsp;
920 for (int col1 = 0; col1 < 8; col1++) {
921 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
922 os::print_location(tty, *dump_sp++);
923 }
924 for (int row = 0; row < 25; row++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 for (int col = 0; col < 4; col++) {
927 tty->print(" 0x%016lx", *dump_sp++);
928 }
929 tty->cr();
930 }
931 // Print some instructions around pc:
932 Disassembler::decode((address)pc-64, (address)pc);
933 tty->print_cr("--------");
934 Disassembler::decode((address)pc, (address)pc+32);
935 }
936
937 #endif // _LP64
938
939 // Now versions that are common to 32/64 bit
940
941 void MacroAssembler::addptr(Register dst, int32_t imm32) {
942 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
943 }
944
945 void MacroAssembler::addptr(Register dst, Register src) {
946 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
947 }
948
949 void MacroAssembler::addptr(Address dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
952
953 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
954 if (reachable(src)) {
955 Assembler::addsd(dst, as_Address(src));
956 } else {
957 lea(rscratch1, src);
958 Assembler::addsd(dst, Address(rscratch1, 0));
959 }
960 }
961
962 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
963 if (reachable(src)) {
964 addss(dst, as_Address(src));
965 } else {
966 lea(rscratch1, src);
967 addss(dst, Address(rscratch1, 0));
968 }
969 }
970
971 void MacroAssembler::align(int modulus) {
972 if (offset() % modulus != 0) {
973 nop(modulus - (offset() % modulus));
974 }
975 }
976
977 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
978 // Used in sign-masking with aligned address.
979 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
980 if (reachable(src)) {
981 Assembler::andpd(dst, as_Address(src));
982 } else {
983 lea(rscratch1, src);
984 Assembler::andpd(dst, Address(rscratch1, 0));
985 }
986 }
987
988 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
989 // Used in sign-masking with aligned address.
990 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
991 if (reachable(src)) {
992 Assembler::andps(dst, as_Address(src));
993 } else {
994 lea(rscratch1, src);
995 Assembler::andps(dst, Address(rscratch1, 0));
996 }
997 }
998
999 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1000 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1001 }
1002
1003 void MacroAssembler::atomic_incl(Address counter_addr) {
1004 if (os::is_MP())
1005 lock();
1006 incrementl(counter_addr);
1007 }
1008
1009 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1010 if (reachable(counter_addr)) {
1011 atomic_incl(as_Address(counter_addr));
1012 } else {
1013 lea(scr, counter_addr);
1014 atomic_incl(Address(scr, 0));
1015 }
1016 }
1017
1018 #ifdef _LP64
1019 void MacroAssembler::atomic_incq(Address counter_addr) {
1020 if (os::is_MP())
1021 lock();
1022 incrementq(counter_addr);
1023 }
1024
1025 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1026 if (reachable(counter_addr)) {
1027 atomic_incq(as_Address(counter_addr));
1028 } else {
1029 lea(scr, counter_addr);
1030 atomic_incq(Address(scr, 0));
1031 }
1032 }
1033 #endif
1034
1035 // Writes to stack successive pages until offset reached to check for
1036 // stack overflow + shadow pages. This clobbers tmp.
1037 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1038 movptr(tmp, rsp);
1039 // Bang stack for total size given plus shadow page size.
1040 // Bang one page at a time because large size can bang beyond yellow and
1041 // red zones.
1042 Label loop;
1043 bind(loop);
1044 movl(Address(tmp, (-os::vm_page_size())), size );
1045 subptr(tmp, os::vm_page_size());
1046 subl(size, os::vm_page_size());
1047 jcc(Assembler::greater, loop);
1048
1049 // Bang down shadow pages too.
1050 // At this point, (tmp-0) is the last address touched, so don't
1051 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1052 // was post-decremented.) Skip this address by starting at i=1, and
1053 // touch a few more pages below. N.B. It is important to touch all
1054 // the way down to and including i=StackShadowPages.
1055 for (int i = 1; i < StackShadowPages; i++) {
1056 // this could be any sized move but this is can be a debugging crumb
1057 // so the bigger the better.
1058 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1059 }
1060 }
1061
1062 int MacroAssembler::biased_locking_enter(Register lock_reg,
1063 Register obj_reg,
1064 Register swap_reg,
1065 Register tmp_reg,
1066 bool swap_reg_contains_mark,
1067 Label& done,
1068 Label* slow_case,
1069 BiasedLockingCounters* counters) {
1070 assert(UseBiasedLocking, "why call this otherwise?");
1071 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1072 LP64_ONLY( assert(tmp_reg != noreg, "tmp_reg must be supplied"); )
1073 bool need_tmp_reg = false;
1074 if (tmp_reg == noreg) {
1075 need_tmp_reg = true;
1076 tmp_reg = lock_reg;
1077 assert_different_registers(lock_reg, obj_reg, swap_reg);
1078 } else {
1079 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1080 }
1081 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1082 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1083 Address saved_mark_addr(lock_reg, 0);
1084
1085 if (PrintBiasedLockingStatistics && counters == NULL) {
1086 counters = BiasedLocking::counters();
1087 }
1088 // Biased locking
1089 // See whether the lock is currently biased toward our thread and
1090 // whether the epoch is still valid
1091 // Note that the runtime guarantees sufficient alignment of JavaThread
1092 // pointers to allow age to be placed into low bits
1093 // First check to see whether biasing is even enabled for this object
1094 Label cas_label;
1095 int null_check_offset = -1;
1096 if (!swap_reg_contains_mark) {
1097 null_check_offset = offset();
1098 movptr(swap_reg, mark_addr);
1099 }
1100 if (need_tmp_reg) {
1101 push(tmp_reg);
1102 }
1103 movptr(tmp_reg, swap_reg);
1104 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1105 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1106 if (need_tmp_reg) {
1107 pop(tmp_reg);
1108 }
1109 jcc(Assembler::notEqual, cas_label);
1110 // The bias pattern is present in the object's header. Need to check
1111 // whether the bias owner and the epoch are both still current.
1112 #ifndef _LP64
1113 // Note that because there is no current thread register on x86_32 we
1114 // need to store off the mark word we read out of the object to
1115 // avoid reloading it and needing to recheck invariants below. This
1116 // store is unfortunate but it makes the overall code shorter and
1117 // simpler.
1118 movptr(saved_mark_addr, swap_reg);
1119 #endif
1120 if (need_tmp_reg) {
1121 push(tmp_reg);
1122 }
1123 if (swap_reg_contains_mark) {
1124 null_check_offset = offset();
1125 }
1126 load_prototype_header(tmp_reg, obj_reg);
1127 #ifdef _LP64
1128 orptr(tmp_reg, r15_thread);
1129 xorptr(tmp_reg, swap_reg);
1130 Register header_reg = tmp_reg;
1131 #else
1132 xorptr(tmp_reg, swap_reg);
1133 get_thread(swap_reg);
1134 xorptr(swap_reg, tmp_reg);
1135 Register header_reg = swap_reg;
1136 #endif
1137 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1138 if (need_tmp_reg) {
1139 pop(tmp_reg);
1140 }
1141 if (counters != NULL) {
1142 cond_inc32(Assembler::zero,
1143 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1144 }
1145 jcc(Assembler::equal, done);
1146
1147 Label try_revoke_bias;
1148 Label try_rebias;
1149
1150 // At this point we know that the header has the bias pattern and
1151 // that we are not the bias owner in the current epoch. We need to
1152 // figure out more details about the state of the header in order to
1153 // know what operations can be legally performed on the object's
1154 // header.
1155
1156 // If the low three bits in the xor result aren't clear, that means
1157 // the prototype header is no longer biased and we have to revoke
1158 // the bias on this object.
1159 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1160 jccb(Assembler::notZero, try_revoke_bias);
1161
1162 // Biasing is still enabled for this data type. See whether the
1163 // epoch of the current bias is still valid, meaning that the epoch
1164 // bits of the mark word are equal to the epoch bits of the
1165 // prototype header. (Note that the prototype header's epoch bits
1166 // only change at a safepoint.) If not, attempt to rebias the object
1167 // toward the current thread. Note that we must be absolutely sure
1168 // that the current epoch is invalid in order to do this because
1169 // otherwise the manipulations it performs on the mark word are
1170 // illegal.
1171 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1172 jccb(Assembler::notZero, try_rebias);
1173
1174 // The epoch of the current bias is still valid but we know nothing
1175 // about the owner; it might be set or it might be clear. Try to
1176 // acquire the bias of the object using an atomic operation. If this
1177 // fails we will go in to the runtime to revoke the object's bias.
1178 // Note that we first construct the presumed unbiased header so we
1179 // don't accidentally blow away another thread's valid bias.
1180 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1181 andptr(swap_reg,
1182 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1183 if (need_tmp_reg) {
1184 push(tmp_reg);
1185 }
1186 #ifdef _LP64
1187 movptr(tmp_reg, swap_reg);
1188 orptr(tmp_reg, r15_thread);
1189 #else
1190 get_thread(tmp_reg);
1191 orptr(tmp_reg, swap_reg);
1192 #endif
1193 if (os::is_MP()) {
1194 lock();
1195 }
1196 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1197 if (need_tmp_reg) {
1198 pop(tmp_reg);
1199 }
1200 // If the biasing toward our thread failed, this means that
1201 // another thread succeeded in biasing it toward itself and we
1202 // need to revoke that bias. The revocation will occur in the
1203 // interpreter runtime in the slow case.
1204 if (counters != NULL) {
1205 cond_inc32(Assembler::zero,
1206 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1207 }
1208 if (slow_case != NULL) {
1209 jcc(Assembler::notZero, *slow_case);
1210 }
1211 jmp(done);
1212
1213 bind(try_rebias);
1214 // At this point we know the epoch has expired, meaning that the
1215 // current "bias owner", if any, is actually invalid. Under these
1216 // circumstances _only_, we are allowed to use the current header's
1217 // value as the comparison value when doing the cas to acquire the
1218 // bias in the current epoch. In other words, we allow transfer of
1219 // the bias from one thread to another directly in this situation.
1220 //
1221 // FIXME: due to a lack of registers we currently blow away the age
1222 // bits in this situation. Should attempt to preserve them.
1223 if (need_tmp_reg) {
1224 push(tmp_reg);
1225 }
1226 load_prototype_header(tmp_reg, obj_reg);
1227 #ifdef _LP64
1228 orptr(tmp_reg, r15_thread);
1229 #else
1230 get_thread(swap_reg);
1231 orptr(tmp_reg, swap_reg);
1232 movptr(swap_reg, saved_mark_addr);
1233 #endif
1234 if (os::is_MP()) {
1235 lock();
1236 }
1237 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1238 if (need_tmp_reg) {
1239 pop(tmp_reg);
1240 }
1241 // If the biasing toward our thread failed, then another thread
1242 // succeeded in biasing it toward itself and we need to revoke that
1243 // bias. The revocation will occur in the runtime in the slow case.
1244 if (counters != NULL) {
1245 cond_inc32(Assembler::zero,
1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247 }
1248 if (slow_case != NULL) {
1249 jcc(Assembler::notZero, *slow_case);
1250 }
1251 jmp(done);
1252
1253 bind(try_revoke_bias);
1254 // The prototype mark in the klass doesn't have the bias bit set any
1255 // more, indicating that objects of this data type are not supposed
1256 // to be biased any more. We are going to try to reset the mark of
1257 // this object to the prototype value and fall through to the
1258 // CAS-based locking scheme. Note that if our CAS fails, it means
1259 // that another thread raced us for the privilege of revoking the
1260 // bias of this particular object, so it's okay to continue in the
1261 // normal locking code.
1262 //
1263 // FIXME: due to a lack of registers we currently blow away the age
1264 // bits in this situation. Should attempt to preserve them.
1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266 if (need_tmp_reg) {
1267 push(tmp_reg);
1268 }
1269 load_prototype_header(tmp_reg, obj_reg);
1270 if (os::is_MP()) {
1271 lock();
1272 }
1273 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1274 if (need_tmp_reg) {
1275 pop(tmp_reg);
1276 }
1277 // Fall through to the normal CAS-based lock, because no matter what
1278 // the result of the above CAS, some thread must have succeeded in
1279 // removing the bias bit from the object's header.
1280 if (counters != NULL) {
1281 cond_inc32(Assembler::zero,
1282 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1283 }
1284
1285 bind(cas_label);
1286
1287 return null_check_offset;
1288 }
1289
1290 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1291 assert(UseBiasedLocking, "why call this otherwise?");
1292
1293 // Check for biased locking unlock case, which is a no-op
1294 // Note: we do not have to check the thread ID for two reasons.
1295 // First, the interpreter checks for IllegalMonitorStateException at
1296 // a higher level. Second, if the bias was revoked while we held the
1297 // lock, the object could not be rebiased toward another thread, so
1298 // the bias bit would be clear.
1299 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1300 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1301 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1302 jcc(Assembler::equal, done);
1303 }
1304
1305 #ifdef COMPILER2
1306
1307 #if INCLUDE_RTM_OPT
1308
1309 // Update rtm_counters based on abort status
1310 // input: abort_status
1311 // rtm_counters (RTMLockingCounters*)
1312 // flags are killed
1313 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1314
1315 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1316 if (PrintPreciseRTMLockingStatistics) {
1317 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1318 Label check_abort;
1319 testl(abort_status, (1<<i));
1320 jccb(Assembler::equal, check_abort);
1321 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1322 bind(check_abort);
1323 }
1324 }
1325 }
1326
1327 // Branch if (random & (count-1) != 0), count is 2^n
1328 // tmp, scr and flags are killed
1329 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1330 assert(tmp == rax, "");
1331 assert(scr == rdx, "");
1332 rdtsc(); // modifies EDX:EAX
1333 andptr(tmp, count-1);
1334 jccb(Assembler::notZero, brLabel);
1335 }
1336
1337 // Perform abort ratio calculation, set no_rtm bit if high ratio
1338 // input: rtm_counters_Reg (RTMLockingCounters* address)
1339 // tmpReg, rtm_counters_Reg and flags are killed
1340 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1341 Register rtm_counters_Reg,
1342 RTMLockingCounters* rtm_counters,
1343 Metadata* method_data) {
1344 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1345
1346 if (RTMLockingCalculationDelay > 0) {
1347 // Delay calculation
1348 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1349 testptr(tmpReg, tmpReg);
1350 jccb(Assembler::equal, L_done);
1351 }
1352 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1353 // Aborted transactions = abort_count * 100
1354 // All transactions = total_count * RTMTotalCountIncrRate
1355 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1356
1357 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1358 cmpptr(tmpReg, RTMAbortThreshold);
1359 jccb(Assembler::below, L_check_always_rtm2);
1360 imulptr(tmpReg, tmpReg, 100);
1361
1362 Register scrReg = rtm_counters_Reg;
1363 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1364 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1365 imulptr(scrReg, scrReg, RTMAbortRatio);
1366 cmpptr(tmpReg, scrReg);
1367 jccb(Assembler::below, L_check_always_rtm1);
1368 if (method_data != NULL) {
1369 // set rtm_state to "no rtm" in MDO
1370 mov_metadata(tmpReg, method_data);
1371 if (os::is_MP()) {
1372 lock();
1373 }
1374 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1375 }
1376 jmpb(L_done);
1377 bind(L_check_always_rtm1);
1378 // Reload RTMLockingCounters* address
1379 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1380 bind(L_check_always_rtm2);
1381 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1382 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1383 jccb(Assembler::below, L_done);
1384 if (method_data != NULL) {
1385 // set rtm_state to "always rtm" in MDO
1386 mov_metadata(tmpReg, method_data);
1387 if (os::is_MP()) {
1388 lock();
1389 }
1390 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1391 }
1392 bind(L_done);
1393 }
1394
1395 // Update counters and perform abort ratio calculation
1396 // input: abort_status_Reg
1397 // rtm_counters_Reg, flags are killed
1398 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1399 Register rtm_counters_Reg,
1400 RTMLockingCounters* rtm_counters,
1401 Metadata* method_data,
1402 bool profile_rtm) {
1403
1404 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1405 // update rtm counters based on rax value at abort
1406 // reads abort_status_Reg, updates flags
1407 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1408 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1409 if (profile_rtm) {
1410 // Save abort status because abort_status_Reg is used by following code.
1411 if (RTMRetryCount > 0) {
1412 push(abort_status_Reg);
1413 }
1414 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1415 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1416 // restore abort status
1417 if (RTMRetryCount > 0) {
1418 pop(abort_status_Reg);
1419 }
1420 }
1421 }
1422
1423 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1424 // inputs: retry_count_Reg
1425 // : abort_status_Reg
1426 // output: retry_count_Reg decremented by 1
1427 // flags are killed
1428 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1429 Label doneRetry;
1430 assert(abort_status_Reg == rax, "");
1431 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1432 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1433 // if reason is in 0x6 and retry count != 0 then retry
1434 andptr(abort_status_Reg, 0x6);
1435 jccb(Assembler::zero, doneRetry);
1436 testl(retry_count_Reg, retry_count_Reg);
1437 jccb(Assembler::zero, doneRetry);
1438 pause();
1439 decrementl(retry_count_Reg);
1440 jmp(retryLabel);
1441 bind(doneRetry);
1442 }
1443
1444 // Spin and retry if lock is busy,
1445 // inputs: box_Reg (monitor address)
1446 // : retry_count_Reg
1447 // output: retry_count_Reg decremented by 1
1448 // : clear z flag if retry count exceeded
1449 // tmp_Reg, scr_Reg, flags are killed
1450 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1451 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1452 Label SpinLoop, SpinExit, doneRetry;
1453 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1454
1455 testl(retry_count_Reg, retry_count_Reg);
1456 jccb(Assembler::zero, doneRetry);
1457 decrementl(retry_count_Reg);
1458 movptr(scr_Reg, RTMSpinLoopCount);
1459
1460 bind(SpinLoop);
1461 pause();
1462 decrementl(scr_Reg);
1463 jccb(Assembler::lessEqual, SpinExit);
1464 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1465 testptr(tmp_Reg, tmp_Reg);
1466 jccb(Assembler::notZero, SpinLoop);
1467
1468 bind(SpinExit);
1469 jmp(retryLabel);
1470 bind(doneRetry);
1471 incrementl(retry_count_Reg); // clear z flag
1472 }
1473
1474 // Use RTM for normal stack locks
1475 // Input: objReg (object to lock)
1476 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1477 Register retry_on_abort_count_Reg,
1478 RTMLockingCounters* stack_rtm_counters,
1479 Metadata* method_data, bool profile_rtm,
1480 Label& DONE_LABEL, Label& IsInflated) {
1481 assert(UseRTMForStackLocks, "why call this otherwise?");
1482 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1483 assert(tmpReg == rax, "");
1484 assert(scrReg == rdx, "");
1485 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1486
1487 if (RTMRetryCount > 0) {
1488 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1489 bind(L_rtm_retry);
1490 }
1491 movptr(tmpReg, Address(objReg, 0));
1492 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1493 jcc(Assembler::notZero, IsInflated);
1494
1495 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1496 Label L_noincrement;
1497 if (RTMTotalCountIncrRate > 1) {
1498 // tmpReg, scrReg and flags are killed
1499 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1500 }
1501 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1502 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1503 bind(L_noincrement);
1504 }
1505 xbegin(L_on_abort);
1506 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1507 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1508 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1509 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1510
1511 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1512 if (UseRTMXendForLockBusy) {
1513 xend();
1514 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1515 jmp(L_decrement_retry);
1516 }
1517 else {
1518 xabort(0);
1519 }
1520 bind(L_on_abort);
1521 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1522 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1523 }
1524 bind(L_decrement_retry);
1525 if (RTMRetryCount > 0) {
1526 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1527 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1528 }
1529 }
1530
1531 // Use RTM for inflating locks
1532 // inputs: objReg (object to lock)
1533 // boxReg (on-stack box address (displaced header location) - KILLED)
1534 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1535 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1536 Register scrReg, Register retry_on_busy_count_Reg,
1537 Register retry_on_abort_count_Reg,
1538 RTMLockingCounters* rtm_counters,
1539 Metadata* method_data, bool profile_rtm,
1540 Label& DONE_LABEL) {
1541 assert(UseRTMLocking, "why call this otherwise?");
1542 assert(tmpReg == rax, "");
1543 assert(scrReg == rdx, "");
1544 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1545 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1546
1547 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1548 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1549 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1550
1551 if (RTMRetryCount > 0) {
1552 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1553 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1554 bind(L_rtm_retry);
1555 }
1556 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1557 Label L_noincrement;
1558 if (RTMTotalCountIncrRate > 1) {
1559 // tmpReg, scrReg and flags are killed
1560 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1561 }
1562 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1563 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1564 bind(L_noincrement);
1565 }
1566 xbegin(L_on_abort);
1567 movptr(tmpReg, Address(objReg, 0));
1568 movptr(tmpReg, Address(tmpReg, owner_offset));
1569 testptr(tmpReg, tmpReg);
1570 jcc(Assembler::zero, DONE_LABEL);
1571 if (UseRTMXendForLockBusy) {
1572 xend();
1573 jmp(L_decrement_retry);
1574 }
1575 else {
1576 xabort(0);
1577 }
1578 bind(L_on_abort);
1579 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1580 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1581 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1582 }
1583 if (RTMRetryCount > 0) {
1584 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1585 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1586 }
1587
1588 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1589 testptr(tmpReg, tmpReg) ;
1590 jccb(Assembler::notZero, L_decrement_retry) ;
1591
1592 // Appears unlocked - try to swing _owner from null to non-null.
1593 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1594 #ifdef _LP64
1595 Register threadReg = r15_thread;
1596 #else
1597 get_thread(scrReg);
1598 Register threadReg = scrReg;
1599 #endif
1600 if (os::is_MP()) {
1601 lock();
1602 }
1603 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1604
1605 if (RTMRetryCount > 0) {
1606 // success done else retry
1607 jccb(Assembler::equal, DONE_LABEL) ;
1608 bind(L_decrement_retry);
1609 // Spin and retry if lock is busy.
1610 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1611 }
1612 else {
1613 bind(L_decrement_retry);
1614 }
1615 }
1616
1617 #endif // INCLUDE_RTM_OPT
1618
1619 // Fast_Lock and Fast_Unlock used by C2
1620
1621 // Because the transitions from emitted code to the runtime
1622 // monitorenter/exit helper stubs are so slow it's critical that
1623 // we inline both the stack-locking fast-path and the inflated fast path.
1624 //
1625 // See also: cmpFastLock and cmpFastUnlock.
1626 //
1627 // What follows is a specialized inline transliteration of the code
1628 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1629 // another option would be to emit TrySlowEnter and TrySlowExit methods
1630 // at startup-time. These methods would accept arguments as
1631 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1632 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1633 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1634 // In practice, however, the # of lock sites is bounded and is usually small.
1635 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1636 // if the processor uses simple bimodal branch predictors keyed by EIP
1637 // Since the helper routines would be called from multiple synchronization
1638 // sites.
1639 //
1640 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1641 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1642 // to those specialized methods. That'd give us a mostly platform-independent
1643 // implementation that the JITs could optimize and inline at their pleasure.
1644 // Done correctly, the only time we'd need to cross to native could would be
1645 // to park() or unpark() threads. We'd also need a few more unsafe operators
1646 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1647 // (b) explicit barriers or fence operations.
1648 //
1649 // TODO:
1650 //
1651 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1652 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1653 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1654 // the lock operators would typically be faster than reifying Self.
1655 //
1656 // * Ideally I'd define the primitives as:
1657 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1658 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1659 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1660 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1661 // Furthermore the register assignments are overconstrained, possibly resulting in
1662 // sub-optimal code near the synchronization site.
1663 //
1664 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1665 // Alternately, use a better sp-proximity test.
1666 //
1667 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1668 // Either one is sufficient to uniquely identify a thread.
1669 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1670 //
1671 // * Intrinsify notify() and notifyAll() for the common cases where the
1672 // object is locked by the calling thread but the waitlist is empty.
1673 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1674 //
1675 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1676 // But beware of excessive branch density on AMD Opterons.
1677 //
1678 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1679 // or failure of the fast-path. If the fast-path fails then we pass
1680 // control to the slow-path, typically in C. In Fast_Lock and
1681 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1682 // will emit a conditional branch immediately after the node.
1683 // So we have branches to branches and lots of ICC.ZF games.
1684 // Instead, it might be better to have C2 pass a "FailureLabel"
1685 // into Fast_Lock and Fast_Unlock. In the case of success, control
1686 // will drop through the node. ICC.ZF is undefined at exit.
1687 // In the case of failure, the node will branch directly to the
1688 // FailureLabel
1689
1690
1691 // obj: object to lock
1692 // box: on-stack box address (displaced header location) - KILLED
1693 // rax,: tmp -- KILLED
1694 // scr: tmp -- KILLED
1695 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1696 Register scrReg, Register cx1Reg, Register cx2Reg,
1697 BiasedLockingCounters* counters,
1698 RTMLockingCounters* rtm_counters,
1699 RTMLockingCounters* stack_rtm_counters,
1700 Metadata* method_data,
1701 bool use_rtm, bool profile_rtm) {
1702 // Ensure the register assignents are disjoint
1703 assert(tmpReg == rax, "");
1704
1705 if (use_rtm) {
1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1707 } else {
1708 assert(cx1Reg == noreg, "");
1709 assert(cx2Reg == noreg, "");
1710 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1711 }
1712
1713 if (counters != NULL) {
1714 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1715 }
1716 if (EmitSync & 1) {
1717 // set box->dhw = markOopDesc::unused_mark()
1718 // Force all sync thru slow-path: slow_enter() and slow_exit()
1719 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1720 cmpptr (rsp, (int32_t)NULL_WORD);
1721 } else
1722 if (EmitSync & 2) {
1723 Label DONE_LABEL ;
1724 if (UseBiasedLocking) {
1725 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
1726 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1727 }
1728
1729 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1730 orptr (tmpReg, 0x1);
1731 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1732 if (os::is_MP()) {
1733 lock();
1734 }
1735 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1736 jccb(Assembler::equal, DONE_LABEL);
1737 // Recursive locking
1738 subptr(tmpReg, rsp);
1739 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1740 movptr(Address(boxReg, 0), tmpReg);
1741 bind(DONE_LABEL);
1742 } else {
1743 // Possible cases that we'll encounter in fast_lock
1744 // ------------------------------------------------
1745 // * Inflated
1746 // -- unlocked
1747 // -- Locked
1748 // = by self
1749 // = by other
1750 // * biased
1751 // -- by Self
1752 // -- by other
1753 // * neutral
1754 // * stack-locked
1755 // -- by self
1756 // = sp-proximity test hits
1757 // = sp-proximity test generates false-negative
1758 // -- by other
1759 //
1760
1761 Label IsInflated, DONE_LABEL;
1762
1763 // it's stack-locked, biased or neutral
1764 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1765 // order to reduce the number of conditional branches in the most common cases.
1766 // Beware -- there's a subtle invariant that fetch of the markword
1767 // at [FETCH], below, will never observe a biased encoding (*101b).
1768 // If this invariant is not held we risk exclusion (safety) failure.
1769 if (UseBiasedLocking && !UseOptoBiasInlining) {
1770 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1771 }
1772
1773 #if INCLUDE_RTM_OPT
1774 if (UseRTMForStackLocks && use_rtm) {
1775 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1776 stack_rtm_counters, method_data, profile_rtm,
1777 DONE_LABEL, IsInflated);
1778 }
1779 #endif // INCLUDE_RTM_OPT
1780
1781 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1782 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1783 jccb(Assembler::notZero, IsInflated);
1784
1785 // Attempt stack-locking ...
1786 orptr (tmpReg, markOopDesc::unlocked_value);
1787 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1788 if (os::is_MP()) {
1789 lock();
1790 }
1791 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1792 if (counters != NULL) {
1793 cond_inc32(Assembler::equal,
1794 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1795 }
1796 jcc(Assembler::equal, DONE_LABEL); // Success
1797
1798 // Recursive locking.
1799 // The object is stack-locked: markword contains stack pointer to BasicLock.
1800 // Locked by current thread if difference with current SP is less than one page.
1801 subptr(tmpReg, rsp);
1802 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1803 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1804 movptr(Address(boxReg, 0), tmpReg);
1805 if (counters != NULL) {
1806 cond_inc32(Assembler::equal,
1807 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1808 }
1809 jmp(DONE_LABEL);
1810
1811 bind(IsInflated);
1812 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1813
1814 #if INCLUDE_RTM_OPT
1815 // Use the same RTM locking code in 32- and 64-bit VM.
1816 if (use_rtm) {
1817 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1818 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1819 } else {
1820 #endif // INCLUDE_RTM_OPT
1821
1822 #ifndef _LP64
1823 // The object is inflated.
1824
1825 // boxReg refers to the on-stack BasicLock in the current frame.
1826 // We'd like to write:
1827 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1828 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1829 // additional latency as we have another ST in the store buffer that must drain.
1830
1831 if (EmitSync & 8192) {
1832 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1833 get_thread (scrReg);
1834 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1835 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1836 if (os::is_MP()) {
1837 lock();
1838 }
1839 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1840 } else
1841 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1842 movptr(scrReg, boxReg);
1843 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1844
1845 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1846 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1847 // prefetchw [eax + Offset(_owner)-2]
1848 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1849 }
1850
1851 if ((EmitSync & 64) == 0) {
1852 // Optimistic form: consider XORL tmpReg,tmpReg
1853 movptr(tmpReg, NULL_WORD);
1854 } else {
1855 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1856 // Test-And-CAS instead of CAS
1857 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1858 testptr(tmpReg, tmpReg); // Locked ?
1859 jccb (Assembler::notZero, DONE_LABEL);
1860 }
1861
1862 // Appears unlocked - try to swing _owner from null to non-null.
1863 // Ideally, I'd manifest "Self" with get_thread and then attempt
1864 // to CAS the register containing Self into m->Owner.
1865 // But we don't have enough registers, so instead we can either try to CAS
1866 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1867 // we later store "Self" into m->Owner. Transiently storing a stack address
1868 // (rsp or the address of the box) into m->owner is harmless.
1869 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1870 if (os::is_MP()) {
1871 lock();
1872 }
1873 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1874 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1875 jccb (Assembler::notZero, DONE_LABEL);
1876 get_thread (scrReg); // beware: clobbers ICCs
1877 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1878 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1879
1880 // If the CAS fails we can either retry or pass control to the slow-path.
1881 // We use the latter tactic.
1882 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1883 // If the CAS was successful ...
1884 // Self has acquired the lock
1885 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1886 // Intentional fall-through into DONE_LABEL ...
1887 } else {
1888 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1889 movptr(boxReg, tmpReg);
1890
1891 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1892 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1893 // prefetchw [eax + Offset(_owner)-2]
1894 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1895 }
1896
1897 if ((EmitSync & 64) == 0) {
1898 // Optimistic form
1899 xorptr (tmpReg, tmpReg);
1900 } else {
1901 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1902 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1903 testptr(tmpReg, tmpReg); // Locked ?
1904 jccb (Assembler::notZero, DONE_LABEL);
1905 }
1906
1907 // Appears unlocked - try to swing _owner from null to non-null.
1908 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1909 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1910 get_thread (scrReg);
1911 if (os::is_MP()) {
1912 lock();
1913 }
1914 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1915
1916 // If the CAS fails we can either retry or pass control to the slow-path.
1917 // We use the latter tactic.
1918 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1919 // If the CAS was successful ...
1920 // Self has acquired the lock
1921 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1922 // Intentional fall-through into DONE_LABEL ...
1923 }
1924 #else // _LP64
1925 // It's inflated
1926
1927 // TODO: someday avoid the ST-before-CAS penalty by
1928 // relocating (deferring) the following ST.
1929 // We should also think about trying a CAS without having
1930 // fetched _owner. If the CAS is successful we may
1931 // avoid an RTO->RTS upgrade on the $line.
1932
1933 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1934 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1935
1936 movptr (boxReg, tmpReg);
1937 movptr(tmpReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1938 testptr(tmpReg, tmpReg);
1939 jccb (Assembler::notZero, DONE_LABEL);
1940
1941 // It's inflated and appears unlocked
1942 if (os::is_MP()) {
1943 lock();
1944 }
1945 cmpxchgptr(r15_thread, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1946 // Intentional fall-through into DONE_LABEL ...
1947 #endif // _LP64
1948
1949 #if INCLUDE_RTM_OPT
1950 } // use_rtm()
1951 #endif
1952 // DONE_LABEL is a hot target - we'd really like to place it at the
1953 // start of cache line by padding with NOPs.
1954 // See the AMD and Intel software optimization manuals for the
1955 // most efficient "long" NOP encodings.
1956 // Unfortunately none of our alignment mechanisms suffice.
1957 bind(DONE_LABEL);
1958
1959 // At DONE_LABEL the icc ZFlag is set as follows ...
1960 // Fast_Unlock uses the same protocol.
1961 // ZFlag == 1 -> Success
1962 // ZFlag == 0 -> Failure - force control through the slow-path
1963 }
1964 }
1965
1966 // obj: object to unlock
1967 // box: box address (displaced header location), killed. Must be EAX.
1968 // tmp: killed, cannot be obj nor box.
1969 //
1970 // Some commentary on balanced locking:
1971 //
1972 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1973 // Methods that don't have provably balanced locking are forced to run in the
1974 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1975 // The interpreter provides two properties:
1976 // I1: At return-time the interpreter automatically and quietly unlocks any
1977 // objects acquired the current activation (frame). Recall that the
1978 // interpreter maintains an on-stack list of locks currently held by
1979 // a frame.
1980 // I2: If a method attempts to unlock an object that is not held by the
1981 // the frame the interpreter throws IMSX.
1982 //
1983 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1984 // B() doesn't have provably balanced locking so it runs in the interpreter.
1985 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1986 // is still locked by A().
1987 //
1988 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1989 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1990 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1991 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1992
1993 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1994 assert(boxReg == rax, "");
1995 assert_different_registers(objReg, boxReg, tmpReg);
1996
1997 if (EmitSync & 4) {
1998 // Disable - inhibit all inlining. Force control through the slow-path
1999 cmpptr (rsp, 0);
2000 } else
2001 if (EmitSync & 8) {
2002 Label DONE_LABEL;
2003 if (UseBiasedLocking) {
2004 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2005 }
2006 // Classic stack-locking code ...
2007 // Check whether the displaced header is 0
2008 //(=> recursive unlock)
2009 movptr(tmpReg, Address(boxReg, 0));
2010 testptr(tmpReg, tmpReg);
2011 jccb(Assembler::zero, DONE_LABEL);
2012 // If not recursive lock, reset the header to displaced header
2013 if (os::is_MP()) {
2014 lock();
2015 }
2016 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2017 bind(DONE_LABEL);
2018 } else {
2019 Label DONE_LABEL, Stacked, CheckSucc;
2020
2021 // Critically, the biased locking test must have precedence over
2022 // and appear before the (box->dhw == 0) recursive stack-lock test.
2023 if (UseBiasedLocking && !UseOptoBiasInlining) {
2024 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2025 }
2026
2027 #if INCLUDE_RTM_OPT
2028 if (UseRTMForStackLocks && use_rtm) {
2029 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
2030 Label L_regular_unlock;
2031 movptr(tmpReg, Address(objReg, 0)); // fetch markword
2032 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2033 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2034 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2035 xend(); // otherwise end...
2036 jmp(DONE_LABEL); // ... and we're done
2037 bind(L_regular_unlock);
2038 }
2039 #endif
2040
2041 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2042 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2043 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
2044 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2045 jccb (Assembler::zero, Stacked);
2046
2047 // It's inflated.
2048 #if INCLUDE_RTM_OPT
2049 if (use_rtm) {
2050 Label L_regular_inflated_unlock;
2051 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2052 movptr(boxReg, Address(tmpReg, owner_offset));
2053 testptr(boxReg, boxReg);
2054 jccb(Assembler::notZero, L_regular_inflated_unlock);
2055 xend();
2056 jmpb(DONE_LABEL);
2057 bind(L_regular_inflated_unlock);
2058 }
2059 #endif
2060
2061 // Despite our balanced locking property we still check that m->_owner == Self
2062 // as java routines or native JNI code called by this thread might
2063 // have released the lock.
2064 // Refer to the comments in synchronizer.cpp for how we might encode extra
2065 // state in _succ so we can avoid fetching EntryList|cxq.
2066 //
2067 // I'd like to add more cases in fast_lock() and fast_unlock() --
2068 // such as recursive enter and exit -- but we have to be wary of
2069 // I$ bloat, T$ effects and BP$ effects.
2070 //
2071 // If there's no contention try a 1-0 exit. That is, exit without
2072 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2073 // we detect and recover from the race that the 1-0 exit admits.
2074 //
2075 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2076 // before it STs null into _owner, releasing the lock. Updates
2077 // to data protected by the critical section must be visible before
2078 // we drop the lock (and thus before any other thread could acquire
2079 // the lock and observe the fields protected by the lock).
2080 // IA32's memory-model is SPO, so STs are ordered with respect to
2081 // each other and there's no need for an explicit barrier (fence).
2082 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2083 #ifndef _LP64
2084 get_thread (boxReg);
2085 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2086 // prefetchw [ebx + Offset(_owner)-2]
2087 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2088 }
2089
2090 // Note that we could employ various encoding schemes to reduce
2091 // the number of loads below (currently 4) to just 2 or 3.
2092 // Refer to the comments in synchronizer.cpp.
2093 // In practice the chain of fetches doesn't seem to impact performance, however.
2094 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2095 // Attempt to reduce branch density - AMD's branch predictor.
2096 xorptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2097 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2098 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2099 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2100 jccb (Assembler::notZero, DONE_LABEL);
2101 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2102 jmpb (DONE_LABEL);
2103 } else {
2104 xorptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2105 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2106 jccb (Assembler::notZero, DONE_LABEL);
2107 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2108 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2109 jccb (Assembler::notZero, CheckSucc);
2110 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2111 jmpb (DONE_LABEL);
2112 }
2113
2114 // The Following code fragment (EmitSync & 65536) improves the performance of
2115 // contended applications and contended synchronization microbenchmarks.
2116 // Unfortunately the emission of the code - even though not executed - causes regressions
2117 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2118 // with an equal number of never-executed NOPs results in the same regression.
2119 // We leave it off by default.
2120
2121 if ((EmitSync & 65536) != 0) {
2122 Label LSuccess, LGoSlowPath ;
2123
2124 bind (CheckSucc);
2125
2126 // Optional pre-test ... it's safe to elide this
2127 if ((EmitSync & 16) == 0) {
2128 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2129 jccb (Assembler::zero, LGoSlowPath);
2130 }
2131
2132 // We have a classic Dekker-style idiom:
2133 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2134 // There are a number of ways to implement the barrier:
2135 // (1) lock:andl &m->_owner, 0
2136 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2137 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2138 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2139 // (2) If supported, an explicit MFENCE is appealing.
2140 // In older IA32 processors MFENCE is slower than lock:add or xchg
2141 // particularly if the write-buffer is full as might be the case if
2142 // if stores closely precede the fence or fence-equivalent instruction.
2143 // In more modern implementations MFENCE appears faster, however.
2144 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2145 // The $lines underlying the top-of-stack should be in M-state.
2146 // The locked add instruction is serializing, of course.
2147 // (4) Use xchg, which is serializing
2148 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2149 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2150 // The integer condition codes will tell us if succ was 0.
2151 // Since _succ and _owner should reside in the same $line and
2152 // we just stored into _owner, it's likely that the $line
2153 // remains in M-state for the lock:orl.
2154 //
2155 // We currently use (3), although it's likely that switching to (2)
2156 // is correct for the future.
2157
2158 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2159 if (os::is_MP()) {
2160 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
2161 mfence();
2162 } else {
2163 lock (); addptr(Address(rsp, 0), 0);
2164 }
2165 }
2166 // Ratify _succ remains non-null
2167 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2168 jccb (Assembler::notZero, LSuccess);
2169
2170 xorptr(boxReg, boxReg); // box is really EAX
2171 if (os::is_MP()) { lock(); }
2172 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2173 jccb (Assembler::notEqual, LSuccess);
2174 // Since we're low on registers we installed rsp as a placeholding in _owner.
2175 // Now install Self over rsp. This is safe as we're transitioning from
2176 // non-null to non=null
2177 get_thread (boxReg);
2178 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2179 // Intentional fall-through into LGoSlowPath ...
2180
2181 bind (LGoSlowPath);
2182 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2183 jmpb (DONE_LABEL);
2184
2185 bind (LSuccess);
2186 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2187 jmpb (DONE_LABEL);
2188 }
2189
2190 bind (Stacked);
2191 // It's not inflated and it's not recursively stack-locked and it's not biased.
2192 // It must be stack-locked.
2193 // Try to reset the header to displaced header.
2194 // The "box" value on the stack is stable, so we can reload
2195 // and be assured we observe the same value as above.
2196 movptr(tmpReg, Address(boxReg, 0));
2197 if (os::is_MP()) {
2198 lock();
2199 }
2200 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2201 // Intention fall-thru into DONE_LABEL
2202
2203 // DONE_LABEL is a hot target - we'd really like to place it at the
2204 // start of cache line by padding with NOPs.
2205 // See the AMD and Intel software optimization manuals for the
2206 // most efficient "long" NOP encodings.
2207 // Unfortunately none of our alignment mechanisms suffice.
2208 if ((EmitSync & 65536) == 0) {
2209 bind (CheckSucc);
2210 }
2211 #else // _LP64
2212 // It's inflated
2213 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2214 xorptr(boxReg, r15_thread);
2215 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2216 jccb (Assembler::notZero, DONE_LABEL);
2217 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2218 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2219 jccb (Assembler::notZero, CheckSucc);
2220 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2221 jmpb (DONE_LABEL);
2222
2223 if ((EmitSync & 65536) == 0) {
2224 Label LSuccess, LGoSlowPath ;
2225 bind (CheckSucc);
2226 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2227 jccb (Assembler::zero, LGoSlowPath);
2228
2229 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2230 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2231 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2232 // are all faster when the write buffer is populated.
2233 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2234 if (os::is_MP()) {
2235 lock (); addl (Address(rsp, 0), 0);
2236 }
2237 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2238 jccb (Assembler::notZero, LSuccess);
2239
2240 movptr (boxReg, (int32_t)NULL_WORD); // box is really EAX
2241 if (os::is_MP()) { lock(); }
2242 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2243 jccb (Assembler::notEqual, LSuccess);
2244 // Intentional fall-through into slow-path
2245
2246 bind (LGoSlowPath);
2247 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2248 jmpb (DONE_LABEL);
2249
2250 bind (LSuccess);
2251 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2252 jmpb (DONE_LABEL);
2253 }
2254
2255 bind (Stacked);
2256 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2257 if (os::is_MP()) { lock(); }
2258 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2259
2260 if (EmitSync & 65536) {
2261 bind (CheckSucc);
2262 }
2263 #endif
2264 bind(DONE_LABEL);
2265 // Avoid branch to branch on AMD processors
2266 if (EmitSync & 32768) {
2267 nop();
2268 }
2269 }
2270 }
2271 #endif // COMPILER2
2272
2273 void MacroAssembler::c2bool(Register x) {
2274 // implements x == 0 ? 0 : 1
2275 // note: must only look at least-significant byte of x
2276 // since C-style booleans are stored in one byte
2277 // only! (was bug)
2278 andl(x, 0xFF);
2279 setb(Assembler::notZero, x);
2280 }
2281
2282 // Wouldn't need if AddressLiteral version had new name
2283 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2284 Assembler::call(L, rtype);
2285 }
2286
2287 void MacroAssembler::call(Register entry) {
2288 Assembler::call(entry);
2289 }
2290
2291 void MacroAssembler::call(AddressLiteral entry) {
2292 if (reachable(entry)) {
2293 Assembler::call_literal(entry.target(), entry.rspec());
2294 } else {
2295 lea(rscratch1, entry);
2296 Assembler::call(rscratch1);
2297 }
2298 }
2299
2300 void MacroAssembler::ic_call(address entry) {
2301 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2302 movptr(rax, (intptr_t)Universe::non_oop_word());
2303 call(AddressLiteral(entry, rh));
2304 }
2305
2306 // Implementation of call_VM versions
2307
2308 void MacroAssembler::call_VM(Register oop_result,
2309 address entry_point,
2310 bool check_exceptions) {
2311 Label C, E;
2312 call(C, relocInfo::none);
2313 jmp(E);
2314
2315 bind(C);
2316 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2317 ret(0);
2318
2319 bind(E);
2320 }
2321
2322 void MacroAssembler::call_VM(Register oop_result,
2323 address entry_point,
2324 Register arg_1,
2325 bool check_exceptions) {
2326 Label C, E;
2327 call(C, relocInfo::none);
2328 jmp(E);
2329
2330 bind(C);
2331 pass_arg1(this, arg_1);
2332 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2333 ret(0);
2334
2335 bind(E);
2336 }
2337
2338 void MacroAssembler::call_VM(Register oop_result,
2339 address entry_point,
2340 Register arg_1,
2341 Register arg_2,
2342 bool check_exceptions) {
2343 Label C, E;
2344 call(C, relocInfo::none);
2345 jmp(E);
2346
2347 bind(C);
2348
2349 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2350
2351 pass_arg2(this, arg_2);
2352 pass_arg1(this, arg_1);
2353 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2354 ret(0);
2355
2356 bind(E);
2357 }
2358
2359 void MacroAssembler::call_VM(Register oop_result,
2360 address entry_point,
2361 Register arg_1,
2362 Register arg_2,
2363 Register arg_3,
2364 bool check_exceptions) {
2365 Label C, E;
2366 call(C, relocInfo::none);
2367 jmp(E);
2368
2369 bind(C);
2370
2371 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2372 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2373 pass_arg3(this, arg_3);
2374
2375 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2376 pass_arg2(this, arg_2);
2377
2378 pass_arg1(this, arg_1);
2379 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2380 ret(0);
2381
2382 bind(E);
2383 }
2384
2385 void MacroAssembler::call_VM(Register oop_result,
2386 Register last_java_sp,
2387 address entry_point,
2388 int number_of_arguments,
2389 bool check_exceptions) {
2390 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2391 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2392 }
2393
2394 void MacroAssembler::call_VM(Register oop_result,
2395 Register last_java_sp,
2396 address entry_point,
2397 Register arg_1,
2398 bool check_exceptions) {
2399 pass_arg1(this, arg_1);
2400 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2401 }
2402
2403 void MacroAssembler::call_VM(Register oop_result,
2404 Register last_java_sp,
2405 address entry_point,
2406 Register arg_1,
2407 Register arg_2,
2408 bool check_exceptions) {
2409
2410 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2411 pass_arg2(this, arg_2);
2412 pass_arg1(this, arg_1);
2413 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2414 }
2415
2416 void MacroAssembler::call_VM(Register oop_result,
2417 Register last_java_sp,
2418 address entry_point,
2419 Register arg_1,
2420 Register arg_2,
2421 Register arg_3,
2422 bool check_exceptions) {
2423 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2424 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2425 pass_arg3(this, arg_3);
2426 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2427 pass_arg2(this, arg_2);
2428 pass_arg1(this, arg_1);
2429 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2430 }
2431
2432 void MacroAssembler::super_call_VM(Register oop_result,
2433 Register last_java_sp,
2434 address entry_point,
2435 int number_of_arguments,
2436 bool check_exceptions) {
2437 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2438 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2439 }
2440
2441 void MacroAssembler::super_call_VM(Register oop_result,
2442 Register last_java_sp,
2443 address entry_point,
2444 Register arg_1,
2445 bool check_exceptions) {
2446 pass_arg1(this, arg_1);
2447 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2448 }
2449
2450 void MacroAssembler::super_call_VM(Register oop_result,
2451 Register last_java_sp,
2452 address entry_point,
2453 Register arg_1,
2454 Register arg_2,
2455 bool check_exceptions) {
2456
2457 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2458 pass_arg2(this, arg_2);
2459 pass_arg1(this, arg_1);
2460 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2461 }
2462
2463 void MacroAssembler::super_call_VM(Register oop_result,
2464 Register last_java_sp,
2465 address entry_point,
2466 Register arg_1,
2467 Register arg_2,
2468 Register arg_3,
2469 bool check_exceptions) {
2470 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2471 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2472 pass_arg3(this, arg_3);
2473 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2474 pass_arg2(this, arg_2);
2475 pass_arg1(this, arg_1);
2476 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2477 }
2478
2479 void MacroAssembler::call_VM_base(Register oop_result,
2480 Register java_thread,
2481 Register last_java_sp,
2482 address entry_point,
2483 int number_of_arguments,
2484 bool check_exceptions) {
2485 // determine java_thread register
2486 if (!java_thread->is_valid()) {
2487 #ifdef _LP64
2488 java_thread = r15_thread;
2489 #else
2490 java_thread = rdi;
2491 get_thread(java_thread);
2492 #endif // LP64
2493 }
2494 // determine last_java_sp register
2495 if (!last_java_sp->is_valid()) {
2496 last_java_sp = rsp;
2497 }
2498 // debugging support
2499 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2500 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2501 #ifdef ASSERT
2502 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2503 // r12 is the heapbase.
2504 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2505 #endif // ASSERT
2506
2507 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2508 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2509
2510 // push java thread (becomes first argument of C function)
2511
2512 NOT_LP64(push(java_thread); number_of_arguments++);
2513 LP64_ONLY(mov(c_rarg0, r15_thread));
2514
2515 // set last Java frame before call
2516 assert(last_java_sp != rbp, "can't use ebp/rbp");
2517
2518 // Only interpreter should have to set fp
2519 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2520
2521 // do the call, remove parameters
2522 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2523
2524 // restore the thread (cannot use the pushed argument since arguments
2525 // may be overwritten by C code generated by an optimizing compiler);
2526 // however can use the register value directly if it is callee saved.
2527 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2528 // rdi & rsi (also r15) are callee saved -> nothing to do
2529 #ifdef ASSERT
2530 guarantee(java_thread != rax, "change this code");
2531 push(rax);
2532 { Label L;
2533 get_thread(rax);
2534 cmpptr(java_thread, rax);
2535 jcc(Assembler::equal, L);
2536 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2537 bind(L);
2538 }
2539 pop(rax);
2540 #endif
2541 } else {
2542 get_thread(java_thread);
2543 }
2544 // reset last Java frame
2545 // Only interpreter should have to clear fp
2546 reset_last_Java_frame(java_thread, true, false);
2547
2548 #ifndef CC_INTERP
2549 // C++ interp handles this in the interpreter
2550 check_and_handle_popframe(java_thread);
2551 check_and_handle_earlyret(java_thread);
2552 #endif /* CC_INTERP */
2553
2554 if (check_exceptions) {
2555 // check for pending exceptions (java_thread is set upon return)
2556 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2557 #ifndef _LP64
2558 jump_cc(Assembler::notEqual,
2559 RuntimeAddress(StubRoutines::forward_exception_entry()));
2560 #else
2561 // This used to conditionally jump to forward_exception however it is
2562 // possible if we relocate that the branch will not reach. So we must jump
2563 // around so we can always reach
2564
2565 Label ok;
2566 jcc(Assembler::equal, ok);
2567 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2568 bind(ok);
2569 #endif // LP64
2570 }
2571
2572 // get oop result if there is one and reset the value in the thread
2573 if (oop_result->is_valid()) {
2574 get_vm_result(oop_result, java_thread);
2575 }
2576 }
2577
2578 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2579
2580 // Calculate the value for last_Java_sp
2581 // somewhat subtle. call_VM does an intermediate call
2582 // which places a return address on the stack just under the
2583 // stack pointer as the user finsihed with it. This allows
2584 // use to retrieve last_Java_pc from last_Java_sp[-1].
2585 // On 32bit we then have to push additional args on the stack to accomplish
2586 // the actual requested call. On 64bit call_VM only can use register args
2587 // so the only extra space is the return address that call_VM created.
2588 // This hopefully explains the calculations here.
2589
2590 #ifdef _LP64
2591 // We've pushed one address, correct last_Java_sp
2592 lea(rax, Address(rsp, wordSize));
2593 #else
2594 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2595 #endif // LP64
2596
2597 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2598
2599 }
2600
2601 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2602 call_VM_leaf_base(entry_point, number_of_arguments);
2603 }
2604
2605 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2606 pass_arg0(this, arg_0);
2607 call_VM_leaf(entry_point, 1);
2608 }
2609
2610 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2611
2612 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2613 pass_arg1(this, arg_1);
2614 pass_arg0(this, arg_0);
2615 call_VM_leaf(entry_point, 2);
2616 }
2617
2618 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2619 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2620 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2621 pass_arg2(this, arg_2);
2622 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2623 pass_arg1(this, arg_1);
2624 pass_arg0(this, arg_0);
2625 call_VM_leaf(entry_point, 3);
2626 }
2627
2628 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2629 pass_arg0(this, arg_0);
2630 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2631 }
2632
2633 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2634
2635 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2636 pass_arg1(this, arg_1);
2637 pass_arg0(this, arg_0);
2638 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2639 }
2640
2641 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2642 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2643 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2644 pass_arg2(this, arg_2);
2645 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2646 pass_arg1(this, arg_1);
2647 pass_arg0(this, arg_0);
2648 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2649 }
2650
2651 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2652 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2653 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2654 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2655 pass_arg3(this, arg_3);
2656 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2657 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2658 pass_arg2(this, arg_2);
2659 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2660 pass_arg1(this, arg_1);
2661 pass_arg0(this, arg_0);
2662 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2663 }
2664
2665 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2666 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2667 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2668 verify_oop(oop_result, "broken oop in call_VM_base");
2669 }
2670
2671 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2672 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2673 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2674 }
2675
2676 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2677 }
2678
2679 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2680 }
2681
2682 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2683 if (reachable(src1)) {
2684 cmpl(as_Address(src1), imm);
2685 } else {
2686 lea(rscratch1, src1);
2687 cmpl(Address(rscratch1, 0), imm);
2688 }
2689 }
2690
2691 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2692 assert(!src2.is_lval(), "use cmpptr");
2693 if (reachable(src2)) {
2694 cmpl(src1, as_Address(src2));
2695 } else {
2696 lea(rscratch1, src2);
2697 cmpl(src1, Address(rscratch1, 0));
2698 }
2699 }
2700
2701 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2702 Assembler::cmpl(src1, imm);
2703 }
2704
2705 void MacroAssembler::cmp32(Register src1, Address src2) {
2706 Assembler::cmpl(src1, src2);
2707 }
2708
2709 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2710 ucomisd(opr1, opr2);
2711
2712 Label L;
2713 if (unordered_is_less) {
2714 movl(dst, -1);
2715 jcc(Assembler::parity, L);
2716 jcc(Assembler::below , L);
2717 movl(dst, 0);
2718 jcc(Assembler::equal , L);
2719 increment(dst);
2720 } else { // unordered is greater
2721 movl(dst, 1);
2722 jcc(Assembler::parity, L);
2723 jcc(Assembler::above , L);
2724 movl(dst, 0);
2725 jcc(Assembler::equal , L);
2726 decrementl(dst);
2727 }
2728 bind(L);
2729 }
2730
2731 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2732 ucomiss(opr1, opr2);
2733
2734 Label L;
2735 if (unordered_is_less) {
2736 movl(dst, -1);
2737 jcc(Assembler::parity, L);
2738 jcc(Assembler::below , L);
2739 movl(dst, 0);
2740 jcc(Assembler::equal , L);
2741 increment(dst);
2742 } else { // unordered is greater
2743 movl(dst, 1);
2744 jcc(Assembler::parity, L);
2745 jcc(Assembler::above , L);
2746 movl(dst, 0);
2747 jcc(Assembler::equal , L);
2748 decrementl(dst);
2749 }
2750 bind(L);
2751 }
2752
2753
2754 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2755 if (reachable(src1)) {
2756 cmpb(as_Address(src1), imm);
2757 } else {
2758 lea(rscratch1, src1);
2759 cmpb(Address(rscratch1, 0), imm);
2760 }
2761 }
2762
2763 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2764 #ifdef _LP64
2765 if (src2.is_lval()) {
2766 movptr(rscratch1, src2);
2767 Assembler::cmpq(src1, rscratch1);
2768 } else if (reachable(src2)) {
2769 cmpq(src1, as_Address(src2));
2770 } else {
2771 lea(rscratch1, src2);
2772 Assembler::cmpq(src1, Address(rscratch1, 0));
2773 }
2774 #else
2775 if (src2.is_lval()) {
2776 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2777 } else {
2778 cmpl(src1, as_Address(src2));
2779 }
2780 #endif // _LP64
2781 }
2782
2783 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2784 assert(src2.is_lval(), "not a mem-mem compare");
2785 #ifdef _LP64
2786 // moves src2's literal address
2787 movptr(rscratch1, src2);
2788 Assembler::cmpq(src1, rscratch1);
2789 #else
2790 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2791 #endif // _LP64
2792 }
2793
2794 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2795 if (reachable(adr)) {
2796 if (os::is_MP())
2797 lock();
2798 cmpxchgptr(reg, as_Address(adr));
2799 } else {
2800 lea(rscratch1, adr);
2801 if (os::is_MP())
2802 lock();
2803 cmpxchgptr(reg, Address(rscratch1, 0));
2804 }
2805 }
2806
2807 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2808 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2809 }
2810
2811 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2812 if (reachable(src)) {
2813 Assembler::comisd(dst, as_Address(src));
2814 } else {
2815 lea(rscratch1, src);
2816 Assembler::comisd(dst, Address(rscratch1, 0));
2817 }
2818 }
2819
2820 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2821 if (reachable(src)) {
2822 Assembler::comiss(dst, as_Address(src));
2823 } else {
2824 lea(rscratch1, src);
2825 Assembler::comiss(dst, Address(rscratch1, 0));
2826 }
2827 }
2828
2829
2830 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2831 Condition negated_cond = negate_condition(cond);
2832 Label L;
2833 jcc(negated_cond, L);
2834 pushf(); // Preserve flags
2835 atomic_incl(counter_addr);
2836 popf();
2837 bind(L);
2838 }
2839
2840 int MacroAssembler::corrected_idivl(Register reg) {
2841 // Full implementation of Java idiv and irem; checks for
2842 // special case as described in JVM spec., p.243 & p.271.
2843 // The function returns the (pc) offset of the idivl
2844 // instruction - may be needed for implicit exceptions.
2845 //
2846 // normal case special case
2847 //
2848 // input : rax,: dividend min_int
2849 // reg: divisor (may not be rax,/rdx) -1
2850 //
2851 // output: rax,: quotient (= rax, idiv reg) min_int
2852 // rdx: remainder (= rax, irem reg) 0
2853 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2854 const int min_int = 0x80000000;
2855 Label normal_case, special_case;
2856
2857 // check for special case
2858 cmpl(rax, min_int);
2859 jcc(Assembler::notEqual, normal_case);
2860 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2861 cmpl(reg, -1);
2862 jcc(Assembler::equal, special_case);
2863
2864 // handle normal case
2865 bind(normal_case);
2866 cdql();
2867 int idivl_offset = offset();
2868 idivl(reg);
2869
2870 // normal and special case exit
2871 bind(special_case);
2872
2873 return idivl_offset;
2874 }
2875
2876
2877
2878 void MacroAssembler::decrementl(Register reg, int value) {
2879 if (value == min_jint) {subl(reg, value) ; return; }
2880 if (value < 0) { incrementl(reg, -value); return; }
2881 if (value == 0) { ; return; }
2882 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2883 /* else */ { subl(reg, value) ; return; }
2884 }
2885
2886 void MacroAssembler::decrementl(Address dst, int value) {
2887 if (value == min_jint) {subl(dst, value) ; return; }
2888 if (value < 0) { incrementl(dst, -value); return; }
2889 if (value == 0) { ; return; }
2890 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2891 /* else */ { subl(dst, value) ; return; }
2892 }
2893
2894 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2895 assert (shift_value > 0, "illegal shift value");
2896 Label _is_positive;
2897 testl (reg, reg);
2898 jcc (Assembler::positive, _is_positive);
2899 int offset = (1 << shift_value) - 1 ;
2900
2901 if (offset == 1) {
2902 incrementl(reg);
2903 } else {
2904 addl(reg, offset);
2905 }
2906
2907 bind (_is_positive);
2908 sarl(reg, shift_value);
2909 }
2910
2911 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2912 if (reachable(src)) {
2913 Assembler::divsd(dst, as_Address(src));
2914 } else {
2915 lea(rscratch1, src);
2916 Assembler::divsd(dst, Address(rscratch1, 0));
2917 }
2918 }
2919
2920 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2921 if (reachable(src)) {
2922 Assembler::divss(dst, as_Address(src));
2923 } else {
2924 lea(rscratch1, src);
2925 Assembler::divss(dst, Address(rscratch1, 0));
2926 }
2927 }
2928
2929 // !defined(COMPILER2) is because of stupid core builds
2930 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2931 void MacroAssembler::empty_FPU_stack() {
2932 if (VM_Version::supports_mmx()) {
2933 emms();
2934 } else {
2935 for (int i = 8; i-- > 0; ) ffree(i);
2936 }
2937 }
2938 #endif // !LP64 || C1 || !C2
2939
2940
2941 // Defines obj, preserves var_size_in_bytes
2942 void MacroAssembler::eden_allocate(Register obj,
2943 Register var_size_in_bytes,
2944 int con_size_in_bytes,
2945 Register t1,
2946 Label& slow_case) {
2947 assert(obj == rax, "obj must be in rax, for cmpxchg");
2948 assert_different_registers(obj, var_size_in_bytes, t1);
2949 if (!Universe::heap()->supports_inline_contig_alloc()) {
2950 jmp(slow_case);
2951 } else {
2952 Register end = t1;
2953 Label retry;
2954 bind(retry);
2955 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2956 movptr(obj, heap_top);
2957 if (var_size_in_bytes == noreg) {
2958 lea(end, Address(obj, con_size_in_bytes));
2959 } else {
2960 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2961 }
2962 // if end < obj then we wrapped around => object too long => slow case
2963 cmpptr(end, obj);
2964 jcc(Assembler::below, slow_case);
2965 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2966 jcc(Assembler::above, slow_case);
2967 // Compare obj with the top addr, and if still equal, store the new top addr in
2968 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2969 // it otherwise. Use lock prefix for atomicity on MPs.
2970 locked_cmpxchgptr(end, heap_top);
2971 jcc(Assembler::notEqual, retry);
2972 }
2973 }
2974
2975 void MacroAssembler::enter() {
2976 push(rbp);
2977 mov(rbp, rsp);
2978 }
2979
2980 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2981 void MacroAssembler::fat_nop() {
2982 if (UseAddressNop) {
2983 addr_nop_5();
2984 } else {
2985 emit_int8(0x26); // es:
2986 emit_int8(0x2e); // cs:
2987 emit_int8(0x64); // fs:
2988 emit_int8(0x65); // gs:
2989 emit_int8((unsigned char)0x90);
2990 }
2991 }
2992
2993 void MacroAssembler::fcmp(Register tmp) {
2994 fcmp(tmp, 1, true, true);
2995 }
2996
2997 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2998 assert(!pop_right || pop_left, "usage error");
2999 if (VM_Version::supports_cmov()) {
3000 assert(tmp == noreg, "unneeded temp");
3001 if (pop_left) {
3002 fucomip(index);
3003 } else {
3004 fucomi(index);
3005 }
3006 if (pop_right) {
3007 fpop();
3008 }
3009 } else {
3010 assert(tmp != noreg, "need temp");
3011 if (pop_left) {
3012 if (pop_right) {
3013 fcompp();
3014 } else {
3015 fcomp(index);
3016 }
3017 } else {
3018 fcom(index);
3019 }
3020 // convert FPU condition into eflags condition via rax,
3021 save_rax(tmp);
3022 fwait(); fnstsw_ax();
3023 sahf();
3024 restore_rax(tmp);
3025 }
3026 // condition codes set as follows:
3027 //
3028 // CF (corresponds to C0) if x < y
3029 // PF (corresponds to C2) if unordered
3030 // ZF (corresponds to C3) if x = y
3031 }
3032
3033 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3034 fcmp2int(dst, unordered_is_less, 1, true, true);
3035 }
3036
3037 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3038 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3039 Label L;
3040 if (unordered_is_less) {
3041 movl(dst, -1);
3042 jcc(Assembler::parity, L);
3043 jcc(Assembler::below , L);
3044 movl(dst, 0);
3045 jcc(Assembler::equal , L);
3046 increment(dst);
3047 } else { // unordered is greater
3048 movl(dst, 1);
3049 jcc(Assembler::parity, L);
3050 jcc(Assembler::above , L);
3051 movl(dst, 0);
3052 jcc(Assembler::equal , L);
3053 decrementl(dst);
3054 }
3055 bind(L);
3056 }
3057
3058 void MacroAssembler::fld_d(AddressLiteral src) {
3059 fld_d(as_Address(src));
3060 }
3061
3062 void MacroAssembler::fld_s(AddressLiteral src) {
3063 fld_s(as_Address(src));
3064 }
3065
3066 void MacroAssembler::fld_x(AddressLiteral src) {
3067 Assembler::fld_x(as_Address(src));
3068 }
3069
3070 void MacroAssembler::fldcw(AddressLiteral src) {
3071 Assembler::fldcw(as_Address(src));
3072 }
3073
3074 void MacroAssembler::pow_exp_core_encoding() {
3075 // kills rax, rcx, rdx
3076 subptr(rsp,sizeof(jdouble));
3077 // computes 2^X. Stack: X ...
3078 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3079 // keep it on the thread's stack to compute 2^int(X) later
3080 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3081 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3082 fld_s(0); // Stack: X X ...
3083 frndint(); // Stack: int(X) X ...
3084 fsuba(1); // Stack: int(X) X-int(X) ...
3085 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3086 f2xm1(); // Stack: 2^(X-int(X))-1 ...
3087 fld1(); // Stack: 1 2^(X-int(X))-1 ...
3088 faddp(1); // Stack: 2^(X-int(X))
3089 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3090 // shift int(X)+1023 to exponent position.
3091 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3092 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3093 // values so detect them and set result to NaN.
3094 movl(rax,Address(rsp,0));
3095 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3096 addl(rax, 1023);
3097 movl(rdx,rax);
3098 shll(rax,20);
3099 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3100 addl(rdx,1);
3101 // Check that 1 < int(X)+1023+1 < 2048
3102 // in 3 steps:
3103 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3104 // 2- (int(X)+1023+1)&-2048 != 0
3105 // 3- (int(X)+1023+1)&-2048 != 1
3106 // Do 2- first because addl just updated the flags.
3107 cmov32(Assembler::equal,rax,rcx);
3108 cmpl(rdx,1);
3109 cmov32(Assembler::equal,rax,rcx);
3110 testl(rdx,rcx);
3111 cmov32(Assembler::notEqual,rax,rcx);
3112 movl(Address(rsp,4),rax);
3113 movl(Address(rsp,0),0);
3114 fmul_d(Address(rsp,0)); // Stack: 2^X ...
3115 addptr(rsp,sizeof(jdouble));
3116 }
3117
3118 void MacroAssembler::increase_precision() {
3119 subptr(rsp, BytesPerWord);
3120 fnstcw(Address(rsp, 0));
3121 movl(rax, Address(rsp, 0));
3122 orl(rax, 0x300);
3123 push(rax);
3124 fldcw(Address(rsp, 0));
3125 pop(rax);
3126 }
3127
3128 void MacroAssembler::restore_precision() {
3129 fldcw(Address(rsp, 0));
3130 addptr(rsp, BytesPerWord);
3131 }
3132
3133 void MacroAssembler::fast_pow() {
3134 // computes X^Y = 2^(Y * log2(X))
3135 // if fast computation is not possible, result is NaN. Requires
3136 // fallback from user of this macro.
3137 // increase precision for intermediate steps of the computation
3138 BLOCK_COMMENT("fast_pow {");
3139 increase_precision();
3140 fyl2x(); // Stack: (Y*log2(X)) ...
3141 pow_exp_core_encoding(); // Stack: exp(X) ...
3142 restore_precision();
3143 BLOCK_COMMENT("} fast_pow");
3144 }
3145
3146 void MacroAssembler::fast_exp() {
3147 // computes exp(X) = 2^(X * log2(e))
3148 // if fast computation is not possible, result is NaN. Requires
3149 // fallback from user of this macro.
3150 // increase precision for intermediate steps of the computation
3151 increase_precision();
3152 fldl2e(); // Stack: log2(e) X ...
3153 fmulp(1); // Stack: (X*log2(e)) ...
3154 pow_exp_core_encoding(); // Stack: exp(X) ...
3155 restore_precision();
3156 }
3157
3158 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
3159 // kills rax, rcx, rdx
3160 // pow and exp needs 2 extra registers on the fpu stack.
3161 Label slow_case, done;
3162 Register tmp = noreg;
3163 if (!VM_Version::supports_cmov()) {
3164 // fcmp needs a temporary so preserve rdx,
3165 tmp = rdx;
3166 }
3167 Register tmp2 = rax;
3168 Register tmp3 = rcx;
3169
3170 if (is_exp) {
3171 // Stack: X
3172 fld_s(0); // duplicate argument for runtime call. Stack: X X
3173 fast_exp(); // Stack: exp(X) X
3174 fcmp(tmp, 0, false, false); // Stack: exp(X) X
3175 // exp(X) not equal to itself: exp(X) is NaN go to slow case.
3176 jcc(Assembler::parity, slow_case);
3177 // get rid of duplicate argument. Stack: exp(X)
3178 if (num_fpu_regs_in_use > 0) {
3179 fxch();
3180 fpop();
3181 } else {
3182 ffree(1);
3183 }
3184 jmp(done);
3185 } else {
3186 // Stack: X Y
3187 Label x_negative, y_not_2;
3188
3189 static double two = 2.0;
3190 ExternalAddress two_addr((address)&two);
3191
3192 fld_d(two_addr); // Stack: 2 X Y
3193 fcmp(tmp, 2, true, false); // Stack: X Y
3194 jcc(Assembler::parity, y_not_2);
3195 jcc(Assembler::notEqual, y_not_2);
3196
3197 fxch(); fpop(); // Stack: X
3198 fmul(0); // Stack: X*X
3199
3200 jmp(done);
3201
3202 bind(y_not_2);
3203
3204 fldz(); // Stack: 0 X Y
3205 fcmp(tmp, 1, true, false); // Stack: X Y
3206 jcc(Assembler::above, x_negative);
3207
3208 // X >= 0
3209
3210 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3211 fld_s(1); // Stack: X Y X Y
3212 fast_pow(); // Stack: X^Y X Y
3213 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3214 // X^Y not equal to itself: X^Y is NaN go to slow case.
3215 jcc(Assembler::parity, slow_case);
3216 // get rid of duplicate arguments. Stack: X^Y
3217 if (num_fpu_regs_in_use > 0) {
3218 fxch(); fpop();
3219 fxch(); fpop();
3220 } else {
3221 ffree(2);
3222 ffree(1);
3223 }
3224 jmp(done);
3225
3226 // X <= 0
3227 bind(x_negative);
3228
3229 fld_s(1); // Stack: Y X Y
3230 frndint(); // Stack: int(Y) X Y
3231 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3232 jcc(Assembler::notEqual, slow_case);
3233
3234 subptr(rsp, 8);
3235
3236 // For X^Y, when X < 0, Y has to be an integer and the final
3237 // result depends on whether it's odd or even. We just checked
3238 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
3239 // integer to test its parity. If int(Y) is huge and doesn't fit
3240 // in the 64 bit integer range, the integer indefinite value will
3241 // end up in the gp registers. Huge numbers are all even, the
3242 // integer indefinite number is even so it's fine.
3243
3244 #ifdef ASSERT
3245 // Let's check we don't end up with an integer indefinite number
3246 // when not expected. First test for huge numbers: check whether
3247 // int(Y)+1 == int(Y) which is true for very large numbers and
3248 // those are all even. A 64 bit integer is guaranteed to not
3249 // overflow for numbers where y+1 != y (when precision is set to
3250 // double precision).
3251 Label y_not_huge;
3252
3253 fld1(); // Stack: 1 int(Y) X Y
3254 fadd(1); // Stack: 1+int(Y) int(Y) X Y
3255
3256 #ifdef _LP64
3257 // trip to memory to force the precision down from double extended
3258 // precision
3259 fstp_d(Address(rsp, 0));
3260 fld_d(Address(rsp, 0));
3261 #endif
3262
3263 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
3264 #endif
3265
3266 // move int(Y) as 64 bit integer to thread's stack
3267 fistp_d(Address(rsp,0)); // Stack: X Y
3268
3269 #ifdef ASSERT
3270 jcc(Assembler::notEqual, y_not_huge);
3271
3272 // Y is huge so we know it's even. It may not fit in a 64 bit
3273 // integer and we don't want the debug code below to see the
3274 // integer indefinite value so overwrite int(Y) on the thread's
3275 // stack with 0.
3276 movl(Address(rsp, 0), 0);
3277 movl(Address(rsp, 4), 0);
3278
3279 bind(y_not_huge);
3280 #endif
3281
3282 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3283 fld_s(1); // Stack: X Y X Y
3284 fabs(); // Stack: abs(X) Y X Y
3285 fast_pow(); // Stack: abs(X)^Y X Y
3286 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3287 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3288
3289 pop(tmp2);
3290 NOT_LP64(pop(tmp3));
3291 jcc(Assembler::parity, slow_case);
3292
3293 #ifdef ASSERT
3294 // Check that int(Y) is not integer indefinite value (int
3295 // overflow). Shouldn't happen because for values that would
3296 // overflow, 1+int(Y)==Y which was tested earlier.
3297 #ifndef _LP64
3298 {
3299 Label integer;
3300 testl(tmp2, tmp2);
3301 jcc(Assembler::notZero, integer);
3302 cmpl(tmp3, 0x80000000);
3303 jcc(Assembler::notZero, integer);
3304 STOP("integer indefinite value shouldn't be seen here");
3305 bind(integer);
3306 }
3307 #else
3308 {
3309 Label integer;
3310 mov(tmp3, tmp2); // preserve tmp2 for parity check below
3311 shlq(tmp3, 1);
3312 jcc(Assembler::carryClear, integer);
3313 jcc(Assembler::notZero, integer);
3314 STOP("integer indefinite value shouldn't be seen here");
3315 bind(integer);
3316 }
3317 #endif
3318 #endif
3319
3320 // get rid of duplicate arguments. Stack: X^Y
3321 if (num_fpu_regs_in_use > 0) {
3322 fxch(); fpop();
3323 fxch(); fpop();
3324 } else {
3325 ffree(2);
3326 ffree(1);
3327 }
3328
3329 testl(tmp2, 1);
3330 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3331 // X <= 0, Y even: X^Y = -abs(X)^Y
3332
3333 fchs(); // Stack: -abs(X)^Y Y
3334 jmp(done);
3335 }
3336
3337 // slow case: runtime call
3338 bind(slow_case);
3339
3340 fpop(); // pop incorrect result or int(Y)
3341
3342 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
3343 is_exp ? 1 : 2, num_fpu_regs_in_use);
3344
3345 // Come here with result in F-TOS
3346 bind(done);
3347 }
3348
3349 void MacroAssembler::fpop() {
3350 ffree();
3351 fincstp();
3352 }
3353
3354 void MacroAssembler::fremr(Register tmp) {
3355 save_rax(tmp);
3356 { Label L;
3357 bind(L);
3358 fprem();
3359 fwait(); fnstsw_ax();
3360 #ifdef _LP64
3361 testl(rax, 0x400);
3362 jcc(Assembler::notEqual, L);
3363 #else
3364 sahf();
3365 jcc(Assembler::parity, L);
3366 #endif // _LP64
3367 }
3368 restore_rax(tmp);
3369 // Result is in ST0.
3370 // Note: fxch & fpop to get rid of ST1
3371 // (otherwise FPU stack could overflow eventually)
3372 fxch(1);
3373 fpop();
3374 }
3375
3376
3377 void MacroAssembler::incrementl(AddressLiteral dst) {
3378 if (reachable(dst)) {
3379 incrementl(as_Address(dst));
3380 } else {
3381 lea(rscratch1, dst);
3382 incrementl(Address(rscratch1, 0));
3383 }
3384 }
3385
3386 void MacroAssembler::incrementl(ArrayAddress dst) {
3387 incrementl(as_Address(dst));
3388 }
3389
3390 void MacroAssembler::incrementl(Register reg, int value) {
3391 if (value == min_jint) {addl(reg, value) ; return; }
3392 if (value < 0) { decrementl(reg, -value); return; }
3393 if (value == 0) { ; return; }
3394 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3395 /* else */ { addl(reg, value) ; return; }
3396 }
3397
3398 void MacroAssembler::incrementl(Address dst, int value) {
3399 if (value == min_jint) {addl(dst, value) ; return; }
3400 if (value < 0) { decrementl(dst, -value); return; }
3401 if (value == 0) { ; return; }
3402 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3403 /* else */ { addl(dst, value) ; return; }
3404 }
3405
3406 void MacroAssembler::jump(AddressLiteral dst) {
3407 if (reachable(dst)) {
3408 jmp_literal(dst.target(), dst.rspec());
3409 } else {
3410 lea(rscratch1, dst);
3411 jmp(rscratch1);
3412 }
3413 }
3414
3415 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3416 if (reachable(dst)) {
3417 InstructionMark im(this);
3418 relocate(dst.reloc());
3419 const int short_size = 2;
3420 const int long_size = 6;
3421 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3422 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3423 // 0111 tttn #8-bit disp
3424 emit_int8(0x70 | cc);
3425 emit_int8((offs - short_size) & 0xFF);
3426 } else {
3427 // 0000 1111 1000 tttn #32-bit disp
3428 emit_int8(0x0F);
3429 emit_int8((unsigned char)(0x80 | cc));
3430 emit_int32(offs - long_size);
3431 }
3432 } else {
3433 #ifdef ASSERT
3434 warning("reversing conditional branch");
3435 #endif /* ASSERT */
3436 Label skip;
3437 jccb(reverse[cc], skip);
3438 lea(rscratch1, dst);
3439 Assembler::jmp(rscratch1);
3440 bind(skip);
3441 }
3442 }
3443
3444 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3445 if (reachable(src)) {
3446 Assembler::ldmxcsr(as_Address(src));
3447 } else {
3448 lea(rscratch1, src);
3449 Assembler::ldmxcsr(Address(rscratch1, 0));
3450 }
3451 }
3452
3453 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3454 int off;
3455 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3456 off = offset();
3457 movsbl(dst, src); // movsxb
3458 } else {
3459 off = load_unsigned_byte(dst, src);
3460 shll(dst, 24);
3461 sarl(dst, 24);
3462 }
3463 return off;
3464 }
3465
3466 // Note: load_signed_short used to be called load_signed_word.
3467 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3468 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3469 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3470 int MacroAssembler::load_signed_short(Register dst, Address src) {
3471 int off;
3472 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3473 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3474 // version but this is what 64bit has always done. This seems to imply
3475 // that users are only using 32bits worth.
3476 off = offset();
3477 movswl(dst, src); // movsxw
3478 } else {
3479 off = load_unsigned_short(dst, src);
3480 shll(dst, 16);
3481 sarl(dst, 16);
3482 }
3483 return off;
3484 }
3485
3486 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3487 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3488 // and "3.9 Partial Register Penalties", p. 22).
3489 int off;
3490 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3491 off = offset();
3492 movzbl(dst, src); // movzxb
3493 } else {
3494 xorl(dst, dst);
3495 off = offset();
3496 movb(dst, src);
3497 }
3498 return off;
3499 }
3500
3501 // Note: load_unsigned_short used to be called load_unsigned_word.
3502 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3503 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3504 // and "3.9 Partial Register Penalties", p. 22).
3505 int off;
3506 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3507 off = offset();
3508 movzwl(dst, src); // movzxw
3509 } else {
3510 xorl(dst, dst);
3511 off = offset();
3512 movw(dst, src);
3513 }
3514 return off;
3515 }
3516
3517 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3518 switch (size_in_bytes) {
3519 #ifndef _LP64
3520 case 8:
3521 assert(dst2 != noreg, "second dest register required");
3522 movl(dst, src);
3523 movl(dst2, src.plus_disp(BytesPerInt));
3524 break;
3525 #else
3526 case 8: movq(dst, src); break;
3527 #endif
3528 case 4: movl(dst, src); break;
3529 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3530 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3531 default: ShouldNotReachHere();
3532 }
3533 }
3534
3535 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3536 switch (size_in_bytes) {
3537 #ifndef _LP64
3538 case 8:
3539 assert(src2 != noreg, "second source register required");
3540 movl(dst, src);
3541 movl(dst.plus_disp(BytesPerInt), src2);
3542 break;
3543 #else
3544 case 8: movq(dst, src); break;
3545 #endif
3546 case 4: movl(dst, src); break;
3547 case 2: movw(dst, src); break;
3548 case 1: movb(dst, src); break;
3549 default: ShouldNotReachHere();
3550 }
3551 }
3552
3553 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3554 if (reachable(dst)) {
3555 movl(as_Address(dst), src);
3556 } else {
3557 lea(rscratch1, dst);
3558 movl(Address(rscratch1, 0), src);
3559 }
3560 }
3561
3562 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3563 if (reachable(src)) {
3564 movl(dst, as_Address(src));
3565 } else {
3566 lea(rscratch1, src);
3567 movl(dst, Address(rscratch1, 0));
3568 }
3569 }
3570
3571 // C++ bool manipulation
3572
3573 void MacroAssembler::movbool(Register dst, Address src) {
3574 if(sizeof(bool) == 1)
3575 movb(dst, src);
3576 else if(sizeof(bool) == 2)
3577 movw(dst, src);
3578 else if(sizeof(bool) == 4)
3579 movl(dst, src);
3580 else
3581 // unsupported
3582 ShouldNotReachHere();
3583 }
3584
3585 void MacroAssembler::movbool(Address dst, bool boolconst) {
3586 if(sizeof(bool) == 1)
3587 movb(dst, (int) boolconst);
3588 else if(sizeof(bool) == 2)
3589 movw(dst, (int) boolconst);
3590 else if(sizeof(bool) == 4)
3591 movl(dst, (int) boolconst);
3592 else
3593 // unsupported
3594 ShouldNotReachHere();
3595 }
3596
3597 void MacroAssembler::movbool(Address dst, Register src) {
3598 if(sizeof(bool) == 1)
3599 movb(dst, src);
3600 else if(sizeof(bool) == 2)
3601 movw(dst, src);
3602 else if(sizeof(bool) == 4)
3603 movl(dst, src);
3604 else
3605 // unsupported
3606 ShouldNotReachHere();
3607 }
3608
3609 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3610 movb(as_Address(dst), src);
3611 }
3612
3613 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3614 if (reachable(src)) {
3615 movdl(dst, as_Address(src));
3616 } else {
3617 lea(rscratch1, src);
3618 movdl(dst, Address(rscratch1, 0));
3619 }
3620 }
3621
3622 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3623 if (reachable(src)) {
3624 movq(dst, as_Address(src));
3625 } else {
3626 lea(rscratch1, src);
3627 movq(dst, Address(rscratch1, 0));
3628 }
3629 }
3630
3631 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3632 if (reachable(src)) {
3633 if (UseXmmLoadAndClearUpper) {
3634 movsd (dst, as_Address(src));
3635 } else {
3636 movlpd(dst, as_Address(src));
3637 }
3638 } else {
3639 lea(rscratch1, src);
3640 if (UseXmmLoadAndClearUpper) {
3641 movsd (dst, Address(rscratch1, 0));
3642 } else {
3643 movlpd(dst, Address(rscratch1, 0));
3644 }
3645 }
3646 }
3647
3648 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3649 if (reachable(src)) {
3650 movss(dst, as_Address(src));
3651 } else {
3652 lea(rscratch1, src);
3653 movss(dst, Address(rscratch1, 0));
3654 }
3655 }
3656
3657 void MacroAssembler::movptr(Register dst, Register src) {
3658 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3659 }
3660
3661 void MacroAssembler::movptr(Register dst, Address src) {
3662 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3663 }
3664
3665 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3666 void MacroAssembler::movptr(Register dst, intptr_t src) {
3667 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3668 }
3669
3670 void MacroAssembler::movptr(Address dst, Register src) {
3671 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3672 }
3673
3674 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3675 if (reachable(src)) {
3676 Assembler::movdqu(dst, as_Address(src));
3677 } else {
3678 lea(rscratch1, src);
3679 Assembler::movdqu(dst, Address(rscratch1, 0));
3680 }
3681 }
3682
3683 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3684 if (reachable(src)) {
3685 Assembler::movdqa(dst, as_Address(src));
3686 } else {
3687 lea(rscratch1, src);
3688 Assembler::movdqa(dst, Address(rscratch1, 0));
3689 }
3690 }
3691
3692 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3693 if (reachable(src)) {
3694 Assembler::movsd(dst, as_Address(src));
3695 } else {
3696 lea(rscratch1, src);
3697 Assembler::movsd(dst, Address(rscratch1, 0));
3698 }
3699 }
3700
3701 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3702 if (reachable(src)) {
3703 Assembler::movss(dst, as_Address(src));
3704 } else {
3705 lea(rscratch1, src);
3706 Assembler::movss(dst, Address(rscratch1, 0));
3707 }
3708 }
3709
3710 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3711 if (reachable(src)) {
3712 Assembler::mulsd(dst, as_Address(src));
3713 } else {
3714 lea(rscratch1, src);
3715 Assembler::mulsd(dst, Address(rscratch1, 0));
3716 }
3717 }
3718
3719 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3720 if (reachable(src)) {
3721 Assembler::mulss(dst, as_Address(src));
3722 } else {
3723 lea(rscratch1, src);
3724 Assembler::mulss(dst, Address(rscratch1, 0));
3725 }
3726 }
3727
3728 void MacroAssembler::null_check(Register reg, int offset) {
3729 if (needs_explicit_null_check(offset)) {
3730 // provoke OS NULL exception if reg = NULL by
3731 // accessing M[reg] w/o changing any (non-CC) registers
3732 // NOTE: cmpl is plenty here to provoke a segv
3733 cmpptr(rax, Address(reg, 0));
3734 // Note: should probably use testl(rax, Address(reg, 0));
3735 // may be shorter code (however, this version of
3736 // testl needs to be implemented first)
3737 } else {
3738 // nothing to do, (later) access of M[reg + offset]
3739 // will provoke OS NULL exception if reg = NULL
3740 }
3741 }
3742
3743 void MacroAssembler::os_breakpoint() {
3744 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3745 // (e.g., MSVC can't call ps() otherwise)
3746 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3747 }
3748
3749 void MacroAssembler::pop_CPU_state() {
3750 pop_FPU_state();
3751 pop_IU_state();
3752 }
3753
3754 void MacroAssembler::pop_FPU_state() {
3755 NOT_LP64(frstor(Address(rsp, 0));)
3756 LP64_ONLY(fxrstor(Address(rsp, 0));)
3757 addptr(rsp, FPUStateSizeInWords * wordSize);
3758 }
3759
3760 void MacroAssembler::pop_IU_state() {
3761 popa();
3762 LP64_ONLY(addq(rsp, 8));
3763 popf();
3764 }
3765
3766 // Save Integer and Float state
3767 // Warning: Stack must be 16 byte aligned (64bit)
3768 void MacroAssembler::push_CPU_state() {
3769 push_IU_state();
3770 push_FPU_state();
3771 }
3772
3773 void MacroAssembler::push_FPU_state() {
3774 subptr(rsp, FPUStateSizeInWords * wordSize);
3775 #ifndef _LP64
3776 fnsave(Address(rsp, 0));
3777 fwait();
3778 #else
3779 fxsave(Address(rsp, 0));
3780 #endif // LP64
3781 }
3782
3783 void MacroAssembler::push_IU_state() {
3784 // Push flags first because pusha kills them
3785 pushf();
3786 // Make sure rsp stays 16-byte aligned
3787 LP64_ONLY(subq(rsp, 8));
3788 pusha();
3789 }
3790
3791 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3792 // determine java_thread register
3793 if (!java_thread->is_valid()) {
3794 java_thread = rdi;
3795 get_thread(java_thread);
3796 }
3797 // we must set sp to zero to clear frame
3798 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3799 if (clear_fp) {
3800 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3801 }
3802
3803 if (clear_pc)
3804 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3805
3806 }
3807
3808 void MacroAssembler::restore_rax(Register tmp) {
3809 if (tmp == noreg) pop(rax);
3810 else if (tmp != rax) mov(rax, tmp);
3811 }
3812
3813 void MacroAssembler::round_to(Register reg, int modulus) {
3814 addptr(reg, modulus - 1);
3815 andptr(reg, -modulus);
3816 }
3817
3818 void MacroAssembler::save_rax(Register tmp) {
3819 if (tmp == noreg) push(rax);
3820 else if (tmp != rax) mov(tmp, rax);
3821 }
3822
3823 // Write serialization page so VM thread can do a pseudo remote membar.
3824 // We use the current thread pointer to calculate a thread specific
3825 // offset to write to within the page. This minimizes bus traffic
3826 // due to cache line collision.
3827 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3828 movl(tmp, thread);
3829 shrl(tmp, os::get_serialize_page_shift_count());
3830 andl(tmp, (os::vm_page_size() - sizeof(int)));
3831
3832 Address index(noreg, tmp, Address::times_1);
3833 ExternalAddress page(os::get_memory_serialize_page());
3834
3835 // Size of store must match masking code above
3836 movl(as_Address(ArrayAddress(page, index)), tmp);
3837 }
3838
3839 // Calls to C land
3840 //
3841 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3842 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3843 // has to be reset to 0. This is required to allow proper stack traversal.
3844 void MacroAssembler::set_last_Java_frame(Register java_thread,
3845 Register last_java_sp,
3846 Register last_java_fp,
3847 address last_java_pc) {
3848 // determine java_thread register
3849 if (!java_thread->is_valid()) {
3850 java_thread = rdi;
3851 get_thread(java_thread);
3852 }
3853 // determine last_java_sp register
3854 if (!last_java_sp->is_valid()) {
3855 last_java_sp = rsp;
3856 }
3857
3858 // last_java_fp is optional
3859
3860 if (last_java_fp->is_valid()) {
3861 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3862 }
3863
3864 // last_java_pc is optional
3865
3866 if (last_java_pc != NULL) {
3867 lea(Address(java_thread,
3868 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3869 InternalAddress(last_java_pc));
3870
3871 }
3872 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3873 }
3874
3875 void MacroAssembler::shlptr(Register dst, int imm8) {
3876 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3877 }
3878
3879 void MacroAssembler::shrptr(Register dst, int imm8) {
3880 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3881 }
3882
3883 void MacroAssembler::sign_extend_byte(Register reg) {
3884 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3885 movsbl(reg, reg); // movsxb
3886 } else {
3887 shll(reg, 24);
3888 sarl(reg, 24);
3889 }
3890 }
3891
3892 void MacroAssembler::sign_extend_short(Register reg) {
3893 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3894 movswl(reg, reg); // movsxw
3895 } else {
3896 shll(reg, 16);
3897 sarl(reg, 16);
3898 }
3899 }
3900
3901 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3902 assert(reachable(src), "Address should be reachable");
3903 testl(dst, as_Address(src));
3904 }
3905
3906 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3907 if (reachable(src)) {
3908 Assembler::sqrtsd(dst, as_Address(src));
3909 } else {
3910 lea(rscratch1, src);
3911 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3912 }
3913 }
3914
3915 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3916 if (reachable(src)) {
3917 Assembler::sqrtss(dst, as_Address(src));
3918 } else {
3919 lea(rscratch1, src);
3920 Assembler::sqrtss(dst, Address(rscratch1, 0));
3921 }
3922 }
3923
3924 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3925 if (reachable(src)) {
3926 Assembler::subsd(dst, as_Address(src));
3927 } else {
3928 lea(rscratch1, src);
3929 Assembler::subsd(dst, Address(rscratch1, 0));
3930 }
3931 }
3932
3933 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3934 if (reachable(src)) {
3935 Assembler::subss(dst, as_Address(src));
3936 } else {
3937 lea(rscratch1, src);
3938 Assembler::subss(dst, Address(rscratch1, 0));
3939 }
3940 }
3941
3942 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3943 if (reachable(src)) {
3944 Assembler::ucomisd(dst, as_Address(src));
3945 } else {
3946 lea(rscratch1, src);
3947 Assembler::ucomisd(dst, Address(rscratch1, 0));
3948 }
3949 }
3950
3951 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3952 if (reachable(src)) {
3953 Assembler::ucomiss(dst, as_Address(src));
3954 } else {
3955 lea(rscratch1, src);
3956 Assembler::ucomiss(dst, Address(rscratch1, 0));
3957 }
3958 }
3959
3960 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3961 // Used in sign-bit flipping with aligned address.
3962 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3963 if (reachable(src)) {
3964 Assembler::xorpd(dst, as_Address(src));
3965 } else {
3966 lea(rscratch1, src);
3967 Assembler::xorpd(dst, Address(rscratch1, 0));
3968 }
3969 }
3970
3971 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3972 // Used in sign-bit flipping with aligned address.
3973 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3974 if (reachable(src)) {
3975 Assembler::xorps(dst, as_Address(src));
3976 } else {
3977 lea(rscratch1, src);
3978 Assembler::xorps(dst, Address(rscratch1, 0));
3979 }
3980 }
3981
3982 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3983 // Used in sign-bit flipping with aligned address.
3984 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3985 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3986 if (reachable(src)) {
3987 Assembler::pshufb(dst, as_Address(src));
3988 } else {
3989 lea(rscratch1, src);
3990 Assembler::pshufb(dst, Address(rscratch1, 0));
3991 }
3992 }
3993
3994 // AVX 3-operands instructions
3995
3996 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3997 if (reachable(src)) {
3998 vaddsd(dst, nds, as_Address(src));
3999 } else {
4000 lea(rscratch1, src);
4001 vaddsd(dst, nds, Address(rscratch1, 0));
4002 }
4003 }
4004
4005 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4006 if (reachable(src)) {
4007 vaddss(dst, nds, as_Address(src));
4008 } else {
4009 lea(rscratch1, src);
4010 vaddss(dst, nds, Address(rscratch1, 0));
4011 }
4012 }
4013
4014 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4015 if (reachable(src)) {
4016 vandpd(dst, nds, as_Address(src), vector256);
4017 } else {
4018 lea(rscratch1, src);
4019 vandpd(dst, nds, Address(rscratch1, 0), vector256);
4020 }
4021 }
4022
4023 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4024 if (reachable(src)) {
4025 vandps(dst, nds, as_Address(src), vector256);
4026 } else {
4027 lea(rscratch1, src);
4028 vandps(dst, nds, Address(rscratch1, 0), vector256);
4029 }
4030 }
4031
4032 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4033 if (reachable(src)) {
4034 vdivsd(dst, nds, as_Address(src));
4035 } else {
4036 lea(rscratch1, src);
4037 vdivsd(dst, nds, Address(rscratch1, 0));
4038 }
4039 }
4040
4041 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4042 if (reachable(src)) {
4043 vdivss(dst, nds, as_Address(src));
4044 } else {
4045 lea(rscratch1, src);
4046 vdivss(dst, nds, Address(rscratch1, 0));
4047 }
4048 }
4049
4050 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4051 if (reachable(src)) {
4052 vmulsd(dst, nds, as_Address(src));
4053 } else {
4054 lea(rscratch1, src);
4055 vmulsd(dst, nds, Address(rscratch1, 0));
4056 }
4057 }
4058
4059 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4060 if (reachable(src)) {
4061 vmulss(dst, nds, as_Address(src));
4062 } else {
4063 lea(rscratch1, src);
4064 vmulss(dst, nds, Address(rscratch1, 0));
4065 }
4066 }
4067
4068 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4069 if (reachable(src)) {
4070 vsubsd(dst, nds, as_Address(src));
4071 } else {
4072 lea(rscratch1, src);
4073 vsubsd(dst, nds, Address(rscratch1, 0));
4074 }
4075 }
4076
4077 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4078 if (reachable(src)) {
4079 vsubss(dst, nds, as_Address(src));
4080 } else {
4081 lea(rscratch1, src);
4082 vsubss(dst, nds, Address(rscratch1, 0));
4083 }
4084 }
4085
4086 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4087 if (reachable(src)) {
4088 vxorpd(dst, nds, as_Address(src), vector256);
4089 } else {
4090 lea(rscratch1, src);
4091 vxorpd(dst, nds, Address(rscratch1, 0), vector256);
4092 }
4093 }
4094
4095 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4096 if (reachable(src)) {
4097 vxorps(dst, nds, as_Address(src), vector256);
4098 } else {
4099 lea(rscratch1, src);
4100 vxorps(dst, nds, Address(rscratch1, 0), vector256);
4101 }
4102 }
4103
4104
4105 //////////////////////////////////////////////////////////////////////////////////
4106 #if INCLUDE_ALL_GCS
4107
4108 void MacroAssembler::g1_write_barrier_pre(Register obj,
4109 Register pre_val,
4110 Register thread,
4111 Register tmp,
4112 bool tosca_live,
4113 bool expand_call) {
4114
4115 // If expand_call is true then we expand the call_VM_leaf macro
4116 // directly to skip generating the check by
4117 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4118
4119 #ifdef _LP64
4120 assert(thread == r15_thread, "must be");
4121 #endif // _LP64
4122
4123 Label done;
4124 Label runtime;
4125
4126 assert(pre_val != noreg, "check this code");
4127
4128 if (obj != noreg) {
4129 assert_different_registers(obj, pre_val, tmp);
4130 assert(pre_val != rax, "check this code");
4131 }
4132
4133 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4134 PtrQueue::byte_offset_of_active()));
4135 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4136 PtrQueue::byte_offset_of_index()));
4137 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4138 PtrQueue::byte_offset_of_buf()));
4139
4140
4141 // Is marking active?
4142 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4143 cmpl(in_progress, 0);
4144 } else {
4145 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4146 cmpb(in_progress, 0);
4147 }
4148 jcc(Assembler::equal, done);
4149
4150 // Do we need to load the previous value?
4151 if (obj != noreg) {
4152 load_heap_oop(pre_val, Address(obj, 0));
4153 }
4154
4155 // Is the previous value null?
4156 cmpptr(pre_val, (int32_t) NULL_WORD);
4157 jcc(Assembler::equal, done);
4158
4159 // Can we store original value in the thread's buffer?
4160 // Is index == 0?
4161 // (The index field is typed as size_t.)
4162
4163 movptr(tmp, index); // tmp := *index_adr
4164 cmpptr(tmp, 0); // tmp == 0?
4165 jcc(Assembler::equal, runtime); // If yes, goto runtime
4166
4167 subptr(tmp, wordSize); // tmp := tmp - wordSize
4168 movptr(index, tmp); // *index_adr := tmp
4169 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
4170
4171 // Record the previous value
4172 movptr(Address(tmp, 0), pre_val);
4173 jmp(done);
4174
4175 bind(runtime);
4176 // save the live input values
4177 if(tosca_live) push(rax);
4178
4179 if (obj != noreg && obj != rax)
4180 push(obj);
4181
4182 if (pre_val != rax)
4183 push(pre_val);
4184
4185 // Calling the runtime using the regular call_VM_leaf mechanism generates
4186 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4187 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4188 //
4189 // If we care generating the pre-barrier without a frame (e.g. in the
4190 // intrinsified Reference.get() routine) then ebp might be pointing to
4191 // the caller frame and so this check will most likely fail at runtime.
4192 //
4193 // Expanding the call directly bypasses the generation of the check.
4194 // So when we do not have have a full interpreter frame on the stack
4195 // expand_call should be passed true.
4196
4197 NOT_LP64( push(thread); )
4198
4199 if (expand_call) {
4200 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4201 pass_arg1(this, thread);
4202 pass_arg0(this, pre_val);
4203 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4204 } else {
4205 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4206 }
4207
4208 NOT_LP64( pop(thread); )
4209
4210 // save the live input values
4211 if (pre_val != rax)
4212 pop(pre_val);
4213
4214 if (obj != noreg && obj != rax)
4215 pop(obj);
4216
4217 if(tosca_live) pop(rax);
4218
4219 bind(done);
4220 }
4221
4222 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4223 Register new_val,
4224 Register thread,
4225 Register tmp,
4226 Register tmp2) {
4227 #ifdef _LP64
4228 assert(thread == r15_thread, "must be");
4229 #endif // _LP64
4230
4231 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4232 PtrQueue::byte_offset_of_index()));
4233 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4234 PtrQueue::byte_offset_of_buf()));
4235
4236 BarrierSet* bs = Universe::heap()->barrier_set();
4237 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4238 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4239
4240 Label done;
4241 Label runtime;
4242
4243 // Does store cross heap regions?
4244
4245 movptr(tmp, store_addr);
4246 xorptr(tmp, new_val);
4247 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4248 jcc(Assembler::equal, done);
4249
4250 // crosses regions, storing NULL?
4251
4252 cmpptr(new_val, (int32_t) NULL_WORD);
4253 jcc(Assembler::equal, done);
4254
4255 // storing region crossing non-NULL, is card already dirty?
4256
4257 const Register card_addr = tmp;
4258 const Register cardtable = tmp2;
4259
4260 movptr(card_addr, store_addr);
4261 shrptr(card_addr, CardTableModRefBS::card_shift);
4262 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4263 // a valid address and therefore is not properly handled by the relocation code.
4264 movptr(cardtable, (intptr_t)ct->byte_map_base);
4265 addptr(card_addr, cardtable);
4266
4267 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4268 jcc(Assembler::equal, done);
4269
4270 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4271 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4272 jcc(Assembler::equal, done);
4273
4274
4275 // storing a region crossing, non-NULL oop, card is clean.
4276 // dirty card and log.
4277
4278 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4279
4280 cmpl(queue_index, 0);
4281 jcc(Assembler::equal, runtime);
4282 subl(queue_index, wordSize);
4283 movptr(tmp2, buffer);
4284 #ifdef _LP64
4285 movslq(rscratch1, queue_index);
4286 addq(tmp2, rscratch1);
4287 movq(Address(tmp2, 0), card_addr);
4288 #else
4289 addl(tmp2, queue_index);
4290 movl(Address(tmp2, 0), card_addr);
4291 #endif
4292 jmp(done);
4293
4294 bind(runtime);
4295 // save the live input values
4296 push(store_addr);
4297 push(new_val);
4298 #ifdef _LP64
4299 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4300 #else
4301 push(thread);
4302 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4303 pop(thread);
4304 #endif
4305 pop(new_val);
4306 pop(store_addr);
4307
4308 bind(done);
4309 }
4310
4311 #endif // INCLUDE_ALL_GCS
4312 //////////////////////////////////////////////////////////////////////////////////
4313
4314
4315 void MacroAssembler::store_check(Register obj) {
4316 // Does a store check for the oop in register obj. The content of
4317 // register obj is destroyed afterwards.
4318 store_check_part_1(obj);
4319 store_check_part_2(obj);
4320 }
4321
4322 void MacroAssembler::store_check(Register obj, Address dst) {
4323 store_check(obj);
4324 }
4325
4326
4327 // split the store check operation so that other instructions can be scheduled inbetween
4328 void MacroAssembler::store_check_part_1(Register obj) {
4329 BarrierSet* bs = Universe::heap()->barrier_set();
4330 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4331 shrptr(obj, CardTableModRefBS::card_shift);
4332 }
4333
4334 void MacroAssembler::store_check_part_2(Register obj) {
4335 BarrierSet* bs = Universe::heap()->barrier_set();
4336 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4337 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4338 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4339
4340 // The calculation for byte_map_base is as follows:
4341 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4342 // So this essentially converts an address to a displacement and it will
4343 // never need to be relocated. On 64bit however the value may be too
4344 // large for a 32bit displacement.
4345 intptr_t disp = (intptr_t) ct->byte_map_base;
4346 if (is_simm32(disp)) {
4347 Address cardtable(noreg, obj, Address::times_1, disp);
4348 movb(cardtable, 0);
4349 } else {
4350 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4351 // displacement and done in a single instruction given favorable mapping and a
4352 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4353 // entry and that entry is not properly handled by the relocation code.
4354 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4355 Address index(noreg, obj, Address::times_1);
4356 movb(as_Address(ArrayAddress(cardtable, index)), 0);
4357 }
4358 }
4359
4360 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4361 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4362 }
4363
4364 // Force generation of a 4 byte immediate value even if it fits into 8bit
4365 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4366 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4367 }
4368
4369 void MacroAssembler::subptr(Register dst, Register src) {
4370 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4371 }
4372
4373 // C++ bool manipulation
4374 void MacroAssembler::testbool(Register dst) {
4375 if(sizeof(bool) == 1)
4376 testb(dst, 0xff);
4377 else if(sizeof(bool) == 2) {
4378 // testw implementation needed for two byte bools
4379 ShouldNotReachHere();
4380 } else if(sizeof(bool) == 4)
4381 testl(dst, dst);
4382 else
4383 // unsupported
4384 ShouldNotReachHere();
4385 }
4386
4387 void MacroAssembler::testptr(Register dst, Register src) {
4388 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4389 }
4390
4391 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4392 void MacroAssembler::tlab_allocate(Register obj,
4393 Register var_size_in_bytes,
4394 int con_size_in_bytes,
4395 Register t1,
4396 Register t2,
4397 Label& slow_case) {
4398 assert_different_registers(obj, t1, t2);
4399 assert_different_registers(obj, var_size_in_bytes, t1);
4400 Register end = t2;
4401 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4402
4403 verify_tlab();
4404
4405 NOT_LP64(get_thread(thread));
4406
4407 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4408 if (var_size_in_bytes == noreg) {
4409 lea(end, Address(obj, con_size_in_bytes));
4410 } else {
4411 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4412 }
4413 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4414 jcc(Assembler::above, slow_case);
4415
4416 // update the tlab top pointer
4417 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4418
4419 // recover var_size_in_bytes if necessary
4420 if (var_size_in_bytes == end) {
4421 subptr(var_size_in_bytes, obj);
4422 }
4423 verify_tlab();
4424 }
4425
4426 // Preserves rbx, and rdx.
4427 Register MacroAssembler::tlab_refill(Label& retry,
4428 Label& try_eden,
4429 Label& slow_case) {
4430 Register top = rax;
4431 Register t1 = rcx;
4432 Register t2 = rsi;
4433 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4434 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4435 Label do_refill, discard_tlab;
4436
4437 if (!Universe::heap()->supports_inline_contig_alloc()) {
4438 // No allocation in the shared eden.
4439 jmp(slow_case);
4440 }
4441
4442 NOT_LP64(get_thread(thread_reg));
4443
4444 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4445 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4446
4447 // calculate amount of free space
4448 subptr(t1, top);
4449 shrptr(t1, LogHeapWordSize);
4450
4451 // Retain tlab and allocate object in shared space if
4452 // the amount free in the tlab is too large to discard.
4453 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4454 jcc(Assembler::lessEqual, discard_tlab);
4455
4456 // Retain
4457 // %%% yuck as movptr...
4458 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4459 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4460 if (TLABStats) {
4461 // increment number of slow_allocations
4462 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4463 }
4464 jmp(try_eden);
4465
4466 bind(discard_tlab);
4467 if (TLABStats) {
4468 // increment number of refills
4469 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4470 // accumulate wastage -- t1 is amount free in tlab
4471 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4472 }
4473
4474 // if tlab is currently allocated (top or end != null) then
4475 // fill [top, end + alignment_reserve) with array object
4476 testptr(top, top);
4477 jcc(Assembler::zero, do_refill);
4478
4479 // set up the mark word
4480 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4481 // set the length to the remaining space
4482 subptr(t1, typeArrayOopDesc::header_size(T_INT));
4483 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4484 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4485 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4486 // set klass to intArrayKlass
4487 // dubious reloc why not an oop reloc?
4488 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4489 // store klass last. concurrent gcs assumes klass length is valid if
4490 // klass field is not null.
4491 store_klass(top, t1);
4492
4493 movptr(t1, top);
4494 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4495 incr_allocated_bytes(thread_reg, t1, 0);
4496
4497 // refill the tlab with an eden allocation
4498 bind(do_refill);
4499 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4500 shlptr(t1, LogHeapWordSize);
4501 // allocate new tlab, address returned in top
4502 eden_allocate(top, t1, 0, t2, slow_case);
4503
4504 // Check that t1 was preserved in eden_allocate.
4505 #ifdef ASSERT
4506 if (UseTLAB) {
4507 Label ok;
4508 Register tsize = rsi;
4509 assert_different_registers(tsize, thread_reg, t1);
4510 push(tsize);
4511 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4512 shlptr(tsize, LogHeapWordSize);
4513 cmpptr(t1, tsize);
4514 jcc(Assembler::equal, ok);
4515 STOP("assert(t1 != tlab size)");
4516 should_not_reach_here();
4517
4518 bind(ok);
4519 pop(tsize);
4520 }
4521 #endif
4522 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4523 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4524 addptr(top, t1);
4525 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4526 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4527 verify_tlab();
4528 jmp(retry);
4529
4530 return thread_reg; // for use by caller
4531 }
4532
4533 void MacroAssembler::incr_allocated_bytes(Register thread,
4534 Register var_size_in_bytes,
4535 int con_size_in_bytes,
4536 Register t1) {
4537 if (!thread->is_valid()) {
4538 #ifdef _LP64
4539 thread = r15_thread;
4540 #else
4541 assert(t1->is_valid(), "need temp reg");
4542 thread = t1;
4543 get_thread(thread);
4544 #endif
4545 }
4546
4547 #ifdef _LP64
4548 if (var_size_in_bytes->is_valid()) {
4549 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4550 } else {
4551 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4552 }
4553 #else
4554 if (var_size_in_bytes->is_valid()) {
4555 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4556 } else {
4557 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4558 }
4559 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4560 #endif
4561 }
4562
4563 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4564 pusha();
4565
4566 // if we are coming from c1, xmm registers may be live
4567 int off = 0;
4568 if (UseSSE == 1) {
4569 subptr(rsp, sizeof(jdouble)*8);
4570 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
4571 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
4572 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
4573 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
4574 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
4575 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
4576 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
4577 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
4578 } else if (UseSSE >= 2) {
4579 #ifdef COMPILER2
4580 if (MaxVectorSize > 16) {
4581 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4582 // Save upper half of YMM registes
4583 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4584 vextractf128h(Address(rsp, 0),xmm0);
4585 vextractf128h(Address(rsp, 16),xmm1);
4586 vextractf128h(Address(rsp, 32),xmm2);
4587 vextractf128h(Address(rsp, 48),xmm3);
4588 vextractf128h(Address(rsp, 64),xmm4);
4589 vextractf128h(Address(rsp, 80),xmm5);
4590 vextractf128h(Address(rsp, 96),xmm6);
4591 vextractf128h(Address(rsp,112),xmm7);
4592 #ifdef _LP64
4593 vextractf128h(Address(rsp,128),xmm8);
4594 vextractf128h(Address(rsp,144),xmm9);
4595 vextractf128h(Address(rsp,160),xmm10);
4596 vextractf128h(Address(rsp,176),xmm11);
4597 vextractf128h(Address(rsp,192),xmm12);
4598 vextractf128h(Address(rsp,208),xmm13);
4599 vextractf128h(Address(rsp,224),xmm14);
4600 vextractf128h(Address(rsp,240),xmm15);
4601 #endif
4602 }
4603 #endif
4604 // Save whole 128bit (16 bytes) XMM regiters
4605 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4606 movdqu(Address(rsp,off++*16),xmm0);
4607 movdqu(Address(rsp,off++*16),xmm1);
4608 movdqu(Address(rsp,off++*16),xmm2);
4609 movdqu(Address(rsp,off++*16),xmm3);
4610 movdqu(Address(rsp,off++*16),xmm4);
4611 movdqu(Address(rsp,off++*16),xmm5);
4612 movdqu(Address(rsp,off++*16),xmm6);
4613 movdqu(Address(rsp,off++*16),xmm7);
4614 #ifdef _LP64
4615 movdqu(Address(rsp,off++*16),xmm8);
4616 movdqu(Address(rsp,off++*16),xmm9);
4617 movdqu(Address(rsp,off++*16),xmm10);
4618 movdqu(Address(rsp,off++*16),xmm11);
4619 movdqu(Address(rsp,off++*16),xmm12);
4620 movdqu(Address(rsp,off++*16),xmm13);
4621 movdqu(Address(rsp,off++*16),xmm14);
4622 movdqu(Address(rsp,off++*16),xmm15);
4623 #endif
4624 }
4625
4626 // Preserve registers across runtime call
4627 int incoming_argument_and_return_value_offset = -1;
4628 if (num_fpu_regs_in_use > 1) {
4629 // Must preserve all other FPU regs (could alternatively convert
4630 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4631 // FPU state, but can not trust C compiler)
4632 NEEDS_CLEANUP;
4633 // NOTE that in this case we also push the incoming argument(s) to
4634 // the stack and restore it later; we also use this stack slot to
4635 // hold the return value from dsin, dcos etc.
4636 for (int i = 0; i < num_fpu_regs_in_use; i++) {
4637 subptr(rsp, sizeof(jdouble));
4638 fstp_d(Address(rsp, 0));
4639 }
4640 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4641 for (int i = nb_args-1; i >= 0; i--) {
4642 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4643 }
4644 }
4645
4646 subptr(rsp, nb_args*sizeof(jdouble));
4647 for (int i = 0; i < nb_args; i++) {
4648 fstp_d(Address(rsp, i*sizeof(jdouble)));
4649 }
4650
4651 #ifdef _LP64
4652 if (nb_args > 0) {
4653 movdbl(xmm0, Address(rsp, 0));
4654 }
4655 if (nb_args > 1) {
4656 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4657 }
4658 assert(nb_args <= 2, "unsupported number of args");
4659 #endif // _LP64
4660
4661 // NOTE: we must not use call_VM_leaf here because that requires a
4662 // complete interpreter frame in debug mode -- same bug as 4387334
4663 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4664 // do proper 64bit abi
4665
4666 NEEDS_CLEANUP;
4667 // Need to add stack banging before this runtime call if it needs to
4668 // be taken; however, there is no generic stack banging routine at
4669 // the MacroAssembler level
4670
4671 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4672
4673 #ifdef _LP64
4674 movsd(Address(rsp, 0), xmm0);
4675 fld_d(Address(rsp, 0));
4676 #endif // _LP64
4677 addptr(rsp, sizeof(jdouble) * nb_args);
4678 if (num_fpu_regs_in_use > 1) {
4679 // Must save return value to stack and then restore entire FPU
4680 // stack except incoming arguments
4681 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4682 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4683 fld_d(Address(rsp, 0));
4684 addptr(rsp, sizeof(jdouble));
4685 }
4686 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4687 addptr(rsp, sizeof(jdouble) * nb_args);
4688 }
4689
4690 off = 0;
4691 if (UseSSE == 1) {
4692 movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
4693 movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
4694 movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
4695 movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
4696 movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
4697 movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
4698 movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
4699 movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
4700 addptr(rsp, sizeof(jdouble)*8);
4701 } else if (UseSSE >= 2) {
4702 // Restore whole 128bit (16 bytes) XMM regiters
4703 movdqu(xmm0, Address(rsp,off++*16));
4704 movdqu(xmm1, Address(rsp,off++*16));
4705 movdqu(xmm2, Address(rsp,off++*16));
4706 movdqu(xmm3, Address(rsp,off++*16));
4707 movdqu(xmm4, Address(rsp,off++*16));
4708 movdqu(xmm5, Address(rsp,off++*16));
4709 movdqu(xmm6, Address(rsp,off++*16));
4710 movdqu(xmm7, Address(rsp,off++*16));
4711 #ifdef _LP64
4712 movdqu(xmm8, Address(rsp,off++*16));
4713 movdqu(xmm9, Address(rsp,off++*16));
4714 movdqu(xmm10, Address(rsp,off++*16));
4715 movdqu(xmm11, Address(rsp,off++*16));
4716 movdqu(xmm12, Address(rsp,off++*16));
4717 movdqu(xmm13, Address(rsp,off++*16));
4718 movdqu(xmm14, Address(rsp,off++*16));
4719 movdqu(xmm15, Address(rsp,off++*16));
4720 #endif
4721 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4722 #ifdef COMPILER2
4723 if (MaxVectorSize > 16) {
4724 // Restore upper half of YMM registes.
4725 vinsertf128h(xmm0, Address(rsp, 0));
4726 vinsertf128h(xmm1, Address(rsp, 16));
4727 vinsertf128h(xmm2, Address(rsp, 32));
4728 vinsertf128h(xmm3, Address(rsp, 48));
4729 vinsertf128h(xmm4, Address(rsp, 64));
4730 vinsertf128h(xmm5, Address(rsp, 80));
4731 vinsertf128h(xmm6, Address(rsp, 96));
4732 vinsertf128h(xmm7, Address(rsp,112));
4733 #ifdef _LP64
4734 vinsertf128h(xmm8, Address(rsp,128));
4735 vinsertf128h(xmm9, Address(rsp,144));
4736 vinsertf128h(xmm10, Address(rsp,160));
4737 vinsertf128h(xmm11, Address(rsp,176));
4738 vinsertf128h(xmm12, Address(rsp,192));
4739 vinsertf128h(xmm13, Address(rsp,208));
4740 vinsertf128h(xmm14, Address(rsp,224));
4741 vinsertf128h(xmm15, Address(rsp,240));
4742 #endif
4743 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4744 }
4745 #endif
4746 }
4747 popa();
4748 }
4749
4750 static const double pi_4 = 0.7853981633974483;
4751
4752 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4753 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4754 // was attempted in this code; unfortunately it appears that the
4755 // switch to 80-bit precision and back causes this to be
4756 // unprofitable compared with simply performing a runtime call if
4757 // the argument is out of the (-pi/4, pi/4) range.
4758
4759 Register tmp = noreg;
4760 if (!VM_Version::supports_cmov()) {
4761 // fcmp needs a temporary so preserve rbx,
4762 tmp = rbx;
4763 push(tmp);
4764 }
4765
4766 Label slow_case, done;
4767
4768 ExternalAddress pi4_adr = (address)&pi_4;
4769 if (reachable(pi4_adr)) {
4770 // x ?<= pi/4
4771 fld_d(pi4_adr);
4772 fld_s(1); // Stack: X PI/4 X
4773 fabs(); // Stack: |X| PI/4 X
4774 fcmp(tmp);
4775 jcc(Assembler::above, slow_case);
4776
4777 // fastest case: -pi/4 <= x <= pi/4
4778 switch(trig) {
4779 case 's':
4780 fsin();
4781 break;
4782 case 'c':
4783 fcos();
4784 break;
4785 case 't':
4786 ftan();
4787 break;
4788 default:
4789 assert(false, "bad intrinsic");
4790 break;
4791 }
4792 jmp(done);
4793 }
4794
4795 // slow case: runtime call
4796 bind(slow_case);
4797
4798 switch(trig) {
4799 case 's':
4800 {
4801 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4802 }
4803 break;
4804 case 'c':
4805 {
4806 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4807 }
4808 break;
4809 case 't':
4810 {
4811 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4812 }
4813 break;
4814 default:
4815 assert(false, "bad intrinsic");
4816 break;
4817 }
4818
4819 // Come here with result in F-TOS
4820 bind(done);
4821
4822 if (tmp != noreg) {
4823 pop(tmp);
4824 }
4825 }
4826
4827
4828 // Look up the method for a megamorphic invokeinterface call.
4829 // The target method is determined by <intf_klass, itable_index>.
4830 // The receiver klass is in recv_klass.
4831 // On success, the result will be in method_result, and execution falls through.
4832 // On failure, execution transfers to the given label.
4833 void MacroAssembler::lookup_interface_method(Register recv_klass,
4834 Register intf_klass,
4835 RegisterOrConstant itable_index,
4836 Register method_result,
4837 Register scan_temp,
4838 Label& L_no_such_interface) {
4839 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
4840 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4841 "caller must use same register for non-constant itable index as for method");
4842
4843 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4844 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4845 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4846 int scan_step = itableOffsetEntry::size() * wordSize;
4847 int vte_size = vtableEntry::size() * wordSize;
4848 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4849 assert(vte_size == wordSize, "else adjust times_vte_scale");
4850
4851 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4852
4853 // %%% Could store the aligned, prescaled offset in the klassoop.
4854 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4855 if (HeapWordsPerLong > 1) {
4856 // Round up to align_object_offset boundary
4857 // see code for InstanceKlass::start_of_itable!
4858 round_to(scan_temp, BytesPerLong);
4859 }
4860
4861 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4862 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4863 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4864
4865 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4866 // if (scan->interface() == intf) {
4867 // result = (klass + scan->offset() + itable_index);
4868 // }
4869 // }
4870 Label search, found_method;
4871
4872 for (int peel = 1; peel >= 0; peel--) {
4873 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4874 cmpptr(intf_klass, method_result);
4875
4876 if (peel) {
4877 jccb(Assembler::equal, found_method);
4878 } else {
4879 jccb(Assembler::notEqual, search);
4880 // (invert the test to fall through to found_method...)
4881 }
4882
4883 if (!peel) break;
4884
4885 bind(search);
4886
4887 // Check that the previous entry is non-null. A null entry means that
4888 // the receiver class doesn't implement the interface, and wasn't the
4889 // same as when the caller was compiled.
4890 testptr(method_result, method_result);
4891 jcc(Assembler::zero, L_no_such_interface);
4892 addptr(scan_temp, scan_step);
4893 }
4894
4895 bind(found_method);
4896
4897 // Got a hit.
4898 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4899 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4900 }
4901
4902
4903 // virtual method calling
4904 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4905 RegisterOrConstant vtable_index,
4906 Register method_result) {
4907 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4908 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4909 Address vtable_entry_addr(recv_klass,
4910 vtable_index, Address::times_ptr,
4911 base + vtableEntry::method_offset_in_bytes());
4912 movptr(method_result, vtable_entry_addr);
4913 }
4914
4915
4916 void MacroAssembler::check_klass_subtype(Register sub_klass,
4917 Register super_klass,
4918 Register temp_reg,
4919 Label& L_success) {
4920 Label L_failure;
4921 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4922 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4923 bind(L_failure);
4924 }
4925
4926
4927 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4928 Register super_klass,
4929 Register temp_reg,
4930 Label* L_success,
4931 Label* L_failure,
4932 Label* L_slow_path,
4933 RegisterOrConstant super_check_offset) {
4934 assert_different_registers(sub_klass, super_klass, temp_reg);
4935 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4936 if (super_check_offset.is_register()) {
4937 assert_different_registers(sub_klass, super_klass,
4938 super_check_offset.as_register());
4939 } else if (must_load_sco) {
4940 assert(temp_reg != noreg, "supply either a temp or a register offset");
4941 }
4942
4943 Label L_fallthrough;
4944 int label_nulls = 0;
4945 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4946 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4947 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4948 assert(label_nulls <= 1, "at most one NULL in the batch");
4949
4950 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4951 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4952 Address super_check_offset_addr(super_klass, sco_offset);
4953
4954 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4955 // range of a jccb. If this routine grows larger, reconsider at
4956 // least some of these.
4957 #define local_jcc(assembler_cond, label) \
4958 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4959 else jcc( assembler_cond, label) /*omit semi*/
4960
4961 // Hacked jmp, which may only be used just before L_fallthrough.
4962 #define final_jmp(label) \
4963 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4964 else jmp(label) /*omit semi*/
4965
4966 // If the pointers are equal, we are done (e.g., String[] elements).
4967 // This self-check enables sharing of secondary supertype arrays among
4968 // non-primary types such as array-of-interface. Otherwise, each such
4969 // type would need its own customized SSA.
4970 // We move this check to the front of the fast path because many
4971 // type checks are in fact trivially successful in this manner,
4972 // so we get a nicely predicted branch right at the start of the check.
4973 cmpptr(sub_klass, super_klass);
4974 local_jcc(Assembler::equal, *L_success);
4975
4976 // Check the supertype display:
4977 if (must_load_sco) {
4978 // Positive movl does right thing on LP64.
4979 movl(temp_reg, super_check_offset_addr);
4980 super_check_offset = RegisterOrConstant(temp_reg);
4981 }
4982 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4983 cmpptr(super_klass, super_check_addr); // load displayed supertype
4984
4985 // This check has worked decisively for primary supers.
4986 // Secondary supers are sought in the super_cache ('super_cache_addr').
4987 // (Secondary supers are interfaces and very deeply nested subtypes.)
4988 // This works in the same check above because of a tricky aliasing
4989 // between the super_cache and the primary super display elements.
4990 // (The 'super_check_addr' can address either, as the case requires.)
4991 // Note that the cache is updated below if it does not help us find
4992 // what we need immediately.
4993 // So if it was a primary super, we can just fail immediately.
4994 // Otherwise, it's the slow path for us (no success at this point).
4995
4996 if (super_check_offset.is_register()) {
4997 local_jcc(Assembler::equal, *L_success);
4998 cmpl(super_check_offset.as_register(), sc_offset);
4999 if (L_failure == &L_fallthrough) {
5000 local_jcc(Assembler::equal, *L_slow_path);
5001 } else {
5002 local_jcc(Assembler::notEqual, *L_failure);
5003 final_jmp(*L_slow_path);
5004 }
5005 } else if (super_check_offset.as_constant() == sc_offset) {
5006 // Need a slow path; fast failure is impossible.
5007 if (L_slow_path == &L_fallthrough) {
5008 local_jcc(Assembler::equal, *L_success);
5009 } else {
5010 local_jcc(Assembler::notEqual, *L_slow_path);
5011 final_jmp(*L_success);
5012 }
5013 } else {
5014 // No slow path; it's a fast decision.
5015 if (L_failure == &L_fallthrough) {
5016 local_jcc(Assembler::equal, *L_success);
5017 } else {
5018 local_jcc(Assembler::notEqual, *L_failure);
5019 final_jmp(*L_success);
5020 }
5021 }
5022
5023 bind(L_fallthrough);
5024
5025 #undef local_jcc
5026 #undef final_jmp
5027 }
5028
5029
5030 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5031 Register super_klass,
5032 Register temp_reg,
5033 Register temp2_reg,
5034 Label* L_success,
5035 Label* L_failure,
5036 bool set_cond_codes) {
5037 assert_different_registers(sub_klass, super_klass, temp_reg);
5038 if (temp2_reg != noreg)
5039 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5040 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5041
5042 Label L_fallthrough;
5043 int label_nulls = 0;
5044 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5045 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5046 assert(label_nulls <= 1, "at most one NULL in the batch");
5047
5048 // a couple of useful fields in sub_klass:
5049 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5050 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5051 Address secondary_supers_addr(sub_klass, ss_offset);
5052 Address super_cache_addr( sub_klass, sc_offset);
5053
5054 // Do a linear scan of the secondary super-klass chain.
5055 // This code is rarely used, so simplicity is a virtue here.
5056 // The repne_scan instruction uses fixed registers, which we must spill.
5057 // Don't worry too much about pre-existing connections with the input regs.
5058
5059 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5060 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5061
5062 // Get super_klass value into rax (even if it was in rdi or rcx).
5063 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5064 if (super_klass != rax || UseCompressedOops) {
5065 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5066 mov(rax, super_klass);
5067 }
5068 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5069 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5070
5071 #ifndef PRODUCT
5072 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5073 ExternalAddress pst_counter_addr((address) pst_counter);
5074 NOT_LP64( incrementl(pst_counter_addr) );
5075 LP64_ONLY( lea(rcx, pst_counter_addr) );
5076 LP64_ONLY( incrementl(Address(rcx, 0)) );
5077 #endif //PRODUCT
5078
5079 // We will consult the secondary-super array.
5080 movptr(rdi, secondary_supers_addr);
5081 // Load the array length. (Positive movl does right thing on LP64.)
5082 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5083 // Skip to start of data.
5084 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5085
5086 // Scan RCX words at [RDI] for an occurrence of RAX.
5087 // Set NZ/Z based on last compare.
5088 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5089 // not change flags (only scas instruction which is repeated sets flags).
5090 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5091
5092 testptr(rax,rax); // Set Z = 0
5093 repne_scan();
5094
5095 // Unspill the temp. registers:
5096 if (pushed_rdi) pop(rdi);
5097 if (pushed_rcx) pop(rcx);
5098 if (pushed_rax) pop(rax);
5099
5100 if (set_cond_codes) {
5101 // Special hack for the AD files: rdi is guaranteed non-zero.
5102 assert(!pushed_rdi, "rdi must be left non-NULL");
5103 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5104 }
5105
5106 if (L_failure == &L_fallthrough)
5107 jccb(Assembler::notEqual, *L_failure);
5108 else jcc(Assembler::notEqual, *L_failure);
5109
5110 // Success. Cache the super we found and proceed in triumph.
5111 movptr(super_cache_addr, super_klass);
5112
5113 if (L_success != &L_fallthrough) {
5114 jmp(*L_success);
5115 }
5116
5117 #undef IS_A_TEMP
5118
5119 bind(L_fallthrough);
5120 }
5121
5122
5123 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5124 if (VM_Version::supports_cmov()) {
5125 cmovl(cc, dst, src);
5126 } else {
5127 Label L;
5128 jccb(negate_condition(cc), L);
5129 movl(dst, src);
5130 bind(L);
5131 }
5132 }
5133
5134 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5135 if (VM_Version::supports_cmov()) {
5136 cmovl(cc, dst, src);
5137 } else {
5138 Label L;
5139 jccb(negate_condition(cc), L);
5140 movl(dst, src);
5141 bind(L);
5142 }
5143 }
5144
5145 void MacroAssembler::verify_oop(Register reg, const char* s) {
5146 if (!VerifyOops) return;
5147
5148 // Pass register number to verify_oop_subroutine
5149 const char* b = NULL;
5150 {
5151 ResourceMark rm;
5152 stringStream ss;
5153 ss.print("verify_oop: %s: %s", reg->name(), s);
5154 b = code_string(ss.as_string());
5155 }
5156 BLOCK_COMMENT("verify_oop {");
5157 #ifdef _LP64
5158 push(rscratch1); // save r10, trashed by movptr()
5159 #endif
5160 push(rax); // save rax,
5161 push(reg); // pass register argument
5162 ExternalAddress buffer((address) b);
5163 // avoid using pushptr, as it modifies scratch registers
5164 // and our contract is not to modify anything
5165 movptr(rax, buffer.addr());
5166 push(rax);
5167 // call indirectly to solve generation ordering problem
5168 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5169 call(rax);
5170 // Caller pops the arguments (oop, message) and restores rax, r10
5171 BLOCK_COMMENT("} verify_oop");
5172 }
5173
5174
5175 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5176 Register tmp,
5177 int offset) {
5178 intptr_t value = *delayed_value_addr;
5179 if (value != 0)
5180 return RegisterOrConstant(value + offset);
5181
5182 // load indirectly to solve generation ordering problem
5183 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5184
5185 #ifdef ASSERT
5186 { Label L;
5187 testptr(tmp, tmp);
5188 if (WizardMode) {
5189 const char* buf = NULL;
5190 {
5191 ResourceMark rm;
5192 stringStream ss;
5193 ss.print("DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
5194 buf = code_string(ss.as_string());
5195 }
5196 jcc(Assembler::notZero, L);
5197 STOP(buf);
5198 } else {
5199 jccb(Assembler::notZero, L);
5200 hlt();
5201 }
5202 bind(L);
5203 }
5204 #endif
5205
5206 if (offset != 0)
5207 addptr(tmp, offset);
5208
5209 return RegisterOrConstant(tmp);
5210 }
5211
5212
5213 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5214 int extra_slot_offset) {
5215 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5216 int stackElementSize = Interpreter::stackElementSize;
5217 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5218 #ifdef ASSERT
5219 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5220 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5221 #endif
5222 Register scale_reg = noreg;
5223 Address::ScaleFactor scale_factor = Address::no_scale;
5224 if (arg_slot.is_constant()) {
5225 offset += arg_slot.as_constant() * stackElementSize;
5226 } else {
5227 scale_reg = arg_slot.as_register();
5228 scale_factor = Address::times(stackElementSize);
5229 }
5230 offset += wordSize; // return PC is on stack
5231 return Address(rsp, scale_reg, scale_factor, offset);
5232 }
5233
5234
5235 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5236 if (!VerifyOops) return;
5237
5238 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5239 // Pass register number to verify_oop_subroutine
5240 const char* b = NULL;
5241 {
5242 ResourceMark rm;
5243 stringStream ss;
5244 ss.print("verify_oop_addr: %s", s);
5245 b = code_string(ss.as_string());
5246 }
5247 #ifdef _LP64
5248 push(rscratch1); // save r10, trashed by movptr()
5249 #endif
5250 push(rax); // save rax,
5251 // addr may contain rsp so we will have to adjust it based on the push
5252 // we just did (and on 64 bit we do two pushes)
5253 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5254 // stores rax into addr which is backwards of what was intended.
5255 if (addr.uses(rsp)) {
5256 lea(rax, addr);
5257 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5258 } else {
5259 pushptr(addr);
5260 }
5261
5262 ExternalAddress buffer((address) b);
5263 // pass msg argument
5264 // avoid using pushptr, as it modifies scratch registers
5265 // and our contract is not to modify anything
5266 movptr(rax, buffer.addr());
5267 push(rax);
5268
5269 // call indirectly to solve generation ordering problem
5270 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5271 call(rax);
5272 // Caller pops the arguments (addr, message) and restores rax, r10.
5273 }
5274
5275 void MacroAssembler::verify_tlab() {
5276 #ifdef ASSERT
5277 if (UseTLAB && VerifyOops) {
5278 Label next, ok;
5279 Register t1 = rsi;
5280 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5281
5282 push(t1);
5283 NOT_LP64(push(thread_reg));
5284 NOT_LP64(get_thread(thread_reg));
5285
5286 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5287 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5288 jcc(Assembler::aboveEqual, next);
5289 STOP("assert(top >= start)");
5290 should_not_reach_here();
5291
5292 bind(next);
5293 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5294 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5295 jcc(Assembler::aboveEqual, ok);
5296 STOP("assert(top <= end)");
5297 should_not_reach_here();
5298
5299 bind(ok);
5300 NOT_LP64(pop(thread_reg));
5301 pop(t1);
5302 }
5303 #endif
5304 }
5305
5306 class ControlWord {
5307 public:
5308 int32_t _value;
5309
5310 int rounding_control() const { return (_value >> 10) & 3 ; }
5311 int precision_control() const { return (_value >> 8) & 3 ; }
5312 bool precision() const { return ((_value >> 5) & 1) != 0; }
5313 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5314 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5315 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5316 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5317 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5318
5319 void print() const {
5320 // rounding control
5321 const char* rc;
5322 switch (rounding_control()) {
5323 case 0: rc = "round near"; break;
5324 case 1: rc = "round down"; break;
5325 case 2: rc = "round up "; break;
5326 case 3: rc = "chop "; break;
5327 };
5328 // precision control
5329 const char* pc;
5330 switch (precision_control()) {
5331 case 0: pc = "24 bits "; break;
5332 case 1: pc = "reserved"; break;
5333 case 2: pc = "53 bits "; break;
5334 case 3: pc = "64 bits "; break;
5335 };
5336 // flags
5337 char f[9];
5338 f[0] = ' ';
5339 f[1] = ' ';
5340 f[2] = (precision ()) ? 'P' : 'p';
5341 f[3] = (underflow ()) ? 'U' : 'u';
5342 f[4] = (overflow ()) ? 'O' : 'o';
5343 f[5] = (zero_divide ()) ? 'Z' : 'z';
5344 f[6] = (denormalized()) ? 'D' : 'd';
5345 f[7] = (invalid ()) ? 'I' : 'i';
5346 f[8] = '\x0';
5347 // output
5348 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5349 }
5350
5351 };
5352
5353 class StatusWord {
5354 public:
5355 int32_t _value;
5356
5357 bool busy() const { return ((_value >> 15) & 1) != 0; }
5358 bool C3() const { return ((_value >> 14) & 1) != 0; }
5359 bool C2() const { return ((_value >> 10) & 1) != 0; }
5360 bool C1() const { return ((_value >> 9) & 1) != 0; }
5361 bool C0() const { return ((_value >> 8) & 1) != 0; }
5362 int top() const { return (_value >> 11) & 7 ; }
5363 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5364 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5365 bool precision() const { return ((_value >> 5) & 1) != 0; }
5366 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5367 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5368 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5369 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5370 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5371
5372 void print() const {
5373 // condition codes
5374 char c[5];
5375 c[0] = (C3()) ? '3' : '-';
5376 c[1] = (C2()) ? '2' : '-';
5377 c[2] = (C1()) ? '1' : '-';
5378 c[3] = (C0()) ? '0' : '-';
5379 c[4] = '\x0';
5380 // flags
5381 char f[9];
5382 f[0] = (error_status()) ? 'E' : '-';
5383 f[1] = (stack_fault ()) ? 'S' : '-';
5384 f[2] = (precision ()) ? 'P' : '-';
5385 f[3] = (underflow ()) ? 'U' : '-';
5386 f[4] = (overflow ()) ? 'O' : '-';
5387 f[5] = (zero_divide ()) ? 'Z' : '-';
5388 f[6] = (denormalized()) ? 'D' : '-';
5389 f[7] = (invalid ()) ? 'I' : '-';
5390 f[8] = '\x0';
5391 // output
5392 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5393 }
5394
5395 };
5396
5397 class TagWord {
5398 public:
5399 int32_t _value;
5400
5401 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5402
5403 void print() const {
5404 printf("%04x", _value & 0xFFFF);
5405 }
5406
5407 };
5408
5409 class FPU_Register {
5410 public:
5411 int32_t _m0;
5412 int32_t _m1;
5413 int16_t _ex;
5414
5415 bool is_indefinite() const {
5416 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5417 }
5418
5419 void print() const {
5420 char sign = (_ex < 0) ? '-' : '+';
5421 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5422 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5423 };
5424
5425 };
5426
5427 class FPU_State {
5428 public:
5429 enum {
5430 register_size = 10,
5431 number_of_registers = 8,
5432 register_mask = 7
5433 };
5434
5435 ControlWord _control_word;
5436 StatusWord _status_word;
5437 TagWord _tag_word;
5438 int32_t _error_offset;
5439 int32_t _error_selector;
5440 int32_t _data_offset;
5441 int32_t _data_selector;
5442 int8_t _register[register_size * number_of_registers];
5443
5444 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5445 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5446
5447 const char* tag_as_string(int tag) const {
5448 switch (tag) {
5449 case 0: return "valid";
5450 case 1: return "zero";
5451 case 2: return "special";
5452 case 3: return "empty";
5453 }
5454 ShouldNotReachHere();
5455 return NULL;
5456 }
5457
5458 void print() const {
5459 // print computation registers
5460 { int t = _status_word.top();
5461 for (int i = 0; i < number_of_registers; i++) {
5462 int j = (i - t) & register_mask;
5463 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5464 st(j)->print();
5465 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5466 }
5467 }
5468 printf("\n");
5469 // print control registers
5470 printf("ctrl = "); _control_word.print(); printf("\n");
5471 printf("stat = "); _status_word .print(); printf("\n");
5472 printf("tags = "); _tag_word .print(); printf("\n");
5473 }
5474
5475 };
5476
5477 class Flag_Register {
5478 public:
5479 int32_t _value;
5480
5481 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5482 bool direction() const { return ((_value >> 10) & 1) != 0; }
5483 bool sign() const { return ((_value >> 7) & 1) != 0; }
5484 bool zero() const { return ((_value >> 6) & 1) != 0; }
5485 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5486 bool parity() const { return ((_value >> 2) & 1) != 0; }
5487 bool carry() const { return ((_value >> 0) & 1) != 0; }
5488
5489 void print() const {
5490 // flags
5491 char f[8];
5492 f[0] = (overflow ()) ? 'O' : '-';
5493 f[1] = (direction ()) ? 'D' : '-';
5494 f[2] = (sign ()) ? 'S' : '-';
5495 f[3] = (zero ()) ? 'Z' : '-';
5496 f[4] = (auxiliary_carry()) ? 'A' : '-';
5497 f[5] = (parity ()) ? 'P' : '-';
5498 f[6] = (carry ()) ? 'C' : '-';
5499 f[7] = '\x0';
5500 // output
5501 printf("%08x flags = %s", _value, f);
5502 }
5503
5504 };
5505
5506 class IU_Register {
5507 public:
5508 int32_t _value;
5509
5510 void print() const {
5511 printf("%08x %11d", _value, _value);
5512 }
5513
5514 };
5515
5516 class IU_State {
5517 public:
5518 Flag_Register _eflags;
5519 IU_Register _rdi;
5520 IU_Register _rsi;
5521 IU_Register _rbp;
5522 IU_Register _rsp;
5523 IU_Register _rbx;
5524 IU_Register _rdx;
5525 IU_Register _rcx;
5526 IU_Register _rax;
5527
5528 void print() const {
5529 // computation registers
5530 printf("rax, = "); _rax.print(); printf("\n");
5531 printf("rbx, = "); _rbx.print(); printf("\n");
5532 printf("rcx = "); _rcx.print(); printf("\n");
5533 printf("rdx = "); _rdx.print(); printf("\n");
5534 printf("rdi = "); _rdi.print(); printf("\n");
5535 printf("rsi = "); _rsi.print(); printf("\n");
5536 printf("rbp, = "); _rbp.print(); printf("\n");
5537 printf("rsp = "); _rsp.print(); printf("\n");
5538 printf("\n");
5539 // control registers
5540 printf("flgs = "); _eflags.print(); printf("\n");
5541 }
5542 };
5543
5544
5545 class CPU_State {
5546 public:
5547 FPU_State _fpu_state;
5548 IU_State _iu_state;
5549
5550 void print() const {
5551 printf("--------------------------------------------------\n");
5552 _iu_state .print();
5553 printf("\n");
5554 _fpu_state.print();
5555 printf("--------------------------------------------------\n");
5556 }
5557
5558 };
5559
5560
5561 static void _print_CPU_state(CPU_State* state) {
5562 state->print();
5563 };
5564
5565
5566 void MacroAssembler::print_CPU_state() {
5567 push_CPU_state();
5568 push(rsp); // pass CPU state
5569 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5570 addptr(rsp, wordSize); // discard argument
5571 pop_CPU_state();
5572 }
5573
5574
5575 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5576 static int counter = 0;
5577 FPU_State* fs = &state->_fpu_state;
5578 counter++;
5579 // For leaf calls, only verify that the top few elements remain empty.
5580 // We only need 1 empty at the top for C2 code.
5581 if( stack_depth < 0 ) {
5582 if( fs->tag_for_st(7) != 3 ) {
5583 printf("FPR7 not empty\n");
5584 state->print();
5585 assert(false, "error");
5586 return false;
5587 }
5588 return true; // All other stack states do not matter
5589 }
5590
5591 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5592 "bad FPU control word");
5593
5594 // compute stack depth
5595 int i = 0;
5596 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5597 int d = i;
5598 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5599 // verify findings
5600 if (i != FPU_State::number_of_registers) {
5601 // stack not contiguous
5602 printf("%s: stack not contiguous at ST%d\n", s, i);
5603 state->print();
5604 assert(false, "error");
5605 return false;
5606 }
5607 // check if computed stack depth corresponds to expected stack depth
5608 if (stack_depth < 0) {
5609 // expected stack depth is -stack_depth or less
5610 if (d > -stack_depth) {
5611 // too many elements on the stack
5612 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5613 state->print();
5614 assert(false, "error");
5615 return false;
5616 }
5617 } else {
5618 // expected stack depth is stack_depth
5619 if (d != stack_depth) {
5620 // wrong stack depth
5621 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5622 state->print();
5623 assert(false, "error");
5624 return false;
5625 }
5626 }
5627 // everything is cool
5628 return true;
5629 }
5630
5631
5632 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5633 if (!VerifyFPU) return;
5634 push_CPU_state();
5635 push(rsp); // pass CPU state
5636 ExternalAddress msg((address) s);
5637 // pass message string s
5638 pushptr(msg.addr());
5639 push(stack_depth); // pass stack depth
5640 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5641 addptr(rsp, 3 * wordSize); // discard arguments
5642 // check for error
5643 { Label L;
5644 testl(rax, rax);
5645 jcc(Assembler::notZero, L);
5646 int3(); // break if error condition
5647 bind(L);
5648 }
5649 pop_CPU_state();
5650 }
5651
5652 void MacroAssembler::restore_cpu_control_state_after_jni() {
5653 // Either restore the MXCSR register after returning from the JNI Call
5654 // or verify that it wasn't changed (with -Xcheck:jni flag).
5655 if (VM_Version::supports_sse()) {
5656 if (RestoreMXCSROnJNICalls) {
5657 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5658 } else if (CheckJNICalls) {
5659 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5660 }
5661 }
5662 if (VM_Version::supports_avx()) {
5663 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5664 vzeroupper();
5665 }
5666
5667 #ifndef _LP64
5668 // Either restore the x87 floating pointer control word after returning
5669 // from the JNI call or verify that it wasn't changed.
5670 if (CheckJNICalls) {
5671 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5672 }
5673 #endif // _LP64
5674 }
5675
5676
5677 void MacroAssembler::load_klass(Register dst, Register src) {
5678 #ifdef _LP64
5679 if (UseCompressedClassPointers) {
5680 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5681 decode_klass_not_null(dst);
5682 } else
5683 #endif
5684 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5685 }
5686
5687 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5688 load_klass(dst, src);
5689 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5690 }
5691
5692 void MacroAssembler::store_klass(Register dst, Register src) {
5693 #ifdef _LP64
5694 if (UseCompressedClassPointers) {
5695 encode_klass_not_null(src);
5696 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5697 } else
5698 #endif
5699 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5700 }
5701
5702 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5703 #ifdef _LP64
5704 // FIXME: Must change all places where we try to load the klass.
5705 if (UseCompressedOops) {
5706 movl(dst, src);
5707 decode_heap_oop(dst);
5708 } else
5709 #endif
5710 movptr(dst, src);
5711 }
5712
5713 // Doesn't do verfication, generates fixed size code
5714 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5715 #ifdef _LP64
5716 if (UseCompressedOops) {
5717 movl(dst, src);
5718 decode_heap_oop_not_null(dst);
5719 } else
5720 #endif
5721 movptr(dst, src);
5722 }
5723
5724 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5725 #ifdef _LP64
5726 if (UseCompressedOops) {
5727 assert(!dst.uses(src), "not enough registers");
5728 encode_heap_oop(src);
5729 movl(dst, src);
5730 } else
5731 #endif
5732 movptr(dst, src);
5733 }
5734
5735 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5736 assert_different_registers(src1, tmp);
5737 #ifdef _LP64
5738 if (UseCompressedOops) {
5739 bool did_push = false;
5740 if (tmp == noreg) {
5741 tmp = rax;
5742 push(tmp);
5743 did_push = true;
5744 assert(!src2.uses(rsp), "can't push");
5745 }
5746 load_heap_oop(tmp, src2);
5747 cmpptr(src1, tmp);
5748 if (did_push) pop(tmp);
5749 } else
5750 #endif
5751 cmpptr(src1, src2);
5752 }
5753
5754 // Used for storing NULLs.
5755 void MacroAssembler::store_heap_oop_null(Address dst) {
5756 #ifdef _LP64
5757 if (UseCompressedOops) {
5758 movl(dst, (int32_t)NULL_WORD);
5759 } else {
5760 movslq(dst, (int32_t)NULL_WORD);
5761 }
5762 #else
5763 movl(dst, (int32_t)NULL_WORD);
5764 #endif
5765 }
5766
5767 #ifdef _LP64
5768 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5769 if (UseCompressedClassPointers) {
5770 // Store to klass gap in destination
5771 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5772 }
5773 }
5774
5775 #ifdef ASSERT
5776 void MacroAssembler::verify_heapbase(const char* msg) {
5777 assert (UseCompressedOops, "should be compressed");
5778 assert (Universe::heap() != NULL, "java heap should be initialized");
5779 if (CheckCompressedOops) {
5780 Label ok;
5781 push(rscratch1); // cmpptr trashes rscratch1
5782 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5783 jcc(Assembler::equal, ok);
5784 STOP(msg);
5785 bind(ok);
5786 pop(rscratch1);
5787 }
5788 }
5789 #endif
5790
5791 // Algorithm must match oop.inline.hpp encode_heap_oop.
5792 void MacroAssembler::encode_heap_oop(Register r) {
5793 #ifdef ASSERT
5794 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5795 #endif
5796 verify_oop(r, "broken oop in encode_heap_oop");
5797 if (Universe::narrow_oop_base() == NULL) {
5798 if (Universe::narrow_oop_shift() != 0) {
5799 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5800 shrq(r, LogMinObjAlignmentInBytes);
5801 }
5802 return;
5803 }
5804 testq(r, r);
5805 cmovq(Assembler::equal, r, r12_heapbase);
5806 subq(r, r12_heapbase);
5807 shrq(r, LogMinObjAlignmentInBytes);
5808 }
5809
5810 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5811 #ifdef ASSERT
5812 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5813 if (CheckCompressedOops) {
5814 Label ok;
5815 testq(r, r);
5816 jcc(Assembler::notEqual, ok);
5817 STOP("null oop passed to encode_heap_oop_not_null");
5818 bind(ok);
5819 }
5820 #endif
5821 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5822 if (Universe::narrow_oop_base() != NULL) {
5823 subq(r, r12_heapbase);
5824 }
5825 if (Universe::narrow_oop_shift() != 0) {
5826 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5827 shrq(r, LogMinObjAlignmentInBytes);
5828 }
5829 }
5830
5831 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5832 #ifdef ASSERT
5833 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5834 if (CheckCompressedOops) {
5835 Label ok;
5836 testq(src, src);
5837 jcc(Assembler::notEqual, ok);
5838 STOP("null oop passed to encode_heap_oop_not_null2");
5839 bind(ok);
5840 }
5841 #endif
5842 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5843 if (dst != src) {
5844 movq(dst, src);
5845 }
5846 if (Universe::narrow_oop_base() != NULL) {
5847 subq(dst, r12_heapbase);
5848 }
5849 if (Universe::narrow_oop_shift() != 0) {
5850 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5851 shrq(dst, LogMinObjAlignmentInBytes);
5852 }
5853 }
5854
5855 void MacroAssembler::decode_heap_oop(Register r) {
5856 #ifdef ASSERT
5857 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5858 #endif
5859 if (Universe::narrow_oop_base() == NULL) {
5860 if (Universe::narrow_oop_shift() != 0) {
5861 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5862 shlq(r, LogMinObjAlignmentInBytes);
5863 }
5864 } else {
5865 Label done;
5866 shlq(r, LogMinObjAlignmentInBytes);
5867 jccb(Assembler::equal, done);
5868 addq(r, r12_heapbase);
5869 bind(done);
5870 }
5871 verify_oop(r, "broken oop in decode_heap_oop");
5872 }
5873
5874 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5875 // Note: it will change flags
5876 assert (UseCompressedOops, "should only be used for compressed headers");
5877 assert (Universe::heap() != NULL, "java heap should be initialized");
5878 // Cannot assert, unverified entry point counts instructions (see .ad file)
5879 // vtableStubs also counts instructions in pd_code_size_limit.
5880 // Also do not verify_oop as this is called by verify_oop.
5881 if (Universe::narrow_oop_shift() != 0) {
5882 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5883 shlq(r, LogMinObjAlignmentInBytes);
5884 if (Universe::narrow_oop_base() != NULL) {
5885 addq(r, r12_heapbase);
5886 }
5887 } else {
5888 assert (Universe::narrow_oop_base() == NULL, "sanity");
5889 }
5890 }
5891
5892 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5893 // Note: it will change flags
5894 assert (UseCompressedOops, "should only be used for compressed headers");
5895 assert (Universe::heap() != NULL, "java heap should be initialized");
5896 // Cannot assert, unverified entry point counts instructions (see .ad file)
5897 // vtableStubs also counts instructions in pd_code_size_limit.
5898 // Also do not verify_oop as this is called by verify_oop.
5899 if (Universe::narrow_oop_shift() != 0) {
5900 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5901 if (LogMinObjAlignmentInBytes == Address::times_8) {
5902 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5903 } else {
5904 if (dst != src) {
5905 movq(dst, src);
5906 }
5907 shlq(dst, LogMinObjAlignmentInBytes);
5908 if (Universe::narrow_oop_base() != NULL) {
5909 addq(dst, r12_heapbase);
5910 }
5911 }
5912 } else {
5913 assert (Universe::narrow_oop_base() == NULL, "sanity");
5914 if (dst != src) {
5915 movq(dst, src);
5916 }
5917 }
5918 }
5919
5920 void MacroAssembler::encode_klass_not_null(Register r) {
5921 if (Universe::narrow_klass_base() != NULL) {
5922 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5923 assert(r != r12_heapbase, "Encoding a klass in r12");
5924 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5925 subq(r, r12_heapbase);
5926 }
5927 if (Universe::narrow_klass_shift() != 0) {
5928 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5929 shrq(r, LogKlassAlignmentInBytes);
5930 }
5931 if (Universe::narrow_klass_base() != NULL) {
5932 reinit_heapbase();
5933 }
5934 }
5935
5936 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5937 if (dst == src) {
5938 encode_klass_not_null(src);
5939 } else {
5940 if (Universe::narrow_klass_base() != NULL) {
5941 mov64(dst, (int64_t)Universe::narrow_klass_base());
5942 negq(dst);
5943 addq(dst, src);
5944 } else {
5945 movptr(dst, src);
5946 }
5947 if (Universe::narrow_klass_shift() != 0) {
5948 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5949 shrq(dst, LogKlassAlignmentInBytes);
5950 }
5951 }
5952 }
5953
5954 // Function instr_size_for_decode_klass_not_null() counts the instructions
5955 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5956 // when (Universe::heap() != NULL). Hence, if the instructions they
5957 // generate change, then this method needs to be updated.
5958 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5959 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5960 if (Universe::narrow_klass_base() != NULL) {
5961 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5962 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5963 } else {
5964 // longest load decode klass function, mov64, leaq
5965 return 16;
5966 }
5967 }
5968
5969 // !!! If the instructions that get generated here change then function
5970 // instr_size_for_decode_klass_not_null() needs to get updated.
5971 void MacroAssembler::decode_klass_not_null(Register r) {
5972 // Note: it will change flags
5973 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5974 assert(r != r12_heapbase, "Decoding a klass in r12");
5975 // Cannot assert, unverified entry point counts instructions (see .ad file)
5976 // vtableStubs also counts instructions in pd_code_size_limit.
5977 // Also do not verify_oop as this is called by verify_oop.
5978 if (Universe::narrow_klass_shift() != 0) {
5979 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5980 shlq(r, LogKlassAlignmentInBytes);
5981 }
5982 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5983 if (Universe::narrow_klass_base() != NULL) {
5984 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5985 addq(r, r12_heapbase);
5986 reinit_heapbase();
5987 }
5988 }
5989
5990 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5991 // Note: it will change flags
5992 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5993 if (dst == src) {
5994 decode_klass_not_null(dst);
5995 } else {
5996 // Cannot assert, unverified entry point counts instructions (see .ad file)
5997 // vtableStubs also counts instructions in pd_code_size_limit.
5998 // Also do not verify_oop as this is called by verify_oop.
5999 mov64(dst, (int64_t)Universe::narrow_klass_base());
6000 if (Universe::narrow_klass_shift() != 0) {
6001 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6002 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6003 leaq(dst, Address(dst, src, Address::times_8, 0));
6004 } else {
6005 addq(dst, src);
6006 }
6007 }
6008 }
6009
6010 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6011 assert (UseCompressedOops, "should only be used for compressed headers");
6012 assert (Universe::heap() != NULL, "java heap should be initialized");
6013 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6014 int oop_index = oop_recorder()->find_index(obj);
6015 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6016 mov_narrow_oop(dst, oop_index, rspec);
6017 }
6018
6019 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6020 assert (UseCompressedOops, "should only be used for compressed headers");
6021 assert (Universe::heap() != NULL, "java heap should be initialized");
6022 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6023 int oop_index = oop_recorder()->find_index(obj);
6024 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6025 mov_narrow_oop(dst, oop_index, rspec);
6026 }
6027
6028 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6029 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6030 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6031 int klass_index = oop_recorder()->find_index(k);
6032 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6033 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6034 }
6035
6036 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6037 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6038 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6039 int klass_index = oop_recorder()->find_index(k);
6040 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6041 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6042 }
6043
6044 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6045 assert (UseCompressedOops, "should only be used for compressed headers");
6046 assert (Universe::heap() != NULL, "java heap should be initialized");
6047 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6048 int oop_index = oop_recorder()->find_index(obj);
6049 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6050 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6051 }
6052
6053 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6054 assert (UseCompressedOops, "should only be used for compressed headers");
6055 assert (Universe::heap() != NULL, "java heap should be initialized");
6056 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6057 int oop_index = oop_recorder()->find_index(obj);
6058 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6059 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6060 }
6061
6062 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6063 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6064 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6065 int klass_index = oop_recorder()->find_index(k);
6066 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6067 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6068 }
6069
6070 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6071 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6072 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6073 int klass_index = oop_recorder()->find_index(k);
6074 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6075 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6076 }
6077
6078 void MacroAssembler::reinit_heapbase() {
6079 if (UseCompressedOops || UseCompressedClassPointers) {
6080 if (Universe::heap() != NULL) {
6081 if (Universe::narrow_oop_base() == NULL) {
6082 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6083 } else {
6084 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6085 }
6086 } else {
6087 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6088 }
6089 }
6090 }
6091
6092 #endif // _LP64
6093
6094
6095 // C2 compiled method's prolog code.
6096 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6097
6098 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6099 // NativeJump::patch_verified_entry will be able to patch out the entry
6100 // code safely. The push to verify stack depth is ok at 5 bytes,
6101 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6102 // stack bang then we must use the 6 byte frame allocation even if
6103 // we have no frame. :-(
6104 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6105
6106 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6107 // Remove word for return addr
6108 framesize -= wordSize;
6109 stack_bang_size -= wordSize;
6110
6111 // Calls to C2R adapters often do not accept exceptional returns.
6112 // We require that their callers must bang for them. But be careful, because
6113 // some VM calls (such as call site linkage) can use several kilobytes of
6114 // stack. But the stack safety zone should account for that.
6115 // See bugs 4446381, 4468289, 4497237.
6116 if (stack_bang_size > 0) {
6117 generate_stack_overflow_check(stack_bang_size);
6118
6119 // We always push rbp, so that on return to interpreter rbp, will be
6120 // restored correctly and we can correct the stack.
6121 push(rbp);
6122 // Remove word for ebp
6123 framesize -= wordSize;
6124
6125 // Create frame
6126 if (framesize) {
6127 subptr(rsp, framesize);
6128 }
6129 } else {
6130 // Create frame (force generation of a 4 byte immediate value)
6131 subptr_imm32(rsp, framesize);
6132
6133 // Save RBP register now.
6134 framesize -= wordSize;
6135 movptr(Address(rsp, framesize), rbp);
6136 }
6137
6138 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6139 framesize -= wordSize;
6140 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6141 }
6142
6143 #ifndef _LP64
6144 // If method sets FPU control word do it now
6145 if (fp_mode_24b) {
6146 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6147 }
6148 if (UseSSE >= 2 && VerifyFPU) {
6149 verify_FPU(0, "FPU stack must be clean on entry");
6150 }
6151 #endif
6152
6153 #ifdef ASSERT
6154 if (VerifyStackAtCalls) {
6155 Label L;
6156 push(rax);
6157 mov(rax, rsp);
6158 andptr(rax, StackAlignmentInBytes-1);
6159 cmpptr(rax, StackAlignmentInBytes-wordSize);
6160 pop(rax);
6161 jcc(Assembler::equal, L);
6162 STOP("Stack is not properly aligned!");
6163 bind(L);
6164 }
6165 #endif
6166
6167 }
6168
6169 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6170 // cnt - number of qwords (8-byte words).
6171 // base - start address, qword aligned.
6172 assert(base==rdi, "base register must be edi for rep stos");
6173 assert(tmp==rax, "tmp register must be eax for rep stos");
6174 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6175
6176 xorptr(tmp, tmp);
6177 if (UseFastStosb) {
6178 shlptr(cnt,3); // convert to number of bytes
6179 rep_stosb();
6180 } else {
6181 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6182 rep_stos();
6183 }
6184 }
6185
6186 // IndexOf for constant substrings with size >= 8 chars
6187 // which don't need to be loaded through stack.
6188 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6189 Register cnt1, Register cnt2,
6190 int int_cnt2, Register result,
6191 XMMRegister vec, Register tmp) {
6192 ShortBranchVerifier sbv(this);
6193 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6194
6195 // This method uses pcmpestri inxtruction with bound registers
6196 // inputs:
6197 // xmm - substring
6198 // rax - substring length (elements count)
6199 // mem - scanned string
6200 // rdx - string length (elements count)
6201 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6202 // outputs:
6203 // rcx - matched index in string
6204 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6205
6206 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6207 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6208 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6209
6210 // Note, inline_string_indexOf() generates checks:
6211 // if (substr.count > string.count) return -1;
6212 // if (substr.count == 0) return 0;
6213 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6214
6215 // Load substring.
6216 movdqu(vec, Address(str2, 0));
6217 movl(cnt2, int_cnt2);
6218 movptr(result, str1); // string addr
6219
6220 if (int_cnt2 > 8) {
6221 jmpb(SCAN_TO_SUBSTR);
6222
6223 // Reload substr for rescan, this code
6224 // is executed only for large substrings (> 8 chars)
6225 bind(RELOAD_SUBSTR);
6226 movdqu(vec, Address(str2, 0));
6227 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6228
6229 bind(RELOAD_STR);
6230 // We came here after the beginning of the substring was
6231 // matched but the rest of it was not so we need to search
6232 // again. Start from the next element after the previous match.
6233
6234 // cnt2 is number of substring reminding elements and
6235 // cnt1 is number of string reminding elements when cmp failed.
6236 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6237 subl(cnt1, cnt2);
6238 addl(cnt1, int_cnt2);
6239 movl(cnt2, int_cnt2); // Now restore cnt2
6240
6241 decrementl(cnt1); // Shift to next element
6242 cmpl(cnt1, cnt2);
6243 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6244
6245 addptr(result, 2);
6246
6247 } // (int_cnt2 > 8)
6248
6249 // Scan string for start of substr in 16-byte vectors
6250 bind(SCAN_TO_SUBSTR);
6251 pcmpestri(vec, Address(result, 0), 0x0d);
6252 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6253 subl(cnt1, 8);
6254 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6255 cmpl(cnt1, cnt2);
6256 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6257 addptr(result, 16);
6258 jmpb(SCAN_TO_SUBSTR);
6259
6260 // Found a potential substr
6261 bind(FOUND_CANDIDATE);
6262 // Matched whole vector if first element matched (tmp(rcx) == 0).
6263 if (int_cnt2 == 8) {
6264 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6265 } else { // int_cnt2 > 8
6266 jccb(Assembler::overflow, FOUND_SUBSTR);
6267 }
6268 // After pcmpestri tmp(rcx) contains matched element index
6269 // Compute start addr of substr
6270 lea(result, Address(result, tmp, Address::times_2));
6271
6272 // Make sure string is still long enough
6273 subl(cnt1, tmp);
6274 cmpl(cnt1, cnt2);
6275 if (int_cnt2 == 8) {
6276 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6277 } else { // int_cnt2 > 8
6278 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6279 }
6280 // Left less then substring.
6281
6282 bind(RET_NOT_FOUND);
6283 movl(result, -1);
6284 jmpb(EXIT);
6285
6286 if (int_cnt2 > 8) {
6287 // This code is optimized for the case when whole substring
6288 // is matched if its head is matched.
6289 bind(MATCH_SUBSTR_HEAD);
6290 pcmpestri(vec, Address(result, 0), 0x0d);
6291 // Reload only string if does not match
6292 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6293
6294 Label CONT_SCAN_SUBSTR;
6295 // Compare the rest of substring (> 8 chars).
6296 bind(FOUND_SUBSTR);
6297 // First 8 chars are already matched.
6298 negptr(cnt2);
6299 addptr(cnt2, 8);
6300
6301 bind(SCAN_SUBSTR);
6302 subl(cnt1, 8);
6303 cmpl(cnt2, -8); // Do not read beyond substring
6304 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6305 // Back-up strings to avoid reading beyond substring:
6306 // cnt1 = cnt1 - cnt2 + 8
6307 addl(cnt1, cnt2); // cnt2 is negative
6308 addl(cnt1, 8);
6309 movl(cnt2, 8); negptr(cnt2);
6310 bind(CONT_SCAN_SUBSTR);
6311 if (int_cnt2 < (int)G) {
6312 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6313 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6314 } else {
6315 // calculate index in register to avoid integer overflow (int_cnt2*2)
6316 movl(tmp, int_cnt2);
6317 addptr(tmp, cnt2);
6318 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6319 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6320 }
6321 // Need to reload strings pointers if not matched whole vector
6322 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6323 addptr(cnt2, 8);
6324 jcc(Assembler::negative, SCAN_SUBSTR);
6325 // Fall through if found full substring
6326
6327 } // (int_cnt2 > 8)
6328
6329 bind(RET_FOUND);
6330 // Found result if we matched full small substring.
6331 // Compute substr offset
6332 subptr(result, str1);
6333 shrl(result, 1); // index
6334 bind(EXIT);
6335
6336 } // string_indexofC8
6337
6338 // Small strings are loaded through stack if they cross page boundary.
6339 void MacroAssembler::string_indexof(Register str1, Register str2,
6340 Register cnt1, Register cnt2,
6341 int int_cnt2, Register result,
6342 XMMRegister vec, Register tmp) {
6343 ShortBranchVerifier sbv(this);
6344 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6345 //
6346 // int_cnt2 is length of small (< 8 chars) constant substring
6347 // or (-1) for non constant substring in which case its length
6348 // is in cnt2 register.
6349 //
6350 // Note, inline_string_indexOf() generates checks:
6351 // if (substr.count > string.count) return -1;
6352 // if (substr.count == 0) return 0;
6353 //
6354 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6355
6356 // This method uses pcmpestri inxtruction with bound registers
6357 // inputs:
6358 // xmm - substring
6359 // rax - substring length (elements count)
6360 // mem - scanned string
6361 // rdx - string length (elements count)
6362 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6363 // outputs:
6364 // rcx - matched index in string
6365 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6366
6367 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6368 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6369 FOUND_CANDIDATE;
6370
6371 { //========================================================
6372 // We don't know where these strings are located
6373 // and we can't read beyond them. Load them through stack.
6374 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6375
6376 movptr(tmp, rsp); // save old SP
6377
6378 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6379 if (int_cnt2 == 1) { // One char
6380 load_unsigned_short(result, Address(str2, 0));
6381 movdl(vec, result); // move 32 bits
6382 } else if (int_cnt2 == 2) { // Two chars
6383 movdl(vec, Address(str2, 0)); // move 32 bits
6384 } else if (int_cnt2 == 4) { // Four chars
6385 movq(vec, Address(str2, 0)); // move 64 bits
6386 } else { // cnt2 = { 3, 5, 6, 7 }
6387 // Array header size is 12 bytes in 32-bit VM
6388 // + 6 bytes for 3 chars == 18 bytes,
6389 // enough space to load vec and shift.
6390 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6391 movdqu(vec, Address(str2, (int_cnt2*2)-16));
6392 psrldq(vec, 16-(int_cnt2*2));
6393 }
6394 } else { // not constant substring
6395 cmpl(cnt2, 8);
6396 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6397
6398 // We can read beyond string if srt+16 does not cross page boundary
6399 // since heaps are aligned and mapped by pages.
6400 assert(os::vm_page_size() < (int)G, "default page should be small");
6401 movl(result, str2); // We need only low 32 bits
6402 andl(result, (os::vm_page_size()-1));
6403 cmpl(result, (os::vm_page_size()-16));
6404 jccb(Assembler::belowEqual, CHECK_STR);
6405
6406 // Move small strings to stack to allow load 16 bytes into vec.
6407 subptr(rsp, 16);
6408 int stk_offset = wordSize-2;
6409 push(cnt2);
6410
6411 bind(COPY_SUBSTR);
6412 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6413 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6414 decrement(cnt2);
6415 jccb(Assembler::notZero, COPY_SUBSTR);
6416
6417 pop(cnt2);
6418 movptr(str2, rsp); // New substring address
6419 } // non constant
6420
6421 bind(CHECK_STR);
6422 cmpl(cnt1, 8);
6423 jccb(Assembler::aboveEqual, BIG_STRINGS);
6424
6425 // Check cross page boundary.
6426 movl(result, str1); // We need only low 32 bits
6427 andl(result, (os::vm_page_size()-1));
6428 cmpl(result, (os::vm_page_size()-16));
6429 jccb(Assembler::belowEqual, BIG_STRINGS);
6430
6431 subptr(rsp, 16);
6432 int stk_offset = -2;
6433 if (int_cnt2 < 0) { // not constant
6434 push(cnt2);
6435 stk_offset += wordSize;
6436 }
6437 movl(cnt2, cnt1);
6438
6439 bind(COPY_STR);
6440 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6441 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6442 decrement(cnt2);
6443 jccb(Assembler::notZero, COPY_STR);
6444
6445 if (int_cnt2 < 0) { // not constant
6446 pop(cnt2);
6447 }
6448 movptr(str1, rsp); // New string address
6449
6450 bind(BIG_STRINGS);
6451 // Load substring.
6452 if (int_cnt2 < 0) { // -1
6453 movdqu(vec, Address(str2, 0));
6454 push(cnt2); // substr count
6455 push(str2); // substr addr
6456 push(str1); // string addr
6457 } else {
6458 // Small (< 8 chars) constant substrings are loaded already.
6459 movl(cnt2, int_cnt2);
6460 }
6461 push(tmp); // original SP
6462
6463 } // Finished loading
6464
6465 //========================================================
6466 // Start search
6467 //
6468
6469 movptr(result, str1); // string addr
6470
6471 if (int_cnt2 < 0) { // Only for non constant substring
6472 jmpb(SCAN_TO_SUBSTR);
6473
6474 // SP saved at sp+0
6475 // String saved at sp+1*wordSize
6476 // Substr saved at sp+2*wordSize
6477 // Substr count saved at sp+3*wordSize
6478
6479 // Reload substr for rescan, this code
6480 // is executed only for large substrings (> 8 chars)
6481 bind(RELOAD_SUBSTR);
6482 movptr(str2, Address(rsp, 2*wordSize));
6483 movl(cnt2, Address(rsp, 3*wordSize));
6484 movdqu(vec, Address(str2, 0));
6485 // We came here after the beginning of the substring was
6486 // matched but the rest of it was not so we need to search
6487 // again. Start from the next element after the previous match.
6488 subptr(str1, result); // Restore counter
6489 shrl(str1, 1);
6490 addl(cnt1, str1);
6491 decrementl(cnt1); // Shift to next element
6492 cmpl(cnt1, cnt2);
6493 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6494
6495 addptr(result, 2);
6496 } // non constant
6497
6498 // Scan string for start of substr in 16-byte vectors
6499 bind(SCAN_TO_SUBSTR);
6500 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6501 pcmpestri(vec, Address(result, 0), 0x0d);
6502 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6503 subl(cnt1, 8);
6504 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6505 cmpl(cnt1, cnt2);
6506 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6507 addptr(result, 16);
6508
6509 bind(ADJUST_STR);
6510 cmpl(cnt1, 8); // Do not read beyond string
6511 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6512 // Back-up string to avoid reading beyond string.
6513 lea(result, Address(result, cnt1, Address::times_2, -16));
6514 movl(cnt1, 8);
6515 jmpb(SCAN_TO_SUBSTR);
6516
6517 // Found a potential substr
6518 bind(FOUND_CANDIDATE);
6519 // After pcmpestri tmp(rcx) contains matched element index
6520
6521 // Make sure string is still long enough
6522 subl(cnt1, tmp);
6523 cmpl(cnt1, cnt2);
6524 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6525 // Left less then substring.
6526
6527 bind(RET_NOT_FOUND);
6528 movl(result, -1);
6529 jmpb(CLEANUP);
6530
6531 bind(FOUND_SUBSTR);
6532 // Compute start addr of substr
6533 lea(result, Address(result, tmp, Address::times_2));
6534
6535 if (int_cnt2 > 0) { // Constant substring
6536 // Repeat search for small substring (< 8 chars)
6537 // from new point without reloading substring.
6538 // Have to check that we don't read beyond string.
6539 cmpl(tmp, 8-int_cnt2);
6540 jccb(Assembler::greater, ADJUST_STR);
6541 // Fall through if matched whole substring.
6542 } else { // non constant
6543 assert(int_cnt2 == -1, "should be != 0");
6544
6545 addl(tmp, cnt2);
6546 // Found result if we matched whole substring.
6547 cmpl(tmp, 8);
6548 jccb(Assembler::lessEqual, RET_FOUND);
6549
6550 // Repeat search for small substring (<= 8 chars)
6551 // from new point 'str1' without reloading substring.
6552 cmpl(cnt2, 8);
6553 // Have to check that we don't read beyond string.
6554 jccb(Assembler::lessEqual, ADJUST_STR);
6555
6556 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6557 // Compare the rest of substring (> 8 chars).
6558 movptr(str1, result);
6559
6560 cmpl(tmp, cnt2);
6561 // First 8 chars are already matched.
6562 jccb(Assembler::equal, CHECK_NEXT);
6563
6564 bind(SCAN_SUBSTR);
6565 pcmpestri(vec, Address(str1, 0), 0x0d);
6566 // Need to reload strings pointers if not matched whole vector
6567 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6568
6569 bind(CHECK_NEXT);
6570 subl(cnt2, 8);
6571 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6572 addptr(str1, 16);
6573 addptr(str2, 16);
6574 subl(cnt1, 8);
6575 cmpl(cnt2, 8); // Do not read beyond substring
6576 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6577 // Back-up strings to avoid reading beyond substring.
6578 lea(str2, Address(str2, cnt2, Address::times_2, -16));
6579 lea(str1, Address(str1, cnt2, Address::times_2, -16));
6580 subl(cnt1, cnt2);
6581 movl(cnt2, 8);
6582 addl(cnt1, 8);
6583 bind(CONT_SCAN_SUBSTR);
6584 movdqu(vec, Address(str2, 0));
6585 jmpb(SCAN_SUBSTR);
6586
6587 bind(RET_FOUND_LONG);
6588 movptr(str1, Address(rsp, wordSize));
6589 } // non constant
6590
6591 bind(RET_FOUND);
6592 // Compute substr offset
6593 subptr(result, str1);
6594 shrl(result, 1); // index
6595
6596 bind(CLEANUP);
6597 pop(rsp); // restore SP
6598
6599 } // string_indexof
6600
6601 // Compare strings.
6602 void MacroAssembler::string_compare(Register str1, Register str2,
6603 Register cnt1, Register cnt2, Register result,
6604 XMMRegister vec1) {
6605 ShortBranchVerifier sbv(this);
6606 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6607
6608 // Compute the minimum of the string lengths and the
6609 // difference of the string lengths (stack).
6610 // Do the conditional move stuff
6611 movl(result, cnt1);
6612 subl(cnt1, cnt2);
6613 push(cnt1);
6614 cmov32(Assembler::lessEqual, cnt2, result);
6615
6616 // Is the minimum length zero?
6617 testl(cnt2, cnt2);
6618 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6619
6620 // Compare first characters
6621 load_unsigned_short(result, Address(str1, 0));
6622 load_unsigned_short(cnt1, Address(str2, 0));
6623 subl(result, cnt1);
6624 jcc(Assembler::notZero, POP_LABEL);
6625 cmpl(cnt2, 1);
6626 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6627
6628 // Check if the strings start at the same location.
6629 cmpptr(str1, str2);
6630 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6631
6632 Address::ScaleFactor scale = Address::times_2;
6633 int stride = 8;
6634
6635 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6636 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6637 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6638 Label COMPARE_TAIL_LONG;
6639 int pcmpmask = 0x19;
6640
6641 // Setup to compare 16-chars (32-bytes) vectors,
6642 // start from first character again because it has aligned address.
6643 int stride2 = 16;
6644 int adr_stride = stride << scale;
6645 int adr_stride2 = stride2 << scale;
6646
6647 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6648 // rax and rdx are used by pcmpestri as elements counters
6649 movl(result, cnt2);
6650 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6651 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6652
6653 // fast path : compare first 2 8-char vectors.
6654 bind(COMPARE_16_CHARS);
6655 movdqu(vec1, Address(str1, 0));
6656 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6657 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6658
6659 movdqu(vec1, Address(str1, adr_stride));
6660 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6661 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6662 addl(cnt1, stride);
6663
6664 // Compare the characters at index in cnt1
6665 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6666 load_unsigned_short(result, Address(str1, cnt1, scale));
6667 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6668 subl(result, cnt2);
6669 jmp(POP_LABEL);
6670
6671 // Setup the registers to start vector comparison loop
6672 bind(COMPARE_WIDE_VECTORS);
6673 lea(str1, Address(str1, result, scale));
6674 lea(str2, Address(str2, result, scale));
6675 subl(result, stride2);
6676 subl(cnt2, stride2);
6677 jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6678 negptr(result);
6679
6680 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6681 bind(COMPARE_WIDE_VECTORS_LOOP);
6682 vmovdqu(vec1, Address(str1, result, scale));
6683 vpxor(vec1, Address(str2, result, scale));
6684 vptest(vec1, vec1);
6685 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6686 addptr(result, stride2);
6687 subl(cnt2, stride2);
6688 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6689 // clean upper bits of YMM registers
6690 vzeroupper();
6691
6692 // compare wide vectors tail
6693 bind(COMPARE_WIDE_TAIL);
6694 testptr(result, result);
6695 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6696
6697 movl(result, stride2);
6698 movl(cnt2, result);
6699 negptr(result);
6700 jmpb(COMPARE_WIDE_VECTORS_LOOP);
6701
6702 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6703 bind(VECTOR_NOT_EQUAL);
6704 // clean upper bits of YMM registers
6705 vzeroupper();
6706 lea(str1, Address(str1, result, scale));
6707 lea(str2, Address(str2, result, scale));
6708 jmp(COMPARE_16_CHARS);
6709
6710 // Compare tail chars, length between 1 to 15 chars
6711 bind(COMPARE_TAIL_LONG);
6712 movl(cnt2, result);
6713 cmpl(cnt2, stride);
6714 jccb(Assembler::less, COMPARE_SMALL_STR);
6715
6716 movdqu(vec1, Address(str1, 0));
6717 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6718 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6719 subptr(cnt2, stride);
6720 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6721 lea(str1, Address(str1, result, scale));
6722 lea(str2, Address(str2, result, scale));
6723 negptr(cnt2);
6724 jmpb(WHILE_HEAD_LABEL);
6725
6726 bind(COMPARE_SMALL_STR);
6727 } else if (UseSSE42Intrinsics) {
6728 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6729 int pcmpmask = 0x19;
6730 // Setup to compare 8-char (16-byte) vectors,
6731 // start from first character again because it has aligned address.
6732 movl(result, cnt2);
6733 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6734 jccb(Assembler::zero, COMPARE_TAIL);
6735
6736 lea(str1, Address(str1, result, scale));
6737 lea(str2, Address(str2, result, scale));
6738 negptr(result);
6739
6740 // pcmpestri
6741 // inputs:
6742 // vec1- substring
6743 // rax - negative string length (elements count)
6744 // mem - scaned string
6745 // rdx - string length (elements count)
6746 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6747 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6748 // outputs:
6749 // rcx - first mismatched element index
6750 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6751
6752 bind(COMPARE_WIDE_VECTORS);
6753 movdqu(vec1, Address(str1, result, scale));
6754 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6755 // After pcmpestri cnt1(rcx) contains mismatched element index
6756
6757 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6758 addptr(result, stride);
6759 subptr(cnt2, stride);
6760 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6761
6762 // compare wide vectors tail
6763 testptr(result, result);
6764 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6765
6766 movl(cnt2, stride);
6767 movl(result, stride);
6768 negptr(result);
6769 movdqu(vec1, Address(str1, result, scale));
6770 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6771 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6772
6773 // Mismatched characters in the vectors
6774 bind(VECTOR_NOT_EQUAL);
6775 addptr(cnt1, result);
6776 load_unsigned_short(result, Address(str1, cnt1, scale));
6777 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6778 subl(result, cnt2);
6779 jmpb(POP_LABEL);
6780
6781 bind(COMPARE_TAIL); // limit is zero
6782 movl(cnt2, result);
6783 // Fallthru to tail compare
6784 }
6785 // Shift str2 and str1 to the end of the arrays, negate min
6786 lea(str1, Address(str1, cnt2, scale));
6787 lea(str2, Address(str2, cnt2, scale));
6788 decrementl(cnt2); // first character was compared already
6789 negptr(cnt2);
6790
6791 // Compare the rest of the elements
6792 bind(WHILE_HEAD_LABEL);
6793 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
6794 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
6795 subl(result, cnt1);
6796 jccb(Assembler::notZero, POP_LABEL);
6797 increment(cnt2);
6798 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6799
6800 // Strings are equal up to min length. Return the length difference.
6801 bind(LENGTH_DIFF_LABEL);
6802 pop(result);
6803 jmpb(DONE_LABEL);
6804
6805 // Discard the stored length difference
6806 bind(POP_LABEL);
6807 pop(cnt1);
6808
6809 // That's it
6810 bind(DONE_LABEL);
6811 }
6812
6813 // Compare char[] arrays aligned to 4 bytes or substrings.
6814 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6815 Register limit, Register result, Register chr,
6816 XMMRegister vec1, XMMRegister vec2) {
6817 ShortBranchVerifier sbv(this);
6818 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
6819
6820 int length_offset = arrayOopDesc::length_offset_in_bytes();
6821 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
6822
6823 // Check the input args
6824 cmpptr(ary1, ary2);
6825 jcc(Assembler::equal, TRUE_LABEL);
6826
6827 if (is_array_equ) {
6828 // Need additional checks for arrays_equals.
6829 testptr(ary1, ary1);
6830 jcc(Assembler::zero, FALSE_LABEL);
6831 testptr(ary2, ary2);
6832 jcc(Assembler::zero, FALSE_LABEL);
6833
6834 // Check the lengths
6835 movl(limit, Address(ary1, length_offset));
6836 cmpl(limit, Address(ary2, length_offset));
6837 jcc(Assembler::notEqual, FALSE_LABEL);
6838 }
6839
6840 // count == 0
6841 testl(limit, limit);
6842 jcc(Assembler::zero, TRUE_LABEL);
6843
6844 if (is_array_equ) {
6845 // Load array address
6846 lea(ary1, Address(ary1, base_offset));
6847 lea(ary2, Address(ary2, base_offset));
6848 }
6849
6850 shll(limit, 1); // byte count != 0
6851 movl(result, limit); // copy
6852
6853 if (UseAVX >= 2) {
6854 // With AVX2, use 32-byte vector compare
6855 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6856
6857 // Compare 32-byte vectors
6858 andl(result, 0x0000001e); // tail count (in bytes)
6859 andl(limit, 0xffffffe0); // vector count (in bytes)
6860 jccb(Assembler::zero, COMPARE_TAIL);
6861
6862 lea(ary1, Address(ary1, limit, Address::times_1));
6863 lea(ary2, Address(ary2, limit, Address::times_1));
6864 negptr(limit);
6865
6866 bind(COMPARE_WIDE_VECTORS);
6867 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6868 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6869 vpxor(vec1, vec2);
6870
6871 vptest(vec1, vec1);
6872 jccb(Assembler::notZero, FALSE_LABEL);
6873 addptr(limit, 32);
6874 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6875
6876 testl(result, result);
6877 jccb(Assembler::zero, TRUE_LABEL);
6878
6879 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6880 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6881 vpxor(vec1, vec2);
6882
6883 vptest(vec1, vec1);
6884 jccb(Assembler::notZero, FALSE_LABEL);
6885 jmpb(TRUE_LABEL);
6886
6887 bind(COMPARE_TAIL); // limit is zero
6888 movl(limit, result);
6889 // Fallthru to tail compare
6890 } else if (UseSSE42Intrinsics) {
6891 // With SSE4.2, use double quad vector compare
6892 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6893
6894 // Compare 16-byte vectors
6895 andl(result, 0x0000000e); // tail count (in bytes)
6896 andl(limit, 0xfffffff0); // vector count (in bytes)
6897 jccb(Assembler::zero, COMPARE_TAIL);
6898
6899 lea(ary1, Address(ary1, limit, Address::times_1));
6900 lea(ary2, Address(ary2, limit, Address::times_1));
6901 negptr(limit);
6902
6903 bind(COMPARE_WIDE_VECTORS);
6904 movdqu(vec1, Address(ary1, limit, Address::times_1));
6905 movdqu(vec2, Address(ary2, limit, Address::times_1));
6906 pxor(vec1, vec2);
6907
6908 ptest(vec1, vec1);
6909 jccb(Assembler::notZero, FALSE_LABEL);
6910 addptr(limit, 16);
6911 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6912
6913 testl(result, result);
6914 jccb(Assembler::zero, TRUE_LABEL);
6915
6916 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6917 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
6918 pxor(vec1, vec2);
6919
6920 ptest(vec1, vec1);
6921 jccb(Assembler::notZero, FALSE_LABEL);
6922 jmpb(TRUE_LABEL);
6923
6924 bind(COMPARE_TAIL); // limit is zero
6925 movl(limit, result);
6926 // Fallthru to tail compare
6927 }
6928
6929 // Compare 4-byte vectors
6930 andl(limit, 0xfffffffc); // vector count (in bytes)
6931 jccb(Assembler::zero, COMPARE_CHAR);
6932
6933 lea(ary1, Address(ary1, limit, Address::times_1));
6934 lea(ary2, Address(ary2, limit, Address::times_1));
6935 negptr(limit);
6936
6937 bind(COMPARE_VECTORS);
6938 movl(chr, Address(ary1, limit, Address::times_1));
6939 cmpl(chr, Address(ary2, limit, Address::times_1));
6940 jccb(Assembler::notEqual, FALSE_LABEL);
6941 addptr(limit, 4);
6942 jcc(Assembler::notZero, COMPARE_VECTORS);
6943
6944 // Compare trailing char (final 2 bytes), if any
6945 bind(COMPARE_CHAR);
6946 testl(result, 0x2); // tail char
6947 jccb(Assembler::zero, TRUE_LABEL);
6948 load_unsigned_short(chr, Address(ary1, 0));
6949 load_unsigned_short(limit, Address(ary2, 0));
6950 cmpl(chr, limit);
6951 jccb(Assembler::notEqual, FALSE_LABEL);
6952
6953 bind(TRUE_LABEL);
6954 movl(result, 1); // return true
6955 jmpb(DONE);
6956
6957 bind(FALSE_LABEL);
6958 xorl(result, result); // return false
6959
6960 // That's it
6961 bind(DONE);
6962 if (UseAVX >= 2) {
6963 // clean upper bits of YMM registers
6964 vzeroupper();
6965 }
6966 }
6967
6968 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6969 Register to, Register value, Register count,
6970 Register rtmp, XMMRegister xtmp) {
6971 ShortBranchVerifier sbv(this);
6972 assert_different_registers(to, value, count, rtmp);
6973 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
6974 Label L_fill_2_bytes, L_fill_4_bytes;
6975
6976 int shift = -1;
6977 switch (t) {
6978 case T_BYTE:
6979 shift = 2;
6980 break;
6981 case T_SHORT:
6982 shift = 1;
6983 break;
6984 case T_INT:
6985 shift = 0;
6986 break;
6987 default: ShouldNotReachHere();
6988 }
6989
6990 if (t == T_BYTE) {
6991 andl(value, 0xff);
6992 movl(rtmp, value);
6993 shll(rtmp, 8);
6994 orl(value, rtmp);
6995 }
6996 if (t == T_SHORT) {
6997 andl(value, 0xffff);
6998 }
6999 if (t == T_BYTE || t == T_SHORT) {
7000 movl(rtmp, value);
7001 shll(rtmp, 16);
7002 orl(value, rtmp);
7003 }
7004
7005 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7006 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7007 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7008 // align source address at 4 bytes address boundary
7009 if (t == T_BYTE) {
7010 // One byte misalignment happens only for byte arrays
7011 testptr(to, 1);
7012 jccb(Assembler::zero, L_skip_align1);
7013 movb(Address(to, 0), value);
7014 increment(to);
7015 decrement(count);
7016 BIND(L_skip_align1);
7017 }
7018 // Two bytes misalignment happens only for byte and short (char) arrays
7019 testptr(to, 2);
7020 jccb(Assembler::zero, L_skip_align2);
7021 movw(Address(to, 0), value);
7022 addptr(to, 2);
7023 subl(count, 1<<(shift-1));
7024 BIND(L_skip_align2);
7025 }
7026 if (UseSSE < 2) {
7027 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7028 // Fill 32-byte chunks
7029 subl(count, 8 << shift);
7030 jcc(Assembler::less, L_check_fill_8_bytes);
7031 align(16);
7032
7033 BIND(L_fill_32_bytes_loop);
7034
7035 for (int i = 0; i < 32; i += 4) {
7036 movl(Address(to, i), value);
7037 }
7038
7039 addptr(to, 32);
7040 subl(count, 8 << shift);
7041 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7042 BIND(L_check_fill_8_bytes);
7043 addl(count, 8 << shift);
7044 jccb(Assembler::zero, L_exit);
7045 jmpb(L_fill_8_bytes);
7046
7047 //
7048 // length is too short, just fill qwords
7049 //
7050 BIND(L_fill_8_bytes_loop);
7051 movl(Address(to, 0), value);
7052 movl(Address(to, 4), value);
7053 addptr(to, 8);
7054 BIND(L_fill_8_bytes);
7055 subl(count, 1 << (shift + 1));
7056 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7057 // fall through to fill 4 bytes
7058 } else {
7059 Label L_fill_32_bytes;
7060 if (!UseUnalignedLoadStores) {
7061 // align to 8 bytes, we know we are 4 byte aligned to start
7062 testptr(to, 4);
7063 jccb(Assembler::zero, L_fill_32_bytes);
7064 movl(Address(to, 0), value);
7065 addptr(to, 4);
7066 subl(count, 1<<shift);
7067 }
7068 BIND(L_fill_32_bytes);
7069 {
7070 assert( UseSSE >= 2, "supported cpu only" );
7071 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7072 movdl(xtmp, value);
7073 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7074 // Fill 64-byte chunks
7075 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7076 vpbroadcastd(xtmp, xtmp);
7077
7078 subl(count, 16 << shift);
7079 jcc(Assembler::less, L_check_fill_32_bytes);
7080 align(16);
7081
7082 BIND(L_fill_64_bytes_loop);
7083 vmovdqu(Address(to, 0), xtmp);
7084 vmovdqu(Address(to, 32), xtmp);
7085 addptr(to, 64);
7086 subl(count, 16 << shift);
7087 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7088
7089 BIND(L_check_fill_32_bytes);
7090 addl(count, 8 << shift);
7091 jccb(Assembler::less, L_check_fill_8_bytes);
7092 vmovdqu(Address(to, 0), xtmp);
7093 addptr(to, 32);
7094 subl(count, 8 << shift);
7095
7096 BIND(L_check_fill_8_bytes);
7097 // clean upper bits of YMM registers
7098 vzeroupper();
7099 } else {
7100 // Fill 32-byte chunks
7101 pshufd(xtmp, xtmp, 0);
7102
7103 subl(count, 8 << shift);
7104 jcc(Assembler::less, L_check_fill_8_bytes);
7105 align(16);
7106
7107 BIND(L_fill_32_bytes_loop);
7108
7109 if (UseUnalignedLoadStores) {
7110 movdqu(Address(to, 0), xtmp);
7111 movdqu(Address(to, 16), xtmp);
7112 } else {
7113 movq(Address(to, 0), xtmp);
7114 movq(Address(to, 8), xtmp);
7115 movq(Address(to, 16), xtmp);
7116 movq(Address(to, 24), xtmp);
7117 }
7118
7119 addptr(to, 32);
7120 subl(count, 8 << shift);
7121 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7122
7123 BIND(L_check_fill_8_bytes);
7124 }
7125 addl(count, 8 << shift);
7126 jccb(Assembler::zero, L_exit);
7127 jmpb(L_fill_8_bytes);
7128
7129 //
7130 // length is too short, just fill qwords
7131 //
7132 BIND(L_fill_8_bytes_loop);
7133 movq(Address(to, 0), xtmp);
7134 addptr(to, 8);
7135 BIND(L_fill_8_bytes);
7136 subl(count, 1 << (shift + 1));
7137 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7138 }
7139 }
7140 // fill trailing 4 bytes
7141 BIND(L_fill_4_bytes);
7142 testl(count, 1<<shift);
7143 jccb(Assembler::zero, L_fill_2_bytes);
7144 movl(Address(to, 0), value);
7145 if (t == T_BYTE || t == T_SHORT) {
7146 addptr(to, 4);
7147 BIND(L_fill_2_bytes);
7148 // fill trailing 2 bytes
7149 testl(count, 1<<(shift-1));
7150 jccb(Assembler::zero, L_fill_byte);
7151 movw(Address(to, 0), value);
7152 if (t == T_BYTE) {
7153 addptr(to, 2);
7154 BIND(L_fill_byte);
7155 // fill trailing byte
7156 testl(count, 1);
7157 jccb(Assembler::zero, L_exit);
7158 movb(Address(to, 0), value);
7159 } else {
7160 BIND(L_fill_byte);
7161 }
7162 } else {
7163 BIND(L_fill_2_bytes);
7164 }
7165 BIND(L_exit);
7166 }
7167
7168 // encode char[] to byte[] in ISO_8859_1
7169 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7170 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7171 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7172 Register tmp5, Register result) {
7173 // rsi: src
7174 // rdi: dst
7175 // rdx: len
7176 // rcx: tmp5
7177 // rax: result
7178 ShortBranchVerifier sbv(this);
7179 assert_different_registers(src, dst, len, tmp5, result);
7180 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7181
7182 // set result
7183 xorl(result, result);
7184 // check for zero length
7185 testl(len, len);
7186 jcc(Assembler::zero, L_done);
7187 movl(result, len);
7188
7189 // Setup pointers
7190 lea(src, Address(src, len, Address::times_2)); // char[]
7191 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7192 negptr(len);
7193
7194 if (UseSSE42Intrinsics || UseAVX >= 2) {
7195 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7196 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7197
7198 if (UseAVX >= 2) {
7199 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7200 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7201 movdl(tmp1Reg, tmp5);
7202 vpbroadcastd(tmp1Reg, tmp1Reg);
7203 jmpb(L_chars_32_check);
7204
7205 bind(L_copy_32_chars);
7206 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7207 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7208 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7209 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7210 jccb(Assembler::notZero, L_copy_32_chars_exit);
7211 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7212 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector256 */ true);
7213 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7214
7215 bind(L_chars_32_check);
7216 addptr(len, 32);
7217 jccb(Assembler::lessEqual, L_copy_32_chars);
7218
7219 bind(L_copy_32_chars_exit);
7220 subptr(len, 16);
7221 jccb(Assembler::greater, L_copy_16_chars_exit);
7222
7223 } else if (UseSSE42Intrinsics) {
7224 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7225 movdl(tmp1Reg, tmp5);
7226 pshufd(tmp1Reg, tmp1Reg, 0);
7227 jmpb(L_chars_16_check);
7228 }
7229
7230 bind(L_copy_16_chars);
7231 if (UseAVX >= 2) {
7232 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7233 vptest(tmp2Reg, tmp1Reg);
7234 jccb(Assembler::notZero, L_copy_16_chars_exit);
7235 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector256 */ true);
7236 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector256 */ true);
7237 } else {
7238 if (UseAVX > 0) {
7239 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7240 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7241 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ false);
7242 } else {
7243 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7244 por(tmp2Reg, tmp3Reg);
7245 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7246 por(tmp2Reg, tmp4Reg);
7247 }
7248 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7249 jccb(Assembler::notZero, L_copy_16_chars_exit);
7250 packuswb(tmp3Reg, tmp4Reg);
7251 }
7252 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7253
7254 bind(L_chars_16_check);
7255 addptr(len, 16);
7256 jccb(Assembler::lessEqual, L_copy_16_chars);
7257
7258 bind(L_copy_16_chars_exit);
7259 if (UseAVX >= 2) {
7260 // clean upper bits of YMM registers
7261 vzeroupper();
7262 }
7263 subptr(len, 8);
7264 jccb(Assembler::greater, L_copy_8_chars_exit);
7265
7266 bind(L_copy_8_chars);
7267 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7268 ptest(tmp3Reg, tmp1Reg);
7269 jccb(Assembler::notZero, L_copy_8_chars_exit);
7270 packuswb(tmp3Reg, tmp1Reg);
7271 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7272 addptr(len, 8);
7273 jccb(Assembler::lessEqual, L_copy_8_chars);
7274
7275 bind(L_copy_8_chars_exit);
7276 subptr(len, 8);
7277 jccb(Assembler::zero, L_done);
7278 }
7279
7280 bind(L_copy_1_char);
7281 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7282 testl(tmp5, 0xff00); // check if Unicode char
7283 jccb(Assembler::notZero, L_copy_1_char_exit);
7284 movb(Address(dst, len, Address::times_1, 0), tmp5);
7285 addptr(len, 1);
7286 jccb(Assembler::less, L_copy_1_char);
7287
7288 bind(L_copy_1_char_exit);
7289 addptr(result, len); // len is negative count of not processed elements
7290 bind(L_done);
7291 }
7292
7293 #ifdef _LP64
7294 /**
7295 * Helper for multiply_to_len().
7296 */
7297 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7298 addq(dest_lo, src1);
7299 adcq(dest_hi, 0);
7300 addq(dest_lo, src2);
7301 adcq(dest_hi, 0);
7302 }
7303
7304 /**
7305 * Multiply 64 bit by 64 bit first loop.
7306 */
7307 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7308 Register y, Register y_idx, Register z,
7309 Register carry, Register product,
7310 Register idx, Register kdx) {
7311 //
7312 // jlong carry, x[], y[], z[];
7313 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7314 // huge_128 product = y[idx] * x[xstart] + carry;
7315 // z[kdx] = (jlong)product;
7316 // carry = (jlong)(product >>> 64);
7317 // }
7318 // z[xstart] = carry;
7319 //
7320
7321 Label L_first_loop, L_first_loop_exit;
7322 Label L_one_x, L_one_y, L_multiply;
7323
7324 decrementl(xstart);
7325 jcc(Assembler::negative, L_one_x);
7326
7327 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7328 rorq(x_xstart, 32); // convert big-endian to little-endian
7329
7330 bind(L_first_loop);
7331 decrementl(idx);
7332 jcc(Assembler::negative, L_first_loop_exit);
7333 decrementl(idx);
7334 jcc(Assembler::negative, L_one_y);
7335 movq(y_idx, Address(y, idx, Address::times_4, 0));
7336 rorq(y_idx, 32); // convert big-endian to little-endian
7337 bind(L_multiply);
7338 movq(product, x_xstart);
7339 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7340 addq(product, carry);
7341 adcq(rdx, 0);
7342 subl(kdx, 2);
7343 movl(Address(z, kdx, Address::times_4, 4), product);
7344 shrq(product, 32);
7345 movl(Address(z, kdx, Address::times_4, 0), product);
7346 movq(carry, rdx);
7347 jmp(L_first_loop);
7348
7349 bind(L_one_y);
7350 movl(y_idx, Address(y, 0));
7351 jmp(L_multiply);
7352
7353 bind(L_one_x);
7354 movl(x_xstart, Address(x, 0));
7355 jmp(L_first_loop);
7356
7357 bind(L_first_loop_exit);
7358 }
7359
7360 /**
7361 * Multiply 64 bit by 64 bit and add 128 bit.
7362 */
7363 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7364 Register yz_idx, Register idx,
7365 Register carry, Register product, int offset) {
7366 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7367 // z[kdx] = (jlong)product;
7368
7369 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7370 rorq(yz_idx, 32); // convert big-endian to little-endian
7371 movq(product, x_xstart);
7372 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7373 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7374 rorq(yz_idx, 32); // convert big-endian to little-endian
7375
7376 add2_with_carry(rdx, product, carry, yz_idx);
7377
7378 movl(Address(z, idx, Address::times_4, offset+4), product);
7379 shrq(product, 32);
7380 movl(Address(z, idx, Address::times_4, offset), product);
7381
7382 }
7383
7384 /**
7385 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7386 */
7387 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7388 Register yz_idx, Register idx, Register jdx,
7389 Register carry, Register product,
7390 Register carry2) {
7391 // jlong carry, x[], y[], z[];
7392 // int kdx = ystart+1;
7393 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7394 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7395 // z[kdx+idx+1] = (jlong)product;
7396 // jlong carry2 = (jlong)(product >>> 64);
7397 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7398 // z[kdx+idx] = (jlong)product;
7399 // carry = (jlong)(product >>> 64);
7400 // }
7401 // idx += 2;
7402 // if (idx > 0) {
7403 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7404 // z[kdx+idx] = (jlong)product;
7405 // carry = (jlong)(product >>> 64);
7406 // }
7407 //
7408
7409 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7410
7411 movl(jdx, idx);
7412 andl(jdx, 0xFFFFFFFC);
7413 shrl(jdx, 2);
7414
7415 bind(L_third_loop);
7416 subl(jdx, 1);
7417 jcc(Assembler::negative, L_third_loop_exit);
7418 subl(idx, 4);
7419
7420 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7421 movq(carry2, rdx);
7422
7423 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7424 movq(carry, rdx);
7425 jmp(L_third_loop);
7426
7427 bind (L_third_loop_exit);
7428
7429 andl (idx, 0x3);
7430 jcc(Assembler::zero, L_post_third_loop_done);
7431
7432 Label L_check_1;
7433 subl(idx, 2);
7434 jcc(Assembler::negative, L_check_1);
7435
7436 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7437 movq(carry, rdx);
7438
7439 bind (L_check_1);
7440 addl (idx, 0x2);
7441 andl (idx, 0x1);
7442 subl(idx, 1);
7443 jcc(Assembler::negative, L_post_third_loop_done);
7444
7445 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7446 movq(product, x_xstart);
7447 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7448 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7449
7450 add2_with_carry(rdx, product, yz_idx, carry);
7451
7452 movl(Address(z, idx, Address::times_4, 0), product);
7453 shrq(product, 32);
7454
7455 shlq(rdx, 32);
7456 orq(product, rdx);
7457 movq(carry, product);
7458
7459 bind(L_post_third_loop_done);
7460 }
7461
7462 /**
7463 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7464 *
7465 */
7466 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7467 Register carry, Register carry2,
7468 Register idx, Register jdx,
7469 Register yz_idx1, Register yz_idx2,
7470 Register tmp, Register tmp3, Register tmp4) {
7471 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7472
7473 // jlong carry, x[], y[], z[];
7474 // int kdx = ystart+1;
7475 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7476 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7477 // jlong carry2 = (jlong)(tmp3 >>> 64);
7478 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7479 // carry = (jlong)(tmp4 >>> 64);
7480 // z[kdx+idx+1] = (jlong)tmp3;
7481 // z[kdx+idx] = (jlong)tmp4;
7482 // }
7483 // idx += 2;
7484 // if (idx > 0) {
7485 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7486 // z[kdx+idx] = (jlong)yz_idx1;
7487 // carry = (jlong)(yz_idx1 >>> 64);
7488 // }
7489 //
7490
7491 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7492
7493 movl(jdx, idx);
7494 andl(jdx, 0xFFFFFFFC);
7495 shrl(jdx, 2);
7496
7497 bind(L_third_loop);
7498 subl(jdx, 1);
7499 jcc(Assembler::negative, L_third_loop_exit);
7500 subl(idx, 4);
7501
7502 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7503 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7504 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7505 rorxq(yz_idx2, yz_idx2, 32);
7506
7507 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7508 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7509
7510 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7511 rorxq(yz_idx1, yz_idx1, 32);
7512 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7513 rorxq(yz_idx2, yz_idx2, 32);
7514
7515 if (VM_Version::supports_adx()) {
7516 adcxq(tmp3, carry);
7517 adoxq(tmp3, yz_idx1);
7518
7519 adcxq(tmp4, tmp);
7520 adoxq(tmp4, yz_idx2);
7521
7522 movl(carry, 0); // does not affect flags
7523 adcxq(carry2, carry);
7524 adoxq(carry2, carry);
7525 } else {
7526 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7527 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7528 }
7529 movq(carry, carry2);
7530
7531 movl(Address(z, idx, Address::times_4, 12), tmp3);
7532 shrq(tmp3, 32);
7533 movl(Address(z, idx, Address::times_4, 8), tmp3);
7534
7535 movl(Address(z, idx, Address::times_4, 4), tmp4);
7536 shrq(tmp4, 32);
7537 movl(Address(z, idx, Address::times_4, 0), tmp4);
7538
7539 jmp(L_third_loop);
7540
7541 bind (L_third_loop_exit);
7542
7543 andl (idx, 0x3);
7544 jcc(Assembler::zero, L_post_third_loop_done);
7545
7546 Label L_check_1;
7547 subl(idx, 2);
7548 jcc(Assembler::negative, L_check_1);
7549
7550 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7551 rorxq(yz_idx1, yz_idx1, 32);
7552 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7553 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7554 rorxq(yz_idx2, yz_idx2, 32);
7555
7556 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7557
7558 movl(Address(z, idx, Address::times_4, 4), tmp3);
7559 shrq(tmp3, 32);
7560 movl(Address(z, idx, Address::times_4, 0), tmp3);
7561 movq(carry, tmp4);
7562
7563 bind (L_check_1);
7564 addl (idx, 0x2);
7565 andl (idx, 0x1);
7566 subl(idx, 1);
7567 jcc(Assembler::negative, L_post_third_loop_done);
7568 movl(tmp4, Address(y, idx, Address::times_4, 0));
7569 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7570 movl(tmp4, Address(z, idx, Address::times_4, 0));
7571
7572 add2_with_carry(carry2, tmp3, tmp4, carry);
7573
7574 movl(Address(z, idx, Address::times_4, 0), tmp3);
7575 shrq(tmp3, 32);
7576
7577 shlq(carry2, 32);
7578 orq(tmp3, carry2);
7579 movq(carry, tmp3);
7580
7581 bind(L_post_third_loop_done);
7582 }
7583
7584 /**
7585 * Code for BigInteger::multiplyToLen() instrinsic.
7586 *
7587 * rdi: x
7588 * rax: xlen
7589 * rsi: y
7590 * rcx: ylen
7591 * r8: z
7592 * r11: zlen
7593 * r12: tmp1
7594 * r13: tmp2
7595 * r14: tmp3
7596 * r15: tmp4
7597 * rbx: tmp5
7598 *
7599 */
7600 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7601 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7602 ShortBranchVerifier sbv(this);
7603 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7604
7605 push(tmp1);
7606 push(tmp2);
7607 push(tmp3);
7608 push(tmp4);
7609 push(tmp5);
7610
7611 push(xlen);
7612 push(zlen);
7613
7614 const Register idx = tmp1;
7615 const Register kdx = tmp2;
7616 const Register xstart = tmp3;
7617
7618 const Register y_idx = tmp4;
7619 const Register carry = tmp5;
7620 const Register product = xlen;
7621 const Register x_xstart = zlen; // reuse register
7622
7623 // First Loop.
7624 //
7625 // final static long LONG_MASK = 0xffffffffL;
7626 // int xstart = xlen - 1;
7627 // int ystart = ylen - 1;
7628 // long carry = 0;
7629 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7630 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7631 // z[kdx] = (int)product;
7632 // carry = product >>> 32;
7633 // }
7634 // z[xstart] = (int)carry;
7635 //
7636
7637 movl(idx, ylen); // idx = ylen;
7638 movl(kdx, zlen); // kdx = xlen+ylen;
7639 xorq(carry, carry); // carry = 0;
7640
7641 Label L_done;
7642
7643 movl(xstart, xlen);
7644 decrementl(xstart);
7645 jcc(Assembler::negative, L_done);
7646
7647 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7648
7649 Label L_second_loop;
7650 testl(kdx, kdx);
7651 jcc(Assembler::zero, L_second_loop);
7652
7653 Label L_carry;
7654 subl(kdx, 1);
7655 jcc(Assembler::zero, L_carry);
7656
7657 movl(Address(z, kdx, Address::times_4, 0), carry);
7658 shrq(carry, 32);
7659 subl(kdx, 1);
7660
7661 bind(L_carry);
7662 movl(Address(z, kdx, Address::times_4, 0), carry);
7663
7664 // Second and third (nested) loops.
7665 //
7666 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7667 // carry = 0;
7668 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7669 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7670 // (z[k] & LONG_MASK) + carry;
7671 // z[k] = (int)product;
7672 // carry = product >>> 32;
7673 // }
7674 // z[i] = (int)carry;
7675 // }
7676 //
7677 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7678
7679 const Register jdx = tmp1;
7680
7681 bind(L_second_loop);
7682 xorl(carry, carry); // carry = 0;
7683 movl(jdx, ylen); // j = ystart+1
7684
7685 subl(xstart, 1); // i = xstart-1;
7686 jcc(Assembler::negative, L_done);
7687
7688 push (z);
7689
7690 Label L_last_x;
7691 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7692 subl(xstart, 1); // i = xstart-1;
7693 jcc(Assembler::negative, L_last_x);
7694
7695 if (UseBMI2Instructions) {
7696 movq(rdx, Address(x, xstart, Address::times_4, 0));
7697 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7698 } else {
7699 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7700 rorq(x_xstart, 32); // convert big-endian to little-endian
7701 }
7702
7703 Label L_third_loop_prologue;
7704 bind(L_third_loop_prologue);
7705
7706 push (x);
7707 push (xstart);
7708 push (ylen);
7709
7710
7711 if (UseBMI2Instructions) {
7712 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7713 } else { // !UseBMI2Instructions
7714 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7715 }
7716
7717 pop(ylen);
7718 pop(xlen);
7719 pop(x);
7720 pop(z);
7721
7722 movl(tmp3, xlen);
7723 addl(tmp3, 1);
7724 movl(Address(z, tmp3, Address::times_4, 0), carry);
7725 subl(tmp3, 1);
7726 jccb(Assembler::negative, L_done);
7727
7728 shrq(carry, 32);
7729 movl(Address(z, tmp3, Address::times_4, 0), carry);
7730 jmp(L_second_loop);
7731
7732 // Next infrequent code is moved outside loops.
7733 bind(L_last_x);
7734 if (UseBMI2Instructions) {
7735 movl(rdx, Address(x, 0));
7736 } else {
7737 movl(x_xstart, Address(x, 0));
7738 }
7739 jmp(L_third_loop_prologue);
7740
7741 bind(L_done);
7742
7743 pop(zlen);
7744 pop(xlen);
7745
7746 pop(tmp5);
7747 pop(tmp4);
7748 pop(tmp3);
7749 pop(tmp2);
7750 pop(tmp1);
7751 }
7752 #endif
7753
7754 /**
7755 * Emits code to update CRC-32 with a byte value according to constants in table
7756 *
7757 * @param [in,out]crc Register containing the crc.
7758 * @param [in]val Register containing the byte to fold into the CRC.
7759 * @param [in]table Register containing the table of crc constants.
7760 *
7761 * uint32_t crc;
7762 * val = crc_table[(val ^ crc) & 0xFF];
7763 * crc = val ^ (crc >> 8);
7764 *
7765 */
7766 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7767 xorl(val, crc);
7768 andl(val, 0xFF);
7769 shrl(crc, 8); // unsigned shift
7770 xorl(crc, Address(table, val, Address::times_4, 0));
7771 }
7772
7773 /**
7774 * Fold 128-bit data chunk
7775 */
7776 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7777 if (UseAVX > 0) {
7778 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7779 vpclmulldq(xcrc, xK, xcrc); // [63:0]
7780 vpxor(xcrc, xcrc, Address(buf, offset), false /* vector256 */);
7781 pxor(xcrc, xtmp);
7782 } else {
7783 movdqa(xtmp, xcrc);
7784 pclmulhdq(xtmp, xK); // [123:64]
7785 pclmulldq(xcrc, xK); // [63:0]
7786 pxor(xcrc, xtmp);
7787 movdqu(xtmp, Address(buf, offset));
7788 pxor(xcrc, xtmp);
7789 }
7790 }
7791
7792 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7793 if (UseAVX > 0) {
7794 vpclmulhdq(xtmp, xK, xcrc);
7795 vpclmulldq(xcrc, xK, xcrc);
7796 pxor(xcrc, xbuf);
7797 pxor(xcrc, xtmp);
7798 } else {
7799 movdqa(xtmp, xcrc);
7800 pclmulhdq(xtmp, xK);
7801 pclmulldq(xcrc, xK);
7802 pxor(xcrc, xbuf);
7803 pxor(xcrc, xtmp);
7804 }
7805 }
7806
7807 /**
7808 * 8-bit folds to compute 32-bit CRC
7809 *
7810 * uint64_t xcrc;
7811 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7812 */
7813 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7814 movdl(tmp, xcrc);
7815 andl(tmp, 0xFF);
7816 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7817 psrldq(xcrc, 1); // unsigned shift one byte
7818 pxor(xcrc, xtmp);
7819 }
7820
7821 /**
7822 * uint32_t crc;
7823 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7824 */
7825 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7826 movl(tmp, crc);
7827 andl(tmp, 0xFF);
7828 shrl(crc, 8);
7829 xorl(crc, Address(table, tmp, Address::times_4, 0));
7830 }
7831
7832 /**
7833 * @param crc register containing existing CRC (32-bit)
7834 * @param buf register pointing to input byte buffer (byte*)
7835 * @param len register containing number of bytes
7836 * @param table register that will contain address of CRC table
7837 * @param tmp scratch register
7838 */
7839 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7840 assert_different_registers(crc, buf, len, table, tmp, rax);
7841
7842 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7843 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7844
7845 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7846 notl(crc); // ~crc
7847 cmpl(len, 16);
7848 jcc(Assembler::less, L_tail);
7849
7850 // Align buffer to 16 bytes
7851 movl(tmp, buf);
7852 andl(tmp, 0xF);
7853 jccb(Assembler::zero, L_aligned);
7854 subl(tmp, 16);
7855 addl(len, tmp);
7856
7857 align(4);
7858 BIND(L_align_loop);
7859 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7860 update_byte_crc32(crc, rax, table);
7861 increment(buf);
7862 incrementl(tmp);
7863 jccb(Assembler::less, L_align_loop);
7864
7865 BIND(L_aligned);
7866 movl(tmp, len); // save
7867 shrl(len, 4);
7868 jcc(Assembler::zero, L_tail_restore);
7869
7870 // Fold crc into first bytes of vector
7871 movdqa(xmm1, Address(buf, 0));
7872 movdl(rax, xmm1);
7873 xorl(crc, rax);
7874 pinsrd(xmm1, crc, 0);
7875 addptr(buf, 16);
7876 subl(len, 4); // len > 0
7877 jcc(Assembler::less, L_fold_tail);
7878
7879 movdqa(xmm2, Address(buf, 0));
7880 movdqa(xmm3, Address(buf, 16));
7881 movdqa(xmm4, Address(buf, 32));
7882 addptr(buf, 48);
7883 subl(len, 3);
7884 jcc(Assembler::lessEqual, L_fold_512b);
7885
7886 // Fold total 512 bits of polynomial on each iteration,
7887 // 128 bits per each of 4 parallel streams.
7888 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
7889
7890 align(32);
7891 BIND(L_fold_512b_loop);
7892 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7893 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7894 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7895 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7896 addptr(buf, 64);
7897 subl(len, 4);
7898 jcc(Assembler::greater, L_fold_512b_loop);
7899
7900 // Fold 512 bits to 128 bits.
7901 BIND(L_fold_512b);
7902 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7903 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7904 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7905 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7906
7907 // Fold the rest of 128 bits data chunks
7908 BIND(L_fold_tail);
7909 addl(len, 3);
7910 jccb(Assembler::lessEqual, L_fold_128b);
7911 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7912
7913 BIND(L_fold_tail_loop);
7914 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7915 addptr(buf, 16);
7916 decrementl(len);
7917 jccb(Assembler::greater, L_fold_tail_loop);
7918
7919 // Fold 128 bits in xmm1 down into 32 bits in crc register.
7920 BIND(L_fold_128b);
7921 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
7922 if (UseAVX > 0) {
7923 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7924 vpand(xmm3, xmm0, xmm2, false /* vector256 */);
7925 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7926 } else {
7927 movdqa(xmm2, xmm0);
7928 pclmulqdq(xmm2, xmm1, 0x1);
7929 movdqa(xmm3, xmm0);
7930 pand(xmm3, xmm2);
7931 pclmulqdq(xmm0, xmm3, 0x1);
7932 }
7933 psrldq(xmm1, 8);
7934 psrldq(xmm2, 4);
7935 pxor(xmm0, xmm1);
7936 pxor(xmm0, xmm2);
7937
7938 // 8 8-bit folds to compute 32-bit CRC.
7939 for (int j = 0; j < 4; j++) {
7940 fold_8bit_crc32(xmm0, table, xmm1, rax);
7941 }
7942 movdl(crc, xmm0); // mov 32 bits to general register
7943 for (int j = 0; j < 4; j++) {
7944 fold_8bit_crc32(crc, table, rax);
7945 }
7946
7947 BIND(L_tail_restore);
7948 movl(len, tmp); // restore
7949 BIND(L_tail);
7950 andl(len, 0xf);
7951 jccb(Assembler::zero, L_exit);
7952
7953 // Fold the rest of bytes
7954 align(4);
7955 BIND(L_tail_loop);
7956 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7957 update_byte_crc32(crc, rax, table);
7958 increment(buf);
7959 decrementl(len);
7960 jccb(Assembler::greater, L_tail_loop);
7961
7962 BIND(L_exit);
7963 notl(crc); // ~c
7964 }
7965
7966 #undef BIND
7967 #undef BLOCK_COMMENT
7968
7969
7970 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
7971 switch (cond) {
7972 // Note some conditions are synonyms for others
7973 case Assembler::zero: return Assembler::notZero;
7974 case Assembler::notZero: return Assembler::zero;
7975 case Assembler::less: return Assembler::greaterEqual;
7976 case Assembler::lessEqual: return Assembler::greater;
7977 case Assembler::greater: return Assembler::lessEqual;
7978 case Assembler::greaterEqual: return Assembler::less;
7979 case Assembler::below: return Assembler::aboveEqual;
7980 case Assembler::belowEqual: return Assembler::above;
7981 case Assembler::above: return Assembler::belowEqual;
7982 case Assembler::aboveEqual: return Assembler::below;
7983 case Assembler::overflow: return Assembler::noOverflow;
7984 case Assembler::noOverflow: return Assembler::overflow;
7985 case Assembler::negative: return Assembler::positive;
7986 case Assembler::positive: return Assembler::negative;
7987 case Assembler::parity: return Assembler::noParity;
7988 case Assembler::noParity: return Assembler::parity;
7989 }
7990 ShouldNotReachHere(); return Assembler::overflow;
7991 }
7992
7993 SkipIfEqual::SkipIfEqual(
7994 MacroAssembler* masm, const bool* flag_addr, bool value) {
7995 _masm = masm;
7996 _masm->cmp8(ExternalAddress((address)flag_addr), value);
7997 _masm->jcc(Assembler::equal, _label);
7998 }
7999
8000 SkipIfEqual::~SkipIfEqual() {
8001 _masm->bind(_label);
8002 }