src/share/vm/opto/matcher.cpp

rev 8006 : 8069191: moving predicate out of loops may cause array accesses to bypass null check
Summary: Remove CastPP nodes only during final graph reshape
Reviewed-by:

*** 1047,1056 ****
--- 1047,1065 ----
          if (m == NULL) break;
          // set -1 to call add_prec() instead of set_req() during Step1
          mstack.push(m, Visit, n, -1);
        }
  
+       // Handle precedence edges for interior nodes
+       for (i = n->len()-1; (uint)i >= n->req(); i--) {
+         Node *m = n->in(i);
+         if (m == NULL || C->node_arena()->contains(m)) continue;
+         n->rm_prec(i);
+         // set -1 to call add_prec() instead of set_req() during Step1
+         mstack.push(m, Visit, n, -1);
+       }
+ 
        // For constant debug info, I'd rather have unmatched constants.
        int cnt = n->req();
        JVMState* jvms = n->jvms();
        int debug_cnt = jvms ? jvms->debug_start() : cnt;
  
*** 1736,1745 ****
--- 1745,1762 ----
    }
  
    return ex;
  }
  
+ static void handle_precedence_edges(Node* n, MachNode *mach) {
+   for (uint i = n->req(); i < n->len(); i++) {
+     if (n->in(i) != NULL) {
+       mach->add_prec(n->in(i));
+     }
+   }
+ }
+ 
  void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
    // 'op' is what I am expecting to receive
    int op = _leftOp[rule];
    // Operand type to catch childs result
    // This is what my child will give me.
*** 1770,1779 ****
--- 1787,1798 ----
    return;
  }
  
  
  uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
+   handle_precedence_edges(s->_leaf, mach);
+ 
    if( s->_leaf->is_Load() ) {
      Node *mem2 = s->_leaf->in(MemNode::Memory);
      assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
      debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
      mem = mem2;
*** 1852,1861 ****
--- 1871,1883 ----
    if( s->_leaf->is_Load() ) {
      assert( mem == (Node*)1, "multiple Memories being matched at once?" );
      mem = s->_leaf->in(MemNode::Memory);
      debug_only(_mem_node = s->_leaf;)
    }
+ 
+   handle_precedence_edges(s->_leaf, mach);
+ 
    if( s->_leaf->in(0) && s->_leaf->req() > 1) {
      if( !mach->in(0) )
        mach->set_req(0,s->_leaf->in(0));
      else {
        assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );