1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/ad.hpp"
28 #include "opto/addnode.hpp"
29 #include "opto/callnode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/movenode.hpp"
34 #include "opto/opcodes.hpp"
35 #include "opto/regmask.hpp"
36 #include "opto/rootnode.hpp"
37 #include "opto/runtime.hpp"
38 #include "opto/type.hpp"
39 #include "opto/vectornode.hpp"
40 #include "runtime/os.hpp"
41 #include "runtime/sharedRuntime.hpp"
42
43 OptoReg::Name OptoReg::c_frame_pointer;
44
45 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
46 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
47 RegMask Matcher::STACK_ONLY_mask;
48 RegMask Matcher::c_frame_ptr_mask;
49 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
50 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
51
52 //---------------------------Matcher-------------------------------------------
53 Matcher::Matcher()
54 : PhaseTransform( Phase::Ins_Select ),
55 #ifdef ASSERT
56 _old2new_map(C->comp_arena()),
57 _new2old_map(C->comp_arena()),
58 #endif
59 _shared_nodes(C->comp_arena()),
60 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
61 _swallowed(swallowed),
62 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
63 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
64 _must_clone(must_clone),
65 _register_save_policy(register_save_policy),
66 _c_reg_save_policy(c_reg_save_policy),
67 _register_save_type(register_save_type),
68 _ruleName(ruleName),
69 _allocation_started(false),
70 _states_arena(Chunk::medium_size),
71 _visited(&_states_arena),
72 _shared(&_states_arena),
73 _dontcare(&_states_arena) {
74 C->set_matcher(this);
75
76 idealreg2spillmask [Op_RegI] = NULL;
77 idealreg2spillmask [Op_RegN] = NULL;
78 idealreg2spillmask [Op_RegL] = NULL;
79 idealreg2spillmask [Op_RegF] = NULL;
80 idealreg2spillmask [Op_RegD] = NULL;
81 idealreg2spillmask [Op_RegP] = NULL;
82 idealreg2spillmask [Op_VecS] = NULL;
83 idealreg2spillmask [Op_VecD] = NULL;
84 idealreg2spillmask [Op_VecX] = NULL;
85 idealreg2spillmask [Op_VecY] = NULL;
86
87 idealreg2debugmask [Op_RegI] = NULL;
88 idealreg2debugmask [Op_RegN] = NULL;
89 idealreg2debugmask [Op_RegL] = NULL;
90 idealreg2debugmask [Op_RegF] = NULL;
91 idealreg2debugmask [Op_RegD] = NULL;
92 idealreg2debugmask [Op_RegP] = NULL;
93 idealreg2debugmask [Op_VecS] = NULL;
94 idealreg2debugmask [Op_VecD] = NULL;
95 idealreg2debugmask [Op_VecX] = NULL;
96 idealreg2debugmask [Op_VecY] = NULL;
97
98 idealreg2mhdebugmask[Op_RegI] = NULL;
99 idealreg2mhdebugmask[Op_RegN] = NULL;
100 idealreg2mhdebugmask[Op_RegL] = NULL;
101 idealreg2mhdebugmask[Op_RegF] = NULL;
102 idealreg2mhdebugmask[Op_RegD] = NULL;
103 idealreg2mhdebugmask[Op_RegP] = NULL;
104 idealreg2mhdebugmask[Op_VecS] = NULL;
105 idealreg2mhdebugmask[Op_VecD] = NULL;
106 idealreg2mhdebugmask[Op_VecX] = NULL;
107 idealreg2mhdebugmask[Op_VecY] = NULL;
108
109 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
110 }
111
112 //------------------------------warp_incoming_stk_arg------------------------
113 // This warps a VMReg into an OptoReg::Name
114 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
115 OptoReg::Name warped;
116 if( reg->is_stack() ) { // Stack slot argument?
117 warped = OptoReg::add(_old_SP, reg->reg2stack() );
118 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
119 if( warped >= _in_arg_limit )
120 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
121 if (!RegMask::can_represent_arg(warped)) {
122 // the compiler cannot represent this method's calling sequence
123 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
124 return OptoReg::Bad;
125 }
126 return warped;
127 }
128 return OptoReg::as_OptoReg(reg);
129 }
130
131 //---------------------------compute_old_SP------------------------------------
132 OptoReg::Name Compile::compute_old_SP() {
133 int fixed = fixed_slots();
134 int preserve = in_preserve_stack_slots();
135 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
136 }
137
138
139
140 #ifdef ASSERT
141 void Matcher::verify_new_nodes_only(Node* xroot) {
142 // Make sure that the new graph only references new nodes
143 ResourceMark rm;
144 Unique_Node_List worklist;
145 VectorSet visited(Thread::current()->resource_area());
146 worklist.push(xroot);
147 while (worklist.size() > 0) {
148 Node* n = worklist.pop();
149 visited <<= n->_idx;
150 assert(C->node_arena()->contains(n), "dead node");
151 for (uint j = 0; j < n->req(); j++) {
152 Node* in = n->in(j);
153 if (in != NULL) {
154 assert(C->node_arena()->contains(in), "dead node");
155 if (!visited.test(in->_idx)) {
156 worklist.push(in);
157 }
158 }
159 }
160 }
161 }
162 #endif
163
164
165 //---------------------------match---------------------------------------------
166 void Matcher::match( ) {
167 if( MaxLabelRootDepth < 100 ) { // Too small?
168 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
169 MaxLabelRootDepth = 100;
170 }
171 // One-time initialization of some register masks.
172 init_spill_mask( C->root()->in(1) );
173 _return_addr_mask = return_addr();
174 #ifdef _LP64
175 // Pointers take 2 slots in 64-bit land
176 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
177 #endif
178
179 // Map a Java-signature return type into return register-value
180 // machine registers for 0, 1 and 2 returned values.
181 const TypeTuple *range = C->tf()->range();
182 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
183 // Get ideal-register return type
184 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
185 // Get machine return register
186 uint sop = C->start()->Opcode();
187 OptoRegPair regs = return_value(ireg, false);
188
189 // And mask for same
190 _return_value_mask = RegMask(regs.first());
191 if( OptoReg::is_valid(regs.second()) )
192 _return_value_mask.Insert(regs.second());
193 }
194
195 // ---------------
196 // Frame Layout
197
198 // Need the method signature to determine the incoming argument types,
199 // because the types determine which registers the incoming arguments are
200 // in, and this affects the matched code.
201 const TypeTuple *domain = C->tf()->domain();
202 uint argcnt = domain->cnt() - TypeFunc::Parms;
203 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
204 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
205 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
206 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
207 uint i;
208 for( i = 0; i<argcnt; i++ ) {
209 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
210 }
211
212 // Pass array of ideal registers and length to USER code (from the AD file)
213 // that will convert this to an array of register numbers.
214 const StartNode *start = C->start();
215 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
216 #ifdef ASSERT
217 // Sanity check users' calling convention. Real handy while trying to
218 // get the initial port correct.
219 { for (uint i = 0; i<argcnt; i++) {
220 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
221 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
222 _parm_regs[i].set_bad();
223 continue;
224 }
225 VMReg parm_reg = vm_parm_regs[i].first();
226 assert(parm_reg->is_valid(), "invalid arg?");
227 if (parm_reg->is_reg()) {
228 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
229 assert(can_be_java_arg(opto_parm_reg) ||
230 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
231 opto_parm_reg == inline_cache_reg(),
232 "parameters in register must be preserved by runtime stubs");
233 }
234 for (uint j = 0; j < i; j++) {
235 assert(parm_reg != vm_parm_regs[j].first(),
236 "calling conv. must produce distinct regs");
237 }
238 }
239 }
240 #endif
241
242 // Do some initial frame layout.
243
244 // Compute the old incoming SP (may be called FP) as
245 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
246 _old_SP = C->compute_old_SP();
247 assert( is_even(_old_SP), "must be even" );
248
249 // Compute highest incoming stack argument as
250 // _old_SP + out_preserve_stack_slots + incoming argument size.
251 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
252 assert( is_even(_in_arg_limit), "out_preserve must be even" );
253 for( i = 0; i < argcnt; i++ ) {
254 // Permit args to have no register
255 _calling_convention_mask[i].Clear();
256 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
257 continue;
258 }
259 // calling_convention returns stack arguments as a count of
260 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
261 // the allocators point of view, taking into account all the
262 // preserve area, locks & pad2.
263
264 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
265 if( OptoReg::is_valid(reg1))
266 _calling_convention_mask[i].Insert(reg1);
267
268 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
269 if( OptoReg::is_valid(reg2))
270 _calling_convention_mask[i].Insert(reg2);
271
272 // Saved biased stack-slot register number
273 _parm_regs[i].set_pair(reg2, reg1);
274 }
275
276 // Finally, make sure the incoming arguments take up an even number of
277 // words, in case the arguments or locals need to contain doubleword stack
278 // slots. The rest of the system assumes that stack slot pairs (in
279 // particular, in the spill area) which look aligned will in fact be
280 // aligned relative to the stack pointer in the target machine. Double
281 // stack slots will always be allocated aligned.
282 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
283
284 // Compute highest outgoing stack argument as
285 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
286 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
287 assert( is_even(_out_arg_limit), "out_preserve must be even" );
288
289 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
290 // the compiler cannot represent this method's calling sequence
291 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
292 }
293
294 if (C->failing()) return; // bailed out on incoming arg failure
295
296 // ---------------
297 // Collect roots of matcher trees. Every node for which
298 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
299 // can be a valid interior of some tree.
300 find_shared( C->root() );
301 find_shared( C->top() );
302
303 C->print_method(PHASE_BEFORE_MATCHING);
304
305 // Create new ideal node ConP #NULL even if it does exist in old space
306 // to avoid false sharing if the corresponding mach node is not used.
307 // The corresponding mach node is only used in rare cases for derived
308 // pointers.
309 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
310
311 // Swap out to old-space; emptying new-space
312 Arena *old = C->node_arena()->move_contents(C->old_arena());
313
314 // Save debug and profile information for nodes in old space:
315 _old_node_note_array = C->node_note_array();
316 if (_old_node_note_array != NULL) {
317 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
318 (C->comp_arena(), _old_node_note_array->length(),
319 0, NULL));
320 }
321
322 // Pre-size the new_node table to avoid the need for range checks.
323 grow_new_node_array(C->unique());
324
325 // Reset node counter so MachNodes start with _idx at 0
326 int nodes = C->unique(); // save value
327 C->set_unique(0);
328 C->reset_dead_node_list();
329
330 // Recursively match trees from old space into new space.
331 // Correct leaves of new-space Nodes; they point to old-space.
332 _visited.Clear(); // Clear visit bits for xform call
333 C->set_cached_top_node(xform( C->top(), nodes ));
334 if (!C->failing()) {
335 Node* xroot = xform( C->root(), 1 );
336 if (xroot == NULL) {
337 Matcher::soft_match_failure(); // recursive matching process failed
338 C->record_method_not_compilable("instruction match failed");
339 } else {
340 // During matching shared constants were attached to C->root()
341 // because xroot wasn't available yet, so transfer the uses to
342 // the xroot.
343 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
344 Node* n = C->root()->fast_out(j);
345 if (C->node_arena()->contains(n)) {
346 assert(n->in(0) == C->root(), "should be control user");
347 n->set_req(0, xroot);
348 --j;
349 --jmax;
350 }
351 }
352
353 // Generate new mach node for ConP #NULL
354 assert(new_ideal_null != NULL, "sanity");
355 _mach_null = match_tree(new_ideal_null);
356 // Don't set control, it will confuse GCM since there are no uses.
357 // The control will be set when this node is used first time
358 // in find_base_for_derived().
359 assert(_mach_null != NULL, "");
360
361 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
362
363 #ifdef ASSERT
364 verify_new_nodes_only(xroot);
365 #endif
366 }
367 }
368 if (C->top() == NULL || C->root() == NULL) {
369 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
370 }
371 if (C->failing()) {
372 // delete old;
373 old->destruct_contents();
374 return;
375 }
376 assert( C->top(), "" );
377 assert( C->root(), "" );
378 validate_null_checks();
379
380 // Now smoke old-space
381 NOT_DEBUG( old->destruct_contents() );
382
383 // ------------------------
384 // Set up save-on-entry registers
385 Fixup_Save_On_Entry( );
386 }
387
388
389 //------------------------------Fixup_Save_On_Entry----------------------------
390 // The stated purpose of this routine is to take care of save-on-entry
391 // registers. However, the overall goal of the Match phase is to convert into
392 // machine-specific instructions which have RegMasks to guide allocation.
393 // So what this procedure really does is put a valid RegMask on each input
394 // to the machine-specific variations of all Return, TailCall and Halt
395 // instructions. It also adds edgs to define the save-on-entry values (and of
396 // course gives them a mask).
397
398 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
399 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
400 // Do all the pre-defined register masks
401 rms[TypeFunc::Control ] = RegMask::Empty;
402 rms[TypeFunc::I_O ] = RegMask::Empty;
403 rms[TypeFunc::Memory ] = RegMask::Empty;
404 rms[TypeFunc::ReturnAdr] = ret_adr;
405 rms[TypeFunc::FramePtr ] = fp;
406 return rms;
407 }
408
409 //---------------------------init_first_stack_mask-----------------------------
410 // Create the initial stack mask used by values spilling to the stack.
411 // Disallow any debug info in outgoing argument areas by setting the
412 // initial mask accordingly.
413 void Matcher::init_first_stack_mask() {
414
415 // Allocate storage for spill masks as masks for the appropriate load type.
416 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
417
418 idealreg2spillmask [Op_RegN] = &rms[0];
419 idealreg2spillmask [Op_RegI] = &rms[1];
420 idealreg2spillmask [Op_RegL] = &rms[2];
421 idealreg2spillmask [Op_RegF] = &rms[3];
422 idealreg2spillmask [Op_RegD] = &rms[4];
423 idealreg2spillmask [Op_RegP] = &rms[5];
424
425 idealreg2debugmask [Op_RegN] = &rms[6];
426 idealreg2debugmask [Op_RegI] = &rms[7];
427 idealreg2debugmask [Op_RegL] = &rms[8];
428 idealreg2debugmask [Op_RegF] = &rms[9];
429 idealreg2debugmask [Op_RegD] = &rms[10];
430 idealreg2debugmask [Op_RegP] = &rms[11];
431
432 idealreg2mhdebugmask[Op_RegN] = &rms[12];
433 idealreg2mhdebugmask[Op_RegI] = &rms[13];
434 idealreg2mhdebugmask[Op_RegL] = &rms[14];
435 idealreg2mhdebugmask[Op_RegF] = &rms[15];
436 idealreg2mhdebugmask[Op_RegD] = &rms[16];
437 idealreg2mhdebugmask[Op_RegP] = &rms[17];
438
439 idealreg2spillmask [Op_VecS] = &rms[18];
440 idealreg2spillmask [Op_VecD] = &rms[19];
441 idealreg2spillmask [Op_VecX] = &rms[20];
442 idealreg2spillmask [Op_VecY] = &rms[21];
443
444 OptoReg::Name i;
445
446 // At first, start with the empty mask
447 C->FIRST_STACK_mask().Clear();
448
449 // Add in the incoming argument area
450 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
451 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
452 C->FIRST_STACK_mask().Insert(i);
453 }
454 // Add in all bits past the outgoing argument area
455 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
456 "must be able to represent all call arguments in reg mask");
457 OptoReg::Name init = _out_arg_limit;
458 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
459 C->FIRST_STACK_mask().Insert(i);
460 }
461 // Finally, set the "infinite stack" bit.
462 C->FIRST_STACK_mask().set_AllStack();
463
464 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
465 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
466 // Keep spill masks aligned.
467 aligned_stack_mask.clear_to_pairs();
468 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
469
470 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
471 #ifdef _LP64
472 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
473 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
474 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
475 #else
476 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
477 #endif
478 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
479 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
480 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
481 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
482 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
483 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
484 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
485 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
486
487 if (Matcher::vector_size_supported(T_BYTE,4)) {
488 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
489 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
490 }
491 if (Matcher::vector_size_supported(T_FLOAT,2)) {
492 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
493 // RA guarantees such alignment since it is needed for Double and Long values.
494 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
495 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
496 }
497 if (Matcher::vector_size_supported(T_FLOAT,4)) {
498 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
499 //
500 // RA can use input arguments stack slots for spills but until RA
501 // we don't know frame size and offset of input arg stack slots.
502 //
503 // Exclude last input arg stack slots to avoid spilling vectors there
504 // otherwise vector spills could stomp over stack slots in caller frame.
505 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
506 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
507 aligned_stack_mask.Remove(in);
508 in = OptoReg::add(in, -1);
509 }
510 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
511 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
512 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
513 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
514 }
515 if (Matcher::vector_size_supported(T_FLOAT,8)) {
516 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
517 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
518 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
519 aligned_stack_mask.Remove(in);
520 in = OptoReg::add(in, -1);
521 }
522 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
523 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
524 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
525 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
526 }
527 if (UseFPUForSpilling) {
528 // This mask logic assumes that the spill operations are
529 // symmetric and that the registers involved are the same size.
530 // On sparc for instance we may have to use 64 bit moves will
531 // kill 2 registers when used with F0-F31.
532 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
533 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
534 #ifdef _LP64
535 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
536 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
537 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
538 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
539 #else
540 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
541 #ifdef ARM
542 // ARM has support for moving 64bit values between a pair of
543 // integer registers and a double register
544 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
545 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
546 #endif
547 #endif
548 }
549
550 // Make up debug masks. Any spill slot plus callee-save registers.
551 // Caller-save registers are assumed to be trashable by the various
552 // inline-cache fixup routines.
553 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
554 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
555 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
556 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
557 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
558 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
559
560 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
561 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
562 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
563 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
564 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
565 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
566
567 // Prevent stub compilations from attempting to reference
568 // callee-saved registers from debug info
569 bool exclude_soe = !Compile::current()->is_method_compilation();
570
571 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
572 // registers the caller has to save do not work
573 if( _register_save_policy[i] == 'C' ||
574 _register_save_policy[i] == 'A' ||
575 (_register_save_policy[i] == 'E' && exclude_soe) ) {
576 idealreg2debugmask [Op_RegN]->Remove(i);
577 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
578 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
579 idealreg2debugmask [Op_RegF]->Remove(i); // masks
580 idealreg2debugmask [Op_RegD]->Remove(i);
581 idealreg2debugmask [Op_RegP]->Remove(i);
582
583 idealreg2mhdebugmask[Op_RegN]->Remove(i);
584 idealreg2mhdebugmask[Op_RegI]->Remove(i);
585 idealreg2mhdebugmask[Op_RegL]->Remove(i);
586 idealreg2mhdebugmask[Op_RegF]->Remove(i);
587 idealreg2mhdebugmask[Op_RegD]->Remove(i);
588 idealreg2mhdebugmask[Op_RegP]->Remove(i);
589 }
590 }
591
592 // Subtract the register we use to save the SP for MethodHandle
593 // invokes to from the debug mask.
594 const RegMask save_mask = method_handle_invoke_SP_save_mask();
595 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
596 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
597 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
598 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
599 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
600 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
601 }
602
603 //---------------------------is_save_on_entry----------------------------------
604 bool Matcher::is_save_on_entry( int reg ) {
605 return
606 _register_save_policy[reg] == 'E' ||
607 _register_save_policy[reg] == 'A' || // Save-on-entry register?
608 // Also save argument registers in the trampolining stubs
609 (C->save_argument_registers() && is_spillable_arg(reg));
610 }
611
612 //---------------------------Fixup_Save_On_Entry-------------------------------
613 void Matcher::Fixup_Save_On_Entry( ) {
614 init_first_stack_mask();
615
616 Node *root = C->root(); // Short name for root
617 // Count number of save-on-entry registers.
618 uint soe_cnt = number_of_saved_registers();
619 uint i;
620
621 // Find the procedure Start Node
622 StartNode *start = C->start();
623 assert( start, "Expect a start node" );
624
625 // Save argument registers in the trampolining stubs
626 if( C->save_argument_registers() )
627 for( i = 0; i < _last_Mach_Reg; i++ )
628 if( is_spillable_arg(i) )
629 soe_cnt++;
630
631 // Input RegMask array shared by all Returns.
632 // The type for doubles and longs has a count of 2, but
633 // there is only 1 returned value
634 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
635 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
636 // Returns have 0 or 1 returned values depending on call signature.
637 // Return register is specified by return_value in the AD file.
638 if (ret_edge_cnt > TypeFunc::Parms)
639 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
640
641 // Input RegMask array shared by all Rethrows.
642 uint reth_edge_cnt = TypeFunc::Parms+1;
643 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
644 // Rethrow takes exception oop only, but in the argument 0 slot.
645 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
646 #ifdef _LP64
647 // Need two slots for ptrs in 64-bit land
648 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
649 #endif
650
651 // Input RegMask array shared by all TailCalls
652 uint tail_call_edge_cnt = TypeFunc::Parms+2;
653 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
654
655 // Input RegMask array shared by all TailJumps
656 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
657 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
658
659 // TailCalls have 2 returned values (target & moop), whose masks come
660 // from the usual MachNode/MachOper mechanism. Find a sample
661 // TailCall to extract these masks and put the correct masks into
662 // the tail_call_rms array.
663 for( i=1; i < root->req(); i++ ) {
664 MachReturnNode *m = root->in(i)->as_MachReturn();
665 if( m->ideal_Opcode() == Op_TailCall ) {
666 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
667 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
668 break;
669 }
670 }
671
672 // TailJumps have 2 returned values (target & ex_oop), whose masks come
673 // from the usual MachNode/MachOper mechanism. Find a sample
674 // TailJump to extract these masks and put the correct masks into
675 // the tail_jump_rms array.
676 for( i=1; i < root->req(); i++ ) {
677 MachReturnNode *m = root->in(i)->as_MachReturn();
678 if( m->ideal_Opcode() == Op_TailJump ) {
679 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
680 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
681 break;
682 }
683 }
684
685 // Input RegMask array shared by all Halts
686 uint halt_edge_cnt = TypeFunc::Parms;
687 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
688
689 // Capture the return input masks into each exit flavor
690 for( i=1; i < root->req(); i++ ) {
691 MachReturnNode *exit = root->in(i)->as_MachReturn();
692 switch( exit->ideal_Opcode() ) {
693 case Op_Return : exit->_in_rms = ret_rms; break;
694 case Op_Rethrow : exit->_in_rms = reth_rms; break;
695 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
696 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
697 case Op_Halt : exit->_in_rms = halt_rms; break;
698 default : ShouldNotReachHere();
699 }
700 }
701
702 // Next unused projection number from Start.
703 int proj_cnt = C->tf()->domain()->cnt();
704
705 // Do all the save-on-entry registers. Make projections from Start for
706 // them, and give them a use at the exit points. To the allocator, they
707 // look like incoming register arguments.
708 for( i = 0; i < _last_Mach_Reg; i++ ) {
709 if( is_save_on_entry(i) ) {
710
711 // Add the save-on-entry to the mask array
712 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
713 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
714 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
715 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
716 // Halts need the SOE registers, but only in the stack as debug info.
717 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
718 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
719
720 Node *mproj;
721
722 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
723 // into a single RegD.
724 if( (i&1) == 0 &&
725 _register_save_type[i ] == Op_RegF &&
726 _register_save_type[i+1] == Op_RegF &&
727 is_save_on_entry(i+1) ) {
728 // Add other bit for double
729 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
730 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
731 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
732 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
733 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
734 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
735 proj_cnt += 2; // Skip 2 for doubles
736 }
737 else if( (i&1) == 1 && // Else check for high half of double
738 _register_save_type[i-1] == Op_RegF &&
739 _register_save_type[i ] == Op_RegF &&
740 is_save_on_entry(i-1) ) {
741 ret_rms [ ret_edge_cnt] = RegMask::Empty;
742 reth_rms [ reth_edge_cnt] = RegMask::Empty;
743 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
744 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
745 halt_rms [ halt_edge_cnt] = RegMask::Empty;
746 mproj = C->top();
747 }
748 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
749 // into a single RegL.
750 else if( (i&1) == 0 &&
751 _register_save_type[i ] == Op_RegI &&
752 _register_save_type[i+1] == Op_RegI &&
753 is_save_on_entry(i+1) ) {
754 // Add other bit for long
755 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
756 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
757 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
758 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
759 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
760 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
761 proj_cnt += 2; // Skip 2 for longs
762 }
763 else if( (i&1) == 1 && // Else check for high half of long
764 _register_save_type[i-1] == Op_RegI &&
765 _register_save_type[i ] == Op_RegI &&
766 is_save_on_entry(i-1) ) {
767 ret_rms [ ret_edge_cnt] = RegMask::Empty;
768 reth_rms [ reth_edge_cnt] = RegMask::Empty;
769 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
770 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
771 halt_rms [ halt_edge_cnt] = RegMask::Empty;
772 mproj = C->top();
773 } else {
774 // Make a projection for it off the Start
775 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
776 }
777
778 ret_edge_cnt ++;
779 reth_edge_cnt ++;
780 tail_call_edge_cnt ++;
781 tail_jump_edge_cnt ++;
782 halt_edge_cnt ++;
783
784 // Add a use of the SOE register to all exit paths
785 for( uint j=1; j < root->req(); j++ )
786 root->in(j)->add_req(mproj);
787 } // End of if a save-on-entry register
788 } // End of for all machine registers
789 }
790
791 //------------------------------init_spill_mask--------------------------------
792 void Matcher::init_spill_mask( Node *ret ) {
793 if( idealreg2regmask[Op_RegI] ) return; // One time only init
794
795 OptoReg::c_frame_pointer = c_frame_pointer();
796 c_frame_ptr_mask = c_frame_pointer();
797 #ifdef _LP64
798 // pointers are twice as big
799 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
800 #endif
801
802 // Start at OptoReg::stack0()
803 STACK_ONLY_mask.Clear();
804 OptoReg::Name init = OptoReg::stack2reg(0);
805 // STACK_ONLY_mask is all stack bits
806 OptoReg::Name i;
807 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
808 STACK_ONLY_mask.Insert(i);
809 // Also set the "infinite stack" bit.
810 STACK_ONLY_mask.set_AllStack();
811
812 // Copy the register names over into the shared world
813 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
814 // SharedInfo::regName[i] = regName[i];
815 // Handy RegMasks per machine register
816 mreg2regmask[i].Insert(i);
817 }
818
819 // Grab the Frame Pointer
820 Node *fp = ret->in(TypeFunc::FramePtr);
821 Node *mem = ret->in(TypeFunc::Memory);
822 const TypePtr* atp = TypePtr::BOTTOM;
823 // Share frame pointer while making spill ops
824 set_shared(fp);
825
826 // Compute generic short-offset Loads
827 #ifdef _LP64
828 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
829 #endif
830 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
831 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered,false));
832 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
833 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
834 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
835 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
836 spillD != NULL && spillP != NULL, "");
837 // Get the ADLC notion of the right regmask, for each basic type.
838 #ifdef _LP64
839 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
840 #endif
841 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
842 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
843 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
844 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
845 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
846
847 // Vector regmasks.
848 if (Matcher::vector_size_supported(T_BYTE,4)) {
849 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
850 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
851 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
852 }
853 if (Matcher::vector_size_supported(T_FLOAT,2)) {
854 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
855 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
856 }
857 if (Matcher::vector_size_supported(T_FLOAT,4)) {
858 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
859 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
860 }
861 if (Matcher::vector_size_supported(T_FLOAT,8)) {
862 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
863 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
864 }
865 }
866
867 #ifdef ASSERT
868 static void match_alias_type(Compile* C, Node* n, Node* m) {
869 if (!VerifyAliases) return; // do not go looking for trouble by default
870 const TypePtr* nat = n->adr_type();
871 const TypePtr* mat = m->adr_type();
872 int nidx = C->get_alias_index(nat);
873 int midx = C->get_alias_index(mat);
874 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
875 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
876 for (uint i = 1; i < n->req(); i++) {
877 Node* n1 = n->in(i);
878 const TypePtr* n1at = n1->adr_type();
879 if (n1at != NULL) {
880 nat = n1at;
881 nidx = C->get_alias_index(n1at);
882 }
883 }
884 }
885 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
886 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
887 switch (n->Opcode()) {
888 case Op_PrefetchAllocation:
889 nidx = Compile::AliasIdxRaw;
890 nat = TypeRawPtr::BOTTOM;
891 break;
892 }
893 }
894 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
895 switch (n->Opcode()) {
896 case Op_ClearArray:
897 midx = Compile::AliasIdxRaw;
898 mat = TypeRawPtr::BOTTOM;
899 break;
900 }
901 }
902 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
903 switch (n->Opcode()) {
904 case Op_Return:
905 case Op_Rethrow:
906 case Op_Halt:
907 case Op_TailCall:
908 case Op_TailJump:
909 nidx = Compile::AliasIdxBot;
910 nat = TypePtr::BOTTOM;
911 break;
912 }
913 }
914 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
915 switch (n->Opcode()) {
916 case Op_StrComp:
917 case Op_StrEquals:
918 case Op_StrIndexOf:
919 case Op_AryEq:
920 case Op_MemBarVolatile:
921 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
922 case Op_EncodeISOArray:
923 nidx = Compile::AliasIdxTop;
924 nat = NULL;
925 break;
926 }
927 }
928 if (nidx != midx) {
929 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
930 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
931 n->dump();
932 m->dump();
933 }
934 assert(C->subsume_loads() && C->must_alias(nat, midx),
935 "must not lose alias info when matching");
936 }
937 }
938 #endif
939
940
941 //------------------------------MStack-----------------------------------------
942 // State and MStack class used in xform() and find_shared() iterative methods.
943 enum Node_State { Pre_Visit, // node has to be pre-visited
944 Visit, // visit node
945 Post_Visit, // post-visit node
946 Alt_Post_Visit // alternative post-visit path
947 };
948
949 class MStack: public Node_Stack {
950 public:
951 MStack(int size) : Node_Stack(size) { }
952
953 void push(Node *n, Node_State ns) {
954 Node_Stack::push(n, (uint)ns);
955 }
956 void push(Node *n, Node_State ns, Node *parent, int indx) {
957 ++_inode_top;
958 if ((_inode_top + 1) >= _inode_max) grow();
959 _inode_top->node = parent;
960 _inode_top->indx = (uint)indx;
961 ++_inode_top;
962 _inode_top->node = n;
963 _inode_top->indx = (uint)ns;
964 }
965 Node *parent() {
966 pop();
967 return node();
968 }
969 Node_State state() const {
970 return (Node_State)index();
971 }
972 void set_state(Node_State ns) {
973 set_index((uint)ns);
974 }
975 };
976
977
978 //------------------------------xform------------------------------------------
979 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
980 // Node in new-space. Given a new-space Node, recursively walk his children.
981 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
982 Node *Matcher::xform( Node *n, int max_stack ) {
983 // Use one stack to keep both: child's node/state and parent's node/index
984 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
985 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
986
987 while (mstack.is_nonempty()) {
988 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
989 if (C->failing()) return NULL;
990 n = mstack.node(); // Leave node on stack
991 Node_State nstate = mstack.state();
992 if (nstate == Visit) {
993 mstack.set_state(Post_Visit);
994 Node *oldn = n;
995 // Old-space or new-space check
996 if (!C->node_arena()->contains(n)) {
997 // Old space!
998 Node* m;
999 if (has_new_node(n)) { // Not yet Label/Reduced
1000 m = new_node(n);
1001 } else {
1002 if (!is_dontcare(n)) { // Matcher can match this guy
1003 // Calls match special. They match alone with no children.
1004 // Their children, the incoming arguments, match normally.
1005 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1006 if (C->failing()) return NULL;
1007 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1008 } else { // Nothing the matcher cares about
1009 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1010 // Convert to machine-dependent projection
1011 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1012 #ifdef ASSERT
1013 _new2old_map.map(m->_idx, n);
1014 #endif
1015 if (m->in(0) != NULL) // m might be top
1016 collect_null_checks(m, n);
1017 } else { // Else just a regular 'ol guy
1018 m = n->clone(); // So just clone into new-space
1019 #ifdef ASSERT
1020 _new2old_map.map(m->_idx, n);
1021 #endif
1022 // Def-Use edges will be added incrementally as Uses
1023 // of this node are matched.
1024 assert(m->outcnt() == 0, "no Uses of this clone yet");
1025 }
1026 }
1027
1028 set_new_node(n, m); // Map old to new
1029 if (_old_node_note_array != NULL) {
1030 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1031 n->_idx);
1032 C->set_node_notes_at(m->_idx, nn);
1033 }
1034 debug_only(match_alias_type(C, n, m));
1035 }
1036 n = m; // n is now a new-space node
1037 mstack.set_node(n);
1038 }
1039
1040 // New space!
1041 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1042
1043 int i;
1044 // Put precedence edges on stack first (match them last).
1045 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1046 Node *m = oldn->in(i);
1047 if (m == NULL) break;
1048 // set -1 to call add_prec() instead of set_req() during Step1
1049 mstack.push(m, Visit, n, -1);
1050 }
1051
1052 // Handle precedence edges for interior nodes
1053 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1054 Node *m = n->in(i);
1055 if (m == NULL || C->node_arena()->contains(m)) continue;
1056 n->rm_prec(i);
1057 // set -1 to call add_prec() instead of set_req() during Step1
1058 mstack.push(m, Visit, n, -1);
1059 }
1060
1061 // For constant debug info, I'd rather have unmatched constants.
1062 int cnt = n->req();
1063 JVMState* jvms = n->jvms();
1064 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1065
1066 // Now do only debug info. Clone constants rather than matching.
1067 // Constants are represented directly in the debug info without
1068 // the need for executable machine instructions.
1069 // Monitor boxes are also represented directly.
1070 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1071 Node *m = n->in(i); // Get input
1072 int op = m->Opcode();
1073 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1074 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1075 op == Op_ConF || op == Op_ConD || op == Op_ConL
1076 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1077 ) {
1078 m = m->clone();
1079 #ifdef ASSERT
1080 _new2old_map.map(m->_idx, n);
1081 #endif
1082 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1083 mstack.push(m->in(0), Visit, m, 0);
1084 } else {
1085 mstack.push(m, Visit, n, i);
1086 }
1087 }
1088
1089 // And now walk his children, and convert his inputs to new-space.
1090 for( ; i >= 0; --i ) { // For all normal inputs do
1091 Node *m = n->in(i); // Get input
1092 if(m != NULL)
1093 mstack.push(m, Visit, n, i);
1094 }
1095
1096 }
1097 else if (nstate == Post_Visit) {
1098 // Set xformed input
1099 Node *p = mstack.parent();
1100 if (p != NULL) { // root doesn't have parent
1101 int i = (int)mstack.index();
1102 if (i >= 0)
1103 p->set_req(i, n); // required input
1104 else if (i == -1)
1105 p->add_prec(n); // precedence input
1106 else
1107 ShouldNotReachHere();
1108 }
1109 mstack.pop(); // remove processed node from stack
1110 }
1111 else {
1112 ShouldNotReachHere();
1113 }
1114 } // while (mstack.is_nonempty())
1115 return n; // Return new-space Node
1116 }
1117
1118 //------------------------------warp_outgoing_stk_arg------------------------
1119 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1120 // Convert outgoing argument location to a pre-biased stack offset
1121 if (reg->is_stack()) {
1122 OptoReg::Name warped = reg->reg2stack();
1123 // Adjust the stack slot offset to be the register number used
1124 // by the allocator.
1125 warped = OptoReg::add(begin_out_arg_area, warped);
1126 // Keep track of the largest numbered stack slot used for an arg.
1127 // Largest used slot per call-site indicates the amount of stack
1128 // that is killed by the call.
1129 if( warped >= out_arg_limit_per_call )
1130 out_arg_limit_per_call = OptoReg::add(warped,1);
1131 if (!RegMask::can_represent_arg(warped)) {
1132 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1133 return OptoReg::Bad;
1134 }
1135 return warped;
1136 }
1137 return OptoReg::as_OptoReg(reg);
1138 }
1139
1140
1141 //------------------------------match_sfpt-------------------------------------
1142 // Helper function to match call instructions. Calls match special.
1143 // They match alone with no children. Their children, the incoming
1144 // arguments, match normally.
1145 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1146 MachSafePointNode *msfpt = NULL;
1147 MachCallNode *mcall = NULL;
1148 uint cnt;
1149 // Split out case for SafePoint vs Call
1150 CallNode *call;
1151 const TypeTuple *domain;
1152 ciMethod* method = NULL;
1153 bool is_method_handle_invoke = false; // for special kill effects
1154 if( sfpt->is_Call() ) {
1155 call = sfpt->as_Call();
1156 domain = call->tf()->domain();
1157 cnt = domain->cnt();
1158
1159 // Match just the call, nothing else
1160 MachNode *m = match_tree(call);
1161 if (C->failing()) return NULL;
1162 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1163
1164 // Copy data from the Ideal SafePoint to the machine version
1165 mcall = m->as_MachCall();
1166
1167 mcall->set_tf( call->tf());
1168 mcall->set_entry_point(call->entry_point());
1169 mcall->set_cnt( call->cnt());
1170
1171 if( mcall->is_MachCallJava() ) {
1172 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1173 const CallJavaNode *call_java = call->as_CallJava();
1174 method = call_java->method();
1175 mcall_java->_method = method;
1176 mcall_java->_bci = call_java->_bci;
1177 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1178 is_method_handle_invoke = call_java->is_method_handle_invoke();
1179 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1180 if (is_method_handle_invoke) {
1181 C->set_has_method_handle_invokes(true);
1182 }
1183 if( mcall_java->is_MachCallStaticJava() )
1184 mcall_java->as_MachCallStaticJava()->_name =
1185 call_java->as_CallStaticJava()->_name;
1186 if( mcall_java->is_MachCallDynamicJava() )
1187 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1188 call_java->as_CallDynamicJava()->_vtable_index;
1189 }
1190 else if( mcall->is_MachCallRuntime() ) {
1191 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1192 }
1193 msfpt = mcall;
1194 }
1195 // This is a non-call safepoint
1196 else {
1197 call = NULL;
1198 domain = NULL;
1199 MachNode *mn = match_tree(sfpt);
1200 if (C->failing()) return NULL;
1201 msfpt = mn->as_MachSafePoint();
1202 cnt = TypeFunc::Parms;
1203 }
1204
1205 // Advertise the correct memory effects (for anti-dependence computation).
1206 msfpt->set_adr_type(sfpt->adr_type());
1207
1208 // Allocate a private array of RegMasks. These RegMasks are not shared.
1209 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1210 // Empty them all.
1211 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1212
1213 // Do all the pre-defined non-Empty register masks
1214 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1215 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1216
1217 // Place first outgoing argument can possibly be put.
1218 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1219 assert( is_even(begin_out_arg_area), "" );
1220 // Compute max outgoing register number per call site.
1221 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1222 // Calls to C may hammer extra stack slots above and beyond any arguments.
1223 // These are usually backing store for register arguments for varargs.
1224 if( call != NULL && call->is_CallRuntime() )
1225 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1226
1227
1228 // Do the normal argument list (parameters) register masks
1229 int argcnt = cnt - TypeFunc::Parms;
1230 if( argcnt > 0 ) { // Skip it all if we have no args
1231 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1232 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1233 int i;
1234 for( i = 0; i < argcnt; i++ ) {
1235 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1236 }
1237 // V-call to pick proper calling convention
1238 call->calling_convention( sig_bt, parm_regs, argcnt );
1239
1240 #ifdef ASSERT
1241 // Sanity check users' calling convention. Really handy during
1242 // the initial porting effort. Fairly expensive otherwise.
1243 { for (int i = 0; i<argcnt; i++) {
1244 if( !parm_regs[i].first()->is_valid() &&
1245 !parm_regs[i].second()->is_valid() ) continue;
1246 VMReg reg1 = parm_regs[i].first();
1247 VMReg reg2 = parm_regs[i].second();
1248 for (int j = 0; j < i; j++) {
1249 if( !parm_regs[j].first()->is_valid() &&
1250 !parm_regs[j].second()->is_valid() ) continue;
1251 VMReg reg3 = parm_regs[j].first();
1252 VMReg reg4 = parm_regs[j].second();
1253 if( !reg1->is_valid() ) {
1254 assert( !reg2->is_valid(), "valid halvsies" );
1255 } else if( !reg3->is_valid() ) {
1256 assert( !reg4->is_valid(), "valid halvsies" );
1257 } else {
1258 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1259 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1260 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1261 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1262 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1263 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1264 }
1265 }
1266 }
1267 }
1268 #endif
1269
1270 // Visit each argument. Compute its outgoing register mask.
1271 // Return results now can have 2 bits returned.
1272 // Compute max over all outgoing arguments both per call-site
1273 // and over the entire method.
1274 for( i = 0; i < argcnt; i++ ) {
1275 // Address of incoming argument mask to fill in
1276 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1277 if( !parm_regs[i].first()->is_valid() &&
1278 !parm_regs[i].second()->is_valid() ) {
1279 continue; // Avoid Halves
1280 }
1281 // Grab first register, adjust stack slots and insert in mask.
1282 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1283 if (OptoReg::is_valid(reg1))
1284 rm->Insert( reg1 );
1285 // Grab second register (if any), adjust stack slots and insert in mask.
1286 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1287 if (OptoReg::is_valid(reg2))
1288 rm->Insert( reg2 );
1289 } // End of for all arguments
1290
1291 // Compute number of stack slots needed to restore stack in case of
1292 // Pascal-style argument popping.
1293 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1294 }
1295
1296 // Compute the max stack slot killed by any call. These will not be
1297 // available for debug info, and will be used to adjust FIRST_STACK_mask
1298 // after all call sites have been visited.
1299 if( _out_arg_limit < out_arg_limit_per_call)
1300 _out_arg_limit = out_arg_limit_per_call;
1301
1302 if (mcall) {
1303 // Kill the outgoing argument area, including any non-argument holes and
1304 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1305 // Since the max-per-method covers the max-per-call-site and debug info
1306 // is excluded on the max-per-method basis, debug info cannot land in
1307 // this killed area.
1308 uint r_cnt = mcall->tf()->range()->cnt();
1309 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1310 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1311 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1312 } else {
1313 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1314 proj->_rout.Insert(OptoReg::Name(i));
1315 }
1316 if (proj->_rout.is_NotEmpty()) {
1317 push_projection(proj);
1318 }
1319 }
1320 // Transfer the safepoint information from the call to the mcall
1321 // Move the JVMState list
1322 msfpt->set_jvms(sfpt->jvms());
1323 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1324 jvms->set_map(sfpt);
1325 }
1326
1327 // Debug inputs begin just after the last incoming parameter
1328 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1329 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1330
1331 // Move the OopMap
1332 msfpt->_oop_map = sfpt->_oop_map;
1333
1334 // Add additional edges.
1335 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1336 // For these calls we can not add MachConstantBase in expand(), as the
1337 // ins are not complete then.
1338 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1339 if (msfpt->jvms() &&
1340 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1341 // We added an edge before jvms, so we must adapt the position of the ins.
1342 msfpt->jvms()->adapt_position(+1);
1343 }
1344 }
1345
1346 // Registers killed by the call are set in the local scheduling pass
1347 // of Global Code Motion.
1348 return msfpt;
1349 }
1350
1351 //---------------------------match_tree----------------------------------------
1352 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1353 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1354 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1355 // a Load's result RegMask for memoization in idealreg2regmask[]
1356 MachNode *Matcher::match_tree( const Node *n ) {
1357 assert( n->Opcode() != Op_Phi, "cannot match" );
1358 assert( !n->is_block_start(), "cannot match" );
1359 // Set the mark for all locally allocated State objects.
1360 // When this call returns, the _states_arena arena will be reset
1361 // freeing all State objects.
1362 ResourceMark rm( &_states_arena );
1363
1364 LabelRootDepth = 0;
1365
1366 // StoreNodes require their Memory input to match any LoadNodes
1367 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1368 #ifdef ASSERT
1369 Node* save_mem_node = _mem_node;
1370 _mem_node = n->is_Store() ? (Node*)n : NULL;
1371 #endif
1372 // State object for root node of match tree
1373 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1374 State *s = new (&_states_arena) State;
1375 s->_kids[0] = NULL;
1376 s->_kids[1] = NULL;
1377 s->_leaf = (Node*)n;
1378 // Label the input tree, allocating labels from top-level arena
1379 Label_Root( n, s, n->in(0), mem );
1380 if (C->failing()) return NULL;
1381
1382 // The minimum cost match for the whole tree is found at the root State
1383 uint mincost = max_juint;
1384 uint cost = max_juint;
1385 uint i;
1386 for( i = 0; i < NUM_OPERANDS; i++ ) {
1387 if( s->valid(i) && // valid entry and
1388 s->_cost[i] < cost && // low cost and
1389 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1390 cost = s->_cost[mincost=i];
1391 }
1392 if (mincost == max_juint) {
1393 #ifndef PRODUCT
1394 tty->print("No matching rule for:");
1395 s->dump();
1396 #endif
1397 Matcher::soft_match_failure();
1398 return NULL;
1399 }
1400 // Reduce input tree based upon the state labels to machine Nodes
1401 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1402 #ifdef ASSERT
1403 _old2new_map.map(n->_idx, m);
1404 _new2old_map.map(m->_idx, (Node*)n);
1405 #endif
1406
1407 // Add any Matcher-ignored edges
1408 uint cnt = n->req();
1409 uint start = 1;
1410 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1411 if( n->is_AddP() ) {
1412 assert( mem == (Node*)1, "" );
1413 start = AddPNode::Base+1;
1414 }
1415 for( i = start; i < cnt; i++ ) {
1416 if( !n->match_edge(i) ) {
1417 if( i < m->req() )
1418 m->ins_req( i, n->in(i) );
1419 else
1420 m->add_req( n->in(i) );
1421 }
1422 }
1423
1424 debug_only( _mem_node = save_mem_node; )
1425 return m;
1426 }
1427
1428
1429 //------------------------------match_into_reg---------------------------------
1430 // Choose to either match this Node in a register or part of the current
1431 // match tree. Return true for requiring a register and false for matching
1432 // as part of the current match tree.
1433 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1434
1435 const Type *t = m->bottom_type();
1436
1437 if (t->singleton()) {
1438 // Never force constants into registers. Allow them to match as
1439 // constants or registers. Copies of the same value will share
1440 // the same register. See find_shared_node.
1441 return false;
1442 } else { // Not a constant
1443 // Stop recursion if they have different Controls.
1444 Node* m_control = m->in(0);
1445 // Control of load's memory can post-dominates load's control.
1446 // So use it since load can't float above its memory.
1447 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1448 if (control && m_control && control != m_control && control != mem_control) {
1449
1450 // Actually, we can live with the most conservative control we
1451 // find, if it post-dominates the others. This allows us to
1452 // pick up load/op/store trees where the load can float a little
1453 // above the store.
1454 Node *x = control;
1455 const uint max_scan = 6; // Arbitrary scan cutoff
1456 uint j;
1457 for (j=0; j<max_scan; j++) {
1458 if (x->is_Region()) // Bail out at merge points
1459 return true;
1460 x = x->in(0);
1461 if (x == m_control) // Does 'control' post-dominate
1462 break; // m->in(0)? If so, we can use it
1463 if (x == mem_control) // Does 'control' post-dominate
1464 break; // mem_control? If so, we can use it
1465 }
1466 if (j == max_scan) // No post-domination before scan end?
1467 return true; // Then break the match tree up
1468 }
1469 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1470 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1471 // These are commonly used in address expressions and can
1472 // efficiently fold into them on X64 in some cases.
1473 return false;
1474 }
1475 }
1476
1477 // Not forceable cloning. If shared, put it into a register.
1478 return shared;
1479 }
1480
1481
1482 //------------------------------Instruction Selection--------------------------
1483 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1484 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1485 // things the Matcher does not match (e.g., Memory), and things with different
1486 // Controls (hence forced into different blocks). We pass in the Control
1487 // selected for this entire State tree.
1488
1489 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1490 // Store and the Load must have identical Memories (as well as identical
1491 // pointers). Since the Matcher does not have anything for Memory (and
1492 // does not handle DAGs), I have to match the Memory input myself. If the
1493 // Tree root is a Store, I require all Loads to have the identical memory.
1494 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1495 // Since Label_Root is a recursive function, its possible that we might run
1496 // out of stack space. See bugs 6272980 & 6227033 for more info.
1497 LabelRootDepth++;
1498 if (LabelRootDepth > MaxLabelRootDepth) {
1499 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1500 return NULL;
1501 }
1502 uint care = 0; // Edges matcher cares about
1503 uint cnt = n->req();
1504 uint i = 0;
1505
1506 // Examine children for memory state
1507 // Can only subsume a child into your match-tree if that child's memory state
1508 // is not modified along the path to another input.
1509 // It is unsafe even if the other inputs are separate roots.
1510 Node *input_mem = NULL;
1511 for( i = 1; i < cnt; i++ ) {
1512 if( !n->match_edge(i) ) continue;
1513 Node *m = n->in(i); // Get ith input
1514 assert( m, "expect non-null children" );
1515 if( m->is_Load() ) {
1516 if( input_mem == NULL ) {
1517 input_mem = m->in(MemNode::Memory);
1518 } else if( input_mem != m->in(MemNode::Memory) ) {
1519 input_mem = NodeSentinel;
1520 }
1521 }
1522 }
1523
1524 for( i = 1; i < cnt; i++ ){// For my children
1525 if( !n->match_edge(i) ) continue;
1526 Node *m = n->in(i); // Get ith input
1527 // Allocate states out of a private arena
1528 State *s = new (&_states_arena) State;
1529 svec->_kids[care++] = s;
1530 assert( care <= 2, "binary only for now" );
1531
1532 // Recursively label the State tree.
1533 s->_kids[0] = NULL;
1534 s->_kids[1] = NULL;
1535 s->_leaf = m;
1536
1537 // Check for leaves of the State Tree; things that cannot be a part of
1538 // the current tree. If it finds any, that value is matched as a
1539 // register operand. If not, then the normal matching is used.
1540 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1541 //
1542 // Stop recursion if this is LoadNode and the root of this tree is a
1543 // StoreNode and the load & store have different memories.
1544 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1545 // Can NOT include the match of a subtree when its memory state
1546 // is used by any of the other subtrees
1547 (input_mem == NodeSentinel) ) {
1548 #ifndef PRODUCT
1549 // Print when we exclude matching due to different memory states at input-loads
1550 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1551 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1552 tty->print_cr("invalid input_mem");
1553 }
1554 #endif
1555 // Switch to a register-only opcode; this value must be in a register
1556 // and cannot be subsumed as part of a larger instruction.
1557 s->DFA( m->ideal_reg(), m );
1558
1559 } else {
1560 // If match tree has no control and we do, adopt it for entire tree
1561 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1562 control = m->in(0); // Pick up control
1563 // Else match as a normal part of the match tree.
1564 control = Label_Root(m,s,control,mem);
1565 if (C->failing()) return NULL;
1566 }
1567 }
1568
1569
1570 // Call DFA to match this node, and return
1571 svec->DFA( n->Opcode(), n );
1572
1573 #ifdef ASSERT
1574 uint x;
1575 for( x = 0; x < _LAST_MACH_OPER; x++ )
1576 if( svec->valid(x) )
1577 break;
1578
1579 if (x >= _LAST_MACH_OPER) {
1580 n->dump();
1581 svec->dump();
1582 assert( false, "bad AD file" );
1583 }
1584 #endif
1585 return control;
1586 }
1587
1588
1589 // Con nodes reduced using the same rule can share their MachNode
1590 // which reduces the number of copies of a constant in the final
1591 // program. The register allocator is free to split uses later to
1592 // split live ranges.
1593 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1594 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1595
1596 // See if this Con has already been reduced using this rule.
1597 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1598 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1599 if (last != NULL && rule == last->rule()) {
1600 // Don't expect control change for DecodeN
1601 if (leaf->is_DecodeNarrowPtr())
1602 return last;
1603 // Get the new space root.
1604 Node* xroot = new_node(C->root());
1605 if (xroot == NULL) {
1606 // This shouldn't happen give the order of matching.
1607 return NULL;
1608 }
1609
1610 // Shared constants need to have their control be root so they
1611 // can be scheduled properly.
1612 Node* control = last->in(0);
1613 if (control != xroot) {
1614 if (control == NULL || control == C->root()) {
1615 last->set_req(0, xroot);
1616 } else {
1617 assert(false, "unexpected control");
1618 return NULL;
1619 }
1620 }
1621 return last;
1622 }
1623 return NULL;
1624 }
1625
1626
1627 //------------------------------ReduceInst-------------------------------------
1628 // Reduce a State tree (with given Control) into a tree of MachNodes.
1629 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1630 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1631 // Each MachNode has a number of complicated MachOper operands; each
1632 // MachOper also covers a further tree of Ideal Nodes.
1633
1634 // The root of the Ideal match tree is always an instruction, so we enter
1635 // the recursion here. After building the MachNode, we need to recurse
1636 // the tree checking for these cases:
1637 // (1) Child is an instruction -
1638 // Build the instruction (recursively), add it as an edge.
1639 // Build a simple operand (register) to hold the result of the instruction.
1640 // (2) Child is an interior part of an instruction -
1641 // Skip over it (do nothing)
1642 // (3) Child is the start of a operand -
1643 // Build the operand, place it inside the instruction
1644 // Call ReduceOper.
1645 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1646 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1647
1648 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1649 if (shared_node != NULL) {
1650 return shared_node;
1651 }
1652
1653 // Build the object to represent this state & prepare for recursive calls
1654 MachNode *mach = s->MachNodeGenerator(rule);
1655 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1656 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1657 Node *leaf = s->_leaf;
1658 // Check for instruction or instruction chain rule
1659 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1660 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1661 "duplicating node that's already been matched");
1662 // Instruction
1663 mach->add_req( leaf->in(0) ); // Set initial control
1664 // Reduce interior of complex instruction
1665 ReduceInst_Interior( s, rule, mem, mach, 1 );
1666 } else {
1667 // Instruction chain rules are data-dependent on their inputs
1668 mach->add_req(0); // Set initial control to none
1669 ReduceInst_Chain_Rule( s, rule, mem, mach );
1670 }
1671
1672 // If a Memory was used, insert a Memory edge
1673 if( mem != (Node*)1 ) {
1674 mach->ins_req(MemNode::Memory,mem);
1675 #ifdef ASSERT
1676 // Verify adr type after matching memory operation
1677 const MachOper* oper = mach->memory_operand();
1678 if (oper != NULL && oper != (MachOper*)-1) {
1679 // It has a unique memory operand. Find corresponding ideal mem node.
1680 Node* m = NULL;
1681 if (leaf->is_Mem()) {
1682 m = leaf;
1683 } else {
1684 m = _mem_node;
1685 assert(m != NULL && m->is_Mem(), "expecting memory node");
1686 }
1687 const Type* mach_at = mach->adr_type();
1688 // DecodeN node consumed by an address may have different type
1689 // then its input. Don't compare types for such case.
1690 if (m->adr_type() != mach_at &&
1691 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1692 m->in(MemNode::Address)->is_AddP() &&
1693 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1694 m->in(MemNode::Address)->is_AddP() &&
1695 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1696 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1697 mach_at = m->adr_type();
1698 }
1699 if (m->adr_type() != mach_at) {
1700 m->dump();
1701 tty->print_cr("mach:");
1702 mach->dump(1);
1703 }
1704 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1705 }
1706 #endif
1707 }
1708
1709 // If the _leaf is an AddP, insert the base edge
1710 if (leaf->is_AddP()) {
1711 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1712 }
1713
1714 uint number_of_projections_prior = number_of_projections();
1715
1716 // Perform any 1-to-many expansions required
1717 MachNode *ex = mach->Expand(s, _projection_list, mem);
1718 if (ex != mach) {
1719 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1720 if( ex->in(1)->is_Con() )
1721 ex->in(1)->set_req(0, C->root());
1722 // Remove old node from the graph
1723 for( uint i=0; i<mach->req(); i++ ) {
1724 mach->set_req(i,NULL);
1725 }
1726 #ifdef ASSERT
1727 _new2old_map.map(ex->_idx, s->_leaf);
1728 #endif
1729 }
1730
1731 // PhaseChaitin::fixup_spills will sometimes generate spill code
1732 // via the matcher. By the time, nodes have been wired into the CFG,
1733 // and any further nodes generated by expand rules will be left hanging
1734 // in space, and will not get emitted as output code. Catch this.
1735 // Also, catch any new register allocation constraints ("projections")
1736 // generated belatedly during spill code generation.
1737 if (_allocation_started) {
1738 guarantee(ex == mach, "no expand rules during spill generation");
1739 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1740 }
1741
1742 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1743 // Record the con for sharing
1744 _shared_nodes.map(leaf->_idx, ex);
1745 }
1746
1747 return ex;
1748 }
1749
1750 static void handle_precedence_edges(Node* n, MachNode *mach) {
1751 for (uint i = n->req(); i < n->len(); i++) {
1752 if (n->in(i) != NULL) {
1753 mach->add_prec(n->in(i));
1754 }
1755 }
1756 }
1757
1758 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1759 // 'op' is what I am expecting to receive
1760 int op = _leftOp[rule];
1761 // Operand type to catch childs result
1762 // This is what my child will give me.
1763 int opnd_class_instance = s->_rule[op];
1764 // Choose between operand class or not.
1765 // This is what I will receive.
1766 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1767 // New rule for child. Chase operand classes to get the actual rule.
1768 int newrule = s->_rule[catch_op];
1769
1770 if( newrule < NUM_OPERANDS ) {
1771 // Chain from operand or operand class, may be output of shared node
1772 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1773 "Bad AD file: Instruction chain rule must chain from operand");
1774 // Insert operand into array of operands for this instruction
1775 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1776
1777 ReduceOper( s, newrule, mem, mach );
1778 } else {
1779 // Chain from the result of an instruction
1780 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1781 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1782 Node *mem1 = (Node*)1;
1783 debug_only(Node *save_mem_node = _mem_node;)
1784 mach->add_req( ReduceInst(s, newrule, mem1) );
1785 debug_only(_mem_node = save_mem_node;)
1786 }
1787 return;
1788 }
1789
1790
1791 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1792 handle_precedence_edges(s->_leaf, mach);
1793
1794 if( s->_leaf->is_Load() ) {
1795 Node *mem2 = s->_leaf->in(MemNode::Memory);
1796 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1797 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1798 mem = mem2;
1799 }
1800 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1801 if( mach->in(0) == NULL )
1802 mach->set_req(0, s->_leaf->in(0));
1803 }
1804
1805 // Now recursively walk the state tree & add operand list.
1806 for( uint i=0; i<2; i++ ) { // binary tree
1807 State *newstate = s->_kids[i];
1808 if( newstate == NULL ) break; // Might only have 1 child
1809 // 'op' is what I am expecting to receive
1810 int op;
1811 if( i == 0 ) {
1812 op = _leftOp[rule];
1813 } else {
1814 op = _rightOp[rule];
1815 }
1816 // Operand type to catch childs result
1817 // This is what my child will give me.
1818 int opnd_class_instance = newstate->_rule[op];
1819 // Choose between operand class or not.
1820 // This is what I will receive.
1821 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1822 // New rule for child. Chase operand classes to get the actual rule.
1823 int newrule = newstate->_rule[catch_op];
1824
1825 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1826 // Operand/operandClass
1827 // Insert operand into array of operands for this instruction
1828 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1829 ReduceOper( newstate, newrule, mem, mach );
1830
1831 } else { // Child is internal operand or new instruction
1832 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1833 // internal operand --> call ReduceInst_Interior
1834 // Interior of complex instruction. Do nothing but recurse.
1835 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1836 } else {
1837 // instruction --> call build operand( ) to catch result
1838 // --> ReduceInst( newrule )
1839 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1840 Node *mem1 = (Node*)1;
1841 debug_only(Node *save_mem_node = _mem_node;)
1842 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1843 debug_only(_mem_node = save_mem_node;)
1844 }
1845 }
1846 assert( mach->_opnds[num_opnds-1], "" );
1847 }
1848 return num_opnds;
1849 }
1850
1851 // This routine walks the interior of possible complex operands.
1852 // At each point we check our children in the match tree:
1853 // (1) No children -
1854 // We are a leaf; add _leaf field as an input to the MachNode
1855 // (2) Child is an internal operand -
1856 // Skip over it ( do nothing )
1857 // (3) Child is an instruction -
1858 // Call ReduceInst recursively and
1859 // and instruction as an input to the MachNode
1860 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1861 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1862 State *kid = s->_kids[0];
1863 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1864
1865 // Leaf? And not subsumed?
1866 if( kid == NULL && !_swallowed[rule] ) {
1867 mach->add_req( s->_leaf ); // Add leaf pointer
1868 return; // Bail out
1869 }
1870
1871 if( s->_leaf->is_Load() ) {
1872 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1873 mem = s->_leaf->in(MemNode::Memory);
1874 debug_only(_mem_node = s->_leaf;)
1875 }
1876
1877 handle_precedence_edges(s->_leaf, mach);
1878
1879 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1880 if( !mach->in(0) )
1881 mach->set_req(0,s->_leaf->in(0));
1882 else {
1883 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1884 }
1885 }
1886
1887 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1888 int newrule;
1889 if( i == 0)
1890 newrule = kid->_rule[_leftOp[rule]];
1891 else
1892 newrule = kid->_rule[_rightOp[rule]];
1893
1894 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1895 // Internal operand; recurse but do nothing else
1896 ReduceOper( kid, newrule, mem, mach );
1897
1898 } else { // Child is a new instruction
1899 // Reduce the instruction, and add a direct pointer from this
1900 // machine instruction to the newly reduced one.
1901 Node *mem1 = (Node*)1;
1902 debug_only(Node *save_mem_node = _mem_node;)
1903 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1904 debug_only(_mem_node = save_mem_node;)
1905 }
1906 }
1907 }
1908
1909
1910 // -------------------------------------------------------------------------
1911 // Java-Java calling convention
1912 // (what you use when Java calls Java)
1913
1914 //------------------------------find_receiver----------------------------------
1915 // For a given signature, return the OptoReg for parameter 0.
1916 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1917 VMRegPair regs;
1918 BasicType sig_bt = T_OBJECT;
1919 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1920 // Return argument 0 register. In the LP64 build pointers
1921 // take 2 registers, but the VM wants only the 'main' name.
1922 return OptoReg::as_OptoReg(regs.first());
1923 }
1924
1925 // This function identifies sub-graphs in which a 'load' node is
1926 // input to two different nodes, and such that it can be matched
1927 // with BMI instructions like blsi, blsr, etc.
1928 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1929 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1930 // refers to the same node.
1931 #ifdef X86
1932 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1933 // This is a temporary solution until we make DAGs expressible in ADL.
1934 template<typename ConType>
1935 class FusedPatternMatcher {
1936 Node* _op1_node;
1937 Node* _mop_node;
1938 int _con_op;
1939
1940 static int match_next(Node* n, int next_op, int next_op_idx) {
1941 if (n->in(1) == NULL || n->in(2) == NULL) {
1942 return -1;
1943 }
1944
1945 if (next_op_idx == -1) { // n is commutative, try rotations
1946 if (n->in(1)->Opcode() == next_op) {
1947 return 1;
1948 } else if (n->in(2)->Opcode() == next_op) {
1949 return 2;
1950 }
1951 } else {
1952 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1953 if (n->in(next_op_idx)->Opcode() == next_op) {
1954 return next_op_idx;
1955 }
1956 }
1957 return -1;
1958 }
1959 public:
1960 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1961 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1962
1963 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1964 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1965 typename ConType::NativeType con_value) {
1966 if (_op1_node->Opcode() != op1) {
1967 return false;
1968 }
1969 if (_mop_node->outcnt() > 2) {
1970 return false;
1971 }
1972 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1973 if (op1_op2_idx == -1) {
1974 return false;
1975 }
1976 // Memory operation must be the other edge
1977 int op1_mop_idx = (op1_op2_idx & 1) + 1;
1978
1979 // Check that the mop node is really what we want
1980 if (_op1_node->in(op1_mop_idx) == _mop_node) {
1981 Node *op2_node = _op1_node->in(op1_op2_idx);
1982 if (op2_node->outcnt() > 1) {
1983 return false;
1984 }
1985 assert(op2_node->Opcode() == op2, "Should be");
1986 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
1987 if (op2_con_idx == -1) {
1988 return false;
1989 }
1990 // Memory operation must be the other edge
1991 int op2_mop_idx = (op2_con_idx & 1) + 1;
1992 // Check that the memory operation is the same node
1993 if (op2_node->in(op2_mop_idx) == _mop_node) {
1994 // Now check the constant
1995 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1996 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1997 return true;
1998 }
1999 }
2000 }
2001 return false;
2002 }
2003 };
2004
2005
2006 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2007 if (n != NULL && m != NULL) {
2008 if (m->Opcode() == Op_LoadI) {
2009 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2010 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2011 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2012 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2013 } else if (m->Opcode() == Op_LoadL) {
2014 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2015 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2016 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2017 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2018 }
2019 }
2020 return false;
2021 }
2022 #endif // X86
2023
2024 // A method-klass-holder may be passed in the inline_cache_reg
2025 // and then expanded into the inline_cache_reg and a method_oop register
2026 // defined in ad_<arch>.cpp
2027
2028
2029 //------------------------------find_shared------------------------------------
2030 // Set bits if Node is shared or otherwise a root
2031 void Matcher::find_shared( Node *n ) {
2032 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
2033 MStack mstack(C->unique() * 2);
2034 // Mark nodes as address_visited if they are inputs to an address expression
2035 VectorSet address_visited(Thread::current()->resource_area());
2036 mstack.push(n, Visit); // Don't need to pre-visit root node
2037 while (mstack.is_nonempty()) {
2038 n = mstack.node(); // Leave node on stack
2039 Node_State nstate = mstack.state();
2040 uint nop = n->Opcode();
2041 if (nstate == Pre_Visit) {
2042 if (address_visited.test(n->_idx)) { // Visited in address already?
2043 // Flag as visited and shared now.
2044 set_visited(n);
2045 }
2046 if (is_visited(n)) { // Visited already?
2047 // Node is shared and has no reason to clone. Flag it as shared.
2048 // This causes it to match into a register for the sharing.
2049 set_shared(n); // Flag as shared and
2050 mstack.pop(); // remove node from stack
2051 continue;
2052 }
2053 nstate = Visit; // Not already visited; so visit now
2054 }
2055 if (nstate == Visit) {
2056 mstack.set_state(Post_Visit);
2057 set_visited(n); // Flag as visited now
2058 bool mem_op = false;
2059
2060 switch( nop ) { // Handle some opcodes special
2061 case Op_Phi: // Treat Phis as shared roots
2062 case Op_Parm:
2063 case Op_Proj: // All handled specially during matching
2064 case Op_SafePointScalarObject:
2065 set_shared(n);
2066 set_dontcare(n);
2067 break;
2068 case Op_If:
2069 case Op_CountedLoopEnd:
2070 mstack.set_state(Alt_Post_Visit); // Alternative way
2071 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2072 // with matching cmp/branch in 1 instruction. The Matcher needs the
2073 // Bool and CmpX side-by-side, because it can only get at constants
2074 // that are at the leaves of Match trees, and the Bool's condition acts
2075 // as a constant here.
2076 mstack.push(n->in(1), Visit); // Clone the Bool
2077 mstack.push(n->in(0), Pre_Visit); // Visit control input
2078 continue; // while (mstack.is_nonempty())
2079 case Op_ConvI2D: // These forms efficiently match with a prior
2080 case Op_ConvI2F: // Load but not a following Store
2081 if( n->in(1)->is_Load() && // Prior load
2082 n->outcnt() == 1 && // Not already shared
2083 n->unique_out()->is_Store() ) // Following store
2084 set_shared(n); // Force it to be a root
2085 break;
2086 case Op_ReverseBytesI:
2087 case Op_ReverseBytesL:
2088 if( n->in(1)->is_Load() && // Prior load
2089 n->outcnt() == 1 ) // Not already shared
2090 set_shared(n); // Force it to be a root
2091 break;
2092 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2093 case Op_IfFalse:
2094 case Op_IfTrue:
2095 case Op_MachProj:
2096 case Op_MergeMem:
2097 case Op_Catch:
2098 case Op_CatchProj:
2099 case Op_CProj:
2100 case Op_JumpProj:
2101 case Op_JProj:
2102 case Op_NeverBranch:
2103 set_dontcare(n);
2104 break;
2105 case Op_Jump:
2106 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2107 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2108 continue; // while (mstack.is_nonempty())
2109 case Op_StrComp:
2110 case Op_StrEquals:
2111 case Op_StrIndexOf:
2112 case Op_AryEq:
2113 case Op_EncodeISOArray:
2114 set_shared(n); // Force result into register (it will be anyways)
2115 break;
2116 case Op_ConP: { // Convert pointers above the centerline to NUL
2117 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2118 const TypePtr* tp = tn->type()->is_ptr();
2119 if (tp->_ptr == TypePtr::AnyNull) {
2120 tn->set_type(TypePtr::NULL_PTR);
2121 }
2122 break;
2123 }
2124 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2125 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2126 const TypePtr* tp = tn->type()->make_ptr();
2127 if (tp && tp->_ptr == TypePtr::AnyNull) {
2128 tn->set_type(TypeNarrowOop::NULL_PTR);
2129 }
2130 break;
2131 }
2132 case Op_Binary: // These are introduced in the Post_Visit state.
2133 ShouldNotReachHere();
2134 break;
2135 case Op_ClearArray:
2136 case Op_SafePoint:
2137 mem_op = true;
2138 break;
2139 default:
2140 if( n->is_Store() ) {
2141 // Do match stores, despite no ideal reg
2142 mem_op = true;
2143 break;
2144 }
2145 if( n->is_Mem() ) { // Loads and LoadStores
2146 mem_op = true;
2147 // Loads must be root of match tree due to prior load conflict
2148 if( C->subsume_loads() == false )
2149 set_shared(n);
2150 }
2151 // Fall into default case
2152 if( !n->ideal_reg() )
2153 set_dontcare(n); // Unmatchable Nodes
2154 } // end_switch
2155
2156 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2157 Node *m = n->in(i); // Get ith input
2158 if (m == NULL) continue; // Ignore NULLs
2159 uint mop = m->Opcode();
2160
2161 // Must clone all producers of flags, or we will not match correctly.
2162 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2163 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2164 // are also there, so we may match a float-branch to int-flags and
2165 // expect the allocator to haul the flags from the int-side to the
2166 // fp-side. No can do.
2167 if( _must_clone[mop] ) {
2168 mstack.push(m, Visit);
2169 continue; // for(int i = ...)
2170 }
2171
2172 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2173 // Bases used in addresses must be shared but since
2174 // they are shared through a DecodeN they may appear
2175 // to have a single use so force sharing here.
2176 set_shared(m->in(AddPNode::Base)->in(1));
2177 }
2178
2179 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2180 #ifdef X86
2181 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2182 mstack.push(m, Visit);
2183 continue;
2184 }
2185 #endif
2186
2187 // Clone addressing expressions as they are "free" in memory access instructions
2188 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2189 // Some inputs for address expression are not put on stack
2190 // to avoid marking them as shared and forcing them into register
2191 // if they are used only in address expressions.
2192 // But they should be marked as shared if there are other uses
2193 // besides address expressions.
2194
2195 Node *off = m->in(AddPNode::Offset);
2196 if( off->is_Con() &&
2197 // When there are other uses besides address expressions
2198 // put it on stack and mark as shared.
2199 !is_visited(m) ) {
2200 address_visited.test_set(m->_idx); // Flag as address_visited
2201 Node *adr = m->in(AddPNode::Address);
2202
2203 // Intel, ARM and friends can handle 2 adds in addressing mode
2204 if( clone_shift_expressions && adr->is_AddP() &&
2205 // AtomicAdd is not an addressing expression.
2206 // Cheap to find it by looking for screwy base.
2207 !adr->in(AddPNode::Base)->is_top() &&
2208 // Are there other uses besides address expressions?
2209 !is_visited(adr) ) {
2210 address_visited.set(adr->_idx); // Flag as address_visited
2211 Node *shift = adr->in(AddPNode::Offset);
2212 // Check for shift by small constant as well
2213 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2214 shift->in(2)->get_int() <= 3 &&
2215 // Are there other uses besides address expressions?
2216 !is_visited(shift) ) {
2217 address_visited.set(shift->_idx); // Flag as address_visited
2218 mstack.push(shift->in(2), Visit);
2219 Node *conv = shift->in(1);
2220 #ifdef _LP64
2221 // Allow Matcher to match the rule which bypass
2222 // ConvI2L operation for an array index on LP64
2223 // if the index value is positive.
2224 if( conv->Opcode() == Op_ConvI2L &&
2225 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2226 // Are there other uses besides address expressions?
2227 !is_visited(conv) ) {
2228 address_visited.set(conv->_idx); // Flag as address_visited
2229 mstack.push(conv->in(1), Pre_Visit);
2230 } else
2231 #endif
2232 mstack.push(conv, Pre_Visit);
2233 } else {
2234 mstack.push(shift, Pre_Visit);
2235 }
2236 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2237 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2238 } else { // Sparc, Alpha, PPC and friends
2239 mstack.push(adr, Pre_Visit);
2240 }
2241
2242 // Clone X+offset as it also folds into most addressing expressions
2243 mstack.push(off, Visit);
2244 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2245 continue; // for(int i = ...)
2246 } // if( off->is_Con() )
2247 } // if( mem_op &&
2248 mstack.push(m, Pre_Visit);
2249 } // for(int i = ...)
2250 }
2251 else if (nstate == Alt_Post_Visit) {
2252 mstack.pop(); // Remove node from stack
2253 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2254 // shared and all users of the Bool need to move the Cmp in parallel.
2255 // This leaves both the Bool and the If pointing at the Cmp. To
2256 // prevent the Matcher from trying to Match the Cmp along both paths
2257 // BoolNode::match_edge always returns a zero.
2258
2259 // We reorder the Op_If in a pre-order manner, so we can visit without
2260 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2261 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2262 }
2263 else if (nstate == Post_Visit) {
2264 mstack.pop(); // Remove node from stack
2265
2266 // Now hack a few special opcodes
2267 switch( n->Opcode() ) { // Handle some opcodes special
2268 case Op_StorePConditional:
2269 case Op_StoreIConditional:
2270 case Op_StoreLConditional:
2271 case Op_CompareAndSwapI:
2272 case Op_CompareAndSwapL:
2273 case Op_CompareAndSwapP:
2274 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2275 Node *newval = n->in(MemNode::ValueIn );
2276 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2277 Node *pair = new BinaryNode( oldval, newval );
2278 n->set_req(MemNode::ValueIn,pair);
2279 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2280 break;
2281 }
2282 case Op_CMoveD: // Convert trinary to binary-tree
2283 case Op_CMoveF:
2284 case Op_CMoveI:
2285 case Op_CMoveL:
2286 case Op_CMoveN:
2287 case Op_CMoveP: {
2288 // Restructure into a binary tree for Matching. It's possible that
2289 // we could move this code up next to the graph reshaping for IfNodes
2290 // or vice-versa, but I do not want to debug this for Ladybird.
2291 // 10/2/2000 CNC.
2292 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2293 n->set_req(1,pair1);
2294 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2295 n->set_req(2,pair2);
2296 n->del_req(3);
2297 break;
2298 }
2299 case Op_LoopLimit: {
2300 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2301 n->set_req(1,pair1);
2302 n->set_req(2,n->in(3));
2303 n->del_req(3);
2304 break;
2305 }
2306 case Op_StrEquals: {
2307 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2308 n->set_req(2,pair1);
2309 n->set_req(3,n->in(4));
2310 n->del_req(4);
2311 break;
2312 }
2313 case Op_StrComp:
2314 case Op_StrIndexOf: {
2315 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2316 n->set_req(2,pair1);
2317 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2318 n->set_req(3,pair2);
2319 n->del_req(5);
2320 n->del_req(4);
2321 break;
2322 }
2323 case Op_EncodeISOArray: {
2324 // Restructure into a binary tree for Matching.
2325 Node* pair = new BinaryNode(n->in(3), n->in(4));
2326 n->set_req(3, pair);
2327 n->del_req(4);
2328 break;
2329 }
2330 default:
2331 break;
2332 }
2333 }
2334 else {
2335 ShouldNotReachHere();
2336 }
2337 } // end of while (mstack.is_nonempty())
2338 }
2339
2340 #ifdef ASSERT
2341 // machine-independent root to machine-dependent root
2342 void Matcher::dump_old2new_map() {
2343 _old2new_map.dump();
2344 }
2345 #endif
2346
2347 //---------------------------collect_null_checks-------------------------------
2348 // Find null checks in the ideal graph; write a machine-specific node for
2349 // it. Used by later implicit-null-check handling. Actually collects
2350 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2351 // value being tested.
2352 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2353 Node *iff = proj->in(0);
2354 if( iff->Opcode() == Op_If ) {
2355 // During matching If's have Bool & Cmp side-by-side
2356 BoolNode *b = iff->in(1)->as_Bool();
2357 Node *cmp = iff->in(2);
2358 int opc = cmp->Opcode();
2359 if (opc != Op_CmpP && opc != Op_CmpN) return;
2360
2361 const Type* ct = cmp->in(2)->bottom_type();
2362 if (ct == TypePtr::NULL_PTR ||
2363 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2364
2365 bool push_it = false;
2366 if( proj->Opcode() == Op_IfTrue ) {
2367 extern int all_null_checks_found;
2368 all_null_checks_found++;
2369 if( b->_test._test == BoolTest::ne ) {
2370 push_it = true;
2371 }
2372 } else {
2373 assert( proj->Opcode() == Op_IfFalse, "" );
2374 if( b->_test._test == BoolTest::eq ) {
2375 push_it = true;
2376 }
2377 }
2378 if( push_it ) {
2379 _null_check_tests.push(proj);
2380 Node* val = cmp->in(1);
2381 #ifdef _LP64
2382 if (val->bottom_type()->isa_narrowoop() &&
2383 !Matcher::narrow_oop_use_complex_address()) {
2384 //
2385 // Look for DecodeN node which should be pinned to orig_proj.
2386 // On platforms (Sparc) which can not handle 2 adds
2387 // in addressing mode we have to keep a DecodeN node and
2388 // use it to do implicit NULL check in address.
2389 //
2390 // DecodeN node was pinned to non-null path (orig_proj) during
2391 // CastPP transformation in final_graph_reshaping_impl().
2392 //
2393 uint cnt = orig_proj->outcnt();
2394 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2395 Node* d = orig_proj->raw_out(i);
2396 if (d->is_DecodeN() && d->in(1) == val) {
2397 val = d;
2398 val->set_req(0, NULL); // Unpin now.
2399 // Mark this as special case to distinguish from
2400 // a regular case: CmpP(DecodeN, NULL).
2401 val = (Node*)(((intptr_t)val) | 1);
2402 break;
2403 }
2404 }
2405 }
2406 #endif
2407 _null_check_tests.push(val);
2408 }
2409 }
2410 }
2411 }
2412
2413 //---------------------------validate_null_checks------------------------------
2414 // Its possible that the value being NULL checked is not the root of a match
2415 // tree. If so, I cannot use the value in an implicit null check.
2416 void Matcher::validate_null_checks( ) {
2417 uint cnt = _null_check_tests.size();
2418 for( uint i=0; i < cnt; i+=2 ) {
2419 Node *test = _null_check_tests[i];
2420 Node *val = _null_check_tests[i+1];
2421 bool is_decoden = ((intptr_t)val) & 1;
2422 val = (Node*)(((intptr_t)val) & ~1);
2423 if (has_new_node(val)) {
2424 Node* new_val = new_node(val);
2425 if (is_decoden) {
2426 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2427 // Note: new_val may have a control edge if
2428 // the original ideal node DecodeN was matched before
2429 // it was unpinned in Matcher::collect_null_checks().
2430 // Unpin the mach node and mark it.
2431 new_val->set_req(0, NULL);
2432 new_val = (Node*)(((intptr_t)new_val) | 1);
2433 }
2434 // Is a match-tree root, so replace with the matched value
2435 _null_check_tests.map(i+1, new_val);
2436 } else {
2437 // Yank from candidate list
2438 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2439 _null_check_tests.map(i,_null_check_tests[--cnt]);
2440 _null_check_tests.pop();
2441 _null_check_tests.pop();
2442 i-=2;
2443 }
2444 }
2445 }
2446
2447 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2448 // atomic instruction acting as a store_load barrier without any
2449 // intervening volatile load, and thus we don't need a barrier here.
2450 // We retain the Node to act as a compiler ordering barrier.
2451 bool Matcher::post_store_load_barrier(const Node* vmb) {
2452 Compile* C = Compile::current();
2453 assert(vmb->is_MemBar(), "");
2454 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2455 const MemBarNode* membar = vmb->as_MemBar();
2456
2457 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2458 Node* ctrl = NULL;
2459 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2460 Node* p = membar->fast_out(i);
2461 assert(p->is_Proj(), "only projections here");
2462 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2463 !C->node_arena()->contains(p)) { // Unmatched old-space only
2464 ctrl = p;
2465 break;
2466 }
2467 }
2468 assert((ctrl != NULL), "missing control projection");
2469
2470 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2471 Node *x = ctrl->fast_out(j);
2472 int xop = x->Opcode();
2473
2474 // We don't need current barrier if we see another or a lock
2475 // before seeing volatile load.
2476 //
2477 // Op_Fastunlock previously appeared in the Op_* list below.
2478 // With the advent of 1-0 lock operations we're no longer guaranteed
2479 // that a monitor exit operation contains a serializing instruction.
2480
2481 if (xop == Op_MemBarVolatile ||
2482 xop == Op_CompareAndSwapL ||
2483 xop == Op_CompareAndSwapP ||
2484 xop == Op_CompareAndSwapN ||
2485 xop == Op_CompareAndSwapI) {
2486 return true;
2487 }
2488
2489 // Op_FastLock previously appeared in the Op_* list above.
2490 // With biased locking we're no longer guaranteed that a monitor
2491 // enter operation contains a serializing instruction.
2492 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2493 return true;
2494 }
2495
2496 if (x->is_MemBar()) {
2497 // We must retain this membar if there is an upcoming volatile
2498 // load, which will be followed by acquire membar.
2499 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2500 return false;
2501 } else {
2502 // For other kinds of barriers, check by pretending we
2503 // are them, and seeing if we can be removed.
2504 return post_store_load_barrier(x->as_MemBar());
2505 }
2506 }
2507
2508 // probably not necessary to check for these
2509 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2510 return false;
2511 }
2512 }
2513 return false;
2514 }
2515
2516 // Check whether node n is a branch to an uncommon trap that we could
2517 // optimize as test with very high branch costs in case of going to
2518 // the uncommon trap. The code must be able to be recompiled to use
2519 // a cheaper test.
2520 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2521 // Don't do it for natives, adapters, or runtime stubs
2522 Compile *C = Compile::current();
2523 if (!C->is_method_compilation()) return false;
2524
2525 assert(n->is_If(), "You should only call this on if nodes.");
2526 IfNode *ifn = n->as_If();
2527
2528 Node *ifFalse = NULL;
2529 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2530 if (ifn->fast_out(i)->is_IfFalse()) {
2531 ifFalse = ifn->fast_out(i);
2532 break;
2533 }
2534 }
2535 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2536
2537 Node *reg = ifFalse;
2538 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2539 // Alternatively use visited set? Seems too expensive.
2540 while (reg != NULL && cnt > 0) {
2541 CallNode *call = NULL;
2542 RegionNode *nxt_reg = NULL;
2543 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2544 Node *o = reg->fast_out(i);
2545 if (o->is_Call()) {
2546 call = o->as_Call();
2547 }
2548 if (o->is_Region()) {
2549 nxt_reg = o->as_Region();
2550 }
2551 }
2552
2553 if (call &&
2554 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2555 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2556 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2557 jint tr_con = trtype->is_int()->get_con();
2558 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2559 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2560 assert((int)reason < (int)BitsPerInt, "recode bit map");
2561
2562 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2563 && action != Deoptimization::Action_none) {
2564 // This uncommon trap is sure to recompile, eventually.
2565 // When that happens, C->too_many_traps will prevent
2566 // this transformation from happening again.
2567 return true;
2568 }
2569 }
2570 }
2571
2572 reg = nxt_reg;
2573 cnt--;
2574 }
2575
2576 return false;
2577 }
2578
2579 //=============================================================================
2580 //---------------------------State---------------------------------------------
2581 State::State(void) {
2582 #ifdef ASSERT
2583 _id = 0;
2584 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2585 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2586 //memset(_cost, -1, sizeof(_cost));
2587 //memset(_rule, -1, sizeof(_rule));
2588 #endif
2589 memset(_valid, 0, sizeof(_valid));
2590 }
2591
2592 #ifdef ASSERT
2593 State::~State() {
2594 _id = 99;
2595 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2596 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2597 memset(_cost, -3, sizeof(_cost));
2598 memset(_rule, -3, sizeof(_rule));
2599 }
2600 #endif
2601
2602 #ifndef PRODUCT
2603 //---------------------------dump----------------------------------------------
2604 void State::dump() {
2605 tty->print("\n");
2606 dump(0);
2607 }
2608
2609 void State::dump(int depth) {
2610 for( int j = 0; j < depth; j++ )
2611 tty->print(" ");
2612 tty->print("--N: ");
2613 _leaf->dump();
2614 uint i;
2615 for( i = 0; i < _LAST_MACH_OPER; i++ )
2616 // Check for valid entry
2617 if( valid(i) ) {
2618 for( int j = 0; j < depth; j++ )
2619 tty->print(" ");
2620 assert(_cost[i] != max_juint, "cost must be a valid value");
2621 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2622 tty->print_cr("%s %d %s",
2623 ruleName[i], _cost[i], ruleName[_rule[i]] );
2624 }
2625 tty->cr();
2626
2627 for( i=0; i<2; i++ )
2628 if( _kids[i] )
2629 _kids[i]->dump(depth+1);
2630 }
2631 #endif