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src/cpu/aarch64/vm/aarch64.ad

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rev 10850 : 8154537: AArch64: some integer rotate instructions are never emitted
Summary: some integer rotate rules in ad file can't be matched
Reviewed-by:
rev 10955 : undo
rev 10957 : 8154826: AArch64: take advantage better of base + shifted offset addressing mode
Summary: reshape address subtree to fit aarch64 addressing mode
Reviewed-by:
rev 10958 : more
rev 10959 : more
rev 10960 : more addressing
rev 10962 : 8155015: Aarch64: bad assert in spill generation code
Reviewed-by:

@@ -3075,11 +3075,11 @@
     if (cbuf) {
       MacroAssembler _masm(cbuf);
       assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity");
       if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
         // stack->stack
-        assert((src_offset & 7) && (dst_offset & 7), "unaligned stack offset");
+        assert((src_offset & 7) == 0 && (dst_offset & 7) == 0, "unaligned stack offset");
         if (ireg == Op_VecD) {
           __ unspill(rscratch1, true, src_offset);
           __ spill(rscratch1, true, dst_offset);
         } else {
           __ spill_copy128(src_offset, dst_offset);
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