1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/macroAssembler.hpp" 28 #include "asm/macroAssembler.inline.hpp" 29 #include "memory/resourceArea.hpp" 30 #include "runtime/java.hpp" 31 #include "runtime/stubCodeGenerator.hpp" 32 #include "utilities/macros.hpp" 33 #include "vm_version_aarch64.hpp" 34 35 #include OS_HEADER_INLINE(os) 36 37 #ifndef BUILTIN_SIM 38 #include <sys/auxv.h> 39 #include <asm/hwcap.h> 40 #else 41 #define getauxval(hwcap) 0 42 #endif 43 44 #ifndef HWCAP_AES 45 #define HWCAP_AES (1<<3) 46 #endif 47 48 #ifndef HWCAP_PMULL 49 #define HWCAP_PMULL (1<<4) 50 #endif 51 52 #ifndef HWCAP_SHA1 53 #define HWCAP_SHA1 (1<<5) 54 #endif 55 56 #ifndef HWCAP_SHA2 57 #define HWCAP_SHA2 (1<<6) 58 #endif 59 60 #ifndef HWCAP_CRC32 61 #define HWCAP_CRC32 (1<<7) 62 #endif 63 64 #ifndef HWCAP_ATOMICS 65 #define HWCAP_ATOMICS (1<<8) 66 #endif 67 68 int VM_Version::_cpu; 69 int VM_Version::_model; 70 int VM_Version::_model2; 71 int VM_Version::_variant; 72 int VM_Version::_revision; 73 int VM_Version::_stepping; 74 VM_Version::PsrInfo VM_Version::_psr_info = { 0, }; 75 76 static BufferBlob* stub_blob; 77 static const int stub_size = 550; 78 79 extern "C" { 80 typedef void (*getPsrInfo_stub_t)(void*); 81 } 82 static getPsrInfo_stub_t getPsrInfo_stub = NULL; 83 84 85 class VM_Version_StubGenerator: public StubCodeGenerator { 86 public: 87 88 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} 89 90 address generate_getPsrInfo() { 91 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); 92 # define __ _masm-> 93 address start = __ pc(); 94 95 #ifdef BUILTIN_SIM 96 __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void); 97 #endif 98 99 // void getPsrInfo(VM_Version::PsrInfo* psr_info); 100 101 address entry = __ pc(); 102 103 __ enter(); 104 105 __ get_dczid_el0(rscratch1); 106 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset()))); 107 108 __ get_ctr_el0(rscratch1); 109 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset()))); 110 111 __ leave(); 112 __ ret(lr); 113 114 # undef __ 115 116 return start; 117 } 118 }; 119 120 121 void VM_Version::get_processor_features() { 122 _supports_cx8 = true; 123 _supports_atomic_getset4 = true; 124 _supports_atomic_getadd4 = true; 125 _supports_atomic_getset8 = true; 126 _supports_atomic_getadd8 = true; 127 128 getPsrInfo_stub(&_psr_info); 129 130 int dcache_line = VM_Version::dcache_line_size(); 131 132 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) 133 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 3*dcache_line); 134 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) 135 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line); 136 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) 137 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line); 138 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) 139 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line); 140 141 if (PrefetchCopyIntervalInBytes != -1 && 142 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) { 143 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768"); 144 PrefetchCopyIntervalInBytes &= ~7; 145 if (PrefetchCopyIntervalInBytes >= 32768) 146 PrefetchCopyIntervalInBytes = 32760; 147 } 148 149 unsigned long auxv = getauxval(AT_HWCAP); 150 151 char buf[512]; 152 153 _features = auxv; 154 155 int cpu_lines = 0; 156 if (FILE *f = fopen("/proc/cpuinfo", "r")) { 157 char buf[128], *p; 158 while (fgets(buf, sizeof (buf), f) != NULL) { 159 if (p = strchr(buf, ':')) { 160 long v = strtol(p+1, NULL, 0); 161 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) { 162 _cpu = v; 163 cpu_lines++; 164 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) { 165 _variant = v; 166 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) { 167 if (_model != v) _model2 = _model; 168 _model = v; 169 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) { 170 _revision = v; 171 } 172 } 173 } 174 fclose(f); 175 } 176 177 // Enable vendor specific features 178 if (_cpu == CPU_CAVIUM) { 179 if (_variant == 0) _features |= CPU_DMB_ATOMICS; 180 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) { 181 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true); 182 } 183 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) { 184 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0)); 185 } 186 } 187 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) _features |= CPU_A53MAC; 188 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH; 189 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07) 190 // we assume the worst and assume we could be on a big little system and have 191 // undisclosed A53 cores which we could be swapped to at any stage 192 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC; 193 194 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision); 195 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2); 196 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd"); 197 if (auxv & HWCAP_CRC32) strcat(buf, ", crc"); 198 if (auxv & HWCAP_AES) strcat(buf, ", aes"); 199 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1"); 200 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256"); 201 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse"); 202 203 _features_string = os::strdup(buf); 204 205 if (FLAG_IS_DEFAULT(UseCRC32)) { 206 UseCRC32 = (auxv & HWCAP_CRC32) != 0; 207 } 208 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) { 209 warning("UseCRC32 specified, but not supported on this CPU"); 210 } 211 212 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) { 213 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true); 214 } 215 216 if (UseVectorizedMismatchIntrinsic) { 217 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 218 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 219 } 220 221 if (auxv & HWCAP_ATOMICS) { 222 if (FLAG_IS_DEFAULT(UseLSE)) 223 FLAG_SET_DEFAULT(UseLSE, true); 224 } else { 225 if (UseLSE) { 226 warning("UseLSE specified, but not supported on this CPU"); 227 } 228 } 229 230 if (auxv & HWCAP_AES) { 231 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES); 232 UseAESIntrinsics = 233 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics)); 234 if (UseAESIntrinsics && !UseAES) { 235 warning("UseAESIntrinsics enabled, but UseAES not, enabling"); 236 UseAES = true; 237 } 238 } else { 239 if (UseAES) { 240 warning("UseAES specified, but not supported on this CPU"); 241 } 242 if (UseAESIntrinsics) { 243 warning("UseAESIntrinsics specified, but not supported on this CPU"); 244 } 245 } 246 247 if (UseAESCTRIntrinsics) { 248 warning("AES/CTR intrinsics are not available on this CPU"); 249 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 250 } 251 252 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 253 UseCRC32Intrinsics = true; 254 } 255 256 if (auxv & HWCAP_CRC32) { 257 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 258 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); 259 } 260 } else if (UseCRC32CIntrinsics) { 261 warning("CRC32C is not available on the CPU"); 262 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 263 } 264 265 if (UseFMA) { 266 warning("FMA instructions are not available on this CPU"); 267 FLAG_SET_DEFAULT(UseFMA, false); 268 } 269 270 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) { 271 if (FLAG_IS_DEFAULT(UseSHA)) { 272 FLAG_SET_DEFAULT(UseSHA, true); 273 } 274 } else if (UseSHA) { 275 warning("SHA instructions are not available on this CPU"); 276 FLAG_SET_DEFAULT(UseSHA, false); 277 } 278 279 if (UseSHA && (auxv & HWCAP_SHA1)) { 280 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 281 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 282 } 283 } else if (UseSHA1Intrinsics) { 284 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 285 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 286 } 287 288 if (UseSHA && (auxv & HWCAP_SHA2)) { 289 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 290 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 291 } 292 } else if (UseSHA256Intrinsics) { 293 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 294 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 295 } 296 297 if (UseSHA512Intrinsics) { 298 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 299 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 300 } 301 302 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 303 FLAG_SET_DEFAULT(UseSHA, false); 304 } 305 306 if (auxv & HWCAP_PMULL) { 307 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { 308 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true); 309 } 310 } else if (UseGHASHIntrinsics) { 311 warning("GHASH intrinsics are not available on this CPU"); 312 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 313 } 314 315 if (is_zva_enabled()) { 316 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 317 FLAG_SET_DEFAULT(UseBlockZeroing, true); 318 } 319 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) { 320 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length()); 321 } 322 } else if (UseBlockZeroing) { 323 warning("DC ZVA is not available on this CPU"); 324 FLAG_SET_DEFAULT(UseBlockZeroing, false); 325 } 326 327 // This machine allows unaligned memory accesses 328 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 329 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 330 } 331 332 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 333 UseMultiplyToLenIntrinsic = true; 334 } 335 336 if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) { 337 UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0; 338 } 339 340 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 341 UsePopCountInstruction = true; 342 } 343 344 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 345 UseMontgomeryMultiplyIntrinsic = true; 346 } 347 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 348 UseMontgomerySquareIntrinsic = true; 349 } 350 351 #ifdef COMPILER2 352 if (FLAG_IS_DEFAULT(OptoScheduling)) { 353 OptoScheduling = true; 354 } 355 #endif 356 } 357 358 void VM_Version::initialize() { 359 ResourceMark rm; 360 361 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); 362 if (stub_blob == NULL) { 363 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); 364 } 365 366 CodeBuffer c(stub_blob); 367 VM_Version_StubGenerator g(&c); 368 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, 369 g.generate_getPsrInfo()); 370 371 get_processor_features(); 372 }