1012 Node* m = n->fast_out(j); 1013 if (m->is_FastLock()) 1014 return false; 1015 #ifdef _LP64 1016 if (m->Opcode() == Op_ConvI2L) 1017 return false; 1018 if (m->is_CastII() && m->isa_CastII()->has_range_check()) { 1019 return false; 1020 } 1021 #endif 1022 } 1023 } 1024 } 1025 return true; 1026 } 1027 1028 1029 //------------------------------place_near_use--------------------------------- 1030 // Place some computation next to use but not inside inner loops. 1031 // For inner loop uses move it to the preheader area. 1032 Node *PhaseIdealLoop::place_near_use( Node *useblock ) const { 1033 IdealLoopTree *u_loop = get_loop( useblock ); 1034 return (u_loop->_irreducible || u_loop->_child) 1035 ? useblock 1036 : u_loop->_head->as_Loop()->skip_strip_mined()->in(LoopNode::EntryControl); 1037 } 1038 1039 1040 bool PhaseIdealLoop::identical_backtoback_ifs(Node *n) { 1041 if (!n->is_If() || n->is_CountedLoopEnd()) { 1042 return false; 1043 } 1044 if (!n->in(0)->is_Region()) { 1045 return false; 1046 } 1047 Node* region = n->in(0); 1048 Node* dom = idom(region); 1049 if (!dom->is_If() || dom->in(1) != n->in(1)) { 1050 return false; 1051 } 1052 IfNode* dom_if = dom->as_If(); 1053 Node* proj_true = dom_if->proj_out(1); 1054 Node* proj_false = dom_if->proj_out(0); 1055 1056 for (uint i = 1; i < region->req(); i++) { | 1012 Node* m = n->fast_out(j); 1013 if (m->is_FastLock()) 1014 return false; 1015 #ifdef _LP64 1016 if (m->Opcode() == Op_ConvI2L) 1017 return false; 1018 if (m->is_CastII() && m->isa_CastII()->has_range_check()) { 1019 return false; 1020 } 1021 #endif 1022 } 1023 } 1024 } 1025 return true; 1026 } 1027 1028 1029 //------------------------------place_near_use--------------------------------- 1030 // Place some computation next to use but not inside inner loops. 1031 // For inner loop uses move it to the preheader area. 1032 Node *PhaseIdealLoop::place_near_use(Node *useblock) const { 1033 IdealLoopTree *u_loop = get_loop( useblock ); 1034 if (u_loop->_irreducible) { 1035 return useblock; 1036 } 1037 if (u_loop->_child) { 1038 if (useblock == u_loop->_head && u_loop->_head->is_OuterStripMinedLoop()) { 1039 return u_loop->_head->in(LoopNode::EntryControl); 1040 } 1041 return useblock; 1042 } 1043 return u_loop->_head->as_Loop()->skip_strip_mined()->in(LoopNode::EntryControl); 1044 } 1045 1046 1047 bool PhaseIdealLoop::identical_backtoback_ifs(Node *n) { 1048 if (!n->is_If() || n->is_CountedLoopEnd()) { 1049 return false; 1050 } 1051 if (!n->in(0)->is_Region()) { 1052 return false; 1053 } 1054 Node* region = n->in(0); 1055 Node* dom = idom(region); 1056 if (!dom->is_If() || dom->in(1) != n->in(1)) { 1057 return false; 1058 } 1059 IfNode* dom_if = dom->as_If(); 1060 Node* proj_true = dom_if->proj_out(1); 1061 Node* proj_false = dom_if->proj_out(0); 1062 1063 for (uint i = 1; i < region->req(); i++) { |