3321
3322 void Assembler::orl(Register dst, Address src) {
3323 InstructionMark im(this);
3324 prefix(src, dst);
3325 emit_int8(0x0B);
3326 emit_operand(dst, src);
3327 }
3328
3329 void Assembler::orl(Register dst, Register src) {
3330 (void) prefix_and_encode(dst->encoding(), src->encoding());
3331 emit_arith(0x0B, 0xC0, dst, src);
3332 }
3333
3334 void Assembler::orl(Address dst, Register src) {
3335 InstructionMark im(this);
3336 prefix(dst, src);
3337 emit_int8(0x09);
3338 emit_operand(src, dst);
3339 }
3340
3341 void Assembler::packuswb(XMMRegister dst, Address src) {
3342 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3343 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3344 InstructionMark im(this);
3345 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3346 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3347 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3348 emit_int8(0x67);
3349 emit_operand(dst, src);
3350 }
3351
3352 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3355 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3356 emit_int8(0x67);
3357 emit_int8((unsigned char)(0xC0 | encode));
3358 }
3359
3360 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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3321
3322 void Assembler::orl(Register dst, Address src) {
3323 InstructionMark im(this);
3324 prefix(src, dst);
3325 emit_int8(0x0B);
3326 emit_operand(dst, src);
3327 }
3328
3329 void Assembler::orl(Register dst, Register src) {
3330 (void) prefix_and_encode(dst->encoding(), src->encoding());
3331 emit_arith(0x0B, 0xC0, dst, src);
3332 }
3333
3334 void Assembler::orl(Address dst, Register src) {
3335 InstructionMark im(this);
3336 prefix(dst, src);
3337 emit_int8(0x09);
3338 emit_operand(src, dst);
3339 }
3340
3341 void Assembler::orb(Address dst, int imm8) {
3342 InstructionMark im(this);
3343 prefix(dst);
3344 emit_int8((unsigned char)0x80);
3345 emit_operand(rcx, dst, 1);
3346 emit_int8(imm8);
3347 }
3348
3349 void Assembler::packuswb(XMMRegister dst, Address src) {
3350 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3351 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3352 InstructionMark im(this);
3353 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3354 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3355 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3356 emit_int8(0x67);
3357 emit_operand(dst, src);
3358 }
3359
3360 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3361 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3362 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3363 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3364 emit_int8(0x67);
3365 emit_int8((unsigned char)(0xC0 | encode));
3366 }
3367
3368 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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