1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
28
29 #include "asm/register.hpp"
30
31 // definitions of various symbolic names for machine registers
32
33 // First intercalls between C and Java which use 8 general registers
34 // and 8 floating registers
35
36 // we also have to copy between x86 and ARM registers but that's a
37 // secondary complication -- not all code employing C call convention
38 // executes as x86 code though -- we generate some of it
39
40 class Argument {
41 public:
42 enum {
43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
45
46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
48 };
49 };
50
51 REGISTER_DECLARATION(Register, c_rarg0, r0);
52 REGISTER_DECLARATION(Register, c_rarg1, r1);
53 REGISTER_DECLARATION(Register, c_rarg2, r2);
54 REGISTER_DECLARATION(Register, c_rarg3, r3);
55 REGISTER_DECLARATION(Register, c_rarg4, r4);
56 REGISTER_DECLARATION(Register, c_rarg5, r5);
57 REGISTER_DECLARATION(Register, c_rarg6, r6);
58 REGISTER_DECLARATION(Register, c_rarg7, r7);
59
60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
68
69 // Symbolically name the register arguments used by the Java calling convention.
70 // We have control over the convention for java so we can do what we please.
71 // What pleases us is to offset the java calling convention so that when
72 // we call a suitable jni method the arguments are lined up and we don't
73 // have to do much shuffling. A suitable jni method is non-static and a
74 // small number of arguments
75 //
76 // |--------------------------------------------------------------------|
77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
78 // |--------------------------------------------------------------------|
79 // | r0 r1 r2 r3 r4 r5 r6 r7 |
80 // |--------------------------------------------------------------------|
81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
82 // |--------------------------------------------------------------------|
83
84
85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
93
94 // Java floating args are passed as per C
95
96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
104
105 // registers used to hold VM data either temporarily within a method
106 // or across method calls
107
108 // volatile (caller-save) registers
109
110 // r8 is used for indirect result location return
111 // we use it and r9 as scratch registers
112 REGISTER_DECLARATION(Register, rscratch1, r8);
113 REGISTER_DECLARATION(Register, rscratch2, r9);
114
115 // current method -- must be in a call-clobbered register
116 REGISTER_DECLARATION(Register, rmethod, r12);
117
118 // non-volatile (callee-save) registers are r16-29
119 // of which the following are dedicated global state
120
121 // link register
122 REGISTER_DECLARATION(Register, lr, r30);
123 // frame pointer
124 REGISTER_DECLARATION(Register, rfp, r29);
125 // current thread
126 REGISTER_DECLARATION(Register, rthread, r28);
127 // base of heap
128 REGISTER_DECLARATION(Register, rheapbase, r27);
129 // constant pool cache
130 REGISTER_DECLARATION(Register, rcpool, r26);
131 // monitors allocated on stack
132 REGISTER_DECLARATION(Register, rmonitors, r25);
133 // locals on stack
134 REGISTER_DECLARATION(Register, rlocals, r24);
135 // bytecode pointer
136 REGISTER_DECLARATION(Register, rbcp, r22);
137 // Dispatch table base
138 REGISTER_DECLARATION(Register, rdispatch, r21);
139 // Java stack pointer
140 REGISTER_DECLARATION(Register, esp, r20);
141
142 #define assert_cond(ARG1) assert(ARG1, #ARG1)
143
144 namespace asm_util {
145 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
146 };
147
148 using namespace asm_util;
149
150
151 class Assembler;
152
153 class Instruction_aarch64 {
154 unsigned insn;
155 #ifdef ASSERT
156 unsigned bits;
157 #endif
158 Assembler *assem;
159
160 public:
161
162 Instruction_aarch64(class Assembler *as) {
163 #ifdef ASSERT
164 bits = 0;
165 #endif
166 insn = 0;
167 assem = as;
168 }
169
170 inline ~Instruction_aarch64();
171
172 unsigned &get_insn() { return insn; }
173 #ifdef ASSERT
174 unsigned &get_bits() { return bits; }
175 #endif
176
177 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
178 union {
179 unsigned u;
180 int n;
181 };
182
183 u = val << (31 - hi);
184 n = n >> (31 - hi + lo);
185 return n;
186 }
187
188 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
189 int nbits = msb - lsb + 1;
190 assert_cond(msb >= lsb);
191 uint32_t mask = (1U << nbits) - 1;
192 uint32_t result = val >> lsb;
193 result &= mask;
194 return result;
195 }
196
197 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
198 uint32_t uval = extract(val, msb, lsb);
199 return extend(uval, msb - lsb);
200 }
201
202 static void patch(address a, int msb, int lsb, unsigned long val) {
203 int nbits = msb - lsb + 1;
204 guarantee(val < (1U << nbits), "Field too big for insn");
205 assert_cond(msb >= lsb);
206 unsigned mask = (1U << nbits) - 1;
207 val <<= lsb;
208 mask <<= lsb;
209 unsigned target = *(unsigned *)a;
210 target &= ~mask;
211 target |= val;
212 *(unsigned *)a = target;
213 }
214
215 static void spatch(address a, int msb, int lsb, long val) {
216 int nbits = msb - lsb + 1;
217 long chk = val >> (nbits - 1);
218 guarantee (chk == -1 || chk == 0, "Field too big for insn");
219 unsigned uval = val;
220 unsigned mask = (1U << nbits) - 1;
221 uval &= mask;
222 uval <<= lsb;
223 mask <<= lsb;
224 unsigned target = *(unsigned *)a;
225 target &= ~mask;
226 target |= uval;
227 *(unsigned *)a = target;
228 }
229
230 void f(unsigned val, int msb, int lsb) {
231 int nbits = msb - lsb + 1;
232 guarantee(val < (1U << nbits), "Field too big for insn");
233 assert_cond(msb >= lsb);
234 unsigned mask = (1U << nbits) - 1;
235 val <<= lsb;
236 mask <<= lsb;
237 insn |= val;
238 assert_cond((bits & mask) == 0);
239 #ifdef ASSERT
240 bits |= mask;
241 #endif
242 }
243
244 void f(unsigned val, int bit) {
245 f(val, bit, bit);
246 }
247
248 void sf(long val, int msb, int lsb) {
249 int nbits = msb - lsb + 1;
250 long chk = val >> (nbits - 1);
251 guarantee (chk == -1 || chk == 0, "Field too big for insn");
252 unsigned uval = val;
253 unsigned mask = (1U << nbits) - 1;
254 uval &= mask;
255 f(uval, lsb + nbits - 1, lsb);
256 }
257
258 void rf(Register r, int lsb) {
259 f(r->encoding_nocheck(), lsb + 4, lsb);
260 }
261
262 // reg|ZR
263 void zrf(Register r, int lsb) {
264 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
265 }
266
267 // reg|SP
268 void srf(Register r, int lsb) {
269 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
270 }
271
272 void rf(FloatRegister r, int lsb) {
273 f(r->encoding_nocheck(), lsb + 4, lsb);
274 }
275
276 unsigned get(int msb = 31, int lsb = 0) {
277 int nbits = msb - lsb + 1;
278 unsigned mask = ((1U << nbits) - 1) << lsb;
279 assert_cond(bits & mask == mask);
280 return (insn & mask) >> lsb;
281 }
282
283 void fixed(unsigned value, unsigned mask) {
284 assert_cond ((mask & bits) == 0);
285 #ifdef ASSERT
286 bits |= mask;
287 #endif
288 insn |= value;
289 }
290 };
291
292 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
293
294 class PrePost {
295 int _offset;
296 Register _r;
297 public:
298 PrePost(Register reg, int o) : _offset(o), _r(reg) { }
299 int offset() { return _offset; }
300 Register reg() { return _r; }
301 };
302
303 class Pre : public PrePost {
304 public:
305 Pre(Register reg, int o) : PrePost(reg, o) { }
306 };
307 class Post : public PrePost {
308 Register _idx;
309 public:
310 Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; }
311 Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; }
312 Register idx_reg() { return _idx; }
313 };
314
315 namespace ext
316 {
317 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
318 };
319
320 // abs methods which cannot overflow and so are well-defined across
321 // the entire domain of integer types.
322 static inline unsigned int uabs(unsigned int n) {
323 union {
324 unsigned int result;
325 int value;
326 };
327 result = n;
328 if (value < 0) result = -result;
329 return result;
330 }
331 static inline unsigned long uabs(unsigned long n) {
332 union {
333 unsigned long result;
334 long value;
335 };
336 result = n;
337 if (value < 0) result = -result;
338 return result;
339 }
340 static inline unsigned long uabs(long n) { return uabs((unsigned long)n); }
341 static inline unsigned long uabs(int n) { return uabs((unsigned int)n); }
342
343 // Addressing modes
344 class Address {
345 public:
346
347 enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
348 base_plus_offset_reg, literal };
349
350 // Shift and extend for base reg + reg offset addressing
351 class extend {
352 int _option, _shift;
353 ext::operation _op;
354 public:
355 extend() { }
356 extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
357 int option() const{ return _option; }
358 int shift() const { return _shift; }
359 ext::operation op() const { return _op; }
360 };
361 class uxtw : public extend {
362 public:
363 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
364 };
365 class lsl : public extend {
366 public:
367 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
368 };
369 class sxtw : public extend {
370 public:
371 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
372 };
373 class sxtx : public extend {
374 public:
375 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
376 };
377
378 private:
379 Register _base;
380 Register _index;
381 long _offset;
382 enum mode _mode;
383 extend _ext;
384
385 RelocationHolder _rspec;
386
387 // Typically we use AddressLiterals we want to use their rval
388 // However in some situations we want the lval (effect address) of
389 // the item. We provide a special factory for making those lvals.
390 bool _is_lval;
391
392 // If the target is far we'll need to load the ea of this to a
393 // register to reach it. Otherwise if near we can do PC-relative
394 // addressing.
395 address _target;
396
397 public:
398 Address()
399 : _mode(no_mode) { }
400 Address(Register r)
401 : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
402 Address(Register r, int o)
403 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
404 Address(Register r, long o)
405 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
406 Address(Register r, unsigned long o)
407 : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
408 #ifdef ASSERT
409 Address(Register r, ByteSize disp)
410 : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }
411 #endif
412 Address(Register r, Register r1, extend ext = lsl())
413 : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),
414 _ext(ext), _target(0) { }
415 Address(Pre p)
416 : _base(p.reg()), _offset(p.offset()), _mode(pre) { }
417 Address(Post p)
418 : _base(p.reg()), _index(p.idx_reg()), _offset(p.offset()),
419 _mode(p.idx_reg() == NULL ? post : post_reg), _target(0) { }
420 Address(address target, RelocationHolder const& rspec)
421 : _mode(literal),
422 _rspec(rspec),
423 _is_lval(false),
424 _target(target) { }
425 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
426 Address(Register base, RegisterOrConstant index, extend ext = lsl())
427 : _base (base),
428 _offset(0), _ext(ext), _target(0) {
429 if (index.is_register()) {
430 _mode = base_plus_offset_reg;
431 _index = index.as_register();
432 } else {
433 guarantee(ext.option() == ext::uxtx, "should be");
434 assert(index.is_constant(), "should be");
435 _mode = base_plus_offset;
436 _offset = index.as_constant() << ext.shift();
437 }
438 }
439
440 Register base() const {
441 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
442 | _mode == post | _mode == post_reg),
443 "wrong mode");
444 return _base;
445 }
446 long offset() const {
447 return _offset;
448 }
449 Register index() const {
450 return _index;
451 }
452 mode getMode() const {
453 return _mode;
454 }
455 bool uses(Register reg) const { return _base == reg || _index == reg; }
456 address target() const { return _target; }
457 const RelocationHolder& rspec() const { return _rspec; }
458
459 void encode(Instruction_aarch64 *i) const {
460 i->f(0b111, 29, 27);
461 i->srf(_base, 5);
462
463 switch(_mode) {
464 case base_plus_offset:
465 {
466 unsigned size = i->get(31, 30);
467 if (i->get(26, 26) && i->get(23, 23)) {
468 // SIMD Q Type - Size = 128 bits
469 assert(size == 0, "bad size");
470 size = 0b100;
471 }
472 unsigned mask = (1 << size) - 1;
473 if (_offset < 0 || _offset & mask)
474 {
475 i->f(0b00, 25, 24);
476 i->f(0, 21), i->f(0b00, 11, 10);
477 i->sf(_offset, 20, 12);
478 } else {
479 i->f(0b01, 25, 24);
480 i->f(_offset >> size, 21, 10);
481 }
482 }
483 break;
484
485 case base_plus_offset_reg:
486 {
487 i->f(0b00, 25, 24);
488 i->f(1, 21);
489 i->rf(_index, 16);
490 i->f(_ext.option(), 15, 13);
491 unsigned size = i->get(31, 30);
492 if (i->get(26, 26) && i->get(23, 23)) {
493 // SIMD Q Type - Size = 128 bits
494 assert(size == 0, "bad size");
495 size = 0b100;
496 }
497 if (size == 0) // It's a byte
498 i->f(_ext.shift() >= 0, 12);
499 else {
500 if (_ext.shift() > 0)
501 assert(_ext.shift() == (int)size, "bad shift");
502 i->f(_ext.shift() > 0, 12);
503 }
504 i->f(0b10, 11, 10);
505 }
506 break;
507
508 case pre:
509 i->f(0b00, 25, 24);
510 i->f(0, 21), i->f(0b11, 11, 10);
511 i->sf(_offset, 20, 12);
512 break;
513
514 case post:
515 i->f(0b00, 25, 24);
516 i->f(0, 21), i->f(0b01, 11, 10);
517 i->sf(_offset, 20, 12);
518 break;
519
520 default:
521 ShouldNotReachHere();
522 }
523 }
524
525 void encode_pair(Instruction_aarch64 *i) const {
526 switch(_mode) {
527 case base_plus_offset:
528 i->f(0b010, 25, 23);
529 break;
530 case pre:
531 i->f(0b011, 25, 23);
532 break;
533 case post:
534 i->f(0b001, 25, 23);
535 break;
536 default:
537 ShouldNotReachHere();
538 }
539
540 unsigned size; // Operand shift in 32-bit words
541
542 if (i->get(26, 26)) { // float
543 switch(i->get(31, 30)) {
544 case 0b10:
545 size = 2; break;
546 case 0b01:
547 size = 1; break;
548 case 0b00:
549 size = 0; break;
550 default:
551 ShouldNotReachHere();
552 size = 0; // unreachable
553 }
554 } else {
555 size = i->get(31, 31);
556 }
557
558 size = 4 << size;
559 guarantee(_offset % size == 0, "bad offset");
560 i->sf(_offset / size, 21, 15);
561 i->srf(_base, 5);
562 }
563
564 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
565 // Only base + offset is allowed
566 i->f(0b000, 25, 23);
567 unsigned size = i->get(31, 31);
568 size = 4 << size;
569 guarantee(_offset % size == 0, "bad offset");
570 i->sf(_offset / size, 21, 15);
571 i->srf(_base, 5);
572 guarantee(_mode == Address::base_plus_offset,
573 "Bad addressing mode for non-temporal op");
574 }
575
576 void lea(MacroAssembler *, Register) const;
577
578 static bool offset_ok_for_immed(long offset, int shift = 0) {
579 unsigned mask = (1 << shift) - 1;
580 if (offset < 0 || offset & mask) {
581 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
582 } else {
583 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
584 }
585 }
586 };
587
588 // Convience classes
589 class RuntimeAddress: public Address {
590
591 public:
592
593 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
594
595 };
596
597 class OopAddress: public Address {
598
599 public:
600
601 OopAddress(address target) : Address(target, relocInfo::oop_type){}
602
603 };
604
605 class ExternalAddress: public Address {
606 private:
607 static relocInfo::relocType reloc_for_target(address target) {
608 // Sometimes ExternalAddress is used for values which aren't
609 // exactly addresses, like the card table base.
610 // external_word_type can't be used for values in the first page
611 // so just skip the reloc in that case.
612 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
613 }
614
615 public:
616
617 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
618
619 };
620
621 class InternalAddress: public Address {
622
623 public:
624
625 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
626 };
627
628 const int FPUStateSizeInWords = 32 * 2;
629 typedef enum {
630 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
631 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
632 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
633 } prfop;
634
635 class Assembler : public AbstractAssembler {
636
637 #ifndef PRODUCT
638 static const unsigned long asm_bp;
639
640 void emit_long(jint x) {
641 if ((unsigned long)pc() == asm_bp)
642 asm volatile ("nop");
643 AbstractAssembler::emit_int32(x);
644 }
645 #else
646 void emit_long(jint x) {
647 AbstractAssembler::emit_int32(x);
648 }
649 #endif
650
651 public:
652
653 enum { instruction_size = 4 };
654
655 Address adjust(Register base, int offset, bool preIncrement) {
656 if (preIncrement)
657 return Address(Pre(base, offset));
658 else
659 return Address(Post(base, offset));
660 }
661
662 Address pre(Register base, int offset) {
663 return adjust(base, offset, true);
664 }
665
666 Address post(Register base, int offset) {
667 return adjust(base, offset, false);
668 }
669
670 Address post(Register base, Register idx) {
671 return Address(Post(base, idx));
672 }
673
674 Instruction_aarch64* current;
675
676 void set_current(Instruction_aarch64* i) { current = i; }
677
678 void f(unsigned val, int msb, int lsb) {
679 current->f(val, msb, lsb);
680 }
681 void f(unsigned val, int msb) {
682 current->f(val, msb, msb);
683 }
684 void sf(long val, int msb, int lsb) {
685 current->sf(val, msb, lsb);
686 }
687 void rf(Register reg, int lsb) {
688 current->rf(reg, lsb);
689 }
690 void srf(Register reg, int lsb) {
691 current->srf(reg, lsb);
692 }
693 void zrf(Register reg, int lsb) {
694 current->zrf(reg, lsb);
695 }
696 void rf(FloatRegister reg, int lsb) {
697 current->rf(reg, lsb);
698 }
699 void fixed(unsigned value, unsigned mask) {
700 current->fixed(value, mask);
701 }
702
703 void emit() {
704 emit_long(current->get_insn());
705 assert_cond(current->get_bits() == 0xffffffff);
706 current = NULL;
707 }
708
709 typedef void (Assembler::* uncond_branch_insn)(address dest);
710 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
711 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
712 typedef void (Assembler::* prefetch_insn)(address target, prfop);
713
714 void wrap_label(Label &L, uncond_branch_insn insn);
715 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
716 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
717 void wrap_label(Label &L, prfop, prefetch_insn insn);
718
719 // PC-rel. addressing
720
721 void adr(Register Rd, address dest);
722 void _adrp(Register Rd, address dest);
723
724 void adr(Register Rd, const Address &dest);
725 void _adrp(Register Rd, const Address &dest);
726
727 void adr(Register Rd, Label &L) {
728 wrap_label(Rd, L, &Assembler::Assembler::adr);
729 }
730 void _adrp(Register Rd, Label &L) {
731 wrap_label(Rd, L, &Assembler::_adrp);
732 }
733
734 void adrp(Register Rd, const Address &dest, unsigned long &offset);
735
736 #undef INSN
737
738 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
739 int negated_op);
740
741 // Add/subtract (immediate)
742 #define INSN(NAME, decode, negated) \
743 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
744 starti; \
745 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
746 zrf(Rd, 0), srf(Rn, 5); \
747 } \
748 \
749 void NAME(Register Rd, Register Rn, unsigned imm) { \
750 starti; \
751 add_sub_immediate(Rd, Rn, imm, decode, negated); \
752 }
753
754 INSN(addsw, 0b001, 0b011);
755 INSN(subsw, 0b011, 0b001);
756 INSN(adds, 0b101, 0b111);
757 INSN(subs, 0b111, 0b101);
758
759 #undef INSN
760
761 #define INSN(NAME, decode, negated) \
762 void NAME(Register Rd, Register Rn, unsigned imm) { \
763 starti; \
764 add_sub_immediate(Rd, Rn, imm, decode, negated); \
765 }
766
767 INSN(addw, 0b000, 0b010);
768 INSN(subw, 0b010, 0b000);
769 INSN(add, 0b100, 0b110);
770 INSN(sub, 0b110, 0b100);
771
772 #undef INSN
773
774 // Logical (immediate)
775 #define INSN(NAME, decode, is32) \
776 void NAME(Register Rd, Register Rn, uint64_t imm) { \
777 starti; \
778 uint32_t val = encode_logical_immediate(is32, imm); \
779 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
780 srf(Rd, 0), zrf(Rn, 5); \
781 }
782
783 INSN(andw, 0b000, true);
784 INSN(orrw, 0b001, true);
785 INSN(eorw, 0b010, true);
786 INSN(andr, 0b100, false);
787 INSN(orr, 0b101, false);
788 INSN(eor, 0b110, false);
789
790 #undef INSN
791
792 #define INSN(NAME, decode, is32) \
793 void NAME(Register Rd, Register Rn, uint64_t imm) { \
794 starti; \
795 uint32_t val = encode_logical_immediate(is32, imm); \
796 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
797 zrf(Rd, 0), zrf(Rn, 5); \
798 }
799
800 INSN(ands, 0b111, false);
801 INSN(andsw, 0b011, true);
802
803 #undef INSN
804
805 // Move wide (immediate)
806 #define INSN(NAME, opcode) \
807 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
808 assert_cond((shift/16)*16 == shift); \
809 starti; \
810 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
811 f(imm, 20, 5); \
812 rf(Rd, 0); \
813 }
814
815 INSN(movnw, 0b000);
816 INSN(movzw, 0b010);
817 INSN(movkw, 0b011);
818 INSN(movn, 0b100);
819 INSN(movz, 0b110);
820 INSN(movk, 0b111);
821
822 #undef INSN
823
824 // Bitfield
825 #define INSN(NAME, opcode) \
826 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
827 starti; \
828 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
829 zrf(Rn, 5), rf(Rd, 0); \
830 }
831
832 INSN(sbfmw, 0b0001001100);
833 INSN(bfmw, 0b0011001100);
834 INSN(ubfmw, 0b0101001100);
835 INSN(sbfm, 0b1001001101);
836 INSN(bfm, 0b1011001101);
837 INSN(ubfm, 0b1101001101);
838
839 #undef INSN
840
841 // Extract
842 #define INSN(NAME, opcode) \
843 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
844 starti; \
845 f(opcode, 31, 21), f(imms, 15, 10); \
846 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
847 }
848
849 INSN(extrw, 0b00010011100);
850 INSN(extr, 0b10010011110);
851
852 #undef INSN
853
854 // The maximum range of a branch is fixed for the AArch64
855 // architecture. In debug mode we shrink it in order to test
856 // trampolines, but not so small that branches in the interpreter
857 // are out of range.
858 static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
859
860 static bool reachable_from_branch_at(address branch, address target) {
861 return uabs(target - branch) < branch_range;
862 }
863
864 // Unconditional branch (immediate)
865 #define INSN(NAME, opcode) \
866 void NAME(address dest) { \
867 starti; \
868 long offset = (dest - pc()) >> 2; \
869 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
870 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
871 } \
872 void NAME(Label &L) { \
873 wrap_label(L, &Assembler::NAME); \
874 } \
875 void NAME(const Address &dest);
876
877 INSN(b, 0);
878 INSN(bl, 1);
879
880 #undef INSN
881
882 // Compare & branch (immediate)
883 #define INSN(NAME, opcode) \
884 void NAME(Register Rt, address dest) { \
885 long offset = (dest - pc()) >> 2; \
886 starti; \
887 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
888 } \
889 void NAME(Register Rt, Label &L) { \
890 wrap_label(Rt, L, &Assembler::NAME); \
891 }
892
893 INSN(cbzw, 0b00110100);
894 INSN(cbnzw, 0b00110101);
895 INSN(cbz, 0b10110100);
896 INSN(cbnz, 0b10110101);
897
898 #undef INSN
899
900 // Test & branch (immediate)
901 #define INSN(NAME, opcode) \
902 void NAME(Register Rt, int bitpos, address dest) { \
903 long offset = (dest - pc()) >> 2; \
904 int b5 = bitpos >> 5; \
905 bitpos &= 0x1f; \
906 starti; \
907 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
908 rf(Rt, 0); \
909 } \
910 void NAME(Register Rt, int bitpos, Label &L) { \
911 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
912 }
913
914 INSN(tbz, 0b0110110);
915 INSN(tbnz, 0b0110111);
916
917 #undef INSN
918
919 // Conditional branch (immediate)
920 enum Condition
921 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
922
923 void br(Condition cond, address dest) {
924 long offset = (dest - pc()) >> 2;
925 starti;
926 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
927 }
928
929 #define INSN(NAME, cond) \
930 void NAME(address dest) { \
931 br(cond, dest); \
932 }
933
934 INSN(beq, EQ);
935 INSN(bne, NE);
936 INSN(bhs, HS);
937 INSN(bcs, CS);
938 INSN(blo, LO);
939 INSN(bcc, CC);
940 INSN(bmi, MI);
941 INSN(bpl, PL);
942 INSN(bvs, VS);
943 INSN(bvc, VC);
944 INSN(bhi, HI);
945 INSN(bls, LS);
946 INSN(bge, GE);
947 INSN(blt, LT);
948 INSN(bgt, GT);
949 INSN(ble, LE);
950 INSN(bal, AL);
951 INSN(bnv, NV);
952
953 void br(Condition cc, Label &L);
954
955 #undef INSN
956
957 // Exception generation
958 void generate_exception(int opc, int op2, int LL, unsigned imm) {
959 starti;
960 f(0b11010100, 31, 24);
961 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
962 }
963
964 #define INSN(NAME, opc, op2, LL) \
965 void NAME(unsigned imm) { \
966 generate_exception(opc, op2, LL, imm); \
967 }
968
969 INSN(svc, 0b000, 0, 0b01);
970 INSN(hvc, 0b000, 0, 0b10);
971 INSN(smc, 0b000, 0, 0b11);
972 INSN(brk, 0b001, 0, 0b00);
973 INSN(hlt, 0b010, 0, 0b00);
974 INSN(dpcs1, 0b101, 0, 0b01);
975 INSN(dpcs2, 0b101, 0, 0b10);
976 INSN(dpcs3, 0b101, 0, 0b11);
977
978 #undef INSN
979
980 // System
981 void system(int op0, int op1, int CRn, int CRm, int op2,
982 Register rt = dummy_reg)
983 {
984 starti;
985 f(0b11010101000, 31, 21);
986 f(op0, 20, 19);
987 f(op1, 18, 16);
988 f(CRn, 15, 12);
989 f(CRm, 11, 8);
990 f(op2, 7, 5);
991 rf(rt, 0);
992 }
993
994 void hint(int imm) {
995 system(0b00, 0b011, 0b0010, 0b0000, imm);
996 }
997
998 void nop() {
999 hint(0);
1000 }
1001
1002 void yield() {
1003 hint(1);
1004 }
1005
1006 void wfe() {
1007 hint(2);
1008 }
1009
1010 void wfi() {
1011 hint(3);
1012 }
1013
1014 void sev() {
1015 hint(4);
1016 }
1017
1018 void sevl() {
1019 hint(5);
1020 }
1021
1022 // we only provide mrs and msr for the special purpose system
1023 // registers where op1 (instr[20:19]) == 11 and, (currently) only
1024 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1025
1026 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1027 starti;
1028 f(0b1101010100011, 31, 19);
1029 f(op1, 18, 16);
1030 f(CRn, 15, 12);
1031 f(CRm, 11, 8);
1032 f(op2, 7, 5);
1033 // writing zr is ok
1034 zrf(rt, 0);
1035 }
1036
1037 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1038 starti;
1039 f(0b1101010100111, 31, 19);
1040 f(op1, 18, 16);
1041 f(CRn, 15, 12);
1042 f(CRm, 11, 8);
1043 f(op2, 7, 5);
1044 // reading to zr is a mistake
1045 rf(rt, 0);
1046 }
1047
1048 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1049 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1050
1051 void dsb(barrier imm) {
1052 system(0b00, 0b011, 0b00011, imm, 0b100);
1053 }
1054
1055 void dmb(barrier imm) {
1056 system(0b00, 0b011, 0b00011, imm, 0b101);
1057 }
1058
1059 void isb() {
1060 system(0b00, 0b011, 0b00011, SY, 0b110);
1061 }
1062
1063 void sys(int op1, int CRn, int CRm, int op2,
1064 Register rt = (Register)0b11111) {
1065 system(0b01, op1, CRn, CRm, op2, rt);
1066 }
1067
1068 // Only implement operations accessible from EL0 or higher, i.e.,
1069 // op1 CRn CRm op2
1070 // IC IVAU 3 7 5 1
1071 // DC CVAC 3 7 10 1
1072 // DC CVAU 3 7 11 1
1073 // DC CIVAC 3 7 14 1
1074 // DC ZVA 3 7 4 1
1075 // So only deal with the CRm field.
1076 enum icache_maintenance {IVAU = 0b0101};
1077 enum dcache_maintenance {CVAC = 0b1010, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1078
1079 void dc(dcache_maintenance cm, Register Rt) {
1080 sys(0b011, 0b0111, cm, 0b001, Rt);
1081 }
1082
1083 void ic(icache_maintenance cm, Register Rt) {
1084 sys(0b011, 0b0111, cm, 0b001, Rt);
1085 }
1086
1087 // A more convenient access to dmb for our purposes
1088 enum Membar_mask_bits {
1089 // We can use ISH for a barrier because the ARM ARM says "This
1090 // architecture assumes that all Processing Elements that use the
1091 // same operating system or hypervisor are in the same Inner
1092 // Shareable shareability domain."
1093 StoreStore = ISHST,
1094 LoadStore = ISHLD,
1095 LoadLoad = ISHLD,
1096 StoreLoad = ISH,
1097 AnyAny = ISH
1098 };
1099
1100 void membar(Membar_mask_bits order_constraint) {
1101 dmb(Assembler::barrier(order_constraint));
1102 }
1103
1104 // Unconditional branch (register)
1105 void branch_reg(Register R, int opc) {
1106 starti;
1107 f(0b1101011, 31, 25);
1108 f(opc, 24, 21);
1109 f(0b11111000000, 20, 10);
1110 rf(R, 5);
1111 f(0b00000, 4, 0);
1112 }
1113
1114 #define INSN(NAME, opc) \
1115 void NAME(Register R) { \
1116 branch_reg(R, opc); \
1117 }
1118
1119 INSN(br, 0b0000);
1120 INSN(blr, 0b0001);
1121 INSN(ret, 0b0010);
1122
1123 void ret(void *p); // This forces a compile-time error for ret(0)
1124
1125 #undef INSN
1126
1127 #define INSN(NAME, opc) \
1128 void NAME() { \
1129 branch_reg(dummy_reg, opc); \
1130 }
1131
1132 INSN(eret, 0b0100);
1133 INSN(drps, 0b0101);
1134
1135 #undef INSN
1136
1137 // Load/store exclusive
1138 enum operand_size { byte, halfword, word, xword };
1139
1140 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1141 Register Rn, enum operand_size sz, int op, bool ordered) {
1142 starti;
1143 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1144 rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0);
1145 }
1146
1147 void load_exclusive(Register dst, Register addr,
1148 enum operand_size sz, bool ordered) {
1149 load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1150 sz, 0b010, ordered);
1151 }
1152
1153 void store_exclusive(Register status, Register new_val, Register addr,
1154 enum operand_size sz, bool ordered) {
1155 load_store_exclusive(status, new_val, dummy_reg, addr,
1156 sz, 0b000, ordered);
1157 }
1158
1159 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1160 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1161 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1162 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1163 }
1164
1165 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1166 void NAME(Register Rs, Register Rt, Register Rn) { \
1167 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1168 load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1169 }
1170
1171 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1172 void NAME(Register Rt, Register Rn) { \
1173 load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1174 Rn, sz, op, o0); \
1175 }
1176
1177 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1178 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1179 guarantee(Rt1 != Rt2, "unpredictable instruction"); \
1180 load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \
1181 }
1182
1183 // bytes
1184 INSN3(stxrb, byte, 0b000, 0);
1185 INSN3(stlxrb, byte, 0b000, 1);
1186 INSN2(ldxrb, byte, 0b010, 0);
1187 INSN2(ldaxrb, byte, 0b010, 1);
1188 INSN2(stlrb, byte, 0b100, 1);
1189 INSN2(ldarb, byte, 0b110, 1);
1190
1191 // halfwords
1192 INSN3(stxrh, halfword, 0b000, 0);
1193 INSN3(stlxrh, halfword, 0b000, 1);
1194 INSN2(ldxrh, halfword, 0b010, 0);
1195 INSN2(ldaxrh, halfword, 0b010, 1);
1196 INSN2(stlrh, halfword, 0b100, 1);
1197 INSN2(ldarh, halfword, 0b110, 1);
1198
1199 // words
1200 INSN3(stxrw, word, 0b000, 0);
1201 INSN3(stlxrw, word, 0b000, 1);
1202 INSN4(stxpw, word, 0b001, 0);
1203 INSN4(stlxpw, word, 0b001, 1);
1204 INSN2(ldxrw, word, 0b010, 0);
1205 INSN2(ldaxrw, word, 0b010, 1);
1206 INSN_FOO(ldxpw, word, 0b011, 0);
1207 INSN_FOO(ldaxpw, word, 0b011, 1);
1208 INSN2(stlrw, word, 0b100, 1);
1209 INSN2(ldarw, word, 0b110, 1);
1210
1211 // xwords
1212 INSN3(stxr, xword, 0b000, 0);
1213 INSN3(stlxr, xword, 0b000, 1);
1214 INSN4(stxp, xword, 0b001, 0);
1215 INSN4(stlxp, xword, 0b001, 1);
1216 INSN2(ldxr, xword, 0b010, 0);
1217 INSN2(ldaxr, xword, 0b010, 1);
1218 INSN_FOO(ldxp, xword, 0b011, 0);
1219 INSN_FOO(ldaxp, xword, 0b011, 1);
1220 INSN2(stlr, xword, 0b100, 1);
1221 INSN2(ldar, xword, 0b110, 1);
1222
1223 #undef INSN2
1224 #undef INSN3
1225 #undef INSN4
1226 #undef INSN_FOO
1227
1228 // 8.1 Compare and swap extensions
1229 void lse_cas(Register Rs, Register Rt, Register Rn,
1230 enum operand_size sz, bool a, bool r, bool not_pair) {
1231 starti;
1232 if (! not_pair) { // Pair
1233 assert(sz == word || sz == xword, "invalid size");
1234 /* The size bit is in bit 30, not 31 */
1235 sz = (operand_size)(sz == word ? 0b00:0b01);
1236 }
1237 f(sz, 31, 30), f(0b001000, 29, 24), f(1, 23), f(a, 22), f(1, 21);
1238 rf(Rs, 16), f(r, 15), f(0b11111, 14, 10), rf(Rn, 5), rf(Rt, 0);
1239 }
1240
1241 // CAS
1242 #define INSN(NAME, a, r) \
1243 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1244 assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
1245 lse_cas(Rs, Rt, Rn, sz, a, r, true); \
1246 }
1247 INSN(cas, false, false)
1248 INSN(casa, true, false)
1249 INSN(casl, false, true)
1250 INSN(casal, true, true)
1251 #undef INSN
1252
1253 // CASP
1254 #define INSN(NAME, a, r) \
1255 void NAME(operand_size sz, Register Rs, Register Rs1, \
1256 Register Rt, Register Rt1, Register Rn) { \
1257 assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 && \
1258 Rs->successor() == Rs1 && Rt->successor() == Rt1 && \
1259 Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \
1260 lse_cas(Rs, Rt, Rn, sz, a, r, false); \
1261 }
1262 INSN(casp, false, false)
1263 INSN(caspa, true, false)
1264 INSN(caspl, false, true)
1265 INSN(caspal, true, true)
1266 #undef INSN
1267
1268 // 8.1 Atomic operations
1269 void lse_atomic(Register Rs, Register Rt, Register Rn,
1270 enum operand_size sz, int op1, int op2, bool a, bool r) {
1271 starti;
1272 f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1273 rf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), rf(Rn, 5), zrf(Rt, 0);
1274 }
1275
1276 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \
1277 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1278 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false); \
1279 } \
1280 void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1281 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false); \
1282 } \
1283 void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1284 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true); \
1285 } \
1286 void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1287 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true); \
1288 }
1289 INSN(ldadd, ldadda, ldaddl, ldaddal, 0, 0b000);
1290 INSN(ldbic, ldbica, ldbicl, ldbical, 0, 0b001);
1291 INSN(ldeor, ldeora, ldeorl, ldeoral, 0, 0b010);
1292 INSN(ldorr, ldorra, ldorrl, ldorral, 0, 0b011);
1293 INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1294 INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1295 INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1296 INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1297 INSN(swp, swpa, swpl, swpal, 1, 0b000);
1298 #undef INSN
1299
1300 // Load register (literal)
1301 #define INSN(NAME, opc, V) \
1302 void NAME(Register Rt, address dest) { \
1303 long offset = (dest - pc()) >> 2; \
1304 starti; \
1305 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1306 sf(offset, 23, 5); \
1307 rf(Rt, 0); \
1308 } \
1309 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1310 InstructionMark im(this); \
1311 guarantee(rtype == relocInfo::internal_word_type, \
1312 "only internal_word_type relocs make sense here"); \
1313 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1314 NAME(Rt, dest); \
1315 } \
1316 void NAME(Register Rt, Label &L) { \
1317 wrap_label(Rt, L, &Assembler::NAME); \
1318 }
1319
1320 INSN(ldrw, 0b00, 0);
1321 INSN(ldr, 0b01, 0);
1322 INSN(ldrsw, 0b10, 0);
1323
1324 #undef INSN
1325
1326 #define INSN(NAME, opc, V) \
1327 void NAME(FloatRegister Rt, address dest) { \
1328 long offset = (dest - pc()) >> 2; \
1329 starti; \
1330 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1331 sf(offset, 23, 5); \
1332 rf((Register)Rt, 0); \
1333 }
1334
1335 INSN(ldrs, 0b00, 1);
1336 INSN(ldrd, 0b01, 1);
1337 INSN(ldrq, 0b10, 1);
1338
1339 #undef INSN
1340
1341 #define INSN(NAME, opc, V) \
1342 void NAME(address dest, prfop op = PLDL1KEEP) { \
1343 long offset = (dest - pc()) >> 2; \
1344 starti; \
1345 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1346 sf(offset, 23, 5); \
1347 f(op, 4, 0); \
1348 } \
1349 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1350 wrap_label(L, op, &Assembler::NAME); \
1351 }
1352
1353 INSN(prfm, 0b11, 0);
1354
1355 #undef INSN
1356
1357 // Load/store
1358 void ld_st1(int opc, int p1, int V, int L,
1359 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1360 starti;
1361 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1362 zrf(Rt2, 10), zrf(Rt1, 0);
1363 if (no_allocate) {
1364 adr.encode_nontemporal_pair(current);
1365 } else {
1366 adr.encode_pair(current);
1367 }
1368 }
1369
1370 // Load/store register pair (offset)
1371 #define INSN(NAME, size, p1, V, L, no_allocate) \
1372 void NAME(Register Rt1, Register Rt2, Address adr) { \
1373 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1374 }
1375
1376 INSN(stpw, 0b00, 0b101, 0, 0, false);
1377 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1378 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1379 INSN(stp, 0b10, 0b101, 0, 0, false);
1380 INSN(ldp, 0b10, 0b101, 0, 1, false);
1381
1382 // Load/store no-allocate pair (offset)
1383 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1384 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1385 INSN(stnp, 0b10, 0b101, 0, 0, true);
1386 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1387
1388 #undef INSN
1389
1390 #define INSN(NAME, size, p1, V, L, no_allocate) \
1391 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1392 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1393 }
1394
1395 INSN(stps, 0b00, 0b101, 1, 0, false);
1396 INSN(ldps, 0b00, 0b101, 1, 1, false);
1397 INSN(stpd, 0b01, 0b101, 1, 0, false);
1398 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1399 INSN(stpq, 0b10, 0b101, 1, 0, false);
1400 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1401
1402 #undef INSN
1403
1404 // Load/store register (all modes)
1405 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1406 starti;
1407
1408 f(V, 26); // general reg?
1409 zrf(Rt, 0);
1410
1411 // Encoding for literal loads is done here (rather than pushed
1412 // down into Address::encode) because the encoding of this
1413 // instruction is too different from all of the other forms to
1414 // make it worth sharing.
1415 if (adr.getMode() == Address::literal) {
1416 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1417 assert(op == 0b01, "literal form can only be used with loads");
1418 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1419 long offset = (adr.target() - pc()) >> 2;
1420 sf(offset, 23, 5);
1421 code_section()->relocate(pc(), adr.rspec());
1422 return;
1423 }
1424
1425 f(size, 31, 30);
1426 f(op, 23, 22); // str
1427 adr.encode(current);
1428 }
1429
1430 #define INSN(NAME, size, op) \
1431 void NAME(Register Rt, const Address &adr) { \
1432 ld_st2(Rt, adr, size, op); \
1433 } \
1434
1435 INSN(str, 0b11, 0b00);
1436 INSN(strw, 0b10, 0b00);
1437 INSN(strb, 0b00, 0b00);
1438 INSN(strh, 0b01, 0b00);
1439
1440 INSN(ldr, 0b11, 0b01);
1441 INSN(ldrw, 0b10, 0b01);
1442 INSN(ldrb, 0b00, 0b01);
1443 INSN(ldrh, 0b01, 0b01);
1444
1445 INSN(ldrsb, 0b00, 0b10);
1446 INSN(ldrsbw, 0b00, 0b11);
1447 INSN(ldrsh, 0b01, 0b10);
1448 INSN(ldrshw, 0b01, 0b11);
1449 INSN(ldrsw, 0b10, 0b10);
1450
1451 #undef INSN
1452
1453 #define INSN(NAME, size, op) \
1454 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1455 ld_st2((Register)pfop, adr, size, op); \
1456 }
1457
1458 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1459 // writeback modes, but the assembler
1460 // doesn't enfore that.
1461
1462 #undef INSN
1463
1464 #define INSN(NAME, size, op) \
1465 void NAME(FloatRegister Rt, const Address &adr) { \
1466 ld_st2((Register)Rt, adr, size, op, 1); \
1467 }
1468
1469 INSN(strd, 0b11, 0b00);
1470 INSN(strs, 0b10, 0b00);
1471 INSN(ldrd, 0b11, 0b01);
1472 INSN(ldrs, 0b10, 0b01);
1473 INSN(strq, 0b00, 0b10);
1474 INSN(ldrq, 0x00, 0b11);
1475
1476 #undef INSN
1477
1478 enum shift_kind { LSL, LSR, ASR, ROR };
1479
1480 void op_shifted_reg(unsigned decode,
1481 enum shift_kind kind, unsigned shift,
1482 unsigned size, unsigned op) {
1483 f(size, 31);
1484 f(op, 30, 29);
1485 f(decode, 28, 24);
1486 f(shift, 15, 10);
1487 f(kind, 23, 22);
1488 }
1489
1490 // Logical (shifted register)
1491 #define INSN(NAME, size, op, N) \
1492 void NAME(Register Rd, Register Rn, Register Rm, \
1493 enum shift_kind kind = LSL, unsigned shift = 0) { \
1494 starti; \
1495 f(N, 21); \
1496 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1497 op_shifted_reg(0b01010, kind, shift, size, op); \
1498 }
1499
1500 INSN(andr, 1, 0b00, 0);
1501 INSN(orr, 1, 0b01, 0);
1502 INSN(eor, 1, 0b10, 0);
1503 INSN(ands, 1, 0b11, 0);
1504 INSN(andw, 0, 0b00, 0);
1505 INSN(orrw, 0, 0b01, 0);
1506 INSN(eorw, 0, 0b10, 0);
1507 INSN(andsw, 0, 0b11, 0);
1508
1509 INSN(bic, 1, 0b00, 1);
1510 INSN(orn, 1, 0b01, 1);
1511 INSN(eon, 1, 0b10, 1);
1512 INSN(bics, 1, 0b11, 1);
1513 INSN(bicw, 0, 0b00, 1);
1514 INSN(ornw, 0, 0b01, 1);
1515 INSN(eonw, 0, 0b10, 1);
1516 INSN(bicsw, 0, 0b11, 1);
1517
1518 #undef INSN
1519
1520 // Aliases for short forms of orn
1521 void mvn(Register Rd, Register Rm,
1522 enum shift_kind kind = LSL, unsigned shift = 0) {
1523 orn(Rd, zr, Rm, kind, shift);
1524 }
1525
1526 void mvnw(Register Rd, Register Rm,
1527 enum shift_kind kind = LSL, unsigned shift = 0) {
1528 ornw(Rd, zr, Rm, kind, shift);
1529 }
1530
1531 // Add/subtract (shifted register)
1532 #define INSN(NAME, size, op) \
1533 void NAME(Register Rd, Register Rn, Register Rm, \
1534 enum shift_kind kind, unsigned shift = 0) { \
1535 starti; \
1536 f(0, 21); \
1537 assert_cond(kind != ROR); \
1538 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1539 op_shifted_reg(0b01011, kind, shift, size, op); \
1540 }
1541
1542 INSN(add, 1, 0b000);
1543 INSN(sub, 1, 0b10);
1544 INSN(addw, 0, 0b000);
1545 INSN(subw, 0, 0b10);
1546
1547 INSN(adds, 1, 0b001);
1548 INSN(subs, 1, 0b11);
1549 INSN(addsw, 0, 0b001);
1550 INSN(subsw, 0, 0b11);
1551
1552 #undef INSN
1553
1554 // Add/subtract (extended register)
1555 #define INSN(NAME, op) \
1556 void NAME(Register Rd, Register Rn, Register Rm, \
1557 ext::operation option, int amount = 0) { \
1558 starti; \
1559 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1560 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1561 }
1562
1563 void add_sub_extended_reg(unsigned op, unsigned decode,
1564 Register Rd, Register Rn, Register Rm,
1565 unsigned opt, ext::operation option, unsigned imm) {
1566 guarantee(imm <= 4, "shift amount must be < 4");
1567 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1568 f(option, 15, 13), f(imm, 12, 10);
1569 }
1570
1571 INSN(addw, 0b000);
1572 INSN(subw, 0b010);
1573 INSN(add, 0b100);
1574 INSN(sub, 0b110);
1575
1576 #undef INSN
1577
1578 #define INSN(NAME, op) \
1579 void NAME(Register Rd, Register Rn, Register Rm, \
1580 ext::operation option, int amount = 0) { \
1581 starti; \
1582 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1583 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1584 }
1585
1586 INSN(addsw, 0b001);
1587 INSN(subsw, 0b011);
1588 INSN(adds, 0b101);
1589 INSN(subs, 0b111);
1590
1591 #undef INSN
1592
1593 // Aliases for short forms of add and sub
1594 #define INSN(NAME) \
1595 void NAME(Register Rd, Register Rn, Register Rm) { \
1596 if (Rd == sp || Rn == sp) \
1597 NAME(Rd, Rn, Rm, ext::uxtx); \
1598 else \
1599 NAME(Rd, Rn, Rm, LSL); \
1600 }
1601
1602 INSN(addw);
1603 INSN(subw);
1604 INSN(add);
1605 INSN(sub);
1606
1607 INSN(addsw);
1608 INSN(subsw);
1609 INSN(adds);
1610 INSN(subs);
1611
1612 #undef INSN
1613
1614 // Add/subtract (with carry)
1615 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1616 starti;
1617 f(op, 31, 29);
1618 f(0b11010000, 28, 21);
1619 f(0b000000, 15, 10);
1620 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1621 }
1622
1623 #define INSN(NAME, op) \
1624 void NAME(Register Rd, Register Rn, Register Rm) { \
1625 add_sub_carry(op, Rd, Rn, Rm); \
1626 }
1627
1628 INSN(adcw, 0b000);
1629 INSN(adcsw, 0b001);
1630 INSN(sbcw, 0b010);
1631 INSN(sbcsw, 0b011);
1632 INSN(adc, 0b100);
1633 INSN(adcs, 0b101);
1634 INSN(sbc,0b110);
1635 INSN(sbcs, 0b111);
1636
1637 #undef INSN
1638
1639 // Conditional compare (both kinds)
1640 void conditional_compare(unsigned op, int o1, int o2, int o3,
1641 Register Rn, unsigned imm5, unsigned nzcv,
1642 unsigned cond) {
1643 starti;
1644 f(op, 31, 29);
1645 f(0b11010010, 28, 21);
1646 f(cond, 15, 12);
1647 f(o1, 11);
1648 f(o2, 10);
1649 f(o3, 4);
1650 f(nzcv, 3, 0);
1651 f(imm5, 20, 16), rf(Rn, 5);
1652 }
1653
1654 #define INSN(NAME, op) \
1655 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1656 int regNumber = (Rm == zr ? 31 : (uintptr_t)Rm); \
1657 conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond); \
1658 } \
1659 \
1660 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1661 conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond); \
1662 }
1663
1664 INSN(ccmnw, 0b001);
1665 INSN(ccmpw, 0b011);
1666 INSN(ccmn, 0b101);
1667 INSN(ccmp, 0b111);
1668
1669 #undef INSN
1670
1671 // Conditional select
1672 void conditional_select(unsigned op, unsigned op2,
1673 Register Rd, Register Rn, Register Rm,
1674 unsigned cond) {
1675 starti;
1676 f(op, 31, 29);
1677 f(0b11010100, 28, 21);
1678 f(cond, 15, 12);
1679 f(op2, 11, 10);
1680 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1681 }
1682
1683 #define INSN(NAME, op, op2) \
1684 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1685 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1686 }
1687
1688 INSN(cselw, 0b000, 0b00);
1689 INSN(csincw, 0b000, 0b01);
1690 INSN(csinvw, 0b010, 0b00);
1691 INSN(csnegw, 0b010, 0b01);
1692 INSN(csel, 0b100, 0b00);
1693 INSN(csinc, 0b100, 0b01);
1694 INSN(csinv, 0b110, 0b00);
1695 INSN(csneg, 0b110, 0b01);
1696
1697 #undef INSN
1698
1699 // Data processing
1700 void data_processing(unsigned op29, unsigned opcode,
1701 Register Rd, Register Rn) {
1702 f(op29, 31, 29), f(0b11010110, 28, 21);
1703 f(opcode, 15, 10);
1704 rf(Rn, 5), rf(Rd, 0);
1705 }
1706
1707 // (1 source)
1708 #define INSN(NAME, op29, opcode2, opcode) \
1709 void NAME(Register Rd, Register Rn) { \
1710 starti; \
1711 f(opcode2, 20, 16); \
1712 data_processing(op29, opcode, Rd, Rn); \
1713 }
1714
1715 INSN(rbitw, 0b010, 0b00000, 0b00000);
1716 INSN(rev16w, 0b010, 0b00000, 0b00001);
1717 INSN(revw, 0b010, 0b00000, 0b00010);
1718 INSN(clzw, 0b010, 0b00000, 0b00100);
1719 INSN(clsw, 0b010, 0b00000, 0b00101);
1720
1721 INSN(rbit, 0b110, 0b00000, 0b00000);
1722 INSN(rev16, 0b110, 0b00000, 0b00001);
1723 INSN(rev32, 0b110, 0b00000, 0b00010);
1724 INSN(rev, 0b110, 0b00000, 0b00011);
1725 INSN(clz, 0b110, 0b00000, 0b00100);
1726 INSN(cls, 0b110, 0b00000, 0b00101);
1727
1728 #undef INSN
1729
1730 // (2 sources)
1731 #define INSN(NAME, op29, opcode) \
1732 void NAME(Register Rd, Register Rn, Register Rm) { \
1733 starti; \
1734 rf(Rm, 16); \
1735 data_processing(op29, opcode, Rd, Rn); \
1736 }
1737
1738 INSN(udivw, 0b000, 0b000010);
1739 INSN(sdivw, 0b000, 0b000011);
1740 INSN(lslvw, 0b000, 0b001000);
1741 INSN(lsrvw, 0b000, 0b001001);
1742 INSN(asrvw, 0b000, 0b001010);
1743 INSN(rorvw, 0b000, 0b001011);
1744
1745 INSN(udiv, 0b100, 0b000010);
1746 INSN(sdiv, 0b100, 0b000011);
1747 INSN(lslv, 0b100, 0b001000);
1748 INSN(lsrv, 0b100, 0b001001);
1749 INSN(asrv, 0b100, 0b001010);
1750 INSN(rorv, 0b100, 0b001011);
1751
1752 #undef INSN
1753
1754 // (3 sources)
1755 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1756 Register Rd, Register Rn, Register Rm,
1757 Register Ra) {
1758 starti;
1759 f(op54, 31, 29), f(0b11011, 28, 24);
1760 f(op31, 23, 21), f(o0, 15);
1761 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1762 }
1763
1764 #define INSN(NAME, op54, op31, o0) \
1765 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1766 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1767 }
1768
1769 INSN(maddw, 0b000, 0b000, 0);
1770 INSN(msubw, 0b000, 0b000, 1);
1771 INSN(madd, 0b100, 0b000, 0);
1772 INSN(msub, 0b100, 0b000, 1);
1773 INSN(smaddl, 0b100, 0b001, 0);
1774 INSN(smsubl, 0b100, 0b001, 1);
1775 INSN(umaddl, 0b100, 0b101, 0);
1776 INSN(umsubl, 0b100, 0b101, 1);
1777
1778 #undef INSN
1779
1780 #define INSN(NAME, op54, op31, o0) \
1781 void NAME(Register Rd, Register Rn, Register Rm) { \
1782 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1783 }
1784
1785 INSN(smulh, 0b100, 0b010, 0);
1786 INSN(umulh, 0b100, 0b110, 0);
1787
1788 #undef INSN
1789
1790 // Floating-point data-processing (1 source)
1791 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1792 FloatRegister Vd, FloatRegister Vn) {
1793 starti;
1794 f(op31, 31, 29);
1795 f(0b11110, 28, 24);
1796 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1797 rf(Vn, 5), rf(Vd, 0);
1798 }
1799
1800 #define INSN(NAME, op31, type, opcode) \
1801 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1802 data_processing(op31, type, opcode, Vd, Vn); \
1803 }
1804
1805 private:
1806 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1807 public:
1808 INSN(fabss, 0b000, 0b00, 0b000001);
1809 INSN(fnegs, 0b000, 0b00, 0b000010);
1810 INSN(fsqrts, 0b000, 0b00, 0b000011);
1811 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1812
1813 private:
1814 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1815 public:
1816 INSN(fabsd, 0b000, 0b01, 0b000001);
1817 INSN(fnegd, 0b000, 0b01, 0b000010);
1818 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1819 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1820
1821 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1822 assert(Vd != Vn, "should be");
1823 i_fmovd(Vd, Vn);
1824 }
1825
1826 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1827 assert(Vd != Vn, "should be");
1828 i_fmovs(Vd, Vn);
1829 }
1830
1831 #undef INSN
1832
1833 // Floating-point data-processing (2 source)
1834 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1835 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1836 starti;
1837 f(op31, 31, 29);
1838 f(0b11110, 28, 24);
1839 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1840 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1841 }
1842
1843 #define INSN(NAME, op31, type, opcode) \
1844 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1845 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1846 }
1847
1848 INSN(fmuls, 0b000, 0b00, 0b0000);
1849 INSN(fdivs, 0b000, 0b00, 0b0001);
1850 INSN(fadds, 0b000, 0b00, 0b0010);
1851 INSN(fsubs, 0b000, 0b00, 0b0011);
1852 INSN(fnmuls, 0b000, 0b00, 0b1000);
1853
1854 INSN(fmuld, 0b000, 0b01, 0b0000);
1855 INSN(fdivd, 0b000, 0b01, 0b0001);
1856 INSN(faddd, 0b000, 0b01, 0b0010);
1857 INSN(fsubd, 0b000, 0b01, 0b0011);
1858 INSN(fnmuld, 0b000, 0b01, 0b1000);
1859
1860 #undef INSN
1861
1862 // Floating-point data-processing (3 source)
1863 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1864 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1865 FloatRegister Va) {
1866 starti;
1867 f(op31, 31, 29);
1868 f(0b11111, 28, 24);
1869 f(type, 23, 22), f(o1, 21), f(o0, 15);
1870 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1871 }
1872
1873 #define INSN(NAME, op31, type, o1, o0) \
1874 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1875 FloatRegister Va) { \
1876 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1877 }
1878
1879 INSN(fmadds, 0b000, 0b00, 0, 0);
1880 INSN(fmsubs, 0b000, 0b00, 0, 1);
1881 INSN(fnmadds, 0b000, 0b00, 1, 0);
1882 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1883
1884 INSN(fmaddd, 0b000, 0b01, 0, 0);
1885 INSN(fmsubd, 0b000, 0b01, 0, 1);
1886 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1887 INSN(fnmsub, 0b000, 0b01, 1, 1);
1888
1889 #undef INSN
1890
1891 // Floating-point conditional select
1892 void fp_conditional_select(unsigned op31, unsigned type,
1893 unsigned op1, unsigned op2,
1894 Condition cond, FloatRegister Vd,
1895 FloatRegister Vn, FloatRegister Vm) {
1896 starti;
1897 f(op31, 31, 29);
1898 f(0b11110, 28, 24);
1899 f(type, 23, 22);
1900 f(op1, 21, 21);
1901 f(op2, 11, 10);
1902 f(cond, 15, 12);
1903 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1904 }
1905
1906 #define INSN(NAME, op31, type, op1, op2) \
1907 void NAME(FloatRegister Vd, FloatRegister Vn, \
1908 FloatRegister Vm, Condition cond) { \
1909 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1910 }
1911
1912 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1913 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1914
1915 #undef INSN
1916
1917 // Floating-point<->integer conversions
1918 void float_int_convert(unsigned op31, unsigned type,
1919 unsigned rmode, unsigned opcode,
1920 Register Rd, Register Rn) {
1921 starti;
1922 f(op31, 31, 29);
1923 f(0b11110, 28, 24);
1924 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1925 f(opcode, 18, 16), f(0b000000, 15, 10);
1926 zrf(Rn, 5), zrf(Rd, 0);
1927 }
1928
1929 #define INSN(NAME, op31, type, rmode, opcode) \
1930 void NAME(Register Rd, FloatRegister Vn) { \
1931 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
1932 }
1933
1934 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1935 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
1936 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1937 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
1938
1939 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1940 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1941
1942 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1943
1944 #undef INSN
1945
1946 #define INSN(NAME, op31, type, rmode, opcode) \
1947 void NAME(FloatRegister Vd, Register Rn) { \
1948 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
1949 }
1950
1951 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1952 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1953
1954 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1955 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
1956 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1957 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
1958
1959 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1960
1961 #undef INSN
1962
1963 // Floating-point compare
1964 void float_compare(unsigned op31, unsigned type,
1965 unsigned op, unsigned op2,
1966 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1967 starti;
1968 f(op31, 31, 29);
1969 f(0b11110, 28, 24);
1970 f(type, 23, 22), f(1, 21);
1971 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1972 rf(Vn, 5), rf(Vm, 16);
1973 }
1974
1975
1976 #define INSN(NAME, op31, type, op, op2) \
1977 void NAME(FloatRegister Vn, FloatRegister Vm) { \
1978 float_compare(op31, type, op, op2, Vn, Vm); \
1979 }
1980
1981 #define INSN1(NAME, op31, type, op, op2) \
1982 void NAME(FloatRegister Vn, double d) { \
1983 assert_cond(d == 0.0); \
1984 float_compare(op31, type, op, op2, Vn); \
1985 }
1986
1987 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
1988 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
1989 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
1990 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
1991
1992 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
1993 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
1994 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
1995 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
1996
1997 #undef INSN
1998 #undef INSN1
1999
2000 // Floating-point Move (immediate)
2001 private:
2002 unsigned pack(double value);
2003
2004 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
2005 starti;
2006 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2007 f(pack(value), 20, 13), f(0b10000000, 12, 5);
2008 rf(Vn, 0);
2009 }
2010
2011 public:
2012
2013 void fmovs(FloatRegister Vn, double value) {
2014 if (value)
2015 fmov_imm(Vn, value, 0b00);
2016 else
2017 fmovs(Vn, zr);
2018 }
2019 void fmovd(FloatRegister Vn, double value) {
2020 if (value)
2021 fmov_imm(Vn, value, 0b01);
2022 else
2023 fmovd(Vn, zr);
2024 }
2025
2026 // Floating-point rounding
2027 // type: half-precision = 11
2028 // single = 00
2029 // double = 01
2030 // rmode: A = Away = 100
2031 // I = current = 111
2032 // M = MinusInf = 010
2033 // N = eveN = 000
2034 // P = PlusInf = 001
2035 // X = eXact = 110
2036 // Z = Zero = 011
2037 void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) {
2038 starti;
2039 f(0b00011110, 31, 24);
2040 f(type, 23, 22);
2041 f(0b1001, 21, 18);
2042 f(rmode, 17, 15);
2043 f(0b10000, 14, 10);
2044 rf(Rn, 5), rf(Rd, 0);
2045 }
2046 #define INSN(NAME, type, rmode) \
2047 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2048 float_round(type, rmode, Vd, Vn); \
2049 }
2050
2051 public:
2052 INSN(frintah, 0b11, 0b100);
2053 INSN(frintih, 0b11, 0b111);
2054 INSN(frintmh, 0b11, 0b010);
2055 INSN(frintnh, 0b11, 0b000);
2056 INSN(frintph, 0b11, 0b001);
2057 INSN(frintxh, 0b11, 0b110);
2058 INSN(frintzh, 0b11, 0b011);
2059
2060 INSN(frintas, 0b00, 0b100);
2061 INSN(frintis, 0b00, 0b111);
2062 INSN(frintms, 0b00, 0b010);
2063 INSN(frintns, 0b00, 0b000);
2064 INSN(frintps, 0b00, 0b001);
2065 INSN(frintxs, 0b00, 0b110);
2066 INSN(frintzs, 0b00, 0b011);
2067
2068 INSN(frintad, 0b01, 0b100);
2069 INSN(frintid, 0b01, 0b111);
2070 INSN(frintmd, 0b01, 0b010);
2071 INSN(frintnd, 0b01, 0b000);
2072 INSN(frintpd, 0b01, 0b001);
2073 INSN(frintxd, 0b01, 0b110);
2074 INSN(frintzd, 0b01, 0b011);
2075 #undef INSN
2076
2077 /* SIMD extensions
2078 *
2079 * We just use FloatRegister in the following. They are exactly the same
2080 * as SIMD registers.
2081 */
2082 public:
2083
2084 enum SIMD_Arrangement {
2085 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
2086 };
2087
2088 enum SIMD_RegVariant {
2089 B, H, S, D, Q
2090 };
2091
2092 private:
2093 static short SIMD_Size_in_bytes[];
2094
2095 public:
2096 #define INSN(NAME, op) \
2097 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
2098 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2099 } \
2100
2101 INSN(ldr, 1);
2102 INSN(str, 0);
2103
2104 #undef INSN
2105
2106 private:
2107
2108 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2109 starti;
2110 f(0,31), f((int)T & 1, 30);
2111 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2112 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2113 }
2114 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2115 int imm, int op1, int op2, int regs) {
2116 guarantee(T <= T1Q && imm == SIMD_Size_in_bytes[T] * regs, "bad offset");
2117 starti;
2118 f(0,31), f((int)T & 1, 30);
2119 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2120 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2121 }
2122 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2123 Register Xm, int op1, int op2) {
2124 starti;
2125 f(0,31), f((int)T & 1, 30);
2126 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2127 f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2128 }
2129
2130 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
2131 switch (a.getMode()) {
2132 case Address::base_plus_offset:
2133 guarantee(a.offset() == 0, "no offset allowed here");
2134 ld_st(Vt, T, a.base(), op1, op2);
2135 break;
2136 case Address::post:
2137 ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
2138 break;
2139 case Address::post_reg:
2140 ld_st(Vt, T, a.base(), a.index(), op1, op2);
2141 break;
2142 default:
2143 ShouldNotReachHere();
2144 }
2145 }
2146
2147 public:
2148
2149 #define INSN1(NAME, op1, op2) \
2150 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
2151 ld_st(Vt, T, a, op1, op2, 1); \
2152 }
2153
2154 #define INSN2(NAME, op1, op2) \
2155 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2156 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
2157 ld_st(Vt, T, a, op1, op2, 2); \
2158 }
2159
2160 #define INSN3(NAME, op1, op2) \
2161 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2162 SIMD_Arrangement T, const Address &a) { \
2163 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
2164 "Registers must be ordered"); \
2165 ld_st(Vt, T, a, op1, op2, 3); \
2166 }
2167
2168 #define INSN4(NAME, op1, op2) \
2169 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
2170 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
2171 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
2172 Vt3->successor() == Vt4, "Registers must be ordered"); \
2173 ld_st(Vt, T, a, op1, op2, 4); \
2174 }
2175
2176 INSN1(ld1, 0b001100010, 0b0111);
2177 INSN2(ld1, 0b001100010, 0b1010);
2178 INSN3(ld1, 0b001100010, 0b0110);
2179 INSN4(ld1, 0b001100010, 0b0010);
2180
2181 INSN2(ld2, 0b001100010, 0b1000);
2182 INSN3(ld3, 0b001100010, 0b0100);
2183 INSN4(ld4, 0b001100010, 0b0000);
2184
2185 INSN1(st1, 0b001100000, 0b0111);
2186 INSN2(st1, 0b001100000, 0b1010);
2187 INSN3(st1, 0b001100000, 0b0110);
2188 INSN4(st1, 0b001100000, 0b0010);
2189
2190 INSN2(st2, 0b001100000, 0b1000);
2191 INSN3(st3, 0b001100000, 0b0100);
2192 INSN4(st4, 0b001100000, 0b0000);
2193
2194 INSN1(ld1r, 0b001101010, 0b1100);
2195 INSN2(ld2r, 0b001101011, 0b1100);
2196 INSN3(ld3r, 0b001101010, 0b1110);
2197 INSN4(ld4r, 0b001101011, 0b1110);
2198
2199 #undef INSN1
2200 #undef INSN2
2201 #undef INSN3
2202 #undef INSN4
2203
2204 #define INSN(NAME, opc) \
2205 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2206 starti; \
2207 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2208 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2209 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2210 }
2211
2212 INSN(eor, 0b101110001);
2213 INSN(orr, 0b001110101);
2214 INSN(andr, 0b001110001);
2215 INSN(bic, 0b001110011);
2216 INSN(bif, 0b101110111);
2217 INSN(bit, 0b101110101);
2218 INSN(bsl, 0b101110011);
2219 INSN(orn, 0b001110111);
2220
2221 #undef INSN
2222
2223 #define INSN(NAME, opc, opc2) \
2224 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2225 starti; \
2226 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2227 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2228 rf(Vn, 5), rf(Vd, 0); \
2229 }
2230
2231 INSN(addv, 0, 0b100001);
2232 INSN(subv, 1, 0b100001);
2233 INSN(mulv, 0, 0b100111);
2234 INSN(mlav, 0, 0b100101);
2235 INSN(mlsv, 1, 0b100101);
2236 INSN(sshl, 0, 0b010001);
2237 INSN(ushl, 1, 0b010001);
2238
2239 #undef INSN
2240
2241 #define INSN(NAME, opc, opc2) \
2242 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2243 starti; \
2244 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2245 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2246 rf(Vn, 5), rf(Vd, 0); \
2247 }
2248
2249 INSN(absr, 0, 0b100000101110);
2250 INSN(negr, 1, 0b100000101110);
2251 INSN(notr, 1, 0b100000010110);
2252 INSN(addv, 0, 0b110001101110);
2253 INSN(cls, 0, 0b100000010010);
2254 INSN(clz, 1, 0b100000010010);
2255 INSN(cnt, 0, 0b100000010110);
2256
2257 #undef INSN
2258
2259 #define INSN(NAME, op0, cmode0) \
2260 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2261 unsigned cmode = cmode0; \
2262 unsigned op = op0; \
2263 starti; \
2264 assert(lsl == 0 || \
2265 ((T == T4H || T == T8H) && lsl == 8) || \
2266 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
2267 cmode |= lsl >> 2; \
2268 if (T == T4H || T == T8H) cmode |= 0b1000; \
2269 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2270 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2271 cmode = 0b1110; \
2272 if (T == T1D || T == T2D) op = 1; \
2273 } \
2274 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2275 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2276 rf(Vd, 0); \
2277 }
2278
2279 INSN(movi, 0, 0);
2280 INSN(orri, 0, 1);
2281 INSN(mvni, 1, 0);
2282 INSN(bici, 1, 1);
2283
2284 #undef INSN
2285
2286 #define INSN(NAME, op1, op2, op3) \
2287 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2288 starti; \
2289 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2290 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2291 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2292 }
2293
2294 INSN(fadd, 0, 0, 0b110101);
2295 INSN(fdiv, 1, 0, 0b111111);
2296 INSN(fmul, 1, 0, 0b110111);
2297 INSN(fsub, 0, 1, 0b110101);
2298 INSN(fmla, 0, 0, 0b110011);
2299 INSN(fmls, 0, 1, 0b110011);
2300
2301 #undef INSN
2302
2303 #define INSN(NAME, opc) \
2304 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2305 starti; \
2306 assert(T == T4S, "arrangement must be T4S"); \
2307 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2308 }
2309
2310 INSN(sha1c, 0b000000);
2311 INSN(sha1m, 0b001000);
2312 INSN(sha1p, 0b000100);
2313 INSN(sha1su0, 0b001100);
2314 INSN(sha256h2, 0b010100);
2315 INSN(sha256h, 0b010000);
2316 INSN(sha256su1, 0b011000);
2317
2318 #undef INSN
2319
2320 #define INSN(NAME, opc) \
2321 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2322 starti; \
2323 assert(T == T4S, "arrangement must be T4S"); \
2324 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2325 }
2326
2327 INSN(sha1h, 0b000010);
2328 INSN(sha1su1, 0b000110);
2329 INSN(sha256su0, 0b001010);
2330
2331 #undef INSN
2332
2333 #define INSN(NAME, opc) \
2334 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2335 starti; \
2336 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2337 }
2338
2339 INSN(aese, 0b0100111000101000010010);
2340 INSN(aesd, 0b0100111000101000010110);
2341 INSN(aesmc, 0b0100111000101000011010);
2342 INSN(aesimc, 0b0100111000101000011110);
2343
2344 #undef INSN
2345
2346 #define INSN(NAME, op1, op2) \
2347 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2348 starti; \
2349 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2350 assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index"); \
2351 f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23); \
2352 f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16); \
2353 f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10); \
2354 rf(Vn, 5), rf(Vd, 0); \
2355 }
2356
2357 // FMLA/FMLS - Vector - Scalar
2358 INSN(fmlavs, 0, 0b0001);
2359 INSN(fmlsvs, 0, 0b0101);
2360 // FMULX - Vector - Scalar
2361 INSN(fmulxvs, 1, 0b1001);
2362
2363 #undef INSN
2364
2365 // Floating-point Reciprocal Estimate
2366 void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2367 assert(type == D || type == S, "Wrong type for frecpe");
2368 starti;
2369 f(0b010111101, 31, 23);
2370 f(type == D ? 1 : 0, 22);
2371 f(0b100001110110, 21, 10);
2372 rf(Vn, 5), rf(Vd, 0);
2373 }
2374
2375 // (double) {a, b} -> (a + b)
2376 void faddpd(FloatRegister Vd, FloatRegister Vn) {
2377 starti;
2378 f(0b0111111001110000110110, 31, 10);
2379 rf(Vn, 5), rf(Vd, 0);
2380 }
2381
2382 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2383 starti;
2384 assert(T != Q, "invalid register variant");
2385 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2386 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2387 }
2388
2389 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2390 starti;
2391 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2392 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2393 rf(Vn, 5), rf(Rd, 0);
2394 }
2395
2396 #define INSN(NAME, opc, opc2, isSHR) \
2397 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2398 starti; \
2399 /* The encodings for the immh:immb fields (bits 22:16) in *SHR are \
2400 * 0001 xxx 8B/16B, shift = 16 - UInt(immh:immb) \
2401 * 001x xxx 4H/8H, shift = 32 - UInt(immh:immb) \
2402 * 01xx xxx 2S/4S, shift = 64 - UInt(immh:immb) \
2403 * 1xxx xxx 1D/2D, shift = 128 - UInt(immh:immb) \
2404 * (1D is RESERVED) \
2405 * for SHL shift is calculated as: \
2406 * 0001 xxx 8B/16B, shift = UInt(immh:immb) - 8 \
2407 * 001x xxx 4H/8H, shift = UInt(immh:immb) - 16 \
2408 * 01xx xxx 2S/4S, shift = UInt(immh:immb) - 32 \
2409 * 1xxx xxx 1D/2D, shift = UInt(immh:immb) - 64 \
2410 * (1D is RESERVED) \
2411 */ \
2412 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2413 int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0))); \
2414 int encodedShift = isSHR ? cVal - shift : cVal + shift; \
2415 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2416 f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2417 }
2418
2419 INSN(shl, 0, 0b010101, /* isSHR = */ false);
2420 INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2421 INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2422
2423 #undef INSN
2424
2425 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2426 starti;
2427 /* The encodings for the immh:immb fields (bits 22:16) are
2428 * 0001 xxx 8H, 8B/16b shift = xxx
2429 * 001x xxx 4S, 4H/8H shift = xxxx
2430 * 01xx xxx 2D, 2S/4S shift = xxxxx
2431 * 1xxx xxx RESERVED
2432 */
2433 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2434 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2435 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2436 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2437 }
2438 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2439 ushll(Vd, Ta, Vn, Tb, shift);
2440 }
2441
2442 // Move from general purpose register
2443 // mov Vd.T[index], Rn
2444 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2445 starti;
2446 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2447 f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0);
2448 }
2449
2450 // Move to general purpose register
2451 // mov Rd, Vn.T[index]
2452 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2453 starti;
2454 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2455 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2456 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2457 }
2458
2459 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2460 starti;
2461 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2462 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2463 int size = (Ta == T1Q) ? 0b11 : 0b00;
2464 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2465 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2466 }
2467 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2468 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2469 pmull(Vd, Ta, Vn, Vm, Tb);
2470 }
2471
2472 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2473 starti;
2474 int size_b = (int)Tb >> 1;
2475 int size_a = (int)Ta >> 1;
2476 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2477 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2478 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2479 }
2480
2481 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2482 {
2483 starti;
2484 assert(T != T1D, "reserved encoding");
2485 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2486 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0);
2487 }
2488
2489 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2490 {
2491 starti;
2492 assert(T != T1D, "reserved encoding");
2493 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2494 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2495 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2496 }
2497
2498 // AdvSIMD ZIP/UZP/TRN
2499 #define INSN(NAME, opcode) \
2500 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2501 starti; \
2502 f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \
2503 f(opcode, 14, 12), f(0b10, 11, 10); \
2504 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); \
2505 f(T & 1, 30), f(T >> 1, 23, 22); \
2506 }
2507
2508 INSN(uzp1, 0b001);
2509 INSN(trn1, 0b010);
2510 INSN(zip1, 0b011);
2511 INSN(uzp2, 0b101);
2512 INSN(trn2, 0b110);
2513 INSN(zip2, 0b111);
2514
2515 #undef INSN
2516
2517 // CRC32 instructions
2518 #define INSN(NAME, c, sf, sz) \
2519 void NAME(Register Rd, Register Rn, Register Rm) { \
2520 starti; \
2521 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \
2522 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2523 }
2524
2525 INSN(crc32b, 0, 0, 0b00);
2526 INSN(crc32h, 0, 0, 0b01);
2527 INSN(crc32w, 0, 0, 0b10);
2528 INSN(crc32x, 0, 1, 0b11);
2529 INSN(crc32cb, 1, 0, 0b00);
2530 INSN(crc32ch, 1, 0, 0b01);
2531 INSN(crc32cw, 1, 0, 0b10);
2532 INSN(crc32cx, 1, 1, 0b11);
2533
2534 #undef INSN
2535
2536 // Table vector lookup
2537 #define INSN(NAME, op) \
2538 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2539 starti; \
2540 assert(T == T8B || T == T16B, "invalid arrangement"); \
2541 assert(0 < registers && registers <= 4, "invalid number of registers"); \
2542 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2543 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2544 }
2545
2546 INSN(tbl, 0);
2547 INSN(tbx, 1);
2548
2549 #undef INSN
2550
2551 // AdvSIMD two-reg misc
2552 #define INSN(NAME, U, opcode) \
2553 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2554 starti; \
2555 assert((ASSERTION), MSG); \
2556 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \
2557 f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12); \
2558 f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2559 }
2560
2561 #define MSG "invalid arrangement"
2562
2563 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2564 INSN(fsqrt, 1, 0b11111);
2565 INSN(fabs, 0, 0b01111);
2566 INSN(fneg, 1, 0b01111);
2567 #undef ASSERTION
2568
2569 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2570 INSN(rev64, 0, 0b00000);
2571 #undef ASSERTION
2572
2573 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2574 INSN(rev32, 1, 0b00000);
2575 private:
2576 INSN(_rbit, 1, 0b00101);
2577 public:
2578
2579 #undef ASSERTION
2580
2581 #define ASSERTION (T == T8B || T == T16B)
2582 INSN(rev16, 0, 0b00001);
2583 // RBIT only allows T8B and T16B but encodes them oddly. Argh...
2584 void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
2585 assert((ASSERTION), MSG);
2586 _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn);
2587 }
2588 #undef ASSERTION
2589
2590 #undef MSG
2591
2592 #undef INSN
2593
2594 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2595 {
2596 starti;
2597 assert(T == T8B || T == T16B, "invalid arrangement");
2598 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2599 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2600 rf(Vm, 16), f(0, 15), f(index, 14, 11);
2601 f(0, 10), rf(Vn, 5), rf(Vd, 0);
2602 }
2603
2604 /* Simulator extensions to the ISA
2605
2606 haltsim
2607
2608 takes no arguments, causes the sim to enter a debug break and then
2609 return from the simulator run() call with STATUS_HALT? The linking
2610 code will call fatal() when it sees STATUS_HALT.
2611
2612 blrt Xn, Wm
2613 blrt Xn, #gpargs, #fpargs, #type
2614 Xn holds the 64 bit x86 branch_address
2615 call format is encoded either as immediate data in the call
2616 or in register Wm. In the latter case
2617 Wm[13..6] = #gpargs,
2618 Wm[5..2] = #fpargs,
2619 Wm[1,0] = #type
2620
2621 calls the x86 code address 'branch_address' supplied in Xn passing
2622 arguments taken from the general and floating point registers according
2623 to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0
2624 or v0 according to the the return type #type' where
2625
2626 address branch_address;
2627 uimm4 gpargs;
2628 uimm4 fpargs;
2629 enum ReturnType type;
2630
2631 enum ReturnType
2632 {
2633 void_ret = 0,
2634 int_ret = 1,
2635 long_ret = 1,
2636 obj_ret = 1, // i.e. same as long
2637 float_ret = 2,
2638 double_ret = 3
2639 }
2640
2641 notify
2642
2643 notifies the simulator of a transfer of control. instr[14:0]
2644 identifies the type of change of control.
2645
2646 0 ==> initial entry to a method.
2647
2648 1 ==> return into a method from a submethod call.
2649
2650 2 ==> exit out of Java method code.
2651
2652 3 ==> start execution for a new bytecode.
2653
2654 in cases 1 and 2 the simulator is expected to use a JVM callback to
2655 identify the name of the specific method being executed. in case 4
2656 the simulator is expected to use a JVM callback to identify the
2657 bytecode index.
2658
2659 Instruction encodings
2660 ---------------------
2661
2662 These are encoded in the space with instr[28:25] = 00 which is
2663 unallocated. Encodings are
2664
2665 10987654321098765432109876543210
2666 PSEUDO_HALT = 0x11100000000000000000000000000000
2667 PSEUDO_BLRT = 0x11000000000000000_______________
2668 PSEUDO_BLRTR = 0x1100000000000000100000__________
2669 PSEUDO_NOTIFY = 0x10100000000000000_______________
2670
2671 instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY
2672
2673 for BLRT
2674 instr[14,11] = #gpargs, instr[10,7] = #fpargs
2675 instr[6,5] = #type, instr[4,0] = Rn
2676 for BLRTR
2677 instr[9,5] = Rm, instr[4,0] = Rn
2678 for NOTIFY
2679 instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart
2680 */
2681
2682 enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start };
2683
2684 virtual void notify(int type) {
2685 if (UseBuiltinSim) {
2686 starti;
2687 // 109
2688 f(0b101, 31, 29);
2689 // 87654321098765
2690 f(0b00000000000000, 28, 15);
2691 f(type, 14, 0);
2692 }
2693 }
2694
2695 void blrt(Register Rn, int gpargs, int fpargs, int type) {
2696 if (UseBuiltinSim) {
2697 starti;
2698 f(0b110, 31 ,29);
2699 f(0b00, 28, 25);
2700 // 4321098765
2701 f(0b0000000000, 24, 15);
2702 f(gpargs, 14, 11);
2703 f(fpargs, 10, 7);
2704 f(type, 6, 5);
2705 rf(Rn, 0);
2706 } else {
2707 blr(Rn);
2708 }
2709 }
2710
2711 void blrt(Register Rn, Register Rm) {
2712 if (UseBuiltinSim) {
2713 starti;
2714 f(0b110, 31 ,29);
2715 f(0b00, 28, 25);
2716 // 4321098765
2717 f(0b0000000001, 24, 15);
2718 // 43210
2719 f(0b00000, 14, 10);
2720 rf(Rm, 5);
2721 rf(Rn, 0);
2722 } else {
2723 blr(Rn);
2724 }
2725 }
2726
2727 void haltsim() {
2728 starti;
2729 f(0b111, 31 ,29);
2730 f(0b00, 28, 27);
2731 // 654321098765432109876543210
2732 f(0b000000000000000000000000000, 26, 0);
2733 }
2734
2735 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2736 }
2737
2738 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2739 Register tmp,
2740 int offset) {
2741 ShouldNotCallThis();
2742 return RegisterOrConstant();
2743 }
2744
2745 // Stack overflow checking
2746 virtual void bang_stack_with_offset(int offset);
2747
2748 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2749 static bool operand_valid_for_add_sub_immediate(long imm);
2750 static bool operand_valid_for_float_immediate(double imm);
2751
2752 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2753 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2754 };
2755
2756 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2757 Assembler::Membar_mask_bits b) {
2758 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2759 }
2760
2761 Instruction_aarch64::~Instruction_aarch64() {
2762 assem->emit();
2763 }
2764
2765 #undef starti
2766
2767 // Invert a condition
2768 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2769 return Assembler::Condition(int(cond) ^ 1);
2770 }
2771
2772 class BiasedLockingCounters;
2773
2774 extern "C" void das(uint64_t start, int len);
2775
2776 #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP