1 /* 2 * Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "memory/allocation.inline.hpp" 27 #include "opto/ad.hpp" 28 #include "opto/block.hpp" 29 #include "opto/c2compiler.hpp" 30 #include "opto/callnode.hpp" 31 #include "opto/cfgnode.hpp" 32 #include "opto/machnode.hpp" 33 #include "opto/runtime.hpp" 34 #include "opto/chaitin.hpp" 35 #include "runtime/sharedRuntime.hpp" 36 37 // Optimization - Graph Style 38 39 // Check whether val is not-null-decoded compressed oop, 40 // i.e. will grab into the base of the heap if it represents NULL. 41 static bool accesses_heap_base_zone(Node *val) { 42 if (Universe::narrow_oop_base() > 0) { // Implies UseCompressedOops. 43 if (val && val->is_Mach()) { 44 if (val->as_Mach()->ideal_Opcode() == Op_DecodeN) { 45 // This assumes all Decodes with TypePtr::NotNull are matched to nodes that 46 // decode NULL to point to the heap base (Decode_NN). 47 if (val->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull) { 48 return true; 49 } 50 } 51 // Must recognize load operation with Decode matched in memory operand. 52 // We should not reach here exept for PPC/AIX, as os::zero_page_read_protected() 53 // returns true everywhere else. On PPC, no such memory operands 54 // exist, therefore we did not yet implement a check for such operands. 55 NOT_AIX(Unimplemented()); 56 } 57 } 58 return false; 59 } 60 61 static bool needs_explicit_null_check_for_read(Node *val) { 62 // On some OSes (AIX) the page at address 0 is only write protected. 63 // If so, only Store operations will trap. 64 if (os::zero_page_read_protected()) { 65 return false; // Implicit null check will work. 66 } 67 // Also a read accessing the base of a heap-based compressed heap will trap. 68 if (accesses_heap_base_zone(val) && // Hits the base zone page. 69 Universe::narrow_oop_use_implicit_null_checks()) { // Base zone page is protected. 70 return false; 71 } 72 73 return true; 74 } 75 76 //------------------------------implicit_null_check---------------------------- 77 // Detect implicit-null-check opportunities. Basically, find NULL checks 78 // with suitable memory ops nearby. Use the memory op to do the NULL check. 79 // I can generate a memory op if there is not one nearby. 80 // The proj is the control projection for the not-null case. 81 // The val is the pointer being checked for nullness or 82 // decodeHeapOop_not_null node if it did not fold into address. 83 void PhaseCFG::implicit_null_check(Block* block, Node *proj, Node *val, int allowed_reasons) { 84 // Assume if null check need for 0 offset then always needed 85 // Intel solaris doesn't support any null checks yet and no 86 // mechanism exists (yet) to set the switches at an os_cpu level 87 if( !ImplicitNullChecks || MacroAssembler::needs_explicit_null_check(0)) return; 88 89 // Make sure the ptr-is-null path appears to be uncommon! 90 float f = block->end()->as_MachIf()->_prob; 91 if( proj->Opcode() == Op_IfTrue ) f = 1.0f - f; 92 if( f > PROB_UNLIKELY_MAG(4) ) return; 93 94 uint bidx = 0; // Capture index of value into memop 95 bool was_store; // Memory op is a store op 96 97 // Get the successor block for if the test ptr is non-null 98 Block* not_null_block; // this one goes with the proj 99 Block* null_block; 100 if (block->get_node(block->number_of_nodes()-1) == proj) { 101 null_block = block->_succs[0]; 102 not_null_block = block->_succs[1]; 103 } else { 104 assert(block->get_node(block->number_of_nodes()-2) == proj, "proj is one or the other"); 105 not_null_block = block->_succs[0]; 106 null_block = block->_succs[1]; 107 } 108 while (null_block->is_Empty() == Block::empty_with_goto) { 109 null_block = null_block->_succs[0]; 110 } 111 112 // Search the exception block for an uncommon trap. 113 // (See Parse::do_if and Parse::do_ifnull for the reason 114 // we need an uncommon trap. Briefly, we need a way to 115 // detect failure of this optimization, as in 6366351.) 116 { 117 bool found_trap = false; 118 for (uint i1 = 0; i1 < null_block->number_of_nodes(); i1++) { 119 Node* nn = null_block->get_node(i1); 120 if (nn->is_MachCall() && 121 nn->as_MachCall()->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) { 122 const Type* trtype = nn->in(TypeFunc::Parms)->bottom_type(); 123 if (trtype->isa_int() && trtype->is_int()->is_con()) { 124 jint tr_con = trtype->is_int()->get_con(); 125 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con); 126 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con); 127 assert((int)reason < (int)BitsPerInt, "recode bit map"); 128 if (is_set_nth_bit(allowed_reasons, (int) reason) 129 && action != Deoptimization::Action_none) { 130 // This uncommon trap is sure to recompile, eventually. 131 // When that happens, C->too_many_traps will prevent 132 // this transformation from happening again. 133 found_trap = true; 134 } 135 } 136 break; 137 } 138 } 139 if (!found_trap) { 140 // We did not find an uncommon trap. 141 return; 142 } 143 } 144 145 // Check for decodeHeapOop_not_null node which did not fold into address 146 bool is_decoden = ((intptr_t)val) & 1; 147 val = (Node*)(((intptr_t)val) & ~1); 148 149 assert(!is_decoden || (val->in(0) == NULL) && val->is_Mach() && 150 (val->as_Mach()->ideal_Opcode() == Op_DecodeN), "sanity"); 151 152 // Search the successor block for a load or store who's base value is also 153 // the tested value. There may be several. 154 Node_List *out = new Node_List(Thread::current()->resource_area()); 155 MachNode *best = NULL; // Best found so far 156 for (DUIterator i = val->outs(); val->has_out(i); i++) { 157 Node *m = val->out(i); 158 if( !m->is_Mach() ) continue; 159 MachNode *mach = m->as_Mach(); 160 was_store = false; 161 int iop = mach->ideal_Opcode(); 162 switch( iop ) { 163 case Op_LoadB: 164 case Op_LoadUB: 165 case Op_LoadUS: 166 case Op_LoadD: 167 case Op_LoadF: 168 case Op_LoadI: 169 case Op_LoadL: 170 case Op_LoadP: 171 case Op_LoadN: 172 case Op_LoadS: 173 case Op_LoadKlass: 174 case Op_LoadNKlass: 175 case Op_LoadRange: 176 case Op_LoadD_unaligned: 177 case Op_LoadL_unaligned: 178 assert(mach->in(2) == val, "should be address"); 179 break; 180 case Op_StoreB: 181 case Op_StoreC: 182 case Op_StoreCM: 183 case Op_StoreD: 184 case Op_StoreF: 185 case Op_StoreI: 186 case Op_StoreL: 187 case Op_StoreP: 188 case Op_StoreN: 189 case Op_StoreNKlass: 190 was_store = true; // Memory op is a store op 191 // Stores will have their address in slot 2 (memory in slot 1). 192 // If the value being nul-checked is in another slot, it means we 193 // are storing the checked value, which does NOT check the value! 194 if( mach->in(2) != val ) continue; 195 break; // Found a memory op? 196 case Op_StrComp: 197 case Op_StrEquals: 198 case Op_StrIndexOf: 199 case Op_StrIndexOfChar: 200 case Op_AryEq: 201 case Op_StrInflatedCopy: 202 case Op_StrCompressedCopy: 203 case Op_EncodeISOArray: 204 case Op_HasNegatives: 205 // Not a legit memory op for implicit null check regardless of 206 // embedded loads 207 continue; 208 default: // Also check for embedded loads 209 if( !mach->needs_anti_dependence_check() ) 210 continue; // Not an memory op; skip it 211 if( must_clone[iop] ) { 212 // Do not move nodes which produce flags because 213 // RA will try to clone it to place near branch and 214 // it will cause recompilation, see clone_node(). 215 continue; 216 } 217 { 218 // Check that value is used in memory address in 219 // instructions with embedded load (CmpP val1,(val2+off)). 220 Node* base; 221 Node* index; 222 const MachOper* oper = mach->memory_inputs(base, index); 223 if (oper == NULL || oper == (MachOper*)-1) { 224 continue; // Not an memory op; skip it 225 } 226 if (val == base || 227 val == index && val->bottom_type()->isa_narrowoop()) { 228 break; // Found it 229 } else { 230 continue; // Skip it 231 } 232 } 233 break; 234 } 235 236 // On some OSes (AIX) the page at address 0 is only write protected. 237 // If so, only Store operations will trap. 238 // But a read accessing the base of a heap-based compressed heap will trap. 239 if (!was_store && needs_explicit_null_check_for_read(val)) { 240 continue; 241 } 242 243 // Check that node's control edge is not-null block's head or dominates it, 244 // otherwise we can't hoist it because there are other control dependencies. 245 Node* ctrl = mach->in(0); 246 if (ctrl != NULL && !(ctrl == not_null_block->head() || 247 get_block_for_node(ctrl)->dominates(not_null_block))) { 248 continue; 249 } 250 251 // check if the offset is not too high for implicit exception 252 { 253 intptr_t offset = 0; 254 const TypePtr *adr_type = NULL; // Do not need this return value here 255 const Node* base = mach->get_base_and_disp(offset, adr_type); 256 if (base == NULL || base == NodeSentinel) { 257 // Narrow oop address doesn't have base, only index. 258 // Give up if offset is beyond page size or if heap base is not protected. 259 if (val->bottom_type()->isa_narrowoop() && 260 (MacroAssembler::needs_explicit_null_check(offset) || 261 !Universe::narrow_oop_use_implicit_null_checks())) 262 continue; 263 // cannot reason about it; is probably not implicit null exception 264 } else { 265 const TypePtr* tptr; 266 if (UseCompressedOops && (Universe::narrow_oop_shift() == 0 || 267 Universe::narrow_klass_shift() == 0)) { 268 // 32-bits narrow oop can be the base of address expressions 269 tptr = base->get_ptr_type(); 270 } else { 271 // only regular oops are expected here 272 tptr = base->bottom_type()->is_ptr(); 273 } 274 // Give up if offset is not a compile-time constant. 275 if (offset == Type::OffsetBot || tptr->offset() == Type::OffsetBot) 276 continue; 277 offset += tptr->offset(); // correct if base is offseted 278 // Give up if reference is beyond page size. 279 if (MacroAssembler::needs_explicit_null_check(offset)) 280 continue; 281 // Give up if base is a decode node and the heap base is not protected. 282 if (base->is_Mach() && base->as_Mach()->ideal_Opcode() == Op_DecodeN && 283 !Universe::narrow_oop_use_implicit_null_checks()) 284 continue; 285 } 286 } 287 288 // Check ctrl input to see if the null-check dominates the memory op 289 Block *cb = get_block_for_node(mach); 290 cb = cb->_idom; // Always hoist at least 1 block 291 if( !was_store ) { // Stores can be hoisted only one block 292 while( cb->_dom_depth > (block->_dom_depth + 1)) 293 cb = cb->_idom; // Hoist loads as far as we want 294 // The non-null-block should dominate the memory op, too. Live 295 // range spilling will insert a spill in the non-null-block if it is 296 // needs to spill the memory op for an implicit null check. 297 if (cb->_dom_depth == (block->_dom_depth + 1)) { 298 if (cb != not_null_block) continue; 299 cb = cb->_idom; 300 } 301 } 302 if( cb != block ) continue; 303 304 // Found a memory user; see if it can be hoisted to check-block 305 uint vidx = 0; // Capture index of value into memop 306 uint j; 307 for( j = mach->req()-1; j > 0; j-- ) { 308 if( mach->in(j) == val ) { 309 vidx = j; 310 // Ignore DecodeN val which could be hoisted to where needed. 311 if( is_decoden ) continue; 312 } 313 // Block of memory-op input 314 Block *inb = get_block_for_node(mach->in(j)); 315 Block *b = block; // Start from nul check 316 while( b != inb && b->_dom_depth > inb->_dom_depth ) 317 b = b->_idom; // search upwards for input 318 // See if input dominates null check 319 if( b != inb ) 320 break; 321 } 322 if( j > 0 ) 323 continue; 324 Block *mb = get_block_for_node(mach); 325 // Hoisting stores requires more checks for the anti-dependence case. 326 // Give up hoisting if we have to move the store past any load. 327 if( was_store ) { 328 Block *b = mb; // Start searching here for a local load 329 // mach use (faulting) trying to hoist 330 // n might be blocker to hoisting 331 while( b != block ) { 332 uint k; 333 for( k = 1; k < b->number_of_nodes(); k++ ) { 334 Node *n = b->get_node(k); 335 if( n->needs_anti_dependence_check() && 336 n->in(LoadNode::Memory) == mach->in(StoreNode::Memory) ) 337 break; // Found anti-dependent load 338 } 339 if( k < b->number_of_nodes() ) 340 break; // Found anti-dependent load 341 // Make sure control does not do a merge (would have to check allpaths) 342 if( b->num_preds() != 2 ) break; 343 b = get_block_for_node(b->pred(1)); // Move up to predecessor block 344 } 345 if( b != block ) continue; 346 } 347 348 // Make sure this memory op is not already being used for a NullCheck 349 Node *e = mb->end(); 350 if( e->is_MachNullCheck() && e->in(1) == mach ) 351 continue; // Already being used as a NULL check 352 353 // Found a candidate! Pick one with least dom depth - the highest 354 // in the dom tree should be closest to the null check. 355 if (best == NULL || get_block_for_node(mach)->_dom_depth < get_block_for_node(best)->_dom_depth) { 356 best = mach; 357 bidx = vidx; 358 } 359 } 360 // No candidate! 361 if (best == NULL) { 362 return; 363 } 364 365 // ---- Found an implicit null check 366 #ifndef PRODUCT 367 extern int implicit_null_checks; 368 implicit_null_checks++; 369 #endif 370 371 if( is_decoden ) { 372 // Check if we need to hoist decodeHeapOop_not_null first. 373 Block *valb = get_block_for_node(val); 374 if( block != valb && block->_dom_depth < valb->_dom_depth ) { 375 // Hoist it up to the end of the test block. 376 valb->find_remove(val); 377 block->add_inst(val); 378 map_node_to_block(val, block); 379 // DecodeN on x86 may kill flags. Check for flag-killing projections 380 // that also need to be hoisted. 381 for (DUIterator_Fast jmax, j = val->fast_outs(jmax); j < jmax; j++) { 382 Node* n = val->fast_out(j); 383 if( n->is_MachProj() ) { 384 get_block_for_node(n)->find_remove(n); 385 block->add_inst(n); 386 map_node_to_block(n, block); 387 } 388 } 389 } 390 } 391 // Hoist the memory candidate up to the end of the test block. 392 Block *old_block = get_block_for_node(best); 393 old_block->find_remove(best); 394 block->add_inst(best); 395 map_node_to_block(best, block); 396 397 // Move the control dependence if it is pinned to not-null block. 398 // Don't change it in other cases: NULL or dominating control. 399 if (best->in(0) == not_null_block->head()) { 400 // Set it to control edge of null check. 401 best->set_req(0, proj->in(0)->in(0)); 402 } 403 404 // Check for flag-killing projections that also need to be hoisted 405 // Should be DU safe because no edge updates. 406 for (DUIterator_Fast jmax, j = best->fast_outs(jmax); j < jmax; j++) { 407 Node* n = best->fast_out(j); 408 if( n->is_MachProj() ) { 409 get_block_for_node(n)->find_remove(n); 410 block->add_inst(n); 411 map_node_to_block(n, block); 412 } 413 } 414 415 // proj==Op_True --> ne test; proj==Op_False --> eq test. 416 // One of two graph shapes got matched: 417 // (IfTrue (If (Bool NE (CmpP ptr NULL)))) 418 // (IfFalse (If (Bool EQ (CmpP ptr NULL)))) 419 // NULL checks are always branch-if-eq. If we see a IfTrue projection 420 // then we are replacing a 'ne' test with a 'eq' NULL check test. 421 // We need to flip the projections to keep the same semantics. 422 if( proj->Opcode() == Op_IfTrue ) { 423 // Swap order of projections in basic block to swap branch targets 424 Node *tmp1 = block->get_node(block->end_idx()+1); 425 Node *tmp2 = block->get_node(block->end_idx()+2); 426 block->map_node(tmp2, block->end_idx()+1); 427 block->map_node(tmp1, block->end_idx()+2); 428 Node *tmp = new Node(C->top()); // Use not NULL input 429 tmp1->replace_by(tmp); 430 tmp2->replace_by(tmp1); 431 tmp->replace_by(tmp2); 432 tmp->destruct(); 433 } 434 435 // Remove the existing null check; use a new implicit null check instead. 436 // Since schedule-local needs precise def-use info, we need to correct 437 // it as well. 438 Node *old_tst = proj->in(0); 439 MachNode *nul_chk = new MachNullCheckNode(old_tst->in(0),best,bidx); 440 block->map_node(nul_chk, block->end_idx()); 441 map_node_to_block(nul_chk, block); 442 // Redirect users of old_test to nul_chk 443 for (DUIterator_Last i2min, i2 = old_tst->last_outs(i2min); i2 >= i2min; --i2) 444 old_tst->last_out(i2)->set_req(0, nul_chk); 445 // Clean-up any dead code 446 for (uint i3 = 0; i3 < old_tst->req(); i3++) { 447 Node* in = old_tst->in(i3); 448 old_tst->set_req(i3, NULL); 449 if (in->outcnt() == 0) { 450 // Remove dead input node 451 in->disconnect_inputs(NULL, C); 452 block->find_remove(in); 453 } 454 } 455 456 latency_from_uses(nul_chk); 457 latency_from_uses(best); 458 459 // insert anti-dependences to defs in this block 460 if (! best->needs_anti_dependence_check()) { 461 for (uint k = 1; k < block->number_of_nodes(); k++) { 462 Node *n = block->get_node(k); 463 if (n->needs_anti_dependence_check() && 464 n->in(LoadNode::Memory) == best->in(StoreNode::Memory)) { 465 // Found anti-dependent load 466 insert_anti_dependences(block, n); 467 } 468 } 469 } 470 } 471 472 473 //------------------------------select----------------------------------------- 474 // Select a nice fellow from the worklist to schedule next. If there is only 475 // one choice, then use it. Projections take top priority for correctness 476 // reasons - if I see a projection, then it is next. There are a number of 477 // other special cases, for instructions that consume condition codes, et al. 478 // These are chosen immediately. Some instructions are required to immediately 479 // precede the last instruction in the block, and these are taken last. Of the 480 // remaining cases (most), choose the instruction with the greatest latency 481 // (that is, the most number of pseudo-cycles required to the end of the 482 // routine). If there is a tie, choose the instruction with the most inputs. 483 Node* PhaseCFG::select( 484 Block* block, 485 Node_List &worklist, 486 GrowableArray<int> &ready_cnt, 487 VectorSet &next_call, 488 uint sched_slot, 489 intptr_t* recalc_pressure_nodes) { 490 491 // If only a single entry on the stack, use it 492 uint cnt = worklist.size(); 493 if (cnt == 1) { 494 Node *n = worklist[0]; 495 worklist.map(0,worklist.pop()); 496 return n; 497 } 498 499 uint choice = 0; // Bigger is most important 500 uint latency = 0; // Bigger is scheduled first 501 uint score = 0; // Bigger is better 502 int idx = -1; // Index in worklist 503 int cand_cnt = 0; // Candidate count 504 bool block_size_threshold_ok = (block->number_of_nodes() > 10) ? true : false; 505 506 for( uint i=0; i<cnt; i++ ) { // Inspect entire worklist 507 // Order in worklist is used to break ties. 508 // See caller for how this is used to delay scheduling 509 // of induction variable increments to after the other 510 // uses of the phi are scheduled. 511 Node *n = worklist[i]; // Get Node on worklist 512 513 int iop = n->is_Mach() ? n->as_Mach()->ideal_Opcode() : 0; 514 if( n->is_Proj() || // Projections always win 515 n->Opcode()== Op_Con || // So does constant 'Top' 516 iop == Op_CreateEx || // Create-exception must start block 517 iop == Op_CheckCastPP 518 ) { 519 worklist.map(i,worklist.pop()); 520 return n; 521 } 522 523 // Final call in a block must be adjacent to 'catch' 524 Node *e = block->end(); 525 if( e->is_Catch() && e->in(0)->in(0) == n ) 526 continue; 527 528 // Memory op for an implicit null check has to be at the end of the block 529 if( e->is_MachNullCheck() && e->in(1) == n ) 530 continue; 531 532 // Schedule IV increment last. 533 if (e->is_Mach() && e->as_Mach()->ideal_Opcode() == Op_CountedLoopEnd) { 534 // Cmp might be matched into CountedLoopEnd node. 535 Node *cmp = (e->in(1)->ideal_reg() == Op_RegFlags) ? e->in(1) : e; 536 if (cmp->req() > 1 && cmp->in(1) == n && n->is_iteratively_computed()) { 537 continue; 538 } 539 } 540 541 uint n_choice = 2; 542 543 // See if this instruction is consumed by a branch. If so, then (as the 544 // branch is the last instruction in the basic block) force it to the 545 // end of the basic block 546 if ( must_clone[iop] ) { 547 // See if any use is a branch 548 bool found_machif = false; 549 550 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) { 551 Node* use = n->fast_out(j); 552 553 // The use is a conditional branch, make them adjacent 554 if (use->is_MachIf() && get_block_for_node(use) == block) { 555 found_machif = true; 556 break; 557 } 558 559 // More than this instruction pending for successor to be ready, 560 // don't choose this if other opportunities are ready 561 if (ready_cnt.at(use->_idx) > 1) 562 n_choice = 1; 563 } 564 565 // loop terminated, prefer not to use this instruction 566 if (found_machif) 567 continue; 568 } 569 570 // See if this has a predecessor that is "must_clone", i.e. sets the 571 // condition code. If so, choose this first 572 for (uint j = 0; j < n->req() ; j++) { 573 Node *inn = n->in(j); 574 if (inn) { 575 if (inn->is_Mach() && must_clone[inn->as_Mach()->ideal_Opcode()] ) { 576 n_choice = 3; 577 break; 578 } 579 } 580 } 581 582 // MachTemps should be scheduled last so they are near their uses 583 if (n->is_MachTemp()) { 584 n_choice = 1; 585 } 586 587 uint n_latency = get_latency_for_node(n); 588 uint n_score = n->req(); // Many inputs get high score to break ties 589 590 if (OptoRegScheduling && block_size_threshold_ok) { 591 if (recalc_pressure_nodes[n->_idx] == 0x7fff7fff) { 592 _regalloc->_scratch_int_pressure.init(_regalloc->_sched_int_pressure.high_pressure_limit()); 593 _regalloc->_scratch_float_pressure.init(_regalloc->_sched_float_pressure.high_pressure_limit()); 594 // simulate the notion that we just picked this node to schedule 595 n->add_flag(Node::Flag_is_scheduled); 596 // now caculate its effect upon the graph if we did 597 adjust_register_pressure(n, block, recalc_pressure_nodes, false); 598 // return its state for finalize in case somebody else wins 599 n->remove_flag(Node::Flag_is_scheduled); 600 // now save the two final pressure components of register pressure, limiting pressure calcs to short size 601 short int_pressure = (short)_regalloc->_scratch_int_pressure.current_pressure(); 602 short float_pressure = (short)_regalloc->_scratch_float_pressure.current_pressure(); 603 recalc_pressure_nodes[n->_idx] = int_pressure; 604 recalc_pressure_nodes[n->_idx] |= (float_pressure << 16); 605 } 606 607 if (_scheduling_for_pressure) { 608 latency = n_latency; 609 if (n_choice != 3) { 610 // Now evaluate each register pressure component based on threshold in the score. 611 // In general the defining register type will dominate the score, ergo we will not see register pressure grow on both banks 612 // on a single instruction, but we might see it shrink on both banks. 613 // For each use of register that has a register class that is over the high pressure limit, we build n_score up for 614 // live ranges that terminate on this instruction. 615 if (_regalloc->_sched_int_pressure.current_pressure() > _regalloc->_sched_int_pressure.high_pressure_limit()) { 616 short int_pressure = (short)recalc_pressure_nodes[n->_idx]; 617 n_score = (int_pressure < 0) ? ((score + n_score) - int_pressure) : (int_pressure > 0) ? 1 : n_score; 618 } 619 if (_regalloc->_sched_float_pressure.current_pressure() > _regalloc->_sched_float_pressure.high_pressure_limit()) { 620 short float_pressure = (short)(recalc_pressure_nodes[n->_idx] >> 16); 621 n_score = (float_pressure < 0) ? ((score + n_score) - float_pressure) : (float_pressure > 0) ? 1 : n_score; 622 } 623 } else { 624 // make sure we choose these candidates 625 score = 0; 626 } 627 } 628 } 629 630 // Keep best latency found 631 cand_cnt++; 632 if (choice < n_choice || 633 (choice == n_choice && 634 ((StressLCM && Compile::randomized_select(cand_cnt)) || 635 (!StressLCM && 636 (latency < n_latency || 637 (latency == n_latency && 638 (score < n_score))))))) { 639 choice = n_choice; 640 latency = n_latency; 641 score = n_score; 642 idx = i; // Also keep index in worklist 643 } 644 } // End of for all ready nodes in worklist 645 646 assert(idx >= 0, "index should be set"); 647 Node *n = worklist[(uint)idx]; // Get the winner 648 649 worklist.map((uint)idx, worklist.pop()); // Compress worklist 650 return n; 651 } 652 653 //-------------------------adjust_register_pressure---------------------------- 654 void PhaseCFG::adjust_register_pressure(Node* n, Block* block, intptr_t* recalc_pressure_nodes, bool finalize_mode) { 655 PhaseLive* liveinfo = _regalloc->get_live(); 656 IndexSet* liveout = liveinfo->live(block); 657 // first adjust the register pressure for the sources 658 for (uint i = 1; i < n->req(); i++) { 659 bool lrg_ends = false; 660 Node *src_n = n->in(i); 661 if (src_n == NULL) continue; 662 if (!src_n->is_Mach()) continue; 663 uint src = _regalloc->_lrg_map.find(src_n); 664 if (src == 0) continue; 665 LRG& lrg_src = _regalloc->lrgs(src); 666 // detect if the live range ends or not 667 if (liveout->member(src) == false) { 668 lrg_ends = true; 669 for (DUIterator_Fast jmax, j = src_n->fast_outs(jmax); j < jmax; j++) { 670 Node* m = src_n->fast_out(j); // Get user 671 if (m == n) continue; 672 if (!m->is_Mach()) continue; 673 MachNode *mach = m->as_Mach(); 674 bool src_matches = false; 675 int iop = mach->ideal_Opcode(); 676 677 switch (iop) { 678 case Op_StoreB: 679 case Op_StoreC: 680 case Op_StoreCM: 681 case Op_StoreD: 682 case Op_StoreF: 683 case Op_StoreI: 684 case Op_StoreL: 685 case Op_StoreP: 686 case Op_StoreN: 687 case Op_StoreVector: 688 case Op_StoreNKlass: 689 for (uint k = 1; k < m->req(); k++) { 690 Node *in = m->in(k); 691 if (in == src_n) { 692 src_matches = true; 693 break; 694 } 695 } 696 break; 697 698 default: 699 src_matches = true; 700 break; 701 } 702 703 // If we have a store as our use, ignore the non source operands 704 if (src_matches == false) continue; 705 706 // Mark every unscheduled use which is not n with a recalculation 707 if ((get_block_for_node(m) == block) && (!m->is_scheduled())) { 708 if (finalize_mode && !m->is_Phi()) { 709 recalc_pressure_nodes[m->_idx] = 0x7fff7fff; 710 } 711 lrg_ends = false; 712 } 713 } 714 } 715 // if none, this live range ends and we can adjust register pressure 716 if (lrg_ends) { 717 if (finalize_mode) { 718 _regalloc->lower_pressure(block, 0, lrg_src, NULL, _regalloc->_sched_int_pressure, _regalloc->_sched_float_pressure); 719 } else { 720 _regalloc->lower_pressure(block, 0, lrg_src, NULL, _regalloc->_scratch_int_pressure, _regalloc->_scratch_float_pressure); 721 } 722 } 723 } 724 725 // now add the register pressure from the dest and evaluate which heuristic we should use: 726 // 1.) The default, latency scheduling 727 // 2.) Register pressure scheduling based on the high pressure limit threshold for int or float register stacks 728 uint dst = _regalloc->_lrg_map.find(n); 729 if (dst != 0) { 730 LRG& lrg_dst = _regalloc->lrgs(dst); 731 if (finalize_mode) { 732 _regalloc->raise_pressure(block, lrg_dst, _regalloc->_sched_int_pressure, _regalloc->_sched_float_pressure); 733 // check to see if we fall over the register pressure cliff here 734 if (_regalloc->_sched_int_pressure.current_pressure() > _regalloc->_sched_int_pressure.high_pressure_limit()) { 735 _scheduling_for_pressure = true; 736 } else if (_regalloc->_sched_float_pressure.current_pressure() > _regalloc->_sched_float_pressure.high_pressure_limit()) { 737 _scheduling_for_pressure = true; 738 } else { 739 // restore latency scheduling mode 740 _scheduling_for_pressure = false; 741 } 742 } else { 743 _regalloc->raise_pressure(block, lrg_dst, _regalloc->_scratch_int_pressure, _regalloc->_scratch_float_pressure); 744 } 745 } 746 } 747 748 //------------------------------set_next_call---------------------------------- 749 void PhaseCFG::set_next_call(Block* block, Node* n, VectorSet& next_call) { 750 if( next_call.test_set(n->_idx) ) return; 751 for( uint i=0; i<n->len(); i++ ) { 752 Node *m = n->in(i); 753 if( !m ) continue; // must see all nodes in block that precede call 754 if (get_block_for_node(m) == block) { 755 set_next_call(block, m, next_call); 756 } 757 } 758 } 759 760 //------------------------------needed_for_next_call--------------------------- 761 // Set the flag 'next_call' for each Node that is needed for the next call to 762 // be scheduled. This flag lets me bias scheduling so Nodes needed for the 763 // next subroutine call get priority - basically it moves things NOT needed 764 // for the next call till after the call. This prevents me from trying to 765 // carry lots of stuff live across a call. 766 void PhaseCFG::needed_for_next_call(Block* block, Node* this_call, VectorSet& next_call) { 767 // Find the next control-defining Node in this block 768 Node* call = NULL; 769 for (DUIterator_Fast imax, i = this_call->fast_outs(imax); i < imax; i++) { 770 Node* m = this_call->fast_out(i); 771 if (get_block_for_node(m) == block && // Local-block user 772 m != this_call && // Not self-start node 773 m->is_MachCall()) { 774 call = m; 775 break; 776 } 777 } 778 if (call == NULL) return; // No next call (e.g., block end is near) 779 // Set next-call for all inputs to this call 780 set_next_call(block, call, next_call); 781 } 782 783 //------------------------------add_call_kills------------------------------------- 784 // helper function that adds caller save registers to MachProjNode 785 static void add_call_kills(MachProjNode *proj, RegMask& regs, const char* save_policy, bool exclude_soe) { 786 // Fill in the kill mask for the call 787 for( OptoReg::Name r = OptoReg::Name(0); r < _last_Mach_Reg; r=OptoReg::add(r,1) ) { 788 if( !regs.Member(r) ) { // Not already defined by the call 789 // Save-on-call register? 790 if ((save_policy[r] == 'C') || 791 (save_policy[r] == 'A') || 792 ((save_policy[r] == 'E') && exclude_soe)) { 793 proj->_rout.Insert(r); 794 } 795 } 796 } 797 } 798 799 800 //------------------------------sched_call------------------------------------- 801 uint PhaseCFG::sched_call(Block* block, uint node_cnt, Node_List& worklist, GrowableArray<int>& ready_cnt, MachCallNode* mcall, VectorSet& next_call) { 802 RegMask regs; 803 804 // Schedule all the users of the call right now. All the users are 805 // projection Nodes, so they must be scheduled next to the call. 806 // Collect all the defined registers. 807 for (DUIterator_Fast imax, i = mcall->fast_outs(imax); i < imax; i++) { 808 Node* n = mcall->fast_out(i); 809 assert( n->is_MachProj(), "" ); 810 int n_cnt = ready_cnt.at(n->_idx)-1; 811 ready_cnt.at_put(n->_idx, n_cnt); 812 assert( n_cnt == 0, "" ); 813 // Schedule next to call 814 block->map_node(n, node_cnt++); 815 // Collect defined registers 816 regs.OR(n->out_RegMask()); 817 // Check for scheduling the next control-definer 818 if( n->bottom_type() == Type::CONTROL ) 819 // Warm up next pile of heuristic bits 820 needed_for_next_call(block, n, next_call); 821 822 // Children of projections are now all ready 823 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) { 824 Node* m = n->fast_out(j); // Get user 825 if(get_block_for_node(m) != block) { 826 continue; 827 } 828 if( m->is_Phi() ) continue; 829 int m_cnt = ready_cnt.at(m->_idx) - 1; 830 ready_cnt.at_put(m->_idx, m_cnt); 831 if( m_cnt == 0 ) 832 worklist.push(m); 833 } 834 835 } 836 837 // Act as if the call defines the Frame Pointer. 838 // Certainly the FP is alive and well after the call. 839 regs.Insert(_matcher.c_frame_pointer()); 840 841 // Set all registers killed and not already defined by the call. 842 uint r_cnt = mcall->tf()->range()->cnt(); 843 int op = mcall->ideal_Opcode(); 844 MachProjNode *proj = new MachProjNode( mcall, r_cnt+1, RegMask::Empty, MachProjNode::fat_proj ); 845 map_node_to_block(proj, block); 846 block->insert_node(proj, node_cnt++); 847 848 // Select the right register save policy. 849 const char *save_policy = NULL; 850 switch (op) { 851 case Op_CallRuntime: 852 case Op_CallLeaf: 853 case Op_CallLeafNoFP: 854 // Calling C code so use C calling convention 855 save_policy = _matcher._c_reg_save_policy; 856 break; 857 858 case Op_CallStaticJava: 859 case Op_CallDynamicJava: 860 // Calling Java code so use Java calling convention 861 save_policy = _matcher._register_save_policy; 862 break; 863 864 default: 865 ShouldNotReachHere(); 866 } 867 868 // When using CallRuntime mark SOE registers as killed by the call 869 // so values that could show up in the RegisterMap aren't live in a 870 // callee saved register since the register wouldn't know where to 871 // find them. CallLeaf and CallLeafNoFP are ok because they can't 872 // have debug info on them. Strictly speaking this only needs to be 873 // done for oops since idealreg2debugmask takes care of debug info 874 // references but there no way to handle oops differently than other 875 // pointers as far as the kill mask goes. 876 bool exclude_soe = op == Op_CallRuntime; 877 878 // If the call is a MethodHandle invoke, we need to exclude the 879 // register which is used to save the SP value over MH invokes from 880 // the mask. Otherwise this register could be used for 881 // deoptimization information. 882 if (op == Op_CallStaticJava) { 883 MachCallStaticJavaNode* mcallstaticjava = (MachCallStaticJavaNode*) mcall; 884 if (mcallstaticjava->_method_handle_invoke) 885 proj->_rout.OR(Matcher::method_handle_invoke_SP_save_mask()); 886 } 887 888 add_call_kills(proj, regs, save_policy, exclude_soe); 889 890 return node_cnt; 891 } 892 893 894 //------------------------------schedule_local--------------------------------- 895 // Topological sort within a block. Someday become a real scheduler. 896 bool PhaseCFG::schedule_local(Block* block, GrowableArray<int>& ready_cnt, VectorSet& next_call, intptr_t *recalc_pressure_nodes) { 897 // Already "sorted" are the block start Node (as the first entry), and 898 // the block-ending Node and any trailing control projections. We leave 899 // these alone. PhiNodes and ParmNodes are made to follow the block start 900 // Node. Everything else gets topo-sorted. 901 902 #ifndef PRODUCT 903 if (trace_opto_pipelining()) { 904 tty->print_cr("# --- schedule_local B%d, before: ---", block->_pre_order); 905 for (uint i = 0;i < block->number_of_nodes(); i++) { 906 tty->print("# "); 907 block->get_node(i)->fast_dump(); 908 } 909 tty->print_cr("#"); 910 } 911 #endif 912 913 // RootNode is already sorted 914 if (block->number_of_nodes() == 1) { 915 return true; 916 } 917 918 bool block_size_threshold_ok = (block->number_of_nodes() > 10) ? true : false; 919 920 // We track the uses of local definitions as input dependences so that 921 // we know when a given instruction is avialable to be scheduled. 922 uint i; 923 if (OptoRegScheduling && block_size_threshold_ok) { 924 for (i = 1; i < block->number_of_nodes(); i++) { // setup nodes for pressure calc 925 Node *n = block->get_node(i); 926 n->remove_flag(Node::Flag_is_scheduled); 927 if (!n->is_Phi()) { 928 recalc_pressure_nodes[n->_idx] = 0x7fff7fff; 929 } 930 } 931 } 932 933 // Move PhiNodes and ParmNodes from 1 to cnt up to the start 934 uint node_cnt = block->end_idx(); 935 uint phi_cnt = 1; 936 for( i = 1; i<node_cnt; i++ ) { // Scan for Phi 937 Node *n = block->get_node(i); 938 if( n->is_Phi() || // Found a PhiNode or ParmNode 939 (n->is_Proj() && n->in(0) == block->head()) ) { 940 // Move guy at 'phi_cnt' to the end; makes a hole at phi_cnt 941 block->map_node(block->get_node(phi_cnt), i); 942 block->map_node(n, phi_cnt++); // swap Phi/Parm up front 943 if (OptoRegScheduling && block_size_threshold_ok) { 944 // mark n as scheduled 945 n->add_flag(Node::Flag_is_scheduled); 946 } 947 } else { // All others 948 // Count block-local inputs to 'n' 949 uint cnt = n->len(); // Input count 950 uint local = 0; 951 for( uint j=0; j<cnt; j++ ) { 952 Node *m = n->in(j); 953 if( m && get_block_for_node(m) == block && !m->is_top() ) 954 local++; // One more block-local input 955 } 956 ready_cnt.at_put(n->_idx, local); // Count em up 957 958 #ifdef ASSERT 959 if( UseConcMarkSweepGC || UseG1GC ) { 960 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_StoreCM ) { 961 // Check the precedence edges 962 for (uint prec = n->req(); prec < n->len(); prec++) { 963 Node* oop_store = n->in(prec); 964 if (oop_store != NULL) { 965 assert(get_block_for_node(oop_store)->_dom_depth <= block->_dom_depth, "oop_store must dominate card-mark"); 966 } 967 } 968 } 969 } 970 #endif 971 972 // A few node types require changing a required edge to a precedence edge 973 // before allocation. 974 if( n->is_Mach() && n->req() > TypeFunc::Parms && 975 (n->as_Mach()->ideal_Opcode() == Op_MemBarAcquire || 976 n->as_Mach()->ideal_Opcode() == Op_MemBarVolatile) ) { 977 // MemBarAcquire could be created without Precedent edge. 978 // del_req() replaces the specified edge with the last input edge 979 // and then removes the last edge. If the specified edge > number of 980 // edges the last edge will be moved outside of the input edges array 981 // and the edge will be lost. This is why this code should be 982 // executed only when Precedent (== TypeFunc::Parms) edge is present. 983 Node *x = n->in(TypeFunc::Parms); 984 if (x != NULL && get_block_for_node(x) == block && n->find_prec_edge(x) != -1) { 985 // Old edge to node within same block will get removed, but no precedence 986 // edge will get added because it already exists. Update ready count. 987 int cnt = ready_cnt.at(n->_idx); 988 assert(cnt > 1, "MemBar node %d must not get ready here", n->_idx); 989 ready_cnt.at_put(n->_idx, cnt-1); 990 } 991 n->del_req(TypeFunc::Parms); 992 n->add_prec(x); 993 } 994 } 995 } 996 for(uint i2=i; i2< block->number_of_nodes(); i2++ ) // Trailing guys get zapped count 997 ready_cnt.at_put(block->get_node(i2)->_idx, 0); 998 999 // All the prescheduled guys do not hold back internal nodes 1000 uint i3; 1001 for (i3 = 0; i3 < phi_cnt; i3++) { // For all pre-scheduled 1002 Node *n = block->get_node(i3); // Get pre-scheduled 1003 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) { 1004 Node* m = n->fast_out(j); 1005 if (get_block_for_node(m) == block) { // Local-block user 1006 int m_cnt = ready_cnt.at(m->_idx)-1; 1007 if (OptoRegScheduling && block_size_threshold_ok) { 1008 // mark m as scheduled 1009 if (m_cnt < 0) { 1010 m->add_flag(Node::Flag_is_scheduled); 1011 } 1012 } 1013 ready_cnt.at_put(m->_idx, m_cnt); // Fix ready count 1014 } 1015 } 1016 } 1017 1018 Node_List delay; 1019 // Make a worklist 1020 Node_List worklist; 1021 for(uint i4=i3; i4<node_cnt; i4++ ) { // Put ready guys on worklist 1022 Node *m = block->get_node(i4); 1023 if( !ready_cnt.at(m->_idx) ) { // Zero ready count? 1024 if (m->is_iteratively_computed()) { 1025 // Push induction variable increments last to allow other uses 1026 // of the phi to be scheduled first. The select() method breaks 1027 // ties in scheduling by worklist order. 1028 delay.push(m); 1029 } else if (m->is_Mach() && m->as_Mach()->ideal_Opcode() == Op_CreateEx) { 1030 // Force the CreateEx to the top of the list so it's processed 1031 // first and ends up at the start of the block. 1032 worklist.insert(0, m); 1033 } else { 1034 worklist.push(m); // Then on to worklist! 1035 } 1036 } 1037 } 1038 while (delay.size()) { 1039 Node* d = delay.pop(); 1040 worklist.push(d); 1041 } 1042 1043 if (OptoRegScheduling && block_size_threshold_ok) { 1044 // To stage register pressure calculations we need to examine the live set variables 1045 // breaking them up by register class to compartmentalize the calculations. 1046 uint float_pressure = Matcher::float_pressure(FLOATPRESSURE); 1047 _regalloc->_sched_int_pressure.init(INTPRESSURE); 1048 _regalloc->_sched_float_pressure.init(float_pressure); 1049 _regalloc->_scratch_int_pressure.init(INTPRESSURE); 1050 _regalloc->_scratch_float_pressure.init(float_pressure); 1051 1052 _regalloc->compute_entry_block_pressure(block); 1053 } 1054 1055 // Warm up the 'next_call' heuristic bits 1056 needed_for_next_call(block, block->head(), next_call); 1057 1058 #ifndef PRODUCT 1059 if (trace_opto_pipelining()) { 1060 for (uint j=0; j< block->number_of_nodes(); j++) { 1061 Node *n = block->get_node(j); 1062 int idx = n->_idx; 1063 tty->print("# ready cnt:%3d ", ready_cnt.at(idx)); 1064 tty->print("latency:%3d ", get_latency_for_node(n)); 1065 tty->print("%4d: %s\n", idx, n->Name()); 1066 } 1067 } 1068 #endif 1069 1070 uint max_idx = (uint)ready_cnt.length(); 1071 // Pull from worklist and schedule 1072 while( worklist.size() ) { // Worklist is not ready 1073 1074 #ifndef PRODUCT 1075 if (trace_opto_pipelining()) { 1076 tty->print("# ready list:"); 1077 for( uint i=0; i<worklist.size(); i++ ) { // Inspect entire worklist 1078 Node *n = worklist[i]; // Get Node on worklist 1079 tty->print(" %d", n->_idx); 1080 } 1081 tty->cr(); 1082 } 1083 #endif 1084 1085 // Select and pop a ready guy from worklist 1086 Node* n = select(block, worklist, ready_cnt, next_call, phi_cnt, recalc_pressure_nodes); 1087 block->map_node(n, phi_cnt++); // Schedule him next 1088 1089 if (OptoRegScheduling && block_size_threshold_ok) { 1090 n->add_flag(Node::Flag_is_scheduled); 1091 1092 // Now adjust the resister pressure with the node we selected 1093 if (!n->is_Phi()) { 1094 adjust_register_pressure(n, block, recalc_pressure_nodes, true); 1095 } 1096 } 1097 1098 #ifndef PRODUCT 1099 if (trace_opto_pipelining()) { 1100 tty->print("# select %d: %s", n->_idx, n->Name()); 1101 tty->print(", latency:%d", get_latency_for_node(n)); 1102 n->dump(); 1103 if (Verbose) { 1104 tty->print("# ready list:"); 1105 for( uint i=0; i<worklist.size(); i++ ) { // Inspect entire worklist 1106 Node *n = worklist[i]; // Get Node on worklist 1107 tty->print(" %d", n->_idx); 1108 } 1109 tty->cr(); 1110 } 1111 } 1112 1113 #endif 1114 if( n->is_MachCall() ) { 1115 MachCallNode *mcall = n->as_MachCall(); 1116 phi_cnt = sched_call(block, phi_cnt, worklist, ready_cnt, mcall, next_call); 1117 continue; 1118 } 1119 1120 if (n->is_Mach() && n->as_Mach()->has_call()) { 1121 RegMask regs; 1122 regs.Insert(_matcher.c_frame_pointer()); 1123 regs.OR(n->out_RegMask()); 1124 1125 MachProjNode *proj = new MachProjNode( n, 1, RegMask::Empty, MachProjNode::fat_proj ); 1126 map_node_to_block(proj, block); 1127 block->insert_node(proj, phi_cnt++); 1128 1129 add_call_kills(proj, regs, _matcher._c_reg_save_policy, false); 1130 } 1131 1132 // Children are now all ready 1133 for (DUIterator_Fast i5max, i5 = n->fast_outs(i5max); i5 < i5max; i5++) { 1134 Node* m = n->fast_out(i5); // Get user 1135 if (get_block_for_node(m) != block) { 1136 continue; 1137 } 1138 if( m->is_Phi() ) continue; 1139 if (m->_idx >= max_idx) { // new node, skip it 1140 assert(m->is_MachProj() && n->is_Mach() && n->as_Mach()->has_call(), "unexpected node types"); 1141 continue; 1142 } 1143 int m_cnt = ready_cnt.at(m->_idx) - 1; 1144 ready_cnt.at_put(m->_idx, m_cnt); 1145 if( m_cnt == 0 ) 1146 worklist.push(m); 1147 } 1148 } 1149 1150 if( phi_cnt != block->end_idx() ) { 1151 // did not schedule all. Retry, Bailout, or Die 1152 if (C->subsume_loads() == true && !C->failing()) { 1153 // Retry with subsume_loads == false 1154 // If this is the first failure, the sentinel string will "stick" 1155 // to the Compile object, and the C2Compiler will see it and retry. 1156 C->record_failure(C2Compiler::retry_no_subsuming_loads()); 1157 } else { 1158 assert(false, "graph should be schedulable"); 1159 } 1160 // assert( phi_cnt == end_idx(), "did not schedule all" ); 1161 return false; 1162 } 1163 1164 if (OptoRegScheduling && block_size_threshold_ok) { 1165 _regalloc->compute_exit_block_pressure(block); 1166 block->_reg_pressure = _regalloc->_sched_int_pressure.final_pressure(); 1167 block->_freg_pressure = _regalloc->_sched_float_pressure.final_pressure(); 1168 } 1169 1170 #ifndef PRODUCT 1171 if (trace_opto_pipelining()) { 1172 tty->print_cr("#"); 1173 tty->print_cr("# after schedule_local"); 1174 for (uint i = 0;i < block->number_of_nodes();i++) { 1175 tty->print("# "); 1176 block->get_node(i)->fast_dump(); 1177 } 1178 tty->print_cr("# "); 1179 1180 if (OptoRegScheduling && block_size_threshold_ok) { 1181 tty->print_cr("# pressure info : %d", block->_pre_order); 1182 _regalloc->print_pressure_info(_regalloc->_sched_int_pressure, "int register info"); 1183 _regalloc->print_pressure_info(_regalloc->_sched_float_pressure, "float register info"); 1184 } 1185 tty->cr(); 1186 } 1187 #endif 1188 1189 return true; 1190 } 1191 1192 //--------------------------catch_cleanup_fix_all_inputs----------------------- 1193 static void catch_cleanup_fix_all_inputs(Node *use, Node *old_def, Node *new_def) { 1194 for (uint l = 0; l < use->len(); l++) { 1195 if (use->in(l) == old_def) { 1196 if (l < use->req()) { 1197 use->set_req(l, new_def); 1198 } else { 1199 use->rm_prec(l); 1200 use->add_prec(new_def); 1201 l--; 1202 } 1203 } 1204 } 1205 } 1206 1207 //------------------------------catch_cleanup_find_cloned_def------------------ 1208 Node* PhaseCFG::catch_cleanup_find_cloned_def(Block *use_blk, Node *def, Block *def_blk, int n_clone_idx) { 1209 assert( use_blk != def_blk, "Inter-block cleanup only"); 1210 1211 // The use is some block below the Catch. Find and return the clone of the def 1212 // that dominates the use. If there is no clone in a dominating block, then 1213 // create a phi for the def in a dominating block. 1214 1215 // Find which successor block dominates this use. The successor 1216 // blocks must all be single-entry (from the Catch only; I will have 1217 // split blocks to make this so), hence they all dominate. 1218 while( use_blk->_dom_depth > def_blk->_dom_depth+1 ) 1219 use_blk = use_blk->_idom; 1220 1221 // Find the successor 1222 Node *fixup = NULL; 1223 1224 uint j; 1225 for( j = 0; j < def_blk->_num_succs; j++ ) 1226 if( use_blk == def_blk->_succs[j] ) 1227 break; 1228 1229 if( j == def_blk->_num_succs ) { 1230 // Block at same level in dom-tree is not a successor. It needs a 1231 // PhiNode, the PhiNode uses from the def and IT's uses need fixup. 1232 Node_Array inputs = new Node_List(Thread::current()->resource_area()); 1233 for(uint k = 1; k < use_blk->num_preds(); k++) { 1234 Block* block = get_block_for_node(use_blk->pred(k)); 1235 inputs.map(k, catch_cleanup_find_cloned_def(block, def, def_blk, n_clone_idx)); 1236 } 1237 1238 // Check to see if the use_blk already has an identical phi inserted. 1239 // If it exists, it will be at the first position since all uses of a 1240 // def are processed together. 1241 Node *phi = use_blk->get_node(1); 1242 if( phi->is_Phi() ) { 1243 fixup = phi; 1244 for (uint k = 1; k < use_blk->num_preds(); k++) { 1245 if (phi->in(k) != inputs[k]) { 1246 // Not a match 1247 fixup = NULL; 1248 break; 1249 } 1250 } 1251 } 1252 1253 // If an existing PhiNode was not found, make a new one. 1254 if (fixup == NULL) { 1255 Node *new_phi = PhiNode::make(use_blk->head(), def); 1256 use_blk->insert_node(new_phi, 1); 1257 map_node_to_block(new_phi, use_blk); 1258 for (uint k = 1; k < use_blk->num_preds(); k++) { 1259 new_phi->set_req(k, inputs[k]); 1260 } 1261 fixup = new_phi; 1262 } 1263 1264 } else { 1265 // Found the use just below the Catch. Make it use the clone. 1266 fixup = use_blk->get_node(n_clone_idx); 1267 } 1268 1269 return fixup; 1270 } 1271 1272 //--------------------------catch_cleanup_intra_block-------------------------- 1273 // Fix all input edges in use that reference "def". The use is in the same 1274 // block as the def and both have been cloned in each successor block. 1275 static void catch_cleanup_intra_block(Node *use, Node *def, Block *blk, int beg, int n_clone_idx) { 1276 1277 // Both the use and def have been cloned. For each successor block, 1278 // get the clone of the use, and make its input the clone of the def 1279 // found in that block. 1280 1281 uint use_idx = blk->find_node(use); 1282 uint offset_idx = use_idx - beg; 1283 for( uint k = 0; k < blk->_num_succs; k++ ) { 1284 // Get clone in each successor block 1285 Block *sb = blk->_succs[k]; 1286 Node *clone = sb->get_node(offset_idx+1); 1287 assert( clone->Opcode() == use->Opcode(), "" ); 1288 1289 // Make use-clone reference the def-clone 1290 catch_cleanup_fix_all_inputs(clone, def, sb->get_node(n_clone_idx)); 1291 } 1292 } 1293 1294 //------------------------------catch_cleanup_inter_block--------------------- 1295 // Fix all input edges in use that reference "def". The use is in a different 1296 // block than the def. 1297 void PhaseCFG::catch_cleanup_inter_block(Node *use, Block *use_blk, Node *def, Block *def_blk, int n_clone_idx) { 1298 if( !use_blk ) return; // Can happen if the use is a precedence edge 1299 1300 Node *new_def = catch_cleanup_find_cloned_def(use_blk, def, def_blk, n_clone_idx); 1301 catch_cleanup_fix_all_inputs(use, def, new_def); 1302 } 1303 1304 //------------------------------call_catch_cleanup----------------------------- 1305 // If we inserted any instructions between a Call and his CatchNode, 1306 // clone the instructions on all paths below the Catch. 1307 void PhaseCFG::call_catch_cleanup(Block* block) { 1308 1309 // End of region to clone 1310 uint end = block->end_idx(); 1311 if( !block->get_node(end)->is_Catch() ) return; 1312 // Start of region to clone 1313 uint beg = end; 1314 while(!block->get_node(beg-1)->is_MachProj() || 1315 !block->get_node(beg-1)->in(0)->is_MachCall() ) { 1316 beg--; 1317 assert(beg > 0,"Catch cleanup walking beyond block boundary"); 1318 } 1319 // Range of inserted instructions is [beg, end) 1320 if( beg == end ) return; 1321 1322 // Clone along all Catch output paths. Clone area between the 'beg' and 1323 // 'end' indices. 1324 for( uint i = 0; i < block->_num_succs; i++ ) { 1325 Block *sb = block->_succs[i]; 1326 // Clone the entire area; ignoring the edge fixup for now. 1327 for( uint j = end; j > beg; j-- ) { 1328 Node *clone = block->get_node(j-1)->clone(); 1329 sb->insert_node(clone, 1); 1330 map_node_to_block(clone, sb); 1331 if (clone->needs_anti_dependence_check()) { 1332 insert_anti_dependences(sb, clone); 1333 } 1334 } 1335 } 1336 1337 1338 // Fixup edges. Check the def-use info per cloned Node 1339 for(uint i2 = beg; i2 < end; i2++ ) { 1340 uint n_clone_idx = i2-beg+1; // Index of clone of n in each successor block 1341 Node *n = block->get_node(i2); // Node that got cloned 1342 // Need DU safe iterator because of edge manipulation in calls. 1343 Unique_Node_List *out = new Unique_Node_List(Thread::current()->resource_area()); 1344 for (DUIterator_Fast j1max, j1 = n->fast_outs(j1max); j1 < j1max; j1++) { 1345 out->push(n->fast_out(j1)); 1346 } 1347 uint max = out->size(); 1348 for (uint j = 0; j < max; j++) {// For all users 1349 Node *use = out->pop(); 1350 Block *buse = get_block_for_node(use); 1351 if( use->is_Phi() ) { 1352 for( uint k = 1; k < use->req(); k++ ) 1353 if( use->in(k) == n ) { 1354 Block* b = get_block_for_node(buse->pred(k)); 1355 Node *fixup = catch_cleanup_find_cloned_def(b, n, block, n_clone_idx); 1356 use->set_req(k, fixup); 1357 } 1358 } else { 1359 if (block == buse) { 1360 catch_cleanup_intra_block(use, n, block, beg, n_clone_idx); 1361 } else { 1362 catch_cleanup_inter_block(use, buse, n, block, n_clone_idx); 1363 } 1364 } 1365 } // End for all users 1366 1367 } // End of for all Nodes in cloned area 1368 1369 // Remove the now-dead cloned ops 1370 for(uint i3 = beg; i3 < end; i3++ ) { 1371 block->get_node(beg)->disconnect_inputs(NULL, C); 1372 block->remove_node(beg); 1373 } 1374 1375 // If the successor blocks have a CreateEx node, move it back to the top 1376 for(uint i4 = 0; i4 < block->_num_succs; i4++ ) { 1377 Block *sb = block->_succs[i4]; 1378 uint new_cnt = end - beg; 1379 // Remove any newly created, but dead, nodes. 1380 for( uint j = new_cnt; j > 0; j-- ) { 1381 Node *n = sb->get_node(j); 1382 if (n->outcnt() == 0 && 1383 (!n->is_Proj() || n->as_Proj()->in(0)->outcnt() == 1) ){ 1384 n->disconnect_inputs(NULL, C); 1385 sb->remove_node(j); 1386 new_cnt--; 1387 } 1388 } 1389 // If any newly created nodes remain, move the CreateEx node to the top 1390 if (new_cnt > 0) { 1391 Node *cex = sb->get_node(1+new_cnt); 1392 if( cex->is_Mach() && cex->as_Mach()->ideal_Opcode() == Op_CreateEx ) { 1393 sb->remove_node(1+new_cnt); 1394 sb->insert_node(cex, 1); 1395 } 1396 } 1397 } 1398 }