1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "opto/ad.hpp"
29 #include "opto/addnode.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/idealGraphPrinter.hpp"
32 #include "opto/matcher.hpp"
33 #include "opto/memnode.hpp"
34 #include "opto/movenode.hpp"
35 #include "opto/opcodes.hpp"
36 #include "opto/regmask.hpp"
37 #include "opto/rootnode.hpp"
38 #include "opto/runtime.hpp"
39 #include "opto/type.hpp"
40 #include "opto/vectornode.hpp"
41 #include "runtime/os.hpp"
42 #include "runtime/sharedRuntime.hpp"
43
44 OptoReg::Name OptoReg::c_frame_pointer;
45
46 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
47 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
48 RegMask Matcher::STACK_ONLY_mask;
49 RegMask Matcher::c_frame_ptr_mask;
50 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
51 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
52
53 //---------------------------Matcher-------------------------------------------
54 Matcher::Matcher()
55 : PhaseTransform( Phase::Ins_Select ),
56 #ifdef ASSERT
57 _old2new_map(C->comp_arena()),
58 _new2old_map(C->comp_arena()),
59 #endif
60 _shared_nodes(C->comp_arena()),
61 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
62 _swallowed(swallowed),
63 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
64 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
65 _must_clone(must_clone),
66 _register_save_policy(register_save_policy),
67 _c_reg_save_policy(c_reg_save_policy),
68 _register_save_type(register_save_type),
69 _ruleName(ruleName),
70 _allocation_started(false),
71 _states_arena(Chunk::medium_size),
72 _visited(&_states_arena),
73 _shared(&_states_arena),
74 _dontcare(&_states_arena) {
75 C->set_matcher(this);
76
77 idealreg2spillmask [Op_RegI] = NULL;
78 idealreg2spillmask [Op_RegN] = NULL;
79 idealreg2spillmask [Op_RegL] = NULL;
80 idealreg2spillmask [Op_RegF] = NULL;
81 idealreg2spillmask [Op_RegD] = NULL;
82 idealreg2spillmask [Op_RegP] = NULL;
83 idealreg2spillmask [Op_VecS] = NULL;
84 idealreg2spillmask [Op_VecD] = NULL;
85 idealreg2spillmask [Op_VecX] = NULL;
86 idealreg2spillmask [Op_VecY] = NULL;
87 idealreg2spillmask [Op_VecZ] = NULL;
88 idealreg2spillmask [Op_RegFlags] = NULL;
89
90 idealreg2debugmask [Op_RegI] = NULL;
91 idealreg2debugmask [Op_RegN] = NULL;
92 idealreg2debugmask [Op_RegL] = NULL;
93 idealreg2debugmask [Op_RegF] = NULL;
94 idealreg2debugmask [Op_RegD] = NULL;
95 idealreg2debugmask [Op_RegP] = NULL;
96 idealreg2debugmask [Op_VecS] = NULL;
97 idealreg2debugmask [Op_VecD] = NULL;
98 idealreg2debugmask [Op_VecX] = NULL;
99 idealreg2debugmask [Op_VecY] = NULL;
100 idealreg2debugmask [Op_VecZ] = NULL;
101 idealreg2debugmask [Op_RegFlags] = NULL;
102
103 idealreg2mhdebugmask[Op_RegI] = NULL;
104 idealreg2mhdebugmask[Op_RegN] = NULL;
105 idealreg2mhdebugmask[Op_RegL] = NULL;
106 idealreg2mhdebugmask[Op_RegF] = NULL;
107 idealreg2mhdebugmask[Op_RegD] = NULL;
108 idealreg2mhdebugmask[Op_RegP] = NULL;
109 idealreg2mhdebugmask[Op_VecS] = NULL;
110 idealreg2mhdebugmask[Op_VecD] = NULL;
111 idealreg2mhdebugmask[Op_VecX] = NULL;
112 idealreg2mhdebugmask[Op_VecY] = NULL;
113 idealreg2mhdebugmask[Op_VecZ] = NULL;
114 idealreg2mhdebugmask[Op_RegFlags] = NULL;
115
116 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
117 }
118
119 //------------------------------warp_incoming_stk_arg------------------------
120 // This warps a VMReg into an OptoReg::Name
121 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
122 OptoReg::Name warped;
123 if( reg->is_stack() ) { // Stack slot argument?
124 warped = OptoReg::add(_old_SP, reg->reg2stack() );
125 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
126 if( warped >= _in_arg_limit )
127 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
128 if (!RegMask::can_represent_arg(warped)) {
129 // the compiler cannot represent this method's calling sequence
130 C->record_method_not_compilable("unsupported incoming calling sequence");
131 return OptoReg::Bad;
132 }
133 return warped;
134 }
135 return OptoReg::as_OptoReg(reg);
136 }
137
138 //---------------------------compute_old_SP------------------------------------
139 OptoReg::Name Compile::compute_old_SP() {
140 int fixed = fixed_slots();
141 int preserve = in_preserve_stack_slots();
142 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
143 }
144
145
146
147 #ifdef ASSERT
148 void Matcher::verify_new_nodes_only(Node* xroot) {
149 // Make sure that the new graph only references new nodes
150 ResourceMark rm;
151 Unique_Node_List worklist;
152 VectorSet visited(Thread::current()->resource_area());
153 worklist.push(xroot);
154 while (worklist.size() > 0) {
155 Node* n = worklist.pop();
156 visited <<= n->_idx;
157 assert(C->node_arena()->contains(n), "dead node");
158 for (uint j = 0; j < n->req(); j++) {
159 Node* in = n->in(j);
160 if (in != NULL) {
161 assert(C->node_arena()->contains(in), "dead node");
162 if (!visited.test(in->_idx)) {
163 worklist.push(in);
164 }
165 }
166 }
167 }
168 }
169 #endif
170
171 // Array of RegMask, one per returned values (value type instances can
172 // be returned as multiple return values, one per field)
173 RegMask* Matcher::return_values_mask(const TypeTuple *range) {
174 uint cnt = range->cnt() - TypeFunc::Parms;
175 if (cnt == 0) {
176 return NULL;
177 }
178 RegMask* mask = NEW_RESOURCE_ARRAY(RegMask, cnt);
179
180 if (!ValueTypeReturnedAsFields) {
181 // Get ideal-register return type
182 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
183 // Get machine return register
184 OptoRegPair regs = return_value(ireg, false);
185
186 // And mask for same
187 mask[0].Clear();
188 mask[0].Insert(regs.first());
189 if (OptoReg::is_valid(regs.second())) {
190 mask[0].Insert(regs.second());
191 }
192 } else {
193 BasicType *sig_bt = NEW_RESOURCE_ARRAY(BasicType, cnt);
194 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY(VMRegPair, cnt);
195
196 for (uint i = 0; i < cnt; i++) {
197 sig_bt[i] = range->field_at(i+TypeFunc::Parms)->basic_type();
198 }
199
200 int regs = SharedRuntime::java_return_convention(sig_bt, vm_parm_regs, cnt);
201 assert(regs > 0, "should have been tested during graph construction");
202 for (uint i = 0; i < cnt; i++) {
203 mask[i].Clear();
204
205 OptoReg::Name reg1 = OptoReg::as_OptoReg(vm_parm_regs[i].first());
206 if (OptoReg::is_valid(reg1)) {
207 mask[i].Insert(reg1);
208 }
209 OptoReg::Name reg2 = OptoReg::as_OptoReg(vm_parm_regs[i].second());
210 if (OptoReg::is_valid(reg2)) {
211 mask[i].Insert(reg2);
212 }
213 }
214 }
215 return mask;
216 }
217
218 //---------------------------match---------------------------------------------
219 void Matcher::match( ) {
220 if( MaxLabelRootDepth < 100 ) { // Too small?
221 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
222 MaxLabelRootDepth = 100;
223 }
224 // One-time initialization of some register masks.
225 init_spill_mask( C->root()->in(1) );
226 _return_addr_mask = return_addr();
227 #ifdef _LP64
228 // Pointers take 2 slots in 64-bit land
229 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
230 #endif
231
232 // Map Java-signature return types into return register-value
233 // machine registers.
234 const TypeTuple *range = C->tf()->range_cc();
235 _return_values_mask = return_values_mask(range);
236
237 // ---------------
238 // Frame Layout
239
240 // Need the method signature to determine the incoming argument types,
241 // because the types determine which registers the incoming arguments are
242 // in, and this affects the matched code.
243 const TypeTuple *domain = C->tf()->domain_cc();
244 uint argcnt = domain->cnt() - TypeFunc::Parms;
245 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
246 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
247 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
248 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
249 uint i;
250 for( i = 0; i<argcnt; i++ ) {
251 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
252 }
253
254 // Pass array of ideal registers and length to USER code (from the AD file)
255 // that will convert this to an array of register numbers.
256 const StartNode *start = C->start();
257 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
258 #ifdef ASSERT
259 // Sanity check users' calling convention. Real handy while trying to
260 // get the initial port correct.
261 { for (uint i = 0; i<argcnt; i++) {
262 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
263 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
264 _parm_regs[i].set_bad();
265 continue;
266 }
267 VMReg parm_reg = vm_parm_regs[i].first();
268 assert(parm_reg->is_valid(), "invalid arg?");
269 if (parm_reg->is_reg()) {
270 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
271 assert(can_be_java_arg(opto_parm_reg) ||
272 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
273 opto_parm_reg == inline_cache_reg(),
274 "parameters in register must be preserved by runtime stubs");
275 }
276 for (uint j = 0; j < i; j++) {
277 assert(parm_reg != vm_parm_regs[j].first(),
278 "calling conv. must produce distinct regs");
279 }
280 }
281 }
282 #endif
283
284 // Do some initial frame layout.
285
286 // Compute the old incoming SP (may be called FP) as
287 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
288 _old_SP = C->compute_old_SP();
289 assert( is_even(_old_SP), "must be even" );
290
291 // Compute highest incoming stack argument as
292 // _old_SP + out_preserve_stack_slots + incoming argument size.
293 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
294 assert( is_even(_in_arg_limit), "out_preserve must be even" );
295 for( i = 0; i < argcnt; i++ ) {
296 // Permit args to have no register
297 _calling_convention_mask[i].Clear();
298 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
299 continue;
300 }
301 // calling_convention returns stack arguments as a count of
302 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
303 // the allocators point of view, taking into account all the
304 // preserve area, locks & pad2.
305
306 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
307 if( OptoReg::is_valid(reg1))
308 _calling_convention_mask[i].Insert(reg1);
309
310 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
311 if( OptoReg::is_valid(reg2))
312 _calling_convention_mask[i].Insert(reg2);
313
314 // Saved biased stack-slot register number
315 _parm_regs[i].set_pair(reg2, reg1);
316 }
317
318 // Finally, make sure the incoming arguments take up an even number of
319 // words, in case the arguments or locals need to contain doubleword stack
320 // slots. The rest of the system assumes that stack slot pairs (in
321 // particular, in the spill area) which look aligned will in fact be
322 // aligned relative to the stack pointer in the target machine. Double
323 // stack slots will always be allocated aligned.
324 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
325
326 // Compute highest outgoing stack argument as
327 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
328 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
329 assert( is_even(_out_arg_limit), "out_preserve must be even" );
330
331 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
332 // the compiler cannot represent this method's calling sequence
333 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
334 }
335
336 if (C->failing()) return; // bailed out on incoming arg failure
337
338 // ---------------
339 // Collect roots of matcher trees. Every node for which
340 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
341 // can be a valid interior of some tree.
342 find_shared( C->root() );
343 find_shared( C->top() );
344
345 C->print_method(PHASE_BEFORE_MATCHING);
346
347 // Create new ideal node ConP #NULL even if it does exist in old space
348 // to avoid false sharing if the corresponding mach node is not used.
349 // The corresponding mach node is only used in rare cases for derived
350 // pointers.
351 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
352
353 // Swap out to old-space; emptying new-space
354 Arena *old = C->node_arena()->move_contents(C->old_arena());
355
356 // Save debug and profile information for nodes in old space:
357 _old_node_note_array = C->node_note_array();
358 if (_old_node_note_array != NULL) {
359 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
360 (C->comp_arena(), _old_node_note_array->length(),
361 0, NULL));
362 }
363
364 // Pre-size the new_node table to avoid the need for range checks.
365 grow_new_node_array(C->unique());
366
367 // Reset node counter so MachNodes start with _idx at 0
368 int live_nodes = C->live_nodes();
369 C->set_unique(0);
370 C->reset_dead_node_list();
371
372 // Recursively match trees from old space into new space.
373 // Correct leaves of new-space Nodes; they point to old-space.
374 _visited.Clear(); // Clear visit bits for xform call
375 C->set_cached_top_node(xform( C->top(), live_nodes ));
376 if (!C->failing()) {
377 Node* xroot = xform( C->root(), 1 );
378 if (xroot == NULL) {
379 Matcher::soft_match_failure(); // recursive matching process failed
380 C->record_method_not_compilable("instruction match failed");
381 } else {
382 // During matching shared constants were attached to C->root()
383 // because xroot wasn't available yet, so transfer the uses to
384 // the xroot.
385 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
386 Node* n = C->root()->fast_out(j);
387 if (C->node_arena()->contains(n)) {
388 assert(n->in(0) == C->root(), "should be control user");
389 n->set_req(0, xroot);
390 --j;
391 --jmax;
392 }
393 }
394
395 // Generate new mach node for ConP #NULL
396 assert(new_ideal_null != NULL, "sanity");
397 _mach_null = match_tree(new_ideal_null);
398 // Don't set control, it will confuse GCM since there are no uses.
399 // The control will be set when this node is used first time
400 // in find_base_for_derived().
401 assert(_mach_null != NULL, "");
402
403 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
404
405 #ifdef ASSERT
406 verify_new_nodes_only(xroot);
407 #endif
408 }
409 }
410 if (C->top() == NULL || C->root() == NULL) {
411 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
412 }
413 if (C->failing()) {
414 // delete old;
415 old->destruct_contents();
416 return;
417 }
418 assert( C->top(), "" );
419 assert( C->root(), "" );
420 validate_null_checks();
421
422 // Now smoke old-space
423 NOT_DEBUG( old->destruct_contents() );
424
425 // ------------------------
426 // Set up save-on-entry registers
427 Fixup_Save_On_Entry( );
428 }
429
430
431 //------------------------------Fixup_Save_On_Entry----------------------------
432 // The stated purpose of this routine is to take care of save-on-entry
433 // registers. However, the overall goal of the Match phase is to convert into
434 // machine-specific instructions which have RegMasks to guide allocation.
435 // So what this procedure really does is put a valid RegMask on each input
436 // to the machine-specific variations of all Return, TailCall and Halt
437 // instructions. It also adds edgs to define the save-on-entry values (and of
438 // course gives them a mask).
439
440 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
441 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
442 // Do all the pre-defined register masks
443 rms[TypeFunc::Control ] = RegMask::Empty;
444 rms[TypeFunc::I_O ] = RegMask::Empty;
445 rms[TypeFunc::Memory ] = RegMask::Empty;
446 rms[TypeFunc::ReturnAdr] = ret_adr;
447 rms[TypeFunc::FramePtr ] = fp;
448 return rms;
449 }
450
451 //---------------------------init_first_stack_mask-----------------------------
452 // Create the initial stack mask used by values spilling to the stack.
453 // Disallow any debug info in outgoing argument areas by setting the
454 // initial mask accordingly.
455 void Matcher::init_first_stack_mask() {
456
457 // Allocate storage for spill masks as masks for the appropriate load type.
458 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
459
460 idealreg2spillmask [Op_RegN] = &rms[0];
461 idealreg2spillmask [Op_RegI] = &rms[1];
462 idealreg2spillmask [Op_RegL] = &rms[2];
463 idealreg2spillmask [Op_RegF] = &rms[3];
464 idealreg2spillmask [Op_RegD] = &rms[4];
465 idealreg2spillmask [Op_RegP] = &rms[5];
466
467 idealreg2debugmask [Op_RegN] = &rms[6];
468 idealreg2debugmask [Op_RegI] = &rms[7];
469 idealreg2debugmask [Op_RegL] = &rms[8];
470 idealreg2debugmask [Op_RegF] = &rms[9];
471 idealreg2debugmask [Op_RegD] = &rms[10];
472 idealreg2debugmask [Op_RegP] = &rms[11];
473
474 idealreg2mhdebugmask[Op_RegN] = &rms[12];
475 idealreg2mhdebugmask[Op_RegI] = &rms[13];
476 idealreg2mhdebugmask[Op_RegL] = &rms[14];
477 idealreg2mhdebugmask[Op_RegF] = &rms[15];
478 idealreg2mhdebugmask[Op_RegD] = &rms[16];
479 idealreg2mhdebugmask[Op_RegP] = &rms[17];
480
481 idealreg2spillmask [Op_VecS] = &rms[18];
482 idealreg2spillmask [Op_VecD] = &rms[19];
483 idealreg2spillmask [Op_VecX] = &rms[20];
484 idealreg2spillmask [Op_VecY] = &rms[21];
485 idealreg2spillmask [Op_VecZ] = &rms[22];
486
487 OptoReg::Name i;
488
489 // At first, start with the empty mask
490 C->FIRST_STACK_mask().Clear();
491
492 // Add in the incoming argument area
493 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
494 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
495 C->FIRST_STACK_mask().Insert(i);
496 }
497 // Add in all bits past the outgoing argument area
498 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
499 "must be able to represent all call arguments in reg mask");
500 OptoReg::Name init = _out_arg_limit;
501 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
502 C->FIRST_STACK_mask().Insert(i);
503 }
504 // Finally, set the "infinite stack" bit.
505 C->FIRST_STACK_mask().set_AllStack();
506
507 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
508 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
509 // Keep spill masks aligned.
510 aligned_stack_mask.clear_to_pairs();
511 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
512
513 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
514 #ifdef _LP64
515 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
516 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
517 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
518 #else
519 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
520 #endif
521 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
522 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
523 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
524 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
525 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
526 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
527 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
528 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
529
530 if (Matcher::vector_size_supported(T_BYTE,4)) {
531 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
532 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
533 }
534 if (Matcher::vector_size_supported(T_FLOAT,2)) {
535 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
536 // RA guarantees such alignment since it is needed for Double and Long values.
537 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
538 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
539 }
540 if (Matcher::vector_size_supported(T_FLOAT,4)) {
541 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
542 //
543 // RA can use input arguments stack slots for spills but until RA
544 // we don't know frame size and offset of input arg stack slots.
545 //
546 // Exclude last input arg stack slots to avoid spilling vectors there
547 // otherwise vector spills could stomp over stack slots in caller frame.
548 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
549 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
550 aligned_stack_mask.Remove(in);
551 in = OptoReg::add(in, -1);
552 }
553 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
554 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
555 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
556 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
557 }
558 if (Matcher::vector_size_supported(T_FLOAT,8)) {
559 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
560 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
561 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
562 aligned_stack_mask.Remove(in);
563 in = OptoReg::add(in, -1);
564 }
565 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
566 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
567 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
568 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
569 }
570 if (Matcher::vector_size_supported(T_FLOAT,16)) {
571 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
572 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
573 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
574 aligned_stack_mask.Remove(in);
575 in = OptoReg::add(in, -1);
576 }
577 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
578 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
579 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
580 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
581 }
582 if (UseFPUForSpilling) {
583 // This mask logic assumes that the spill operations are
584 // symmetric and that the registers involved are the same size.
585 // On sparc for instance we may have to use 64 bit moves will
586 // kill 2 registers when used with F0-F31.
587 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
588 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
589 #ifdef _LP64
590 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
591 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
592 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
593 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
594 #else
595 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
596 #ifdef ARM
597 // ARM has support for moving 64bit values between a pair of
598 // integer registers and a double register
599 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
600 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
601 #endif
602 #endif
603 }
604
605 // Make up debug masks. Any spill slot plus callee-save registers.
606 // Caller-save registers are assumed to be trashable by the various
607 // inline-cache fixup routines.
608 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
609 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
610 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
611 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
612 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
613 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
614
615 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
616 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
617 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
618 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
619 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
620 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
621
622 // Prevent stub compilations from attempting to reference
623 // callee-saved registers from debug info
624 bool exclude_soe = !Compile::current()->is_method_compilation();
625
626 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
627 // registers the caller has to save do not work
628 if( _register_save_policy[i] == 'C' ||
629 _register_save_policy[i] == 'A' ||
630 (_register_save_policy[i] == 'E' && exclude_soe) ) {
631 idealreg2debugmask [Op_RegN]->Remove(i);
632 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
633 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
634 idealreg2debugmask [Op_RegF]->Remove(i); // masks
635 idealreg2debugmask [Op_RegD]->Remove(i);
636 idealreg2debugmask [Op_RegP]->Remove(i);
637
638 idealreg2mhdebugmask[Op_RegN]->Remove(i);
639 idealreg2mhdebugmask[Op_RegI]->Remove(i);
640 idealreg2mhdebugmask[Op_RegL]->Remove(i);
641 idealreg2mhdebugmask[Op_RegF]->Remove(i);
642 idealreg2mhdebugmask[Op_RegD]->Remove(i);
643 idealreg2mhdebugmask[Op_RegP]->Remove(i);
644 }
645 }
646
647 // Subtract the register we use to save the SP for MethodHandle
648 // invokes to from the debug mask.
649 const RegMask save_mask = method_handle_invoke_SP_save_mask();
650 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
651 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
652 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
653 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
654 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
655 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
656 }
657
658 //---------------------------is_save_on_entry----------------------------------
659 bool Matcher::is_save_on_entry( int reg ) {
660 return
661 _register_save_policy[reg] == 'E' ||
662 _register_save_policy[reg] == 'A' || // Save-on-entry register?
663 // Also save argument registers in the trampolining stubs
664 (C->save_argument_registers() && is_spillable_arg(reg));
665 }
666
667 //---------------------------Fixup_Save_On_Entry-------------------------------
668 void Matcher::Fixup_Save_On_Entry( ) {
669 init_first_stack_mask();
670
671 Node *root = C->root(); // Short name for root
672 // Count number of save-on-entry registers.
673 uint soe_cnt = number_of_saved_registers();
674 uint i;
675
676 // Find the procedure Start Node
677 StartNode *start = C->start();
678 assert( start, "Expect a start node" );
679
680 // Save argument registers in the trampolining stubs
681 if( C->save_argument_registers() )
682 for( i = 0; i < _last_Mach_Reg; i++ )
683 if( is_spillable_arg(i) )
684 soe_cnt++;
685
686 // Input RegMask array shared by all Returns.
687 // The type for doubles and longs has a count of 2, but
688 // there is only 1 returned value
689 uint ret_edge_cnt = C->tf()->range_cc()->cnt();
690 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
691 for (i = TypeFunc::Parms; i < ret_edge_cnt; i++) {
692 ret_rms[i] = _return_values_mask[i-TypeFunc::Parms];
693 }
694
695 // Input RegMask array shared by all Rethrows.
696 uint reth_edge_cnt = TypeFunc::Parms+1;
697 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
698 // Rethrow takes exception oop only, but in the argument 0 slot.
699 OptoReg::Name reg = find_receiver(false);
700 if (reg >= 0) {
701 reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
702 #ifdef _LP64
703 // Need two slots for ptrs in 64-bit land
704 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
705 #endif
706 }
707
708 // Input RegMask array shared by all TailCalls
709 uint tail_call_edge_cnt = TypeFunc::Parms+2;
710 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
711
712 // Input RegMask array shared by all TailJumps
713 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
714 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
715
716 // TailCalls have 2 returned values (target & moop), whose masks come
717 // from the usual MachNode/MachOper mechanism. Find a sample
718 // TailCall to extract these masks and put the correct masks into
719 // the tail_call_rms array.
720 for( i=1; i < root->req(); i++ ) {
721 MachReturnNode *m = root->in(i)->as_MachReturn();
722 if( m->ideal_Opcode() == Op_TailCall ) {
723 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
724 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
725 break;
726 }
727 }
728
729 // TailJumps have 2 returned values (target & ex_oop), whose masks come
730 // from the usual MachNode/MachOper mechanism. Find a sample
731 // TailJump to extract these masks and put the correct masks into
732 // the tail_jump_rms array.
733 for( i=1; i < root->req(); i++ ) {
734 MachReturnNode *m = root->in(i)->as_MachReturn();
735 if( m->ideal_Opcode() == Op_TailJump ) {
736 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
737 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
738 break;
739 }
740 }
741
742 // Input RegMask array shared by all Halts
743 uint halt_edge_cnt = TypeFunc::Parms;
744 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
745
746 // Capture the return input masks into each exit flavor
747 for( i=1; i < root->req(); i++ ) {
748 MachReturnNode *exit = root->in(i)->as_MachReturn();
749 switch( exit->ideal_Opcode() ) {
750 case Op_Return : exit->_in_rms = ret_rms; break;
751 case Op_Rethrow : exit->_in_rms = reth_rms; break;
752 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
753 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
754 case Op_Halt : exit->_in_rms = halt_rms; break;
755 default : ShouldNotReachHere();
756 }
757 }
758
759 // Next unused projection number from Start.
760 int proj_cnt = C->tf()->domain_cc()->cnt();
761
762 // Do all the save-on-entry registers. Make projections from Start for
763 // them, and give them a use at the exit points. To the allocator, they
764 // look like incoming register arguments.
765 for( i = 0; i < _last_Mach_Reg; i++ ) {
766 if( is_save_on_entry(i) ) {
767
768 // Add the save-on-entry to the mask array
769 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
770 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
771 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
772 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
773 // Halts need the SOE registers, but only in the stack as debug info.
774 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
775 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
776
777 Node *mproj;
778
779 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
780 // into a single RegD.
781 if( (i&1) == 0 &&
782 _register_save_type[i ] == Op_RegF &&
783 _register_save_type[i+1] == Op_RegF &&
784 is_save_on_entry(i+1) ) {
785 // Add other bit for double
786 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
787 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
788 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
789 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
790 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
791 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
792 proj_cnt += 2; // Skip 2 for doubles
793 }
794 else if( (i&1) == 1 && // Else check for high half of double
795 _register_save_type[i-1] == Op_RegF &&
796 _register_save_type[i ] == Op_RegF &&
797 is_save_on_entry(i-1) ) {
798 ret_rms [ ret_edge_cnt] = RegMask::Empty;
799 reth_rms [ reth_edge_cnt] = RegMask::Empty;
800 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
801 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
802 halt_rms [ halt_edge_cnt] = RegMask::Empty;
803 mproj = C->top();
804 }
805 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
806 // into a single RegL.
807 else if( (i&1) == 0 &&
808 _register_save_type[i ] == Op_RegI &&
809 _register_save_type[i+1] == Op_RegI &&
810 is_save_on_entry(i+1) ) {
811 // Add other bit for long
812 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
813 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
814 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
815 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
816 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
817 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
818 proj_cnt += 2; // Skip 2 for longs
819 }
820 else if( (i&1) == 1 && // Else check for high half of long
821 _register_save_type[i-1] == Op_RegI &&
822 _register_save_type[i ] == Op_RegI &&
823 is_save_on_entry(i-1) ) {
824 ret_rms [ ret_edge_cnt] = RegMask::Empty;
825 reth_rms [ reth_edge_cnt] = RegMask::Empty;
826 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
827 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
828 halt_rms [ halt_edge_cnt] = RegMask::Empty;
829 mproj = C->top();
830 } else {
831 // Make a projection for it off the Start
832 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
833 }
834
835 ret_edge_cnt ++;
836 reth_edge_cnt ++;
837 tail_call_edge_cnt ++;
838 tail_jump_edge_cnt ++;
839 halt_edge_cnt ++;
840
841 // Add a use of the SOE register to all exit paths
842 for( uint j=1; j < root->req(); j++ )
843 root->in(j)->add_req(mproj);
844 } // End of if a save-on-entry register
845 } // End of for all machine registers
846 }
847
848 //------------------------------init_spill_mask--------------------------------
849 void Matcher::init_spill_mask( Node *ret ) {
850 if( idealreg2regmask[Op_RegI] ) return; // One time only init
851
852 OptoReg::c_frame_pointer = c_frame_pointer();
853 c_frame_ptr_mask = c_frame_pointer();
854 #ifdef _LP64
855 // pointers are twice as big
856 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
857 #endif
858
859 // Start at OptoReg::stack0()
860 STACK_ONLY_mask.Clear();
861 OptoReg::Name init = OptoReg::stack2reg(0);
862 // STACK_ONLY_mask is all stack bits
863 OptoReg::Name i;
864 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
865 STACK_ONLY_mask.Insert(i);
866 // Also set the "infinite stack" bit.
867 STACK_ONLY_mask.set_AllStack();
868
869 // Copy the register names over into the shared world
870 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
871 // SharedInfo::regName[i] = regName[i];
872 // Handy RegMasks per machine register
873 mreg2regmask[i].Insert(i);
874 }
875
876 // Grab the Frame Pointer
877 Node *fp = ret->in(TypeFunc::FramePtr);
878 Node *mem = ret->in(TypeFunc::Memory);
879 const TypePtr* atp = TypePtr::BOTTOM;
880 // Share frame pointer while making spill ops
881 set_shared(fp);
882
883 // Compute generic short-offset Loads
884 #ifdef _LP64
885 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
886 #endif
887 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
888 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
889 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
890 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
891 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
892 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
893 spillD != NULL && spillP != NULL, "");
894 // Get the ADLC notion of the right regmask, for each basic type.
895 #ifdef _LP64
896 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
897 #endif
898 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
899 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
900 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
901 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
902 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
903
904 // Vector regmasks.
905 if (Matcher::vector_size_supported(T_BYTE,4)) {
906 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
907 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
908 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
909 }
910 if (Matcher::vector_size_supported(T_FLOAT,2)) {
911 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
912 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
913 }
914 if (Matcher::vector_size_supported(T_FLOAT,4)) {
915 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
916 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
917 }
918 if (Matcher::vector_size_supported(T_FLOAT,8)) {
919 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
920 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
921 }
922 if (Matcher::vector_size_supported(T_FLOAT,16)) {
923 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
924 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
925 }
926 }
927
928 #ifdef ASSERT
929 static void match_alias_type(Compile* C, Node* n, Node* m) {
930 if (!VerifyAliases) return; // do not go looking for trouble by default
931 const TypePtr* nat = n->adr_type();
932 const TypePtr* mat = m->adr_type();
933 int nidx = C->get_alias_index(nat);
934 int midx = C->get_alias_index(mat);
935 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
936 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
937 for (uint i = 1; i < n->req(); i++) {
938 Node* n1 = n->in(i);
939 const TypePtr* n1at = n1->adr_type();
940 if (n1at != NULL) {
941 nat = n1at;
942 nidx = C->get_alias_index(n1at);
943 }
944 }
945 }
946 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
947 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
948 switch (n->Opcode()) {
949 case Op_PrefetchAllocation:
950 nidx = Compile::AliasIdxRaw;
951 nat = TypeRawPtr::BOTTOM;
952 break;
953 }
954 }
955 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
956 switch (n->Opcode()) {
957 case Op_ClearArray:
958 midx = Compile::AliasIdxRaw;
959 mat = TypeRawPtr::BOTTOM;
960 break;
961 }
962 }
963 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
964 switch (n->Opcode()) {
965 case Op_Return:
966 case Op_Rethrow:
967 case Op_Halt:
968 case Op_TailCall:
969 case Op_TailJump:
970 nidx = Compile::AliasIdxBot;
971 nat = TypePtr::BOTTOM;
972 break;
973 }
974 }
975 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
976 switch (n->Opcode()) {
977 case Op_StrComp:
978 case Op_StrEquals:
979 case Op_StrIndexOf:
980 case Op_StrIndexOfChar:
981 case Op_AryEq:
982 case Op_HasNegatives:
983 case Op_MemBarVolatile:
984 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
985 case Op_StrInflatedCopy:
986 case Op_StrCompressedCopy:
987 case Op_OnSpinWait:
988 case Op_EncodeISOArray:
989 nidx = Compile::AliasIdxTop;
990 nat = NULL;
991 break;
992 }
993 }
994 if (nidx != midx) {
995 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
996 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
997 n->dump();
998 m->dump();
999 }
1000 assert(C->subsume_loads() && C->must_alias(nat, midx),
1001 "must not lose alias info when matching");
1002 }
1003 }
1004 #endif
1005
1006 //------------------------------xform------------------------------------------
1007 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1008 // Node in new-space. Given a new-space Node, recursively walk his children.
1009 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1010 Node *Matcher::xform( Node *n, int max_stack ) {
1011 // Use one stack to keep both: child's node/state and parent's node/index
1012 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1013 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
1014
1015 while (mstack.is_nonempty()) {
1016 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1017 if (C->failing()) return NULL;
1018 n = mstack.node(); // Leave node on stack
1019 Node_State nstate = mstack.state();
1020 if (nstate == Visit) {
1021 mstack.set_state(Post_Visit);
1022 Node *oldn = n;
1023 // Old-space or new-space check
1024 if (!C->node_arena()->contains(n)) {
1025 // Old space!
1026 Node* m;
1027 if (has_new_node(n)) { // Not yet Label/Reduced
1028 m = new_node(n);
1029 } else {
1030 if (!is_dontcare(n)) { // Matcher can match this guy
1031 // Calls match special. They match alone with no children.
1032 // Their children, the incoming arguments, match normally.
1033 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1034 if (C->failing()) return NULL;
1035 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1036 } else { // Nothing the matcher cares about
1037 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1038 // Convert to machine-dependent projection
1039 RegMask* mask = NULL;
1040 if (n->in(0)->is_Call()) {
1041 mask = return_values_mask(n->in(0)->as_Call()->tf()->range_cc());
1042 }
1043 m = n->in(0)->as_Multi()->match(n->as_Proj(), this, mask);
1044 #ifdef ASSERT
1045 _new2old_map.map(m->_idx, n);
1046 #endif
1047 if (m->in(0) != NULL) // m might be top
1048 collect_null_checks(m, n);
1049 } else { // Else just a regular 'ol guy
1050 m = n->clone(); // So just clone into new-space
1051 #ifdef ASSERT
1052 _new2old_map.map(m->_idx, n);
1053 #endif
1054 // Def-Use edges will be added incrementally as Uses
1055 // of this node are matched.
1056 assert(m->outcnt() == 0, "no Uses of this clone yet");
1057 }
1058 }
1059
1060 set_new_node(n, m); // Map old to new
1061 if (_old_node_note_array != NULL) {
1062 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1063 n->_idx);
1064 C->set_node_notes_at(m->_idx, nn);
1065 }
1066 debug_only(match_alias_type(C, n, m));
1067 }
1068 n = m; // n is now a new-space node
1069 mstack.set_node(n);
1070 }
1071
1072 // New space!
1073 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1074
1075 int i;
1076 // Put precedence edges on stack first (match them last).
1077 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1078 Node *m = oldn->in(i);
1079 if (m == NULL) break;
1080 // set -1 to call add_prec() instead of set_req() during Step1
1081 mstack.push(m, Visit, n, -1);
1082 }
1083
1084 // Handle precedence edges for interior nodes
1085 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1086 Node *m = n->in(i);
1087 if (m == NULL || C->node_arena()->contains(m)) continue;
1088 n->rm_prec(i);
1089 // set -1 to call add_prec() instead of set_req() during Step1
1090 mstack.push(m, Visit, n, -1);
1091 }
1092
1093 // For constant debug info, I'd rather have unmatched constants.
1094 int cnt = n->req();
1095 JVMState* jvms = n->jvms();
1096 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1097
1098 // Now do only debug info. Clone constants rather than matching.
1099 // Constants are represented directly in the debug info without
1100 // the need for executable machine instructions.
1101 // Monitor boxes are also represented directly.
1102 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1103 Node *m = n->in(i); // Get input
1104 int op = m->Opcode();
1105 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1106 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1107 op == Op_ConF || op == Op_ConD || op == Op_ConL
1108 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1109 ) {
1110 m = m->clone();
1111 #ifdef ASSERT
1112 _new2old_map.map(m->_idx, n);
1113 #endif
1114 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1115 mstack.push(m->in(0), Visit, m, 0);
1116 } else {
1117 mstack.push(m, Visit, n, i);
1118 }
1119 }
1120
1121 // And now walk his children, and convert his inputs to new-space.
1122 for( ; i >= 0; --i ) { // For all normal inputs do
1123 Node *m = n->in(i); // Get input
1124 if(m != NULL)
1125 mstack.push(m, Visit, n, i);
1126 }
1127
1128 }
1129 else if (nstate == Post_Visit) {
1130 // Set xformed input
1131 Node *p = mstack.parent();
1132 if (p != NULL) { // root doesn't have parent
1133 int i = (int)mstack.index();
1134 if (i >= 0)
1135 p->set_req(i, n); // required input
1136 else if (i == -1)
1137 p->add_prec(n); // precedence input
1138 else
1139 ShouldNotReachHere();
1140 }
1141 mstack.pop(); // remove processed node from stack
1142 }
1143 else {
1144 ShouldNotReachHere();
1145 }
1146 } // while (mstack.is_nonempty())
1147 return n; // Return new-space Node
1148 }
1149
1150 //------------------------------warp_outgoing_stk_arg------------------------
1151 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1152 // Convert outgoing argument location to a pre-biased stack offset
1153 if (reg->is_stack()) {
1154 OptoReg::Name warped = reg->reg2stack();
1155 // Adjust the stack slot offset to be the register number used
1156 // by the allocator.
1157 warped = OptoReg::add(begin_out_arg_area, warped);
1158 // Keep track of the largest numbered stack slot used for an arg.
1159 // Largest used slot per call-site indicates the amount of stack
1160 // that is killed by the call.
1161 if( warped >= out_arg_limit_per_call )
1162 out_arg_limit_per_call = OptoReg::add(warped,1);
1163 if (!RegMask::can_represent_arg(warped)) {
1164 C->record_method_not_compilable("unsupported calling sequence");
1165 return OptoReg::Bad;
1166 }
1167 return warped;
1168 }
1169 return OptoReg::as_OptoReg(reg);
1170 }
1171
1172
1173 //------------------------------match_sfpt-------------------------------------
1174 // Helper function to match call instructions. Calls match special.
1175 // They match alone with no children. Their children, the incoming
1176 // arguments, match normally.
1177 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1178 MachSafePointNode *msfpt = NULL;
1179 MachCallNode *mcall = NULL;
1180 uint cnt;
1181 // Split out case for SafePoint vs Call
1182 CallNode *call;
1183 const TypeTuple *domain;
1184 ciMethod* method = NULL;
1185 bool is_method_handle_invoke = false; // for special kill effects
1186 if( sfpt->is_Call() ) {
1187 call = sfpt->as_Call();
1188 domain = call->tf()->domain_cc();
1189 cnt = domain->cnt();
1190
1191 // Match just the call, nothing else
1192 MachNode *m = match_tree(call);
1193 if (C->failing()) return NULL;
1194 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1195
1196 // Copy data from the Ideal SafePoint to the machine version
1197 mcall = m->as_MachCall();
1198
1199 mcall->set_tf( call->tf());
1200 mcall->set_entry_point(call->entry_point());
1201 mcall->set_cnt( call->cnt());
1202
1203 if( mcall->is_MachCallJava() ) {
1204 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1205 const CallJavaNode *call_java = call->as_CallJava();
1206 method = call_java->method();
1207 mcall_java->_method = method;
1208 mcall_java->_bci = call_java->_bci;
1209 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1210 is_method_handle_invoke = call_java->is_method_handle_invoke();
1211 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1212 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1213 if (is_method_handle_invoke) {
1214 C->set_has_method_handle_invokes(true);
1215 }
1216 if( mcall_java->is_MachCallStaticJava() )
1217 mcall_java->as_MachCallStaticJava()->_name =
1218 call_java->as_CallStaticJava()->_name;
1219 if( mcall_java->is_MachCallDynamicJava() )
1220 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1221 call_java->as_CallDynamicJava()->_vtable_index;
1222 }
1223 else if( mcall->is_MachCallRuntime() ) {
1224 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1225 }
1226 msfpt = mcall;
1227 }
1228 // This is a non-call safepoint
1229 else {
1230 call = NULL;
1231 domain = NULL;
1232 MachNode *mn = match_tree(sfpt);
1233 if (C->failing()) return NULL;
1234 msfpt = mn->as_MachSafePoint();
1235 cnt = TypeFunc::Parms;
1236 }
1237
1238 // Advertise the correct memory effects (for anti-dependence computation).
1239 msfpt->set_adr_type(sfpt->adr_type());
1240
1241 // Allocate a private array of RegMasks. These RegMasks are not shared.
1242 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1243 // Empty them all.
1244 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1245
1246 // Do all the pre-defined non-Empty register masks
1247 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1248 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1249
1250 // Place first outgoing argument can possibly be put.
1251 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1252 assert( is_even(begin_out_arg_area), "" );
1253 // Compute max outgoing register number per call site.
1254 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1255 // Calls to C may hammer extra stack slots above and beyond any arguments.
1256 // These are usually backing store for register arguments for varargs.
1257 if( call != NULL && call->is_CallRuntime() )
1258 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1259
1260
1261 // Do the normal argument list (parameters) register masks
1262 int argcnt = cnt - TypeFunc::Parms;
1263 if( argcnt > 0 ) { // Skip it all if we have no args
1264 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1265 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1266 int i;
1267 for( i = 0; i < argcnt; i++ ) {
1268 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1269 }
1270 // V-call to pick proper calling convention
1271 call->calling_convention( sig_bt, parm_regs, argcnt );
1272
1273 #ifdef ASSERT
1274 // Sanity check users' calling convention. Really handy during
1275 // the initial porting effort. Fairly expensive otherwise.
1276 { for (int i = 0; i<argcnt; i++) {
1277 if( !parm_regs[i].first()->is_valid() &&
1278 !parm_regs[i].second()->is_valid() ) continue;
1279 VMReg reg1 = parm_regs[i].first();
1280 VMReg reg2 = parm_regs[i].second();
1281 for (int j = 0; j < i; j++) {
1282 if( !parm_regs[j].first()->is_valid() &&
1283 !parm_regs[j].second()->is_valid() ) continue;
1284 VMReg reg3 = parm_regs[j].first();
1285 VMReg reg4 = parm_regs[j].second();
1286 if( !reg1->is_valid() ) {
1287 assert( !reg2->is_valid(), "valid halvsies" );
1288 } else if( !reg3->is_valid() ) {
1289 assert( !reg4->is_valid(), "valid halvsies" );
1290 } else {
1291 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1292 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1293 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1294 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1295 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1296 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1297 }
1298 }
1299 }
1300 }
1301 #endif
1302
1303 // Visit each argument. Compute its outgoing register mask.
1304 // Return results now can have 2 bits returned.
1305 // Compute max over all outgoing arguments both per call-site
1306 // and over the entire method.
1307 for( i = 0; i < argcnt; i++ ) {
1308 // Address of incoming argument mask to fill in
1309 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1310 if( !parm_regs[i].first()->is_valid() &&
1311 !parm_regs[i].second()->is_valid() ) {
1312 continue; // Avoid Halves
1313 }
1314 // Grab first register, adjust stack slots and insert in mask.
1315 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1316 if (OptoReg::is_valid(reg1)) {
1317 rm->Insert( reg1 );
1318 }
1319 // Grab second register (if any), adjust stack slots and insert in mask.
1320 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1321 if (OptoReg::is_valid(reg2)) {
1322 rm->Insert( reg2 );
1323 }
1324 } // End of for all arguments
1325
1326 // Compute number of stack slots needed to restore stack in case of
1327 // Pascal-style argument popping.
1328 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1329 }
1330
1331 // Compute the max stack slot killed by any call. These will not be
1332 // available for debug info, and will be used to adjust FIRST_STACK_mask
1333 // after all call sites have been visited.
1334 if( _out_arg_limit < out_arg_limit_per_call)
1335 _out_arg_limit = out_arg_limit_per_call;
1336
1337 if (mcall) {
1338 // Kill the outgoing argument area, including any non-argument holes and
1339 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1340 // Since the max-per-method covers the max-per-call-site and debug info
1341 // is excluded on the max-per-method basis, debug info cannot land in
1342 // this killed area.
1343 uint r_cnt = mcall->tf()->range_sig()->cnt();
1344 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1345 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1346 C->record_method_not_compilable("unsupported outgoing calling sequence");
1347 } else {
1348 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1349 proj->_rout.Insert(OptoReg::Name(i));
1350 }
1351 if (proj->_rout.is_NotEmpty()) {
1352 push_projection(proj);
1353 }
1354 }
1355 // Transfer the safepoint information from the call to the mcall
1356 // Move the JVMState list
1357 msfpt->set_jvms(sfpt->jvms());
1358 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1359 jvms->set_map(sfpt);
1360 }
1361
1362 // Debug inputs begin just after the last incoming parameter
1363 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1364 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain_cc()->cnt()), "");
1365
1366 // Move the OopMap
1367 msfpt->_oop_map = sfpt->_oop_map;
1368
1369 // Add additional edges.
1370 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1371 // For these calls we can not add MachConstantBase in expand(), as the
1372 // ins are not complete then.
1373 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1374 if (msfpt->jvms() &&
1375 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1376 // We added an edge before jvms, so we must adapt the position of the ins.
1377 msfpt->jvms()->adapt_position(+1);
1378 }
1379 }
1380
1381 // Registers killed by the call are set in the local scheduling pass
1382 // of Global Code Motion.
1383 return msfpt;
1384 }
1385
1386 //---------------------------match_tree----------------------------------------
1387 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1388 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1389 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1390 // a Load's result RegMask for memoization in idealreg2regmask[]
1391 MachNode *Matcher::match_tree( const Node *n ) {
1392 assert( n->Opcode() != Op_Phi, "cannot match" );
1393 assert( !n->is_block_start(), "cannot match" );
1394 // Set the mark for all locally allocated State objects.
1395 // When this call returns, the _states_arena arena will be reset
1396 // freeing all State objects.
1397 ResourceMark rm( &_states_arena );
1398
1399 LabelRootDepth = 0;
1400
1401 // StoreNodes require their Memory input to match any LoadNodes
1402 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1403 #ifdef ASSERT
1404 Node* save_mem_node = _mem_node;
1405 _mem_node = n->is_Store() ? (Node*)n : NULL;
1406 #endif
1407 // State object for root node of match tree
1408 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1409 State *s = new (&_states_arena) State;
1410 s->_kids[0] = NULL;
1411 s->_kids[1] = NULL;
1412 s->_leaf = (Node*)n;
1413 // Label the input tree, allocating labels from top-level arena
1414 Label_Root( n, s, n->in(0), mem );
1415 if (C->failing()) return NULL;
1416
1417 // The minimum cost match for the whole tree is found at the root State
1418 uint mincost = max_juint;
1419 uint cost = max_juint;
1420 uint i;
1421 for( i = 0; i < NUM_OPERANDS; i++ ) {
1422 if( s->valid(i) && // valid entry and
1423 s->_cost[i] < cost && // low cost and
1424 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1425 cost = s->_cost[mincost=i];
1426 }
1427 if (mincost == max_juint) {
1428 #ifndef PRODUCT
1429 tty->print("No matching rule for:");
1430 s->dump();
1431 #endif
1432 Matcher::soft_match_failure();
1433 return NULL;
1434 }
1435 // Reduce input tree based upon the state labels to machine Nodes
1436 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1437 #ifdef ASSERT
1438 _old2new_map.map(n->_idx, m);
1439 _new2old_map.map(m->_idx, (Node*)n);
1440 #endif
1441
1442 // Add any Matcher-ignored edges
1443 uint cnt = n->req();
1444 uint start = 1;
1445 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1446 if( n->is_AddP() ) {
1447 assert( mem == (Node*)1, "" );
1448 start = AddPNode::Base+1;
1449 }
1450 for( i = start; i < cnt; i++ ) {
1451 if( !n->match_edge(i) ) {
1452 if( i < m->req() )
1453 m->ins_req( i, n->in(i) );
1454 else
1455 m->add_req( n->in(i) );
1456 }
1457 }
1458
1459 debug_only( _mem_node = save_mem_node; )
1460 return m;
1461 }
1462
1463
1464 //------------------------------match_into_reg---------------------------------
1465 // Choose to either match this Node in a register or part of the current
1466 // match tree. Return true for requiring a register and false for matching
1467 // as part of the current match tree.
1468 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1469
1470 const Type *t = m->bottom_type();
1471
1472 if (t->singleton()) {
1473 // Never force constants into registers. Allow them to match as
1474 // constants or registers. Copies of the same value will share
1475 // the same register. See find_shared_node.
1476 return false;
1477 } else { // Not a constant
1478 // Stop recursion if they have different Controls.
1479 Node* m_control = m->in(0);
1480 // Control of load's memory can post-dominates load's control.
1481 // So use it since load can't float above its memory.
1482 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1483 if (control && m_control && control != m_control && control != mem_control) {
1484
1485 // Actually, we can live with the most conservative control we
1486 // find, if it post-dominates the others. This allows us to
1487 // pick up load/op/store trees where the load can float a little
1488 // above the store.
1489 Node *x = control;
1490 const uint max_scan = 6; // Arbitrary scan cutoff
1491 uint j;
1492 for (j=0; j<max_scan; j++) {
1493 if (x->is_Region()) // Bail out at merge points
1494 return true;
1495 x = x->in(0);
1496 if (x == m_control) // Does 'control' post-dominate
1497 break; // m->in(0)? If so, we can use it
1498 if (x == mem_control) // Does 'control' post-dominate
1499 break; // mem_control? If so, we can use it
1500 }
1501 if (j == max_scan) // No post-domination before scan end?
1502 return true; // Then break the match tree up
1503 }
1504 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1505 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1506 // These are commonly used in address expressions and can
1507 // efficiently fold into them on X64 in some cases.
1508 return false;
1509 }
1510 }
1511
1512 // Not forceable cloning. If shared, put it into a register.
1513 return shared;
1514 }
1515
1516
1517 //------------------------------Instruction Selection--------------------------
1518 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1519 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1520 // things the Matcher does not match (e.g., Memory), and things with different
1521 // Controls (hence forced into different blocks). We pass in the Control
1522 // selected for this entire State tree.
1523
1524 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1525 // Store and the Load must have identical Memories (as well as identical
1526 // pointers). Since the Matcher does not have anything for Memory (and
1527 // does not handle DAGs), I have to match the Memory input myself. If the
1528 // Tree root is a Store, I require all Loads to have the identical memory.
1529 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1530 // Since Label_Root is a recursive function, its possible that we might run
1531 // out of stack space. See bugs 6272980 & 6227033 for more info.
1532 LabelRootDepth++;
1533 if (LabelRootDepth > MaxLabelRootDepth) {
1534 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1535 return NULL;
1536 }
1537 uint care = 0; // Edges matcher cares about
1538 uint cnt = n->req();
1539 uint i = 0;
1540
1541 // Examine children for memory state
1542 // Can only subsume a child into your match-tree if that child's memory state
1543 // is not modified along the path to another input.
1544 // It is unsafe even if the other inputs are separate roots.
1545 Node *input_mem = NULL;
1546 for( i = 1; i < cnt; i++ ) {
1547 if( !n->match_edge(i) ) continue;
1548 Node *m = n->in(i); // Get ith input
1549 assert( m, "expect non-null children" );
1550 if( m->is_Load() ) {
1551 if( input_mem == NULL ) {
1552 input_mem = m->in(MemNode::Memory);
1553 } else if( input_mem != m->in(MemNode::Memory) ) {
1554 input_mem = NodeSentinel;
1555 }
1556 }
1557 }
1558
1559 for( i = 1; i < cnt; i++ ){// For my children
1560 if( !n->match_edge(i) ) continue;
1561 Node *m = n->in(i); // Get ith input
1562 // Allocate states out of a private arena
1563 State *s = new (&_states_arena) State;
1564 svec->_kids[care++] = s;
1565 assert( care <= 2, "binary only for now" );
1566
1567 // Recursively label the State tree.
1568 s->_kids[0] = NULL;
1569 s->_kids[1] = NULL;
1570 s->_leaf = m;
1571
1572 // Check for leaves of the State Tree; things that cannot be a part of
1573 // the current tree. If it finds any, that value is matched as a
1574 // register operand. If not, then the normal matching is used.
1575 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1576 //
1577 // Stop recursion if this is LoadNode and the root of this tree is a
1578 // StoreNode and the load & store have different memories.
1579 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1580 // Can NOT include the match of a subtree when its memory state
1581 // is used by any of the other subtrees
1582 (input_mem == NodeSentinel) ) {
1583 // Print when we exclude matching due to different memory states at input-loads
1584 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1585 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1586 tty->print_cr("invalid input_mem");
1587 }
1588 // Switch to a register-only opcode; this value must be in a register
1589 // and cannot be subsumed as part of a larger instruction.
1590 s->DFA( m->ideal_reg(), m );
1591
1592 } else {
1593 // If match tree has no control and we do, adopt it for entire tree
1594 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1595 control = m->in(0); // Pick up control
1596 // Else match as a normal part of the match tree.
1597 control = Label_Root(m,s,control,mem);
1598 if (C->failing()) return NULL;
1599 }
1600 }
1601
1602
1603 // Call DFA to match this node, and return
1604 svec->DFA( n->Opcode(), n );
1605
1606 #ifdef ASSERT
1607 uint x;
1608 for( x = 0; x < _LAST_MACH_OPER; x++ )
1609 if( svec->valid(x) )
1610 break;
1611
1612 if (x >= _LAST_MACH_OPER) {
1613 n->dump();
1614 svec->dump();
1615 assert( false, "bad AD file" );
1616 }
1617 #endif
1618 return control;
1619 }
1620
1621
1622 // Con nodes reduced using the same rule can share their MachNode
1623 // which reduces the number of copies of a constant in the final
1624 // program. The register allocator is free to split uses later to
1625 // split live ranges.
1626 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1627 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1628
1629 // See if this Con has already been reduced using this rule.
1630 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1631 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1632 if (last != NULL && rule == last->rule()) {
1633 // Don't expect control change for DecodeN
1634 if (leaf->is_DecodeNarrowPtr())
1635 return last;
1636 // Get the new space root.
1637 Node* xroot = new_node(C->root());
1638 if (xroot == NULL) {
1639 // This shouldn't happen give the order of matching.
1640 return NULL;
1641 }
1642
1643 // Shared constants need to have their control be root so they
1644 // can be scheduled properly.
1645 Node* control = last->in(0);
1646 if (control != xroot) {
1647 if (control == NULL || control == C->root()) {
1648 last->set_req(0, xroot);
1649 } else {
1650 assert(false, "unexpected control");
1651 return NULL;
1652 }
1653 }
1654 return last;
1655 }
1656 return NULL;
1657 }
1658
1659
1660 //------------------------------ReduceInst-------------------------------------
1661 // Reduce a State tree (with given Control) into a tree of MachNodes.
1662 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1663 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1664 // Each MachNode has a number of complicated MachOper operands; each
1665 // MachOper also covers a further tree of Ideal Nodes.
1666
1667 // The root of the Ideal match tree is always an instruction, so we enter
1668 // the recursion here. After building the MachNode, we need to recurse
1669 // the tree checking for these cases:
1670 // (1) Child is an instruction -
1671 // Build the instruction (recursively), add it as an edge.
1672 // Build a simple operand (register) to hold the result of the instruction.
1673 // (2) Child is an interior part of an instruction -
1674 // Skip over it (do nothing)
1675 // (3) Child is the start of a operand -
1676 // Build the operand, place it inside the instruction
1677 // Call ReduceOper.
1678 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1679 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1680
1681 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1682 if (shared_node != NULL) {
1683 return shared_node;
1684 }
1685
1686 // Build the object to represent this state & prepare for recursive calls
1687 MachNode *mach = s->MachNodeGenerator(rule);
1688 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1689 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1690 Node *leaf = s->_leaf;
1691 // Check for instruction or instruction chain rule
1692 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1693 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1694 "duplicating node that's already been matched");
1695 // Instruction
1696 mach->add_req( leaf->in(0) ); // Set initial control
1697 // Reduce interior of complex instruction
1698 ReduceInst_Interior( s, rule, mem, mach, 1 );
1699 } else {
1700 // Instruction chain rules are data-dependent on their inputs
1701 mach->add_req(0); // Set initial control to none
1702 ReduceInst_Chain_Rule( s, rule, mem, mach );
1703 }
1704
1705 // If a Memory was used, insert a Memory edge
1706 if( mem != (Node*)1 ) {
1707 mach->ins_req(MemNode::Memory,mem);
1708 #ifdef ASSERT
1709 // Verify adr type after matching memory operation
1710 const MachOper* oper = mach->memory_operand();
1711 if (oper != NULL && oper != (MachOper*)-1) {
1712 // It has a unique memory operand. Find corresponding ideal mem node.
1713 Node* m = NULL;
1714 if (leaf->is_Mem()) {
1715 m = leaf;
1716 } else {
1717 m = _mem_node;
1718 assert(m != NULL && m->is_Mem(), "expecting memory node");
1719 }
1720 const Type* mach_at = mach->adr_type();
1721 // DecodeN node consumed by an address may have different type
1722 // then its input. Don't compare types for such case.
1723 if (m->adr_type() != mach_at &&
1724 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1725 m->in(MemNode::Address)->is_AddP() &&
1726 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1727 m->in(MemNode::Address)->is_AddP() &&
1728 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1729 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1730 mach_at = m->adr_type();
1731 }
1732 if (m->adr_type() != mach_at) {
1733 m->dump();
1734 tty->print_cr("mach:");
1735 mach->dump(1);
1736 }
1737 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1738 }
1739 #endif
1740 }
1741
1742 // If the _leaf is an AddP, insert the base edge
1743 if (leaf->is_AddP()) {
1744 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1745 }
1746
1747 uint number_of_projections_prior = number_of_projections();
1748
1749 // Perform any 1-to-many expansions required
1750 MachNode *ex = mach->Expand(s, _projection_list, mem);
1751 if (ex != mach) {
1752 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1753 if( ex->in(1)->is_Con() )
1754 ex->in(1)->set_req(0, C->root());
1755 // Remove old node from the graph
1756 for( uint i=0; i<mach->req(); i++ ) {
1757 mach->set_req(i,NULL);
1758 }
1759 #ifdef ASSERT
1760 _new2old_map.map(ex->_idx, s->_leaf);
1761 #endif
1762 }
1763
1764 // PhaseChaitin::fixup_spills will sometimes generate spill code
1765 // via the matcher. By the time, nodes have been wired into the CFG,
1766 // and any further nodes generated by expand rules will be left hanging
1767 // in space, and will not get emitted as output code. Catch this.
1768 // Also, catch any new register allocation constraints ("projections")
1769 // generated belatedly during spill code generation.
1770 if (_allocation_started) {
1771 guarantee(ex == mach, "no expand rules during spill generation");
1772 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1773 }
1774
1775 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1776 // Record the con for sharing
1777 _shared_nodes.map(leaf->_idx, ex);
1778 }
1779
1780 return ex;
1781 }
1782
1783 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1784 for (uint i = n->req(); i < n->len(); i++) {
1785 if (n->in(i) != NULL) {
1786 mach->add_prec(n->in(i));
1787 }
1788 }
1789 }
1790
1791 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1792 // 'op' is what I am expecting to receive
1793 int op = _leftOp[rule];
1794 // Operand type to catch childs result
1795 // This is what my child will give me.
1796 int opnd_class_instance = s->_rule[op];
1797 // Choose between operand class or not.
1798 // This is what I will receive.
1799 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1800 // New rule for child. Chase operand classes to get the actual rule.
1801 int newrule = s->_rule[catch_op];
1802
1803 if( newrule < NUM_OPERANDS ) {
1804 // Chain from operand or operand class, may be output of shared node
1805 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1806 "Bad AD file: Instruction chain rule must chain from operand");
1807 // Insert operand into array of operands for this instruction
1808 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1809
1810 ReduceOper( s, newrule, mem, mach );
1811 } else {
1812 // Chain from the result of an instruction
1813 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1814 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1815 Node *mem1 = (Node*)1;
1816 debug_only(Node *save_mem_node = _mem_node;)
1817 mach->add_req( ReduceInst(s, newrule, mem1) );
1818 debug_only(_mem_node = save_mem_node;)
1819 }
1820 return;
1821 }
1822
1823
1824 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1825 handle_precedence_edges(s->_leaf, mach);
1826
1827 if( s->_leaf->is_Load() ) {
1828 Node *mem2 = s->_leaf->in(MemNode::Memory);
1829 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1830 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1831 mem = mem2;
1832 }
1833 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1834 if( mach->in(0) == NULL )
1835 mach->set_req(0, s->_leaf->in(0));
1836 }
1837
1838 // Now recursively walk the state tree & add operand list.
1839 for( uint i=0; i<2; i++ ) { // binary tree
1840 State *newstate = s->_kids[i];
1841 if( newstate == NULL ) break; // Might only have 1 child
1842 // 'op' is what I am expecting to receive
1843 int op;
1844 if( i == 0 ) {
1845 op = _leftOp[rule];
1846 } else {
1847 op = _rightOp[rule];
1848 }
1849 // Operand type to catch childs result
1850 // This is what my child will give me.
1851 int opnd_class_instance = newstate->_rule[op];
1852 // Choose between operand class or not.
1853 // This is what I will receive.
1854 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1855 // New rule for child. Chase operand classes to get the actual rule.
1856 int newrule = newstate->_rule[catch_op];
1857
1858 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1859 // Operand/operandClass
1860 // Insert operand into array of operands for this instruction
1861 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1862 ReduceOper( newstate, newrule, mem, mach );
1863
1864 } else { // Child is internal operand or new instruction
1865 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1866 // internal operand --> call ReduceInst_Interior
1867 // Interior of complex instruction. Do nothing but recurse.
1868 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1869 } else {
1870 // instruction --> call build operand( ) to catch result
1871 // --> ReduceInst( newrule )
1872 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1873 Node *mem1 = (Node*)1;
1874 debug_only(Node *save_mem_node = _mem_node;)
1875 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1876 debug_only(_mem_node = save_mem_node;)
1877 }
1878 }
1879 assert( mach->_opnds[num_opnds-1], "" );
1880 }
1881 return num_opnds;
1882 }
1883
1884 // This routine walks the interior of possible complex operands.
1885 // At each point we check our children in the match tree:
1886 // (1) No children -
1887 // We are a leaf; add _leaf field as an input to the MachNode
1888 // (2) Child is an internal operand -
1889 // Skip over it ( do nothing )
1890 // (3) Child is an instruction -
1891 // Call ReduceInst recursively and
1892 // and instruction as an input to the MachNode
1893 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1894 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1895 State *kid = s->_kids[0];
1896 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1897
1898 // Leaf? And not subsumed?
1899 if( kid == NULL && !_swallowed[rule] ) {
1900 mach->add_req( s->_leaf ); // Add leaf pointer
1901 return; // Bail out
1902 }
1903
1904 if( s->_leaf->is_Load() ) {
1905 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1906 mem = s->_leaf->in(MemNode::Memory);
1907 debug_only(_mem_node = s->_leaf;)
1908 }
1909
1910 handle_precedence_edges(s->_leaf, mach);
1911
1912 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1913 if( !mach->in(0) )
1914 mach->set_req(0,s->_leaf->in(0));
1915 else {
1916 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1917 }
1918 }
1919
1920 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1921 int newrule;
1922 if( i == 0)
1923 newrule = kid->_rule[_leftOp[rule]];
1924 else
1925 newrule = kid->_rule[_rightOp[rule]];
1926
1927 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1928 // Internal operand; recurse but do nothing else
1929 ReduceOper( kid, newrule, mem, mach );
1930
1931 } else { // Child is a new instruction
1932 // Reduce the instruction, and add a direct pointer from this
1933 // machine instruction to the newly reduced one.
1934 Node *mem1 = (Node*)1;
1935 debug_only(Node *save_mem_node = _mem_node;)
1936 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1937 debug_only(_mem_node = save_mem_node;)
1938 }
1939 }
1940 }
1941
1942
1943 // -------------------------------------------------------------------------
1944 // Java-Java calling convention
1945 // (what you use when Java calls Java)
1946
1947 //------------------------------find_receiver----------------------------------
1948 // For a given signature, return the OptoReg for parameter 0.
1949 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1950 VMRegPair regs;
1951 BasicType sig_bt = T_OBJECT;
1952 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1953 // Return argument 0 register. In the LP64 build pointers
1954 // take 2 registers, but the VM wants only the 'main' name.
1955 return OptoReg::as_OptoReg(regs.first());
1956 }
1957
1958 // This function identifies sub-graphs in which a 'load' node is
1959 // input to two different nodes, and such that it can be matched
1960 // with BMI instructions like blsi, blsr, etc.
1961 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1962 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1963 // refers to the same node.
1964 #ifdef X86
1965 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1966 // This is a temporary solution until we make DAGs expressible in ADL.
1967 template<typename ConType>
1968 class FusedPatternMatcher {
1969 Node* _op1_node;
1970 Node* _mop_node;
1971 int _con_op;
1972
1973 static int match_next(Node* n, int next_op, int next_op_idx) {
1974 if (n->in(1) == NULL || n->in(2) == NULL) {
1975 return -1;
1976 }
1977
1978 if (next_op_idx == -1) { // n is commutative, try rotations
1979 if (n->in(1)->Opcode() == next_op) {
1980 return 1;
1981 } else if (n->in(2)->Opcode() == next_op) {
1982 return 2;
1983 }
1984 } else {
1985 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1986 if (n->in(next_op_idx)->Opcode() == next_op) {
1987 return next_op_idx;
1988 }
1989 }
1990 return -1;
1991 }
1992 public:
1993 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1994 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1995
1996 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1997 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1998 typename ConType::NativeType con_value) {
1999 if (_op1_node->Opcode() != op1) {
2000 return false;
2001 }
2002 if (_mop_node->outcnt() > 2) {
2003 return false;
2004 }
2005 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
2006 if (op1_op2_idx == -1) {
2007 return false;
2008 }
2009 // Memory operation must be the other edge
2010 int op1_mop_idx = (op1_op2_idx & 1) + 1;
2011
2012 // Check that the mop node is really what we want
2013 if (_op1_node->in(op1_mop_idx) == _mop_node) {
2014 Node *op2_node = _op1_node->in(op1_op2_idx);
2015 if (op2_node->outcnt() > 1) {
2016 return false;
2017 }
2018 assert(op2_node->Opcode() == op2, "Should be");
2019 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
2020 if (op2_con_idx == -1) {
2021 return false;
2022 }
2023 // Memory operation must be the other edge
2024 int op2_mop_idx = (op2_con_idx & 1) + 1;
2025 // Check that the memory operation is the same node
2026 if (op2_node->in(op2_mop_idx) == _mop_node) {
2027 // Now check the constant
2028 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
2029 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
2030 return true;
2031 }
2032 }
2033 }
2034 return false;
2035 }
2036 };
2037
2038
2039 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2040 if (n != NULL && m != NULL) {
2041 if (m->Opcode() == Op_LoadI) {
2042 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2043 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2044 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2045 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2046 } else if (m->Opcode() == Op_LoadL) {
2047 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2048 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2049 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2050 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2051 }
2052 }
2053 return false;
2054 }
2055 #endif // X86
2056
2057 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2058 Node *off = m->in(AddPNode::Offset);
2059 if (off->is_Con()) {
2060 address_visited.test_set(m->_idx); // Flag as address_visited
2061 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2062 // Clone X+offset as it also folds into most addressing expressions
2063 mstack.push(off, Visit);
2064 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2065 return true;
2066 }
2067 return false;
2068 }
2069
2070 // A method-klass-holder may be passed in the inline_cache_reg
2071 // and then expanded into the inline_cache_reg and a method_oop register
2072 // defined in ad_<arch>.cpp
2073
2074 //------------------------------find_shared------------------------------------
2075 // Set bits if Node is shared or otherwise a root
2076 void Matcher::find_shared( Node *n ) {
2077 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2078 MStack mstack(C->live_nodes() * 2);
2079 // Mark nodes as address_visited if they are inputs to an address expression
2080 VectorSet address_visited(Thread::current()->resource_area());
2081 mstack.push(n, Visit); // Don't need to pre-visit root node
2082 while (mstack.is_nonempty()) {
2083 n = mstack.node(); // Leave node on stack
2084 Node_State nstate = mstack.state();
2085 uint nop = n->Opcode();
2086 if (nstate == Pre_Visit) {
2087 if (address_visited.test(n->_idx)) { // Visited in address already?
2088 // Flag as visited and shared now.
2089 set_visited(n);
2090 }
2091 if (is_visited(n)) { // Visited already?
2092 // Node is shared and has no reason to clone. Flag it as shared.
2093 // This causes it to match into a register for the sharing.
2094 set_shared(n); // Flag as shared and
2095 mstack.pop(); // remove node from stack
2096 continue;
2097 }
2098 nstate = Visit; // Not already visited; so visit now
2099 }
2100 if (nstate == Visit) {
2101 mstack.set_state(Post_Visit);
2102 set_visited(n); // Flag as visited now
2103 bool mem_op = false;
2104
2105 switch( nop ) { // Handle some opcodes special
2106 case Op_Phi: // Treat Phis as shared roots
2107 case Op_Parm:
2108 case Op_Proj: // All handled specially during matching
2109 case Op_SafePointScalarObject:
2110 set_shared(n);
2111 set_dontcare(n);
2112 break;
2113 case Op_If:
2114 case Op_CountedLoopEnd:
2115 mstack.set_state(Alt_Post_Visit); // Alternative way
2116 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2117 // with matching cmp/branch in 1 instruction. The Matcher needs the
2118 // Bool and CmpX side-by-side, because it can only get at constants
2119 // that are at the leaves of Match trees, and the Bool's condition acts
2120 // as a constant here.
2121 mstack.push(n->in(1), Visit); // Clone the Bool
2122 mstack.push(n->in(0), Pre_Visit); // Visit control input
2123 continue; // while (mstack.is_nonempty())
2124 case Op_ConvI2D: // These forms efficiently match with a prior
2125 case Op_ConvI2F: // Load but not a following Store
2126 if( n->in(1)->is_Load() && // Prior load
2127 n->outcnt() == 1 && // Not already shared
2128 n->unique_out()->is_Store() ) // Following store
2129 set_shared(n); // Force it to be a root
2130 break;
2131 case Op_ReverseBytesI:
2132 case Op_ReverseBytesL:
2133 if( n->in(1)->is_Load() && // Prior load
2134 n->outcnt() == 1 ) // Not already shared
2135 set_shared(n); // Force it to be a root
2136 break;
2137 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2138 case Op_IfFalse:
2139 case Op_IfTrue:
2140 case Op_MachProj:
2141 case Op_MergeMem:
2142 case Op_Catch:
2143 case Op_CatchProj:
2144 case Op_CProj:
2145 case Op_JumpProj:
2146 case Op_JProj:
2147 case Op_NeverBranch:
2148 set_dontcare(n);
2149 break;
2150 case Op_Jump:
2151 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2152 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2153 continue; // while (mstack.is_nonempty())
2154 case Op_StrComp:
2155 case Op_StrEquals:
2156 case Op_StrIndexOf:
2157 case Op_StrIndexOfChar:
2158 case Op_AryEq:
2159 case Op_HasNegatives:
2160 case Op_StrInflatedCopy:
2161 case Op_StrCompressedCopy:
2162 case Op_EncodeISOArray:
2163 case Op_FmaD:
2164 case Op_FmaF:
2165 set_shared(n); // Force result into register (it will be anyways)
2166 break;
2167 case Op_ConP: { // Convert pointers above the centerline to NUL
2168 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2169 const TypePtr* tp = tn->type()->is_ptr();
2170 if (tp->_ptr == TypePtr::AnyNull) {
2171 tn->set_type(TypePtr::NULL_PTR);
2172 }
2173 break;
2174 }
2175 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2176 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2177 const TypePtr* tp = tn->type()->make_ptr();
2178 if (tp && tp->_ptr == TypePtr::AnyNull) {
2179 tn->set_type(TypeNarrowOop::NULL_PTR);
2180 }
2181 break;
2182 }
2183 case Op_Binary: // These are introduced in the Post_Visit state.
2184 ShouldNotReachHere();
2185 break;
2186 case Op_ClearArray:
2187 case Op_SafePoint:
2188 mem_op = true;
2189 break;
2190 default:
2191 if( n->is_Store() ) {
2192 // Do match stores, despite no ideal reg
2193 mem_op = true;
2194 break;
2195 }
2196 if( n->is_Mem() ) { // Loads and LoadStores
2197 mem_op = true;
2198 // Loads must be root of match tree due to prior load conflict
2199 if( C->subsume_loads() == false )
2200 set_shared(n);
2201 }
2202 // Fall into default case
2203 if( !n->ideal_reg() )
2204 set_dontcare(n); // Unmatchable Nodes
2205 } // end_switch
2206
2207 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2208 Node *m = n->in(i); // Get ith input
2209 if (m == NULL) continue; // Ignore NULLs
2210 uint mop = m->Opcode();
2211
2212 // Must clone all producers of flags, or we will not match correctly.
2213 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2214 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2215 // are also there, so we may match a float-branch to int-flags and
2216 // expect the allocator to haul the flags from the int-side to the
2217 // fp-side. No can do.
2218 if( _must_clone[mop] ) {
2219 mstack.push(m, Visit);
2220 continue; // for(int i = ...)
2221 }
2222
2223 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2224 // Bases used in addresses must be shared but since
2225 // they are shared through a DecodeN they may appear
2226 // to have a single use so force sharing here.
2227 set_shared(m->in(AddPNode::Base)->in(1));
2228 }
2229
2230 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2231 #ifdef X86
2232 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2233 mstack.push(m, Visit);
2234 continue;
2235 }
2236 #endif
2237
2238 // Clone addressing expressions as they are "free" in memory access instructions
2239 if (mem_op && i == MemNode::Address && mop == Op_AddP &&
2240 // When there are other uses besides address expressions
2241 // put it on stack and mark as shared.
2242 !is_visited(m)) {
2243 // Some inputs for address expression are not put on stack
2244 // to avoid marking them as shared and forcing them into register
2245 // if they are used only in address expressions.
2246 // But they should be marked as shared if there are other uses
2247 // besides address expressions.
2248
2249 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2250 continue;
2251 }
2252 } // if( mem_op &&
2253 mstack.push(m, Pre_Visit);
2254 } // for(int i = ...)
2255 }
2256 else if (nstate == Alt_Post_Visit) {
2257 mstack.pop(); // Remove node from stack
2258 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2259 // shared and all users of the Bool need to move the Cmp in parallel.
2260 // This leaves both the Bool and the If pointing at the Cmp. To
2261 // prevent the Matcher from trying to Match the Cmp along both paths
2262 // BoolNode::match_edge always returns a zero.
2263
2264 // We reorder the Op_If in a pre-order manner, so we can visit without
2265 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2266 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2267 }
2268 else if (nstate == Post_Visit) {
2269 mstack.pop(); // Remove node from stack
2270
2271 // Now hack a few special opcodes
2272 switch( n->Opcode() ) { // Handle some opcodes special
2273 case Op_StorePConditional:
2274 case Op_StoreIConditional:
2275 case Op_StoreLConditional:
2276 case Op_CompareAndExchangeB:
2277 case Op_CompareAndExchangeS:
2278 case Op_CompareAndExchangeI:
2279 case Op_CompareAndExchangeL:
2280 case Op_CompareAndExchangeP:
2281 case Op_CompareAndExchangeN:
2282 case Op_WeakCompareAndSwapB:
2283 case Op_WeakCompareAndSwapS:
2284 case Op_WeakCompareAndSwapI:
2285 case Op_WeakCompareAndSwapL:
2286 case Op_WeakCompareAndSwapP:
2287 case Op_WeakCompareAndSwapN:
2288 case Op_CompareAndSwapB:
2289 case Op_CompareAndSwapS:
2290 case Op_CompareAndSwapI:
2291 case Op_CompareAndSwapL:
2292 case Op_CompareAndSwapP:
2293 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2294 Node *newval = n->in(MemNode::ValueIn );
2295 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2296 Node *pair = new BinaryNode( oldval, newval );
2297 n->set_req(MemNode::ValueIn,pair);
2298 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2299 break;
2300 }
2301 case Op_CMoveD: // Convert trinary to binary-tree
2302 case Op_CMoveF:
2303 case Op_CMoveI:
2304 case Op_CMoveL:
2305 case Op_CMoveN:
2306 case Op_CMoveP:
2307 case Op_CMoveVD: {
2308 // Restructure into a binary tree for Matching. It's possible that
2309 // we could move this code up next to the graph reshaping for IfNodes
2310 // or vice-versa, but I do not want to debug this for Ladybird.
2311 // 10/2/2000 CNC.
2312 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2313 n->set_req(1,pair1);
2314 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2315 n->set_req(2,pair2);
2316 n->del_req(3);
2317 break;
2318 }
2319 case Op_LoopLimit: {
2320 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2321 n->set_req(1,pair1);
2322 n->set_req(2,n->in(3));
2323 n->del_req(3);
2324 break;
2325 }
2326 case Op_StrEquals:
2327 case Op_StrIndexOfChar: {
2328 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2329 n->set_req(2,pair1);
2330 n->set_req(3,n->in(4));
2331 n->del_req(4);
2332 break;
2333 }
2334 case Op_StrComp:
2335 case Op_StrIndexOf: {
2336 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2337 n->set_req(2,pair1);
2338 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2339 n->set_req(3,pair2);
2340 n->del_req(5);
2341 n->del_req(4);
2342 break;
2343 }
2344 case Op_StrCompressedCopy:
2345 case Op_StrInflatedCopy:
2346 case Op_EncodeISOArray: {
2347 // Restructure into a binary tree for Matching.
2348 Node* pair = new BinaryNode(n->in(3), n->in(4));
2349 n->set_req(3, pair);
2350 n->del_req(4);
2351 break;
2352 }
2353 case Op_FmaD:
2354 case Op_FmaF: {
2355 // Restructure into a binary tree for Matching.
2356 Node* pair = new BinaryNode(n->in(1), n->in(2));
2357 n->set_req(2, pair);
2358 n->set_req(1, n->in(3));
2359 n->del_req(3);
2360 break;
2361 }
2362 default:
2363 break;
2364 }
2365 }
2366 else {
2367 ShouldNotReachHere();
2368 }
2369 } // end of while (mstack.is_nonempty())
2370 }
2371
2372 #ifdef ASSERT
2373 // machine-independent root to machine-dependent root
2374 void Matcher::dump_old2new_map() {
2375 _old2new_map.dump();
2376 }
2377 #endif
2378
2379 //---------------------------collect_null_checks-------------------------------
2380 // Find null checks in the ideal graph; write a machine-specific node for
2381 // it. Used by later implicit-null-check handling. Actually collects
2382 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2383 // value being tested.
2384 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2385 Node *iff = proj->in(0);
2386 if( iff->Opcode() == Op_If ) {
2387 // During matching If's have Bool & Cmp side-by-side
2388 BoolNode *b = iff->in(1)->as_Bool();
2389 Node *cmp = iff->in(2);
2390 int opc = cmp->Opcode();
2391 if (opc != Op_CmpP && opc != Op_CmpN) return;
2392
2393 const Type* ct = cmp->in(2)->bottom_type();
2394 if (ct == TypePtr::NULL_PTR ||
2395 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2396
2397 bool push_it = false;
2398 if( proj->Opcode() == Op_IfTrue ) {
2399 #ifndef PRODUCT
2400 extern int all_null_checks_found;
2401 all_null_checks_found++;
2402 #endif
2403 if( b->_test._test == BoolTest::ne ) {
2404 push_it = true;
2405 }
2406 } else {
2407 assert( proj->Opcode() == Op_IfFalse, "" );
2408 if( b->_test._test == BoolTest::eq ) {
2409 push_it = true;
2410 }
2411 }
2412 if( push_it ) {
2413 _null_check_tests.push(proj);
2414 Node* val = cmp->in(1);
2415 #ifdef _LP64
2416 if (val->bottom_type()->isa_narrowoop() &&
2417 !Matcher::narrow_oop_use_complex_address()) {
2418 //
2419 // Look for DecodeN node which should be pinned to orig_proj.
2420 // On platforms (Sparc) which can not handle 2 adds
2421 // in addressing mode we have to keep a DecodeN node and
2422 // use it to do implicit NULL check in address.
2423 //
2424 // DecodeN node was pinned to non-null path (orig_proj) during
2425 // CastPP transformation in final_graph_reshaping_impl().
2426 //
2427 uint cnt = orig_proj->outcnt();
2428 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2429 Node* d = orig_proj->raw_out(i);
2430 if (d->is_DecodeN() && d->in(1) == val) {
2431 val = d;
2432 val->set_req(0, NULL); // Unpin now.
2433 // Mark this as special case to distinguish from
2434 // a regular case: CmpP(DecodeN, NULL).
2435 val = (Node*)(((intptr_t)val) | 1);
2436 break;
2437 }
2438 }
2439 }
2440 #endif
2441 _null_check_tests.push(val);
2442 }
2443 }
2444 }
2445 }
2446
2447 //---------------------------validate_null_checks------------------------------
2448 // Its possible that the value being NULL checked is not the root of a match
2449 // tree. If so, I cannot use the value in an implicit null check.
2450 void Matcher::validate_null_checks( ) {
2451 uint cnt = _null_check_tests.size();
2452 for( uint i=0; i < cnt; i+=2 ) {
2453 Node *test = _null_check_tests[i];
2454 Node *val = _null_check_tests[i+1];
2455 bool is_decoden = ((intptr_t)val) & 1;
2456 val = (Node*)(((intptr_t)val) & ~1);
2457 if (has_new_node(val)) {
2458 Node* new_val = new_node(val);
2459 if (is_decoden) {
2460 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2461 // Note: new_val may have a control edge if
2462 // the original ideal node DecodeN was matched before
2463 // it was unpinned in Matcher::collect_null_checks().
2464 // Unpin the mach node and mark it.
2465 new_val->set_req(0, NULL);
2466 new_val = (Node*)(((intptr_t)new_val) | 1);
2467 }
2468 // Is a match-tree root, so replace with the matched value
2469 _null_check_tests.map(i+1, new_val);
2470 } else {
2471 // Yank from candidate list
2472 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2473 _null_check_tests.map(i,_null_check_tests[--cnt]);
2474 _null_check_tests.pop();
2475 _null_check_tests.pop();
2476 i-=2;
2477 }
2478 }
2479 }
2480
2481 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2482 // atomic instruction acting as a store_load barrier without any
2483 // intervening volatile load, and thus we don't need a barrier here.
2484 // We retain the Node to act as a compiler ordering barrier.
2485 bool Matcher::post_store_load_barrier(const Node* vmb) {
2486 Compile* C = Compile::current();
2487 assert(vmb->is_MemBar(), "");
2488 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2489 const MemBarNode* membar = vmb->as_MemBar();
2490
2491 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2492 Node* ctrl = NULL;
2493 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2494 Node* p = membar->fast_out(i);
2495 assert(p->is_Proj(), "only projections here");
2496 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2497 !C->node_arena()->contains(p)) { // Unmatched old-space only
2498 ctrl = p;
2499 break;
2500 }
2501 }
2502 assert((ctrl != NULL), "missing control projection");
2503
2504 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2505 Node *x = ctrl->fast_out(j);
2506 int xop = x->Opcode();
2507
2508 // We don't need current barrier if we see another or a lock
2509 // before seeing volatile load.
2510 //
2511 // Op_Fastunlock previously appeared in the Op_* list below.
2512 // With the advent of 1-0 lock operations we're no longer guaranteed
2513 // that a monitor exit operation contains a serializing instruction.
2514
2515 if (xop == Op_MemBarVolatile ||
2516 xop == Op_CompareAndExchangeB ||
2517 xop == Op_CompareAndExchangeS ||
2518 xop == Op_CompareAndExchangeI ||
2519 xop == Op_CompareAndExchangeL ||
2520 xop == Op_CompareAndExchangeP ||
2521 xop == Op_CompareAndExchangeN ||
2522 xop == Op_WeakCompareAndSwapB ||
2523 xop == Op_WeakCompareAndSwapS ||
2524 xop == Op_WeakCompareAndSwapL ||
2525 xop == Op_WeakCompareAndSwapP ||
2526 xop == Op_WeakCompareAndSwapN ||
2527 xop == Op_WeakCompareAndSwapI ||
2528 xop == Op_CompareAndSwapB ||
2529 xop == Op_CompareAndSwapS ||
2530 xop == Op_CompareAndSwapL ||
2531 xop == Op_CompareAndSwapP ||
2532 xop == Op_CompareAndSwapN ||
2533 xop == Op_CompareAndSwapI) {
2534 return true;
2535 }
2536
2537 // Op_FastLock previously appeared in the Op_* list above.
2538 // With biased locking we're no longer guaranteed that a monitor
2539 // enter operation contains a serializing instruction.
2540 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2541 return true;
2542 }
2543
2544 if (x->is_MemBar()) {
2545 // We must retain this membar if there is an upcoming volatile
2546 // load, which will be followed by acquire membar.
2547 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2548 return false;
2549 } else {
2550 // For other kinds of barriers, check by pretending we
2551 // are them, and seeing if we can be removed.
2552 return post_store_load_barrier(x->as_MemBar());
2553 }
2554 }
2555
2556 // probably not necessary to check for these
2557 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2558 return false;
2559 }
2560 }
2561 return false;
2562 }
2563
2564 // Check whether node n is a branch to an uncommon trap that we could
2565 // optimize as test with very high branch costs in case of going to
2566 // the uncommon trap. The code must be able to be recompiled to use
2567 // a cheaper test.
2568 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2569 // Don't do it for natives, adapters, or runtime stubs
2570 Compile *C = Compile::current();
2571 if (!C->is_method_compilation()) return false;
2572
2573 assert(n->is_If(), "You should only call this on if nodes.");
2574 IfNode *ifn = n->as_If();
2575
2576 Node *ifFalse = NULL;
2577 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2578 if (ifn->fast_out(i)->is_IfFalse()) {
2579 ifFalse = ifn->fast_out(i);
2580 break;
2581 }
2582 }
2583 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2584
2585 Node *reg = ifFalse;
2586 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2587 // Alternatively use visited set? Seems too expensive.
2588 while (reg != NULL && cnt > 0) {
2589 CallNode *call = NULL;
2590 RegionNode *nxt_reg = NULL;
2591 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2592 Node *o = reg->fast_out(i);
2593 if (o->is_Call()) {
2594 call = o->as_Call();
2595 }
2596 if (o->is_Region()) {
2597 nxt_reg = o->as_Region();
2598 }
2599 }
2600
2601 if (call &&
2602 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2603 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2604 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2605 jint tr_con = trtype->is_int()->get_con();
2606 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2607 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2608 assert((int)reason < (int)BitsPerInt, "recode bit map");
2609
2610 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2611 && action != Deoptimization::Action_none) {
2612 // This uncommon trap is sure to recompile, eventually.
2613 // When that happens, C->too_many_traps will prevent
2614 // this transformation from happening again.
2615 return true;
2616 }
2617 }
2618 }
2619
2620 reg = nxt_reg;
2621 cnt--;
2622 }
2623
2624 return false;
2625 }
2626
2627 //=============================================================================
2628 //---------------------------State---------------------------------------------
2629 State::State(void) {
2630 #ifdef ASSERT
2631 _id = 0;
2632 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2633 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2634 //memset(_cost, -1, sizeof(_cost));
2635 //memset(_rule, -1, sizeof(_rule));
2636 #endif
2637 memset(_valid, 0, sizeof(_valid));
2638 }
2639
2640 #ifdef ASSERT
2641 State::~State() {
2642 _id = 99;
2643 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2644 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2645 memset(_cost, -3, sizeof(_cost));
2646 memset(_rule, -3, sizeof(_rule));
2647 }
2648 #endif
2649
2650 #ifndef PRODUCT
2651 //---------------------------dump----------------------------------------------
2652 void State::dump() {
2653 tty->print("\n");
2654 dump(0);
2655 }
2656
2657 void State::dump(int depth) {
2658 for( int j = 0; j < depth; j++ )
2659 tty->print(" ");
2660 tty->print("--N: ");
2661 _leaf->dump();
2662 uint i;
2663 for( i = 0; i < _LAST_MACH_OPER; i++ )
2664 // Check for valid entry
2665 if( valid(i) ) {
2666 for( int j = 0; j < depth; j++ )
2667 tty->print(" ");
2668 assert(_cost[i] != max_juint, "cost must be a valid value");
2669 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2670 tty->print_cr("%s %d %s",
2671 ruleName[i], _cost[i], ruleName[_rule[i]] );
2672 }
2673 tty->cr();
2674
2675 for( i=0; i<2; i++ )
2676 if( _kids[i] )
2677 _kids[i]->dump(depth+1);
2678 }
2679 #endif