1 /*
2 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/safepointMechanism.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "vmreg_x86.inline.hpp"
44
45
46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
47 // instructions, to allow sign-masking or sign-bit flipping. They allow
48 // fast versions of NegF/NegD and AbsF/AbsD.
49
50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
52 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
53 // of 128-bits operands for SSE instructions.
54 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
55 // Store the value to a 128-bits operand.
56 operand[0] = lo;
57 operand[1] = hi;
58 return operand;
59 }
60
61 // Buffer for 128-bits masks used by SSE instructions.
62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
63
64 // Static initialization during VM startup.
65 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
67 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
69
70
71
72 NEEDS_CLEANUP // remove this definitions ?
73 const Register IC_Klass = rax; // where the IC klass is cached
74 const Register SYNC_header = rax; // synchronization header
75 const Register SHIFT_count = rcx; // where count for shift operations must be
76
77 #define __ _masm->
78
79
80 static void select_different_registers(Register preserve,
81 Register extra,
82 Register &tmp1,
83 Register &tmp2) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, extra);
89 tmp2 = extra;
90 }
91 assert_different_registers(preserve, tmp1, tmp2);
92 }
93
94
95
96 static void select_different_registers(Register preserve,
97 Register extra,
98 Register &tmp1,
99 Register &tmp2,
100 Register &tmp3) {
101 if (tmp1 == preserve) {
102 assert_different_registers(tmp1, tmp2, tmp3, extra);
103 tmp1 = extra;
104 } else if (tmp2 == preserve) {
105 assert_different_registers(tmp1, tmp2, tmp3, extra);
106 tmp2 = extra;
107 } else if (tmp3 == preserve) {
108 assert_different_registers(tmp1, tmp2, tmp3, extra);
109 tmp3 = extra;
110 }
111 assert_different_registers(preserve, tmp1, tmp2, tmp3);
112 }
113
114
115
116 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
117 if (opr->is_constant()) {
118 LIR_Const* constant = opr->as_constant_ptr();
119 switch (constant->type()) {
120 case T_INT: {
121 return true;
122 }
123
124 default:
125 return false;
126 }
127 }
128 return false;
129 }
130
131
132 LIR_Opr LIR_Assembler::receiverOpr() {
133 return FrameMap::receiver_opr;
134 }
135
136 LIR_Opr LIR_Assembler::osrBufferPointer() {
137 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
138 }
139
140 //--------------fpu register translations-----------------------
141
142
143 address LIR_Assembler::float_constant(float f) {
144 address const_addr = __ float_constant(f);
145 if (const_addr == NULL) {
146 bailout("const section overflow");
147 return __ code()->consts()->start();
148 } else {
149 return const_addr;
150 }
151 }
152
153
154 address LIR_Assembler::double_constant(double d) {
155 address const_addr = __ double_constant(d);
156 if (const_addr == NULL) {
157 bailout("const section overflow");
158 return __ code()->consts()->start();
159 } else {
160 return const_addr;
161 }
162 }
163
164
165 void LIR_Assembler::set_24bit_FPU() {
166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
167 }
168
169 void LIR_Assembler::reset_FPU() {
170 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
171 }
172
173 void LIR_Assembler::fpop() {
174 __ fpop();
175 }
176
177 void LIR_Assembler::fxch(int i) {
178 __ fxch(i);
179 }
180
181 void LIR_Assembler::fld(int i) {
182 __ fld_s(i);
183 }
184
185 void LIR_Assembler::ffree(int i) {
186 __ ffree(i);
187 }
188
189 void LIR_Assembler::breakpoint() {
190 __ int3();
191 }
192
193 void LIR_Assembler::push(LIR_Opr opr) {
194 if (opr->is_single_cpu()) {
195 __ push_reg(opr->as_register());
196 } else if (opr->is_double_cpu()) {
197 NOT_LP64(__ push_reg(opr->as_register_hi()));
198 __ push_reg(opr->as_register_lo());
199 } else if (opr->is_stack()) {
200 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
201 } else if (opr->is_constant()) {
202 LIR_Const* const_opr = opr->as_constant_ptr();
203 if (const_opr->type() == T_OBJECT) {
204 __ push_oop(const_opr->as_jobject());
205 } else if (const_opr->type() == T_INT) {
206 __ push_jint(const_opr->as_jint());
207 } else {
208 ShouldNotReachHere();
209 }
210
211 } else {
212 ShouldNotReachHere();
213 }
214 }
215
216 void LIR_Assembler::pop(LIR_Opr opr) {
217 if (opr->is_single_cpu()) {
218 __ pop_reg(opr->as_register());
219 } else {
220 ShouldNotReachHere();
221 }
222 }
223
224 void LIR_Assembler::getfp(LIR_Opr opr) {
225 __ lea(opr->as_register_lo(), Address(rsp, initial_frame_size_in_bytes() + wordSize)); // + wordSize seems to be required to handle the push rbp before the sub of rsp
226 }
227
228 void LIR_Assembler::getsp(LIR_Opr opr) {
229 __ movptr(opr->as_register_lo(), rsp);
230 }
231
232 #if 0
233 void LIR_Assembler::getpc(LIR_Opr opr) {
234 const char *name + "cont_getPC";
235 address entry = StubRoutines::cont_getPC();
236 __ call_VM_leaf(entry, 0);
237 __ movptr(opr->as_register_lo(), rax);
238 }
239 #endif
240
241 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
242 return addr->base()->is_illegal() && addr->index()->is_illegal();
243 }
244
245 //-------------------------------------------
246
247 Address LIR_Assembler::as_Address(LIR_Address* addr) {
248 return as_Address(addr, rscratch1);
249 }
250
251 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
252 if (addr->base()->is_illegal()) {
253 assert(addr->index()->is_illegal(), "must be illegal too");
254 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
255 if (! __ reachable(laddr)) {
256 __ movptr(tmp, laddr.addr());
257 Address res(tmp, 0);
258 return res;
259 } else {
260 return __ as_Address(laddr);
261 }
262 }
263
264 Register base = addr->base()->as_pointer_register();
265
266 if (addr->index()->is_illegal()) {
267 return Address( base, addr->disp());
268 } else if (addr->index()->is_cpu_register()) {
269 Register index = addr->index()->as_pointer_register();
270 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
271 } else if (addr->index()->is_constant()) {
272 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
273 assert(Assembler::is_simm32(addr_offset), "must be");
274
275 return Address(base, addr_offset);
276 } else {
277 Unimplemented();
278 return Address();
279 }
280 }
281
282
283 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
284 Address base = as_Address(addr);
285 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
286 }
287
288
289 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
290 return as_Address(addr);
291 }
292
293
294 void LIR_Assembler::osr_entry() {
295 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
296 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
297 ValueStack* entry_state = osr_entry->state();
298 int number_of_locks = entry_state->locks_size();
299
300 // we jump here if osr happens with the interpreter
301 // state set up to continue at the beginning of the
302 // loop that triggered osr - in particular, we have
303 // the following registers setup:
304 //
305 // rcx: osr buffer
306 //
307
308 // build frame
309 ciMethod* m = compilation()->method();
310 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
311
312 // OSR buffer is
313 //
314 // locals[nlocals-1..0]
315 // monitors[0..number_of_locks]
316 //
317 // locals is a direct copy of the interpreter frame so in the osr buffer
318 // so first slot in the local array is the last local from the interpreter
319 // and last slot is local[0] (receiver) from the interpreter
320 //
321 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
322 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
323 // in the interpreter frame (the method lock if a sync method)
324
325 // Initialize monitors in the compiled activation.
326 // rcx: pointer to osr buffer
327 //
328 // All other registers are dead at this point and the locals will be
329 // copied into place by code emitted in the IR.
330
331 Register OSR_buf = osrBufferPointer()->as_pointer_register();
332 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
333 int monitor_offset = BytesPerWord * method()->max_locals() +
334 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
335 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
336 // the OSR buffer using 2 word entries: first the lock and then
337 // the oop.
338 for (int i = 0; i < number_of_locks; i++) {
339 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
340 #ifdef ASSERT
341 // verify the interpreter's monitor has a non-null object
342 {
343 Label L;
344 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
345 __ jcc(Assembler::notZero, L);
346 __ stop("locked object is NULL");
347 __ bind(L);
348 }
349 #endif
350 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
351 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
352 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
353 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
354 }
355 }
356 }
357
358
359 // inline cache check; done before the frame is built.
360 int LIR_Assembler::check_icache() {
361 Register receiver = FrameMap::receiver_opr->as_register();
362 Register ic_klass = IC_Klass;
363 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
364 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
365 if (!do_post_padding) {
366 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
367 __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
368 }
369 int offset = __ offset();
370 __ inline_cache_check(receiver, IC_Klass);
371 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
372 if (do_post_padding) {
373 // force alignment after the cache check.
374 // It's been verified to be aligned if !VerifyOops
375 __ align(CodeEntryAlignment);
376 }
377 return offset;
378 }
379
380
381 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
382 jobject o = NULL;
383 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
384 __ movoop(reg, o);
385 patching_epilog(patch, lir_patch_normal, reg, info);
386 }
387
388 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
389 Metadata* o = NULL;
390 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
391 __ mov_metadata(reg, o);
392 patching_epilog(patch, lir_patch_normal, reg, info);
393 }
394
395 // This specifies the rsp decrement needed to build the frame
396 int LIR_Assembler::initial_frame_size_in_bytes() const {
397 // if rounding, must let FrameMap know!
398
399 // The frame_map records size in slots (32bit word)
400
401 // subtract two words to account for return address and link
402 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
403 }
404
405
406 int LIR_Assembler::emit_exception_handler() {
407 // if the last instruction is a call (typically to do a throw which
408 // is coming at the end after block reordering) the return address
409 // must still point into the code area in order to avoid assertion
410 // failures when searching for the corresponding bci => add a nop
411 // (was bug 5/14/1999 - gri)
412 __ nop();
413
414 // generate code for exception handler
415 address handler_base = __ start_a_stub(exception_handler_size());
416 if (handler_base == NULL) {
417 // not enough space left for the handler
418 bailout("exception handler overflow");
419 return -1;
420 }
421
422 int offset = code_offset();
423
424 // the exception oop and pc are in rax, and rdx
425 // no other registers need to be preserved, so invalidate them
426 __ invalidate_registers(false, true, true, false, true, true);
427
428 // check that there is really an exception
429 __ verify_not_null_oop(rax);
430
431 // search an exception handler (rax: exception oop, rdx: throwing pc)
432 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
433 __ should_not_reach_here();
434 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
435 __ end_a_stub();
436
437 return offset;
438 }
439
440
441 // Emit the code to remove the frame from the stack in the exception
442 // unwind path.
443 int LIR_Assembler::emit_unwind_handler() {
444 #ifndef PRODUCT
445 if (CommentedAssembly) {
446 _masm->block_comment("Unwind handler");
447 }
448 #endif
449
450 int offset = code_offset();
451
452 // Fetch the exception from TLS and clear out exception related thread state
453 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
454 NOT_LP64(__ get_thread(rsi));
455 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
456 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
457 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
458
459 __ bind(_unwind_handler_entry);
460 __ verify_not_null_oop(rax);
461 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
462 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
463 }
464
465 // Preform needed unlocking
466 MonitorExitStub* stub = NULL;
467 if (method()->is_synchronized()) {
468 monitor_address(0, FrameMap::rax_opr);
469 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
470 __ unlock_object(rdi, rsi, rax, *stub->entry());
471 __ bind(*stub->continuation());
472 }
473
474 if (compilation()->env()->dtrace_method_probes()) {
475 #ifdef _LP64
476 __ mov(rdi, r15_thread);
477 __ mov_metadata(rsi, method()->constant_encoding());
478 #else
479 __ get_thread(rax);
480 __ movptr(Address(rsp, 0), rax);
481 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
482 #endif
483 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
484 }
485
486 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
487 __ mov(rax, rbx); // Restore the exception
488 }
489
490 // remove the activation and dispatch to the unwind handler
491 __ remove_frame(initial_frame_size_in_bytes());
492 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
493
494 // Emit the slow path assembly
495 if (stub != NULL) {
496 stub->emit_code(this);
497 }
498
499 return offset;
500 }
501
502
503 int LIR_Assembler::emit_deopt_handler() {
504 // if the last instruction is a call (typically to do a throw which
505 // is coming at the end after block reordering) the return address
506 // must still point into the code area in order to avoid assertion
507 // failures when searching for the corresponding bci => add a nop
508 // (was bug 5/14/1999 - gri)
509 __ nop();
510
511 // generate code for exception handler
512 address handler_base = __ start_a_stub(deopt_handler_size());
513 if (handler_base == NULL) {
514 // not enough space left for the handler
515 bailout("deopt handler overflow");
516 return -1;
517 }
518
519 int offset = code_offset();
520 InternalAddress here(__ pc());
521
522 __ pushptr(here.addr());
523 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
524 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
525 __ end_a_stub();
526
527 return offset;
528 }
529
530
531 void LIR_Assembler::return_op(LIR_Opr result) {
532 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
533 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
534 assert(result->fpu() == 0, "result must already be on TOS");
535 }
536
537 // Pop the stack before the safepoint code
538 __ remove_frame(initial_frame_size_in_bytes());
539
540 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
541 __ reserved_stack_check();
542 }
543
544 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
545
546 // Note: we do not need to round double result; float result has the right precision
547 // the poll sets the condition code, but no data registers
548
549 if (SafepointMechanism::uses_thread_local_poll()) {
550 #ifdef _LP64
551 const Register poll_addr = rscratch1;
552 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
553 #else
554 const Register poll_addr = rbx;
555 assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
556 __ get_thread(poll_addr);
557 __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
558 #endif
559 __ relocate(relocInfo::poll_return_type);
560 __ testl(rax, Address(poll_addr, 0));
561 } else {
562 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
563
564 if (Assembler::is_polling_page_far()) {
565 __ lea(rscratch1, polling_page);
566 __ relocate(relocInfo::poll_return_type);
567 __ testl(rax, Address(rscratch1, 0));
568 } else {
569 __ testl(rax, polling_page);
570 }
571 }
572 __ ret(0);
573 }
574
575
576 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
577 guarantee(info != NULL, "Shouldn't be NULL");
578 int offset = __ offset();
579 if (SafepointMechanism::uses_thread_local_poll()) {
580 #ifdef _LP64
581 const Register poll_addr = rscratch1;
582 __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
583 #else
584 assert(tmp->is_cpu_register(), "needed");
585 const Register poll_addr = tmp->as_register();
586 __ get_thread(poll_addr);
587 __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
588 #endif
589 add_debug_info_for_branch(info);
590 __ relocate(relocInfo::poll_type);
591 address pre_pc = __ pc();
592 __ testl(rax, Address(poll_addr, 0));
593 address post_pc = __ pc();
594 guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
595 } else {
596 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
597 if (Assembler::is_polling_page_far()) {
598 __ lea(rscratch1, polling_page);
599 offset = __ offset();
600 add_debug_info_for_branch(info);
601 __ relocate(relocInfo::poll_type);
602 __ testl(rax, Address(rscratch1, 0));
603 } else {
604 add_debug_info_for_branch(info);
605 __ testl(rax, polling_page);
606 }
607 }
608 return offset;
609 }
610
611
612 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
613 if (from_reg != to_reg) __ mov(to_reg, from_reg);
614 }
615
616 void LIR_Assembler::swap_reg(Register a, Register b) {
617 __ xchgptr(a, b);
618 }
619
620
621 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
622 assert(src->is_constant(), "should not call otherwise");
623 assert(dest->is_register(), "should not call otherwise");
624 LIR_Const* c = src->as_constant_ptr();
625
626 switch (c->type()) {
627 case T_INT: {
628 assert(patch_code == lir_patch_none, "no patching handled here");
629 __ movl(dest->as_register(), c->as_jint());
630 break;
631 }
632
633 case T_ADDRESS: {
634 assert(patch_code == lir_patch_none, "no patching handled here");
635 __ movptr(dest->as_register(), c->as_jint());
636 break;
637 }
638
639 case T_LONG: {
640 assert(patch_code == lir_patch_none, "no patching handled here");
641 #ifdef _LP64
642 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
643 #else
644 __ movptr(dest->as_register_lo(), c->as_jint_lo());
645 __ movptr(dest->as_register_hi(), c->as_jint_hi());
646 #endif // _LP64
647 break;
648 }
649
650 case T_OBJECT: {
651 if (patch_code != lir_patch_none) {
652 jobject2reg_with_patching(dest->as_register(), info);
653 } else {
654 __ movoop(dest->as_register(), c->as_jobject());
655 }
656 break;
657 }
658
659 case T_METADATA: {
660 if (patch_code != lir_patch_none) {
661 klass2reg_with_patching(dest->as_register(), info);
662 } else {
663 __ mov_metadata(dest->as_register(), c->as_metadata());
664 }
665 break;
666 }
667
668 case T_FLOAT: {
669 if (dest->is_single_xmm()) {
670 if (c->is_zero_float()) {
671 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
672 } else {
673 __ movflt(dest->as_xmm_float_reg(),
674 InternalAddress(float_constant(c->as_jfloat())));
675 }
676 } else {
677 assert(dest->is_single_fpu(), "must be");
678 assert(dest->fpu_regnr() == 0, "dest must be TOS");
679 if (c->is_zero_float()) {
680 __ fldz();
681 } else if (c->is_one_float()) {
682 __ fld1();
683 } else {
684 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
685 }
686 }
687 break;
688 }
689
690 case T_DOUBLE: {
691 if (dest->is_double_xmm()) {
692 if (c->is_zero_double()) {
693 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
694 } else {
695 __ movdbl(dest->as_xmm_double_reg(),
696 InternalAddress(double_constant(c->as_jdouble())));
697 }
698 } else {
699 assert(dest->is_double_fpu(), "must be");
700 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
701 if (c->is_zero_double()) {
702 __ fldz();
703 } else if (c->is_one_double()) {
704 __ fld1();
705 } else {
706 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
707 }
708 }
709 break;
710 }
711
712 default:
713 ShouldNotReachHere();
714 }
715 }
716
717 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
718 assert(src->is_constant(), "should not call otherwise");
719 assert(dest->is_stack(), "should not call otherwise");
720 LIR_Const* c = src->as_constant_ptr();
721
722 switch (c->type()) {
723 case T_INT: // fall through
724 case T_FLOAT:
725 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
726 break;
727
728 case T_ADDRESS:
729 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
730 break;
731
732 case T_OBJECT:
733 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
734 break;
735
736 case T_LONG: // fall through
737 case T_DOUBLE:
738 #ifdef _LP64
739 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
740 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
741 #else
742 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
743 lo_word_offset_in_bytes), c->as_jint_lo_bits());
744 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
745 hi_word_offset_in_bytes), c->as_jint_hi_bits());
746 #endif // _LP64
747 break;
748
749 default:
750 ShouldNotReachHere();
751 }
752 }
753
754 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
755 assert(src->is_constant(), "should not call otherwise");
756 assert(dest->is_address(), "should not call otherwise");
757 LIR_Const* c = src->as_constant_ptr();
758 LIR_Address* addr = dest->as_address_ptr();
759
760 int null_check_here = code_offset();
761 switch (type) {
762 case T_INT: // fall through
763 case T_FLOAT:
764 __ movl(as_Address(addr), c->as_jint_bits());
765 break;
766
767 case T_ADDRESS:
768 __ movptr(as_Address(addr), c->as_jint_bits());
769 break;
770
771 case T_OBJECT: // fall through
772 case T_ARRAY:
773 if (c->as_jobject() == NULL) {
774 if (UseCompressedOops && !wide) {
775 __ movl(as_Address(addr), (int32_t)NULL_WORD);
776 } else {
777 #ifdef _LP64
778 __ xorptr(rscratch1, rscratch1);
779 null_check_here = code_offset();
780 __ movptr(as_Address(addr), rscratch1);
781 #else
782 __ movptr(as_Address(addr), NULL_WORD);
783 #endif
784 }
785 } else {
786 if (is_literal_address(addr)) {
787 ShouldNotReachHere();
788 __ movoop(as_Address(addr, noreg), c->as_jobject());
789 } else {
790 #ifdef _LP64
791 __ movoop(rscratch1, c->as_jobject());
792 if (UseCompressedOops && !wide) {
793 __ encode_heap_oop(rscratch1);
794 null_check_here = code_offset();
795 __ movl(as_Address_lo(addr), rscratch1);
796 } else {
797 null_check_here = code_offset();
798 __ movptr(as_Address_lo(addr), rscratch1);
799 }
800 #else
801 __ movoop(as_Address(addr), c->as_jobject());
802 #endif
803 }
804 }
805 break;
806
807 case T_LONG: // fall through
808 case T_DOUBLE:
809 #ifdef _LP64
810 if (is_literal_address(addr)) {
811 ShouldNotReachHere();
812 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
813 } else {
814 __ movptr(r10, (intptr_t)c->as_jlong_bits());
815 null_check_here = code_offset();
816 __ movptr(as_Address_lo(addr), r10);
817 }
818 #else
819 // Always reachable in 32bit so this doesn't produce useless move literal
820 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
821 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
822 #endif // _LP64
823 break;
824
825 case T_BOOLEAN: // fall through
826 case T_BYTE:
827 __ movb(as_Address(addr), c->as_jint() & 0xFF);
828 break;
829
830 case T_CHAR: // fall through
831 case T_SHORT:
832 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
833 break;
834
835 default:
836 ShouldNotReachHere();
837 };
838
839 if (info != NULL) {
840 add_debug_info_for_null_check(null_check_here, info);
841 }
842 }
843
844
845 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
846 assert(src->is_register(), "should not call otherwise");
847 assert(dest->is_register(), "should not call otherwise");
848
849 // move between cpu-registers
850 if (dest->is_single_cpu()) {
851 #ifdef _LP64
852 if (src->type() == T_LONG) {
853 // Can do LONG -> OBJECT
854 move_regs(src->as_register_lo(), dest->as_register());
855 return;
856 }
857 #endif
858 assert(src->is_single_cpu(), "must match");
859 if (src->type() == T_OBJECT) {
860 __ verify_oop(src->as_register());
861 }
862 move_regs(src->as_register(), dest->as_register());
863
864 } else if (dest->is_double_cpu()) {
865 #ifdef _LP64
866 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
867 // Surprising to me but we can see move of a long to t_object
868 __ verify_oop(src->as_register());
869 move_regs(src->as_register(), dest->as_register_lo());
870 return;
871 }
872 #endif
873 assert(src->is_double_cpu(), "must match");
874 Register f_lo = src->as_register_lo();
875 Register f_hi = src->as_register_hi();
876 Register t_lo = dest->as_register_lo();
877 Register t_hi = dest->as_register_hi();
878 #ifdef _LP64
879 assert(f_hi == f_lo, "must be same");
880 assert(t_hi == t_lo, "must be same");
881 move_regs(f_lo, t_lo);
882 #else
883 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
884
885
886 if (f_lo == t_hi && f_hi == t_lo) {
887 swap_reg(f_lo, f_hi);
888 } else if (f_hi == t_lo) {
889 assert(f_lo != t_hi, "overwriting register");
890 move_regs(f_hi, t_hi);
891 move_regs(f_lo, t_lo);
892 } else {
893 assert(f_hi != t_lo, "overwriting register");
894 move_regs(f_lo, t_lo);
895 move_regs(f_hi, t_hi);
896 }
897 #endif // LP64
898
899 // special moves from fpu-register to xmm-register
900 // necessary for method results
901 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
902 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
903 __ fld_s(Address(rsp, 0));
904 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
905 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
906 __ fld_d(Address(rsp, 0));
907 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
908 __ fstp_s(Address(rsp, 0));
909 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
910 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
911 __ fstp_d(Address(rsp, 0));
912 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
913
914 // move between xmm-registers
915 } else if (dest->is_single_xmm()) {
916 assert(src->is_single_xmm(), "must match");
917 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
918 } else if (dest->is_double_xmm()) {
919 assert(src->is_double_xmm(), "must match");
920 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
921
922 // move between fpu-registers (no instruction necessary because of fpu-stack)
923 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
924 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
925 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
926 } else {
927 ShouldNotReachHere();
928 }
929 }
930
931 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
932 assert(src->is_register(), "should not call otherwise");
933 assert(dest->is_stack(), "should not call otherwise");
934
935 if (src->is_single_cpu()) {
936 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
937 if (type == T_OBJECT || type == T_ARRAY) {
938 __ verify_oop(src->as_register());
939 __ movptr (dst, src->as_register());
940 } else if (type == T_METADATA) {
941 __ movptr (dst, src->as_register());
942 } else {
943 __ movl (dst, src->as_register());
944 }
945
946 } else if (src->is_double_cpu()) {
947 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
948 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
949 __ movptr (dstLO, src->as_register_lo());
950 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
951
952 } else if (src->is_single_xmm()) {
953 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
954 __ movflt(dst_addr, src->as_xmm_float_reg());
955
956 } else if (src->is_double_xmm()) {
957 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
958 __ movdbl(dst_addr, src->as_xmm_double_reg());
959
960 } else if (src->is_single_fpu()) {
961 assert(src->fpu_regnr() == 0, "argument must be on TOS");
962 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
963 if (pop_fpu_stack) __ fstp_s (dst_addr);
964 else __ fst_s (dst_addr);
965
966 } else if (src->is_double_fpu()) {
967 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
968 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
969 if (pop_fpu_stack) __ fstp_d (dst_addr);
970 else __ fst_d (dst_addr);
971
972 } else {
973 ShouldNotReachHere();
974 }
975 }
976
977
978 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
979 LIR_Address* to_addr = dest->as_address_ptr();
980 PatchingStub* patch = NULL;
981 Register compressed_src = rscratch1;
982
983 if (type == T_ARRAY || type == T_OBJECT) {
984 __ verify_oop(src->as_register());
985 #ifdef _LP64
986 if (UseCompressedOops && !wide) {
987 __ movptr(compressed_src, src->as_register());
988 __ encode_heap_oop(compressed_src);
989 if (patch_code != lir_patch_none) {
990 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
991 }
992 }
993 #endif
994 }
995
996 if (patch_code != lir_patch_none) {
997 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
998 Address toa = as_Address(to_addr);
999 assert(toa.disp() != 0, "must have");
1000 }
1001
1002 int null_check_here = code_offset();
1003 switch (type) {
1004 case T_FLOAT: {
1005 if (src->is_single_xmm()) {
1006 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1007 } else {
1008 assert(src->is_single_fpu(), "must be");
1009 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1010 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1011 else __ fst_s (as_Address(to_addr));
1012 }
1013 break;
1014 }
1015
1016 case T_DOUBLE: {
1017 if (src->is_double_xmm()) {
1018 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1019 } else {
1020 assert(src->is_double_fpu(), "must be");
1021 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1022 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1023 else __ fst_d (as_Address(to_addr));
1024 }
1025 break;
1026 }
1027
1028 case T_ARRAY: // fall through
1029 case T_OBJECT: // fall through
1030 if (UseCompressedOops && !wide) {
1031 __ movl(as_Address(to_addr), compressed_src);
1032 } else {
1033 __ movptr(as_Address(to_addr), src->as_register());
1034 }
1035 break;
1036 case T_METADATA:
1037 // We get here to store a method pointer to the stack to pass to
1038 // a dtrace runtime call. This can't work on 64 bit with
1039 // compressed klass ptrs: T_METADATA can be a compressed klass
1040 // ptr or a 64 bit method pointer.
1041 LP64_ONLY(ShouldNotReachHere());
1042 __ movptr(as_Address(to_addr), src->as_register());
1043 break;
1044 case T_ADDRESS:
1045 __ movptr(as_Address(to_addr), src->as_register());
1046 break;
1047 case T_INT:
1048 __ movl(as_Address(to_addr), src->as_register());
1049 break;
1050
1051 case T_LONG: {
1052 Register from_lo = src->as_register_lo();
1053 Register from_hi = src->as_register_hi();
1054 #ifdef _LP64
1055 __ movptr(as_Address_lo(to_addr), from_lo);
1056 #else
1057 Register base = to_addr->base()->as_register();
1058 Register index = noreg;
1059 if (to_addr->index()->is_register()) {
1060 index = to_addr->index()->as_register();
1061 }
1062 if (base == from_lo || index == from_lo) {
1063 assert(base != from_hi, "can't be");
1064 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1065 __ movl(as_Address_hi(to_addr), from_hi);
1066 if (patch != NULL) {
1067 patching_epilog(patch, lir_patch_high, base, info);
1068 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1069 patch_code = lir_patch_low;
1070 }
1071 __ movl(as_Address_lo(to_addr), from_lo);
1072 } else {
1073 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1074 __ movl(as_Address_lo(to_addr), from_lo);
1075 if (patch != NULL) {
1076 patching_epilog(patch, lir_patch_low, base, info);
1077 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1078 patch_code = lir_patch_high;
1079 }
1080 __ movl(as_Address_hi(to_addr), from_hi);
1081 }
1082 #endif // _LP64
1083 break;
1084 }
1085
1086 case T_BYTE: // fall through
1087 case T_BOOLEAN: {
1088 Register src_reg = src->as_register();
1089 Address dst_addr = as_Address(to_addr);
1090 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1091 __ movb(dst_addr, src_reg);
1092 break;
1093 }
1094
1095 case T_CHAR: // fall through
1096 case T_SHORT:
1097 __ movw(as_Address(to_addr), src->as_register());
1098 break;
1099
1100 default:
1101 ShouldNotReachHere();
1102 }
1103 if (info != NULL) {
1104 add_debug_info_for_null_check(null_check_here, info);
1105 }
1106
1107 if (patch_code != lir_patch_none) {
1108 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1109 }
1110 }
1111
1112
1113 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1114 assert(src->is_stack(), "should not call otherwise");
1115 assert(dest->is_register(), "should not call otherwise");
1116
1117 if (dest->is_single_cpu()) {
1118 if (type == T_ARRAY || type == T_OBJECT) {
1119 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1120 __ verify_oop(dest->as_register());
1121 } else if (type == T_METADATA) {
1122 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1123 } else {
1124 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1125 }
1126
1127 } else if (dest->is_double_cpu()) {
1128 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1129 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1130 __ movptr(dest->as_register_lo(), src_addr_LO);
1131 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1132
1133 } else if (dest->is_single_xmm()) {
1134 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1135 __ movflt(dest->as_xmm_float_reg(), src_addr);
1136
1137 } else if (dest->is_double_xmm()) {
1138 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1139 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1140
1141 } else if (dest->is_single_fpu()) {
1142 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1143 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1144 __ fld_s(src_addr);
1145
1146 } else if (dest->is_double_fpu()) {
1147 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1148 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1149 __ fld_d(src_addr);
1150
1151 } else {
1152 ShouldNotReachHere();
1153 }
1154 }
1155
1156
1157 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1158 if (src->is_single_stack()) {
1159 if (type == T_OBJECT || type == T_ARRAY) {
1160 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1161 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1162 } else {
1163 #ifndef _LP64
1164 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1165 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1166 #else
1167 //no pushl on 64bits
1168 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1169 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1170 #endif
1171 }
1172
1173 } else if (src->is_double_stack()) {
1174 #ifdef _LP64
1175 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1176 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1177 #else
1178 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1179 // push and pop the part at src + wordSize, adding wordSize for the previous push
1180 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1181 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1182 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1183 #endif // _LP64
1184
1185 } else {
1186 ShouldNotReachHere();
1187 }
1188 }
1189
1190
1191 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1192 assert(src->is_address(), "should not call otherwise");
1193 assert(dest->is_register(), "should not call otherwise");
1194
1195 LIR_Address* addr = src->as_address_ptr();
1196 Address from_addr = as_Address(addr);
1197
1198 if (addr->base()->type() == T_OBJECT) {
1199 __ verify_oop(addr->base()->as_pointer_register());
1200 }
1201
1202 switch (type) {
1203 case T_BOOLEAN: // fall through
1204 case T_BYTE: // fall through
1205 case T_CHAR: // fall through
1206 case T_SHORT:
1207 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1208 // on pre P6 processors we may get partial register stalls
1209 // so blow away the value of to_rinfo before loading a
1210 // partial word into it. Do it here so that it precedes
1211 // the potential patch point below.
1212 __ xorptr(dest->as_register(), dest->as_register());
1213 }
1214 break;
1215 default:
1216 break;
1217 }
1218
1219 PatchingStub* patch = NULL;
1220 if (patch_code != lir_patch_none) {
1221 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1222 assert(from_addr.disp() != 0, "must have");
1223 }
1224 if (info != NULL) {
1225 add_debug_info_for_null_check_here(info);
1226 }
1227
1228 switch (type) {
1229 case T_FLOAT: {
1230 if (dest->is_single_xmm()) {
1231 __ movflt(dest->as_xmm_float_reg(), from_addr);
1232 } else {
1233 assert(dest->is_single_fpu(), "must be");
1234 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1235 __ fld_s(from_addr);
1236 }
1237 break;
1238 }
1239
1240 case T_DOUBLE: {
1241 if (dest->is_double_xmm()) {
1242 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1243 } else {
1244 assert(dest->is_double_fpu(), "must be");
1245 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1246 __ fld_d(from_addr);
1247 }
1248 break;
1249 }
1250
1251 case T_OBJECT: // fall through
1252 case T_ARRAY: // fall through
1253 if (UseCompressedOops && !wide) {
1254 __ movl(dest->as_register(), from_addr);
1255 } else {
1256 __ movptr(dest->as_register(), from_addr);
1257 }
1258 break;
1259
1260 case T_ADDRESS:
1261 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1262 __ movl(dest->as_register(), from_addr);
1263 } else {
1264 __ movptr(dest->as_register(), from_addr);
1265 }
1266 break;
1267 case T_INT:
1268 __ movl(dest->as_register(), from_addr);
1269 break;
1270
1271 case T_LONG: {
1272 Register to_lo = dest->as_register_lo();
1273 Register to_hi = dest->as_register_hi();
1274 #ifdef _LP64
1275 __ movptr(to_lo, as_Address_lo(addr));
1276 #else
1277 Register base = addr->base()->as_register();
1278 Register index = noreg;
1279 if (addr->index()->is_register()) {
1280 index = addr->index()->as_register();
1281 }
1282 if ((base == to_lo && index == to_hi) ||
1283 (base == to_hi && index == to_lo)) {
1284 // addresses with 2 registers are only formed as a result of
1285 // array access so this code will never have to deal with
1286 // patches or null checks.
1287 assert(info == NULL && patch == NULL, "must be");
1288 __ lea(to_hi, as_Address(addr));
1289 __ movl(to_lo, Address(to_hi, 0));
1290 __ movl(to_hi, Address(to_hi, BytesPerWord));
1291 } else if (base == to_lo || index == to_lo) {
1292 assert(base != to_hi, "can't be");
1293 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1294 __ movl(to_hi, as_Address_hi(addr));
1295 if (patch != NULL) {
1296 patching_epilog(patch, lir_patch_high, base, info);
1297 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1298 patch_code = lir_patch_low;
1299 }
1300 __ movl(to_lo, as_Address_lo(addr));
1301 } else {
1302 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1303 __ movl(to_lo, as_Address_lo(addr));
1304 if (patch != NULL) {
1305 patching_epilog(patch, lir_patch_low, base, info);
1306 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1307 patch_code = lir_patch_high;
1308 }
1309 __ movl(to_hi, as_Address_hi(addr));
1310 }
1311 #endif // _LP64
1312 break;
1313 }
1314
1315 case T_BOOLEAN: // fall through
1316 case T_BYTE: {
1317 Register dest_reg = dest->as_register();
1318 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1319 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1320 __ movsbl(dest_reg, from_addr);
1321 } else {
1322 __ movb(dest_reg, from_addr);
1323 __ shll(dest_reg, 24);
1324 __ sarl(dest_reg, 24);
1325 }
1326 break;
1327 }
1328
1329 case T_CHAR: {
1330 Register dest_reg = dest->as_register();
1331 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1332 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1333 __ movzwl(dest_reg, from_addr);
1334 } else {
1335 __ movw(dest_reg, from_addr);
1336 }
1337 break;
1338 }
1339
1340 case T_SHORT: {
1341 Register dest_reg = dest->as_register();
1342 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1343 __ movswl(dest_reg, from_addr);
1344 } else {
1345 __ movw(dest_reg, from_addr);
1346 __ shll(dest_reg, 16);
1347 __ sarl(dest_reg, 16);
1348 }
1349 break;
1350 }
1351
1352 default:
1353 ShouldNotReachHere();
1354 }
1355
1356 if (patch != NULL) {
1357 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1358 }
1359
1360 if (type == T_ARRAY || type == T_OBJECT) {
1361 #ifdef _LP64
1362 if (UseCompressedOops && !wide) {
1363 __ decode_heap_oop(dest->as_register());
1364 }
1365 #endif
1366 __ verify_oop(dest->as_register());
1367 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1368 #ifdef _LP64
1369 if (UseCompressedClassPointers) {
1370 __ decode_klass_not_null(dest->as_register());
1371 }
1372 #endif
1373 }
1374 }
1375
1376
1377 NEEDS_CLEANUP; // This could be static?
1378 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1379 int elem_size = type2aelembytes(type);
1380 switch (elem_size) {
1381 case 1: return Address::times_1;
1382 case 2: return Address::times_2;
1383 case 4: return Address::times_4;
1384 case 8: return Address::times_8;
1385 }
1386 ShouldNotReachHere();
1387 return Address::no_scale;
1388 }
1389
1390
1391 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1392 switch (op->code()) {
1393 case lir_idiv:
1394 case lir_irem:
1395 arithmetic_idiv(op->code(),
1396 op->in_opr1(),
1397 op->in_opr2(),
1398 op->in_opr3(),
1399 op->result_opr(),
1400 op->info());
1401 break;
1402 case lir_fmad:
1403 __ fmad(op->result_opr()->as_xmm_double_reg(),
1404 op->in_opr1()->as_xmm_double_reg(),
1405 op->in_opr2()->as_xmm_double_reg(),
1406 op->in_opr3()->as_xmm_double_reg());
1407 break;
1408 case lir_fmaf:
1409 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1410 op->in_opr1()->as_xmm_float_reg(),
1411 op->in_opr2()->as_xmm_float_reg(),
1412 op->in_opr3()->as_xmm_float_reg());
1413 break;
1414 default: ShouldNotReachHere(); break;
1415 }
1416 }
1417
1418 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1419 #ifdef ASSERT
1420 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1421 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1422 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1423 #endif
1424
1425 if (op->cond() == lir_cond_always) {
1426 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1427 __ jmp (*(op->label()));
1428 } else {
1429 Assembler::Condition acond = Assembler::zero;
1430 if (op->code() == lir_cond_float_branch) {
1431 assert(op->ublock() != NULL, "must have unordered successor");
1432 __ jcc(Assembler::parity, *(op->ublock()->label()));
1433 switch(op->cond()) {
1434 case lir_cond_equal: acond = Assembler::equal; break;
1435 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1436 case lir_cond_less: acond = Assembler::below; break;
1437 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1438 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1439 case lir_cond_greater: acond = Assembler::above; break;
1440 default: ShouldNotReachHere();
1441 }
1442 } else {
1443 switch (op->cond()) {
1444 case lir_cond_equal: acond = Assembler::equal; break;
1445 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1446 case lir_cond_less: acond = Assembler::less; break;
1447 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1448 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1449 case lir_cond_greater: acond = Assembler::greater; break;
1450 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1451 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1452 default: ShouldNotReachHere();
1453 }
1454 }
1455 __ jcc(acond,*(op->label()));
1456 }
1457 }
1458
1459 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1460 LIR_Opr src = op->in_opr();
1461 LIR_Opr dest = op->result_opr();
1462
1463 switch (op->bytecode()) {
1464 case Bytecodes::_i2l:
1465 #ifdef _LP64
1466 __ movl2ptr(dest->as_register_lo(), src->as_register());
1467 #else
1468 move_regs(src->as_register(), dest->as_register_lo());
1469 move_regs(src->as_register(), dest->as_register_hi());
1470 __ sarl(dest->as_register_hi(), 31);
1471 #endif // LP64
1472 break;
1473
1474 case Bytecodes::_l2i:
1475 #ifdef _LP64
1476 __ movl(dest->as_register(), src->as_register_lo());
1477 #else
1478 move_regs(src->as_register_lo(), dest->as_register());
1479 #endif
1480 break;
1481
1482 case Bytecodes::_i2b:
1483 move_regs(src->as_register(), dest->as_register());
1484 __ sign_extend_byte(dest->as_register());
1485 break;
1486
1487 case Bytecodes::_i2c:
1488 move_regs(src->as_register(), dest->as_register());
1489 __ andl(dest->as_register(), 0xFFFF);
1490 break;
1491
1492 case Bytecodes::_i2s:
1493 move_regs(src->as_register(), dest->as_register());
1494 __ sign_extend_short(dest->as_register());
1495 break;
1496
1497
1498 case Bytecodes::_f2d:
1499 case Bytecodes::_d2f:
1500 if (dest->is_single_xmm()) {
1501 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1502 } else if (dest->is_double_xmm()) {
1503 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1504 } else {
1505 assert(src->fpu() == dest->fpu(), "register must be equal");
1506 // do nothing (float result is rounded later through spilling)
1507 }
1508 break;
1509
1510 case Bytecodes::_i2f:
1511 case Bytecodes::_i2d:
1512 if (dest->is_single_xmm()) {
1513 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1514 } else if (dest->is_double_xmm()) {
1515 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1516 } else {
1517 assert(dest->fpu() == 0, "result must be on TOS");
1518 __ movl(Address(rsp, 0), src->as_register());
1519 __ fild_s(Address(rsp, 0));
1520 }
1521 break;
1522
1523 case Bytecodes::_f2i:
1524 case Bytecodes::_d2i:
1525 if (src->is_single_xmm()) {
1526 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1527 } else if (src->is_double_xmm()) {
1528 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1529 } else {
1530 assert(src->fpu() == 0, "input must be on TOS");
1531 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1532 __ fist_s(Address(rsp, 0));
1533 __ movl(dest->as_register(), Address(rsp, 0));
1534 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1535 }
1536
1537 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1538 assert(op->stub() != NULL, "stub required");
1539 __ cmpl(dest->as_register(), 0x80000000);
1540 __ jcc(Assembler::equal, *op->stub()->entry());
1541 __ bind(*op->stub()->continuation());
1542 break;
1543
1544 case Bytecodes::_l2f:
1545 case Bytecodes::_l2d:
1546 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1547 assert(dest->fpu() == 0, "result must be on TOS");
1548
1549 __ movptr(Address(rsp, 0), src->as_register_lo());
1550 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1551 __ fild_d(Address(rsp, 0));
1552 // float result is rounded later through spilling
1553 break;
1554
1555 case Bytecodes::_f2l:
1556 case Bytecodes::_d2l:
1557 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1558 assert(src->fpu() == 0, "input must be on TOS");
1559 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1560
1561 // instruction sequence too long to inline it here
1562 {
1563 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1564 }
1565 break;
1566
1567 default: ShouldNotReachHere();
1568 }
1569 }
1570
1571 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1572 if (op->init_check()) {
1573 add_debug_info_for_null_check_here(op->stub()->info());
1574 __ cmpb(Address(op->klass()->as_register(),
1575 InstanceKlass::init_state_offset()),
1576 InstanceKlass::fully_initialized);
1577 __ jcc(Assembler::notEqual, *op->stub()->entry());
1578 }
1579 __ allocate_object(op->obj()->as_register(),
1580 op->tmp1()->as_register(),
1581 op->tmp2()->as_register(),
1582 op->header_size(),
1583 op->object_size(),
1584 op->klass()->as_register(),
1585 *op->stub()->entry());
1586 __ bind(*op->stub()->continuation());
1587 }
1588
1589 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1590 Register len = op->len()->as_register();
1591 LP64_ONLY( __ movslq(len, len); )
1592
1593 if (UseSlowPath ||
1594 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1595 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1596 __ jmp(*op->stub()->entry());
1597 } else {
1598 Register tmp1 = op->tmp1()->as_register();
1599 Register tmp2 = op->tmp2()->as_register();
1600 Register tmp3 = op->tmp3()->as_register();
1601 if (len == tmp1) {
1602 tmp1 = tmp3;
1603 } else if (len == tmp2) {
1604 tmp2 = tmp3;
1605 } else if (len == tmp3) {
1606 // everything is ok
1607 } else {
1608 __ mov(tmp3, len);
1609 }
1610 __ allocate_array(op->obj()->as_register(),
1611 len,
1612 tmp1,
1613 tmp2,
1614 arrayOopDesc::header_size(op->type()),
1615 array_element_size(op->type()),
1616 op->klass()->as_register(),
1617 *op->stub()->entry());
1618 }
1619 __ bind(*op->stub()->continuation());
1620 }
1621
1622 void LIR_Assembler::type_profile_helper(Register mdo,
1623 ciMethodData *md, ciProfileData *data,
1624 Register recv, Label* update_done) {
1625 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1626 Label next_test;
1627 // See if the receiver is receiver[n].
1628 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1629 __ jccb(Assembler::notEqual, next_test);
1630 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1631 __ addptr(data_addr, DataLayout::counter_increment);
1632 __ jmp(*update_done);
1633 __ bind(next_test);
1634 }
1635
1636 // Didn't find receiver; find next empty slot and fill it in
1637 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1638 Label next_test;
1639 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1640 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1641 __ jccb(Assembler::notEqual, next_test);
1642 __ movptr(recv_addr, recv);
1643 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1644 __ jmp(*update_done);
1645 __ bind(next_test);
1646 }
1647 }
1648
1649 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1650 // we always need a stub for the failure case.
1651 CodeStub* stub = op->stub();
1652 Register obj = op->object()->as_register();
1653 Register k_RInfo = op->tmp1()->as_register();
1654 Register klass_RInfo = op->tmp2()->as_register();
1655 Register dst = op->result_opr()->as_register();
1656 ciKlass* k = op->klass();
1657 Register Rtmp1 = noreg;
1658
1659 // check if it needs to be profiled
1660 ciMethodData* md = NULL;
1661 ciProfileData* data = NULL;
1662
1663 if (op->should_profile()) {
1664 ciMethod* method = op->profiled_method();
1665 assert(method != NULL, "Should have method");
1666 int bci = op->profiled_bci();
1667 md = method->method_data_or_null();
1668 assert(md != NULL, "Sanity");
1669 data = md->bci_to_data(bci);
1670 assert(data != NULL, "need data for type check");
1671 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1672 }
1673 Label profile_cast_success, profile_cast_failure;
1674 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1675 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1676
1677 if (obj == k_RInfo) {
1678 k_RInfo = dst;
1679 } else if (obj == klass_RInfo) {
1680 klass_RInfo = dst;
1681 }
1682 if (k->is_loaded() && !UseCompressedClassPointers) {
1683 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1684 } else {
1685 Rtmp1 = op->tmp3()->as_register();
1686 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1687 }
1688
1689 assert_different_registers(obj, k_RInfo, klass_RInfo);
1690
1691 __ cmpptr(obj, (int32_t)NULL_WORD);
1692 if (op->should_profile()) {
1693 Label not_null;
1694 __ jccb(Assembler::notEqual, not_null);
1695 // Object is null; update MDO and exit
1696 Register mdo = klass_RInfo;
1697 __ mov_metadata(mdo, md->constant_encoding());
1698 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1699 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1700 __ orl(data_addr, header_bits);
1701 __ jmp(*obj_is_null);
1702 __ bind(not_null);
1703 } else {
1704 __ jcc(Assembler::equal, *obj_is_null);
1705 }
1706
1707 if (!k->is_loaded()) {
1708 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1709 } else {
1710 #ifdef _LP64
1711 __ mov_metadata(k_RInfo, k->constant_encoding());
1712 #endif // _LP64
1713 }
1714 __ verify_oop(obj);
1715
1716 if (op->fast_check()) {
1717 // get object class
1718 // not a safepoint as obj null check happens earlier
1719 #ifdef _LP64
1720 if (UseCompressedClassPointers) {
1721 __ load_klass(Rtmp1, obj);
1722 __ cmpptr(k_RInfo, Rtmp1);
1723 } else {
1724 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1725 }
1726 #else
1727 if (k->is_loaded()) {
1728 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1729 } else {
1730 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1731 }
1732 #endif
1733 __ jcc(Assembler::notEqual, *failure_target);
1734 // successful cast, fall through to profile or jump
1735 } else {
1736 // get object class
1737 // not a safepoint as obj null check happens earlier
1738 __ load_klass(klass_RInfo, obj);
1739 if (k->is_loaded()) {
1740 // See if we get an immediate positive hit
1741 #ifdef _LP64
1742 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1743 #else
1744 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1745 #endif // _LP64
1746 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1747 __ jcc(Assembler::notEqual, *failure_target);
1748 // successful cast, fall through to profile or jump
1749 } else {
1750 // See if we get an immediate positive hit
1751 __ jcc(Assembler::equal, *success_target);
1752 // check for self
1753 #ifdef _LP64
1754 __ cmpptr(klass_RInfo, k_RInfo);
1755 #else
1756 __ cmpklass(klass_RInfo, k->constant_encoding());
1757 #endif // _LP64
1758 __ jcc(Assembler::equal, *success_target);
1759
1760 __ push(klass_RInfo);
1761 #ifdef _LP64
1762 __ push(k_RInfo);
1763 #else
1764 __ pushklass(k->constant_encoding());
1765 #endif // _LP64
1766 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1767 __ pop(klass_RInfo);
1768 __ pop(klass_RInfo);
1769 // result is a boolean
1770 __ cmpl(klass_RInfo, 0);
1771 __ jcc(Assembler::equal, *failure_target);
1772 // successful cast, fall through to profile or jump
1773 }
1774 } else {
1775 // perform the fast part of the checking logic
1776 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1777 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1778 __ push(klass_RInfo);
1779 __ push(k_RInfo);
1780 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1781 __ pop(klass_RInfo);
1782 __ pop(k_RInfo);
1783 // result is a boolean
1784 __ cmpl(k_RInfo, 0);
1785 __ jcc(Assembler::equal, *failure_target);
1786 // successful cast, fall through to profile or jump
1787 }
1788 }
1789 if (op->should_profile()) {
1790 Register mdo = klass_RInfo, recv = k_RInfo;
1791 __ bind(profile_cast_success);
1792 __ mov_metadata(mdo, md->constant_encoding());
1793 __ load_klass(recv, obj);
1794 Label update_done;
1795 type_profile_helper(mdo, md, data, recv, success);
1796 __ jmp(*success);
1797
1798 __ bind(profile_cast_failure);
1799 __ mov_metadata(mdo, md->constant_encoding());
1800 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1801 __ subptr(counter_addr, DataLayout::counter_increment);
1802 __ jmp(*failure);
1803 }
1804 __ jmp(*success);
1805 }
1806
1807
1808 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1809 LIR_Code code = op->code();
1810 if (code == lir_store_check) {
1811 Register value = op->object()->as_register();
1812 Register array = op->array()->as_register();
1813 Register k_RInfo = op->tmp1()->as_register();
1814 Register klass_RInfo = op->tmp2()->as_register();
1815 Register Rtmp1 = op->tmp3()->as_register();
1816
1817 CodeStub* stub = op->stub();
1818
1819 // check if it needs to be profiled
1820 ciMethodData* md = NULL;
1821 ciProfileData* data = NULL;
1822
1823 if (op->should_profile()) {
1824 ciMethod* method = op->profiled_method();
1825 assert(method != NULL, "Should have method");
1826 int bci = op->profiled_bci();
1827 md = method->method_data_or_null();
1828 assert(md != NULL, "Sanity");
1829 data = md->bci_to_data(bci);
1830 assert(data != NULL, "need data for type check");
1831 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1832 }
1833 Label profile_cast_success, profile_cast_failure, done;
1834 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1835 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1836
1837 __ cmpptr(value, (int32_t)NULL_WORD);
1838 if (op->should_profile()) {
1839 Label not_null;
1840 __ jccb(Assembler::notEqual, not_null);
1841 // Object is null; update MDO and exit
1842 Register mdo = klass_RInfo;
1843 __ mov_metadata(mdo, md->constant_encoding());
1844 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1845 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1846 __ orl(data_addr, header_bits);
1847 __ jmp(done);
1848 __ bind(not_null);
1849 } else {
1850 __ jcc(Assembler::equal, done);
1851 }
1852
1853 add_debug_info_for_null_check_here(op->info_for_exception());
1854 __ load_klass(k_RInfo, array);
1855 __ load_klass(klass_RInfo, value);
1856
1857 // get instance klass (it's already uncompressed)
1858 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1859 // perform the fast part of the checking logic
1860 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1861 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1862 __ push(klass_RInfo);
1863 __ push(k_RInfo);
1864 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1865 __ pop(klass_RInfo);
1866 __ pop(k_RInfo);
1867 // result is a boolean
1868 __ cmpl(k_RInfo, 0);
1869 __ jcc(Assembler::equal, *failure_target);
1870 // fall through to the success case
1871
1872 if (op->should_profile()) {
1873 Register mdo = klass_RInfo, recv = k_RInfo;
1874 __ bind(profile_cast_success);
1875 __ mov_metadata(mdo, md->constant_encoding());
1876 __ load_klass(recv, value);
1877 Label update_done;
1878 type_profile_helper(mdo, md, data, recv, &done);
1879 __ jmpb(done);
1880
1881 __ bind(profile_cast_failure);
1882 __ mov_metadata(mdo, md->constant_encoding());
1883 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1884 __ subptr(counter_addr, DataLayout::counter_increment);
1885 __ jmp(*stub->entry());
1886 }
1887
1888 __ bind(done);
1889 } else
1890 if (code == lir_checkcast) {
1891 Register obj = op->object()->as_register();
1892 Register dst = op->result_opr()->as_register();
1893 Label success;
1894 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1895 __ bind(success);
1896 if (dst != obj) {
1897 __ mov(dst, obj);
1898 }
1899 } else
1900 if (code == lir_instanceof) {
1901 Register obj = op->object()->as_register();
1902 Register dst = op->result_opr()->as_register();
1903 Label success, failure, done;
1904 emit_typecheck_helper(op, &success, &failure, &failure);
1905 __ bind(failure);
1906 __ xorptr(dst, dst);
1907 __ jmpb(done);
1908 __ bind(success);
1909 __ movptr(dst, 1);
1910 __ bind(done);
1911 } else {
1912 ShouldNotReachHere();
1913 }
1914
1915 }
1916
1917
1918 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1919 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1920 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1921 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1922 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1923 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1924 Register addr = op->addr()->as_register();
1925 if (os::is_MP()) {
1926 __ lock();
1927 }
1928 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1929
1930 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1931 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1932 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1933 Register newval = op->new_value()->as_register();
1934 Register cmpval = op->cmp_value()->as_register();
1935 assert(cmpval == rax, "wrong register");
1936 assert(newval != NULL, "new val must be register");
1937 assert(cmpval != newval, "cmp and new values must be in different registers");
1938 assert(cmpval != addr, "cmp and addr must be in different registers");
1939 assert(newval != addr, "new value and addr must be in different registers");
1940
1941 if ( op->code() == lir_cas_obj) {
1942 #ifdef _LP64
1943 if (UseCompressedOops) {
1944 __ encode_heap_oop(cmpval);
1945 __ mov(rscratch1, newval);
1946 __ encode_heap_oop(rscratch1);
1947 if (os::is_MP()) {
1948 __ lock();
1949 }
1950 // cmpval (rax) is implicitly used by this instruction
1951 __ cmpxchgl(rscratch1, Address(addr, 0));
1952 } else
1953 #endif
1954 {
1955 if (os::is_MP()) {
1956 __ lock();
1957 }
1958 __ cmpxchgptr(newval, Address(addr, 0));
1959 }
1960 } else {
1961 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1962 if (os::is_MP()) {
1963 __ lock();
1964 }
1965 __ cmpxchgl(newval, Address(addr, 0));
1966 }
1967 #ifdef _LP64
1968 } else if (op->code() == lir_cas_long) {
1969 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1970 Register newval = op->new_value()->as_register_lo();
1971 Register cmpval = op->cmp_value()->as_register_lo();
1972 assert(cmpval == rax, "wrong register");
1973 assert(newval != NULL, "new val must be register");
1974 assert(cmpval != newval, "cmp and new values must be in different registers");
1975 assert(cmpval != addr, "cmp and addr must be in different registers");
1976 assert(newval != addr, "new value and addr must be in different registers");
1977 if (os::is_MP()) {
1978 __ lock();
1979 }
1980 __ cmpxchgq(newval, Address(addr, 0));
1981 #endif // _LP64
1982 } else {
1983 Unimplemented();
1984 }
1985 }
1986
1987 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1988 Assembler::Condition acond, ncond;
1989 switch (condition) {
1990 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1991 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1992 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1993 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1994 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1995 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1996 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1997 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1998 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1999 ShouldNotReachHere();
2000 }
2001
2002 if (opr1->is_cpu_register()) {
2003 reg2reg(opr1, result);
2004 } else if (opr1->is_stack()) {
2005 stack2reg(opr1, result, result->type());
2006 } else if (opr1->is_constant()) {
2007 const2reg(opr1, result, lir_patch_none, NULL);
2008 } else {
2009 ShouldNotReachHere();
2010 }
2011
2012 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2013 // optimized version that does not require a branch
2014 if (opr2->is_single_cpu()) {
2015 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2016 __ cmov(ncond, result->as_register(), opr2->as_register());
2017 } else if (opr2->is_double_cpu()) {
2018 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2019 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2020 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2021 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2022 } else if (opr2->is_single_stack()) {
2023 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2024 } else if (opr2->is_double_stack()) {
2025 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2026 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2027 } else {
2028 ShouldNotReachHere();
2029 }
2030
2031 } else {
2032 Label skip;
2033 __ jcc (acond, skip);
2034 if (opr2->is_cpu_register()) {
2035 reg2reg(opr2, result);
2036 } else if (opr2->is_stack()) {
2037 stack2reg(opr2, result, result->type());
2038 } else if (opr2->is_constant()) {
2039 const2reg(opr2, result, lir_patch_none, NULL);
2040 } else {
2041 ShouldNotReachHere();
2042 }
2043 __ bind(skip);
2044 }
2045 }
2046
2047
2048 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2049 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2050
2051 if (left->is_single_cpu()) {
2052 assert(left == dest, "left and dest must be equal");
2053 Register lreg = left->as_register();
2054
2055 if (right->is_single_cpu()) {
2056 // cpu register - cpu register
2057 Register rreg = right->as_register();
2058 switch (code) {
2059 case lir_add: __ addl (lreg, rreg); break;
2060 case lir_sub: __ subl (lreg, rreg); break;
2061 case lir_mul: __ imull(lreg, rreg); break;
2062 default: ShouldNotReachHere();
2063 }
2064
2065 } else if (right->is_stack()) {
2066 // cpu register - stack
2067 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2068 switch (code) {
2069 case lir_add: __ addl(lreg, raddr); break;
2070 case lir_sub: __ subl(lreg, raddr); break;
2071 default: ShouldNotReachHere();
2072 }
2073
2074 } else if (right->is_constant()) {
2075 // cpu register - constant
2076 jint c = right->as_constant_ptr()->as_jint();
2077 switch (code) {
2078 case lir_add: {
2079 __ incrementl(lreg, c);
2080 break;
2081 }
2082 case lir_sub: {
2083 __ decrementl(lreg, c);
2084 break;
2085 }
2086 default: ShouldNotReachHere();
2087 }
2088
2089 } else {
2090 ShouldNotReachHere();
2091 }
2092
2093 } else if (left->is_double_cpu()) {
2094 assert(left == dest, "left and dest must be equal");
2095 Register lreg_lo = left->as_register_lo();
2096 Register lreg_hi = left->as_register_hi();
2097
2098 if (right->is_double_cpu()) {
2099 // cpu register - cpu register
2100 Register rreg_lo = right->as_register_lo();
2101 Register rreg_hi = right->as_register_hi();
2102 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2103 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2104 switch (code) {
2105 case lir_add:
2106 __ addptr(lreg_lo, rreg_lo);
2107 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2108 break;
2109 case lir_sub:
2110 __ subptr(lreg_lo, rreg_lo);
2111 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2112 break;
2113 case lir_mul:
2114 #ifdef _LP64
2115 __ imulq(lreg_lo, rreg_lo);
2116 #else
2117 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2118 __ imull(lreg_hi, rreg_lo);
2119 __ imull(rreg_hi, lreg_lo);
2120 __ addl (rreg_hi, lreg_hi);
2121 __ mull (rreg_lo);
2122 __ addl (lreg_hi, rreg_hi);
2123 #endif // _LP64
2124 break;
2125 default:
2126 ShouldNotReachHere();
2127 }
2128
2129 } else if (right->is_constant()) {
2130 // cpu register - constant
2131 #ifdef _LP64
2132 jlong c = right->as_constant_ptr()->as_jlong_bits();
2133 __ movptr(r10, (intptr_t) c);
2134 switch (code) {
2135 case lir_add:
2136 __ addptr(lreg_lo, r10);
2137 break;
2138 case lir_sub:
2139 __ subptr(lreg_lo, r10);
2140 break;
2141 default:
2142 ShouldNotReachHere();
2143 }
2144 #else
2145 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2146 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2147 switch (code) {
2148 case lir_add:
2149 __ addptr(lreg_lo, c_lo);
2150 __ adcl(lreg_hi, c_hi);
2151 break;
2152 case lir_sub:
2153 __ subptr(lreg_lo, c_lo);
2154 __ sbbl(lreg_hi, c_hi);
2155 break;
2156 default:
2157 ShouldNotReachHere();
2158 }
2159 #endif // _LP64
2160
2161 } else {
2162 ShouldNotReachHere();
2163 }
2164
2165 } else if (left->is_single_xmm()) {
2166 assert(left == dest, "left and dest must be equal");
2167 XMMRegister lreg = left->as_xmm_float_reg();
2168
2169 if (right->is_single_xmm()) {
2170 XMMRegister rreg = right->as_xmm_float_reg();
2171 switch (code) {
2172 case lir_add: __ addss(lreg, rreg); break;
2173 case lir_sub: __ subss(lreg, rreg); break;
2174 case lir_mul_strictfp: // fall through
2175 case lir_mul: __ mulss(lreg, rreg); break;
2176 case lir_div_strictfp: // fall through
2177 case lir_div: __ divss(lreg, rreg); break;
2178 default: ShouldNotReachHere();
2179 }
2180 } else {
2181 Address raddr;
2182 if (right->is_single_stack()) {
2183 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2184 } else if (right->is_constant()) {
2185 // hack for now
2186 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2187 } else {
2188 ShouldNotReachHere();
2189 }
2190 switch (code) {
2191 case lir_add: __ addss(lreg, raddr); break;
2192 case lir_sub: __ subss(lreg, raddr); break;
2193 case lir_mul_strictfp: // fall through
2194 case lir_mul: __ mulss(lreg, raddr); break;
2195 case lir_div_strictfp: // fall through
2196 case lir_div: __ divss(lreg, raddr); break;
2197 default: ShouldNotReachHere();
2198 }
2199 }
2200
2201 } else if (left->is_double_xmm()) {
2202 assert(left == dest, "left and dest must be equal");
2203
2204 XMMRegister lreg = left->as_xmm_double_reg();
2205 if (right->is_double_xmm()) {
2206 XMMRegister rreg = right->as_xmm_double_reg();
2207 switch (code) {
2208 case lir_add: __ addsd(lreg, rreg); break;
2209 case lir_sub: __ subsd(lreg, rreg); break;
2210 case lir_mul_strictfp: // fall through
2211 case lir_mul: __ mulsd(lreg, rreg); break;
2212 case lir_div_strictfp: // fall through
2213 case lir_div: __ divsd(lreg, rreg); break;
2214 default: ShouldNotReachHere();
2215 }
2216 } else {
2217 Address raddr;
2218 if (right->is_double_stack()) {
2219 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2220 } else if (right->is_constant()) {
2221 // hack for now
2222 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2223 } else {
2224 ShouldNotReachHere();
2225 }
2226 switch (code) {
2227 case lir_add: __ addsd(lreg, raddr); break;
2228 case lir_sub: __ subsd(lreg, raddr); break;
2229 case lir_mul_strictfp: // fall through
2230 case lir_mul: __ mulsd(lreg, raddr); break;
2231 case lir_div_strictfp: // fall through
2232 case lir_div: __ divsd(lreg, raddr); break;
2233 default: ShouldNotReachHere();
2234 }
2235 }
2236
2237 } else if (left->is_single_fpu()) {
2238 assert(dest->is_single_fpu(), "fpu stack allocation required");
2239
2240 if (right->is_single_fpu()) {
2241 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2242
2243 } else {
2244 assert(left->fpu_regnr() == 0, "left must be on TOS");
2245 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2246
2247 Address raddr;
2248 if (right->is_single_stack()) {
2249 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2250 } else if (right->is_constant()) {
2251 address const_addr = float_constant(right->as_jfloat());
2252 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2253 // hack for now
2254 raddr = __ as_Address(InternalAddress(const_addr));
2255 } else {
2256 ShouldNotReachHere();
2257 }
2258
2259 switch (code) {
2260 case lir_add: __ fadd_s(raddr); break;
2261 case lir_sub: __ fsub_s(raddr); break;
2262 case lir_mul_strictfp: // fall through
2263 case lir_mul: __ fmul_s(raddr); break;
2264 case lir_div_strictfp: // fall through
2265 case lir_div: __ fdiv_s(raddr); break;
2266 default: ShouldNotReachHere();
2267 }
2268 }
2269
2270 } else if (left->is_double_fpu()) {
2271 assert(dest->is_double_fpu(), "fpu stack allocation required");
2272
2273 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2274 // Double values require special handling for strictfp mul/div on x86
2275 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2276 __ fmulp(left->fpu_regnrLo() + 1);
2277 }
2278
2279 if (right->is_double_fpu()) {
2280 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2281
2282 } else {
2283 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2284 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2285
2286 Address raddr;
2287 if (right->is_double_stack()) {
2288 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2289 } else if (right->is_constant()) {
2290 // hack for now
2291 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2292 } else {
2293 ShouldNotReachHere();
2294 }
2295
2296 switch (code) {
2297 case lir_add: __ fadd_d(raddr); break;
2298 case lir_sub: __ fsub_d(raddr); break;
2299 case lir_mul_strictfp: // fall through
2300 case lir_mul: __ fmul_d(raddr); break;
2301 case lir_div_strictfp: // fall through
2302 case lir_div: __ fdiv_d(raddr); break;
2303 default: ShouldNotReachHere();
2304 }
2305 }
2306
2307 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2308 // Double values require special handling for strictfp mul/div on x86
2309 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2310 __ fmulp(dest->fpu_regnrLo() + 1);
2311 }
2312
2313 } else if (left->is_single_stack() || left->is_address()) {
2314 assert(left == dest, "left and dest must be equal");
2315
2316 Address laddr;
2317 if (left->is_single_stack()) {
2318 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2319 } else if (left->is_address()) {
2320 laddr = as_Address(left->as_address_ptr());
2321 } else {
2322 ShouldNotReachHere();
2323 }
2324
2325 if (right->is_single_cpu()) {
2326 Register rreg = right->as_register();
2327 switch (code) {
2328 case lir_add: __ addl(laddr, rreg); break;
2329 case lir_sub: __ subl(laddr, rreg); break;
2330 default: ShouldNotReachHere();
2331 }
2332 } else if (right->is_constant()) {
2333 jint c = right->as_constant_ptr()->as_jint();
2334 switch (code) {
2335 case lir_add: {
2336 __ incrementl(laddr, c);
2337 break;
2338 }
2339 case lir_sub: {
2340 __ decrementl(laddr, c);
2341 break;
2342 }
2343 default: ShouldNotReachHere();
2344 }
2345 } else {
2346 ShouldNotReachHere();
2347 }
2348
2349 } else {
2350 ShouldNotReachHere();
2351 }
2352 }
2353
2354 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2355 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2356 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2357 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2358
2359 bool left_is_tos = (left_index == 0);
2360 bool dest_is_tos = (dest_index == 0);
2361 int non_tos_index = (left_is_tos ? right_index : left_index);
2362
2363 switch (code) {
2364 case lir_add:
2365 if (pop_fpu_stack) __ faddp(non_tos_index);
2366 else if (dest_is_tos) __ fadd (non_tos_index);
2367 else __ fadda(non_tos_index);
2368 break;
2369
2370 case lir_sub:
2371 if (left_is_tos) {
2372 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2373 else if (dest_is_tos) __ fsub (non_tos_index);
2374 else __ fsubra(non_tos_index);
2375 } else {
2376 if (pop_fpu_stack) __ fsubp (non_tos_index);
2377 else if (dest_is_tos) __ fsubr (non_tos_index);
2378 else __ fsuba (non_tos_index);
2379 }
2380 break;
2381
2382 case lir_mul_strictfp: // fall through
2383 case lir_mul:
2384 if (pop_fpu_stack) __ fmulp(non_tos_index);
2385 else if (dest_is_tos) __ fmul (non_tos_index);
2386 else __ fmula(non_tos_index);
2387 break;
2388
2389 case lir_div_strictfp: // fall through
2390 case lir_div:
2391 if (left_is_tos) {
2392 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2393 else if (dest_is_tos) __ fdiv (non_tos_index);
2394 else __ fdivra(non_tos_index);
2395 } else {
2396 if (pop_fpu_stack) __ fdivp (non_tos_index);
2397 else if (dest_is_tos) __ fdivr (non_tos_index);
2398 else __ fdiva (non_tos_index);
2399 }
2400 break;
2401
2402 case lir_rem:
2403 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2404 __ fremr(noreg);
2405 break;
2406
2407 default:
2408 ShouldNotReachHere();
2409 }
2410 }
2411
2412
2413 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2414 if (value->is_double_xmm()) {
2415 switch(code) {
2416 case lir_abs :
2417 {
2418 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2419 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2420 }
2421 __ andpd(dest->as_xmm_double_reg(),
2422 ExternalAddress((address)double_signmask_pool));
2423 }
2424 break;
2425
2426 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2427 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2428 default : ShouldNotReachHere();
2429 }
2430
2431 } else if (value->is_double_fpu()) {
2432 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2433 switch(code) {
2434 case lir_abs : __ fabs() ; break;
2435 case lir_sqrt : __ fsqrt(); break;
2436 default : ShouldNotReachHere();
2437 }
2438 } else {
2439 Unimplemented();
2440 }
2441 }
2442
2443 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2444 // assert(left->destroys_register(), "check");
2445 if (left->is_single_cpu()) {
2446 Register reg = left->as_register();
2447 if (right->is_constant()) {
2448 int val = right->as_constant_ptr()->as_jint();
2449 switch (code) {
2450 case lir_logic_and: __ andl (reg, val); break;
2451 case lir_logic_or: __ orl (reg, val); break;
2452 case lir_logic_xor: __ xorl (reg, val); break;
2453 default: ShouldNotReachHere();
2454 }
2455 } else if (right->is_stack()) {
2456 // added support for stack operands
2457 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2458 switch (code) {
2459 case lir_logic_and: __ andl (reg, raddr); break;
2460 case lir_logic_or: __ orl (reg, raddr); break;
2461 case lir_logic_xor: __ xorl (reg, raddr); break;
2462 default: ShouldNotReachHere();
2463 }
2464 } else {
2465 Register rright = right->as_register();
2466 switch (code) {
2467 case lir_logic_and: __ andptr (reg, rright); break;
2468 case lir_logic_or : __ orptr (reg, rright); break;
2469 case lir_logic_xor: __ xorptr (reg, rright); break;
2470 default: ShouldNotReachHere();
2471 }
2472 }
2473 move_regs(reg, dst->as_register());
2474 } else {
2475 Register l_lo = left->as_register_lo();
2476 Register l_hi = left->as_register_hi();
2477 if (right->is_constant()) {
2478 #ifdef _LP64
2479 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2480 switch (code) {
2481 case lir_logic_and:
2482 __ andq(l_lo, rscratch1);
2483 break;
2484 case lir_logic_or:
2485 __ orq(l_lo, rscratch1);
2486 break;
2487 case lir_logic_xor:
2488 __ xorq(l_lo, rscratch1);
2489 break;
2490 default: ShouldNotReachHere();
2491 }
2492 #else
2493 int r_lo = right->as_constant_ptr()->as_jint_lo();
2494 int r_hi = right->as_constant_ptr()->as_jint_hi();
2495 switch (code) {
2496 case lir_logic_and:
2497 __ andl(l_lo, r_lo);
2498 __ andl(l_hi, r_hi);
2499 break;
2500 case lir_logic_or:
2501 __ orl(l_lo, r_lo);
2502 __ orl(l_hi, r_hi);
2503 break;
2504 case lir_logic_xor:
2505 __ xorl(l_lo, r_lo);
2506 __ xorl(l_hi, r_hi);
2507 break;
2508 default: ShouldNotReachHere();
2509 }
2510 #endif // _LP64
2511 } else {
2512 #ifdef _LP64
2513 Register r_lo;
2514 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2515 r_lo = right->as_register();
2516 } else {
2517 r_lo = right->as_register_lo();
2518 }
2519 #else
2520 Register r_lo = right->as_register_lo();
2521 Register r_hi = right->as_register_hi();
2522 assert(l_lo != r_hi, "overwriting registers");
2523 #endif
2524 switch (code) {
2525 case lir_logic_and:
2526 __ andptr(l_lo, r_lo);
2527 NOT_LP64(__ andptr(l_hi, r_hi);)
2528 break;
2529 case lir_logic_or:
2530 __ orptr(l_lo, r_lo);
2531 NOT_LP64(__ orptr(l_hi, r_hi);)
2532 break;
2533 case lir_logic_xor:
2534 __ xorptr(l_lo, r_lo);
2535 NOT_LP64(__ xorptr(l_hi, r_hi);)
2536 break;
2537 default: ShouldNotReachHere();
2538 }
2539 }
2540
2541 Register dst_lo = dst->as_register_lo();
2542 Register dst_hi = dst->as_register_hi();
2543
2544 #ifdef _LP64
2545 move_regs(l_lo, dst_lo);
2546 #else
2547 if (dst_lo == l_hi) {
2548 assert(dst_hi != l_lo, "overwriting registers");
2549 move_regs(l_hi, dst_hi);
2550 move_regs(l_lo, dst_lo);
2551 } else {
2552 assert(dst_lo != l_hi, "overwriting registers");
2553 move_regs(l_lo, dst_lo);
2554 move_regs(l_hi, dst_hi);
2555 }
2556 #endif // _LP64
2557 }
2558 }
2559
2560
2561 // we assume that rax, and rdx can be overwritten
2562 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2563
2564 assert(left->is_single_cpu(), "left must be register");
2565 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2566 assert(result->is_single_cpu(), "result must be register");
2567
2568 // assert(left->destroys_register(), "check");
2569 // assert(right->destroys_register(), "check");
2570
2571 Register lreg = left->as_register();
2572 Register dreg = result->as_register();
2573
2574 if (right->is_constant()) {
2575 int divisor = right->as_constant_ptr()->as_jint();
2576 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2577 if (code == lir_idiv) {
2578 assert(lreg == rax, "must be rax,");
2579 assert(temp->as_register() == rdx, "tmp register must be rdx");
2580 __ cdql(); // sign extend into rdx:rax
2581 if (divisor == 2) {
2582 __ subl(lreg, rdx);
2583 } else {
2584 __ andl(rdx, divisor - 1);
2585 __ addl(lreg, rdx);
2586 }
2587 __ sarl(lreg, log2_intptr(divisor));
2588 move_regs(lreg, dreg);
2589 } else if (code == lir_irem) {
2590 Label done;
2591 __ mov(dreg, lreg);
2592 __ andl(dreg, 0x80000000 | (divisor - 1));
2593 __ jcc(Assembler::positive, done);
2594 __ decrement(dreg);
2595 __ orl(dreg, ~(divisor - 1));
2596 __ increment(dreg);
2597 __ bind(done);
2598 } else {
2599 ShouldNotReachHere();
2600 }
2601 } else {
2602 Register rreg = right->as_register();
2603 assert(lreg == rax, "left register must be rax,");
2604 assert(rreg != rdx, "right register must not be rdx");
2605 assert(temp->as_register() == rdx, "tmp register must be rdx");
2606
2607 move_regs(lreg, rax);
2608
2609 int idivl_offset = __ corrected_idivl(rreg);
2610 if (ImplicitDiv0Checks) {
2611 add_debug_info_for_div0(idivl_offset, info);
2612 }
2613 if (code == lir_irem) {
2614 move_regs(rdx, dreg); // result is in rdx
2615 } else {
2616 move_regs(rax, dreg);
2617 }
2618 }
2619 }
2620
2621
2622 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2623 if (opr1->is_single_cpu()) {
2624 Register reg1 = opr1->as_register();
2625 if (opr2->is_single_cpu()) {
2626 // cpu register - cpu register
2627 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2628 __ cmpoop(reg1, opr2->as_register());
2629 } else {
2630 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2631 __ cmpl(reg1, opr2->as_register());
2632 }
2633 } else if (opr2->is_stack()) {
2634 // cpu register - stack
2635 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2636 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2637 } else {
2638 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2639 }
2640 } else if (opr2->is_constant()) {
2641 // cpu register - constant
2642 LIR_Const* c = opr2->as_constant_ptr();
2643 if (c->type() == T_INT) {
2644 __ cmpl(reg1, c->as_jint());
2645 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2646 // In 64bit oops are single register
2647 jobject o = c->as_jobject();
2648 if (o == NULL) {
2649 __ cmpptr(reg1, (int32_t)NULL_WORD);
2650 } else {
2651 __ cmpoop(reg1, o);
2652 }
2653 } else {
2654 fatal("unexpected type: %s", basictype_to_str(c->type()));
2655 }
2656 // cpu register - address
2657 } else if (opr2->is_address()) {
2658 if (op->info() != NULL) {
2659 add_debug_info_for_null_check_here(op->info());
2660 }
2661 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2662 } else {
2663 ShouldNotReachHere();
2664 }
2665
2666 } else if(opr1->is_double_cpu()) {
2667 Register xlo = opr1->as_register_lo();
2668 Register xhi = opr1->as_register_hi();
2669 if (opr2->is_double_cpu()) {
2670 #ifdef _LP64
2671 __ cmpptr(xlo, opr2->as_register_lo());
2672 #else
2673 // cpu register - cpu register
2674 Register ylo = opr2->as_register_lo();
2675 Register yhi = opr2->as_register_hi();
2676 __ subl(xlo, ylo);
2677 __ sbbl(xhi, yhi);
2678 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2679 __ orl(xhi, xlo);
2680 }
2681 #endif // _LP64
2682 } else if (opr2->is_constant()) {
2683 // cpu register - constant 0
2684 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2685 #ifdef _LP64
2686 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2687 #else
2688 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2689 __ orl(xhi, xlo);
2690 #endif // _LP64
2691 } else {
2692 ShouldNotReachHere();
2693 }
2694
2695 } else if (opr1->is_single_xmm()) {
2696 XMMRegister reg1 = opr1->as_xmm_float_reg();
2697 if (opr2->is_single_xmm()) {
2698 // xmm register - xmm register
2699 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2700 } else if (opr2->is_stack()) {
2701 // xmm register - stack
2702 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2703 } else if (opr2->is_constant()) {
2704 // xmm register - constant
2705 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2706 } else if (opr2->is_address()) {
2707 // xmm register - address
2708 if (op->info() != NULL) {
2709 add_debug_info_for_null_check_here(op->info());
2710 }
2711 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2712 } else {
2713 ShouldNotReachHere();
2714 }
2715
2716 } else if (opr1->is_double_xmm()) {
2717 XMMRegister reg1 = opr1->as_xmm_double_reg();
2718 if (opr2->is_double_xmm()) {
2719 // xmm register - xmm register
2720 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2721 } else if (opr2->is_stack()) {
2722 // xmm register - stack
2723 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2724 } else if (opr2->is_constant()) {
2725 // xmm register - constant
2726 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2727 } else if (opr2->is_address()) {
2728 // xmm register - address
2729 if (op->info() != NULL) {
2730 add_debug_info_for_null_check_here(op->info());
2731 }
2732 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2733 } else {
2734 ShouldNotReachHere();
2735 }
2736
2737 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2738 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2739 assert(opr2->is_fpu_register(), "both must be registers");
2740 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2741
2742 } else if (opr1->is_address() && opr2->is_constant()) {
2743 LIR_Const* c = opr2->as_constant_ptr();
2744 #ifdef _LP64
2745 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2746 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2747 __ movoop(rscratch1, c->as_jobject());
2748 }
2749 #endif // LP64
2750 if (op->info() != NULL) {
2751 add_debug_info_for_null_check_here(op->info());
2752 }
2753 // special case: address - constant
2754 LIR_Address* addr = opr1->as_address_ptr();
2755 if (c->type() == T_INT) {
2756 __ cmpl(as_Address(addr), c->as_jint());
2757 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2758 #ifdef _LP64
2759 // %%% Make this explode if addr isn't reachable until we figure out a
2760 // better strategy by giving noreg as the temp for as_Address
2761 __ cmpoop(rscratch1, as_Address(addr, noreg));
2762 #else
2763 __ cmpoop(as_Address(addr), c->as_jobject());
2764 #endif // _LP64
2765 } else {
2766 ShouldNotReachHere();
2767 }
2768
2769 } else {
2770 ShouldNotReachHere();
2771 }
2772 }
2773
2774 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2775 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2776 if (left->is_single_xmm()) {
2777 assert(right->is_single_xmm(), "must match");
2778 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2779 } else if (left->is_double_xmm()) {
2780 assert(right->is_double_xmm(), "must match");
2781 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2782
2783 } else {
2784 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2785 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2786
2787 assert(left->fpu() == 0, "left must be on TOS");
2788 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2789 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2790 }
2791 } else {
2792 assert(code == lir_cmp_l2i, "check");
2793 #ifdef _LP64
2794 Label done;
2795 Register dest = dst->as_register();
2796 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2797 __ movl(dest, -1);
2798 __ jccb(Assembler::less, done);
2799 __ set_byte_if_not_zero(dest);
2800 __ movzbl(dest, dest);
2801 __ bind(done);
2802 #else
2803 __ lcmp2int(left->as_register_hi(),
2804 left->as_register_lo(),
2805 right->as_register_hi(),
2806 right->as_register_lo());
2807 move_regs(left->as_register_hi(), dst->as_register());
2808 #endif // _LP64
2809 }
2810 }
2811
2812
2813 void LIR_Assembler::align_call(LIR_Code code) {
2814 if (os::is_MP()) {
2815 // make sure that the displacement word of the call ends up word aligned
2816 int offset = __ offset();
2817 switch (code) {
2818 case lir_static_call:
2819 case lir_optvirtual_call:
2820 case lir_dynamic_call:
2821 offset += NativeCall::displacement_offset;
2822 break;
2823 case lir_icvirtual_call:
2824 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2825 break;
2826 case lir_virtual_call: // currently, sparc-specific for niagara
2827 default: ShouldNotReachHere();
2828 }
2829 __ align(BytesPerWord, offset);
2830 }
2831 }
2832
2833
2834 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2835 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2836 "must be aligned");
2837 __ call(AddressLiteral(op->addr(), rtype));
2838 add_call_info(code_offset(), op->info());
2839 }
2840
2841
2842 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2843 __ ic_call(op->addr());
2844 add_call_info(code_offset(), op->info());
2845 assert(!os::is_MP() ||
2846 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2847 "must be aligned");
2848 }
2849
2850
2851 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2852 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2853 ShouldNotReachHere();
2854 }
2855
2856
2857 void LIR_Assembler::emit_static_call_stub() {
2858 address call_pc = __ pc();
2859 address stub = __ start_a_stub(call_stub_size());
2860 if (stub == NULL) {
2861 bailout("static call stub overflow");
2862 return;
2863 }
2864
2865 int start = __ offset();
2866 if (os::is_MP()) {
2867 // make sure that the displacement word of the call ends up word aligned
2868 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2869 }
2870 __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2871 __ mov_metadata(rbx, (Metadata*)NULL);
2872 // must be set to -1 at code generation time
2873 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2874 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2875 __ jump(RuntimeAddress(__ pc()));
2876
2877 if (UseAOT) {
2878 // Trampoline to aot code
2879 __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2880 #ifdef _LP64
2881 __ mov64(rax, CONST64(0)); // address is zapped till fixup time.
2882 #else
2883 __ movl(rax, 0xdeadffff); // address is zapped till fixup time.
2884 #endif
2885 __ jmp(rax);
2886 }
2887 assert(__ offset() - start <= call_stub_size(), "stub too big");
2888 __ end_a_stub();
2889 }
2890
2891
2892 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2893 assert(exceptionOop->as_register() == rax, "must match");
2894 assert(exceptionPC->as_register() == rdx, "must match");
2895
2896 // exception object is not added to oop map by LinearScan
2897 // (LinearScan assumes that no oops are in fixed registers)
2898 info->add_register_oop(exceptionOop);
2899 Runtime1::StubID unwind_id;
2900
2901 // get current pc information
2902 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2903 int pc_for_athrow_offset = __ offset();
2904 InternalAddress pc_for_athrow(__ pc());
2905 __ lea(exceptionPC->as_register(), pc_for_athrow);
2906 add_call_info(pc_for_athrow_offset, info); // for exception handler
2907
2908 __ verify_not_null_oop(rax);
2909 // search an exception handler (rax: exception oop, rdx: throwing pc)
2910 if (compilation()->has_fpu_code()) {
2911 unwind_id = Runtime1::handle_exception_id;
2912 } else {
2913 unwind_id = Runtime1::handle_exception_nofpu_id;
2914 }
2915 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2916
2917 // enough room for two byte trap
2918 __ nop();
2919 }
2920
2921
2922 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2923 assert(exceptionOop->as_register() == rax, "must match");
2924
2925 __ jmp(_unwind_handler_entry);
2926 }
2927
2928
2929 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2930
2931 // optimized version for linear scan:
2932 // * count must be already in ECX (guaranteed by LinearScan)
2933 // * left and dest must be equal
2934 // * tmp must be unused
2935 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2936 assert(left == dest, "left and dest must be equal");
2937 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2938
2939 if (left->is_single_cpu()) {
2940 Register value = left->as_register();
2941 assert(value != SHIFT_count, "left cannot be ECX");
2942
2943 switch (code) {
2944 case lir_shl: __ shll(value); break;
2945 case lir_shr: __ sarl(value); break;
2946 case lir_ushr: __ shrl(value); break;
2947 default: ShouldNotReachHere();
2948 }
2949 } else if (left->is_double_cpu()) {
2950 Register lo = left->as_register_lo();
2951 Register hi = left->as_register_hi();
2952 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2953 #ifdef _LP64
2954 switch (code) {
2955 case lir_shl: __ shlptr(lo); break;
2956 case lir_shr: __ sarptr(lo); break;
2957 case lir_ushr: __ shrptr(lo); break;
2958 default: ShouldNotReachHere();
2959 }
2960 #else
2961
2962 switch (code) {
2963 case lir_shl: __ lshl(hi, lo); break;
2964 case lir_shr: __ lshr(hi, lo, true); break;
2965 case lir_ushr: __ lshr(hi, lo, false); break;
2966 default: ShouldNotReachHere();
2967 }
2968 #endif // LP64
2969 } else {
2970 ShouldNotReachHere();
2971 }
2972 }
2973
2974
2975 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2976 if (dest->is_single_cpu()) {
2977 // first move left into dest so that left is not destroyed by the shift
2978 Register value = dest->as_register();
2979 count = count & 0x1F; // Java spec
2980
2981 move_regs(left->as_register(), value);
2982 switch (code) {
2983 case lir_shl: __ shll(value, count); break;
2984 case lir_shr: __ sarl(value, count); break;
2985 case lir_ushr: __ shrl(value, count); break;
2986 default: ShouldNotReachHere();
2987 }
2988 } else if (dest->is_double_cpu()) {
2989 #ifndef _LP64
2990 Unimplemented();
2991 #else
2992 // first move left into dest so that left is not destroyed by the shift
2993 Register value = dest->as_register_lo();
2994 count = count & 0x1F; // Java spec
2995
2996 move_regs(left->as_register_lo(), value);
2997 switch (code) {
2998 case lir_shl: __ shlptr(value, count); break;
2999 case lir_shr: __ sarptr(value, count); break;
3000 case lir_ushr: __ shrptr(value, count); break;
3001 default: ShouldNotReachHere();
3002 }
3003 #endif // _LP64
3004 } else {
3005 ShouldNotReachHere();
3006 }
3007 }
3008
3009
3010 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3011 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3012 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3013 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3014 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3015 }
3016
3017
3018 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3019 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3020 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3021 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3022 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3023 }
3024
3025
3026 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3027 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3028 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3029 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3030 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3031 }
3032
3033
3034 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
3035 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3036 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3037 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3038 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3039 }
3040
3041
3042 // This code replaces a call to arraycopy; no exception may
3043 // be thrown in this code, they must be thrown in the System.arraycopy
3044 // activation frame; we could save some checks if this would not be the case
3045 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3046 ciArrayKlass* default_type = op->expected_type();
3047 Register src = op->src()->as_register();
3048 Register dst = op->dst()->as_register();
3049 Register src_pos = op->src_pos()->as_register();
3050 Register dst_pos = op->dst_pos()->as_register();
3051 Register length = op->length()->as_register();
3052 Register tmp = op->tmp()->as_register();
3053
3054 CodeStub* stub = op->stub();
3055 int flags = op->flags();
3056 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3057 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3058
3059 // if we don't know anything, just go through the generic arraycopy
3060 if (default_type == NULL) {
3061 Label done;
3062 // save outgoing arguments on stack in case call to System.arraycopy is needed
3063 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3064 // for interpreter calling conventions. Now we have to do it in new style conventions.
3065 // For the moment until C1 gets the new register allocator I just force all the
3066 // args to the right place (except the register args) and then on the back side
3067 // reload the register args properly if we go slow path. Yuck
3068
3069 // These are proper for the calling convention
3070 store_parameter(length, 2);
3071 store_parameter(dst_pos, 1);
3072 store_parameter(dst, 0);
3073
3074 // these are just temporary placements until we need to reload
3075 store_parameter(src_pos, 3);
3076 store_parameter(src, 4);
3077 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3078
3079 address copyfunc_addr = StubRoutines::generic_arraycopy();
3080 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3081
3082 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3083 #ifdef _LP64
3084 // The arguments are in java calling convention so we can trivially shift them to C
3085 // convention
3086 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3087 __ mov(c_rarg0, j_rarg0);
3088 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3089 __ mov(c_rarg1, j_rarg1);
3090 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3091 __ mov(c_rarg2, j_rarg2);
3092 assert_different_registers(c_rarg3, j_rarg4);
3093 __ mov(c_rarg3, j_rarg3);
3094 #ifdef _WIN64
3095 // Allocate abi space for args but be sure to keep stack aligned
3096 __ subptr(rsp, 6*wordSize);
3097 store_parameter(j_rarg4, 4);
3098 #ifndef PRODUCT
3099 if (PrintC1Statistics) {
3100 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3101 }
3102 #endif
3103 __ call(RuntimeAddress(copyfunc_addr));
3104 __ addptr(rsp, 6*wordSize);
3105 #else
3106 __ mov(c_rarg4, j_rarg4);
3107 #ifndef PRODUCT
3108 if (PrintC1Statistics) {
3109 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3110 }
3111 #endif
3112 __ call(RuntimeAddress(copyfunc_addr));
3113 #endif // _WIN64
3114 #else
3115 __ push(length);
3116 __ push(dst_pos);
3117 __ push(dst);
3118 __ push(src_pos);
3119 __ push(src);
3120
3121 #ifndef PRODUCT
3122 if (PrintC1Statistics) {
3123 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3124 }
3125 #endif
3126 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3127
3128 #endif // _LP64
3129
3130 __ cmpl(rax, 0);
3131 __ jcc(Assembler::equal, *stub->continuation());
3132
3133 __ mov(tmp, rax);
3134 __ xorl(tmp, -1);
3135
3136 // Reload values from the stack so they are where the stub
3137 // expects them.
3138 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3139 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3140 __ movptr (length, Address(rsp, 2*BytesPerWord));
3141 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3142 __ movptr (src, Address(rsp, 4*BytesPerWord));
3143
3144 __ subl(length, tmp);
3145 __ addl(src_pos, tmp);
3146 __ addl(dst_pos, tmp);
3147 __ jmp(*stub->entry());
3148
3149 __ bind(*stub->continuation());
3150 return;
3151 }
3152
3153 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3154
3155 int elem_size = type2aelembytes(basic_type);
3156 Address::ScaleFactor scale;
3157
3158 switch (elem_size) {
3159 case 1 :
3160 scale = Address::times_1;
3161 break;
3162 case 2 :
3163 scale = Address::times_2;
3164 break;
3165 case 4 :
3166 scale = Address::times_4;
3167 break;
3168 case 8 :
3169 scale = Address::times_8;
3170 break;
3171 default:
3172 scale = Address::no_scale;
3173 ShouldNotReachHere();
3174 }
3175
3176 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3177 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3178 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3179 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3180
3181 // length and pos's are all sign extended at this point on 64bit
3182
3183 // test for NULL
3184 if (flags & LIR_OpArrayCopy::src_null_check) {
3185 __ testptr(src, src);
3186 __ jcc(Assembler::zero, *stub->entry());
3187 }
3188 if (flags & LIR_OpArrayCopy::dst_null_check) {
3189 __ testptr(dst, dst);
3190 __ jcc(Assembler::zero, *stub->entry());
3191 }
3192
3193 // If the compiler was not able to prove that exact type of the source or the destination
3194 // of the arraycopy is an array type, check at runtime if the source or the destination is
3195 // an instance type.
3196 if (flags & LIR_OpArrayCopy::type_check) {
3197 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3198 __ load_klass(tmp, dst);
3199 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3200 __ jcc(Assembler::greaterEqual, *stub->entry());
3201 }
3202
3203 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3204 __ load_klass(tmp, src);
3205 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3206 __ jcc(Assembler::greaterEqual, *stub->entry());
3207 }
3208 }
3209
3210 // check if negative
3211 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3212 __ testl(src_pos, src_pos);
3213 __ jcc(Assembler::less, *stub->entry());
3214 }
3215 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3216 __ testl(dst_pos, dst_pos);
3217 __ jcc(Assembler::less, *stub->entry());
3218 }
3219
3220 if (flags & LIR_OpArrayCopy::src_range_check) {
3221 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3222 __ cmpl(tmp, src_length_addr);
3223 __ jcc(Assembler::above, *stub->entry());
3224 }
3225 if (flags & LIR_OpArrayCopy::dst_range_check) {
3226 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3227 __ cmpl(tmp, dst_length_addr);
3228 __ jcc(Assembler::above, *stub->entry());
3229 }
3230
3231 if (flags & LIR_OpArrayCopy::length_positive_check) {
3232 __ testl(length, length);
3233 __ jcc(Assembler::less, *stub->entry());
3234 }
3235
3236 #ifdef _LP64
3237 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3238 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3239 #endif
3240
3241 if (flags & LIR_OpArrayCopy::type_check) {
3242 // We don't know the array types are compatible
3243 if (basic_type != T_OBJECT) {
3244 // Simple test for basic type arrays
3245 if (UseCompressedClassPointers) {
3246 __ movl(tmp, src_klass_addr);
3247 __ cmpl(tmp, dst_klass_addr);
3248 } else {
3249 __ movptr(tmp, src_klass_addr);
3250 __ cmpptr(tmp, dst_klass_addr);
3251 }
3252 __ jcc(Assembler::notEqual, *stub->entry());
3253 } else {
3254 // For object arrays, if src is a sub class of dst then we can
3255 // safely do the copy.
3256 Label cont, slow;
3257
3258 __ push(src);
3259 __ push(dst);
3260
3261 __ load_klass(src, src);
3262 __ load_klass(dst, dst);
3263
3264 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3265
3266 __ push(src);
3267 __ push(dst);
3268 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3269 __ pop(dst);
3270 __ pop(src);
3271
3272 __ cmpl(src, 0);
3273 __ jcc(Assembler::notEqual, cont);
3274
3275 __ bind(slow);
3276 __ pop(dst);
3277 __ pop(src);
3278
3279 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3280 if (copyfunc_addr != NULL) { // use stub if available
3281 // src is not a sub class of dst so we have to do a
3282 // per-element check.
3283
3284 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3285 if ((flags & mask) != mask) {
3286 // Check that at least both of them object arrays.
3287 assert(flags & mask, "one of the two should be known to be an object array");
3288
3289 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3290 __ load_klass(tmp, src);
3291 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3292 __ load_klass(tmp, dst);
3293 }
3294 int lh_offset = in_bytes(Klass::layout_helper_offset());
3295 Address klass_lh_addr(tmp, lh_offset);
3296 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3297 __ cmpl(klass_lh_addr, objArray_lh);
3298 __ jcc(Assembler::notEqual, *stub->entry());
3299 }
3300
3301 // Spill because stubs can use any register they like and it's
3302 // easier to restore just those that we care about.
3303 store_parameter(dst, 0);
3304 store_parameter(dst_pos, 1);
3305 store_parameter(length, 2);
3306 store_parameter(src_pos, 3);
3307 store_parameter(src, 4);
3308
3309 #ifndef _LP64
3310 __ movptr(tmp, dst_klass_addr);
3311 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3312 __ push(tmp);
3313 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3314 __ push(tmp);
3315 __ push(length);
3316 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3317 __ push(tmp);
3318 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3319 __ push(tmp);
3320
3321 __ call_VM_leaf(copyfunc_addr, 5);
3322 #else
3323 __ movl2ptr(length, length); //higher 32bits must be null
3324
3325 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3326 assert_different_registers(c_rarg0, dst, dst_pos, length);
3327 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3328 assert_different_registers(c_rarg1, dst, length);
3329
3330 __ mov(c_rarg2, length);
3331 assert_different_registers(c_rarg2, dst);
3332
3333 #ifdef _WIN64
3334 // Allocate abi space for args but be sure to keep stack aligned
3335 __ subptr(rsp, 6*wordSize);
3336 __ load_klass(c_rarg3, dst);
3337 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3338 store_parameter(c_rarg3, 4);
3339 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3340 __ call(RuntimeAddress(copyfunc_addr));
3341 __ addptr(rsp, 6*wordSize);
3342 #else
3343 __ load_klass(c_rarg4, dst);
3344 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3345 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3346 __ call(RuntimeAddress(copyfunc_addr));
3347 #endif
3348
3349 #endif
3350
3351 #ifndef PRODUCT
3352 if (PrintC1Statistics) {
3353 Label failed;
3354 __ testl(rax, rax);
3355 __ jcc(Assembler::notZero, failed);
3356 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3357 __ bind(failed);
3358 }
3359 #endif
3360
3361 __ testl(rax, rax);
3362 __ jcc(Assembler::zero, *stub->continuation());
3363
3364 #ifndef PRODUCT
3365 if (PrintC1Statistics) {
3366 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3367 }
3368 #endif
3369
3370 __ mov(tmp, rax);
3371
3372 __ xorl(tmp, -1);
3373
3374 // Restore previously spilled arguments
3375 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3376 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3377 __ movptr (length, Address(rsp, 2*BytesPerWord));
3378 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3379 __ movptr (src, Address(rsp, 4*BytesPerWord));
3380
3381
3382 __ subl(length, tmp);
3383 __ addl(src_pos, tmp);
3384 __ addl(dst_pos, tmp);
3385 }
3386
3387 __ jmp(*stub->entry());
3388
3389 __ bind(cont);
3390 __ pop(dst);
3391 __ pop(src);
3392 }
3393 }
3394
3395 #ifdef ASSERT
3396 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3397 // Sanity check the known type with the incoming class. For the
3398 // primitive case the types must match exactly with src.klass and
3399 // dst.klass each exactly matching the default type. For the
3400 // object array case, if no type check is needed then either the
3401 // dst type is exactly the expected type and the src type is a
3402 // subtype which we can't check or src is the same array as dst
3403 // but not necessarily exactly of type default_type.
3404 Label known_ok, halt;
3405 __ mov_metadata(tmp, default_type->constant_encoding());
3406 #ifdef _LP64
3407 if (UseCompressedClassPointers) {
3408 __ encode_klass_not_null(tmp);
3409 }
3410 #endif
3411
3412 if (basic_type != T_OBJECT) {
3413
3414 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3415 else __ cmpptr(tmp, dst_klass_addr);
3416 __ jcc(Assembler::notEqual, halt);
3417 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3418 else __ cmpptr(tmp, src_klass_addr);
3419 __ jcc(Assembler::equal, known_ok);
3420 } else {
3421 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3422 else __ cmpptr(tmp, dst_klass_addr);
3423 __ jcc(Assembler::equal, known_ok);
3424 __ cmpptr(src, dst);
3425 __ jcc(Assembler::equal, known_ok);
3426 }
3427 __ bind(halt);
3428 __ stop("incorrect type information in arraycopy");
3429 __ bind(known_ok);
3430 }
3431 #endif
3432
3433 #ifndef PRODUCT
3434 if (PrintC1Statistics) {
3435 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3436 }
3437 #endif
3438
3439 #ifdef _LP64
3440 assert_different_registers(c_rarg0, dst, dst_pos, length);
3441 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3442 assert_different_registers(c_rarg1, length);
3443 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3444 __ mov(c_rarg2, length);
3445
3446 #else
3447 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3448 store_parameter(tmp, 0);
3449 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3450 store_parameter(tmp, 1);
3451 store_parameter(length, 2);
3452 #endif // _LP64
3453
3454 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3455 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3456 const char *name;
3457 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3458 __ call_VM_leaf(entry, 0);
3459
3460 __ bind(*stub->continuation());
3461 }
3462
3463 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3464 assert(op->crc()->is_single_cpu(), "crc must be register");
3465 assert(op->val()->is_single_cpu(), "byte value must be register");
3466 assert(op->result_opr()->is_single_cpu(), "result must be register");
3467 Register crc = op->crc()->as_register();
3468 Register val = op->val()->as_register();
3469 Register res = op->result_opr()->as_register();
3470
3471 assert_different_registers(val, crc, res);
3472
3473 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3474 __ notl(crc); // ~crc
3475 __ update_byte_crc32(crc, val, res);
3476 __ notl(crc); // ~crc
3477 __ mov(res, crc);
3478 }
3479
3480 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3481 Register obj = op->obj_opr()->as_register(); // may not be an oop
3482 Register hdr = op->hdr_opr()->as_register();
3483 Register lock = op->lock_opr()->as_register();
3484 if (!UseFastLocking) {
3485 __ jmp(*op->stub()->entry());
3486 } else if (op->code() == lir_lock) {
3487 Register scratch = noreg;
3488 if (UseBiasedLocking) {
3489 scratch = op->scratch_opr()->as_register();
3490 }
3491 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3492 // add debug info for NullPointerException only if one is possible
3493 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3494 if (op->info() != NULL) {
3495 add_debug_info_for_null_check(null_check_offset, op->info());
3496 }
3497 // done
3498 } else if (op->code() == lir_unlock) {
3499 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3500 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3501 } else {
3502 Unimplemented();
3503 }
3504 __ bind(*op->stub()->continuation());
3505 }
3506
3507
3508 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3509 ciMethod* method = op->profiled_method();
3510 int bci = op->profiled_bci();
3511 ciMethod* callee = op->profiled_callee();
3512
3513 // Update counter for all call types
3514 ciMethodData* md = method->method_data_or_null();
3515 assert(md != NULL, "Sanity");
3516 ciProfileData* data = md->bci_to_data(bci);
3517 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3518 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3519 Register mdo = op->mdo()->as_register();
3520 __ mov_metadata(mdo, md->constant_encoding());
3521 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3522 // Perform additional virtual call profiling for invokevirtual and
3523 // invokeinterface bytecodes
3524 if (op->should_profile_receiver_type()) {
3525 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3526 Register recv = op->recv()->as_register();
3527 assert_different_registers(mdo, recv);
3528 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3529 ciKlass* known_klass = op->known_holder();
3530 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3531 // We know the type that will be seen at this call site; we can
3532 // statically update the MethodData* rather than needing to do
3533 // dynamic tests on the receiver type
3534
3535 // NOTE: we should probably put a lock around this search to
3536 // avoid collisions by concurrent compilations
3537 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3538 uint i;
3539 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3540 ciKlass* receiver = vc_data->receiver(i);
3541 if (known_klass->equals(receiver)) {
3542 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3543 __ addptr(data_addr, DataLayout::counter_increment);
3544 return;
3545 }
3546 }
3547
3548 // Receiver type not found in profile data; select an empty slot
3549
3550 // Note that this is less efficient than it should be because it
3551 // always does a write to the receiver part of the
3552 // VirtualCallData rather than just the first time
3553 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3554 ciKlass* receiver = vc_data->receiver(i);
3555 if (receiver == NULL) {
3556 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3557 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3558 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3559 __ addptr(data_addr, DataLayout::counter_increment);
3560 return;
3561 }
3562 }
3563 } else {
3564 __ load_klass(recv, recv);
3565 Label update_done;
3566 type_profile_helper(mdo, md, data, recv, &update_done);
3567 // Receiver did not match any saved receiver and there is no empty row for it.
3568 // Increment total counter to indicate polymorphic case.
3569 __ addptr(counter_addr, DataLayout::counter_increment);
3570
3571 __ bind(update_done);
3572 }
3573 } else {
3574 // Static call
3575 __ addptr(counter_addr, DataLayout::counter_increment);
3576 }
3577 }
3578
3579 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3580 Register obj = op->obj()->as_register();
3581 Register tmp = op->tmp()->as_pointer_register();
3582 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3583 ciKlass* exact_klass = op->exact_klass();
3584 intptr_t current_klass = op->current_klass();
3585 bool not_null = op->not_null();
3586 bool no_conflict = op->no_conflict();
3587
3588 Label update, next, none;
3589
3590 bool do_null = !not_null;
3591 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3592 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3593
3594 assert(do_null || do_update, "why are we here?");
3595 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3596
3597 __ verify_oop(obj);
3598
3599 if (tmp != obj) {
3600 __ mov(tmp, obj);
3601 }
3602 if (do_null) {
3603 __ testptr(tmp, tmp);
3604 __ jccb(Assembler::notZero, update);
3605 if (!TypeEntries::was_null_seen(current_klass)) {
3606 __ orptr(mdo_addr, TypeEntries::null_seen);
3607 }
3608 if (do_update) {
3609 #ifndef ASSERT
3610 __ jmpb(next);
3611 }
3612 #else
3613 __ jmp(next);
3614 }
3615 } else {
3616 __ testptr(tmp, tmp);
3617 __ jccb(Assembler::notZero, update);
3618 __ stop("unexpect null obj");
3619 #endif
3620 }
3621
3622 __ bind(update);
3623
3624 if (do_update) {
3625 #ifdef ASSERT
3626 if (exact_klass != NULL) {
3627 Label ok;
3628 __ load_klass(tmp, tmp);
3629 __ push(tmp);
3630 __ mov_metadata(tmp, exact_klass->constant_encoding());
3631 __ cmpptr(tmp, Address(rsp, 0));
3632 __ jccb(Assembler::equal, ok);
3633 __ stop("exact klass and actual klass differ");
3634 __ bind(ok);
3635 __ pop(tmp);
3636 }
3637 #endif
3638 if (!no_conflict) {
3639 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3640 if (exact_klass != NULL) {
3641 __ mov_metadata(tmp, exact_klass->constant_encoding());
3642 } else {
3643 __ load_klass(tmp, tmp);
3644 }
3645
3646 __ xorptr(tmp, mdo_addr);
3647 __ testptr(tmp, TypeEntries::type_klass_mask);
3648 // klass seen before, nothing to do. The unknown bit may have been
3649 // set already but no need to check.
3650 __ jccb(Assembler::zero, next);
3651
3652 __ testptr(tmp, TypeEntries::type_unknown);
3653 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3654
3655 if (TypeEntries::is_type_none(current_klass)) {
3656 __ cmpptr(mdo_addr, 0);
3657 __ jccb(Assembler::equal, none);
3658 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3659 __ jccb(Assembler::equal, none);
3660 // There is a chance that the checks above (re-reading profiling
3661 // data from memory) fail if another thread has just set the
3662 // profiling to this obj's klass
3663 __ xorptr(tmp, mdo_addr);
3664 __ testptr(tmp, TypeEntries::type_klass_mask);
3665 __ jccb(Assembler::zero, next);
3666 }
3667 } else {
3668 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3669 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3670
3671 __ movptr(tmp, mdo_addr);
3672 __ testptr(tmp, TypeEntries::type_unknown);
3673 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3674 }
3675
3676 // different than before. Cannot keep accurate profile.
3677 __ orptr(mdo_addr, TypeEntries::type_unknown);
3678
3679 if (TypeEntries::is_type_none(current_klass)) {
3680 __ jmpb(next);
3681
3682 __ bind(none);
3683 // first time here. Set profile type.
3684 __ movptr(mdo_addr, tmp);
3685 }
3686 } else {
3687 // There's a single possible klass at this profile point
3688 assert(exact_klass != NULL, "should be");
3689 if (TypeEntries::is_type_none(current_klass)) {
3690 __ mov_metadata(tmp, exact_klass->constant_encoding());
3691 __ xorptr(tmp, mdo_addr);
3692 __ testptr(tmp, TypeEntries::type_klass_mask);
3693 #ifdef ASSERT
3694 __ jcc(Assembler::zero, next);
3695
3696 {
3697 Label ok;
3698 __ push(tmp);
3699 __ cmpptr(mdo_addr, 0);
3700 __ jcc(Assembler::equal, ok);
3701 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3702 __ jcc(Assembler::equal, ok);
3703 // may have been set by another thread
3704 __ mov_metadata(tmp, exact_klass->constant_encoding());
3705 __ xorptr(tmp, mdo_addr);
3706 __ testptr(tmp, TypeEntries::type_mask);
3707 __ jcc(Assembler::zero, ok);
3708
3709 __ stop("unexpected profiling mismatch");
3710 __ bind(ok);
3711 __ pop(tmp);
3712 }
3713 #else
3714 __ jccb(Assembler::zero, next);
3715 #endif
3716 // first time here. Set profile type.
3717 __ movptr(mdo_addr, tmp);
3718 } else {
3719 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3720 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3721
3722 __ movptr(tmp, mdo_addr);
3723 __ testptr(tmp, TypeEntries::type_unknown);
3724 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3725
3726 __ orptr(mdo_addr, TypeEntries::type_unknown);
3727 }
3728 }
3729
3730 __ bind(next);
3731 }
3732 }
3733
3734 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3735 Unimplemented();
3736 }
3737
3738
3739 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3740 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3741 }
3742
3743
3744 void LIR_Assembler::align_backward_branch_target() {
3745 __ align(BytesPerWord);
3746 }
3747
3748
3749 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3750 if (left->is_single_cpu()) {
3751 __ negl(left->as_register());
3752 move_regs(left->as_register(), dest->as_register());
3753
3754 } else if (left->is_double_cpu()) {
3755 Register lo = left->as_register_lo();
3756 #ifdef _LP64
3757 Register dst = dest->as_register_lo();
3758 __ movptr(dst, lo);
3759 __ negptr(dst);
3760 #else
3761 Register hi = left->as_register_hi();
3762 __ lneg(hi, lo);
3763 if (dest->as_register_lo() == hi) {
3764 assert(dest->as_register_hi() != lo, "destroying register");
3765 move_regs(hi, dest->as_register_hi());
3766 move_regs(lo, dest->as_register_lo());
3767 } else {
3768 move_regs(lo, dest->as_register_lo());
3769 move_regs(hi, dest->as_register_hi());
3770 }
3771 #endif // _LP64
3772
3773 } else if (dest->is_single_xmm()) {
3774 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3775 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3776 }
3777 if (UseAVX > 0) {
3778 __ vnegatess(dest->as_xmm_float_reg(), dest->as_xmm_float_reg(),
3779 ExternalAddress((address)float_signflip_pool));
3780 } else {
3781 __ xorps(dest->as_xmm_float_reg(),
3782 ExternalAddress((address)float_signflip_pool));
3783 }
3784 } else if (dest->is_double_xmm()) {
3785 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3786 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3787 }
3788 if (UseAVX > 0) {
3789 __ vnegatesd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg(),
3790 ExternalAddress((address)double_signflip_pool));
3791 } else {
3792 __ xorpd(dest->as_xmm_double_reg(),
3793 ExternalAddress((address)double_signflip_pool));
3794 }
3795 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3796 assert(left->fpu() == 0, "arg must be on TOS");
3797 assert(dest->fpu() == 0, "dest must be TOS");
3798 __ fchs();
3799
3800 } else {
3801 ShouldNotReachHere();
3802 }
3803 }
3804
3805
3806 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3807 assert(src->is_address(), "must be an address");
3808 assert(dest->is_register(), "must be a register");
3809
3810 PatchingStub* patch = NULL;
3811 if (patch_code != lir_patch_none) {
3812 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3813 }
3814
3815 Register reg = dest->as_pointer_register();
3816 LIR_Address* addr = src->as_address_ptr();
3817 __ lea(reg, as_Address(addr));
3818
3819 if (patch != NULL) {
3820 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3821 }
3822 }
3823
3824
3825
3826 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3827 assert(!tmp->is_valid(), "don't need temporary");
3828 __ call(RuntimeAddress(dest));
3829 if (info != NULL) {
3830 add_call_info_here(info);
3831 }
3832 }
3833
3834
3835 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3836 assert(type == T_LONG, "only for volatile long fields");
3837
3838 if (info != NULL) {
3839 add_debug_info_for_null_check_here(info);
3840 }
3841
3842 if (src->is_double_xmm()) {
3843 if (dest->is_double_cpu()) {
3844 #ifdef _LP64
3845 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3846 #else
3847 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3848 __ psrlq(src->as_xmm_double_reg(), 32);
3849 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3850 #endif // _LP64
3851 } else if (dest->is_double_stack()) {
3852 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3853 } else if (dest->is_address()) {
3854 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3855 } else {
3856 ShouldNotReachHere();
3857 }
3858
3859 } else if (dest->is_double_xmm()) {
3860 if (src->is_double_stack()) {
3861 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3862 } else if (src->is_address()) {
3863 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3864 } else {
3865 ShouldNotReachHere();
3866 }
3867
3868 } else if (src->is_double_fpu()) {
3869 assert(src->fpu_regnrLo() == 0, "must be TOS");
3870 if (dest->is_double_stack()) {
3871 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3872 } else if (dest->is_address()) {
3873 __ fistp_d(as_Address(dest->as_address_ptr()));
3874 } else {
3875 ShouldNotReachHere();
3876 }
3877
3878 } else if (dest->is_double_fpu()) {
3879 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3880 if (src->is_double_stack()) {
3881 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3882 } else if (src->is_address()) {
3883 __ fild_d(as_Address(src->as_address_ptr()));
3884 } else {
3885 ShouldNotReachHere();
3886 }
3887 } else {
3888 ShouldNotReachHere();
3889 }
3890 }
3891
3892 #ifdef ASSERT
3893 // emit run-time assertion
3894 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3895 assert(op->code() == lir_assert, "must be");
3896
3897 if (op->in_opr1()->is_valid()) {
3898 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3899 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3900 } else {
3901 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3902 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3903 }
3904
3905 Label ok;
3906 if (op->condition() != lir_cond_always) {
3907 Assembler::Condition acond = Assembler::zero;
3908 switch (op->condition()) {
3909 case lir_cond_equal: acond = Assembler::equal; break;
3910 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3911 case lir_cond_less: acond = Assembler::less; break;
3912 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3913 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3914 case lir_cond_greater: acond = Assembler::greater; break;
3915 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3916 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3917 default: ShouldNotReachHere();
3918 }
3919 __ jcc(acond, ok);
3920 }
3921 if (op->halt()) {
3922 const char* str = __ code_string(op->msg());
3923 __ stop(str);
3924 } else {
3925 breakpoint();
3926 }
3927 __ bind(ok);
3928 }
3929 #endif
3930
3931 void LIR_Assembler::membar() {
3932 // QQQ sparc TSO uses this,
3933 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3934 }
3935
3936 void LIR_Assembler::membar_acquire() {
3937 // No x86 machines currently require load fences
3938 }
3939
3940 void LIR_Assembler::membar_release() {
3941 // No x86 machines currently require store fences
3942 }
3943
3944 void LIR_Assembler::membar_loadload() {
3945 // no-op
3946 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3947 }
3948
3949 void LIR_Assembler::membar_storestore() {
3950 // no-op
3951 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3952 }
3953
3954 void LIR_Assembler::membar_loadstore() {
3955 // no-op
3956 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3957 }
3958
3959 void LIR_Assembler::membar_storeload() {
3960 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3961 }
3962
3963 void LIR_Assembler::on_spin_wait() {
3964 __ pause ();
3965 }
3966
3967 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3968 assert(result_reg->is_register(), "check");
3969 #ifdef _LP64
3970 // __ get_thread(result_reg->as_register_lo());
3971 __ mov(result_reg->as_register(), r15_thread);
3972 #else
3973 __ get_thread(result_reg->as_register());
3974 #endif // _LP64
3975 }
3976
3977
3978 void LIR_Assembler::peephole(LIR_List*) {
3979 // do nothing for now
3980 }
3981
3982 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3983 assert(data == dest, "xchg/xadd uses only 2 operands");
3984
3985 if (data->type() == T_INT) {
3986 if (code == lir_xadd) {
3987 if (os::is_MP()) {
3988 __ lock();
3989 }
3990 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3991 } else {
3992 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3993 }
3994 } else if (data->is_oop()) {
3995 assert (code == lir_xchg, "xadd for oops");
3996 Register obj = data->as_register();
3997 #ifdef _LP64
3998 if (UseCompressedOops) {
3999 __ encode_heap_oop(obj);
4000 __ xchgl(obj, as_Address(src->as_address_ptr()));
4001 __ decode_heap_oop(obj);
4002 } else {
4003 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4004 }
4005 #else
4006 __ xchgl(obj, as_Address(src->as_address_ptr()));
4007 #endif
4008 } else if (data->type() == T_LONG) {
4009 #ifdef _LP64
4010 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4011 if (code == lir_xadd) {
4012 if (os::is_MP()) {
4013 __ lock();
4014 }
4015 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4016 } else {
4017 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4018 }
4019 #else
4020 ShouldNotReachHere();
4021 #endif
4022 } else {
4023 ShouldNotReachHere();
4024 }
4025 }
4026
4027 #undef __