1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 public:
42 // Support for VM calls
43 //
44 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
45 // may customize this version by overriding it for its purposes (e.g., to save/restore
46 // additional registers when doing a VM call).
47
48 virtual void call_VM_leaf_base(
49 address entry_point, // the entry point
50 int number_of_arguments // the number of arguments to pop after the call
51 );
52
53 protected:
54 // This is the base routine called by the different versions of call_VM. The interpreter
55 // may customize this version by overriding it for its purposes (e.g., to save/restore
56 // additional registers when doing a VM call).
57 //
58 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
59 // returns the register which contains the thread upon return. If a thread register has been
60 // specified, the return value will correspond to that register. If no last_java_sp is specified
61 // (noreg) than rsp will be used instead.
62 virtual void call_VM_base( // returns the register containing the thread upon return
63 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
64 Register java_thread, // the thread if computed before ; use noreg otherwise
65 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
68 bool check_exceptions // whether to check for pending exceptions after return
69 );
70
71 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
72
73 // helpers for FPU flag access
74 // tmp is a temporary register, if none is available use noreg
75 void save_rax (Register tmp);
76 void restore_rax(Register tmp);
77
78 public:
79 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
80
81 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
82 // The implementation is only non-empty for the InterpreterMacroAssembler,
83 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
84 virtual void check_and_handle_popframe(Register java_thread);
85 virtual void check_and_handle_earlyret(Register java_thread);
86
87 Address as_Address(AddressLiteral adr);
88 Address as_Address(ArrayAddress adr);
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // special instructions for EVEX
160 void setvectmask(Register dst, Register src);
161 void restorevectmask();
162
163 // Support optimal SSE move instructions.
164 void movflt(XMMRegister dst, XMMRegister src) {
165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
166 else { movss (dst, src); return; }
167 }
168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
169 void movflt(XMMRegister dst, AddressLiteral src);
170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
171
172 void movdbl(XMMRegister dst, XMMRegister src) {
173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
174 else { movsd (dst, src); return; }
175 }
176
177 void movdbl(XMMRegister dst, AddressLiteral src);
178
179 void movdbl(XMMRegister dst, Address src) {
180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
181 else { movlpd(dst, src); return; }
182 }
183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
184
185 void incrementl(AddressLiteral dst);
186 void incrementl(ArrayAddress dst);
187
188 void incrementq(AddressLiteral dst);
189
190 // Alignment
191 void align(int modulus);
192 void align(int modulus, int target);
193
194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
195 void fat_nop();
196
197 // Stack frame creation/removal
198 void enter();
199 void leave();
200
201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
202 // The pointer will be loaded into the thread register.
203 void get_thread(Register thread);
204
205
206 // Support for VM calls
207 //
208 // It is imperative that all calls into the VM are handled via the call_VM macros.
209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
211
212
213 void call_VM(Register oop_result,
214 address entry_point,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2, Register arg_3,
227 bool check_exceptions = true);
228
229 // Overloadings with last_Java_sp
230 void call_VM(Register oop_result,
231 Register last_java_sp,
232 address entry_point,
233 int number_of_arguments = 0,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 Register arg_1, bool
239 check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2, Register arg_3,
249 bool check_exceptions = true);
250
251 void get_vm_result (Register oop_result, Register thread);
252 void get_vm_result_2(Register metadata_result, Register thread);
253
254 // These always tightly bind to MacroAssembler::call_VM_base
255 // bypassing the virtual implementation
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
261
262 void call_VM_leaf0(address entry_point);
263 void call_VM_leaf(address entry_point,
264 int number_of_arguments = 0);
265 void call_VM_leaf(address entry_point,
266 Register arg_1);
267 void call_VM_leaf(address entry_point,
268 Register arg_1, Register arg_2);
269 void call_VM_leaf(address entry_point,
270 Register arg_1, Register arg_2, Register arg_3);
271
272 // These always tightly bind to MacroAssembler::call_VM_leaf_base
273 // bypassing the virtual implementation
274 void super_call_VM_leaf(address entry_point);
275 void super_call_VM_leaf(address entry_point, Register arg_1);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
279
280 // last Java Frame (fills frame anchor)
281 void set_last_Java_frame(Register thread,
282 Register last_java_sp,
283 Register last_java_fp,
284 address last_java_pc);
285
286 // thread in the default location (r15_thread on 64bit)
287 void set_last_Java_frame(Register last_java_sp,
288 Register last_java_fp,
289 address last_java_pc);
290
291 void reset_last_Java_frame(Register thread, bool clear_fp);
292
293 // thread in the default location (r15_thread on 64bit)
294 void reset_last_Java_frame(bool clear_fp);
295
296 // jobjects
297 void clear_jweak_tag(Register possibly_jweak);
298 void resolve_jobject(Register value, Register thread, Register tmp);
299
300 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
301 void c2bool(Register x);
302
303 // C++ bool manipulation
304
305 void movbool(Register dst, Address src);
306 void movbool(Address dst, bool boolconst);
307 void movbool(Address dst, Register src);
308 void testbool(Register dst);
309
310 void resolve_oop_handle(Register result, Register tmp = rscratch2);
311 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
312
313 // oop manipulations
314 void load_klass(Register dst, Register src);
315 void store_klass(Register dst, Register src);
316
317 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
318 Register tmp1, Register thread_tmp);
319 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
320 Register tmp1, Register tmp2);
321
322 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
323 Register thread_tmp = noreg, DecoratorSet decorators = 0);
324 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
325 Register thread_tmp = noreg, DecoratorSet decorators = 0);
326 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
327 Register tmp2 = noreg, DecoratorSet decorators = 0);
328
329 // Used for storing NULL. All other oop constants should be
330 // stored using routines that take a jobject.
331 void store_heap_oop_null(Address dst);
332
333 void load_prototype_header(Register dst, Register src);
334
335 #ifdef _LP64
336 void store_klass_gap(Register dst, Register src);
337
338 // This dummy is to prevent a call to store_heap_oop from
339 // converting a zero (like NULL) into a Register by giving
340 // the compiler two choices it can't resolve
341
342 void store_heap_oop(Address dst, void* dummy);
343
344 void encode_heap_oop(Register r);
345 void decode_heap_oop(Register r);
346 void encode_heap_oop_not_null(Register r);
347 void decode_heap_oop_not_null(Register r);
348 void encode_heap_oop_not_null(Register dst, Register src);
349 void decode_heap_oop_not_null(Register dst, Register src);
350
351 void set_narrow_oop(Register dst, jobject obj);
352 void set_narrow_oop(Address dst, jobject obj);
353 void cmp_narrow_oop(Register dst, jobject obj);
354 void cmp_narrow_oop(Address dst, jobject obj);
355
356 void encode_klass_not_null(Register r);
357 void decode_klass_not_null(Register r);
358 void encode_klass_not_null(Register dst, Register src);
359 void decode_klass_not_null(Register dst, Register src);
360 void set_narrow_klass(Register dst, Klass* k);
361 void set_narrow_klass(Address dst, Klass* k);
362 void cmp_narrow_klass(Register dst, Klass* k);
363 void cmp_narrow_klass(Address dst, Klass* k);
364
365 // Returns the byte size of the instructions generated by decode_klass_not_null()
366 // when compressed klass pointers are being used.
367 static int instr_size_for_decode_klass_not_null();
368
369 // if heap base register is used - reinit it with the correct value
370 void reinit_heapbase();
371
372 DEBUG_ONLY(void verify_heapbase(const char* msg);)
373
374 #endif // _LP64
375
376 // Int division/remainder for Java
377 // (as idivl, but checks for special case as described in JVM spec.)
378 // returns idivl instruction offset for implicit exception handling
379 int corrected_idivl(Register reg);
380
381 // Long division/remainder for Java
382 // (as idivq, but checks for special case as described in JVM spec.)
383 // returns idivq instruction offset for implicit exception handling
384 int corrected_idivq(Register reg);
385
386 void int3();
387
388 // Long operation macros for a 32bit cpu
389 // Long negation for Java
390 void lneg(Register hi, Register lo);
391
392 // Long multiplication for Java
393 // (destroys contents of eax, ebx, ecx and edx)
394 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
395
396 // Long shifts for Java
397 // (semantics as described in JVM spec.)
398 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
399 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
400
401 // Long compare for Java
402 // (semantics as described in JVM spec.)
403 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
404
405
406 // misc
407
408 // Sign extension
409 void sign_extend_short(Register reg);
410 void sign_extend_byte(Register reg);
411
412 // Division by power of 2, rounding towards 0
413 void division_with_shift(Register reg, int shift_value);
414
415 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
416 //
417 // CF (corresponds to C0) if x < y
418 // PF (corresponds to C2) if unordered
419 // ZF (corresponds to C3) if x = y
420 //
421 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
422 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
423 void fcmp(Register tmp);
424 // Variant of the above which allows y to be further down the stack
425 // and which only pops x and y if specified. If pop_right is
426 // specified then pop_left must also be specified.
427 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
428
429 // Floating-point comparison for Java
430 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
431 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
432 // (semantics as described in JVM spec.)
433 void fcmp2int(Register dst, bool unordered_is_less);
434 // Variant of the above which allows y to be further down the stack
435 // and which only pops x and y if specified. If pop_right is
436 // specified then pop_left must also be specified.
437 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
438
439 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
440 // tmp is a temporary register, if none is available use noreg
441 void fremr(Register tmp);
442
443 // dst = c = a * b + c
444 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
445 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
446
447 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
448 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
449 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
450 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
451
452
453 // same as fcmp2int, but using SSE2
454 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
455 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
456
457 // branch to L if FPU flag C2 is set/not set
458 // tmp is a temporary register, if none is available use noreg
459 void jC2 (Register tmp, Label& L);
460 void jnC2(Register tmp, Label& L);
461
462 // Pop ST (ffree & fincstp combined)
463 void fpop();
464
465 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
466 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
467 void load_float(Address src);
468
469 // Store float value to 'address'. If UseSSE >= 1, the value is stored
470 // from register xmm0. Otherwise, the value is stored from the FPU stack.
471 void store_float(Address dst);
472
473 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
474 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
475 void load_double(Address src);
476
477 // Store double value to 'address'. If UseSSE >= 2, the value is stored
478 // from register xmm0. Otherwise, the value is stored from the FPU stack.
479 void store_double(Address dst);
480
481 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
482 void push_fTOS();
483
484 // pops double TOS element from CPU stack and pushes on FPU stack
485 void pop_fTOS();
486
487 void empty_FPU_stack();
488
489 void push_IU_state();
490 void pop_IU_state();
491
492 void push_FPU_state();
493 void pop_FPU_state();
494
495 void push_CPU_state();
496 void pop_CPU_state();
497
498 DEBUG_ONLY(void stop_if_in_cont(Register cont_reg, const char* name);)
499
500 // Round up to a power of two
501 void round_to(Register reg, int modulus);
502
503 // Callee saved registers handling
504 void push_callee_saved_registers();
505 void pop_callee_saved_registers();
506
507 // allocation
508 void eden_allocate(
509 Register obj, // result: pointer to object after successful allocation
510 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
511 int con_size_in_bytes, // object size in bytes if known at compile time
512 Register t1, // temp register
513 Label& slow_case // continuation point if fast allocation fails
514 );
515 void tlab_allocate(
516 Register obj, // result: pointer to object after successful allocation
517 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
518 int con_size_in_bytes, // object size in bytes if known at compile time
519 Register t1, // temp register
520 Register t2, // temp register
521 Label& slow_case // continuation point if fast allocation fails
522 );
523 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
524
525 void incr_allocated_bytes(Register thread,
526 Register var_size_in_bytes, int con_size_in_bytes,
527 Register t1 = noreg);
528
529 // interface method calling
530 void lookup_interface_method(Register recv_klass,
531 Register intf_klass,
532 RegisterOrConstant itable_index,
533 Register method_result,
534 Register scan_temp,
535 Label& no_such_interface,
536 bool return_method = true);
537
538 // virtual method calling
539 void lookup_virtual_method(Register recv_klass,
540 RegisterOrConstant vtable_index,
541 Register method_result);
542
543 // Test sub_klass against super_klass, with fast and slow paths.
544
545 // The fast path produces a tri-state answer: yes / no / maybe-slow.
546 // One of the three labels can be NULL, meaning take the fall-through.
547 // If super_check_offset is -1, the value is loaded up from super_klass.
548 // No registers are killed, except temp_reg.
549 void check_klass_subtype_fast_path(Register sub_klass,
550 Register super_klass,
551 Register temp_reg,
552 Label* L_success,
553 Label* L_failure,
554 Label* L_slow_path,
555 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
556
557 // The rest of the type check; must be wired to a corresponding fast path.
558 // It does not repeat the fast path logic, so don't use it standalone.
559 // The temp_reg and temp2_reg can be noreg, if no temps are available.
560 // Updates the sub's secondary super cache as necessary.
561 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
562 void check_klass_subtype_slow_path(Register sub_klass,
563 Register super_klass,
564 Register temp_reg,
565 Register temp2_reg,
566 Label* L_success,
567 Label* L_failure,
568 bool set_cond_codes = false);
569
570 // Simplified, combined version, good for typical uses.
571 // Falls through on failure.
572 void check_klass_subtype(Register sub_klass,
573 Register super_klass,
574 Register temp_reg,
575 Label& L_success);
576
577 // method handles (JSR 292)
578 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
579
580 //----
581 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
582
583 // Debugging
584
585 // only if +VerifyOops
586 // TODO: Make these macros with file and line like sparc version!
587 void verify_oop(Register reg, const char* s = "broken oop");
588 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
589
590 // TODO: verify method and klass metadata (compare against vptr?)
591 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
592 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
593
594 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
595 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
596
597 // only if +VerifyFPU
598 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
599
600 // Verify or restore cpu control state after JNI call
601 void restore_cpu_control_state_after_jni();
602
603 // prints msg, dumps registers and stops execution
604 void stop(const char* msg);
605
606 // prints msg and continues
607 void warn(const char* msg);
608
609 // dumps registers and other state
610 void print_state();
611
612 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
613 static void debug64(char* msg, int64_t pc, int64_t regs[]);
614 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
615 static void print_state64(int64_t pc, int64_t regs[]);
616
617 void os_breakpoint();
618
619 void untested() { stop("untested"); }
620
621 void unimplemented(const char* what = "");
622
623 void should_not_reach_here() { stop("should not reach here"); }
624
625 void print_CPU_state();
626
627 // Stack overflow checking
628 void bang_stack_with_offset(int offset) {
629 // stack grows down, caller passes positive offset
630 assert(offset > 0, "must bang with negative offset");
631 movl(Address(rsp, (-offset)), rax);
632 }
633
634 // Writes to stack successive pages until offset reached to check for
635 // stack overflow + shadow pages. Also, clobbers tmp
636 void bang_stack_size(Register size, Register tmp);
637
638 // Check for reserved stack access in method being exited (for JIT)
639 void reserved_stack_check();
640
641 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
642 Register tmp,
643 int offset);
644
645 // Support for serializing memory accesses between threads
646 void serialize_memory(Register thread, Register tmp);
647
648 // If thread_reg is != noreg the code assumes the register passed contains
649 // the thread (required on 64 bit).
650 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
651
652 void verify_tlab();
653
654 // Biased locking support
655 // lock_reg and obj_reg must be loaded up with the appropriate values.
656 // swap_reg must be rax, and is killed.
657 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
658 // be killed; if not supplied, push/pop will be used internally to
659 // allocate a temporary (inefficient, avoid if possible).
660 // Optional slow case is for implementations (interpreter and C1) which branch to
661 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
662 // Returns offset of first potentially-faulting instruction for null
663 // check info (currently consumed only by C1). If
664 // swap_reg_contains_mark is true then returns -1 as it is assumed
665 // the calling code has already passed any potential faults.
666 int biased_locking_enter(Register lock_reg, Register obj_reg,
667 Register swap_reg, Register tmp_reg,
668 bool swap_reg_contains_mark,
669 Label& done, Label* slow_case = NULL,
670 BiasedLockingCounters* counters = NULL);
671 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
672 #ifdef COMPILER2
673 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
674 // See full desription in macroAssembler_x86.cpp.
675 void fast_lock(Register obj, Register box, Register tmp,
676 Register scr, Register cx1, Register cx2,
677 BiasedLockingCounters* counters,
678 RTMLockingCounters* rtm_counters,
679 RTMLockingCounters* stack_rtm_counters,
680 Metadata* method_data,
681 bool use_rtm, bool profile_rtm);
682 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
683 #if INCLUDE_RTM_OPT
684 void rtm_counters_update(Register abort_status, Register rtm_counters);
685 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
686 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
687 RTMLockingCounters* rtm_counters,
688 Metadata* method_data);
689 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
690 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
691 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
692 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
693 void rtm_stack_locking(Register obj, Register tmp, Register scr,
694 Register retry_on_abort_count,
695 RTMLockingCounters* stack_rtm_counters,
696 Metadata* method_data, bool profile_rtm,
697 Label& DONE_LABEL, Label& IsInflated);
698 void rtm_inflated_locking(Register obj, Register box, Register tmp,
699 Register scr, Register retry_on_busy_count,
700 Register retry_on_abort_count,
701 RTMLockingCounters* rtm_counters,
702 Metadata* method_data, bool profile_rtm,
703 Label& DONE_LABEL);
704 #endif
705 #endif
706
707 Condition negate_condition(Condition cond);
708
709 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
710 // operands. In general the names are modified to avoid hiding the instruction in Assembler
711 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
712 // here in MacroAssembler. The major exception to this rule is call
713
714 // Arithmetics
715
716
717 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
718 void addptr(Address dst, Register src);
719
720 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
721 void addptr(Register dst, int32_t src);
722 void addptr(Register dst, Register src);
723 void addptr(Register dst, RegisterOrConstant src) {
724 if (src.is_constant()) addptr(dst, (int) src.as_constant());
725 else addptr(dst, src.as_register());
726 }
727
728 void andptr(Register dst, int32_t src);
729 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
730
731 void cmp8(AddressLiteral src1, int imm);
732
733 // renamed to drag out the casting of address to int32_t/intptr_t
734 void cmp32(Register src1, int32_t imm);
735
736 void cmp32(AddressLiteral src1, int32_t imm);
737 // compare reg - mem, or reg - &mem
738 void cmp32(Register src1, AddressLiteral src2);
739
740 void cmp32(Register src1, Address src2);
741
742 #ifndef _LP64
743 void cmpklass(Address dst, Metadata* obj);
744 void cmpklass(Register dst, Metadata* obj);
745 void cmpoop(Address dst, jobject obj);
746 #endif // _LP64
747
748 void cmpoop(Register src1, Register src2);
749 void cmpoop(Register src1, Address src2);
750 void cmpoop(Register dst, jobject obj);
751
752 // NOTE src2 must be the lval. This is NOT an mem-mem compare
753 void cmpptr(Address src1, AddressLiteral src2);
754
755 void cmpptr(Register src1, AddressLiteral src2);
756
757 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
758 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
759 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
760
761 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
762 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
763
764 // cmp64 to avoild hiding cmpq
765 void cmp64(Register src1, AddressLiteral src);
766
767 void cmpxchgptr(Register reg, Address adr);
768
769 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
770
771
772 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
773 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
774
775
776 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
777
778 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
779
780 void shlptr(Register dst, int32_t shift);
781 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
782
783 void shrptr(Register dst, int32_t shift);
784 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
785
786 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
787 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
788
789 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
790
791 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
792 void subptr(Register dst, int32_t src);
793 // Force generation of a 4 byte immediate value even if it fits into 8bit
794 void subptr_imm32(Register dst, int32_t src);
795 void subptr(Register dst, Register src);
796 void subptr(Register dst, RegisterOrConstant src) {
797 if (src.is_constant()) subptr(dst, (int) src.as_constant());
798 else subptr(dst, src.as_register());
799 }
800
801 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
802 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
803
804 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
805 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
806
807 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
808
809
810
811 // Helper functions for statistics gathering.
812 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
813 void cond_inc32(Condition cond, AddressLiteral counter_addr);
814 // Unconditional atomic increment.
815 void atomic_incl(Address counter_addr);
816 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
817 #ifdef _LP64
818 void atomic_incq(Address counter_addr);
819 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
820 #endif
821 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
822 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
823
824 void lea(Register dst, AddressLiteral adr);
825 void lea(Address dst, AddressLiteral adr);
826 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
827
828 void leal32(Register dst, Address src) { leal(dst, src); }
829
830 // Import other testl() methods from the parent class or else
831 // they will be hidden by the following overriding declaration.
832 using Assembler::testl;
833 void testl(Register dst, AddressLiteral src);
834
835 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
836 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
837 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
838 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
839
840 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
841 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
842 void testptr(Register src1, Register src2);
843
844 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
845 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
846
847 // Calls
848
849 void call(Label& L, relocInfo::relocType rtype);
850 void call(Register entry);
851
852 // NOTE: this call transfers to the effective address of entry NOT
853 // the address contained by entry. This is because this is more natural
854 // for jumps/calls.
855 void call(AddressLiteral entry);
856
857 // Emit the CompiledIC call idiom
858 void ic_call(address entry, jint method_index = 0);
859
860 // Jumps
861
862 // NOTE: these jumps tranfer to the effective address of dst NOT
863 // the address contained by dst. This is because this is more natural
864 // for jumps/calls.
865 void jump(AddressLiteral dst);
866 void jump_cc(Condition cc, AddressLiteral dst);
867
868 // 32bit can do a case table jump in one instruction but we no longer allow the base
869 // to be installed in the Address class. This jump will tranfers to the address
870 // contained in the location described by entry (not the address of entry)
871 void jump(ArrayAddress entry);
872
873 // Floating
874
875 void push_f(XMMRegister r);
876 void pop_f(XMMRegister r);
877 void push_d(XMMRegister r);
878 void pop_d(XMMRegister r);
879
880 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
881 void andpd(XMMRegister dst, AddressLiteral src);
882 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
883
884 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
885 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
886 void andps(XMMRegister dst, AddressLiteral src);
887
888 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
889 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
890 void comiss(XMMRegister dst, AddressLiteral src);
891
892 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
893 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
894 void comisd(XMMRegister dst, AddressLiteral src);
895
896 void fadd_s(Address src) { Assembler::fadd_s(src); }
897 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
898
899 void fldcw(Address src) { Assembler::fldcw(src); }
900 void fldcw(AddressLiteral src);
901
902 void fld_s(int index) { Assembler::fld_s(index); }
903 void fld_s(Address src) { Assembler::fld_s(src); }
904 void fld_s(AddressLiteral src);
905
906 void fld_d(Address src) { Assembler::fld_d(src); }
907 void fld_d(AddressLiteral src);
908
909 void fld_x(Address src) { Assembler::fld_x(src); }
910 void fld_x(AddressLiteral src);
911
912 void fmul_s(Address src) { Assembler::fmul_s(src); }
913 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
914
915 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
916 void ldmxcsr(AddressLiteral src);
917
918 #ifdef _LP64
919 private:
920 void sha256_AVX2_one_round_compute(
921 Register reg_old_h,
922 Register reg_a,
923 Register reg_b,
924 Register reg_c,
925 Register reg_d,
926 Register reg_e,
927 Register reg_f,
928 Register reg_g,
929 Register reg_h,
930 int iter);
931 void sha256_AVX2_four_rounds_compute_first(int start);
932 void sha256_AVX2_four_rounds_compute_last(int start);
933 void sha256_AVX2_one_round_and_sched(
934 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
935 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
936 XMMRegister xmm_2, /* ymm6 */
937 XMMRegister xmm_3, /* ymm7 */
938 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
939 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
940 Register reg_c, /* edi */
941 Register reg_d, /* esi */
942 Register reg_e, /* r8d */
943 Register reg_f, /* r9d */
944 Register reg_g, /* r10d */
945 Register reg_h, /* r11d */
946 int iter);
947
948 void addm(int disp, Register r1, Register r2);
949
950 public:
951 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
952 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
953 Register buf, Register state, Register ofs, Register limit, Register rsp,
954 bool multi_block, XMMRegister shuf_mask);
955 #endif
956
957 #ifdef _LP64
958 private:
959 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
960 Register e, Register f, Register g, Register h, int iteration);
961
962 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
963 Register a, Register b, Register c, Register d, Register e, Register f,
964 Register g, Register h, int iteration);
965
966 void addmq(int disp, Register r1, Register r2);
967 public:
968 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
969 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
970 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
971 XMMRegister shuf_mask);
972 #endif
973
974 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
975 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
976 Register buf, Register state, Register ofs, Register limit, Register rsp,
977 bool multi_block);
978
979 #ifdef _LP64
980 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
981 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
982 Register buf, Register state, Register ofs, Register limit, Register rsp,
983 bool multi_block, XMMRegister shuf_mask);
984 #else
985 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
986 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
987 Register buf, Register state, Register ofs, Register limit, Register rsp,
988 bool multi_block);
989 #endif
990
991 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
992 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
993 Register rax, Register rcx, Register rdx, Register tmp);
994
995 #ifdef _LP64
996 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
997 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
998 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
999
1000 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1001 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1002 Register rax, Register rcx, Register rdx, Register r11);
1003
1004 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1005 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1006 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1007
1008 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1009 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1010 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1011 Register tmp3, Register tmp4);
1012
1013 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1014 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1015 Register rax, Register rcx, Register rdx, Register tmp1,
1016 Register tmp2, Register tmp3, Register tmp4);
1017 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1018 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1019 Register rax, Register rcx, Register rdx, Register tmp1,
1020 Register tmp2, Register tmp3, Register tmp4);
1021 #else
1022 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1023 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1024 Register rax, Register rcx, Register rdx, Register tmp1);
1025
1026 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1027 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1028 Register rax, Register rcx, Register rdx, Register tmp);
1029
1030 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1031 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1032 Register rdx, Register tmp);
1033
1034 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1035 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1036 Register rax, Register rbx, Register rdx);
1037
1038 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1039 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1040 Register rax, Register rcx, Register rdx, Register tmp);
1041
1042 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1043 Register edx, Register ebx, Register esi, Register edi,
1044 Register ebp, Register esp);
1045
1046 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1047 Register esi, Register edi, Register ebp, Register esp);
1048
1049 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1050 Register edx, Register ebx, Register esi, Register edi,
1051 Register ebp, Register esp);
1052
1053 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1054 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1055 Register rax, Register rcx, Register rdx, Register tmp);
1056 #endif
1057
1058 void increase_precision();
1059 void restore_precision();
1060
1061 private:
1062
1063 // these are private because users should be doing movflt/movdbl
1064
1065 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1066 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1067 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1068 void movss(XMMRegister dst, AddressLiteral src);
1069
1070 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1071 void movlpd(XMMRegister dst, AddressLiteral src);
1072
1073 public:
1074
1075 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1076 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1077 void addsd(XMMRegister dst, AddressLiteral src);
1078
1079 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1080 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1081 void addss(XMMRegister dst, AddressLiteral src);
1082
1083 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1084 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1085 void addpd(XMMRegister dst, AddressLiteral src);
1086
1087 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1088 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1089 void divsd(XMMRegister dst, AddressLiteral src);
1090
1091 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1092 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1093 void divss(XMMRegister dst, AddressLiteral src);
1094
1095 // Move Unaligned Double Quadword
1096 void movdqu(Address dst, XMMRegister src);
1097 void movdqu(XMMRegister dst, Address src);
1098 void movdqu(XMMRegister dst, XMMRegister src);
1099 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1100 // AVX Unaligned forms
1101 void vmovdqu(Address dst, XMMRegister src);
1102 void vmovdqu(XMMRegister dst, Address src);
1103 void vmovdqu(XMMRegister dst, XMMRegister src);
1104 void vmovdqu(XMMRegister dst, AddressLiteral src);
1105
1106 // Move Aligned Double Quadword
1107 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1108 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1109 void movdqa(XMMRegister dst, AddressLiteral src);
1110
1111 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1112 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1113 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1114 void movsd(XMMRegister dst, AddressLiteral src);
1115
1116 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1117 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1118 void mulpd(XMMRegister dst, AddressLiteral src);
1119
1120 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1121 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1122 void mulsd(XMMRegister dst, AddressLiteral src);
1123
1124 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1125 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1126 void mulss(XMMRegister dst, AddressLiteral src);
1127
1128 // Carry-Less Multiplication Quadword
1129 void pclmulldq(XMMRegister dst, XMMRegister src) {
1130 // 0x00 - multiply lower 64 bits [0:63]
1131 Assembler::pclmulqdq(dst, src, 0x00);
1132 }
1133 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1134 // 0x11 - multiply upper 64 bits [64:127]
1135 Assembler::pclmulqdq(dst, src, 0x11);
1136 }
1137
1138 void pcmpeqb(XMMRegister dst, XMMRegister src);
1139 void pcmpeqw(XMMRegister dst, XMMRegister src);
1140
1141 void pcmpestri(XMMRegister dst, Address src, int imm8);
1142 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1143
1144 void pmovzxbw(XMMRegister dst, XMMRegister src);
1145 void pmovzxbw(XMMRegister dst, Address src);
1146
1147 void pmovmskb(Register dst, XMMRegister src);
1148
1149 void ptest(XMMRegister dst, XMMRegister src);
1150
1151 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1152 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1153 void sqrtsd(XMMRegister dst, AddressLiteral src);
1154
1155 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1156 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1157 void sqrtss(XMMRegister dst, AddressLiteral src);
1158
1159 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1160 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1161 void subsd(XMMRegister dst, AddressLiteral src);
1162
1163 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1164 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1165 void subss(XMMRegister dst, AddressLiteral src);
1166
1167 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1168 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1169 void ucomiss(XMMRegister dst, AddressLiteral src);
1170
1171 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1172 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1173 void ucomisd(XMMRegister dst, AddressLiteral src);
1174
1175 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1176 void xorpd(XMMRegister dst, XMMRegister src);
1177 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1178 void xorpd(XMMRegister dst, AddressLiteral src);
1179
1180 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1181 void xorps(XMMRegister dst, XMMRegister src);
1182 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1183 void xorps(XMMRegister dst, AddressLiteral src);
1184
1185 // Shuffle Bytes
1186 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1187 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1188 void pshufb(XMMRegister dst, AddressLiteral src);
1189 // AVX 3-operands instructions
1190
1191 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1192 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1193 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1194
1195 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1196 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1197 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1198
1199 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1200 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1201
1202 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1203 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1204
1205 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1206 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1207
1208 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1209 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1210 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1211
1212 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1213
1214 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1215 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1216
1217 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1218 void vpmovmskb(Register dst, XMMRegister src);
1219
1220 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1221 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1222
1223 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1224 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1225
1226 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1227 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1228
1229 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1230 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1231
1232 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1233 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1234
1235 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1236 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1237
1238 void vptest(XMMRegister dst, XMMRegister src);
1239
1240 void punpcklbw(XMMRegister dst, XMMRegister src);
1241 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1242
1243 void pshufd(XMMRegister dst, Address src, int mode);
1244 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1245
1246 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1247 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1248
1249 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1250 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1251 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1252
1253 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1254 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1255 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1256
1257 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1258 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1259 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1260
1261 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1262 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1263 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1264
1265 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1266 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1267 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1268
1269 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1270 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1271 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1272
1273 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1274 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1275 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1276
1277 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1278 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1279 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1280
1281 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1282 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1283
1284 // AVX Vector instructions
1285
1286 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1287 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1288 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1289
1290 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1291 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1292 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1293
1294 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1295 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1296 Assembler::vpxor(dst, nds, src, vector_len);
1297 else
1298 Assembler::vxorpd(dst, nds, src, vector_len);
1299 }
1300 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1301 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1302 Assembler::vpxor(dst, nds, src, vector_len);
1303 else
1304 Assembler::vxorpd(dst, nds, src, vector_len);
1305 }
1306
1307 // Simple version for AVX2 256bit vectors
1308 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1309 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1310
1311 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1312 if (UseAVX > 2) {
1313 Assembler::vinserti32x4(dst, dst, src, imm8);
1314 } else if (UseAVX > 1) {
1315 // vinserti128 is available only in AVX2
1316 Assembler::vinserti128(dst, nds, src, imm8);
1317 } else {
1318 Assembler::vinsertf128(dst, nds, src, imm8);
1319 }
1320 }
1321
1322 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1323 if (UseAVX > 2) {
1324 Assembler::vinserti32x4(dst, dst, src, imm8);
1325 } else if (UseAVX > 1) {
1326 // vinserti128 is available only in AVX2
1327 Assembler::vinserti128(dst, nds, src, imm8);
1328 } else {
1329 Assembler::vinsertf128(dst, nds, src, imm8);
1330 }
1331 }
1332
1333 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1334 if (UseAVX > 2) {
1335 Assembler::vextracti32x4(dst, src, imm8);
1336 } else if (UseAVX > 1) {
1337 // vextracti128 is available only in AVX2
1338 Assembler::vextracti128(dst, src, imm8);
1339 } else {
1340 Assembler::vextractf128(dst, src, imm8);
1341 }
1342 }
1343
1344 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1345 if (UseAVX > 2) {
1346 Assembler::vextracti32x4(dst, src, imm8);
1347 } else if (UseAVX > 1) {
1348 // vextracti128 is available only in AVX2
1349 Assembler::vextracti128(dst, src, imm8);
1350 } else {
1351 Assembler::vextractf128(dst, src, imm8);
1352 }
1353 }
1354
1355 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1356 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1357 vinserti128(dst, dst, src, 1);
1358 }
1359 void vinserti128_high(XMMRegister dst, Address src) {
1360 vinserti128(dst, dst, src, 1);
1361 }
1362 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1363 vextracti128(dst, src, 1);
1364 }
1365 void vextracti128_high(Address dst, XMMRegister src) {
1366 vextracti128(dst, src, 1);
1367 }
1368
1369 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1370 if (UseAVX > 2) {
1371 Assembler::vinsertf32x4(dst, dst, src, 1);
1372 } else {
1373 Assembler::vinsertf128(dst, dst, src, 1);
1374 }
1375 }
1376
1377 void vinsertf128_high(XMMRegister dst, Address src) {
1378 if (UseAVX > 2) {
1379 Assembler::vinsertf32x4(dst, dst, src, 1);
1380 } else {
1381 Assembler::vinsertf128(dst, dst, src, 1);
1382 }
1383 }
1384
1385 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1386 if (UseAVX > 2) {
1387 Assembler::vextractf32x4(dst, src, 1);
1388 } else {
1389 Assembler::vextractf128(dst, src, 1);
1390 }
1391 }
1392
1393 void vextractf128_high(Address dst, XMMRegister src) {
1394 if (UseAVX > 2) {
1395 Assembler::vextractf32x4(dst, src, 1);
1396 } else {
1397 Assembler::vextractf128(dst, src, 1);
1398 }
1399 }
1400
1401 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1402 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1403 Assembler::vinserti64x4(dst, dst, src, 1);
1404 }
1405 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1406 Assembler::vinsertf64x4(dst, dst, src, 1);
1407 }
1408 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1409 Assembler::vextracti64x4(dst, src, 1);
1410 }
1411 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1412 Assembler::vextractf64x4(dst, src, 1);
1413 }
1414 void vextractf64x4_high(Address dst, XMMRegister src) {
1415 Assembler::vextractf64x4(dst, src, 1);
1416 }
1417 void vinsertf64x4_high(XMMRegister dst, Address src) {
1418 Assembler::vinsertf64x4(dst, dst, src, 1);
1419 }
1420
1421 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1422 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1423 vinserti128(dst, dst, src, 0);
1424 }
1425 void vinserti128_low(XMMRegister dst, Address src) {
1426 vinserti128(dst, dst, src, 0);
1427 }
1428 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1429 vextracti128(dst, src, 0);
1430 }
1431 void vextracti128_low(Address dst, XMMRegister src) {
1432 vextracti128(dst, src, 0);
1433 }
1434
1435 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1436 if (UseAVX > 2) {
1437 Assembler::vinsertf32x4(dst, dst, src, 0);
1438 } else {
1439 Assembler::vinsertf128(dst, dst, src, 0);
1440 }
1441 }
1442
1443 void vinsertf128_low(XMMRegister dst, Address src) {
1444 if (UseAVX > 2) {
1445 Assembler::vinsertf32x4(dst, dst, src, 0);
1446 } else {
1447 Assembler::vinsertf128(dst, dst, src, 0);
1448 }
1449 }
1450
1451 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1452 if (UseAVX > 2) {
1453 Assembler::vextractf32x4(dst, src, 0);
1454 } else {
1455 Assembler::vextractf128(dst, src, 0);
1456 }
1457 }
1458
1459 void vextractf128_low(Address dst, XMMRegister src) {
1460 if (UseAVX > 2) {
1461 Assembler::vextractf32x4(dst, src, 0);
1462 } else {
1463 Assembler::vextractf128(dst, src, 0);
1464 }
1465 }
1466
1467 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1468 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1469 Assembler::vinserti64x4(dst, dst, src, 0);
1470 }
1471 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1472 Assembler::vinsertf64x4(dst, dst, src, 0);
1473 }
1474 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1475 Assembler::vextracti64x4(dst, src, 0);
1476 }
1477 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1478 Assembler::vextractf64x4(dst, src, 0);
1479 }
1480 void vextractf64x4_low(Address dst, XMMRegister src) {
1481 Assembler::vextractf64x4(dst, src, 0);
1482 }
1483 void vinsertf64x4_low(XMMRegister dst, Address src) {
1484 Assembler::vinsertf64x4(dst, dst, src, 0);
1485 }
1486
1487 // Carry-Less Multiplication Quadword
1488 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1489 // 0x00 - multiply lower 64 bits [0:63]
1490 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1491 }
1492 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1493 // 0x11 - multiply upper 64 bits [64:127]
1494 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1495 }
1496 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1497 // 0x00 - multiply lower 64 bits [0:63]
1498 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1499 }
1500 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1501 // 0x11 - multiply upper 64 bits [64:127]
1502 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1503 }
1504
1505 // Data
1506
1507 void cmov32( Condition cc, Register dst, Address src);
1508 void cmov32( Condition cc, Register dst, Register src);
1509
1510 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1511
1512 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1513 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1514
1515 void movoop(Register dst, jobject obj);
1516 void movoop(Address dst, jobject obj);
1517
1518 void mov_metadata(Register dst, Metadata* obj);
1519 void mov_metadata(Address dst, Metadata* obj);
1520
1521 void movptr(ArrayAddress dst, Register src);
1522 // can this do an lea?
1523 void movptr(Register dst, ArrayAddress src);
1524
1525 void movptr(Register dst, Address src);
1526
1527 #ifdef _LP64
1528 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1529 #else
1530 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1531 #endif
1532
1533 void movptr(Register dst, intptr_t src);
1534 void movptr(Register dst, Register src);
1535 void movptr(Address dst, intptr_t src);
1536
1537 void movptr(Address dst, Register src);
1538
1539 void movptr(Register dst, RegisterOrConstant src) {
1540 if (src.is_constant()) movptr(dst, src.as_constant());
1541 else movptr(dst, src.as_register());
1542 }
1543
1544 #ifdef _LP64
1545 // Generally the next two are only used for moving NULL
1546 // Although there are situations in initializing the mark word where
1547 // they could be used. They are dangerous.
1548
1549 // They only exist on LP64 so that int32_t and intptr_t are not the same
1550 // and we have ambiguous declarations.
1551
1552 void movptr(Address dst, int32_t imm32);
1553 void movptr(Register dst, int32_t imm32);
1554 #endif // _LP64
1555
1556 // to avoid hiding movl
1557 void mov32(AddressLiteral dst, Register src);
1558 void mov32(Register dst, AddressLiteral src);
1559
1560 // to avoid hiding movb
1561 void movbyte(ArrayAddress dst, int src);
1562
1563 // Import other mov() methods from the parent class or else
1564 // they will be hidden by the following overriding declaration.
1565 using Assembler::movdl;
1566 using Assembler::movq;
1567 void movdl(XMMRegister dst, AddressLiteral src);
1568 void movq(XMMRegister dst, AddressLiteral src);
1569
1570 // Can push value or effective address
1571 void pushptr(AddressLiteral src);
1572
1573 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1574 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1575
1576 void pushoop(jobject obj);
1577 void pushklass(Metadata* obj);
1578
1579 // sign extend as need a l to ptr sized element
1580 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1581 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1582
1583 // C2 compiled method's prolog code.
1584 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1585
1586 // clear memory of size 'cnt' qwords, starting at 'base';
1587 // if 'is_large' is set, do not try to produce short loop
1588 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1589
1590 #ifdef COMPILER2
1591 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1592 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1593
1594 // IndexOf strings.
1595 // Small strings are loaded through stack if they cross page boundary.
1596 void string_indexof(Register str1, Register str2,
1597 Register cnt1, Register cnt2,
1598 int int_cnt2, Register result,
1599 XMMRegister vec, Register tmp,
1600 int ae);
1601
1602 // IndexOf for constant substrings with size >= 8 elements
1603 // which don't need to be loaded through stack.
1604 void string_indexofC8(Register str1, Register str2,
1605 Register cnt1, Register cnt2,
1606 int int_cnt2, Register result,
1607 XMMRegister vec, Register tmp,
1608 int ae);
1609
1610 // Smallest code: we don't need to load through stack,
1611 // check string tail.
1612
1613 // helper function for string_compare
1614 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1615 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1616 Address::ScaleFactor scale2, Register index, int ae);
1617 // Compare strings.
1618 void string_compare(Register str1, Register str2,
1619 Register cnt1, Register cnt2, Register result,
1620 XMMRegister vec1, int ae);
1621
1622 // Search for Non-ASCII character (Negative byte value) in a byte array,
1623 // return true if it has any and false otherwise.
1624 void has_negatives(Register ary1, Register len,
1625 Register result, Register tmp1,
1626 XMMRegister vec1, XMMRegister vec2);
1627
1628 // Compare char[] or byte[] arrays.
1629 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1630 Register limit, Register result, Register chr,
1631 XMMRegister vec1, XMMRegister vec2, bool is_char);
1632
1633 #endif
1634
1635 // Fill primitive arrays
1636 void generate_fill(BasicType t, bool aligned,
1637 Register to, Register value, Register count,
1638 Register rtmp, XMMRegister xtmp);
1639
1640 void encode_iso_array(Register src, Register dst, Register len,
1641 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1642 XMMRegister tmp4, Register tmp5, Register result);
1643
1644 #ifdef _LP64
1645 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1646 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1647 Register y, Register y_idx, Register z,
1648 Register carry, Register product,
1649 Register idx, Register kdx);
1650 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1651 Register yz_idx, Register idx,
1652 Register carry, Register product, int offset);
1653 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1654 Register carry, Register carry2,
1655 Register idx, Register jdx,
1656 Register yz_idx1, Register yz_idx2,
1657 Register tmp, Register tmp3, Register tmp4);
1658 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1659 Register yz_idx, Register idx, Register jdx,
1660 Register carry, Register product,
1661 Register carry2);
1662 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1663 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1664 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1665 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1666 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1667 Register tmp2);
1668 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1669 Register rdxReg, Register raxReg);
1670 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1671 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1672 Register tmp3, Register tmp4);
1673 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1674 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1675
1676 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1677 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1678 Register raxReg);
1679 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1680 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1681 Register raxReg);
1682 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1683 Register result, Register tmp1, Register tmp2,
1684 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1685 #endif
1686
1687 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1688 void update_byte_crc32(Register crc, Register val, Register table);
1689 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1690 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1691 // Note on a naming convention:
1692 // Prefix w = register only used on a Westmere+ architecture
1693 // Prefix n = register only used on a Nehalem architecture
1694 #ifdef _LP64
1695 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1696 Register tmp1, Register tmp2, Register tmp3);
1697 #else
1698 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1699 Register tmp1, Register tmp2, Register tmp3,
1700 XMMRegister xtmp1, XMMRegister xtmp2);
1701 #endif
1702 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1703 Register in_out,
1704 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1705 XMMRegister w_xtmp2,
1706 Register tmp1,
1707 Register n_tmp2, Register n_tmp3);
1708 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1709 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1710 Register tmp1, Register tmp2,
1711 Register n_tmp3);
1712 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1713 Register in_out1, Register in_out2, Register in_out3,
1714 Register tmp1, Register tmp2, Register tmp3,
1715 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1716 Register tmp4, Register tmp5,
1717 Register n_tmp6);
1718 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1719 Register tmp1, Register tmp2, Register tmp3,
1720 Register tmp4, Register tmp5, Register tmp6,
1721 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1722 bool is_pclmulqdq_supported);
1723 // Fold 128-bit data chunk
1724 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1725 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1726 // Fold 8-bit data
1727 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1728 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1729 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1730
1731 // Compress char[] array to byte[].
1732 void char_array_compress(Register src, Register dst, Register len,
1733 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1734 XMMRegister tmp4, Register tmp5, Register result);
1735
1736 // Inflate byte[] array to char[].
1737 void byte_array_inflate(Register src, Register dst, Register len,
1738 XMMRegister tmp1, Register tmp2);
1739
1740 };
1741
1742 /**
1743 * class SkipIfEqual:
1744 *
1745 * Instantiating this class will result in assembly code being output that will
1746 * jump around any code emitted between the creation of the instance and it's
1747 * automatic destruction at the end of a scope block, depending on the value of
1748 * the flag passed to the constructor, which will be checked at run-time.
1749 */
1750 class SkipIfEqual {
1751 private:
1752 MacroAssembler* _masm;
1753 Label _label;
1754
1755 public:
1756 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1757 ~SkipIfEqual();
1758 };
1759
1760 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP