1 //
2 // Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // The registers which can be used for
321 // a thread local safepoint poll
322 // * R12 is reserved for heap base
323 // * R13 cannot be encoded for addressing without an offset byte
324 // * R15 is reserved for the JavaThread
325 reg_class ptr_rex_reg(R8, R8_H,
326 R9, R9_H,
327 R10, R10_H,
328 R11, R11_H,
329 R14, R14_H);
330
331
332 // Class for all long registers (excluding RSP)
333 reg_class long_reg_with_rbp(RAX, RAX_H,
334 RDX, RDX_H,
335 RBP, RBP_H,
336 RDI, RDI_H,
337 RSI, RSI_H,
338 RCX, RCX_H,
339 RBX, RBX_H,
340 R8, R8_H,
341 R9, R9_H,
342 R10, R10_H,
343 R11, R11_H,
344 R13, R13_H,
345 R14, R14_H);
346
347 // Class for all long registers (excluding RSP and RBP)
348 reg_class long_reg_no_rbp(RAX, RAX_H,
349 RDX, RDX_H,
350 RDI, RDI_H,
351 RSI, RSI_H,
352 RCX, RCX_H,
353 RBX, RBX_H,
354 R8, R8_H,
355 R9, R9_H,
356 R10, R10_H,
357 R11, R11_H,
358 R13, R13_H,
359 R14, R14_H);
360
361 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
362 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
363
364 // Class for all long registers (excluding RAX, RDX and RSP)
365 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
366 RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
378 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
379 RSI, RSI_H,
380 RCX, RCX_H,
381 RBX, RBX_H,
382 R8, R8_H,
383 R9, R9_H,
384 R10, R10_H,
385 R11, R11_H,
386 R13, R13_H,
387 R14, R14_H);
388
389 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
390 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
391
392 // Class for all long registers (excluding RCX and RSP)
393 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
394 RDI, RDI_H,
395 RSI, RSI_H,
396 RAX, RAX_H,
397 RDX, RDX_H,
398 RBX, RBX_H,
399 R8, R8_H,
400 R9, R9_H,
401 R10, R10_H,
402 R11, R11_H,
403 R13, R13_H,
404 R14, R14_H);
405
406 // Class for all long registers (excluding RCX, RSP, and RBP)
407 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
408 RSI, RSI_H,
409 RAX, RAX_H,
410 RDX, RDX_H,
411 RBX, RBX_H,
412 R8, R8_H,
413 R9, R9_H,
414 R10, R10_H,
415 R11, R11_H,
416 R13, R13_H,
417 R14, R14_H);
418
419 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
420 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
421
422 // Singleton class for RAX long register
423 reg_class long_rax_reg(RAX, RAX_H);
424
425 // Singleton class for RCX long register
426 reg_class long_rcx_reg(RCX, RCX_H);
427
428 // Singleton class for RDX long register
429 reg_class long_rdx_reg(RDX, RDX_H);
430
431 // Class for all int registers (excluding RSP)
432 reg_class int_reg_with_rbp(RAX,
433 RDX,
434 RBP,
435 RDI,
436 RSI,
437 RCX,
438 RBX,
439 R8,
440 R9,
441 R10,
442 R11,
443 R13,
444 R14);
445
446 // Class for all int registers (excluding RSP and RBP)
447 reg_class int_reg_no_rbp(RAX,
448 RDX,
449 RDI,
450 RSI,
451 RCX,
452 RBX,
453 R8,
454 R9,
455 R10,
456 R11,
457 R13,
458 R14);
459
460 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
461 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
462
463 // Class for all int registers (excluding RCX and RSP)
464 reg_class int_no_rcx_reg_with_rbp(RAX,
465 RDX,
466 RBP,
467 RDI,
468 RSI,
469 RBX,
470 R8,
471 R9,
472 R10,
473 R11,
474 R13,
475 R14);
476
477 // Class for all int registers (excluding RCX, RSP, and RBP)
478 reg_class int_no_rcx_reg_no_rbp(RAX,
479 RDX,
480 RDI,
481 RSI,
482 RBX,
483 R8,
484 R9,
485 R10,
486 R11,
487 R13,
488 R14);
489
490 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
491 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
492
493 // Class for all int registers (excluding RAX, RDX, and RSP)
494 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
495 RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
507 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
508 RSI,
509 RCX,
510 RBX,
511 R8,
512 R9,
513 R10,
514 R11,
515 R13,
516 R14);
517
518 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
519 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
520
521 // Singleton class for RAX int register
522 reg_class int_rax_reg(RAX);
523
524 // Singleton class for RBX int register
525 reg_class int_rbx_reg(RBX);
526
527 // Singleton class for RCX int register
528 reg_class int_rcx_reg(RCX);
529
530 // Singleton class for RCX int register
531 reg_class int_rdx_reg(RDX);
532
533 // Singleton class for RCX int register
534 reg_class int_rdi_reg(RDI);
535
536 // Singleton class for instruction pointer
537 // reg_class ip_reg(RIP);
538
539 %}
540
541 //----------SOURCE BLOCK-------------------------------------------------------
542 // This is a block of C++ code which provides values, functions, and
543 // definitions necessary in the rest of the architecture description
544 source %{
545 #define RELOC_IMM64 Assembler::imm_operand
546 #define RELOC_DISP32 Assembler::disp32_operand
547
548 #define __ _masm.
549
550 static bool generate_vzeroupper(Compile* C) {
551 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
552 }
553
554 static int clear_avx_size() {
555 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
556 }
557
558 // !!!!! Special hack to get all types of calls to specify the byte offset
559 // from the start of the call to the point where the return address
560 // will point.
561 int MachCallStaticJavaNode::ret_addr_offset()
562 {
563 int offset = 5; // 5 bytes from start of call to where return address points
564 offset += clear_avx_size();
565 return offset;
566 }
567
568 int MachCallDynamicJavaNode::ret_addr_offset()
569 {
570 int offset = 15; // 15 bytes from start of call to where return address points
571 offset += clear_avx_size();
572 return offset;
573 }
574
575 int MachCallRuntimeNode::ret_addr_offset() {
576 int offset = 13; // movq r10,#addr; callq (r10)
577 offset += clear_avx_size();
578 return offset;
579 }
580
581 // Indicate if the safepoint node needs the polling page as an input,
582 // it does if the polling page is more than disp32 away.
583 bool SafePointNode::needs_polling_address_input()
584 {
585 return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
586 }
587
588 //
589 // Compute padding required for nodes which need alignment
590 //
591
592 // The address of the call instruction needs to be 4-byte aligned to
593 // ensure that it does not span a cache line so that it can be patched.
594 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
595 {
596 current_offset += clear_avx_size(); // skip vzeroupper
597 current_offset += 1; // skip call opcode byte
598 return align_up(current_offset, alignment_required()) - current_offset;
599 }
600
601 // The address of the call instruction needs to be 4-byte aligned to
602 // ensure that it does not span a cache line so that it can be patched.
603 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
604 {
605 current_offset += clear_avx_size(); // skip vzeroupper
606 current_offset += 11; // skip movq instruction + call opcode byte
607 return align_up(current_offset, alignment_required()) - current_offset;
608 }
609
610 // EMIT_RM()
611 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
612 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
613 cbuf.insts()->emit_int8(c);
614 }
615
616 // EMIT_CC()
617 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
618 unsigned char c = (unsigned char) (f1 | f2);
619 cbuf.insts()->emit_int8(c);
620 }
621
622 // EMIT_OPCODE()
623 void emit_opcode(CodeBuffer &cbuf, int code) {
624 cbuf.insts()->emit_int8((unsigned char) code);
625 }
626
627 // EMIT_OPCODE() w/ relocation information
628 void emit_opcode(CodeBuffer &cbuf,
629 int code, relocInfo::relocType reloc, int offset, int format)
630 {
631 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
632 emit_opcode(cbuf, code);
633 }
634
635 // EMIT_D8()
636 void emit_d8(CodeBuffer &cbuf, int d8) {
637 cbuf.insts()->emit_int8((unsigned char) d8);
638 }
639
640 // EMIT_D16()
641 void emit_d16(CodeBuffer &cbuf, int d16) {
642 cbuf.insts()->emit_int16(d16);
643 }
644
645 // EMIT_D32()
646 void emit_d32(CodeBuffer &cbuf, int d32) {
647 cbuf.insts()->emit_int32(d32);
648 }
649
650 // EMIT_D64()
651 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
652 cbuf.insts()->emit_int64(d64);
653 }
654
655 // emit 32 bit value and construct relocation entry from relocInfo::relocType
656 void emit_d32_reloc(CodeBuffer& cbuf,
657 int d32,
658 relocInfo::relocType reloc,
659 int format)
660 {
661 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
662 cbuf.relocate(cbuf.insts_mark(), reloc, format);
663 cbuf.insts()->emit_int32(d32);
664 }
665
666 // emit 32 bit value and construct relocation entry from RelocationHolder
667 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
668 #ifdef ASSERT
669 if (rspec.reloc()->type() == relocInfo::oop_type &&
670 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
671 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
672 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop((intptr_t)d32))), "cannot embed scavengable oops in code");
673 }
674 #endif
675 cbuf.relocate(cbuf.insts_mark(), rspec, format);
676 cbuf.insts()->emit_int32(d32);
677 }
678
679 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
680 address next_ip = cbuf.insts_end() + 4;
681 emit_d32_reloc(cbuf, (int) (addr - next_ip),
682 external_word_Relocation::spec(addr),
683 RELOC_DISP32);
684 }
685
686
687 // emit 64 bit value and construct relocation entry from relocInfo::relocType
688 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
689 cbuf.relocate(cbuf.insts_mark(), reloc, format);
690 cbuf.insts()->emit_int64(d64);
691 }
692
693 // emit 64 bit value and construct relocation entry from RelocationHolder
694 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
695 #ifdef ASSERT
696 if (rspec.reloc()->type() == relocInfo::oop_type &&
697 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
698 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
699 assert(oopDesc::is_oop(cast_to_oop(d64)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop(d64))),
700 "cannot embed scavengable oops in code");
701 }
702 #endif
703 cbuf.relocate(cbuf.insts_mark(), rspec, format);
704 cbuf.insts()->emit_int64(d64);
705 }
706
707 // Access stack slot for load or store
708 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
709 {
710 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
711 if (-0x80 <= disp && disp < 0x80) {
712 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
713 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
714 emit_d8(cbuf, disp); // Displacement // R/M byte
715 } else {
716 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
717 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
718 emit_d32(cbuf, disp); // Displacement // R/M byte
719 }
720 }
721
722 // rRegI ereg, memory mem) %{ // emit_reg_mem
723 void encode_RegMem(CodeBuffer &cbuf,
724 int reg,
725 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
726 {
727 assert(disp_reloc == relocInfo::none, "cannot have disp");
728 int regenc = reg & 7;
729 int baseenc = base & 7;
730 int indexenc = index & 7;
731
732 // There is no index & no scale, use form without SIB byte
733 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
734 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
735 if (disp == 0 && base != RBP_enc && base != R13_enc) {
736 emit_rm(cbuf, 0x0, regenc, baseenc); // *
737 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
738 // If 8-bit displacement, mode 0x1
739 emit_rm(cbuf, 0x1, regenc, baseenc); // *
740 emit_d8(cbuf, disp);
741 } else {
742 // If 32-bit displacement
743 if (base == -1) { // Special flag for absolute address
744 emit_rm(cbuf, 0x0, regenc, 0x5); // *
745 if (disp_reloc != relocInfo::none) {
746 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
747 } else {
748 emit_d32(cbuf, disp);
749 }
750 } else {
751 // Normal base + offset
752 emit_rm(cbuf, 0x2, regenc, baseenc); // *
753 if (disp_reloc != relocInfo::none) {
754 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
755 } else {
756 emit_d32(cbuf, disp);
757 }
758 }
759 }
760 } else {
761 // Else, encode with the SIB byte
762 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
763 if (disp == 0 && base != RBP_enc && base != R13_enc) {
764 // If no displacement
765 emit_rm(cbuf, 0x0, regenc, 0x4); // *
766 emit_rm(cbuf, scale, indexenc, baseenc);
767 } else {
768 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
769 // If 8-bit displacement, mode 0x1
770 emit_rm(cbuf, 0x1, regenc, 0x4); // *
771 emit_rm(cbuf, scale, indexenc, baseenc);
772 emit_d8(cbuf, disp);
773 } else {
774 // If 32-bit displacement
775 if (base == 0x04 ) {
776 emit_rm(cbuf, 0x2, regenc, 0x4);
777 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
778 } else {
779 emit_rm(cbuf, 0x2, regenc, 0x4);
780 emit_rm(cbuf, scale, indexenc, baseenc); // *
781 }
782 if (disp_reloc != relocInfo::none) {
783 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
784 } else {
785 emit_d32(cbuf, disp);
786 }
787 }
788 }
789 }
790 }
791
792 // This could be in MacroAssembler but it's fairly C2 specific
793 void emit_cmpfp_fixup(MacroAssembler& _masm) {
794 Label exit;
795 __ jccb(Assembler::noParity, exit);
796 __ pushf();
797 //
798 // comiss/ucomiss instructions set ZF,PF,CF flags and
799 // zero OF,AF,SF for NaN values.
800 // Fixup flags by zeroing ZF,PF so that compare of NaN
801 // values returns 'less than' result (CF is set).
802 // Leave the rest of flags unchanged.
803 //
804 // 7 6 5 4 3 2 1 0
805 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
806 // 0 0 1 0 1 0 1 1 (0x2B)
807 //
808 __ andq(Address(rsp, 0), 0xffffff2b);
809 __ popf();
810 __ bind(exit);
811 }
812
813 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
814 Label done;
815 __ movl(dst, -1);
816 __ jcc(Assembler::parity, done);
817 __ jcc(Assembler::below, done);
818 __ setb(Assembler::notEqual, dst);
819 __ movzbl(dst, dst);
820 __ bind(done);
821 }
822
823
824 //=============================================================================
825 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
826
827 int Compile::ConstantTable::calculate_table_base_offset() const {
828 return 0; // absolute addressing, no offset
829 }
830
831 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
832 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
833 ShouldNotReachHere();
834 }
835
836 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
837 // Empty encoding
838 }
839
840 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
841 return 0;
842 }
843
844 #ifndef PRODUCT
845 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
846 st->print("# MachConstantBaseNode (empty encoding)");
847 }
848 #endif
849
850
851 //=============================================================================
852 #ifndef PRODUCT
853 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
854 Compile* C = ra_->C;
855
856 int framesize = C->frame_size_in_bytes();
857 int bangsize = C->bang_size_in_bytes();
858 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
859 // Remove wordSize for return addr which is already pushed.
860 framesize -= wordSize;
861
862 if (C->need_stack_bang(bangsize)) {
863 framesize -= wordSize;
864 st->print("# stack bang (%d bytes)", bangsize);
865 st->print("\n\t");
866 st->print("pushq rbp\t# Save rbp");
867 if (PreserveFramePointer) {
868 st->print("\n\t");
869 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
870 }
871 if (framesize) {
872 st->print("\n\t");
873 st->print("subq rsp, #%d\t# Create frame",framesize);
874 }
875 } else {
876 st->print("subq rsp, #%d\t# Create frame",framesize);
877 st->print("\n\t");
878 framesize -= wordSize;
879 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
880 if (PreserveFramePointer) {
881 st->print("\n\t");
882 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
883 if (framesize > 0) {
884 st->print("\n\t");
885 st->print("addq rbp, #%d", framesize);
886 }
887 }
888 }
889
890 if (VerifyStackAtCalls) {
891 st->print("\n\t");
892 framesize -= wordSize;
893 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
894 #ifdef ASSERT
895 st->print("\n\t");
896 st->print("# stack alignment check");
897 #endif
898 }
899 st->cr();
900 }
901 #endif
902
903 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
904 Compile* C = ra_->C;
905 MacroAssembler _masm(&cbuf);
906
907 int framesize = C->frame_size_in_bytes();
908 int bangsize = C->bang_size_in_bytes();
909
910 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
911
912 C->set_frame_complete(cbuf.insts_size());
913
914 if (C->has_mach_constant_base_node()) {
915 // NOTE: We set the table base offset here because users might be
916 // emitted before MachConstantBaseNode.
917 Compile::ConstantTable& constant_table = C->constant_table();
918 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
919 }
920 }
921
922 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
923 {
924 return MachNode::size(ra_); // too many variables; just compute it
925 // the hard way
926 }
927
928 int MachPrologNode::reloc() const
929 {
930 return 0; // a large enough number
931 }
932
933 //=============================================================================
934 #ifndef PRODUCT
935 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
936 {
937 Compile* C = ra_->C;
938 if (generate_vzeroupper(C)) {
939 st->print("vzeroupper");
940 st->cr(); st->print("\t");
941 }
942
943 int framesize = C->frame_size_in_bytes();
944 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
945 // Remove word for return adr already pushed
946 // and RBP
947 framesize -= 2*wordSize;
948
949 if (framesize) {
950 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
951 st->print("\t");
952 }
953
954 st->print_cr("popq rbp");
955 if (do_polling() && C->is_method_compilation()) {
956 st->print("\t");
957 if (SafepointMechanism::uses_thread_local_poll()) {
958 st->print_cr("movq rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
959 "testl rax, [rscratch1]\t"
960 "# Safepoint: poll for GC");
961 } else if (Assembler::is_polling_page_far()) {
962 st->print_cr("movq rscratch1, #polling_page_address\n\t"
963 "testl rax, [rscratch1]\t"
964 "# Safepoint: poll for GC");
965 } else {
966 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
967 "# Safepoint: poll for GC");
968 }
969 }
970 }
971 #endif
972
973 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
974 {
975 Compile* C = ra_->C;
976 MacroAssembler _masm(&cbuf);
977
978 if (generate_vzeroupper(C)) {
979 // Clear upper bits of YMM registers when current compiled code uses
980 // wide vectors to avoid AVX <-> SSE transition penalty during call.
981 __ vzeroupper();
982 }
983
984 int framesize = C->frame_size_in_bytes();
985 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
986 // Remove word for return adr already pushed
987 // and RBP
988 framesize -= 2*wordSize;
989
990 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
991
992 if (framesize) {
993 emit_opcode(cbuf, Assembler::REX_W);
994 if (framesize < 0x80) {
995 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
996 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
997 emit_d8(cbuf, framesize);
998 } else {
999 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1000 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1001 emit_d32(cbuf, framesize);
1002 }
1003 }
1004
1005 // popq rbp
1006 emit_opcode(cbuf, 0x58 | RBP_enc);
1007
1008 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1009 __ reserved_stack_check();
1010 }
1011
1012 if (do_polling() && C->is_method_compilation()) {
1013 MacroAssembler _masm(&cbuf);
1014 if (SafepointMechanism::uses_thread_local_poll()) {
1015 __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
1016 __ relocate(relocInfo::poll_return_type);
1017 __ testl(rax, Address(rscratch1, 0));
1018 } else {
1019 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1020 if (Assembler::is_polling_page_far()) {
1021 __ lea(rscratch1, polling_page);
1022 __ relocate(relocInfo::poll_return_type);
1023 __ testl(rax, Address(rscratch1, 0));
1024 } else {
1025 __ testl(rax, polling_page);
1026 }
1027 }
1028 }
1029 }
1030
1031 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1032 {
1033 return MachNode::size(ra_); // too many variables; just compute it
1034 // the hard way
1035 }
1036
1037 int MachEpilogNode::reloc() const
1038 {
1039 return 2; // a large enough number
1040 }
1041
1042 const Pipeline* MachEpilogNode::pipeline() const
1043 {
1044 return MachNode::pipeline_class();
1045 }
1046
1047 int MachEpilogNode::safepoint_offset() const
1048 {
1049 return 0;
1050 }
1051
1052 //=============================================================================
1053
1054 enum RC {
1055 rc_bad,
1056 rc_int,
1057 rc_float,
1058 rc_stack
1059 };
1060
1061 static enum RC rc_class(OptoReg::Name reg)
1062 {
1063 if( !OptoReg::is_valid(reg) ) return rc_bad;
1064
1065 if (OptoReg::is_stack(reg)) return rc_stack;
1066
1067 VMReg r = OptoReg::as_VMReg(reg);
1068
1069 if (r->is_Register()) return rc_int;
1070
1071 assert(r->is_XMMRegister(), "must be");
1072 return rc_float;
1073 }
1074
1075 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1076 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1077 int src_hi, int dst_hi, uint ireg, outputStream* st);
1078
1079 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1080 int stack_offset, int reg, uint ireg, outputStream* st);
1081
1082 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1083 int dst_offset, uint ireg, outputStream* st) {
1084 if (cbuf) {
1085 MacroAssembler _masm(cbuf);
1086 switch (ireg) {
1087 case Op_VecS:
1088 __ movq(Address(rsp, -8), rax);
1089 __ movl(rax, Address(rsp, src_offset));
1090 __ movl(Address(rsp, dst_offset), rax);
1091 __ movq(rax, Address(rsp, -8));
1092 break;
1093 case Op_VecD:
1094 __ pushq(Address(rsp, src_offset));
1095 __ popq (Address(rsp, dst_offset));
1096 break;
1097 case Op_VecX:
1098 __ pushq(Address(rsp, src_offset));
1099 __ popq (Address(rsp, dst_offset));
1100 __ pushq(Address(rsp, src_offset+8));
1101 __ popq (Address(rsp, dst_offset+8));
1102 break;
1103 case Op_VecY:
1104 __ vmovdqu(Address(rsp, -32), xmm0);
1105 __ vmovdqu(xmm0, Address(rsp, src_offset));
1106 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1107 __ vmovdqu(xmm0, Address(rsp, -32));
1108 break;
1109 case Op_VecZ:
1110 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1111 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1112 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1113 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1114 break;
1115 default:
1116 ShouldNotReachHere();
1117 }
1118 #ifndef PRODUCT
1119 } else {
1120 switch (ireg) {
1121 case Op_VecS:
1122 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1123 "movl rax, [rsp + #%d]\n\t"
1124 "movl [rsp + #%d], rax\n\t"
1125 "movq rax, [rsp - #8]",
1126 src_offset, dst_offset);
1127 break;
1128 case Op_VecD:
1129 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1130 "popq [rsp + #%d]",
1131 src_offset, dst_offset);
1132 break;
1133 case Op_VecX:
1134 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1135 "popq [rsp + #%d]\n\t"
1136 "pushq [rsp + #%d]\n\t"
1137 "popq [rsp + #%d]",
1138 src_offset, dst_offset, src_offset+8, dst_offset+8);
1139 break;
1140 case Op_VecY:
1141 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1142 "vmovdqu xmm0, [rsp + #%d]\n\t"
1143 "vmovdqu [rsp + #%d], xmm0\n\t"
1144 "vmovdqu xmm0, [rsp - #32]",
1145 src_offset, dst_offset);
1146 break;
1147 case Op_VecZ:
1148 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1149 "vmovdqu xmm0, [rsp + #%d]\n\t"
1150 "vmovdqu [rsp + #%d], xmm0\n\t"
1151 "vmovdqu xmm0, [rsp - #64]",
1152 src_offset, dst_offset);
1153 break;
1154 default:
1155 ShouldNotReachHere();
1156 }
1157 #endif
1158 }
1159 }
1160
1161 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1162 PhaseRegAlloc* ra_,
1163 bool do_size,
1164 outputStream* st) const {
1165 assert(cbuf != NULL || st != NULL, "sanity");
1166 // Get registers to move
1167 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1168 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1169 OptoReg::Name dst_second = ra_->get_reg_second(this);
1170 OptoReg::Name dst_first = ra_->get_reg_first(this);
1171
1172 enum RC src_second_rc = rc_class(src_second);
1173 enum RC src_first_rc = rc_class(src_first);
1174 enum RC dst_second_rc = rc_class(dst_second);
1175 enum RC dst_first_rc = rc_class(dst_first);
1176
1177 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1178 "must move at least 1 register" );
1179
1180 if (src_first == dst_first && src_second == dst_second) {
1181 // Self copy, no move
1182 return 0;
1183 }
1184 if (bottom_type()->isa_vect() != NULL) {
1185 uint ireg = ideal_reg();
1186 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1187 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1188 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1189 // mem -> mem
1190 int src_offset = ra_->reg2offset(src_first);
1191 int dst_offset = ra_->reg2offset(dst_first);
1192 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1193 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1194 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1195 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1196 int stack_offset = ra_->reg2offset(dst_first);
1197 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1198 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1199 int stack_offset = ra_->reg2offset(src_first);
1200 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1201 } else {
1202 ShouldNotReachHere();
1203 }
1204 return 0;
1205 }
1206 if (src_first_rc == rc_stack) {
1207 // mem ->
1208 if (dst_first_rc == rc_stack) {
1209 // mem -> mem
1210 assert(src_second != dst_first, "overlap");
1211 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1212 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1213 // 64-bit
1214 int src_offset = ra_->reg2offset(src_first);
1215 int dst_offset = ra_->reg2offset(dst_first);
1216 if (cbuf) {
1217 MacroAssembler _masm(cbuf);
1218 __ pushq(Address(rsp, src_offset));
1219 __ popq (Address(rsp, dst_offset));
1220 #ifndef PRODUCT
1221 } else {
1222 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1223 "popq [rsp + #%d]",
1224 src_offset, dst_offset);
1225 #endif
1226 }
1227 } else {
1228 // 32-bit
1229 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1230 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1231 // No pushl/popl, so:
1232 int src_offset = ra_->reg2offset(src_first);
1233 int dst_offset = ra_->reg2offset(dst_first);
1234 if (cbuf) {
1235 MacroAssembler _masm(cbuf);
1236 __ movq(Address(rsp, -8), rax);
1237 __ movl(rax, Address(rsp, src_offset));
1238 __ movl(Address(rsp, dst_offset), rax);
1239 __ movq(rax, Address(rsp, -8));
1240 #ifndef PRODUCT
1241 } else {
1242 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1243 "movl rax, [rsp + #%d]\n\t"
1244 "movl [rsp + #%d], rax\n\t"
1245 "movq rax, [rsp - #8]",
1246 src_offset, dst_offset);
1247 #endif
1248 }
1249 }
1250 return 0;
1251 } else if (dst_first_rc == rc_int) {
1252 // mem -> gpr
1253 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1254 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1255 // 64-bit
1256 int offset = ra_->reg2offset(src_first);
1257 if (cbuf) {
1258 MacroAssembler _masm(cbuf);
1259 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1260 #ifndef PRODUCT
1261 } else {
1262 st->print("movq %s, [rsp + #%d]\t# spill",
1263 Matcher::regName[dst_first],
1264 offset);
1265 #endif
1266 }
1267 } else {
1268 // 32-bit
1269 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1270 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1271 int offset = ra_->reg2offset(src_first);
1272 if (cbuf) {
1273 MacroAssembler _masm(cbuf);
1274 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1275 #ifndef PRODUCT
1276 } else {
1277 st->print("movl %s, [rsp + #%d]\t# spill",
1278 Matcher::regName[dst_first],
1279 offset);
1280 #endif
1281 }
1282 }
1283 return 0;
1284 } else if (dst_first_rc == rc_float) {
1285 // mem-> xmm
1286 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1287 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1288 // 64-bit
1289 int offset = ra_->reg2offset(src_first);
1290 if (cbuf) {
1291 MacroAssembler _masm(cbuf);
1292 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1293 #ifndef PRODUCT
1294 } else {
1295 st->print("%s %s, [rsp + #%d]\t# spill",
1296 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1297 Matcher::regName[dst_first],
1298 offset);
1299 #endif
1300 }
1301 } else {
1302 // 32-bit
1303 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1304 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1305 int offset = ra_->reg2offset(src_first);
1306 if (cbuf) {
1307 MacroAssembler _masm(cbuf);
1308 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1309 #ifndef PRODUCT
1310 } else {
1311 st->print("movss %s, [rsp + #%d]\t# spill",
1312 Matcher::regName[dst_first],
1313 offset);
1314 #endif
1315 }
1316 }
1317 return 0;
1318 }
1319 } else if (src_first_rc == rc_int) {
1320 // gpr ->
1321 if (dst_first_rc == rc_stack) {
1322 // gpr -> mem
1323 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1324 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1325 // 64-bit
1326 int offset = ra_->reg2offset(dst_first);
1327 if (cbuf) {
1328 MacroAssembler _masm(cbuf);
1329 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1330 #ifndef PRODUCT
1331 } else {
1332 st->print("movq [rsp + #%d], %s\t# spill",
1333 offset,
1334 Matcher::regName[src_first]);
1335 #endif
1336 }
1337 } else {
1338 // 32-bit
1339 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1340 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1341 int offset = ra_->reg2offset(dst_first);
1342 if (cbuf) {
1343 MacroAssembler _masm(cbuf);
1344 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1345 #ifndef PRODUCT
1346 } else {
1347 st->print("movl [rsp + #%d], %s\t# spill",
1348 offset,
1349 Matcher::regName[src_first]);
1350 #endif
1351 }
1352 }
1353 return 0;
1354 } else if (dst_first_rc == rc_int) {
1355 // gpr -> gpr
1356 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1357 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1358 // 64-bit
1359 if (cbuf) {
1360 MacroAssembler _masm(cbuf);
1361 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1362 as_Register(Matcher::_regEncode[src_first]));
1363 #ifndef PRODUCT
1364 } else {
1365 st->print("movq %s, %s\t# spill",
1366 Matcher::regName[dst_first],
1367 Matcher::regName[src_first]);
1368 #endif
1369 }
1370 return 0;
1371 } else {
1372 // 32-bit
1373 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1374 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1375 if (cbuf) {
1376 MacroAssembler _masm(cbuf);
1377 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1378 as_Register(Matcher::_regEncode[src_first]));
1379 #ifndef PRODUCT
1380 } else {
1381 st->print("movl %s, %s\t# spill",
1382 Matcher::regName[dst_first],
1383 Matcher::regName[src_first]);
1384 #endif
1385 }
1386 return 0;
1387 }
1388 } else if (dst_first_rc == rc_float) {
1389 // gpr -> xmm
1390 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1391 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1392 // 64-bit
1393 if (cbuf) {
1394 MacroAssembler _masm(cbuf);
1395 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1396 #ifndef PRODUCT
1397 } else {
1398 st->print("movdq %s, %s\t# spill",
1399 Matcher::regName[dst_first],
1400 Matcher::regName[src_first]);
1401 #endif
1402 }
1403 } else {
1404 // 32-bit
1405 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1406 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1407 if (cbuf) {
1408 MacroAssembler _masm(cbuf);
1409 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1410 #ifndef PRODUCT
1411 } else {
1412 st->print("movdl %s, %s\t# spill",
1413 Matcher::regName[dst_first],
1414 Matcher::regName[src_first]);
1415 #endif
1416 }
1417 }
1418 return 0;
1419 }
1420 } else if (src_first_rc == rc_float) {
1421 // xmm ->
1422 if (dst_first_rc == rc_stack) {
1423 // xmm -> mem
1424 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1425 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1426 // 64-bit
1427 int offset = ra_->reg2offset(dst_first);
1428 if (cbuf) {
1429 MacroAssembler _masm(cbuf);
1430 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1431 #ifndef PRODUCT
1432 } else {
1433 st->print("movsd [rsp + #%d], %s\t# spill",
1434 offset,
1435 Matcher::regName[src_first]);
1436 #endif
1437 }
1438 } else {
1439 // 32-bit
1440 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1441 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1442 int offset = ra_->reg2offset(dst_first);
1443 if (cbuf) {
1444 MacroAssembler _masm(cbuf);
1445 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1446 #ifndef PRODUCT
1447 } else {
1448 st->print("movss [rsp + #%d], %s\t# spill",
1449 offset,
1450 Matcher::regName[src_first]);
1451 #endif
1452 }
1453 }
1454 return 0;
1455 } else if (dst_first_rc == rc_int) {
1456 // xmm -> gpr
1457 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1458 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1459 // 64-bit
1460 if (cbuf) {
1461 MacroAssembler _masm(cbuf);
1462 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1463 #ifndef PRODUCT
1464 } else {
1465 st->print("movdq %s, %s\t# spill",
1466 Matcher::regName[dst_first],
1467 Matcher::regName[src_first]);
1468 #endif
1469 }
1470 } else {
1471 // 32-bit
1472 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1473 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1474 if (cbuf) {
1475 MacroAssembler _masm(cbuf);
1476 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1477 #ifndef PRODUCT
1478 } else {
1479 st->print("movdl %s, %s\t# spill",
1480 Matcher::regName[dst_first],
1481 Matcher::regName[src_first]);
1482 #endif
1483 }
1484 }
1485 return 0;
1486 } else if (dst_first_rc == rc_float) {
1487 // xmm -> xmm
1488 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1489 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1490 // 64-bit
1491 if (cbuf) {
1492 MacroAssembler _masm(cbuf);
1493 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1494 #ifndef PRODUCT
1495 } else {
1496 st->print("%s %s, %s\t# spill",
1497 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1498 Matcher::regName[dst_first],
1499 Matcher::regName[src_first]);
1500 #endif
1501 }
1502 } else {
1503 // 32-bit
1504 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1505 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1506 if (cbuf) {
1507 MacroAssembler _masm(cbuf);
1508 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1509 #ifndef PRODUCT
1510 } else {
1511 st->print("%s %s, %s\t# spill",
1512 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1513 Matcher::regName[dst_first],
1514 Matcher::regName[src_first]);
1515 #endif
1516 }
1517 }
1518 return 0;
1519 }
1520 }
1521
1522 assert(0," foo ");
1523 Unimplemented();
1524 return 0;
1525 }
1526
1527 #ifndef PRODUCT
1528 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1529 implementation(NULL, ra_, false, st);
1530 }
1531 #endif
1532
1533 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1534 implementation(&cbuf, ra_, false, NULL);
1535 }
1536
1537 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1538 return MachNode::size(ra_);
1539 }
1540
1541 //=============================================================================
1542 #ifndef PRODUCT
1543 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1544 {
1545 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1546 int reg = ra_->get_reg_first(this);
1547 st->print("leaq %s, [rsp + #%d]\t# box lock",
1548 Matcher::regName[reg], offset);
1549 }
1550 #endif
1551
1552 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1553 {
1554 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1555 int reg = ra_->get_encode(this);
1556 if (offset >= 0x80) {
1557 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1558 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1559 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1560 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1561 emit_d32(cbuf, offset);
1562 } else {
1563 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1564 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1565 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1566 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1567 emit_d8(cbuf, offset);
1568 }
1569 }
1570
1571 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1572 {
1573 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1574 return (offset < 0x80) ? 5 : 8; // REX
1575 }
1576
1577 //=============================================================================
1578 #ifndef PRODUCT
1579 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1580 {
1581 if (UseCompressedClassPointers) {
1582 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1583 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1584 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1585 } else {
1586 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1587 "# Inline cache check");
1588 }
1589 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1590 st->print_cr("\tnop\t# nops to align entry point");
1591 }
1592 #endif
1593
1594 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1595 {
1596 MacroAssembler masm(&cbuf);
1597 uint insts_size = cbuf.insts_size();
1598 if (UseCompressedClassPointers) {
1599 masm.load_klass(rscratch1, j_rarg0);
1600 masm.cmpptr(rax, rscratch1);
1601 } else {
1602 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1603 }
1604
1605 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1606
1607 /* WARNING these NOPs are critical so that verified entry point is properly
1608 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1609 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1610 if (OptoBreakpoint) {
1611 // Leave space for int3
1612 nops_cnt -= 1;
1613 }
1614 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1615 if (nops_cnt > 0)
1616 masm.nop(nops_cnt);
1617 }
1618
1619 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1620 {
1621 return MachNode::size(ra_); // too many variables; just compute it
1622 // the hard way
1623 }
1624
1625
1626 //=============================================================================
1627
1628 int Matcher::regnum_to_fpu_offset(int regnum)
1629 {
1630 return regnum - 32; // The FP registers are in the second chunk
1631 }
1632
1633 // This is UltraSparc specific, true just means we have fast l2f conversion
1634 const bool Matcher::convL2FSupported(void) {
1635 return true;
1636 }
1637
1638 // Is this branch offset short enough that a short branch can be used?
1639 //
1640 // NOTE: If the platform does not provide any short branch variants, then
1641 // this method should return false for offset 0.
1642 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1643 // The passed offset is relative to address of the branch.
1644 // On 86 a branch displacement is calculated relative to address
1645 // of a next instruction.
1646 offset -= br_size;
1647
1648 // the short version of jmpConUCF2 contains multiple branches,
1649 // making the reach slightly less
1650 if (rule == jmpConUCF2_rule)
1651 return (-126 <= offset && offset <= 125);
1652 return (-128 <= offset && offset <= 127);
1653 }
1654
1655 const bool Matcher::isSimpleConstant64(jlong value) {
1656 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1657 //return value == (int) value; // Cf. storeImmL and immL32.
1658
1659 // Probably always true, even if a temp register is required.
1660 return true;
1661 }
1662
1663 // The ecx parameter to rep stosq for the ClearArray node is in words.
1664 const bool Matcher::init_array_count_is_in_bytes = false;
1665
1666 // No additional cost for CMOVL.
1667 const int Matcher::long_cmove_cost() { return 0; }
1668
1669 // No CMOVF/CMOVD with SSE2
1670 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1671
1672 // Does the CPU require late expand (see block.cpp for description of late expand)?
1673 const bool Matcher::require_postalloc_expand = false;
1674
1675 // Do we need to mask the count passed to shift instructions or does
1676 // the cpu only look at the lower 5/6 bits anyway?
1677 const bool Matcher::need_masked_shift_count = false;
1678
1679 bool Matcher::narrow_oop_use_complex_address() {
1680 assert(UseCompressedOops, "only for compressed oops code");
1681 return (LogMinObjAlignmentInBytes <= 3);
1682 }
1683
1684 bool Matcher::narrow_klass_use_complex_address() {
1685 assert(UseCompressedClassPointers, "only for compressed klass code");
1686 return (LogKlassAlignmentInBytes <= 3);
1687 }
1688
1689 bool Matcher::const_oop_prefer_decode() {
1690 // Prefer ConN+DecodeN over ConP.
1691 return true;
1692 }
1693
1694 bool Matcher::const_klass_prefer_decode() {
1695 // TODO: Either support matching DecodeNKlass (heap-based) in operand
1696 // or condisider the following:
1697 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1698 //return Universe::narrow_klass_base() == NULL;
1699 return true;
1700 }
1701
1702 // Is it better to copy float constants, or load them directly from
1703 // memory? Intel can load a float constant from a direct address,
1704 // requiring no extra registers. Most RISCs will have to materialize
1705 // an address into a register first, so they would do better to copy
1706 // the constant from stack.
1707 const bool Matcher::rematerialize_float_constants = true; // XXX
1708
1709 // If CPU can load and store mis-aligned doubles directly then no
1710 // fixup is needed. Else we split the double into 2 integer pieces
1711 // and move it piece-by-piece. Only happens when passing doubles into
1712 // C code as the Java calling convention forces doubles to be aligned.
1713 const bool Matcher::misaligned_doubles_ok = true;
1714
1715 // No-op on amd64
1716 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1717
1718 // Advertise here if the CPU requires explicit rounding operations to
1719 // implement the UseStrictFP mode.
1720 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1721
1722 // Are floats conerted to double when stored to stack during deoptimization?
1723 // On x64 it is stored without convertion so we can use normal access.
1724 bool Matcher::float_in_double() { return false; }
1725
1726 // Do ints take an entire long register or just half?
1727 const bool Matcher::int_in_long = true;
1728
1729 // Return whether or not this register is ever used as an argument.
1730 // This function is used on startup to build the trampoline stubs in
1731 // generateOptoStub. Registers not mentioned will be killed by the VM
1732 // call in the trampoline, and arguments in those registers not be
1733 // available to the callee.
1734 bool Matcher::can_be_java_arg(int reg)
1735 {
1736 return
1737 reg == RDI_num || reg == RDI_H_num ||
1738 reg == RSI_num || reg == RSI_H_num ||
1739 reg == RDX_num || reg == RDX_H_num ||
1740 reg == RCX_num || reg == RCX_H_num ||
1741 reg == R8_num || reg == R8_H_num ||
1742 reg == R9_num || reg == R9_H_num ||
1743 reg == R12_num || reg == R12_H_num ||
1744 reg == XMM0_num || reg == XMM0b_num ||
1745 reg == XMM1_num || reg == XMM1b_num ||
1746 reg == XMM2_num || reg == XMM2b_num ||
1747 reg == XMM3_num || reg == XMM3b_num ||
1748 reg == XMM4_num || reg == XMM4b_num ||
1749 reg == XMM5_num || reg == XMM5b_num ||
1750 reg == XMM6_num || reg == XMM6b_num ||
1751 reg == XMM7_num || reg == XMM7b_num;
1752 }
1753
1754 bool Matcher::is_spillable_arg(int reg)
1755 {
1756 return can_be_java_arg(reg);
1757 }
1758
1759 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1760 // In 64 bit mode a code which use multiply when
1761 // devisor is constant is faster than hardware
1762 // DIV instruction (it uses MulHiL).
1763 return false;
1764 }
1765
1766 // Register for DIVI projection of divmodI
1767 RegMask Matcher::divI_proj_mask() {
1768 return INT_RAX_REG_mask();
1769 }
1770
1771 // Register for MODI projection of divmodI
1772 RegMask Matcher::modI_proj_mask() {
1773 return INT_RDX_REG_mask();
1774 }
1775
1776 // Register for DIVL projection of divmodL
1777 RegMask Matcher::divL_proj_mask() {
1778 return LONG_RAX_REG_mask();
1779 }
1780
1781 // Register for MODL projection of divmodL
1782 RegMask Matcher::modL_proj_mask() {
1783 return LONG_RDX_REG_mask();
1784 }
1785
1786 // Register for saving SP into on method handle invokes. Not used on x86_64.
1787 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1788 return NO_REG_mask();
1789 }
1790
1791 %}
1792
1793 //----------ENCODING BLOCK-----------------------------------------------------
1794 // This block specifies the encoding classes used by the compiler to
1795 // output byte streams. Encoding classes are parameterized macros
1796 // used by Machine Instruction Nodes in order to generate the bit
1797 // encoding of the instruction. Operands specify their base encoding
1798 // interface with the interface keyword. There are currently
1799 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1800 // COND_INTER. REG_INTER causes an operand to generate a function
1801 // which returns its register number when queried. CONST_INTER causes
1802 // an operand to generate a function which returns the value of the
1803 // constant when queried. MEMORY_INTER causes an operand to generate
1804 // four functions which return the Base Register, the Index Register,
1805 // the Scale Value, and the Offset Value of the operand when queried.
1806 // COND_INTER causes an operand to generate six functions which return
1807 // the encoding code (ie - encoding bits for the instruction)
1808 // associated with each basic boolean condition for a conditional
1809 // instruction.
1810 //
1811 // Instructions specify two basic values for encoding. Again, a
1812 // function is available to check if the constant displacement is an
1813 // oop. They use the ins_encode keyword to specify their encoding
1814 // classes (which must be a sequence of enc_class names, and their
1815 // parameters, specified in the encoding block), and they use the
1816 // opcode keyword to specify, in order, their primary, secondary, and
1817 // tertiary opcode. Only the opcode sections which a particular
1818 // instruction needs for encoding need to be specified.
1819 encode %{
1820 // Build emit functions for each basic byte or larger field in the
1821 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1822 // from C++ code in the enc_class source block. Emit functions will
1823 // live in the main source block for now. In future, we can
1824 // generalize this by adding a syntax that specifies the sizes of
1825 // fields in an order, so that the adlc can build the emit functions
1826 // automagically
1827
1828 // Emit primary opcode
1829 enc_class OpcP
1830 %{
1831 emit_opcode(cbuf, $primary);
1832 %}
1833
1834 // Emit secondary opcode
1835 enc_class OpcS
1836 %{
1837 emit_opcode(cbuf, $secondary);
1838 %}
1839
1840 // Emit tertiary opcode
1841 enc_class OpcT
1842 %{
1843 emit_opcode(cbuf, $tertiary);
1844 %}
1845
1846 // Emit opcode directly
1847 enc_class Opcode(immI d8)
1848 %{
1849 emit_opcode(cbuf, $d8$$constant);
1850 %}
1851
1852 // Emit size prefix
1853 enc_class SizePrefix
1854 %{
1855 emit_opcode(cbuf, 0x66);
1856 %}
1857
1858 enc_class reg(rRegI reg)
1859 %{
1860 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1861 %}
1862
1863 enc_class reg_reg(rRegI dst, rRegI src)
1864 %{
1865 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1866 %}
1867
1868 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1869 %{
1870 emit_opcode(cbuf, $opcode$$constant);
1871 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1872 %}
1873
1874 enc_class cdql_enc(no_rax_rdx_RegI div)
1875 %{
1876 // Full implementation of Java idiv and irem; checks for
1877 // special case as described in JVM spec., p.243 & p.271.
1878 //
1879 // normal case special case
1880 //
1881 // input : rax: dividend min_int
1882 // reg: divisor -1
1883 //
1884 // output: rax: quotient (= rax idiv reg) min_int
1885 // rdx: remainder (= rax irem reg) 0
1886 //
1887 // Code sequnce:
1888 //
1889 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1890 // 5: 75 07/08 jne e <normal>
1891 // 7: 33 d2 xor %edx,%edx
1892 // [div >= 8 -> offset + 1]
1893 // [REX_B]
1894 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1895 // c: 74 03/04 je 11 <done>
1896 // 000000000000000e <normal>:
1897 // e: 99 cltd
1898 // [div >= 8 -> offset + 1]
1899 // [REX_B]
1900 // f: f7 f9 idiv $div
1901 // 0000000000000011 <done>:
1902
1903 // cmp $0x80000000,%eax
1904 emit_opcode(cbuf, 0x3d);
1905 emit_d8(cbuf, 0x00);
1906 emit_d8(cbuf, 0x00);
1907 emit_d8(cbuf, 0x00);
1908 emit_d8(cbuf, 0x80);
1909
1910 // jne e <normal>
1911 emit_opcode(cbuf, 0x75);
1912 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1913
1914 // xor %edx,%edx
1915 emit_opcode(cbuf, 0x33);
1916 emit_d8(cbuf, 0xD2);
1917
1918 // cmp $0xffffffffffffffff,%ecx
1919 if ($div$$reg >= 8) {
1920 emit_opcode(cbuf, Assembler::REX_B);
1921 }
1922 emit_opcode(cbuf, 0x83);
1923 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1924 emit_d8(cbuf, 0xFF);
1925
1926 // je 11 <done>
1927 emit_opcode(cbuf, 0x74);
1928 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1929
1930 // <normal>
1931 // cltd
1932 emit_opcode(cbuf, 0x99);
1933
1934 // idivl (note: must be emitted by the user of this rule)
1935 // <done>
1936 %}
1937
1938 enc_class cdqq_enc(no_rax_rdx_RegL div)
1939 %{
1940 // Full implementation of Java ldiv and lrem; checks for
1941 // special case as described in JVM spec., p.243 & p.271.
1942 //
1943 // normal case special case
1944 //
1945 // input : rax: dividend min_long
1946 // reg: divisor -1
1947 //
1948 // output: rax: quotient (= rax idiv reg) min_long
1949 // rdx: remainder (= rax irem reg) 0
1950 //
1951 // Code sequnce:
1952 //
1953 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1954 // 7: 00 00 80
1955 // a: 48 39 d0 cmp %rdx,%rax
1956 // d: 75 08 jne 17 <normal>
1957 // f: 33 d2 xor %edx,%edx
1958 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1959 // 15: 74 05 je 1c <done>
1960 // 0000000000000017 <normal>:
1961 // 17: 48 99 cqto
1962 // 19: 48 f7 f9 idiv $div
1963 // 000000000000001c <done>:
1964
1965 // mov $0x8000000000000000,%rdx
1966 emit_opcode(cbuf, Assembler::REX_W);
1967 emit_opcode(cbuf, 0xBA);
1968 emit_d8(cbuf, 0x00);
1969 emit_d8(cbuf, 0x00);
1970 emit_d8(cbuf, 0x00);
1971 emit_d8(cbuf, 0x00);
1972 emit_d8(cbuf, 0x00);
1973 emit_d8(cbuf, 0x00);
1974 emit_d8(cbuf, 0x00);
1975 emit_d8(cbuf, 0x80);
1976
1977 // cmp %rdx,%rax
1978 emit_opcode(cbuf, Assembler::REX_W);
1979 emit_opcode(cbuf, 0x39);
1980 emit_d8(cbuf, 0xD0);
1981
1982 // jne 17 <normal>
1983 emit_opcode(cbuf, 0x75);
1984 emit_d8(cbuf, 0x08);
1985
1986 // xor %edx,%edx
1987 emit_opcode(cbuf, 0x33);
1988 emit_d8(cbuf, 0xD2);
1989
1990 // cmp $0xffffffffffffffff,$div
1991 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1992 emit_opcode(cbuf, 0x83);
1993 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1994 emit_d8(cbuf, 0xFF);
1995
1996 // je 1e <done>
1997 emit_opcode(cbuf, 0x74);
1998 emit_d8(cbuf, 0x05);
1999
2000 // <normal>
2001 // cqto
2002 emit_opcode(cbuf, Assembler::REX_W);
2003 emit_opcode(cbuf, 0x99);
2004
2005 // idivq (note: must be emitted by the user of this rule)
2006 // <done>
2007 %}
2008
2009 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2010 enc_class OpcSE(immI imm)
2011 %{
2012 // Emit primary opcode and set sign-extend bit
2013 // Check for 8-bit immediate, and set sign extend bit in opcode
2014 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2015 emit_opcode(cbuf, $primary | 0x02);
2016 } else {
2017 // 32-bit immediate
2018 emit_opcode(cbuf, $primary);
2019 }
2020 %}
2021
2022 enc_class OpcSErm(rRegI dst, immI imm)
2023 %{
2024 // OpcSEr/m
2025 int dstenc = $dst$$reg;
2026 if (dstenc >= 8) {
2027 emit_opcode(cbuf, Assembler::REX_B);
2028 dstenc -= 8;
2029 }
2030 // Emit primary opcode and set sign-extend bit
2031 // Check for 8-bit immediate, and set sign extend bit in opcode
2032 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2033 emit_opcode(cbuf, $primary | 0x02);
2034 } else {
2035 // 32-bit immediate
2036 emit_opcode(cbuf, $primary);
2037 }
2038 // Emit r/m byte with secondary opcode, after primary opcode.
2039 emit_rm(cbuf, 0x3, $secondary, dstenc);
2040 %}
2041
2042 enc_class OpcSErm_wide(rRegL dst, immI imm)
2043 %{
2044 // OpcSEr/m
2045 int dstenc = $dst$$reg;
2046 if (dstenc < 8) {
2047 emit_opcode(cbuf, Assembler::REX_W);
2048 } else {
2049 emit_opcode(cbuf, Assembler::REX_WB);
2050 dstenc -= 8;
2051 }
2052 // Emit primary opcode and set sign-extend bit
2053 // Check for 8-bit immediate, and set sign extend bit in opcode
2054 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2055 emit_opcode(cbuf, $primary | 0x02);
2056 } else {
2057 // 32-bit immediate
2058 emit_opcode(cbuf, $primary);
2059 }
2060 // Emit r/m byte with secondary opcode, after primary opcode.
2061 emit_rm(cbuf, 0x3, $secondary, dstenc);
2062 %}
2063
2064 enc_class Con8or32(immI imm)
2065 %{
2066 // Check for 8-bit immediate, and set sign extend bit in opcode
2067 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2068 $$$emit8$imm$$constant;
2069 } else {
2070 // 32-bit immediate
2071 $$$emit32$imm$$constant;
2072 }
2073 %}
2074
2075 enc_class opc2_reg(rRegI dst)
2076 %{
2077 // BSWAP
2078 emit_cc(cbuf, $secondary, $dst$$reg);
2079 %}
2080
2081 enc_class opc3_reg(rRegI dst)
2082 %{
2083 // BSWAP
2084 emit_cc(cbuf, $tertiary, $dst$$reg);
2085 %}
2086
2087 enc_class reg_opc(rRegI div)
2088 %{
2089 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2090 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2091 %}
2092
2093 enc_class enc_cmov(cmpOp cop)
2094 %{
2095 // CMOV
2096 $$$emit8$primary;
2097 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2098 %}
2099
2100 enc_class enc_PartialSubtypeCheck()
2101 %{
2102 Register Rrdi = as_Register(RDI_enc); // result register
2103 Register Rrax = as_Register(RAX_enc); // super class
2104 Register Rrcx = as_Register(RCX_enc); // killed
2105 Register Rrsi = as_Register(RSI_enc); // sub class
2106 Label miss;
2107 const bool set_cond_codes = true;
2108
2109 MacroAssembler _masm(&cbuf);
2110 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2111 NULL, &miss,
2112 /*set_cond_codes:*/ true);
2113 if ($primary) {
2114 __ xorptr(Rrdi, Rrdi);
2115 }
2116 __ bind(miss);
2117 %}
2118
2119 enc_class clear_avx %{
2120 debug_only(int off0 = cbuf.insts_size());
2121 if (generate_vzeroupper(Compile::current())) {
2122 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2123 // Clear upper bits of YMM registers when current compiled code uses
2124 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2125 MacroAssembler _masm(&cbuf);
2126 __ vzeroupper();
2127 }
2128 debug_only(int off1 = cbuf.insts_size());
2129 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2130 %}
2131
2132 enc_class Java_To_Runtime(method meth) %{
2133 // No relocation needed
2134 MacroAssembler _masm(&cbuf);
2135 __ mov64(r10, (int64_t) $meth$$method);
2136 __ call(r10);
2137 %}
2138
2139 enc_class Java_To_Interpreter(method meth)
2140 %{
2141 // CALL Java_To_Interpreter
2142 // This is the instruction starting address for relocation info.
2143 cbuf.set_insts_mark();
2144 $$$emit8$primary;
2145 // CALL directly to the runtime
2146 emit_d32_reloc(cbuf,
2147 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2148 runtime_call_Relocation::spec(),
2149 RELOC_DISP32);
2150 %}
2151
2152 enc_class Java_Static_Call(method meth)
2153 %{
2154 // JAVA STATIC CALL
2155 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2156 // determine who we intended to call.
2157 cbuf.set_insts_mark();
2158 $$$emit8$primary;
2159
2160 if (!_method) {
2161 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2162 runtime_call_Relocation::spec(),
2163 RELOC_DISP32);
2164 } else {
2165 int method_index = resolved_method_index(cbuf);
2166 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2167 : static_call_Relocation::spec(method_index);
2168 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2169 rspec, RELOC_DISP32);
2170 // Emit stubs for static call.
2171 address mark = cbuf.insts_mark();
2172 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2173 if (stub == NULL) {
2174 ciEnv::current()->record_failure("CodeCache is full");
2175 return;
2176 }
2177 #if INCLUDE_AOT
2178 CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2179 #endif
2180 }
2181 %}
2182
2183 enc_class Java_Dynamic_Call(method meth) %{
2184 MacroAssembler _masm(&cbuf);
2185 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2186 %}
2187
2188 enc_class Java_Compiled_Call(method meth)
2189 %{
2190 // JAVA COMPILED CALL
2191 int disp = in_bytes(Method:: from_compiled_offset());
2192
2193 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2194 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2195
2196 // callq *disp(%rax)
2197 cbuf.set_insts_mark();
2198 $$$emit8$primary;
2199 if (disp < 0x80) {
2200 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2201 emit_d8(cbuf, disp); // Displacement
2202 } else {
2203 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2204 emit_d32(cbuf, disp); // Displacement
2205 }
2206 %}
2207
2208 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2209 %{
2210 // SAL, SAR, SHR
2211 int dstenc = $dst$$reg;
2212 if (dstenc >= 8) {
2213 emit_opcode(cbuf, Assembler::REX_B);
2214 dstenc -= 8;
2215 }
2216 $$$emit8$primary;
2217 emit_rm(cbuf, 0x3, $secondary, dstenc);
2218 $$$emit8$shift$$constant;
2219 %}
2220
2221 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2222 %{
2223 // SAL, SAR, SHR
2224 int dstenc = $dst$$reg;
2225 if (dstenc < 8) {
2226 emit_opcode(cbuf, Assembler::REX_W);
2227 } else {
2228 emit_opcode(cbuf, Assembler::REX_WB);
2229 dstenc -= 8;
2230 }
2231 $$$emit8$primary;
2232 emit_rm(cbuf, 0x3, $secondary, dstenc);
2233 $$$emit8$shift$$constant;
2234 %}
2235
2236 enc_class load_immI(rRegI dst, immI src)
2237 %{
2238 int dstenc = $dst$$reg;
2239 if (dstenc >= 8) {
2240 emit_opcode(cbuf, Assembler::REX_B);
2241 dstenc -= 8;
2242 }
2243 emit_opcode(cbuf, 0xB8 | dstenc);
2244 $$$emit32$src$$constant;
2245 %}
2246
2247 enc_class load_immL(rRegL dst, immL src)
2248 %{
2249 int dstenc = $dst$$reg;
2250 if (dstenc < 8) {
2251 emit_opcode(cbuf, Assembler::REX_W);
2252 } else {
2253 emit_opcode(cbuf, Assembler::REX_WB);
2254 dstenc -= 8;
2255 }
2256 emit_opcode(cbuf, 0xB8 | dstenc);
2257 emit_d64(cbuf, $src$$constant);
2258 %}
2259
2260 enc_class load_immUL32(rRegL dst, immUL32 src)
2261 %{
2262 // same as load_immI, but this time we care about zeroes in the high word
2263 int dstenc = $dst$$reg;
2264 if (dstenc >= 8) {
2265 emit_opcode(cbuf, Assembler::REX_B);
2266 dstenc -= 8;
2267 }
2268 emit_opcode(cbuf, 0xB8 | dstenc);
2269 $$$emit32$src$$constant;
2270 %}
2271
2272 enc_class load_immL32(rRegL dst, immL32 src)
2273 %{
2274 int dstenc = $dst$$reg;
2275 if (dstenc < 8) {
2276 emit_opcode(cbuf, Assembler::REX_W);
2277 } else {
2278 emit_opcode(cbuf, Assembler::REX_WB);
2279 dstenc -= 8;
2280 }
2281 emit_opcode(cbuf, 0xC7);
2282 emit_rm(cbuf, 0x03, 0x00, dstenc);
2283 $$$emit32$src$$constant;
2284 %}
2285
2286 enc_class load_immP31(rRegP dst, immP32 src)
2287 %{
2288 // same as load_immI, but this time we care about zeroes in the high word
2289 int dstenc = $dst$$reg;
2290 if (dstenc >= 8) {
2291 emit_opcode(cbuf, Assembler::REX_B);
2292 dstenc -= 8;
2293 }
2294 emit_opcode(cbuf, 0xB8 | dstenc);
2295 $$$emit32$src$$constant;
2296 %}
2297
2298 enc_class load_immP(rRegP dst, immP src)
2299 %{
2300 int dstenc = $dst$$reg;
2301 if (dstenc < 8) {
2302 emit_opcode(cbuf, Assembler::REX_W);
2303 } else {
2304 emit_opcode(cbuf, Assembler::REX_WB);
2305 dstenc -= 8;
2306 }
2307 emit_opcode(cbuf, 0xB8 | dstenc);
2308 // This next line should be generated from ADLC
2309 if ($src->constant_reloc() != relocInfo::none) {
2310 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2311 } else {
2312 emit_d64(cbuf, $src$$constant);
2313 }
2314 %}
2315
2316 enc_class Con32(immI src)
2317 %{
2318 // Output immediate
2319 $$$emit32$src$$constant;
2320 %}
2321
2322 enc_class Con32F_as_bits(immF src)
2323 %{
2324 // Output Float immediate bits
2325 jfloat jf = $src$$constant;
2326 jint jf_as_bits = jint_cast(jf);
2327 emit_d32(cbuf, jf_as_bits);
2328 %}
2329
2330 enc_class Con16(immI src)
2331 %{
2332 // Output immediate
2333 $$$emit16$src$$constant;
2334 %}
2335
2336 // How is this different from Con32??? XXX
2337 enc_class Con_d32(immI src)
2338 %{
2339 emit_d32(cbuf,$src$$constant);
2340 %}
2341
2342 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2343 // Output immediate memory reference
2344 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2345 emit_d32(cbuf, 0x00);
2346 %}
2347
2348 enc_class lock_prefix()
2349 %{
2350 if (os::is_MP()) {
2351 emit_opcode(cbuf, 0xF0); // lock
2352 }
2353 %}
2354
2355 enc_class REX_mem(memory mem)
2356 %{
2357 if ($mem$$base >= 8) {
2358 if ($mem$$index < 8) {
2359 emit_opcode(cbuf, Assembler::REX_B);
2360 } else {
2361 emit_opcode(cbuf, Assembler::REX_XB);
2362 }
2363 } else {
2364 if ($mem$$index >= 8) {
2365 emit_opcode(cbuf, Assembler::REX_X);
2366 }
2367 }
2368 %}
2369
2370 enc_class REX_mem_wide(memory mem)
2371 %{
2372 if ($mem$$base >= 8) {
2373 if ($mem$$index < 8) {
2374 emit_opcode(cbuf, Assembler::REX_WB);
2375 } else {
2376 emit_opcode(cbuf, Assembler::REX_WXB);
2377 }
2378 } else {
2379 if ($mem$$index < 8) {
2380 emit_opcode(cbuf, Assembler::REX_W);
2381 } else {
2382 emit_opcode(cbuf, Assembler::REX_WX);
2383 }
2384 }
2385 %}
2386
2387 // for byte regs
2388 enc_class REX_breg(rRegI reg)
2389 %{
2390 if ($reg$$reg >= 4) {
2391 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2392 }
2393 %}
2394
2395 // for byte regs
2396 enc_class REX_reg_breg(rRegI dst, rRegI src)
2397 %{
2398 if ($dst$$reg < 8) {
2399 if ($src$$reg >= 4) {
2400 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2401 }
2402 } else {
2403 if ($src$$reg < 8) {
2404 emit_opcode(cbuf, Assembler::REX_R);
2405 } else {
2406 emit_opcode(cbuf, Assembler::REX_RB);
2407 }
2408 }
2409 %}
2410
2411 // for byte regs
2412 enc_class REX_breg_mem(rRegI reg, memory mem)
2413 %{
2414 if ($reg$$reg < 8) {
2415 if ($mem$$base < 8) {
2416 if ($mem$$index >= 8) {
2417 emit_opcode(cbuf, Assembler::REX_X);
2418 } else if ($reg$$reg >= 4) {
2419 emit_opcode(cbuf, Assembler::REX);
2420 }
2421 } else {
2422 if ($mem$$index < 8) {
2423 emit_opcode(cbuf, Assembler::REX_B);
2424 } else {
2425 emit_opcode(cbuf, Assembler::REX_XB);
2426 }
2427 }
2428 } else {
2429 if ($mem$$base < 8) {
2430 if ($mem$$index < 8) {
2431 emit_opcode(cbuf, Assembler::REX_R);
2432 } else {
2433 emit_opcode(cbuf, Assembler::REX_RX);
2434 }
2435 } else {
2436 if ($mem$$index < 8) {
2437 emit_opcode(cbuf, Assembler::REX_RB);
2438 } else {
2439 emit_opcode(cbuf, Assembler::REX_RXB);
2440 }
2441 }
2442 }
2443 %}
2444
2445 enc_class REX_reg(rRegI reg)
2446 %{
2447 if ($reg$$reg >= 8) {
2448 emit_opcode(cbuf, Assembler::REX_B);
2449 }
2450 %}
2451
2452 enc_class REX_reg_wide(rRegI reg)
2453 %{
2454 if ($reg$$reg < 8) {
2455 emit_opcode(cbuf, Assembler::REX_W);
2456 } else {
2457 emit_opcode(cbuf, Assembler::REX_WB);
2458 }
2459 %}
2460
2461 enc_class REX_reg_reg(rRegI dst, rRegI src)
2462 %{
2463 if ($dst$$reg < 8) {
2464 if ($src$$reg >= 8) {
2465 emit_opcode(cbuf, Assembler::REX_B);
2466 }
2467 } else {
2468 if ($src$$reg < 8) {
2469 emit_opcode(cbuf, Assembler::REX_R);
2470 } else {
2471 emit_opcode(cbuf, Assembler::REX_RB);
2472 }
2473 }
2474 %}
2475
2476 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2477 %{
2478 if ($dst$$reg < 8) {
2479 if ($src$$reg < 8) {
2480 emit_opcode(cbuf, Assembler::REX_W);
2481 } else {
2482 emit_opcode(cbuf, Assembler::REX_WB);
2483 }
2484 } else {
2485 if ($src$$reg < 8) {
2486 emit_opcode(cbuf, Assembler::REX_WR);
2487 } else {
2488 emit_opcode(cbuf, Assembler::REX_WRB);
2489 }
2490 }
2491 %}
2492
2493 enc_class REX_reg_mem(rRegI reg, memory mem)
2494 %{
2495 if ($reg$$reg < 8) {
2496 if ($mem$$base < 8) {
2497 if ($mem$$index >= 8) {
2498 emit_opcode(cbuf, Assembler::REX_X);
2499 }
2500 } else {
2501 if ($mem$$index < 8) {
2502 emit_opcode(cbuf, Assembler::REX_B);
2503 } else {
2504 emit_opcode(cbuf, Assembler::REX_XB);
2505 }
2506 }
2507 } else {
2508 if ($mem$$base < 8) {
2509 if ($mem$$index < 8) {
2510 emit_opcode(cbuf, Assembler::REX_R);
2511 } else {
2512 emit_opcode(cbuf, Assembler::REX_RX);
2513 }
2514 } else {
2515 if ($mem$$index < 8) {
2516 emit_opcode(cbuf, Assembler::REX_RB);
2517 } else {
2518 emit_opcode(cbuf, Assembler::REX_RXB);
2519 }
2520 }
2521 }
2522 %}
2523
2524 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2525 %{
2526 if ($reg$$reg < 8) {
2527 if ($mem$$base < 8) {
2528 if ($mem$$index < 8) {
2529 emit_opcode(cbuf, Assembler::REX_W);
2530 } else {
2531 emit_opcode(cbuf, Assembler::REX_WX);
2532 }
2533 } else {
2534 if ($mem$$index < 8) {
2535 emit_opcode(cbuf, Assembler::REX_WB);
2536 } else {
2537 emit_opcode(cbuf, Assembler::REX_WXB);
2538 }
2539 }
2540 } else {
2541 if ($mem$$base < 8) {
2542 if ($mem$$index < 8) {
2543 emit_opcode(cbuf, Assembler::REX_WR);
2544 } else {
2545 emit_opcode(cbuf, Assembler::REX_WRX);
2546 }
2547 } else {
2548 if ($mem$$index < 8) {
2549 emit_opcode(cbuf, Assembler::REX_WRB);
2550 } else {
2551 emit_opcode(cbuf, Assembler::REX_WRXB);
2552 }
2553 }
2554 }
2555 %}
2556
2557 enc_class reg_mem(rRegI ereg, memory mem)
2558 %{
2559 // High registers handle in encode_RegMem
2560 int reg = $ereg$$reg;
2561 int base = $mem$$base;
2562 int index = $mem$$index;
2563 int scale = $mem$$scale;
2564 int disp = $mem$$disp;
2565 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2566
2567 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2568 %}
2569
2570 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2571 %{
2572 int rm_byte_opcode = $rm_opcode$$constant;
2573
2574 // High registers handle in encode_RegMem
2575 int base = $mem$$base;
2576 int index = $mem$$index;
2577 int scale = $mem$$scale;
2578 int displace = $mem$$disp;
2579
2580 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2581 // working with static
2582 // globals
2583 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2584 disp_reloc);
2585 %}
2586
2587 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2588 %{
2589 int reg_encoding = $dst$$reg;
2590 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2591 int index = 0x04; // 0x04 indicates no index
2592 int scale = 0x00; // 0x00 indicates no scale
2593 int displace = $src1$$constant; // 0x00 indicates no displacement
2594 relocInfo::relocType disp_reloc = relocInfo::none;
2595 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2596 disp_reloc);
2597 %}
2598
2599 enc_class neg_reg(rRegI dst)
2600 %{
2601 int dstenc = $dst$$reg;
2602 if (dstenc >= 8) {
2603 emit_opcode(cbuf, Assembler::REX_B);
2604 dstenc -= 8;
2605 }
2606 // NEG $dst
2607 emit_opcode(cbuf, 0xF7);
2608 emit_rm(cbuf, 0x3, 0x03, dstenc);
2609 %}
2610
2611 enc_class neg_reg_wide(rRegI dst)
2612 %{
2613 int dstenc = $dst$$reg;
2614 if (dstenc < 8) {
2615 emit_opcode(cbuf, Assembler::REX_W);
2616 } else {
2617 emit_opcode(cbuf, Assembler::REX_WB);
2618 dstenc -= 8;
2619 }
2620 // NEG $dst
2621 emit_opcode(cbuf, 0xF7);
2622 emit_rm(cbuf, 0x3, 0x03, dstenc);
2623 %}
2624
2625 enc_class setLT_reg(rRegI dst)
2626 %{
2627 int dstenc = $dst$$reg;
2628 if (dstenc >= 8) {
2629 emit_opcode(cbuf, Assembler::REX_B);
2630 dstenc -= 8;
2631 } else if (dstenc >= 4) {
2632 emit_opcode(cbuf, Assembler::REX);
2633 }
2634 // SETLT $dst
2635 emit_opcode(cbuf, 0x0F);
2636 emit_opcode(cbuf, 0x9C);
2637 emit_rm(cbuf, 0x3, 0x0, dstenc);
2638 %}
2639
2640 enc_class setNZ_reg(rRegI dst)
2641 %{
2642 int dstenc = $dst$$reg;
2643 if (dstenc >= 8) {
2644 emit_opcode(cbuf, Assembler::REX_B);
2645 dstenc -= 8;
2646 } else if (dstenc >= 4) {
2647 emit_opcode(cbuf, Assembler::REX);
2648 }
2649 // SETNZ $dst
2650 emit_opcode(cbuf, 0x0F);
2651 emit_opcode(cbuf, 0x95);
2652 emit_rm(cbuf, 0x3, 0x0, dstenc);
2653 %}
2654
2655
2656 // Compare the lonogs and set -1, 0, or 1 into dst
2657 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2658 %{
2659 int src1enc = $src1$$reg;
2660 int src2enc = $src2$$reg;
2661 int dstenc = $dst$$reg;
2662
2663 // cmpq $src1, $src2
2664 if (src1enc < 8) {
2665 if (src2enc < 8) {
2666 emit_opcode(cbuf, Assembler::REX_W);
2667 } else {
2668 emit_opcode(cbuf, Assembler::REX_WB);
2669 }
2670 } else {
2671 if (src2enc < 8) {
2672 emit_opcode(cbuf, Assembler::REX_WR);
2673 } else {
2674 emit_opcode(cbuf, Assembler::REX_WRB);
2675 }
2676 }
2677 emit_opcode(cbuf, 0x3B);
2678 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2679
2680 // movl $dst, -1
2681 if (dstenc >= 8) {
2682 emit_opcode(cbuf, Assembler::REX_B);
2683 }
2684 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2685 emit_d32(cbuf, -1);
2686
2687 // jl,s done
2688 emit_opcode(cbuf, 0x7C);
2689 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2690
2691 // setne $dst
2692 if (dstenc >= 4) {
2693 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2694 }
2695 emit_opcode(cbuf, 0x0F);
2696 emit_opcode(cbuf, 0x95);
2697 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2698
2699 // movzbl $dst, $dst
2700 if (dstenc >= 4) {
2701 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2702 }
2703 emit_opcode(cbuf, 0x0F);
2704 emit_opcode(cbuf, 0xB6);
2705 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2706 %}
2707
2708 enc_class Push_ResultXD(regD dst) %{
2709 MacroAssembler _masm(&cbuf);
2710 __ fstp_d(Address(rsp, 0));
2711 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2712 __ addptr(rsp, 8);
2713 %}
2714
2715 enc_class Push_SrcXD(regD src) %{
2716 MacroAssembler _masm(&cbuf);
2717 __ subptr(rsp, 8);
2718 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2719 __ fld_d(Address(rsp, 0));
2720 %}
2721
2722
2723 enc_class enc_rethrow()
2724 %{
2725 cbuf.set_insts_mark();
2726 emit_opcode(cbuf, 0xE9); // jmp entry
2727 emit_d32_reloc(cbuf,
2728 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2729 runtime_call_Relocation::spec(),
2730 RELOC_DISP32);
2731 %}
2732
2733 %}
2734
2735
2736
2737 //----------FRAME--------------------------------------------------------------
2738 // Definition of frame structure and management information.
2739 //
2740 // S T A C K L A Y O U T Allocators stack-slot number
2741 // | (to get allocators register number
2742 // G Owned by | | v add OptoReg::stack0())
2743 // r CALLER | |
2744 // o | +--------+ pad to even-align allocators stack-slot
2745 // w V | pad0 | numbers; owned by CALLER
2746 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2747 // h ^ | in | 5
2748 // | | args | 4 Holes in incoming args owned by SELF
2749 // | | | | 3
2750 // | | +--------+
2751 // V | | old out| Empty on Intel, window on Sparc
2752 // | old |preserve| Must be even aligned.
2753 // | SP-+--------+----> Matcher::_old_SP, even aligned
2754 // | | in | 3 area for Intel ret address
2755 // Owned by |preserve| Empty on Sparc.
2756 // SELF +--------+
2757 // | | pad2 | 2 pad to align old SP
2758 // | +--------+ 1
2759 // | | locks | 0
2760 // | +--------+----> OptoReg::stack0(), even aligned
2761 // | | pad1 | 11 pad to align new SP
2762 // | +--------+
2763 // | | | 10
2764 // | | spills | 9 spills
2765 // V | | 8 (pad0 slot for callee)
2766 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2767 // ^ | out | 7
2768 // | | args | 6 Holes in outgoing args owned by CALLEE
2769 // Owned by +--------+
2770 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2771 // | new |preserve| Must be even-aligned.
2772 // | SP-+--------+----> Matcher::_new_SP, even aligned
2773 // | | |
2774 //
2775 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2776 // known from SELF's arguments and the Java calling convention.
2777 // Region 6-7 is determined per call site.
2778 // Note 2: If the calling convention leaves holes in the incoming argument
2779 // area, those holes are owned by SELF. Holes in the outgoing area
2780 // are owned by the CALLEE. Holes should not be nessecary in the
2781 // incoming area, as the Java calling convention is completely under
2782 // the control of the AD file. Doubles can be sorted and packed to
2783 // avoid holes. Holes in the outgoing arguments may be nessecary for
2784 // varargs C calling conventions.
2785 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2786 // even aligned with pad0 as needed.
2787 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2788 // region 6-11 is even aligned; it may be padded out more so that
2789 // the region from SP to FP meets the minimum stack alignment.
2790 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2791 // alignment. Region 11, pad1, may be dynamically extended so that
2792 // SP meets the minimum alignment.
2793
2794 frame
2795 %{
2796 // What direction does stack grow in (assumed to be same for C & Java)
2797 stack_direction(TOWARDS_LOW);
2798
2799 // These three registers define part of the calling convention
2800 // between compiled code and the interpreter.
2801 inline_cache_reg(RAX); // Inline Cache Register
2802 interpreter_method_oop_reg(RBX); // Method Oop Register when
2803 // calling interpreter
2804
2805 // Optional: name the operand used by cisc-spilling to access
2806 // [stack_pointer + offset]
2807 cisc_spilling_operand_name(indOffset32);
2808
2809 // Number of stack slots consumed by locking an object
2810 sync_stack_slots(2);
2811
2812 // Compiled code's Frame Pointer
2813 frame_pointer(RSP);
2814
2815 // Interpreter stores its frame pointer in a register which is
2816 // stored to the stack by I2CAdaptors.
2817 // I2CAdaptors convert from interpreted java to compiled java.
2818 interpreter_frame_pointer(RBP);
2819
2820 // Stack alignment requirement
2821 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2822
2823 // Number of stack slots between incoming argument block and the start of
2824 // a new frame. The PROLOG must add this many slots to the stack. The
2825 // EPILOG must remove this many slots. amd64 needs two slots for
2826 // return address.
2827 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2828
2829 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2830 // for calls to C. Supports the var-args backing area for register parms.
2831 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2832
2833 // The after-PROLOG location of the return address. Location of
2834 // return address specifies a type (REG or STACK) and a number
2835 // representing the register number (i.e. - use a register name) or
2836 // stack slot.
2837 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2838 // Otherwise, it is above the locks and verification slot and alignment word
2839 return_addr(STACK - 2 +
2840 align_up((Compile::current()->in_preserve_stack_slots() +
2841 Compile::current()->fixed_slots()),
2842 stack_alignment_in_slots()));
2843
2844 // Body of function which returns an integer array locating
2845 // arguments either in registers or in stack slots. Passed an array
2846 // of ideal registers called "sig" and a "length" count. Stack-slot
2847 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2848 // arguments for a CALLEE. Incoming stack arguments are
2849 // automatically biased by the preserve_stack_slots field above.
2850
2851 calling_convention
2852 %{
2853 // No difference between ingoing/outgoing just pass false
2854 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2855 %}
2856
2857 c_calling_convention
2858 %{
2859 // This is obviously always outgoing
2860 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2861 %}
2862
2863 // Location of compiled Java return values. Same as C for now.
2864 return_value
2865 %{
2866 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2867 "only return normal values");
2868
2869 static const int lo[Op_RegL + 1] = {
2870 0,
2871 0,
2872 RAX_num, // Op_RegN
2873 RAX_num, // Op_RegI
2874 RAX_num, // Op_RegP
2875 XMM0_num, // Op_RegF
2876 XMM0_num, // Op_RegD
2877 RAX_num // Op_RegL
2878 };
2879 static const int hi[Op_RegL + 1] = {
2880 0,
2881 0,
2882 OptoReg::Bad, // Op_RegN
2883 OptoReg::Bad, // Op_RegI
2884 RAX_H_num, // Op_RegP
2885 OptoReg::Bad, // Op_RegF
2886 XMM0b_num, // Op_RegD
2887 RAX_H_num // Op_RegL
2888 };
2889 // Excluded flags and vector registers.
2890 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2891 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2892 %}
2893 %}
2894
2895 //----------ATTRIBUTES---------------------------------------------------------
2896 //----------Operand Attributes-------------------------------------------------
2897 op_attrib op_cost(0); // Required cost attribute
2898
2899 //----------Instruction Attributes---------------------------------------------
2900 ins_attrib ins_cost(100); // Required cost attribute
2901 ins_attrib ins_size(8); // Required size attribute (in bits)
2902 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2903 // a non-matching short branch variant
2904 // of some long branch?
2905 ins_attrib ins_alignment(1); // Required alignment attribute (must
2906 // be a power of 2) specifies the
2907 // alignment that some part of the
2908 // instruction (not necessarily the
2909 // start) requires. If > 1, a
2910 // compute_padding() function must be
2911 // provided for the instruction
2912
2913 //----------OPERANDS-----------------------------------------------------------
2914 // Operand definitions must precede instruction definitions for correct parsing
2915 // in the ADLC because operands constitute user defined types which are used in
2916 // instruction definitions.
2917
2918 //----------Simple Operands----------------------------------------------------
2919 // Immediate Operands
2920 // Integer Immediate
2921 operand immI()
2922 %{
2923 match(ConI);
2924
2925 op_cost(10);
2926 format %{ %}
2927 interface(CONST_INTER);
2928 %}
2929
2930 // Constant for test vs zero
2931 operand immI0()
2932 %{
2933 predicate(n->get_int() == 0);
2934 match(ConI);
2935
2936 op_cost(0);
2937 format %{ %}
2938 interface(CONST_INTER);
2939 %}
2940
2941 // Constant for increment
2942 operand immI1()
2943 %{
2944 predicate(n->get_int() == 1);
2945 match(ConI);
2946
2947 op_cost(0);
2948 format %{ %}
2949 interface(CONST_INTER);
2950 %}
2951
2952 // Constant for decrement
2953 operand immI_M1()
2954 %{
2955 predicate(n->get_int() == -1);
2956 match(ConI);
2957
2958 op_cost(0);
2959 format %{ %}
2960 interface(CONST_INTER);
2961 %}
2962
2963 // Valid scale values for addressing modes
2964 operand immI2()
2965 %{
2966 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2967 match(ConI);
2968
2969 format %{ %}
2970 interface(CONST_INTER);
2971 %}
2972
2973 operand immI8()
2974 %{
2975 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2976 match(ConI);
2977
2978 op_cost(5);
2979 format %{ %}
2980 interface(CONST_INTER);
2981 %}
2982
2983 operand immU8()
2984 %{
2985 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2986 match(ConI);
2987
2988 op_cost(5);
2989 format %{ %}
2990 interface(CONST_INTER);
2991 %}
2992
2993 operand immI16()
2994 %{
2995 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2996 match(ConI);
2997
2998 op_cost(10);
2999 format %{ %}
3000 interface(CONST_INTER);
3001 %}
3002
3003 // Int Immediate non-negative
3004 operand immU31()
3005 %{
3006 predicate(n->get_int() >= 0);
3007 match(ConI);
3008
3009 op_cost(0);
3010 format %{ %}
3011 interface(CONST_INTER);
3012 %}
3013
3014 // Constant for long shifts
3015 operand immI_32()
3016 %{
3017 predicate( n->get_int() == 32 );
3018 match(ConI);
3019
3020 op_cost(0);
3021 format %{ %}
3022 interface(CONST_INTER);
3023 %}
3024
3025 // Constant for long shifts
3026 operand immI_64()
3027 %{
3028 predicate( n->get_int() == 64 );
3029 match(ConI);
3030
3031 op_cost(0);
3032 format %{ %}
3033 interface(CONST_INTER);
3034 %}
3035
3036 // Pointer Immediate
3037 operand immP()
3038 %{
3039 match(ConP);
3040
3041 op_cost(10);
3042 format %{ %}
3043 interface(CONST_INTER);
3044 %}
3045
3046 // NULL Pointer Immediate
3047 operand immP0()
3048 %{
3049 predicate(n->get_ptr() == 0);
3050 match(ConP);
3051
3052 op_cost(5);
3053 format %{ %}
3054 interface(CONST_INTER);
3055 %}
3056
3057 // Pointer Immediate
3058 operand immN() %{
3059 match(ConN);
3060
3061 op_cost(10);
3062 format %{ %}
3063 interface(CONST_INTER);
3064 %}
3065
3066 operand immNKlass() %{
3067 match(ConNKlass);
3068
3069 op_cost(10);
3070 format %{ %}
3071 interface(CONST_INTER);
3072 %}
3073
3074 // NULL Pointer Immediate
3075 operand immN0() %{
3076 predicate(n->get_narrowcon() == 0);
3077 match(ConN);
3078
3079 op_cost(5);
3080 format %{ %}
3081 interface(CONST_INTER);
3082 %}
3083
3084 operand immP31()
3085 %{
3086 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3087 && (n->get_ptr() >> 31) == 0);
3088 match(ConP);
3089
3090 op_cost(5);
3091 format %{ %}
3092 interface(CONST_INTER);
3093 %}
3094
3095
3096 // Long Immediate
3097 operand immL()
3098 %{
3099 match(ConL);
3100
3101 op_cost(20);
3102 format %{ %}
3103 interface(CONST_INTER);
3104 %}
3105
3106 // Long Immediate 8-bit
3107 operand immL8()
3108 %{
3109 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3110 match(ConL);
3111
3112 op_cost(5);
3113 format %{ %}
3114 interface(CONST_INTER);
3115 %}
3116
3117 // Long Immediate 32-bit unsigned
3118 operand immUL32()
3119 %{
3120 predicate(n->get_long() == (unsigned int) (n->get_long()));
3121 match(ConL);
3122
3123 op_cost(10);
3124 format %{ %}
3125 interface(CONST_INTER);
3126 %}
3127
3128 // Long Immediate 32-bit signed
3129 operand immL32()
3130 %{
3131 predicate(n->get_long() == (int) (n->get_long()));
3132 match(ConL);
3133
3134 op_cost(15);
3135 format %{ %}
3136 interface(CONST_INTER);
3137 %}
3138
3139 // Long Immediate zero
3140 operand immL0()
3141 %{
3142 predicate(n->get_long() == 0L);
3143 match(ConL);
3144
3145 op_cost(10);
3146 format %{ %}
3147 interface(CONST_INTER);
3148 %}
3149
3150 // Constant for increment
3151 operand immL1()
3152 %{
3153 predicate(n->get_long() == 1);
3154 match(ConL);
3155
3156 format %{ %}
3157 interface(CONST_INTER);
3158 %}
3159
3160 // Constant for decrement
3161 operand immL_M1()
3162 %{
3163 predicate(n->get_long() == -1);
3164 match(ConL);
3165
3166 format %{ %}
3167 interface(CONST_INTER);
3168 %}
3169
3170 // Long Immediate: the value 10
3171 operand immL10()
3172 %{
3173 predicate(n->get_long() == 10);
3174 match(ConL);
3175
3176 format %{ %}
3177 interface(CONST_INTER);
3178 %}
3179
3180 // Long immediate from 0 to 127.
3181 // Used for a shorter form of long mul by 10.
3182 operand immL_127()
3183 %{
3184 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3185 match(ConL);
3186
3187 op_cost(10);
3188 format %{ %}
3189 interface(CONST_INTER);
3190 %}
3191
3192 // Long Immediate: low 32-bit mask
3193 operand immL_32bits()
3194 %{
3195 predicate(n->get_long() == 0xFFFFFFFFL);
3196 match(ConL);
3197 op_cost(20);
3198
3199 format %{ %}
3200 interface(CONST_INTER);
3201 %}
3202
3203 // Float Immediate zero
3204 operand immF0()
3205 %{
3206 predicate(jint_cast(n->getf()) == 0);
3207 match(ConF);
3208
3209 op_cost(5);
3210 format %{ %}
3211 interface(CONST_INTER);
3212 %}
3213
3214 // Float Immediate
3215 operand immF()
3216 %{
3217 match(ConF);
3218
3219 op_cost(15);
3220 format %{ %}
3221 interface(CONST_INTER);
3222 %}
3223
3224 // Double Immediate zero
3225 operand immD0()
3226 %{
3227 predicate(jlong_cast(n->getd()) == 0);
3228 match(ConD);
3229
3230 op_cost(5);
3231 format %{ %}
3232 interface(CONST_INTER);
3233 %}
3234
3235 // Double Immediate
3236 operand immD()
3237 %{
3238 match(ConD);
3239
3240 op_cost(15);
3241 format %{ %}
3242 interface(CONST_INTER);
3243 %}
3244
3245 // Immediates for special shifts (sign extend)
3246
3247 // Constants for increment
3248 operand immI_16()
3249 %{
3250 predicate(n->get_int() == 16);
3251 match(ConI);
3252
3253 format %{ %}
3254 interface(CONST_INTER);
3255 %}
3256
3257 operand immI_24()
3258 %{
3259 predicate(n->get_int() == 24);
3260 match(ConI);
3261
3262 format %{ %}
3263 interface(CONST_INTER);
3264 %}
3265
3266 // Constant for byte-wide masking
3267 operand immI_255()
3268 %{
3269 predicate(n->get_int() == 255);
3270 match(ConI);
3271
3272 format %{ %}
3273 interface(CONST_INTER);
3274 %}
3275
3276 // Constant for short-wide masking
3277 operand immI_65535()
3278 %{
3279 predicate(n->get_int() == 65535);
3280 match(ConI);
3281
3282 format %{ %}
3283 interface(CONST_INTER);
3284 %}
3285
3286 // Constant for byte-wide masking
3287 operand immL_255()
3288 %{
3289 predicate(n->get_long() == 255);
3290 match(ConL);
3291
3292 format %{ %}
3293 interface(CONST_INTER);
3294 %}
3295
3296 // Constant for short-wide masking
3297 operand immL_65535()
3298 %{
3299 predicate(n->get_long() == 65535);
3300 match(ConL);
3301
3302 format %{ %}
3303 interface(CONST_INTER);
3304 %}
3305
3306 // Register Operands
3307 // Integer Register
3308 operand rRegI()
3309 %{
3310 constraint(ALLOC_IN_RC(int_reg));
3311 match(RegI);
3312
3313 match(rax_RegI);
3314 match(rbx_RegI);
3315 match(rcx_RegI);
3316 match(rdx_RegI);
3317 match(rdi_RegI);
3318
3319 format %{ %}
3320 interface(REG_INTER);
3321 %}
3322
3323 // Special Registers
3324 operand rax_RegI()
3325 %{
3326 constraint(ALLOC_IN_RC(int_rax_reg));
3327 match(RegI);
3328 match(rRegI);
3329
3330 format %{ "RAX" %}
3331 interface(REG_INTER);
3332 %}
3333
3334 // Special Registers
3335 operand rbx_RegI()
3336 %{
3337 constraint(ALLOC_IN_RC(int_rbx_reg));
3338 match(RegI);
3339 match(rRegI);
3340
3341 format %{ "RBX" %}
3342 interface(REG_INTER);
3343 %}
3344
3345 operand rcx_RegI()
3346 %{
3347 constraint(ALLOC_IN_RC(int_rcx_reg));
3348 match(RegI);
3349 match(rRegI);
3350
3351 format %{ "RCX" %}
3352 interface(REG_INTER);
3353 %}
3354
3355 operand rdx_RegI()
3356 %{
3357 constraint(ALLOC_IN_RC(int_rdx_reg));
3358 match(RegI);
3359 match(rRegI);
3360
3361 format %{ "RDX" %}
3362 interface(REG_INTER);
3363 %}
3364
3365 operand rdi_RegI()
3366 %{
3367 constraint(ALLOC_IN_RC(int_rdi_reg));
3368 match(RegI);
3369 match(rRegI);
3370
3371 format %{ "RDI" %}
3372 interface(REG_INTER);
3373 %}
3374
3375 operand no_rcx_RegI()
3376 %{
3377 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3378 match(RegI);
3379 match(rax_RegI);
3380 match(rbx_RegI);
3381 match(rdx_RegI);
3382 match(rdi_RegI);
3383
3384 format %{ %}
3385 interface(REG_INTER);
3386 %}
3387
3388 operand no_rax_rdx_RegI()
3389 %{
3390 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3391 match(RegI);
3392 match(rbx_RegI);
3393 match(rcx_RegI);
3394 match(rdi_RegI);
3395
3396 format %{ %}
3397 interface(REG_INTER);
3398 %}
3399
3400 // Pointer Register
3401 operand any_RegP()
3402 %{
3403 constraint(ALLOC_IN_RC(any_reg));
3404 match(RegP);
3405 match(rax_RegP);
3406 match(rbx_RegP);
3407 match(rdi_RegP);
3408 match(rsi_RegP);
3409 match(rbp_RegP);
3410 match(r15_RegP);
3411 match(rRegP);
3412
3413 format %{ %}
3414 interface(REG_INTER);
3415 %}
3416
3417 operand rRegP()
3418 %{
3419 constraint(ALLOC_IN_RC(ptr_reg));
3420 match(RegP);
3421 match(rax_RegP);
3422 match(rbx_RegP);
3423 match(rdi_RegP);
3424 match(rsi_RegP);
3425 match(rbp_RegP); // See Q&A below about
3426 match(r15_RegP); // r15_RegP and rbp_RegP.
3427
3428 format %{ %}
3429 interface(REG_INTER);
3430 %}
3431
3432 operand rRegN() %{
3433 constraint(ALLOC_IN_RC(int_reg));
3434 match(RegN);
3435
3436 format %{ %}
3437 interface(REG_INTER);
3438 %}
3439
3440 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3441 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3442 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3443 // The output of an instruction is controlled by the allocator, which respects
3444 // register class masks, not match rules. Unless an instruction mentions
3445 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3446 // by the allocator as an input.
3447 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3448 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3449 // result, RBP is not included in the output of the instruction either.
3450
3451 operand no_rax_RegP()
3452 %{
3453 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3454 match(RegP);
3455 match(rbx_RegP);
3456 match(rsi_RegP);
3457 match(rdi_RegP);
3458
3459 format %{ %}
3460 interface(REG_INTER);
3461 %}
3462
3463 // This operand is not allowed to use RBP even if
3464 // RBP is not used to hold the frame pointer.
3465 operand no_rbp_RegP()
3466 %{
3467 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3468 match(RegP);
3469 match(rbx_RegP);
3470 match(rsi_RegP);
3471 match(rdi_RegP);
3472
3473 format %{ %}
3474 interface(REG_INTER);
3475 %}
3476
3477 operand no_rax_rbx_RegP()
3478 %{
3479 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3480 match(RegP);
3481 match(rsi_RegP);
3482 match(rdi_RegP);
3483
3484 format %{ %}
3485 interface(REG_INTER);
3486 %}
3487
3488 // Special Registers
3489 // Return a pointer value
3490 operand rax_RegP()
3491 %{
3492 constraint(ALLOC_IN_RC(ptr_rax_reg));
3493 match(RegP);
3494 match(rRegP);
3495
3496 format %{ %}
3497 interface(REG_INTER);
3498 %}
3499
3500 // Special Registers
3501 // Return a compressed pointer value
3502 operand rax_RegN()
3503 %{
3504 constraint(ALLOC_IN_RC(int_rax_reg));
3505 match(RegN);
3506 match(rRegN);
3507
3508 format %{ %}
3509 interface(REG_INTER);
3510 %}
3511
3512 // Used in AtomicAdd
3513 operand rbx_RegP()
3514 %{
3515 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3516 match(RegP);
3517 match(rRegP);
3518
3519 format %{ %}
3520 interface(REG_INTER);
3521 %}
3522
3523 operand rsi_RegP()
3524 %{
3525 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3526 match(RegP);
3527 match(rRegP);
3528
3529 format %{ %}
3530 interface(REG_INTER);
3531 %}
3532
3533 // Used in rep stosq
3534 operand rdi_RegP()
3535 %{
3536 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3537 match(RegP);
3538 match(rRegP);
3539
3540 format %{ %}
3541 interface(REG_INTER);
3542 %}
3543
3544 operand r15_RegP()
3545 %{
3546 constraint(ALLOC_IN_RC(ptr_r15_reg));
3547 match(RegP);
3548 match(rRegP);
3549
3550 format %{ %}
3551 interface(REG_INTER);
3552 %}
3553
3554 operand rex_RegP()
3555 %{
3556 constraint(ALLOC_IN_RC(ptr_rex_reg));
3557 match(RegP);
3558 match(rRegP);
3559
3560 format %{ %}
3561 interface(REG_INTER);
3562 %}
3563
3564 operand rRegL()
3565 %{
3566 constraint(ALLOC_IN_RC(long_reg));
3567 match(RegL);
3568 match(rax_RegL);
3569 match(rdx_RegL);
3570
3571 format %{ %}
3572 interface(REG_INTER);
3573 %}
3574
3575 // Special Registers
3576 operand no_rax_rdx_RegL()
3577 %{
3578 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3579 match(RegL);
3580 match(rRegL);
3581
3582 format %{ %}
3583 interface(REG_INTER);
3584 %}
3585
3586 operand no_rax_RegL()
3587 %{
3588 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3589 match(RegL);
3590 match(rRegL);
3591 match(rdx_RegL);
3592
3593 format %{ %}
3594 interface(REG_INTER);
3595 %}
3596
3597 operand no_rcx_RegL()
3598 %{
3599 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3600 match(RegL);
3601 match(rRegL);
3602
3603 format %{ %}
3604 interface(REG_INTER);
3605 %}
3606
3607 operand rax_RegL()
3608 %{
3609 constraint(ALLOC_IN_RC(long_rax_reg));
3610 match(RegL);
3611 match(rRegL);
3612
3613 format %{ "RAX" %}
3614 interface(REG_INTER);
3615 %}
3616
3617 operand rcx_RegL()
3618 %{
3619 constraint(ALLOC_IN_RC(long_rcx_reg));
3620 match(RegL);
3621 match(rRegL);
3622
3623 format %{ %}
3624 interface(REG_INTER);
3625 %}
3626
3627 operand rdx_RegL()
3628 %{
3629 constraint(ALLOC_IN_RC(long_rdx_reg));
3630 match(RegL);
3631 match(rRegL);
3632
3633 format %{ %}
3634 interface(REG_INTER);
3635 %}
3636
3637 // Flags register, used as output of compare instructions
3638 operand rFlagsReg()
3639 %{
3640 constraint(ALLOC_IN_RC(int_flags));
3641 match(RegFlags);
3642
3643 format %{ "RFLAGS" %}
3644 interface(REG_INTER);
3645 %}
3646
3647 // Flags register, used as output of FLOATING POINT compare instructions
3648 operand rFlagsRegU()
3649 %{
3650 constraint(ALLOC_IN_RC(int_flags));
3651 match(RegFlags);
3652
3653 format %{ "RFLAGS_U" %}
3654 interface(REG_INTER);
3655 %}
3656
3657 operand rFlagsRegUCF() %{
3658 constraint(ALLOC_IN_RC(int_flags));
3659 match(RegFlags);
3660 predicate(false);
3661
3662 format %{ "RFLAGS_U_CF" %}
3663 interface(REG_INTER);
3664 %}
3665
3666 // Float register operands
3667 operand regF() %{
3668 constraint(ALLOC_IN_RC(float_reg));
3669 match(RegF);
3670
3671 format %{ %}
3672 interface(REG_INTER);
3673 %}
3674
3675 // Double register operands
3676 operand regD() %{
3677 constraint(ALLOC_IN_RC(double_reg));
3678 match(RegD);
3679
3680 format %{ %}
3681 interface(REG_INTER);
3682 %}
3683
3684 // Vectors
3685 operand vecS() %{
3686 constraint(ALLOC_IN_RC(vectors_reg));
3687 match(VecS);
3688
3689 format %{ %}
3690 interface(REG_INTER);
3691 %}
3692
3693 operand vecD() %{
3694 constraint(ALLOC_IN_RC(vectord_reg));
3695 match(VecD);
3696
3697 format %{ %}
3698 interface(REG_INTER);
3699 %}
3700
3701 operand vecX() %{
3702 constraint(ALLOC_IN_RC(vectorx_reg));
3703 match(VecX);
3704
3705 format %{ %}
3706 interface(REG_INTER);
3707 %}
3708
3709 operand vecY() %{
3710 constraint(ALLOC_IN_RC(vectory_reg));
3711 match(VecY);
3712
3713 format %{ %}
3714 interface(REG_INTER);
3715 %}
3716
3717 //----------Memory Operands----------------------------------------------------
3718 // Direct Memory Operand
3719 // operand direct(immP addr)
3720 // %{
3721 // match(addr);
3722
3723 // format %{ "[$addr]" %}
3724 // interface(MEMORY_INTER) %{
3725 // base(0xFFFFFFFF);
3726 // index(0x4);
3727 // scale(0x0);
3728 // disp($addr);
3729 // %}
3730 // %}
3731
3732 // Indirect Memory Operand
3733 operand indirect(any_RegP reg)
3734 %{
3735 constraint(ALLOC_IN_RC(ptr_reg));
3736 match(reg);
3737
3738 format %{ "[$reg]" %}
3739 interface(MEMORY_INTER) %{
3740 base($reg);
3741 index(0x4);
3742 scale(0x0);
3743 disp(0x0);
3744 %}
3745 %}
3746
3747 // Indirect Memory Plus Short Offset Operand
3748 operand indOffset8(any_RegP reg, immL8 off)
3749 %{
3750 constraint(ALLOC_IN_RC(ptr_reg));
3751 match(AddP reg off);
3752
3753 format %{ "[$reg + $off (8-bit)]" %}
3754 interface(MEMORY_INTER) %{
3755 base($reg);
3756 index(0x4);
3757 scale(0x0);
3758 disp($off);
3759 %}
3760 %}
3761
3762 // Indirect Memory Plus Long Offset Operand
3763 operand indOffset32(any_RegP reg, immL32 off)
3764 %{
3765 constraint(ALLOC_IN_RC(ptr_reg));
3766 match(AddP reg off);
3767
3768 format %{ "[$reg + $off (32-bit)]" %}
3769 interface(MEMORY_INTER) %{
3770 base($reg);
3771 index(0x4);
3772 scale(0x0);
3773 disp($off);
3774 %}
3775 %}
3776
3777 // Indirect Memory Plus Index Register Plus Offset Operand
3778 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3779 %{
3780 constraint(ALLOC_IN_RC(ptr_reg));
3781 match(AddP (AddP reg lreg) off);
3782
3783 op_cost(10);
3784 format %{"[$reg + $off + $lreg]" %}
3785 interface(MEMORY_INTER) %{
3786 base($reg);
3787 index($lreg);
3788 scale(0x0);
3789 disp($off);
3790 %}
3791 %}
3792
3793 // Indirect Memory Plus Index Register Plus Offset Operand
3794 operand indIndex(any_RegP reg, rRegL lreg)
3795 %{
3796 constraint(ALLOC_IN_RC(ptr_reg));
3797 match(AddP reg lreg);
3798
3799 op_cost(10);
3800 format %{"[$reg + $lreg]" %}
3801 interface(MEMORY_INTER) %{
3802 base($reg);
3803 index($lreg);
3804 scale(0x0);
3805 disp(0x0);
3806 %}
3807 %}
3808
3809 // Indirect Memory Times Scale Plus Index Register
3810 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3811 %{
3812 constraint(ALLOC_IN_RC(ptr_reg));
3813 match(AddP reg (LShiftL lreg scale));
3814
3815 op_cost(10);
3816 format %{"[$reg + $lreg << $scale]" %}
3817 interface(MEMORY_INTER) %{
3818 base($reg);
3819 index($lreg);
3820 scale($scale);
3821 disp(0x0);
3822 %}
3823 %}
3824
3825 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3826 %{
3827 constraint(ALLOC_IN_RC(ptr_reg));
3828 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3829 match(AddP reg (LShiftL (ConvI2L idx) scale));
3830
3831 op_cost(10);
3832 format %{"[$reg + pos $idx << $scale]" %}
3833 interface(MEMORY_INTER) %{
3834 base($reg);
3835 index($idx);
3836 scale($scale);
3837 disp(0x0);
3838 %}
3839 %}
3840
3841 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3842 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3843 %{
3844 constraint(ALLOC_IN_RC(ptr_reg));
3845 match(AddP (AddP reg (LShiftL lreg scale)) off);
3846
3847 op_cost(10);
3848 format %{"[$reg + $off + $lreg << $scale]" %}
3849 interface(MEMORY_INTER) %{
3850 base($reg);
3851 index($lreg);
3852 scale($scale);
3853 disp($off);
3854 %}
3855 %}
3856
3857 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3858 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3859 %{
3860 constraint(ALLOC_IN_RC(ptr_reg));
3861 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3862 match(AddP (AddP reg (ConvI2L idx)) off);
3863
3864 op_cost(10);
3865 format %{"[$reg + $off + $idx]" %}
3866 interface(MEMORY_INTER) %{
3867 base($reg);
3868 index($idx);
3869 scale(0x0);
3870 disp($off);
3871 %}
3872 %}
3873
3874 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3875 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3876 %{
3877 constraint(ALLOC_IN_RC(ptr_reg));
3878 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3879 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3880
3881 op_cost(10);
3882 format %{"[$reg + $off + $idx << $scale]" %}
3883 interface(MEMORY_INTER) %{
3884 base($reg);
3885 index($idx);
3886 scale($scale);
3887 disp($off);
3888 %}
3889 %}
3890
3891 // Indirect Narrow Oop Plus Offset Operand
3892 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3893 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3894 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3895 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3896 constraint(ALLOC_IN_RC(ptr_reg));
3897 match(AddP (DecodeN reg) off);
3898
3899 op_cost(10);
3900 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3901 interface(MEMORY_INTER) %{
3902 base(0xc); // R12
3903 index($reg);
3904 scale(0x3);
3905 disp($off);
3906 %}
3907 %}
3908
3909 // Indirect Memory Operand
3910 operand indirectNarrow(rRegN reg)
3911 %{
3912 predicate(Universe::narrow_oop_shift() == 0);
3913 constraint(ALLOC_IN_RC(ptr_reg));
3914 match(DecodeN reg);
3915
3916 format %{ "[$reg]" %}
3917 interface(MEMORY_INTER) %{
3918 base($reg);
3919 index(0x4);
3920 scale(0x0);
3921 disp(0x0);
3922 %}
3923 %}
3924
3925 // Indirect Memory Plus Short Offset Operand
3926 operand indOffset8Narrow(rRegN reg, immL8 off)
3927 %{
3928 predicate(Universe::narrow_oop_shift() == 0);
3929 constraint(ALLOC_IN_RC(ptr_reg));
3930 match(AddP (DecodeN reg) off);
3931
3932 format %{ "[$reg + $off (8-bit)]" %}
3933 interface(MEMORY_INTER) %{
3934 base($reg);
3935 index(0x4);
3936 scale(0x0);
3937 disp($off);
3938 %}
3939 %}
3940
3941 // Indirect Memory Plus Long Offset Operand
3942 operand indOffset32Narrow(rRegN reg, immL32 off)
3943 %{
3944 predicate(Universe::narrow_oop_shift() == 0);
3945 constraint(ALLOC_IN_RC(ptr_reg));
3946 match(AddP (DecodeN reg) off);
3947
3948 format %{ "[$reg + $off (32-bit)]" %}
3949 interface(MEMORY_INTER) %{
3950 base($reg);
3951 index(0x4);
3952 scale(0x0);
3953 disp($off);
3954 %}
3955 %}
3956
3957 // Indirect Memory Plus Index Register Plus Offset Operand
3958 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3959 %{
3960 predicate(Universe::narrow_oop_shift() == 0);
3961 constraint(ALLOC_IN_RC(ptr_reg));
3962 match(AddP (AddP (DecodeN reg) lreg) off);
3963
3964 op_cost(10);
3965 format %{"[$reg + $off + $lreg]" %}
3966 interface(MEMORY_INTER) %{
3967 base($reg);
3968 index($lreg);
3969 scale(0x0);
3970 disp($off);
3971 %}
3972 %}
3973
3974 // Indirect Memory Plus Index Register Plus Offset Operand
3975 operand indIndexNarrow(rRegN reg, rRegL lreg)
3976 %{
3977 predicate(Universe::narrow_oop_shift() == 0);
3978 constraint(ALLOC_IN_RC(ptr_reg));
3979 match(AddP (DecodeN reg) lreg);
3980
3981 op_cost(10);
3982 format %{"[$reg + $lreg]" %}
3983 interface(MEMORY_INTER) %{
3984 base($reg);
3985 index($lreg);
3986 scale(0x0);
3987 disp(0x0);
3988 %}
3989 %}
3990
3991 // Indirect Memory Times Scale Plus Index Register
3992 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3993 %{
3994 predicate(Universe::narrow_oop_shift() == 0);
3995 constraint(ALLOC_IN_RC(ptr_reg));
3996 match(AddP (DecodeN reg) (LShiftL lreg scale));
3997
3998 op_cost(10);
3999 format %{"[$reg + $lreg << $scale]" %}
4000 interface(MEMORY_INTER) %{
4001 base($reg);
4002 index($lreg);
4003 scale($scale);
4004 disp(0x0);
4005 %}
4006 %}
4007
4008 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4009 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4010 %{
4011 predicate(Universe::narrow_oop_shift() == 0);
4012 constraint(ALLOC_IN_RC(ptr_reg));
4013 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4014
4015 op_cost(10);
4016 format %{"[$reg + $off + $lreg << $scale]" %}
4017 interface(MEMORY_INTER) %{
4018 base($reg);
4019 index($lreg);
4020 scale($scale);
4021 disp($off);
4022 %}
4023 %}
4024
4025 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4026 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4027 %{
4028 constraint(ALLOC_IN_RC(ptr_reg));
4029 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4030 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4031
4032 op_cost(10);
4033 format %{"[$reg + $off + $idx]" %}
4034 interface(MEMORY_INTER) %{
4035 base($reg);
4036 index($idx);
4037 scale(0x0);
4038 disp($off);
4039 %}
4040 %}
4041
4042 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4043 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4044 %{
4045 constraint(ALLOC_IN_RC(ptr_reg));
4046 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4047 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4048
4049 op_cost(10);
4050 format %{"[$reg + $off + $idx << $scale]" %}
4051 interface(MEMORY_INTER) %{
4052 base($reg);
4053 index($idx);
4054 scale($scale);
4055 disp($off);
4056 %}
4057 %}
4058
4059 //----------Special Memory Operands--------------------------------------------
4060 // Stack Slot Operand - This operand is used for loading and storing temporary
4061 // values on the stack where a match requires a value to
4062 // flow through memory.
4063 operand stackSlotP(sRegP reg)
4064 %{
4065 constraint(ALLOC_IN_RC(stack_slots));
4066 // No match rule because this operand is only generated in matching
4067
4068 format %{ "[$reg]" %}
4069 interface(MEMORY_INTER) %{
4070 base(0x4); // RSP
4071 index(0x4); // No Index
4072 scale(0x0); // No Scale
4073 disp($reg); // Stack Offset
4074 %}
4075 %}
4076
4077 operand stackSlotI(sRegI reg)
4078 %{
4079 constraint(ALLOC_IN_RC(stack_slots));
4080 // No match rule because this operand is only generated in matching
4081
4082 format %{ "[$reg]" %}
4083 interface(MEMORY_INTER) %{
4084 base(0x4); // RSP
4085 index(0x4); // No Index
4086 scale(0x0); // No Scale
4087 disp($reg); // Stack Offset
4088 %}
4089 %}
4090
4091 operand stackSlotF(sRegF reg)
4092 %{
4093 constraint(ALLOC_IN_RC(stack_slots));
4094 // No match rule because this operand is only generated in matching
4095
4096 format %{ "[$reg]" %}
4097 interface(MEMORY_INTER) %{
4098 base(0x4); // RSP
4099 index(0x4); // No Index
4100 scale(0x0); // No Scale
4101 disp($reg); // Stack Offset
4102 %}
4103 %}
4104
4105 operand stackSlotD(sRegD reg)
4106 %{
4107 constraint(ALLOC_IN_RC(stack_slots));
4108 // No match rule because this operand is only generated in matching
4109
4110 format %{ "[$reg]" %}
4111 interface(MEMORY_INTER) %{
4112 base(0x4); // RSP
4113 index(0x4); // No Index
4114 scale(0x0); // No Scale
4115 disp($reg); // Stack Offset
4116 %}
4117 %}
4118 operand stackSlotL(sRegL reg)
4119 %{
4120 constraint(ALLOC_IN_RC(stack_slots));
4121 // No match rule because this operand is only generated in matching
4122
4123 format %{ "[$reg]" %}
4124 interface(MEMORY_INTER) %{
4125 base(0x4); // RSP
4126 index(0x4); // No Index
4127 scale(0x0); // No Scale
4128 disp($reg); // Stack Offset
4129 %}
4130 %}
4131
4132 //----------Conditional Branch Operands----------------------------------------
4133 // Comparison Op - This is the operation of the comparison, and is limited to
4134 // the following set of codes:
4135 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4136 //
4137 // Other attributes of the comparison, such as unsignedness, are specified
4138 // by the comparison instruction that sets a condition code flags register.
4139 // That result is represented by a flags operand whose subtype is appropriate
4140 // to the unsignedness (etc.) of the comparison.
4141 //
4142 // Later, the instruction which matches both the Comparison Op (a Bool) and
4143 // the flags (produced by the Cmp) specifies the coding of the comparison op
4144 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4145
4146 // Comparision Code
4147 operand cmpOp()
4148 %{
4149 match(Bool);
4150
4151 format %{ "" %}
4152 interface(COND_INTER) %{
4153 equal(0x4, "e");
4154 not_equal(0x5, "ne");
4155 less(0xC, "l");
4156 greater_equal(0xD, "ge");
4157 less_equal(0xE, "le");
4158 greater(0xF, "g");
4159 overflow(0x0, "o");
4160 no_overflow(0x1, "no");
4161 %}
4162 %}
4163
4164 // Comparison Code, unsigned compare. Used by FP also, with
4165 // C2 (unordered) turned into GT or LT already. The other bits
4166 // C0 and C3 are turned into Carry & Zero flags.
4167 operand cmpOpU()
4168 %{
4169 match(Bool);
4170
4171 format %{ "" %}
4172 interface(COND_INTER) %{
4173 equal(0x4, "e");
4174 not_equal(0x5, "ne");
4175 less(0x2, "b");
4176 greater_equal(0x3, "nb");
4177 less_equal(0x6, "be");
4178 greater(0x7, "nbe");
4179 overflow(0x0, "o");
4180 no_overflow(0x1, "no");
4181 %}
4182 %}
4183
4184
4185 // Floating comparisons that don't require any fixup for the unordered case
4186 operand cmpOpUCF() %{
4187 match(Bool);
4188 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4189 n->as_Bool()->_test._test == BoolTest::ge ||
4190 n->as_Bool()->_test._test == BoolTest::le ||
4191 n->as_Bool()->_test._test == BoolTest::gt);
4192 format %{ "" %}
4193 interface(COND_INTER) %{
4194 equal(0x4, "e");
4195 not_equal(0x5, "ne");
4196 less(0x2, "b");
4197 greater_equal(0x3, "nb");
4198 less_equal(0x6, "be");
4199 greater(0x7, "nbe");
4200 overflow(0x0, "o");
4201 no_overflow(0x1, "no");
4202 %}
4203 %}
4204
4205
4206 // Floating comparisons that can be fixed up with extra conditional jumps
4207 operand cmpOpUCF2() %{
4208 match(Bool);
4209 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4210 n->as_Bool()->_test._test == BoolTest::eq);
4211 format %{ "" %}
4212 interface(COND_INTER) %{
4213 equal(0x4, "e");
4214 not_equal(0x5, "ne");
4215 less(0x2, "b");
4216 greater_equal(0x3, "nb");
4217 less_equal(0x6, "be");
4218 greater(0x7, "nbe");
4219 overflow(0x0, "o");
4220 no_overflow(0x1, "no");
4221 %}
4222 %}
4223
4224
4225 //----------OPERAND CLASSES----------------------------------------------------
4226 // Operand Classes are groups of operands that are used as to simplify
4227 // instruction definitions by not requiring the AD writer to specify separate
4228 // instructions for every form of operand when the instruction accepts
4229 // multiple operand types with the same basic encoding and format. The classic
4230 // case of this is memory operands.
4231
4232 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4233 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4234 indCompressedOopOffset,
4235 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4236 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4237 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4238
4239 //----------PIPELINE-----------------------------------------------------------
4240 // Rules which define the behavior of the target architectures pipeline.
4241 pipeline %{
4242
4243 //----------ATTRIBUTES---------------------------------------------------------
4244 attributes %{
4245 variable_size_instructions; // Fixed size instructions
4246 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4247 instruction_unit_size = 1; // An instruction is 1 bytes long
4248 instruction_fetch_unit_size = 16; // The processor fetches one line
4249 instruction_fetch_units = 1; // of 16 bytes
4250
4251 // List of nop instructions
4252 nops( MachNop );
4253 %}
4254
4255 //----------RESOURCES----------------------------------------------------------
4256 // Resources are the functional units available to the machine
4257
4258 // Generic P2/P3 pipeline
4259 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4260 // 3 instructions decoded per cycle.
4261 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4262 // 3 ALU op, only ALU0 handles mul instructions.
4263 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4264 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4265 BR, FPU,
4266 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4267
4268 //----------PIPELINE DESCRIPTION-----------------------------------------------
4269 // Pipeline Description specifies the stages in the machine's pipeline
4270
4271 // Generic P2/P3 pipeline
4272 pipe_desc(S0, S1, S2, S3, S4, S5);
4273
4274 //----------PIPELINE CLASSES---------------------------------------------------
4275 // Pipeline Classes describe the stages in which input and output are
4276 // referenced by the hardware pipeline.
4277
4278 // Naming convention: ialu or fpu
4279 // Then: _reg
4280 // Then: _reg if there is a 2nd register
4281 // Then: _long if it's a pair of instructions implementing a long
4282 // Then: _fat if it requires the big decoder
4283 // Or: _mem if it requires the big decoder and a memory unit.
4284
4285 // Integer ALU reg operation
4286 pipe_class ialu_reg(rRegI dst)
4287 %{
4288 single_instruction;
4289 dst : S4(write);
4290 dst : S3(read);
4291 DECODE : S0; // any decoder
4292 ALU : S3; // any alu
4293 %}
4294
4295 // Long ALU reg operation
4296 pipe_class ialu_reg_long(rRegL dst)
4297 %{
4298 instruction_count(2);
4299 dst : S4(write);
4300 dst : S3(read);
4301 DECODE : S0(2); // any 2 decoders
4302 ALU : S3(2); // both alus
4303 %}
4304
4305 // Integer ALU reg operation using big decoder
4306 pipe_class ialu_reg_fat(rRegI dst)
4307 %{
4308 single_instruction;
4309 dst : S4(write);
4310 dst : S3(read);
4311 D0 : S0; // big decoder only
4312 ALU : S3; // any alu
4313 %}
4314
4315 // Long ALU reg operation using big decoder
4316 pipe_class ialu_reg_long_fat(rRegL dst)
4317 %{
4318 instruction_count(2);
4319 dst : S4(write);
4320 dst : S3(read);
4321 D0 : S0(2); // big decoder only; twice
4322 ALU : S3(2); // any 2 alus
4323 %}
4324
4325 // Integer ALU reg-reg operation
4326 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4327 %{
4328 single_instruction;
4329 dst : S4(write);
4330 src : S3(read);
4331 DECODE : S0; // any decoder
4332 ALU : S3; // any alu
4333 %}
4334
4335 // Long ALU reg-reg operation
4336 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4337 %{
4338 instruction_count(2);
4339 dst : S4(write);
4340 src : S3(read);
4341 DECODE : S0(2); // any 2 decoders
4342 ALU : S3(2); // both alus
4343 %}
4344
4345 // Integer ALU reg-reg operation
4346 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4347 %{
4348 single_instruction;
4349 dst : S4(write);
4350 src : S3(read);
4351 D0 : S0; // big decoder only
4352 ALU : S3; // any alu
4353 %}
4354
4355 // Long ALU reg-reg operation
4356 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4357 %{
4358 instruction_count(2);
4359 dst : S4(write);
4360 src : S3(read);
4361 D0 : S0(2); // big decoder only; twice
4362 ALU : S3(2); // both alus
4363 %}
4364
4365 // Integer ALU reg-mem operation
4366 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4367 %{
4368 single_instruction;
4369 dst : S5(write);
4370 mem : S3(read);
4371 D0 : S0; // big decoder only
4372 ALU : S4; // any alu
4373 MEM : S3; // any mem
4374 %}
4375
4376 // Integer mem operation (prefetch)
4377 pipe_class ialu_mem(memory mem)
4378 %{
4379 single_instruction;
4380 mem : S3(read);
4381 D0 : S0; // big decoder only
4382 MEM : S3; // any mem
4383 %}
4384
4385 // Integer Store to Memory
4386 pipe_class ialu_mem_reg(memory mem, rRegI src)
4387 %{
4388 single_instruction;
4389 mem : S3(read);
4390 src : S5(read);
4391 D0 : S0; // big decoder only
4392 ALU : S4; // any alu
4393 MEM : S3;
4394 %}
4395
4396 // // Long Store to Memory
4397 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4398 // %{
4399 // instruction_count(2);
4400 // mem : S3(read);
4401 // src : S5(read);
4402 // D0 : S0(2); // big decoder only; twice
4403 // ALU : S4(2); // any 2 alus
4404 // MEM : S3(2); // Both mems
4405 // %}
4406
4407 // Integer Store to Memory
4408 pipe_class ialu_mem_imm(memory mem)
4409 %{
4410 single_instruction;
4411 mem : S3(read);
4412 D0 : S0; // big decoder only
4413 ALU : S4; // any alu
4414 MEM : S3;
4415 %}
4416
4417 // Integer ALU0 reg-reg operation
4418 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4419 %{
4420 single_instruction;
4421 dst : S4(write);
4422 src : S3(read);
4423 D0 : S0; // Big decoder only
4424 ALU0 : S3; // only alu0
4425 %}
4426
4427 // Integer ALU0 reg-mem operation
4428 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4429 %{
4430 single_instruction;
4431 dst : S5(write);
4432 mem : S3(read);
4433 D0 : S0; // big decoder only
4434 ALU0 : S4; // ALU0 only
4435 MEM : S3; // any mem
4436 %}
4437
4438 // Integer ALU reg-reg operation
4439 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4440 %{
4441 single_instruction;
4442 cr : S4(write);
4443 src1 : S3(read);
4444 src2 : S3(read);
4445 DECODE : S0; // any decoder
4446 ALU : S3; // any alu
4447 %}
4448
4449 // Integer ALU reg-imm operation
4450 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4451 %{
4452 single_instruction;
4453 cr : S4(write);
4454 src1 : S3(read);
4455 DECODE : S0; // any decoder
4456 ALU : S3; // any alu
4457 %}
4458
4459 // Integer ALU reg-mem operation
4460 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4461 %{
4462 single_instruction;
4463 cr : S4(write);
4464 src1 : S3(read);
4465 src2 : S3(read);
4466 D0 : S0; // big decoder only
4467 ALU : S4; // any alu
4468 MEM : S3;
4469 %}
4470
4471 // Conditional move reg-reg
4472 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4473 %{
4474 instruction_count(4);
4475 y : S4(read);
4476 q : S3(read);
4477 p : S3(read);
4478 DECODE : S0(4); // any decoder
4479 %}
4480
4481 // Conditional move reg-reg
4482 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4483 %{
4484 single_instruction;
4485 dst : S4(write);
4486 src : S3(read);
4487 cr : S3(read);
4488 DECODE : S0; // any decoder
4489 %}
4490
4491 // Conditional move reg-mem
4492 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4493 %{
4494 single_instruction;
4495 dst : S4(write);
4496 src : S3(read);
4497 cr : S3(read);
4498 DECODE : S0; // any decoder
4499 MEM : S3;
4500 %}
4501
4502 // Conditional move reg-reg long
4503 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4504 %{
4505 single_instruction;
4506 dst : S4(write);
4507 src : S3(read);
4508 cr : S3(read);
4509 DECODE : S0(2); // any 2 decoders
4510 %}
4511
4512 // XXX
4513 // // Conditional move double reg-reg
4514 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4515 // %{
4516 // single_instruction;
4517 // dst : S4(write);
4518 // src : S3(read);
4519 // cr : S3(read);
4520 // DECODE : S0; // any decoder
4521 // %}
4522
4523 // Float reg-reg operation
4524 pipe_class fpu_reg(regD dst)
4525 %{
4526 instruction_count(2);
4527 dst : S3(read);
4528 DECODE : S0(2); // any 2 decoders
4529 FPU : S3;
4530 %}
4531
4532 // Float reg-reg operation
4533 pipe_class fpu_reg_reg(regD dst, regD src)
4534 %{
4535 instruction_count(2);
4536 dst : S4(write);
4537 src : S3(read);
4538 DECODE : S0(2); // any 2 decoders
4539 FPU : S3;
4540 %}
4541
4542 // Float reg-reg operation
4543 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4544 %{
4545 instruction_count(3);
4546 dst : S4(write);
4547 src1 : S3(read);
4548 src2 : S3(read);
4549 DECODE : S0(3); // any 3 decoders
4550 FPU : S3(2);
4551 %}
4552
4553 // Float reg-reg operation
4554 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4555 %{
4556 instruction_count(4);
4557 dst : S4(write);
4558 src1 : S3(read);
4559 src2 : S3(read);
4560 src3 : S3(read);
4561 DECODE : S0(4); // any 3 decoders
4562 FPU : S3(2);
4563 %}
4564
4565 // Float reg-reg operation
4566 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4567 %{
4568 instruction_count(4);
4569 dst : S4(write);
4570 src1 : S3(read);
4571 src2 : S3(read);
4572 src3 : S3(read);
4573 DECODE : S1(3); // any 3 decoders
4574 D0 : S0; // Big decoder only
4575 FPU : S3(2);
4576 MEM : S3;
4577 %}
4578
4579 // Float reg-mem operation
4580 pipe_class fpu_reg_mem(regD dst, memory mem)
4581 %{
4582 instruction_count(2);
4583 dst : S5(write);
4584 mem : S3(read);
4585 D0 : S0; // big decoder only
4586 DECODE : S1; // any decoder for FPU POP
4587 FPU : S4;
4588 MEM : S3; // any mem
4589 %}
4590
4591 // Float reg-mem operation
4592 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4593 %{
4594 instruction_count(3);
4595 dst : S5(write);
4596 src1 : S3(read);
4597 mem : S3(read);
4598 D0 : S0; // big decoder only
4599 DECODE : S1(2); // any decoder for FPU POP
4600 FPU : S4;
4601 MEM : S3; // any mem
4602 %}
4603
4604 // Float mem-reg operation
4605 pipe_class fpu_mem_reg(memory mem, regD src)
4606 %{
4607 instruction_count(2);
4608 src : S5(read);
4609 mem : S3(read);
4610 DECODE : S0; // any decoder for FPU PUSH
4611 D0 : S1; // big decoder only
4612 FPU : S4;
4613 MEM : S3; // any mem
4614 %}
4615
4616 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4617 %{
4618 instruction_count(3);
4619 src1 : S3(read);
4620 src2 : S3(read);
4621 mem : S3(read);
4622 DECODE : S0(2); // any decoder for FPU PUSH
4623 D0 : S1; // big decoder only
4624 FPU : S4;
4625 MEM : S3; // any mem
4626 %}
4627
4628 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4629 %{
4630 instruction_count(3);
4631 src1 : S3(read);
4632 src2 : S3(read);
4633 mem : S4(read);
4634 DECODE : S0; // any decoder for FPU PUSH
4635 D0 : S0(2); // big decoder only
4636 FPU : S4;
4637 MEM : S3(2); // any mem
4638 %}
4639
4640 pipe_class fpu_mem_mem(memory dst, memory src1)
4641 %{
4642 instruction_count(2);
4643 src1 : S3(read);
4644 dst : S4(read);
4645 D0 : S0(2); // big decoder only
4646 MEM : S3(2); // any mem
4647 %}
4648
4649 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4650 %{
4651 instruction_count(3);
4652 src1 : S3(read);
4653 src2 : S3(read);
4654 dst : S4(read);
4655 D0 : S0(3); // big decoder only
4656 FPU : S4;
4657 MEM : S3(3); // any mem
4658 %}
4659
4660 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4661 %{
4662 instruction_count(3);
4663 src1 : S4(read);
4664 mem : S4(read);
4665 DECODE : S0; // any decoder for FPU PUSH
4666 D0 : S0(2); // big decoder only
4667 FPU : S4;
4668 MEM : S3(2); // any mem
4669 %}
4670
4671 // Float load constant
4672 pipe_class fpu_reg_con(regD dst)
4673 %{
4674 instruction_count(2);
4675 dst : S5(write);
4676 D0 : S0; // big decoder only for the load
4677 DECODE : S1; // any decoder for FPU POP
4678 FPU : S4;
4679 MEM : S3; // any mem
4680 %}
4681
4682 // Float load constant
4683 pipe_class fpu_reg_reg_con(regD dst, regD src)
4684 %{
4685 instruction_count(3);
4686 dst : S5(write);
4687 src : S3(read);
4688 D0 : S0; // big decoder only for the load
4689 DECODE : S1(2); // any decoder for FPU POP
4690 FPU : S4;
4691 MEM : S3; // any mem
4692 %}
4693
4694 // UnConditional branch
4695 pipe_class pipe_jmp(label labl)
4696 %{
4697 single_instruction;
4698 BR : S3;
4699 %}
4700
4701 // Conditional branch
4702 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4703 %{
4704 single_instruction;
4705 cr : S1(read);
4706 BR : S3;
4707 %}
4708
4709 // Allocation idiom
4710 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4711 %{
4712 instruction_count(1); force_serialization;
4713 fixed_latency(6);
4714 heap_ptr : S3(read);
4715 DECODE : S0(3);
4716 D0 : S2;
4717 MEM : S3;
4718 ALU : S3(2);
4719 dst : S5(write);
4720 BR : S5;
4721 %}
4722
4723 // Generic big/slow expanded idiom
4724 pipe_class pipe_slow()
4725 %{
4726 instruction_count(10); multiple_bundles; force_serialization;
4727 fixed_latency(100);
4728 D0 : S0(2);
4729 MEM : S3(2);
4730 %}
4731
4732 // The real do-nothing guy
4733 pipe_class empty()
4734 %{
4735 instruction_count(0);
4736 %}
4737
4738 // Define the class for the Nop node
4739 define
4740 %{
4741 MachNop = empty;
4742 %}
4743
4744 %}
4745
4746 //----------INSTRUCTIONS-------------------------------------------------------
4747 //
4748 // match -- States which machine-independent subtree may be replaced
4749 // by this instruction.
4750 // ins_cost -- The estimated cost of this instruction is used by instruction
4751 // selection to identify a minimum cost tree of machine
4752 // instructions that matches a tree of machine-independent
4753 // instructions.
4754 // format -- A string providing the disassembly for this instruction.
4755 // The value of an instruction's operand may be inserted
4756 // by referring to it with a '$' prefix.
4757 // opcode -- Three instruction opcodes may be provided. These are referred
4758 // to within an encode class as $primary, $secondary, and $tertiary
4759 // rrspectively. The primary opcode is commonly used to
4760 // indicate the type of machine instruction, while secondary
4761 // and tertiary are often used for prefix options or addressing
4762 // modes.
4763 // ins_encode -- A list of encode classes with parameters. The encode class
4764 // name must have been defined in an 'enc_class' specification
4765 // in the encode section of the architecture description.
4766
4767
4768 //----------Load/Store/Move Instructions---------------------------------------
4769 //----------Load Instructions--------------------------------------------------
4770
4771 // Load Byte (8 bit signed)
4772 instruct loadB(rRegI dst, memory mem)
4773 %{
4774 match(Set dst (LoadB mem));
4775
4776 ins_cost(125);
4777 format %{ "movsbl $dst, $mem\t# byte" %}
4778
4779 ins_encode %{
4780 __ movsbl($dst$$Register, $mem$$Address);
4781 %}
4782
4783 ins_pipe(ialu_reg_mem);
4784 %}
4785
4786 // Load Byte (8 bit signed) into Long Register
4787 instruct loadB2L(rRegL dst, memory mem)
4788 %{
4789 match(Set dst (ConvI2L (LoadB mem)));
4790
4791 ins_cost(125);
4792 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4793
4794 ins_encode %{
4795 __ movsbq($dst$$Register, $mem$$Address);
4796 %}
4797
4798 ins_pipe(ialu_reg_mem);
4799 %}
4800
4801 // Load Unsigned Byte (8 bit UNsigned)
4802 instruct loadUB(rRegI dst, memory mem)
4803 %{
4804 match(Set dst (LoadUB mem));
4805
4806 ins_cost(125);
4807 format %{ "movzbl $dst, $mem\t# ubyte" %}
4808
4809 ins_encode %{
4810 __ movzbl($dst$$Register, $mem$$Address);
4811 %}
4812
4813 ins_pipe(ialu_reg_mem);
4814 %}
4815
4816 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4817 instruct loadUB2L(rRegL dst, memory mem)
4818 %{
4819 match(Set dst (ConvI2L (LoadUB mem)));
4820
4821 ins_cost(125);
4822 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4823
4824 ins_encode %{
4825 __ movzbq($dst$$Register, $mem$$Address);
4826 %}
4827
4828 ins_pipe(ialu_reg_mem);
4829 %}
4830
4831 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4832 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4833 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4834 effect(KILL cr);
4835
4836 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4837 "andl $dst, right_n_bits($mask, 8)" %}
4838 ins_encode %{
4839 Register Rdst = $dst$$Register;
4840 __ movzbq(Rdst, $mem$$Address);
4841 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4842 %}
4843 ins_pipe(ialu_reg_mem);
4844 %}
4845
4846 // Load Short (16 bit signed)
4847 instruct loadS(rRegI dst, memory mem)
4848 %{
4849 match(Set dst (LoadS mem));
4850
4851 ins_cost(125);
4852 format %{ "movswl $dst, $mem\t# short" %}
4853
4854 ins_encode %{
4855 __ movswl($dst$$Register, $mem$$Address);
4856 %}
4857
4858 ins_pipe(ialu_reg_mem);
4859 %}
4860
4861 // Load Short (16 bit signed) to Byte (8 bit signed)
4862 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4863 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4864
4865 ins_cost(125);
4866 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4867 ins_encode %{
4868 __ movsbl($dst$$Register, $mem$$Address);
4869 %}
4870 ins_pipe(ialu_reg_mem);
4871 %}
4872
4873 // Load Short (16 bit signed) into Long Register
4874 instruct loadS2L(rRegL dst, memory mem)
4875 %{
4876 match(Set dst (ConvI2L (LoadS mem)));
4877
4878 ins_cost(125);
4879 format %{ "movswq $dst, $mem\t# short -> long" %}
4880
4881 ins_encode %{
4882 __ movswq($dst$$Register, $mem$$Address);
4883 %}
4884
4885 ins_pipe(ialu_reg_mem);
4886 %}
4887
4888 // Load Unsigned Short/Char (16 bit UNsigned)
4889 instruct loadUS(rRegI dst, memory mem)
4890 %{
4891 match(Set dst (LoadUS mem));
4892
4893 ins_cost(125);
4894 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4895
4896 ins_encode %{
4897 __ movzwl($dst$$Register, $mem$$Address);
4898 %}
4899
4900 ins_pipe(ialu_reg_mem);
4901 %}
4902
4903 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4904 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4905 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4906
4907 ins_cost(125);
4908 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4909 ins_encode %{
4910 __ movsbl($dst$$Register, $mem$$Address);
4911 %}
4912 ins_pipe(ialu_reg_mem);
4913 %}
4914
4915 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4916 instruct loadUS2L(rRegL dst, memory mem)
4917 %{
4918 match(Set dst (ConvI2L (LoadUS mem)));
4919
4920 ins_cost(125);
4921 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4922
4923 ins_encode %{
4924 __ movzwq($dst$$Register, $mem$$Address);
4925 %}
4926
4927 ins_pipe(ialu_reg_mem);
4928 %}
4929
4930 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4931 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4932 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4933
4934 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4935 ins_encode %{
4936 __ movzbq($dst$$Register, $mem$$Address);
4937 %}
4938 ins_pipe(ialu_reg_mem);
4939 %}
4940
4941 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4942 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4943 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4944 effect(KILL cr);
4945
4946 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4947 "andl $dst, right_n_bits($mask, 16)" %}
4948 ins_encode %{
4949 Register Rdst = $dst$$Register;
4950 __ movzwq(Rdst, $mem$$Address);
4951 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4952 %}
4953 ins_pipe(ialu_reg_mem);
4954 %}
4955
4956 // Load Integer
4957 instruct loadI(rRegI dst, memory mem)
4958 %{
4959 match(Set dst (LoadI mem));
4960
4961 ins_cost(125);
4962 format %{ "movl $dst, $mem\t# int" %}
4963
4964 ins_encode %{
4965 __ movl($dst$$Register, $mem$$Address);
4966 %}
4967
4968 ins_pipe(ialu_reg_mem);
4969 %}
4970
4971 // Load Integer (32 bit signed) to Byte (8 bit signed)
4972 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4973 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4974
4975 ins_cost(125);
4976 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4977 ins_encode %{
4978 __ movsbl($dst$$Register, $mem$$Address);
4979 %}
4980 ins_pipe(ialu_reg_mem);
4981 %}
4982
4983 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4984 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4985 match(Set dst (AndI (LoadI mem) mask));
4986
4987 ins_cost(125);
4988 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4989 ins_encode %{
4990 __ movzbl($dst$$Register, $mem$$Address);
4991 %}
4992 ins_pipe(ialu_reg_mem);
4993 %}
4994
4995 // Load Integer (32 bit signed) to Short (16 bit signed)
4996 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4997 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4998
4999 ins_cost(125);
5000 format %{ "movswl $dst, $mem\t# int -> short" %}
5001 ins_encode %{
5002 __ movswl($dst$$Register, $mem$$Address);
5003 %}
5004 ins_pipe(ialu_reg_mem);
5005 %}
5006
5007 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5008 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5009 match(Set dst (AndI (LoadI mem) mask));
5010
5011 ins_cost(125);
5012 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5013 ins_encode %{
5014 __ movzwl($dst$$Register, $mem$$Address);
5015 %}
5016 ins_pipe(ialu_reg_mem);
5017 %}
5018
5019 // Load Integer into Long Register
5020 instruct loadI2L(rRegL dst, memory mem)
5021 %{
5022 match(Set dst (ConvI2L (LoadI mem)));
5023
5024 ins_cost(125);
5025 format %{ "movslq $dst, $mem\t# int -> long" %}
5026
5027 ins_encode %{
5028 __ movslq($dst$$Register, $mem$$Address);
5029 %}
5030
5031 ins_pipe(ialu_reg_mem);
5032 %}
5033
5034 // Load Integer with mask 0xFF into Long Register
5035 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5036 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5037
5038 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5039 ins_encode %{
5040 __ movzbq($dst$$Register, $mem$$Address);
5041 %}
5042 ins_pipe(ialu_reg_mem);
5043 %}
5044
5045 // Load Integer with mask 0xFFFF into Long Register
5046 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5047 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5048
5049 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5050 ins_encode %{
5051 __ movzwq($dst$$Register, $mem$$Address);
5052 %}
5053 ins_pipe(ialu_reg_mem);
5054 %}
5055
5056 // Load Integer with a 31-bit mask into Long Register
5057 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5058 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5059 effect(KILL cr);
5060
5061 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5062 "andl $dst, $mask" %}
5063 ins_encode %{
5064 Register Rdst = $dst$$Register;
5065 __ movl(Rdst, $mem$$Address);
5066 __ andl(Rdst, $mask$$constant);
5067 %}
5068 ins_pipe(ialu_reg_mem);
5069 %}
5070
5071 // Load Unsigned Integer into Long Register
5072 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5073 %{
5074 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5075
5076 ins_cost(125);
5077 format %{ "movl $dst, $mem\t# uint -> long" %}
5078
5079 ins_encode %{
5080 __ movl($dst$$Register, $mem$$Address);
5081 %}
5082
5083 ins_pipe(ialu_reg_mem);
5084 %}
5085
5086 // Load Long
5087 instruct loadL(rRegL dst, memory mem)
5088 %{
5089 match(Set dst (LoadL mem));
5090
5091 ins_cost(125);
5092 format %{ "movq $dst, $mem\t# long" %}
5093
5094 ins_encode %{
5095 __ movq($dst$$Register, $mem$$Address);
5096 %}
5097
5098 ins_pipe(ialu_reg_mem); // XXX
5099 %}
5100
5101 // Load Range
5102 instruct loadRange(rRegI dst, memory mem)
5103 %{
5104 match(Set dst (LoadRange mem));
5105
5106 ins_cost(125); // XXX
5107 format %{ "movl $dst, $mem\t# range" %}
5108 opcode(0x8B);
5109 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5110 ins_pipe(ialu_reg_mem);
5111 %}
5112
5113 // Load Pointer
5114 instruct loadP(rRegP dst, memory mem)
5115 %{
5116 match(Set dst (LoadP mem));
5117
5118 ins_cost(125); // XXX
5119 format %{ "movq $dst, $mem\t# ptr" %}
5120 opcode(0x8B);
5121 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5122 ins_pipe(ialu_reg_mem); // XXX
5123 %}
5124
5125 // Load Compressed Pointer
5126 instruct loadN(rRegN dst, memory mem)
5127 %{
5128 match(Set dst (LoadN mem));
5129
5130 ins_cost(125); // XXX
5131 format %{ "movl $dst, $mem\t# compressed ptr" %}
5132 ins_encode %{
5133 __ movl($dst$$Register, $mem$$Address);
5134 %}
5135 ins_pipe(ialu_reg_mem); // XXX
5136 %}
5137
5138
5139 // Load Klass Pointer
5140 instruct loadKlass(rRegP dst, memory mem)
5141 %{
5142 match(Set dst (LoadKlass mem));
5143
5144 ins_cost(125); // XXX
5145 format %{ "movq $dst, $mem\t# class" %}
5146 opcode(0x8B);
5147 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5148 ins_pipe(ialu_reg_mem); // XXX
5149 %}
5150
5151 // Load narrow Klass Pointer
5152 instruct loadNKlass(rRegN dst, memory mem)
5153 %{
5154 match(Set dst (LoadNKlass mem));
5155
5156 ins_cost(125); // XXX
5157 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5158 ins_encode %{
5159 __ movl($dst$$Register, $mem$$Address);
5160 %}
5161 ins_pipe(ialu_reg_mem); // XXX
5162 %}
5163
5164 // Load Float
5165 instruct loadF(regF dst, memory mem)
5166 %{
5167 match(Set dst (LoadF mem));
5168
5169 ins_cost(145); // XXX
5170 format %{ "movss $dst, $mem\t# float" %}
5171 ins_encode %{
5172 __ movflt($dst$$XMMRegister, $mem$$Address);
5173 %}
5174 ins_pipe(pipe_slow); // XXX
5175 %}
5176
5177 // Load Double
5178 instruct loadD_partial(regD dst, memory mem)
5179 %{
5180 predicate(!UseXmmLoadAndClearUpper);
5181 match(Set dst (LoadD mem));
5182
5183 ins_cost(145); // XXX
5184 format %{ "movlpd $dst, $mem\t# double" %}
5185 ins_encode %{
5186 __ movdbl($dst$$XMMRegister, $mem$$Address);
5187 %}
5188 ins_pipe(pipe_slow); // XXX
5189 %}
5190
5191 instruct loadD(regD dst, memory mem)
5192 %{
5193 predicate(UseXmmLoadAndClearUpper);
5194 match(Set dst (LoadD mem));
5195
5196 ins_cost(145); // XXX
5197 format %{ "movsd $dst, $mem\t# double" %}
5198 ins_encode %{
5199 __ movdbl($dst$$XMMRegister, $mem$$Address);
5200 %}
5201 ins_pipe(pipe_slow); // XXX
5202 %}
5203
5204 // Load Effective Address
5205 instruct leaP8(rRegP dst, indOffset8 mem)
5206 %{
5207 match(Set dst mem);
5208
5209 ins_cost(110); // XXX
5210 format %{ "leaq $dst, $mem\t# ptr 8" %}
5211 opcode(0x8D);
5212 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5213 ins_pipe(ialu_reg_reg_fat);
5214 %}
5215
5216 instruct leaP32(rRegP dst, indOffset32 mem)
5217 %{
5218 match(Set dst mem);
5219
5220 ins_cost(110);
5221 format %{ "leaq $dst, $mem\t# ptr 32" %}
5222 opcode(0x8D);
5223 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5224 ins_pipe(ialu_reg_reg_fat);
5225 %}
5226
5227 // instruct leaPIdx(rRegP dst, indIndex mem)
5228 // %{
5229 // match(Set dst mem);
5230
5231 // ins_cost(110);
5232 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5233 // opcode(0x8D);
5234 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5235 // ins_pipe(ialu_reg_reg_fat);
5236 // %}
5237
5238 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5239 %{
5240 match(Set dst mem);
5241
5242 ins_cost(110);
5243 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5244 opcode(0x8D);
5245 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5246 ins_pipe(ialu_reg_reg_fat);
5247 %}
5248
5249 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5250 %{
5251 match(Set dst mem);
5252
5253 ins_cost(110);
5254 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5255 opcode(0x8D);
5256 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5257 ins_pipe(ialu_reg_reg_fat);
5258 %}
5259
5260 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5261 %{
5262 match(Set dst mem);
5263
5264 ins_cost(110);
5265 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5266 opcode(0x8D);
5267 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5268 ins_pipe(ialu_reg_reg_fat);
5269 %}
5270
5271 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5272 %{
5273 match(Set dst mem);
5274
5275 ins_cost(110);
5276 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5277 opcode(0x8D);
5278 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5279 ins_pipe(ialu_reg_reg_fat);
5280 %}
5281
5282 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5283 %{
5284 match(Set dst mem);
5285
5286 ins_cost(110);
5287 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5288 opcode(0x8D);
5289 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5290 ins_pipe(ialu_reg_reg_fat);
5291 %}
5292
5293 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5294 %{
5295 match(Set dst mem);
5296
5297 ins_cost(110);
5298 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5299 opcode(0x8D);
5300 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5301 ins_pipe(ialu_reg_reg_fat);
5302 %}
5303
5304 // Load Effective Address which uses Narrow (32-bits) oop
5305 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5306 %{
5307 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5308 match(Set dst mem);
5309
5310 ins_cost(110);
5311 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5312 opcode(0x8D);
5313 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5314 ins_pipe(ialu_reg_reg_fat);
5315 %}
5316
5317 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5318 %{
5319 predicate(Universe::narrow_oop_shift() == 0);
5320 match(Set dst mem);
5321
5322 ins_cost(110); // XXX
5323 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5324 opcode(0x8D);
5325 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5326 ins_pipe(ialu_reg_reg_fat);
5327 %}
5328
5329 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5330 %{
5331 predicate(Universe::narrow_oop_shift() == 0);
5332 match(Set dst mem);
5333
5334 ins_cost(110);
5335 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5336 opcode(0x8D);
5337 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5338 ins_pipe(ialu_reg_reg_fat);
5339 %}
5340
5341 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5342 %{
5343 predicate(Universe::narrow_oop_shift() == 0);
5344 match(Set dst mem);
5345
5346 ins_cost(110);
5347 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5348 opcode(0x8D);
5349 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5350 ins_pipe(ialu_reg_reg_fat);
5351 %}
5352
5353 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5354 %{
5355 predicate(Universe::narrow_oop_shift() == 0);
5356 match(Set dst mem);
5357
5358 ins_cost(110);
5359 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5360 opcode(0x8D);
5361 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5362 ins_pipe(ialu_reg_reg_fat);
5363 %}
5364
5365 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5366 %{
5367 predicate(Universe::narrow_oop_shift() == 0);
5368 match(Set dst mem);
5369
5370 ins_cost(110);
5371 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5372 opcode(0x8D);
5373 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5374 ins_pipe(ialu_reg_reg_fat);
5375 %}
5376
5377 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5378 %{
5379 predicate(Universe::narrow_oop_shift() == 0);
5380 match(Set dst mem);
5381
5382 ins_cost(110);
5383 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5384 opcode(0x8D);
5385 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5386 ins_pipe(ialu_reg_reg_fat);
5387 %}
5388
5389 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5390 %{
5391 predicate(Universe::narrow_oop_shift() == 0);
5392 match(Set dst mem);
5393
5394 ins_cost(110);
5395 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5396 opcode(0x8D);
5397 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5398 ins_pipe(ialu_reg_reg_fat);
5399 %}
5400
5401 instruct loadConI(rRegI dst, immI src)
5402 %{
5403 match(Set dst src);
5404
5405 format %{ "movl $dst, $src\t# int" %}
5406 ins_encode(load_immI(dst, src));
5407 ins_pipe(ialu_reg_fat); // XXX
5408 %}
5409
5410 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5411 %{
5412 match(Set dst src);
5413 effect(KILL cr);
5414
5415 ins_cost(50);
5416 format %{ "xorl $dst, $dst\t# int" %}
5417 opcode(0x33); /* + rd */
5418 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5419 ins_pipe(ialu_reg);
5420 %}
5421
5422 instruct loadConL(rRegL dst, immL src)
5423 %{
5424 match(Set dst src);
5425
5426 ins_cost(150);
5427 format %{ "movq $dst, $src\t# long" %}
5428 ins_encode(load_immL(dst, src));
5429 ins_pipe(ialu_reg);
5430 %}
5431
5432 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5433 %{
5434 match(Set dst src);
5435 effect(KILL cr);
5436
5437 ins_cost(50);
5438 format %{ "xorl $dst, $dst\t# long" %}
5439 opcode(0x33); /* + rd */
5440 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5441 ins_pipe(ialu_reg); // XXX
5442 %}
5443
5444 instruct loadConUL32(rRegL dst, immUL32 src)
5445 %{
5446 match(Set dst src);
5447
5448 ins_cost(60);
5449 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5450 ins_encode(load_immUL32(dst, src));
5451 ins_pipe(ialu_reg);
5452 %}
5453
5454 instruct loadConL32(rRegL dst, immL32 src)
5455 %{
5456 match(Set dst src);
5457
5458 ins_cost(70);
5459 format %{ "movq $dst, $src\t# long (32-bit)" %}
5460 ins_encode(load_immL32(dst, src));
5461 ins_pipe(ialu_reg);
5462 %}
5463
5464 instruct loadConP(rRegP dst, immP con) %{
5465 match(Set dst con);
5466
5467 format %{ "movq $dst, $con\t# ptr" %}
5468 ins_encode(load_immP(dst, con));
5469 ins_pipe(ialu_reg_fat); // XXX
5470 %}
5471
5472 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5473 %{
5474 match(Set dst src);
5475 effect(KILL cr);
5476
5477 ins_cost(50);
5478 format %{ "xorl $dst, $dst\t# ptr" %}
5479 opcode(0x33); /* + rd */
5480 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5481 ins_pipe(ialu_reg);
5482 %}
5483
5484 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5485 %{
5486 match(Set dst src);
5487 effect(KILL cr);
5488
5489 ins_cost(60);
5490 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5491 ins_encode(load_immP31(dst, src));
5492 ins_pipe(ialu_reg);
5493 %}
5494
5495 instruct loadConF(regF dst, immF con) %{
5496 match(Set dst con);
5497 ins_cost(125);
5498 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5499 ins_encode %{
5500 __ movflt($dst$$XMMRegister, $constantaddress($con));
5501 %}
5502 ins_pipe(pipe_slow);
5503 %}
5504
5505 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5506 match(Set dst src);
5507 effect(KILL cr);
5508 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5509 ins_encode %{
5510 __ xorq($dst$$Register, $dst$$Register);
5511 %}
5512 ins_pipe(ialu_reg);
5513 %}
5514
5515 instruct loadConN(rRegN dst, immN src) %{
5516 match(Set dst src);
5517
5518 ins_cost(125);
5519 format %{ "movl $dst, $src\t# compressed ptr" %}
5520 ins_encode %{
5521 address con = (address)$src$$constant;
5522 if (con == NULL) {
5523 ShouldNotReachHere();
5524 } else {
5525 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5526 }
5527 %}
5528 ins_pipe(ialu_reg_fat); // XXX
5529 %}
5530
5531 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5532 match(Set dst src);
5533
5534 ins_cost(125);
5535 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5536 ins_encode %{
5537 address con = (address)$src$$constant;
5538 if (con == NULL) {
5539 ShouldNotReachHere();
5540 } else {
5541 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5542 }
5543 %}
5544 ins_pipe(ialu_reg_fat); // XXX
5545 %}
5546
5547 instruct loadConF0(regF dst, immF0 src)
5548 %{
5549 match(Set dst src);
5550 ins_cost(100);
5551
5552 format %{ "xorps $dst, $dst\t# float 0.0" %}
5553 ins_encode %{
5554 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5555 %}
5556 ins_pipe(pipe_slow);
5557 %}
5558
5559 // Use the same format since predicate() can not be used here.
5560 instruct loadConD(regD dst, immD con) %{
5561 match(Set dst con);
5562 ins_cost(125);
5563 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5564 ins_encode %{
5565 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5566 %}
5567 ins_pipe(pipe_slow);
5568 %}
5569
5570 instruct loadConD0(regD dst, immD0 src)
5571 %{
5572 match(Set dst src);
5573 ins_cost(100);
5574
5575 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5576 ins_encode %{
5577 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5578 %}
5579 ins_pipe(pipe_slow);
5580 %}
5581
5582 instruct loadSSI(rRegI dst, stackSlotI src)
5583 %{
5584 match(Set dst src);
5585
5586 ins_cost(125);
5587 format %{ "movl $dst, $src\t# int stk" %}
5588 opcode(0x8B);
5589 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5590 ins_pipe(ialu_reg_mem);
5591 %}
5592
5593 instruct loadSSL(rRegL dst, stackSlotL src)
5594 %{
5595 match(Set dst src);
5596
5597 ins_cost(125);
5598 format %{ "movq $dst, $src\t# long stk" %}
5599 opcode(0x8B);
5600 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5601 ins_pipe(ialu_reg_mem);
5602 %}
5603
5604 instruct loadSSP(rRegP dst, stackSlotP src)
5605 %{
5606 match(Set dst src);
5607
5608 ins_cost(125);
5609 format %{ "movq $dst, $src\t# ptr stk" %}
5610 opcode(0x8B);
5611 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5612 ins_pipe(ialu_reg_mem);
5613 %}
5614
5615 instruct loadSSF(regF dst, stackSlotF src)
5616 %{
5617 match(Set dst src);
5618
5619 ins_cost(125);
5620 format %{ "movss $dst, $src\t# float stk" %}
5621 ins_encode %{
5622 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5623 %}
5624 ins_pipe(pipe_slow); // XXX
5625 %}
5626
5627 // Use the same format since predicate() can not be used here.
5628 instruct loadSSD(regD dst, stackSlotD src)
5629 %{
5630 match(Set dst src);
5631
5632 ins_cost(125);
5633 format %{ "movsd $dst, $src\t# double stk" %}
5634 ins_encode %{
5635 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5636 %}
5637 ins_pipe(pipe_slow); // XXX
5638 %}
5639
5640 // Prefetch instructions for allocation.
5641 // Must be safe to execute with invalid address (cannot fault).
5642
5643 instruct prefetchAlloc( memory mem ) %{
5644 predicate(AllocatePrefetchInstr==3);
5645 match(PrefetchAllocation mem);
5646 ins_cost(125);
5647
5648 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5649 ins_encode %{
5650 __ prefetchw($mem$$Address);
5651 %}
5652 ins_pipe(ialu_mem);
5653 %}
5654
5655 instruct prefetchAllocNTA( memory mem ) %{
5656 predicate(AllocatePrefetchInstr==0);
5657 match(PrefetchAllocation mem);
5658 ins_cost(125);
5659
5660 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5661 ins_encode %{
5662 __ prefetchnta($mem$$Address);
5663 %}
5664 ins_pipe(ialu_mem);
5665 %}
5666
5667 instruct prefetchAllocT0( memory mem ) %{
5668 predicate(AllocatePrefetchInstr==1);
5669 match(PrefetchAllocation mem);
5670 ins_cost(125);
5671
5672 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5673 ins_encode %{
5674 __ prefetcht0($mem$$Address);
5675 %}
5676 ins_pipe(ialu_mem);
5677 %}
5678
5679 instruct prefetchAllocT2( memory mem ) %{
5680 predicate(AllocatePrefetchInstr==2);
5681 match(PrefetchAllocation mem);
5682 ins_cost(125);
5683
5684 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5685 ins_encode %{
5686 __ prefetcht2($mem$$Address);
5687 %}
5688 ins_pipe(ialu_mem);
5689 %}
5690
5691 //----------Store Instructions-------------------------------------------------
5692
5693 // Store Byte
5694 instruct storeB(memory mem, rRegI src)
5695 %{
5696 match(Set mem (StoreB mem src));
5697
5698 ins_cost(125); // XXX
5699 format %{ "movb $mem, $src\t# byte" %}
5700 opcode(0x88);
5701 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5702 ins_pipe(ialu_mem_reg);
5703 %}
5704
5705 // Store Char/Short
5706 instruct storeC(memory mem, rRegI src)
5707 %{
5708 match(Set mem (StoreC mem src));
5709
5710 ins_cost(125); // XXX
5711 format %{ "movw $mem, $src\t# char/short" %}
5712 opcode(0x89);
5713 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5714 ins_pipe(ialu_mem_reg);
5715 %}
5716
5717 // Store Integer
5718 instruct storeI(memory mem, rRegI src)
5719 %{
5720 match(Set mem (StoreI mem src));
5721
5722 ins_cost(125); // XXX
5723 format %{ "movl $mem, $src\t# int" %}
5724 opcode(0x89);
5725 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5726 ins_pipe(ialu_mem_reg);
5727 %}
5728
5729 // Store Long
5730 instruct storeL(memory mem, rRegL src)
5731 %{
5732 match(Set mem (StoreL mem src));
5733
5734 ins_cost(125); // XXX
5735 format %{ "movq $mem, $src\t# long" %}
5736 opcode(0x89);
5737 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5738 ins_pipe(ialu_mem_reg); // XXX
5739 %}
5740
5741 // Store Pointer
5742 instruct storeP(memory mem, any_RegP src)
5743 %{
5744 match(Set mem (StoreP mem src));
5745
5746 ins_cost(125); // XXX
5747 format %{ "movq $mem, $src\t# ptr" %}
5748 opcode(0x89);
5749 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5750 ins_pipe(ialu_mem_reg);
5751 %}
5752
5753 instruct storeImmP0(memory mem, immP0 zero)
5754 %{
5755 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5756 match(Set mem (StoreP mem zero));
5757
5758 ins_cost(125); // XXX
5759 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5760 ins_encode %{
5761 __ movq($mem$$Address, r12);
5762 %}
5763 ins_pipe(ialu_mem_reg);
5764 %}
5765
5766 // Store NULL Pointer, mark word, or other simple pointer constant.
5767 instruct storeImmP(memory mem, immP31 src)
5768 %{
5769 match(Set mem (StoreP mem src));
5770
5771 ins_cost(150); // XXX
5772 format %{ "movq $mem, $src\t# ptr" %}
5773 opcode(0xC7); /* C7 /0 */
5774 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5775 ins_pipe(ialu_mem_imm);
5776 %}
5777
5778 // Store Compressed Pointer
5779 instruct storeN(memory mem, rRegN src)
5780 %{
5781 match(Set mem (StoreN mem src));
5782
5783 ins_cost(125); // XXX
5784 format %{ "movl $mem, $src\t# compressed ptr" %}
5785 ins_encode %{
5786 __ movl($mem$$Address, $src$$Register);
5787 %}
5788 ins_pipe(ialu_mem_reg);
5789 %}
5790
5791 instruct storeNKlass(memory mem, rRegN src)
5792 %{
5793 match(Set mem (StoreNKlass mem src));
5794
5795 ins_cost(125); // XXX
5796 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5797 ins_encode %{
5798 __ movl($mem$$Address, $src$$Register);
5799 %}
5800 ins_pipe(ialu_mem_reg);
5801 %}
5802
5803 instruct storeImmN0(memory mem, immN0 zero)
5804 %{
5805 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5806 match(Set mem (StoreN mem zero));
5807
5808 ins_cost(125); // XXX
5809 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5810 ins_encode %{
5811 __ movl($mem$$Address, r12);
5812 %}
5813 ins_pipe(ialu_mem_reg);
5814 %}
5815
5816 instruct storeImmN(memory mem, immN src)
5817 %{
5818 match(Set mem (StoreN mem src));
5819
5820 ins_cost(150); // XXX
5821 format %{ "movl $mem, $src\t# compressed ptr" %}
5822 ins_encode %{
5823 address con = (address)$src$$constant;
5824 if (con == NULL) {
5825 __ movl($mem$$Address, (int32_t)0);
5826 } else {
5827 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5828 }
5829 %}
5830 ins_pipe(ialu_mem_imm);
5831 %}
5832
5833 instruct storeImmNKlass(memory mem, immNKlass src)
5834 %{
5835 match(Set mem (StoreNKlass mem src));
5836
5837 ins_cost(150); // XXX
5838 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5839 ins_encode %{
5840 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5841 %}
5842 ins_pipe(ialu_mem_imm);
5843 %}
5844
5845 // Store Integer Immediate
5846 instruct storeImmI0(memory mem, immI0 zero)
5847 %{
5848 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5849 match(Set mem (StoreI mem zero));
5850
5851 ins_cost(125); // XXX
5852 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5853 ins_encode %{
5854 __ movl($mem$$Address, r12);
5855 %}
5856 ins_pipe(ialu_mem_reg);
5857 %}
5858
5859 instruct storeImmI(memory mem, immI src)
5860 %{
5861 match(Set mem (StoreI mem src));
5862
5863 ins_cost(150);
5864 format %{ "movl $mem, $src\t# int" %}
5865 opcode(0xC7); /* C7 /0 */
5866 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5867 ins_pipe(ialu_mem_imm);
5868 %}
5869
5870 // Store Long Immediate
5871 instruct storeImmL0(memory mem, immL0 zero)
5872 %{
5873 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5874 match(Set mem (StoreL mem zero));
5875
5876 ins_cost(125); // XXX
5877 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5878 ins_encode %{
5879 __ movq($mem$$Address, r12);
5880 %}
5881 ins_pipe(ialu_mem_reg);
5882 %}
5883
5884 instruct storeImmL(memory mem, immL32 src)
5885 %{
5886 match(Set mem (StoreL mem src));
5887
5888 ins_cost(150);
5889 format %{ "movq $mem, $src\t# long" %}
5890 opcode(0xC7); /* C7 /0 */
5891 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5892 ins_pipe(ialu_mem_imm);
5893 %}
5894
5895 // Store Short/Char Immediate
5896 instruct storeImmC0(memory mem, immI0 zero)
5897 %{
5898 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5899 match(Set mem (StoreC mem zero));
5900
5901 ins_cost(125); // XXX
5902 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5903 ins_encode %{
5904 __ movw($mem$$Address, r12);
5905 %}
5906 ins_pipe(ialu_mem_reg);
5907 %}
5908
5909 instruct storeImmI16(memory mem, immI16 src)
5910 %{
5911 predicate(UseStoreImmI16);
5912 match(Set mem (StoreC mem src));
5913
5914 ins_cost(150);
5915 format %{ "movw $mem, $src\t# short/char" %}
5916 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5917 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5918 ins_pipe(ialu_mem_imm);
5919 %}
5920
5921 // Store Byte Immediate
5922 instruct storeImmB0(memory mem, immI0 zero)
5923 %{
5924 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5925 match(Set mem (StoreB mem zero));
5926
5927 ins_cost(125); // XXX
5928 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5929 ins_encode %{
5930 __ movb($mem$$Address, r12);
5931 %}
5932 ins_pipe(ialu_mem_reg);
5933 %}
5934
5935 instruct storeImmB(memory mem, immI8 src)
5936 %{
5937 match(Set mem (StoreB mem src));
5938
5939 ins_cost(150); // XXX
5940 format %{ "movb $mem, $src\t# byte" %}
5941 opcode(0xC6); /* C6 /0 */
5942 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5943 ins_pipe(ialu_mem_imm);
5944 %}
5945
5946 // Store CMS card-mark Immediate
5947 instruct storeImmCM0_reg(memory mem, immI0 zero)
5948 %{
5949 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5950 match(Set mem (StoreCM mem zero));
5951
5952 ins_cost(125); // XXX
5953 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5954 ins_encode %{
5955 __ movb($mem$$Address, r12);
5956 %}
5957 ins_pipe(ialu_mem_reg);
5958 %}
5959
5960 instruct storeImmCM0(memory mem, immI0 src)
5961 %{
5962 match(Set mem (StoreCM mem src));
5963
5964 ins_cost(150); // XXX
5965 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5966 opcode(0xC6); /* C6 /0 */
5967 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5968 ins_pipe(ialu_mem_imm);
5969 %}
5970
5971 // Store Float
5972 instruct storeF(memory mem, regF src)
5973 %{
5974 match(Set mem (StoreF mem src));
5975
5976 ins_cost(95); // XXX
5977 format %{ "movss $mem, $src\t# float" %}
5978 ins_encode %{
5979 __ movflt($mem$$Address, $src$$XMMRegister);
5980 %}
5981 ins_pipe(pipe_slow); // XXX
5982 %}
5983
5984 // Store immediate Float value (it is faster than store from XMM register)
5985 instruct storeF0(memory mem, immF0 zero)
5986 %{
5987 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5988 match(Set mem (StoreF mem zero));
5989
5990 ins_cost(25); // XXX
5991 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5992 ins_encode %{
5993 __ movl($mem$$Address, r12);
5994 %}
5995 ins_pipe(ialu_mem_reg);
5996 %}
5997
5998 instruct storeF_imm(memory mem, immF src)
5999 %{
6000 match(Set mem (StoreF mem src));
6001
6002 ins_cost(50);
6003 format %{ "movl $mem, $src\t# float" %}
6004 opcode(0xC7); /* C7 /0 */
6005 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6006 ins_pipe(ialu_mem_imm);
6007 %}
6008
6009 // Store Double
6010 instruct storeD(memory mem, regD src)
6011 %{
6012 match(Set mem (StoreD mem src));
6013
6014 ins_cost(95); // XXX
6015 format %{ "movsd $mem, $src\t# double" %}
6016 ins_encode %{
6017 __ movdbl($mem$$Address, $src$$XMMRegister);
6018 %}
6019 ins_pipe(pipe_slow); // XXX
6020 %}
6021
6022 // Store immediate double 0.0 (it is faster than store from XMM register)
6023 instruct storeD0_imm(memory mem, immD0 src)
6024 %{
6025 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6026 match(Set mem (StoreD mem src));
6027
6028 ins_cost(50);
6029 format %{ "movq $mem, $src\t# double 0." %}
6030 opcode(0xC7); /* C7 /0 */
6031 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6032 ins_pipe(ialu_mem_imm);
6033 %}
6034
6035 instruct storeD0(memory mem, immD0 zero)
6036 %{
6037 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6038 match(Set mem (StoreD mem zero));
6039
6040 ins_cost(25); // XXX
6041 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6042 ins_encode %{
6043 __ movq($mem$$Address, r12);
6044 %}
6045 ins_pipe(ialu_mem_reg);
6046 %}
6047
6048 instruct storeSSI(stackSlotI dst, rRegI src)
6049 %{
6050 match(Set dst src);
6051
6052 ins_cost(100);
6053 format %{ "movl $dst, $src\t# int stk" %}
6054 opcode(0x89);
6055 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6056 ins_pipe( ialu_mem_reg );
6057 %}
6058
6059 instruct storeSSL(stackSlotL dst, rRegL src)
6060 %{
6061 match(Set dst src);
6062
6063 ins_cost(100);
6064 format %{ "movq $dst, $src\t# long stk" %}
6065 opcode(0x89);
6066 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6067 ins_pipe(ialu_mem_reg);
6068 %}
6069
6070 instruct storeSSP(stackSlotP dst, rRegP src)
6071 %{
6072 match(Set dst src);
6073
6074 ins_cost(100);
6075 format %{ "movq $dst, $src\t# ptr stk" %}
6076 opcode(0x89);
6077 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6078 ins_pipe(ialu_mem_reg);
6079 %}
6080
6081 instruct storeSSF(stackSlotF dst, regF src)
6082 %{
6083 match(Set dst src);
6084
6085 ins_cost(95); // XXX
6086 format %{ "movss $dst, $src\t# float stk" %}
6087 ins_encode %{
6088 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6089 %}
6090 ins_pipe(pipe_slow); // XXX
6091 %}
6092
6093 instruct storeSSD(stackSlotD dst, regD src)
6094 %{
6095 match(Set dst src);
6096
6097 ins_cost(95); // XXX
6098 format %{ "movsd $dst, $src\t# double stk" %}
6099 ins_encode %{
6100 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6101 %}
6102 ins_pipe(pipe_slow); // XXX
6103 %}
6104
6105 //----------BSWAP Instructions-------------------------------------------------
6106 instruct bytes_reverse_int(rRegI dst) %{
6107 match(Set dst (ReverseBytesI dst));
6108
6109 format %{ "bswapl $dst" %}
6110 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6111 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6112 ins_pipe( ialu_reg );
6113 %}
6114
6115 instruct bytes_reverse_long(rRegL dst) %{
6116 match(Set dst (ReverseBytesL dst));
6117
6118 format %{ "bswapq $dst" %}
6119 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6120 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6121 ins_pipe( ialu_reg);
6122 %}
6123
6124 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6125 match(Set dst (ReverseBytesUS dst));
6126 effect(KILL cr);
6127
6128 format %{ "bswapl $dst\n\t"
6129 "shrl $dst,16\n\t" %}
6130 ins_encode %{
6131 __ bswapl($dst$$Register);
6132 __ shrl($dst$$Register, 16);
6133 %}
6134 ins_pipe( ialu_reg );
6135 %}
6136
6137 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6138 match(Set dst (ReverseBytesS dst));
6139 effect(KILL cr);
6140
6141 format %{ "bswapl $dst\n\t"
6142 "sar $dst,16\n\t" %}
6143 ins_encode %{
6144 __ bswapl($dst$$Register);
6145 __ sarl($dst$$Register, 16);
6146 %}
6147 ins_pipe( ialu_reg );
6148 %}
6149
6150 //---------- Zeros Count Instructions ------------------------------------------
6151
6152 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6153 predicate(UseCountLeadingZerosInstruction);
6154 match(Set dst (CountLeadingZerosI src));
6155 effect(KILL cr);
6156
6157 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6158 ins_encode %{
6159 __ lzcntl($dst$$Register, $src$$Register);
6160 %}
6161 ins_pipe(ialu_reg);
6162 %}
6163
6164 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6165 predicate(!UseCountLeadingZerosInstruction);
6166 match(Set dst (CountLeadingZerosI src));
6167 effect(KILL cr);
6168
6169 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6170 "jnz skip\n\t"
6171 "movl $dst, -1\n"
6172 "skip:\n\t"
6173 "negl $dst\n\t"
6174 "addl $dst, 31" %}
6175 ins_encode %{
6176 Register Rdst = $dst$$Register;
6177 Register Rsrc = $src$$Register;
6178 Label skip;
6179 __ bsrl(Rdst, Rsrc);
6180 __ jccb(Assembler::notZero, skip);
6181 __ movl(Rdst, -1);
6182 __ bind(skip);
6183 __ negl(Rdst);
6184 __ addl(Rdst, BitsPerInt - 1);
6185 %}
6186 ins_pipe(ialu_reg);
6187 %}
6188
6189 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6190 predicate(UseCountLeadingZerosInstruction);
6191 match(Set dst (CountLeadingZerosL src));
6192 effect(KILL cr);
6193
6194 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6195 ins_encode %{
6196 __ lzcntq($dst$$Register, $src$$Register);
6197 %}
6198 ins_pipe(ialu_reg);
6199 %}
6200
6201 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6202 predicate(!UseCountLeadingZerosInstruction);
6203 match(Set dst (CountLeadingZerosL src));
6204 effect(KILL cr);
6205
6206 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6207 "jnz skip\n\t"
6208 "movl $dst, -1\n"
6209 "skip:\n\t"
6210 "negl $dst\n\t"
6211 "addl $dst, 63" %}
6212 ins_encode %{
6213 Register Rdst = $dst$$Register;
6214 Register Rsrc = $src$$Register;
6215 Label skip;
6216 __ bsrq(Rdst, Rsrc);
6217 __ jccb(Assembler::notZero, skip);
6218 __ movl(Rdst, -1);
6219 __ bind(skip);
6220 __ negl(Rdst);
6221 __ addl(Rdst, BitsPerLong - 1);
6222 %}
6223 ins_pipe(ialu_reg);
6224 %}
6225
6226 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6227 predicate(UseCountTrailingZerosInstruction);
6228 match(Set dst (CountTrailingZerosI src));
6229 effect(KILL cr);
6230
6231 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6232 ins_encode %{
6233 __ tzcntl($dst$$Register, $src$$Register);
6234 %}
6235 ins_pipe(ialu_reg);
6236 %}
6237
6238 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6239 predicate(!UseCountTrailingZerosInstruction);
6240 match(Set dst (CountTrailingZerosI src));
6241 effect(KILL cr);
6242
6243 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6244 "jnz done\n\t"
6245 "movl $dst, 32\n"
6246 "done:" %}
6247 ins_encode %{
6248 Register Rdst = $dst$$Register;
6249 Label done;
6250 __ bsfl(Rdst, $src$$Register);
6251 __ jccb(Assembler::notZero, done);
6252 __ movl(Rdst, BitsPerInt);
6253 __ bind(done);
6254 %}
6255 ins_pipe(ialu_reg);
6256 %}
6257
6258 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6259 predicate(UseCountTrailingZerosInstruction);
6260 match(Set dst (CountTrailingZerosL src));
6261 effect(KILL cr);
6262
6263 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6264 ins_encode %{
6265 __ tzcntq($dst$$Register, $src$$Register);
6266 %}
6267 ins_pipe(ialu_reg);
6268 %}
6269
6270 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6271 predicate(!UseCountTrailingZerosInstruction);
6272 match(Set dst (CountTrailingZerosL src));
6273 effect(KILL cr);
6274
6275 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6276 "jnz done\n\t"
6277 "movl $dst, 64\n"
6278 "done:" %}
6279 ins_encode %{
6280 Register Rdst = $dst$$Register;
6281 Label done;
6282 __ bsfq(Rdst, $src$$Register);
6283 __ jccb(Assembler::notZero, done);
6284 __ movl(Rdst, BitsPerLong);
6285 __ bind(done);
6286 %}
6287 ins_pipe(ialu_reg);
6288 %}
6289
6290
6291 //---------- Population Count Instructions -------------------------------------
6292
6293 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6294 predicate(UsePopCountInstruction);
6295 match(Set dst (PopCountI src));
6296 effect(KILL cr);
6297
6298 format %{ "popcnt $dst, $src" %}
6299 ins_encode %{
6300 __ popcntl($dst$$Register, $src$$Register);
6301 %}
6302 ins_pipe(ialu_reg);
6303 %}
6304
6305 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6306 predicate(UsePopCountInstruction);
6307 match(Set dst (PopCountI (LoadI mem)));
6308 effect(KILL cr);
6309
6310 format %{ "popcnt $dst, $mem" %}
6311 ins_encode %{
6312 __ popcntl($dst$$Register, $mem$$Address);
6313 %}
6314 ins_pipe(ialu_reg);
6315 %}
6316
6317 // Note: Long.bitCount(long) returns an int.
6318 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6319 predicate(UsePopCountInstruction);
6320 match(Set dst (PopCountL src));
6321 effect(KILL cr);
6322
6323 format %{ "popcnt $dst, $src" %}
6324 ins_encode %{
6325 __ popcntq($dst$$Register, $src$$Register);
6326 %}
6327 ins_pipe(ialu_reg);
6328 %}
6329
6330 // Note: Long.bitCount(long) returns an int.
6331 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6332 predicate(UsePopCountInstruction);
6333 match(Set dst (PopCountL (LoadL mem)));
6334 effect(KILL cr);
6335
6336 format %{ "popcnt $dst, $mem" %}
6337 ins_encode %{
6338 __ popcntq($dst$$Register, $mem$$Address);
6339 %}
6340 ins_pipe(ialu_reg);
6341 %}
6342
6343
6344 //----------MemBar Instructions-----------------------------------------------
6345 // Memory barrier flavors
6346
6347 instruct membar_acquire()
6348 %{
6349 match(MemBarAcquire);
6350 match(LoadFence);
6351 ins_cost(0);
6352
6353 size(0);
6354 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6355 ins_encode();
6356 ins_pipe(empty);
6357 %}
6358
6359 instruct membar_acquire_lock()
6360 %{
6361 match(MemBarAcquireLock);
6362 ins_cost(0);
6363
6364 size(0);
6365 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6366 ins_encode();
6367 ins_pipe(empty);
6368 %}
6369
6370 instruct membar_release()
6371 %{
6372 match(MemBarRelease);
6373 match(StoreFence);
6374 ins_cost(0);
6375
6376 size(0);
6377 format %{ "MEMBAR-release ! (empty encoding)" %}
6378 ins_encode();
6379 ins_pipe(empty);
6380 %}
6381
6382 instruct membar_release_lock()
6383 %{
6384 match(MemBarReleaseLock);
6385 ins_cost(0);
6386
6387 size(0);
6388 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6389 ins_encode();
6390 ins_pipe(empty);
6391 %}
6392
6393 instruct membar_volatile(rFlagsReg cr) %{
6394 match(MemBarVolatile);
6395 effect(KILL cr);
6396 ins_cost(400);
6397
6398 format %{
6399 $$template
6400 if (os::is_MP()) {
6401 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6402 } else {
6403 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6404 }
6405 %}
6406 ins_encode %{
6407 __ membar(Assembler::StoreLoad);
6408 %}
6409 ins_pipe(pipe_slow);
6410 %}
6411
6412 instruct unnecessary_membar_volatile()
6413 %{
6414 match(MemBarVolatile);
6415 predicate(Matcher::post_store_load_barrier(n));
6416 ins_cost(0);
6417
6418 size(0);
6419 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6420 ins_encode();
6421 ins_pipe(empty);
6422 %}
6423
6424 instruct membar_storestore() %{
6425 match(MemBarStoreStore);
6426 ins_cost(0);
6427
6428 size(0);
6429 format %{ "MEMBAR-storestore (empty encoding)" %}
6430 ins_encode( );
6431 ins_pipe(empty);
6432 %}
6433
6434 //----------Move Instructions--------------------------------------------------
6435
6436 instruct castX2P(rRegP dst, rRegL src)
6437 %{
6438 match(Set dst (CastX2P src));
6439
6440 format %{ "movq $dst, $src\t# long->ptr" %}
6441 ins_encode %{
6442 if ($dst$$reg != $src$$reg) {
6443 __ movptr($dst$$Register, $src$$Register);
6444 }
6445 %}
6446 ins_pipe(ialu_reg_reg); // XXX
6447 %}
6448
6449 instruct castP2X(rRegL dst, rRegP src)
6450 %{
6451 match(Set dst (CastP2X src));
6452
6453 format %{ "movq $dst, $src\t# ptr -> long" %}
6454 ins_encode %{
6455 if ($dst$$reg != $src$$reg) {
6456 __ movptr($dst$$Register, $src$$Register);
6457 }
6458 %}
6459 ins_pipe(ialu_reg_reg); // XXX
6460 %}
6461
6462 // Convert oop into int for vectors alignment masking
6463 instruct convP2I(rRegI dst, rRegP src)
6464 %{
6465 match(Set dst (ConvL2I (CastP2X src)));
6466
6467 format %{ "movl $dst, $src\t# ptr -> int" %}
6468 ins_encode %{
6469 __ movl($dst$$Register, $src$$Register);
6470 %}
6471 ins_pipe(ialu_reg_reg); // XXX
6472 %}
6473
6474 // Convert compressed oop into int for vectors alignment masking
6475 // in case of 32bit oops (heap < 4Gb).
6476 instruct convN2I(rRegI dst, rRegN src)
6477 %{
6478 predicate(Universe::narrow_oop_shift() == 0);
6479 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6480
6481 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6482 ins_encode %{
6483 __ movl($dst$$Register, $src$$Register);
6484 %}
6485 ins_pipe(ialu_reg_reg); // XXX
6486 %}
6487
6488 // Convert oop pointer into compressed form
6489 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6490 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6491 match(Set dst (EncodeP src));
6492 effect(KILL cr);
6493 format %{ "encode_heap_oop $dst,$src" %}
6494 ins_encode %{
6495 Register s = $src$$Register;
6496 Register d = $dst$$Register;
6497 if (s != d) {
6498 __ movq(d, s);
6499 }
6500 __ encode_heap_oop(d);
6501 %}
6502 ins_pipe(ialu_reg_long);
6503 %}
6504
6505 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6506 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6507 match(Set dst (EncodeP src));
6508 effect(KILL cr);
6509 format %{ "encode_heap_oop_not_null $dst,$src" %}
6510 ins_encode %{
6511 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6512 %}
6513 ins_pipe(ialu_reg_long);
6514 %}
6515
6516 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6517 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6518 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6519 match(Set dst (DecodeN src));
6520 effect(KILL cr);
6521 format %{ "decode_heap_oop $dst,$src" %}
6522 ins_encode %{
6523 Register s = $src$$Register;
6524 Register d = $dst$$Register;
6525 if (s != d) {
6526 __ movq(d, s);
6527 }
6528 __ decode_heap_oop(d);
6529 %}
6530 ins_pipe(ialu_reg_long);
6531 %}
6532
6533 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6534 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6535 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6536 match(Set dst (DecodeN src));
6537 effect(KILL cr);
6538 format %{ "decode_heap_oop_not_null $dst,$src" %}
6539 ins_encode %{
6540 Register s = $src$$Register;
6541 Register d = $dst$$Register;
6542 if (s != d) {
6543 __ decode_heap_oop_not_null(d, s);
6544 } else {
6545 __ decode_heap_oop_not_null(d);
6546 }
6547 %}
6548 ins_pipe(ialu_reg_long);
6549 %}
6550
6551 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6552 match(Set dst (EncodePKlass src));
6553 effect(KILL cr);
6554 format %{ "encode_klass_not_null $dst,$src" %}
6555 ins_encode %{
6556 __ encode_klass_not_null($dst$$Register, $src$$Register);
6557 %}
6558 ins_pipe(ialu_reg_long);
6559 %}
6560
6561 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6562 match(Set dst (DecodeNKlass src));
6563 effect(KILL cr);
6564 format %{ "decode_klass_not_null $dst,$src" %}
6565 ins_encode %{
6566 Register s = $src$$Register;
6567 Register d = $dst$$Register;
6568 if (s != d) {
6569 __ decode_klass_not_null(d, s);
6570 } else {
6571 __ decode_klass_not_null(d);
6572 }
6573 %}
6574 ins_pipe(ialu_reg_long);
6575 %}
6576
6577
6578 //----------Conditional Move---------------------------------------------------
6579 // Jump
6580 // dummy instruction for generating temp registers
6581 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6582 match(Jump (LShiftL switch_val shift));
6583 ins_cost(350);
6584 predicate(false);
6585 effect(TEMP dest);
6586
6587 format %{ "leaq $dest, [$constantaddress]\n\t"
6588 "jmp [$dest + $switch_val << $shift]\n\t" %}
6589 ins_encode %{
6590 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6591 // to do that and the compiler is using that register as one it can allocate.
6592 // So we build it all by hand.
6593 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6594 // ArrayAddress dispatch(table, index);
6595 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6596 __ lea($dest$$Register, $constantaddress);
6597 __ jmp(dispatch);
6598 %}
6599 ins_pipe(pipe_jmp);
6600 %}
6601
6602 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6603 match(Jump (AddL (LShiftL switch_val shift) offset));
6604 ins_cost(350);
6605 effect(TEMP dest);
6606
6607 format %{ "leaq $dest, [$constantaddress]\n\t"
6608 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6609 ins_encode %{
6610 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6611 // to do that and the compiler is using that register as one it can allocate.
6612 // So we build it all by hand.
6613 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6614 // ArrayAddress dispatch(table, index);
6615 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6616 __ lea($dest$$Register, $constantaddress);
6617 __ jmp(dispatch);
6618 %}
6619 ins_pipe(pipe_jmp);
6620 %}
6621
6622 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6623 match(Jump switch_val);
6624 ins_cost(350);
6625 effect(TEMP dest);
6626
6627 format %{ "leaq $dest, [$constantaddress]\n\t"
6628 "jmp [$dest + $switch_val]\n\t" %}
6629 ins_encode %{
6630 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6631 // to do that and the compiler is using that register as one it can allocate.
6632 // So we build it all by hand.
6633 // Address index(noreg, switch_reg, Address::times_1);
6634 // ArrayAddress dispatch(table, index);
6635 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6636 __ lea($dest$$Register, $constantaddress);
6637 __ jmp(dispatch);
6638 %}
6639 ins_pipe(pipe_jmp);
6640 %}
6641
6642 // Conditional move
6643 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6644 %{
6645 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6646
6647 ins_cost(200); // XXX
6648 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6649 opcode(0x0F, 0x40);
6650 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6651 ins_pipe(pipe_cmov_reg);
6652 %}
6653
6654 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6655 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6656
6657 ins_cost(200); // XXX
6658 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6659 opcode(0x0F, 0x40);
6660 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6661 ins_pipe(pipe_cmov_reg);
6662 %}
6663
6664 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6665 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6666 ins_cost(200);
6667 expand %{
6668 cmovI_regU(cop, cr, dst, src);
6669 %}
6670 %}
6671
6672 // Conditional move
6673 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6674 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6675
6676 ins_cost(250); // XXX
6677 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6678 opcode(0x0F, 0x40);
6679 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6680 ins_pipe(pipe_cmov_mem);
6681 %}
6682
6683 // Conditional move
6684 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6685 %{
6686 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6687
6688 ins_cost(250); // XXX
6689 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6690 opcode(0x0F, 0x40);
6691 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6692 ins_pipe(pipe_cmov_mem);
6693 %}
6694
6695 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6696 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6697 ins_cost(250);
6698 expand %{
6699 cmovI_memU(cop, cr, dst, src);
6700 %}
6701 %}
6702
6703 // Conditional move
6704 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6705 %{
6706 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6707
6708 ins_cost(200); // XXX
6709 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6710 opcode(0x0F, 0x40);
6711 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6712 ins_pipe(pipe_cmov_reg);
6713 %}
6714
6715 // Conditional move
6716 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6717 %{
6718 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6719
6720 ins_cost(200); // XXX
6721 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6722 opcode(0x0F, 0x40);
6723 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6724 ins_pipe(pipe_cmov_reg);
6725 %}
6726
6727 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6728 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6729 ins_cost(200);
6730 expand %{
6731 cmovN_regU(cop, cr, dst, src);
6732 %}
6733 %}
6734
6735 // Conditional move
6736 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6737 %{
6738 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6739
6740 ins_cost(200); // XXX
6741 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6742 opcode(0x0F, 0x40);
6743 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6744 ins_pipe(pipe_cmov_reg); // XXX
6745 %}
6746
6747 // Conditional move
6748 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6749 %{
6750 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6751
6752 ins_cost(200); // XXX
6753 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6754 opcode(0x0F, 0x40);
6755 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6756 ins_pipe(pipe_cmov_reg); // XXX
6757 %}
6758
6759 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6760 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6761 ins_cost(200);
6762 expand %{
6763 cmovP_regU(cop, cr, dst, src);
6764 %}
6765 %}
6766
6767 // DISABLED: Requires the ADLC to emit a bottom_type call that
6768 // correctly meets the two pointer arguments; one is an incoming
6769 // register but the other is a memory operand. ALSO appears to
6770 // be buggy with implicit null checks.
6771 //
6772 //// Conditional move
6773 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6774 //%{
6775 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6776 // ins_cost(250);
6777 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6778 // opcode(0x0F,0x40);
6779 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6780 // ins_pipe( pipe_cmov_mem );
6781 //%}
6782 //
6783 //// Conditional move
6784 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6785 //%{
6786 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6787 // ins_cost(250);
6788 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6789 // opcode(0x0F,0x40);
6790 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6791 // ins_pipe( pipe_cmov_mem );
6792 //%}
6793
6794 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6795 %{
6796 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6797
6798 ins_cost(200); // XXX
6799 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6800 opcode(0x0F, 0x40);
6801 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6802 ins_pipe(pipe_cmov_reg); // XXX
6803 %}
6804
6805 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6806 %{
6807 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6808
6809 ins_cost(200); // XXX
6810 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6811 opcode(0x0F, 0x40);
6812 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6813 ins_pipe(pipe_cmov_mem); // XXX
6814 %}
6815
6816 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6817 %{
6818 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6819
6820 ins_cost(200); // XXX
6821 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6822 opcode(0x0F, 0x40);
6823 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6824 ins_pipe(pipe_cmov_reg); // XXX
6825 %}
6826
6827 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6828 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6829 ins_cost(200);
6830 expand %{
6831 cmovL_regU(cop, cr, dst, src);
6832 %}
6833 %}
6834
6835 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6836 %{
6837 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6838
6839 ins_cost(200); // XXX
6840 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6841 opcode(0x0F, 0x40);
6842 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6843 ins_pipe(pipe_cmov_mem); // XXX
6844 %}
6845
6846 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6847 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6848 ins_cost(200);
6849 expand %{
6850 cmovL_memU(cop, cr, dst, src);
6851 %}
6852 %}
6853
6854 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6855 %{
6856 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6857
6858 ins_cost(200); // XXX
6859 format %{ "jn$cop skip\t# signed cmove float\n\t"
6860 "movss $dst, $src\n"
6861 "skip:" %}
6862 ins_encode %{
6863 Label Lskip;
6864 // Invert sense of branch from sense of CMOV
6865 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6866 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6867 __ bind(Lskip);
6868 %}
6869 ins_pipe(pipe_slow);
6870 %}
6871
6872 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6873 // %{
6874 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6875
6876 // ins_cost(200); // XXX
6877 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6878 // "movss $dst, $src\n"
6879 // "skip:" %}
6880 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6881 // ins_pipe(pipe_slow);
6882 // %}
6883
6884 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6885 %{
6886 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6887
6888 ins_cost(200); // XXX
6889 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6890 "movss $dst, $src\n"
6891 "skip:" %}
6892 ins_encode %{
6893 Label Lskip;
6894 // Invert sense of branch from sense of CMOV
6895 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6896 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6897 __ bind(Lskip);
6898 %}
6899 ins_pipe(pipe_slow);
6900 %}
6901
6902 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6903 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6904 ins_cost(200);
6905 expand %{
6906 cmovF_regU(cop, cr, dst, src);
6907 %}
6908 %}
6909
6910 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6911 %{
6912 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6913
6914 ins_cost(200); // XXX
6915 format %{ "jn$cop skip\t# signed cmove double\n\t"
6916 "movsd $dst, $src\n"
6917 "skip:" %}
6918 ins_encode %{
6919 Label Lskip;
6920 // Invert sense of branch from sense of CMOV
6921 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6922 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6923 __ bind(Lskip);
6924 %}
6925 ins_pipe(pipe_slow);
6926 %}
6927
6928 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6929 %{
6930 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6931
6932 ins_cost(200); // XXX
6933 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6934 "movsd $dst, $src\n"
6935 "skip:" %}
6936 ins_encode %{
6937 Label Lskip;
6938 // Invert sense of branch from sense of CMOV
6939 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6940 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6941 __ bind(Lskip);
6942 %}
6943 ins_pipe(pipe_slow);
6944 %}
6945
6946 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6947 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6948 ins_cost(200);
6949 expand %{
6950 cmovD_regU(cop, cr, dst, src);
6951 %}
6952 %}
6953
6954 //----------Arithmetic Instructions--------------------------------------------
6955 //----------Addition Instructions----------------------------------------------
6956
6957 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6958 %{
6959 match(Set dst (AddI dst src));
6960 effect(KILL cr);
6961
6962 format %{ "addl $dst, $src\t# int" %}
6963 opcode(0x03);
6964 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6965 ins_pipe(ialu_reg_reg);
6966 %}
6967
6968 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6969 %{
6970 match(Set dst (AddI dst src));
6971 effect(KILL cr);
6972
6973 format %{ "addl $dst, $src\t# int" %}
6974 opcode(0x81, 0x00); /* /0 id */
6975 ins_encode(OpcSErm(dst, src), Con8or32(src));
6976 ins_pipe( ialu_reg );
6977 %}
6978
6979 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6980 %{
6981 match(Set dst (AddI dst (LoadI src)));
6982 effect(KILL cr);
6983
6984 ins_cost(125); // XXX
6985 format %{ "addl $dst, $src\t# int" %}
6986 opcode(0x03);
6987 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6988 ins_pipe(ialu_reg_mem);
6989 %}
6990
6991 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6992 %{
6993 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6994 effect(KILL cr);
6995
6996 ins_cost(150); // XXX
6997 format %{ "addl $dst, $src\t# int" %}
6998 opcode(0x01); /* Opcode 01 /r */
6999 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7000 ins_pipe(ialu_mem_reg);
7001 %}
7002
7003 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7004 %{
7005 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7006 effect(KILL cr);
7007
7008 ins_cost(125); // XXX
7009 format %{ "addl $dst, $src\t# int" %}
7010 opcode(0x81); /* Opcode 81 /0 id */
7011 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7012 ins_pipe(ialu_mem_imm);
7013 %}
7014
7015 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7016 %{
7017 predicate(UseIncDec);
7018 match(Set dst (AddI dst src));
7019 effect(KILL cr);
7020
7021 format %{ "incl $dst\t# int" %}
7022 opcode(0xFF, 0x00); // FF /0
7023 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7024 ins_pipe(ialu_reg);
7025 %}
7026
7027 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7028 %{
7029 predicate(UseIncDec);
7030 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7031 effect(KILL cr);
7032
7033 ins_cost(125); // XXX
7034 format %{ "incl $dst\t# int" %}
7035 opcode(0xFF); /* Opcode FF /0 */
7036 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7037 ins_pipe(ialu_mem_imm);
7038 %}
7039
7040 // XXX why does that use AddI
7041 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7042 %{
7043 predicate(UseIncDec);
7044 match(Set dst (AddI dst src));
7045 effect(KILL cr);
7046
7047 format %{ "decl $dst\t# int" %}
7048 opcode(0xFF, 0x01); // FF /1
7049 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7050 ins_pipe(ialu_reg);
7051 %}
7052
7053 // XXX why does that use AddI
7054 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7055 %{
7056 predicate(UseIncDec);
7057 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7058 effect(KILL cr);
7059
7060 ins_cost(125); // XXX
7061 format %{ "decl $dst\t# int" %}
7062 opcode(0xFF); /* Opcode FF /1 */
7063 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7064 ins_pipe(ialu_mem_imm);
7065 %}
7066
7067 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7068 %{
7069 match(Set dst (AddI src0 src1));
7070
7071 ins_cost(110);
7072 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7073 opcode(0x8D); /* 0x8D /r */
7074 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7075 ins_pipe(ialu_reg_reg);
7076 %}
7077
7078 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7079 %{
7080 match(Set dst (AddL dst src));
7081 effect(KILL cr);
7082
7083 format %{ "addq $dst, $src\t# long" %}
7084 opcode(0x03);
7085 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7086 ins_pipe(ialu_reg_reg);
7087 %}
7088
7089 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7090 %{
7091 match(Set dst (AddL dst src));
7092 effect(KILL cr);
7093
7094 format %{ "addq $dst, $src\t# long" %}
7095 opcode(0x81, 0x00); /* /0 id */
7096 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7097 ins_pipe( ialu_reg );
7098 %}
7099
7100 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7101 %{
7102 match(Set dst (AddL dst (LoadL src)));
7103 effect(KILL cr);
7104
7105 ins_cost(125); // XXX
7106 format %{ "addq $dst, $src\t# long" %}
7107 opcode(0x03);
7108 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7109 ins_pipe(ialu_reg_mem);
7110 %}
7111
7112 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7113 %{
7114 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7115 effect(KILL cr);
7116
7117 ins_cost(150); // XXX
7118 format %{ "addq $dst, $src\t# long" %}
7119 opcode(0x01); /* Opcode 01 /r */
7120 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7121 ins_pipe(ialu_mem_reg);
7122 %}
7123
7124 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7125 %{
7126 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7127 effect(KILL cr);
7128
7129 ins_cost(125); // XXX
7130 format %{ "addq $dst, $src\t# long" %}
7131 opcode(0x81); /* Opcode 81 /0 id */
7132 ins_encode(REX_mem_wide(dst),
7133 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7134 ins_pipe(ialu_mem_imm);
7135 %}
7136
7137 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7138 %{
7139 predicate(UseIncDec);
7140 match(Set dst (AddL dst src));
7141 effect(KILL cr);
7142
7143 format %{ "incq $dst\t# long" %}
7144 opcode(0xFF, 0x00); // FF /0
7145 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7146 ins_pipe(ialu_reg);
7147 %}
7148
7149 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7150 %{
7151 predicate(UseIncDec);
7152 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7153 effect(KILL cr);
7154
7155 ins_cost(125); // XXX
7156 format %{ "incq $dst\t# long" %}
7157 opcode(0xFF); /* Opcode FF /0 */
7158 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7159 ins_pipe(ialu_mem_imm);
7160 %}
7161
7162 // XXX why does that use AddL
7163 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7164 %{
7165 predicate(UseIncDec);
7166 match(Set dst (AddL dst src));
7167 effect(KILL cr);
7168
7169 format %{ "decq $dst\t# long" %}
7170 opcode(0xFF, 0x01); // FF /1
7171 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7172 ins_pipe(ialu_reg);
7173 %}
7174
7175 // XXX why does that use AddL
7176 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7177 %{
7178 predicate(UseIncDec);
7179 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7180 effect(KILL cr);
7181
7182 ins_cost(125); // XXX
7183 format %{ "decq $dst\t# long" %}
7184 opcode(0xFF); /* Opcode FF /1 */
7185 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7186 ins_pipe(ialu_mem_imm);
7187 %}
7188
7189 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7190 %{
7191 match(Set dst (AddL src0 src1));
7192
7193 ins_cost(110);
7194 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7195 opcode(0x8D); /* 0x8D /r */
7196 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7197 ins_pipe(ialu_reg_reg);
7198 %}
7199
7200 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7201 %{
7202 match(Set dst (AddP dst src));
7203 effect(KILL cr);
7204
7205 format %{ "addq $dst, $src\t# ptr" %}
7206 opcode(0x03);
7207 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7208 ins_pipe(ialu_reg_reg);
7209 %}
7210
7211 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7212 %{
7213 match(Set dst (AddP dst src));
7214 effect(KILL cr);
7215
7216 format %{ "addq $dst, $src\t# ptr" %}
7217 opcode(0x81, 0x00); /* /0 id */
7218 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7219 ins_pipe( ialu_reg );
7220 %}
7221
7222 // XXX addP mem ops ????
7223
7224 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7225 %{
7226 match(Set dst (AddP src0 src1));
7227
7228 ins_cost(110);
7229 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7230 opcode(0x8D); /* 0x8D /r */
7231 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7232 ins_pipe(ialu_reg_reg);
7233 %}
7234
7235 instruct checkCastPP(rRegP dst)
7236 %{
7237 match(Set dst (CheckCastPP dst));
7238
7239 size(0);
7240 format %{ "# checkcastPP of $dst" %}
7241 ins_encode(/* empty encoding */);
7242 ins_pipe(empty);
7243 %}
7244
7245 instruct castPP(rRegP dst)
7246 %{
7247 match(Set dst (CastPP dst));
7248
7249 size(0);
7250 format %{ "# castPP of $dst" %}
7251 ins_encode(/* empty encoding */);
7252 ins_pipe(empty);
7253 %}
7254
7255 instruct castII(rRegI dst)
7256 %{
7257 match(Set dst (CastII dst));
7258
7259 size(0);
7260 format %{ "# castII of $dst" %}
7261 ins_encode(/* empty encoding */);
7262 ins_cost(0);
7263 ins_pipe(empty);
7264 %}
7265
7266 // LoadP-locked same as a regular LoadP when used with compare-swap
7267 instruct loadPLocked(rRegP dst, memory mem)
7268 %{
7269 match(Set dst (LoadPLocked mem));
7270
7271 ins_cost(125); // XXX
7272 format %{ "movq $dst, $mem\t# ptr locked" %}
7273 opcode(0x8B);
7274 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7275 ins_pipe(ialu_reg_mem); // XXX
7276 %}
7277
7278 // Conditional-store of the updated heap-top.
7279 // Used during allocation of the shared heap.
7280 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7281
7282 instruct storePConditional(memory heap_top_ptr,
7283 rax_RegP oldval, rRegP newval,
7284 rFlagsReg cr)
7285 %{
7286 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7287
7288 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7289 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7290 opcode(0x0F, 0xB1);
7291 ins_encode(lock_prefix,
7292 REX_reg_mem_wide(newval, heap_top_ptr),
7293 OpcP, OpcS,
7294 reg_mem(newval, heap_top_ptr));
7295 ins_pipe(pipe_cmpxchg);
7296 %}
7297
7298 // Conditional-store of an int value.
7299 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7300 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7301 %{
7302 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7303 effect(KILL oldval);
7304
7305 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7306 opcode(0x0F, 0xB1);
7307 ins_encode(lock_prefix,
7308 REX_reg_mem(newval, mem),
7309 OpcP, OpcS,
7310 reg_mem(newval, mem));
7311 ins_pipe(pipe_cmpxchg);
7312 %}
7313
7314 // Conditional-store of a long value.
7315 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7316 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7317 %{
7318 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7319 effect(KILL oldval);
7320
7321 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7322 opcode(0x0F, 0xB1);
7323 ins_encode(lock_prefix,
7324 REX_reg_mem_wide(newval, mem),
7325 OpcP, OpcS,
7326 reg_mem(newval, mem));
7327 ins_pipe(pipe_cmpxchg);
7328 %}
7329
7330
7331 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7332 instruct compareAndSwapP(rRegI res,
7333 memory mem_ptr,
7334 rax_RegP oldval, rRegP newval,
7335 rFlagsReg cr)
7336 %{
7337 predicate(VM_Version::supports_cx8());
7338 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7339 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7340 effect(KILL cr, KILL oldval);
7341
7342 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7343 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7344 "sete $res\n\t"
7345 "movzbl $res, $res" %}
7346 opcode(0x0F, 0xB1);
7347 ins_encode(lock_prefix,
7348 REX_reg_mem_wide(newval, mem_ptr),
7349 OpcP, OpcS,
7350 reg_mem(newval, mem_ptr),
7351 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7352 REX_reg_breg(res, res), // movzbl
7353 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7354 ins_pipe( pipe_cmpxchg );
7355 %}
7356
7357 instruct compareAndSwapL(rRegI res,
7358 memory mem_ptr,
7359 rax_RegL oldval, rRegL newval,
7360 rFlagsReg cr)
7361 %{
7362 predicate(VM_Version::supports_cx8());
7363 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7364 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7365 effect(KILL cr, KILL oldval);
7366
7367 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7368 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7369 "sete $res\n\t"
7370 "movzbl $res, $res" %}
7371 opcode(0x0F, 0xB1);
7372 ins_encode(lock_prefix,
7373 REX_reg_mem_wide(newval, mem_ptr),
7374 OpcP, OpcS,
7375 reg_mem(newval, mem_ptr),
7376 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7377 REX_reg_breg(res, res), // movzbl
7378 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7379 ins_pipe( pipe_cmpxchg );
7380 %}
7381
7382 instruct compareAndSwapI(rRegI res,
7383 memory mem_ptr,
7384 rax_RegI oldval, rRegI newval,
7385 rFlagsReg cr)
7386 %{
7387 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7388 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7389 effect(KILL cr, KILL oldval);
7390
7391 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7392 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7393 "sete $res\n\t"
7394 "movzbl $res, $res" %}
7395 opcode(0x0F, 0xB1);
7396 ins_encode(lock_prefix,
7397 REX_reg_mem(newval, mem_ptr),
7398 OpcP, OpcS,
7399 reg_mem(newval, mem_ptr),
7400 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7401 REX_reg_breg(res, res), // movzbl
7402 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7403 ins_pipe( pipe_cmpxchg );
7404 %}
7405
7406 instruct compareAndSwapB(rRegI res,
7407 memory mem_ptr,
7408 rax_RegI oldval, rRegI newval,
7409 rFlagsReg cr)
7410 %{
7411 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7412 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7413 effect(KILL cr, KILL oldval);
7414
7415 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7416 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7417 "sete $res\n\t"
7418 "movzbl $res, $res" %}
7419 opcode(0x0F, 0xB0);
7420 ins_encode(lock_prefix,
7421 REX_breg_mem(newval, mem_ptr),
7422 OpcP, OpcS,
7423 reg_mem(newval, mem_ptr),
7424 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7425 REX_reg_breg(res, res), // movzbl
7426 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7427 ins_pipe( pipe_cmpxchg );
7428 %}
7429
7430 instruct compareAndSwapS(rRegI res,
7431 memory mem_ptr,
7432 rax_RegI oldval, rRegI newval,
7433 rFlagsReg cr)
7434 %{
7435 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7436 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7437 effect(KILL cr, KILL oldval);
7438
7439 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7440 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7441 "sete $res\n\t"
7442 "movzbl $res, $res" %}
7443 opcode(0x0F, 0xB1);
7444 ins_encode(lock_prefix,
7445 SizePrefix,
7446 REX_reg_mem(newval, mem_ptr),
7447 OpcP, OpcS,
7448 reg_mem(newval, mem_ptr),
7449 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7450 REX_reg_breg(res, res), // movzbl
7451 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7452 ins_pipe( pipe_cmpxchg );
7453 %}
7454
7455 instruct compareAndSwapN(rRegI res,
7456 memory mem_ptr,
7457 rax_RegN oldval, rRegN newval,
7458 rFlagsReg cr) %{
7459 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7460 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7461 effect(KILL cr, KILL oldval);
7462
7463 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7464 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7465 "sete $res\n\t"
7466 "movzbl $res, $res" %}
7467 opcode(0x0F, 0xB1);
7468 ins_encode(lock_prefix,
7469 REX_reg_mem(newval, mem_ptr),
7470 OpcP, OpcS,
7471 reg_mem(newval, mem_ptr),
7472 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7473 REX_reg_breg(res, res), // movzbl
7474 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7475 ins_pipe( pipe_cmpxchg );
7476 %}
7477
7478 instruct compareAndExchangeB(
7479 memory mem_ptr,
7480 rax_RegI oldval, rRegI newval,
7481 rFlagsReg cr)
7482 %{
7483 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7484 effect(KILL cr);
7485
7486 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7487 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7488 opcode(0x0F, 0xB0);
7489 ins_encode(lock_prefix,
7490 REX_breg_mem(newval, mem_ptr),
7491 OpcP, OpcS,
7492 reg_mem(newval, mem_ptr) // lock cmpxchg
7493 );
7494 ins_pipe( pipe_cmpxchg );
7495 %}
7496
7497 instruct compareAndExchangeS(
7498 memory mem_ptr,
7499 rax_RegI oldval, rRegI newval,
7500 rFlagsReg cr)
7501 %{
7502 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7503 effect(KILL cr);
7504
7505 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7506 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7507 opcode(0x0F, 0xB1);
7508 ins_encode(lock_prefix,
7509 SizePrefix,
7510 REX_reg_mem(newval, mem_ptr),
7511 OpcP, OpcS,
7512 reg_mem(newval, mem_ptr) // lock cmpxchg
7513 );
7514 ins_pipe( pipe_cmpxchg );
7515 %}
7516
7517 instruct compareAndExchangeI(
7518 memory mem_ptr,
7519 rax_RegI oldval, rRegI newval,
7520 rFlagsReg cr)
7521 %{
7522 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7523 effect(KILL cr);
7524
7525 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7526 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7527 opcode(0x0F, 0xB1);
7528 ins_encode(lock_prefix,
7529 REX_reg_mem(newval, mem_ptr),
7530 OpcP, OpcS,
7531 reg_mem(newval, mem_ptr) // lock cmpxchg
7532 );
7533 ins_pipe( pipe_cmpxchg );
7534 %}
7535
7536 instruct compareAndExchangeL(
7537 memory mem_ptr,
7538 rax_RegL oldval, rRegL newval,
7539 rFlagsReg cr)
7540 %{
7541 predicate(VM_Version::supports_cx8());
7542 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7543 effect(KILL cr);
7544
7545 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7546 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7547 opcode(0x0F, 0xB1);
7548 ins_encode(lock_prefix,
7549 REX_reg_mem_wide(newval, mem_ptr),
7550 OpcP, OpcS,
7551 reg_mem(newval, mem_ptr) // lock cmpxchg
7552 );
7553 ins_pipe( pipe_cmpxchg );
7554 %}
7555
7556 instruct compareAndExchangeN(
7557 memory mem_ptr,
7558 rax_RegN oldval, rRegN newval,
7559 rFlagsReg cr) %{
7560 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7561 effect(KILL cr);
7562
7563 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7564 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7565 opcode(0x0F, 0xB1);
7566 ins_encode(lock_prefix,
7567 REX_reg_mem(newval, mem_ptr),
7568 OpcP, OpcS,
7569 reg_mem(newval, mem_ptr) // lock cmpxchg
7570 );
7571 ins_pipe( pipe_cmpxchg );
7572 %}
7573
7574 instruct compareAndExchangeP(
7575 memory mem_ptr,
7576 rax_RegP oldval, rRegP newval,
7577 rFlagsReg cr)
7578 %{
7579 predicate(VM_Version::supports_cx8());
7580 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7581 effect(KILL cr);
7582
7583 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7584 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7585 opcode(0x0F, 0xB1);
7586 ins_encode(lock_prefix,
7587 REX_reg_mem_wide(newval, mem_ptr),
7588 OpcP, OpcS,
7589 reg_mem(newval, mem_ptr) // lock cmpxchg
7590 );
7591 ins_pipe( pipe_cmpxchg );
7592 %}
7593
7594 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7595 predicate(n->as_LoadStore()->result_not_used());
7596 match(Set dummy (GetAndAddB mem add));
7597 effect(KILL cr);
7598 format %{ "ADDB [$mem],$add" %}
7599 ins_encode %{
7600 if (os::is_MP()) { __ lock(); }
7601 __ addb($mem$$Address, $add$$constant);
7602 %}
7603 ins_pipe( pipe_cmpxchg );
7604 %}
7605
7606 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7607 match(Set newval (GetAndAddB mem newval));
7608 effect(KILL cr);
7609 format %{ "XADDB [$mem],$newval" %}
7610 ins_encode %{
7611 if (os::is_MP()) { __ lock(); }
7612 __ xaddb($mem$$Address, $newval$$Register);
7613 %}
7614 ins_pipe( pipe_cmpxchg );
7615 %}
7616
7617 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7618 predicate(n->as_LoadStore()->result_not_used());
7619 match(Set dummy (GetAndAddS mem add));
7620 effect(KILL cr);
7621 format %{ "ADDW [$mem],$add" %}
7622 ins_encode %{
7623 if (os::is_MP()) { __ lock(); }
7624 __ addw($mem$$Address, $add$$constant);
7625 %}
7626 ins_pipe( pipe_cmpxchg );
7627 %}
7628
7629 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7630 match(Set newval (GetAndAddS mem newval));
7631 effect(KILL cr);
7632 format %{ "XADDW [$mem],$newval" %}
7633 ins_encode %{
7634 if (os::is_MP()) { __ lock(); }
7635 __ xaddw($mem$$Address, $newval$$Register);
7636 %}
7637 ins_pipe( pipe_cmpxchg );
7638 %}
7639
7640 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7641 predicate(n->as_LoadStore()->result_not_used());
7642 match(Set dummy (GetAndAddI mem add));
7643 effect(KILL cr);
7644 format %{ "ADDL [$mem],$add" %}
7645 ins_encode %{
7646 if (os::is_MP()) { __ lock(); }
7647 __ addl($mem$$Address, $add$$constant);
7648 %}
7649 ins_pipe( pipe_cmpxchg );
7650 %}
7651
7652 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7653 match(Set newval (GetAndAddI mem newval));
7654 effect(KILL cr);
7655 format %{ "XADDL [$mem],$newval" %}
7656 ins_encode %{
7657 if (os::is_MP()) { __ lock(); }
7658 __ xaddl($mem$$Address, $newval$$Register);
7659 %}
7660 ins_pipe( pipe_cmpxchg );
7661 %}
7662
7663 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7664 predicate(n->as_LoadStore()->result_not_used());
7665 match(Set dummy (GetAndAddL mem add));
7666 effect(KILL cr);
7667 format %{ "ADDQ [$mem],$add" %}
7668 ins_encode %{
7669 if (os::is_MP()) { __ lock(); }
7670 __ addq($mem$$Address, $add$$constant);
7671 %}
7672 ins_pipe( pipe_cmpxchg );
7673 %}
7674
7675 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7676 match(Set newval (GetAndAddL mem newval));
7677 effect(KILL cr);
7678 format %{ "XADDQ [$mem],$newval" %}
7679 ins_encode %{
7680 if (os::is_MP()) { __ lock(); }
7681 __ xaddq($mem$$Address, $newval$$Register);
7682 %}
7683 ins_pipe( pipe_cmpxchg );
7684 %}
7685
7686 instruct xchgB( memory mem, rRegI newval) %{
7687 match(Set newval (GetAndSetB mem newval));
7688 format %{ "XCHGB $newval,[$mem]" %}
7689 ins_encode %{
7690 __ xchgb($newval$$Register, $mem$$Address);
7691 %}
7692 ins_pipe( pipe_cmpxchg );
7693 %}
7694
7695 instruct xchgS( memory mem, rRegI newval) %{
7696 match(Set newval (GetAndSetS mem newval));
7697 format %{ "XCHGW $newval,[$mem]" %}
7698 ins_encode %{
7699 __ xchgw($newval$$Register, $mem$$Address);
7700 %}
7701 ins_pipe( pipe_cmpxchg );
7702 %}
7703
7704 instruct xchgI( memory mem, rRegI newval) %{
7705 match(Set newval (GetAndSetI mem newval));
7706 format %{ "XCHGL $newval,[$mem]" %}
7707 ins_encode %{
7708 __ xchgl($newval$$Register, $mem$$Address);
7709 %}
7710 ins_pipe( pipe_cmpxchg );
7711 %}
7712
7713 instruct xchgL( memory mem, rRegL newval) %{
7714 match(Set newval (GetAndSetL mem newval));
7715 format %{ "XCHGL $newval,[$mem]" %}
7716 ins_encode %{
7717 __ xchgq($newval$$Register, $mem$$Address);
7718 %}
7719 ins_pipe( pipe_cmpxchg );
7720 %}
7721
7722 instruct xchgP( memory mem, rRegP newval) %{
7723 match(Set newval (GetAndSetP mem newval));
7724 format %{ "XCHGQ $newval,[$mem]" %}
7725 ins_encode %{
7726 __ xchgq($newval$$Register, $mem$$Address);
7727 %}
7728 ins_pipe( pipe_cmpxchg );
7729 %}
7730
7731 instruct xchgN( memory mem, rRegN newval) %{
7732 match(Set newval (GetAndSetN mem newval));
7733 format %{ "XCHGL $newval,$mem]" %}
7734 ins_encode %{
7735 __ xchgl($newval$$Register, $mem$$Address);
7736 %}
7737 ins_pipe( pipe_cmpxchg );
7738 %}
7739
7740 //----------Subtraction Instructions-------------------------------------------
7741
7742 // Integer Subtraction Instructions
7743 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7744 %{
7745 match(Set dst (SubI dst src));
7746 effect(KILL cr);
7747
7748 format %{ "subl $dst, $src\t# int" %}
7749 opcode(0x2B);
7750 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7751 ins_pipe(ialu_reg_reg);
7752 %}
7753
7754 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7755 %{
7756 match(Set dst (SubI dst src));
7757 effect(KILL cr);
7758
7759 format %{ "subl $dst, $src\t# int" %}
7760 opcode(0x81, 0x05); /* Opcode 81 /5 */
7761 ins_encode(OpcSErm(dst, src), Con8or32(src));
7762 ins_pipe(ialu_reg);
7763 %}
7764
7765 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7766 %{
7767 match(Set dst (SubI dst (LoadI src)));
7768 effect(KILL cr);
7769
7770 ins_cost(125);
7771 format %{ "subl $dst, $src\t# int" %}
7772 opcode(0x2B);
7773 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7774 ins_pipe(ialu_reg_mem);
7775 %}
7776
7777 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7778 %{
7779 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7780 effect(KILL cr);
7781
7782 ins_cost(150);
7783 format %{ "subl $dst, $src\t# int" %}
7784 opcode(0x29); /* Opcode 29 /r */
7785 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7786 ins_pipe(ialu_mem_reg);
7787 %}
7788
7789 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7790 %{
7791 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7792 effect(KILL cr);
7793
7794 ins_cost(125); // XXX
7795 format %{ "subl $dst, $src\t# int" %}
7796 opcode(0x81); /* Opcode 81 /5 id */
7797 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7798 ins_pipe(ialu_mem_imm);
7799 %}
7800
7801 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7802 %{
7803 match(Set dst (SubL dst src));
7804 effect(KILL cr);
7805
7806 format %{ "subq $dst, $src\t# long" %}
7807 opcode(0x2B);
7808 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7809 ins_pipe(ialu_reg_reg);
7810 %}
7811
7812 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7813 %{
7814 match(Set dst (SubL dst src));
7815 effect(KILL cr);
7816
7817 format %{ "subq $dst, $src\t# long" %}
7818 opcode(0x81, 0x05); /* Opcode 81 /5 */
7819 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7820 ins_pipe(ialu_reg);
7821 %}
7822
7823 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7824 %{
7825 match(Set dst (SubL dst (LoadL src)));
7826 effect(KILL cr);
7827
7828 ins_cost(125);
7829 format %{ "subq $dst, $src\t# long" %}
7830 opcode(0x2B);
7831 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7832 ins_pipe(ialu_reg_mem);
7833 %}
7834
7835 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7836 %{
7837 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7838 effect(KILL cr);
7839
7840 ins_cost(150);
7841 format %{ "subq $dst, $src\t# long" %}
7842 opcode(0x29); /* Opcode 29 /r */
7843 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7844 ins_pipe(ialu_mem_reg);
7845 %}
7846
7847 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7848 %{
7849 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7850 effect(KILL cr);
7851
7852 ins_cost(125); // XXX
7853 format %{ "subq $dst, $src\t# long" %}
7854 opcode(0x81); /* Opcode 81 /5 id */
7855 ins_encode(REX_mem_wide(dst),
7856 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7857 ins_pipe(ialu_mem_imm);
7858 %}
7859
7860 // Subtract from a pointer
7861 // XXX hmpf???
7862 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7863 %{
7864 match(Set dst (AddP dst (SubI zero src)));
7865 effect(KILL cr);
7866
7867 format %{ "subq $dst, $src\t# ptr - int" %}
7868 opcode(0x2B);
7869 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7870 ins_pipe(ialu_reg_reg);
7871 %}
7872
7873 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7874 %{
7875 match(Set dst (SubI zero dst));
7876 effect(KILL cr);
7877
7878 format %{ "negl $dst\t# int" %}
7879 opcode(0xF7, 0x03); // Opcode F7 /3
7880 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7881 ins_pipe(ialu_reg);
7882 %}
7883
7884 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7885 %{
7886 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7887 effect(KILL cr);
7888
7889 format %{ "negl $dst\t# int" %}
7890 opcode(0xF7, 0x03); // Opcode F7 /3
7891 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7892 ins_pipe(ialu_reg);
7893 %}
7894
7895 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7896 %{
7897 match(Set dst (SubL zero dst));
7898 effect(KILL cr);
7899
7900 format %{ "negq $dst\t# long" %}
7901 opcode(0xF7, 0x03); // Opcode F7 /3
7902 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7903 ins_pipe(ialu_reg);
7904 %}
7905
7906 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7907 %{
7908 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7909 effect(KILL cr);
7910
7911 format %{ "negq $dst\t# long" %}
7912 opcode(0xF7, 0x03); // Opcode F7 /3
7913 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7914 ins_pipe(ialu_reg);
7915 %}
7916
7917 //----------Multiplication/Division Instructions-------------------------------
7918 // Integer Multiplication Instructions
7919 // Multiply Register
7920
7921 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7922 %{
7923 match(Set dst (MulI dst src));
7924 effect(KILL cr);
7925
7926 ins_cost(300);
7927 format %{ "imull $dst, $src\t# int" %}
7928 opcode(0x0F, 0xAF);
7929 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7930 ins_pipe(ialu_reg_reg_alu0);
7931 %}
7932
7933 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7934 %{
7935 match(Set dst (MulI src imm));
7936 effect(KILL cr);
7937
7938 ins_cost(300);
7939 format %{ "imull $dst, $src, $imm\t# int" %}
7940 opcode(0x69); /* 69 /r id */
7941 ins_encode(REX_reg_reg(dst, src),
7942 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7943 ins_pipe(ialu_reg_reg_alu0);
7944 %}
7945
7946 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7947 %{
7948 match(Set dst (MulI dst (LoadI src)));
7949 effect(KILL cr);
7950
7951 ins_cost(350);
7952 format %{ "imull $dst, $src\t# int" %}
7953 opcode(0x0F, 0xAF);
7954 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7955 ins_pipe(ialu_reg_mem_alu0);
7956 %}
7957
7958 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7959 %{
7960 match(Set dst (MulI (LoadI src) imm));
7961 effect(KILL cr);
7962
7963 ins_cost(300);
7964 format %{ "imull $dst, $src, $imm\t# int" %}
7965 opcode(0x69); /* 69 /r id */
7966 ins_encode(REX_reg_mem(dst, src),
7967 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7968 ins_pipe(ialu_reg_mem_alu0);
7969 %}
7970
7971 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7972 %{
7973 match(Set dst (MulL dst src));
7974 effect(KILL cr);
7975
7976 ins_cost(300);
7977 format %{ "imulq $dst, $src\t# long" %}
7978 opcode(0x0F, 0xAF);
7979 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7980 ins_pipe(ialu_reg_reg_alu0);
7981 %}
7982
7983 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7984 %{
7985 match(Set dst (MulL src imm));
7986 effect(KILL cr);
7987
7988 ins_cost(300);
7989 format %{ "imulq $dst, $src, $imm\t# long" %}
7990 opcode(0x69); /* 69 /r id */
7991 ins_encode(REX_reg_reg_wide(dst, src),
7992 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7993 ins_pipe(ialu_reg_reg_alu0);
7994 %}
7995
7996 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7997 %{
7998 match(Set dst (MulL dst (LoadL src)));
7999 effect(KILL cr);
8000
8001 ins_cost(350);
8002 format %{ "imulq $dst, $src\t# long" %}
8003 opcode(0x0F, 0xAF);
8004 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8005 ins_pipe(ialu_reg_mem_alu0);
8006 %}
8007
8008 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8009 %{
8010 match(Set dst (MulL (LoadL src) imm));
8011 effect(KILL cr);
8012
8013 ins_cost(300);
8014 format %{ "imulq $dst, $src, $imm\t# long" %}
8015 opcode(0x69); /* 69 /r id */
8016 ins_encode(REX_reg_mem_wide(dst, src),
8017 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8018 ins_pipe(ialu_reg_mem_alu0);
8019 %}
8020
8021 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8022 %{
8023 match(Set dst (MulHiL src rax));
8024 effect(USE_KILL rax, KILL cr);
8025
8026 ins_cost(300);
8027 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8028 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8029 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8030 ins_pipe(ialu_reg_reg_alu0);
8031 %}
8032
8033 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8034 rFlagsReg cr)
8035 %{
8036 match(Set rax (DivI rax div));
8037 effect(KILL rdx, KILL cr);
8038
8039 ins_cost(30*100+10*100); // XXX
8040 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8041 "jne,s normal\n\t"
8042 "xorl rdx, rdx\n\t"
8043 "cmpl $div, -1\n\t"
8044 "je,s done\n"
8045 "normal: cdql\n\t"
8046 "idivl $div\n"
8047 "done:" %}
8048 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8049 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8050 ins_pipe(ialu_reg_reg_alu0);
8051 %}
8052
8053 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8054 rFlagsReg cr)
8055 %{
8056 match(Set rax (DivL rax div));
8057 effect(KILL rdx, KILL cr);
8058
8059 ins_cost(30*100+10*100); // XXX
8060 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8061 "cmpq rax, rdx\n\t"
8062 "jne,s normal\n\t"
8063 "xorl rdx, rdx\n\t"
8064 "cmpq $div, -1\n\t"
8065 "je,s done\n"
8066 "normal: cdqq\n\t"
8067 "idivq $div\n"
8068 "done:" %}
8069 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8070 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8071 ins_pipe(ialu_reg_reg_alu0);
8072 %}
8073
8074 // Integer DIVMOD with Register, both quotient and mod results
8075 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8076 rFlagsReg cr)
8077 %{
8078 match(DivModI rax div);
8079 effect(KILL cr);
8080
8081 ins_cost(30*100+10*100); // XXX
8082 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8083 "jne,s normal\n\t"
8084 "xorl rdx, rdx\n\t"
8085 "cmpl $div, -1\n\t"
8086 "je,s done\n"
8087 "normal: cdql\n\t"
8088 "idivl $div\n"
8089 "done:" %}
8090 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8091 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8092 ins_pipe(pipe_slow);
8093 %}
8094
8095 // Long DIVMOD with Register, both quotient and mod results
8096 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8097 rFlagsReg cr)
8098 %{
8099 match(DivModL rax div);
8100 effect(KILL cr);
8101
8102 ins_cost(30*100+10*100); // XXX
8103 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8104 "cmpq rax, rdx\n\t"
8105 "jne,s normal\n\t"
8106 "xorl rdx, rdx\n\t"
8107 "cmpq $div, -1\n\t"
8108 "je,s done\n"
8109 "normal: cdqq\n\t"
8110 "idivq $div\n"
8111 "done:" %}
8112 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8113 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8114 ins_pipe(pipe_slow);
8115 %}
8116
8117 //----------- DivL-By-Constant-Expansions--------------------------------------
8118 // DivI cases are handled by the compiler
8119
8120 // Magic constant, reciprocal of 10
8121 instruct loadConL_0x6666666666666667(rRegL dst)
8122 %{
8123 effect(DEF dst);
8124
8125 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8126 ins_encode(load_immL(dst, 0x6666666666666667));
8127 ins_pipe(ialu_reg);
8128 %}
8129
8130 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8131 %{
8132 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8133
8134 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8135 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8136 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8137 ins_pipe(ialu_reg_reg_alu0);
8138 %}
8139
8140 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8141 %{
8142 effect(USE_DEF dst, KILL cr);
8143
8144 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8145 opcode(0xC1, 0x7); /* C1 /7 ib */
8146 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8147 ins_pipe(ialu_reg);
8148 %}
8149
8150 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8151 %{
8152 effect(USE_DEF dst, KILL cr);
8153
8154 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8155 opcode(0xC1, 0x7); /* C1 /7 ib */
8156 ins_encode(reg_opc_imm_wide(dst, 0x2));
8157 ins_pipe(ialu_reg);
8158 %}
8159
8160 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8161 %{
8162 match(Set dst (DivL src div));
8163
8164 ins_cost((5+8)*100);
8165 expand %{
8166 rax_RegL rax; // Killed temp
8167 rFlagsReg cr; // Killed
8168 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8169 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8170 sarL_rReg_63(src, cr); // sarq src, 63
8171 sarL_rReg_2(dst, cr); // sarq rdx, 2
8172 subL_rReg(dst, src, cr); // subl rdx, src
8173 %}
8174 %}
8175
8176 //-----------------------------------------------------------------------------
8177
8178 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8179 rFlagsReg cr)
8180 %{
8181 match(Set rdx (ModI rax div));
8182 effect(KILL rax, KILL cr);
8183
8184 ins_cost(300); // XXX
8185 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8186 "jne,s normal\n\t"
8187 "xorl rdx, rdx\n\t"
8188 "cmpl $div, -1\n\t"
8189 "je,s done\n"
8190 "normal: cdql\n\t"
8191 "idivl $div\n"
8192 "done:" %}
8193 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8194 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8195 ins_pipe(ialu_reg_reg_alu0);
8196 %}
8197
8198 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8199 rFlagsReg cr)
8200 %{
8201 match(Set rdx (ModL rax div));
8202 effect(KILL rax, KILL cr);
8203
8204 ins_cost(300); // XXX
8205 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8206 "cmpq rax, rdx\n\t"
8207 "jne,s normal\n\t"
8208 "xorl rdx, rdx\n\t"
8209 "cmpq $div, -1\n\t"
8210 "je,s done\n"
8211 "normal: cdqq\n\t"
8212 "idivq $div\n"
8213 "done:" %}
8214 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8215 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8216 ins_pipe(ialu_reg_reg_alu0);
8217 %}
8218
8219 // Integer Shift Instructions
8220 // Shift Left by one
8221 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8222 %{
8223 match(Set dst (LShiftI dst shift));
8224 effect(KILL cr);
8225
8226 format %{ "sall $dst, $shift" %}
8227 opcode(0xD1, 0x4); /* D1 /4 */
8228 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8229 ins_pipe(ialu_reg);
8230 %}
8231
8232 // Shift Left by one
8233 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8234 %{
8235 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8236 effect(KILL cr);
8237
8238 format %{ "sall $dst, $shift\t" %}
8239 opcode(0xD1, 0x4); /* D1 /4 */
8240 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8241 ins_pipe(ialu_mem_imm);
8242 %}
8243
8244 // Shift Left by 8-bit immediate
8245 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8246 %{
8247 match(Set dst (LShiftI dst shift));
8248 effect(KILL cr);
8249
8250 format %{ "sall $dst, $shift" %}
8251 opcode(0xC1, 0x4); /* C1 /4 ib */
8252 ins_encode(reg_opc_imm(dst, shift));
8253 ins_pipe(ialu_reg);
8254 %}
8255
8256 // Shift Left by 8-bit immediate
8257 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8258 %{
8259 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8260 effect(KILL cr);
8261
8262 format %{ "sall $dst, $shift" %}
8263 opcode(0xC1, 0x4); /* C1 /4 ib */
8264 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8265 ins_pipe(ialu_mem_imm);
8266 %}
8267
8268 // Shift Left by variable
8269 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8270 %{
8271 match(Set dst (LShiftI dst shift));
8272 effect(KILL cr);
8273
8274 format %{ "sall $dst, $shift" %}
8275 opcode(0xD3, 0x4); /* D3 /4 */
8276 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8277 ins_pipe(ialu_reg_reg);
8278 %}
8279
8280 // Shift Left by variable
8281 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8282 %{
8283 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8284 effect(KILL cr);
8285
8286 format %{ "sall $dst, $shift" %}
8287 opcode(0xD3, 0x4); /* D3 /4 */
8288 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8289 ins_pipe(ialu_mem_reg);
8290 %}
8291
8292 // Arithmetic shift right by one
8293 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8294 %{
8295 match(Set dst (RShiftI dst shift));
8296 effect(KILL cr);
8297
8298 format %{ "sarl $dst, $shift" %}
8299 opcode(0xD1, 0x7); /* D1 /7 */
8300 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8301 ins_pipe(ialu_reg);
8302 %}
8303
8304 // Arithmetic shift right by one
8305 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8306 %{
8307 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8308 effect(KILL cr);
8309
8310 format %{ "sarl $dst, $shift" %}
8311 opcode(0xD1, 0x7); /* D1 /7 */
8312 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8313 ins_pipe(ialu_mem_imm);
8314 %}
8315
8316 // Arithmetic Shift Right by 8-bit immediate
8317 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8318 %{
8319 match(Set dst (RShiftI dst shift));
8320 effect(KILL cr);
8321
8322 format %{ "sarl $dst, $shift" %}
8323 opcode(0xC1, 0x7); /* C1 /7 ib */
8324 ins_encode(reg_opc_imm(dst, shift));
8325 ins_pipe(ialu_mem_imm);
8326 %}
8327
8328 // Arithmetic Shift Right by 8-bit immediate
8329 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8330 %{
8331 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8332 effect(KILL cr);
8333
8334 format %{ "sarl $dst, $shift" %}
8335 opcode(0xC1, 0x7); /* C1 /7 ib */
8336 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8337 ins_pipe(ialu_mem_imm);
8338 %}
8339
8340 // Arithmetic Shift Right by variable
8341 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8342 %{
8343 match(Set dst (RShiftI dst shift));
8344 effect(KILL cr);
8345
8346 format %{ "sarl $dst, $shift" %}
8347 opcode(0xD3, 0x7); /* D3 /7 */
8348 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8349 ins_pipe(ialu_reg_reg);
8350 %}
8351
8352 // Arithmetic Shift Right by variable
8353 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8354 %{
8355 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8356 effect(KILL cr);
8357
8358 format %{ "sarl $dst, $shift" %}
8359 opcode(0xD3, 0x7); /* D3 /7 */
8360 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8361 ins_pipe(ialu_mem_reg);
8362 %}
8363
8364 // Logical shift right by one
8365 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8366 %{
8367 match(Set dst (URShiftI dst shift));
8368 effect(KILL cr);
8369
8370 format %{ "shrl $dst, $shift" %}
8371 opcode(0xD1, 0x5); /* D1 /5 */
8372 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8373 ins_pipe(ialu_reg);
8374 %}
8375
8376 // Logical shift right by one
8377 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8378 %{
8379 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8380 effect(KILL cr);
8381
8382 format %{ "shrl $dst, $shift" %}
8383 opcode(0xD1, 0x5); /* D1 /5 */
8384 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8385 ins_pipe(ialu_mem_imm);
8386 %}
8387
8388 // Logical Shift Right by 8-bit immediate
8389 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8390 %{
8391 match(Set dst (URShiftI dst shift));
8392 effect(KILL cr);
8393
8394 format %{ "shrl $dst, $shift" %}
8395 opcode(0xC1, 0x5); /* C1 /5 ib */
8396 ins_encode(reg_opc_imm(dst, shift));
8397 ins_pipe(ialu_reg);
8398 %}
8399
8400 // Logical Shift Right by 8-bit immediate
8401 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8402 %{
8403 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8404 effect(KILL cr);
8405
8406 format %{ "shrl $dst, $shift" %}
8407 opcode(0xC1, 0x5); /* C1 /5 ib */
8408 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8409 ins_pipe(ialu_mem_imm);
8410 %}
8411
8412 // Logical Shift Right by variable
8413 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8414 %{
8415 match(Set dst (URShiftI dst shift));
8416 effect(KILL cr);
8417
8418 format %{ "shrl $dst, $shift" %}
8419 opcode(0xD3, 0x5); /* D3 /5 */
8420 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8421 ins_pipe(ialu_reg_reg);
8422 %}
8423
8424 // Logical Shift Right by variable
8425 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8426 %{
8427 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8428 effect(KILL cr);
8429
8430 format %{ "shrl $dst, $shift" %}
8431 opcode(0xD3, 0x5); /* D3 /5 */
8432 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8433 ins_pipe(ialu_mem_reg);
8434 %}
8435
8436 // Long Shift Instructions
8437 // Shift Left by one
8438 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8439 %{
8440 match(Set dst (LShiftL dst shift));
8441 effect(KILL cr);
8442
8443 format %{ "salq $dst, $shift" %}
8444 opcode(0xD1, 0x4); /* D1 /4 */
8445 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8446 ins_pipe(ialu_reg);
8447 %}
8448
8449 // Shift Left by one
8450 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8451 %{
8452 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8453 effect(KILL cr);
8454
8455 format %{ "salq $dst, $shift" %}
8456 opcode(0xD1, 0x4); /* D1 /4 */
8457 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8458 ins_pipe(ialu_mem_imm);
8459 %}
8460
8461 // Shift Left by 8-bit immediate
8462 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8463 %{
8464 match(Set dst (LShiftL dst shift));
8465 effect(KILL cr);
8466
8467 format %{ "salq $dst, $shift" %}
8468 opcode(0xC1, 0x4); /* C1 /4 ib */
8469 ins_encode(reg_opc_imm_wide(dst, shift));
8470 ins_pipe(ialu_reg);
8471 %}
8472
8473 // Shift Left by 8-bit immediate
8474 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8475 %{
8476 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8477 effect(KILL cr);
8478
8479 format %{ "salq $dst, $shift" %}
8480 opcode(0xC1, 0x4); /* C1 /4 ib */
8481 ins_encode(REX_mem_wide(dst), OpcP,
8482 RM_opc_mem(secondary, dst), Con8or32(shift));
8483 ins_pipe(ialu_mem_imm);
8484 %}
8485
8486 // Shift Left by variable
8487 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8488 %{
8489 match(Set dst (LShiftL dst shift));
8490 effect(KILL cr);
8491
8492 format %{ "salq $dst, $shift" %}
8493 opcode(0xD3, 0x4); /* D3 /4 */
8494 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8495 ins_pipe(ialu_reg_reg);
8496 %}
8497
8498 // Shift Left by variable
8499 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8500 %{
8501 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8502 effect(KILL cr);
8503
8504 format %{ "salq $dst, $shift" %}
8505 opcode(0xD3, 0x4); /* D3 /4 */
8506 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8507 ins_pipe(ialu_mem_reg);
8508 %}
8509
8510 // Arithmetic shift right by one
8511 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8512 %{
8513 match(Set dst (RShiftL dst shift));
8514 effect(KILL cr);
8515
8516 format %{ "sarq $dst, $shift" %}
8517 opcode(0xD1, 0x7); /* D1 /7 */
8518 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8519 ins_pipe(ialu_reg);
8520 %}
8521
8522 // Arithmetic shift right by one
8523 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8524 %{
8525 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8526 effect(KILL cr);
8527
8528 format %{ "sarq $dst, $shift" %}
8529 opcode(0xD1, 0x7); /* D1 /7 */
8530 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8531 ins_pipe(ialu_mem_imm);
8532 %}
8533
8534 // Arithmetic Shift Right by 8-bit immediate
8535 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8536 %{
8537 match(Set dst (RShiftL dst shift));
8538 effect(KILL cr);
8539
8540 format %{ "sarq $dst, $shift" %}
8541 opcode(0xC1, 0x7); /* C1 /7 ib */
8542 ins_encode(reg_opc_imm_wide(dst, shift));
8543 ins_pipe(ialu_mem_imm);
8544 %}
8545
8546 // Arithmetic Shift Right by 8-bit immediate
8547 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8548 %{
8549 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8550 effect(KILL cr);
8551
8552 format %{ "sarq $dst, $shift" %}
8553 opcode(0xC1, 0x7); /* C1 /7 ib */
8554 ins_encode(REX_mem_wide(dst), OpcP,
8555 RM_opc_mem(secondary, dst), Con8or32(shift));
8556 ins_pipe(ialu_mem_imm);
8557 %}
8558
8559 // Arithmetic Shift Right by variable
8560 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8561 %{
8562 match(Set dst (RShiftL dst shift));
8563 effect(KILL cr);
8564
8565 format %{ "sarq $dst, $shift" %}
8566 opcode(0xD3, 0x7); /* D3 /7 */
8567 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8568 ins_pipe(ialu_reg_reg);
8569 %}
8570
8571 // Arithmetic Shift Right by variable
8572 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8573 %{
8574 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8575 effect(KILL cr);
8576
8577 format %{ "sarq $dst, $shift" %}
8578 opcode(0xD3, 0x7); /* D3 /7 */
8579 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8580 ins_pipe(ialu_mem_reg);
8581 %}
8582
8583 // Logical shift right by one
8584 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8585 %{
8586 match(Set dst (URShiftL dst shift));
8587 effect(KILL cr);
8588
8589 format %{ "shrq $dst, $shift" %}
8590 opcode(0xD1, 0x5); /* D1 /5 */
8591 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8592 ins_pipe(ialu_reg);
8593 %}
8594
8595 // Logical shift right by one
8596 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8597 %{
8598 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8599 effect(KILL cr);
8600
8601 format %{ "shrq $dst, $shift" %}
8602 opcode(0xD1, 0x5); /* D1 /5 */
8603 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8604 ins_pipe(ialu_mem_imm);
8605 %}
8606
8607 // Logical Shift Right by 8-bit immediate
8608 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8609 %{
8610 match(Set dst (URShiftL dst shift));
8611 effect(KILL cr);
8612
8613 format %{ "shrq $dst, $shift" %}
8614 opcode(0xC1, 0x5); /* C1 /5 ib */
8615 ins_encode(reg_opc_imm_wide(dst, shift));
8616 ins_pipe(ialu_reg);
8617 %}
8618
8619
8620 // Logical Shift Right by 8-bit immediate
8621 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8622 %{
8623 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8624 effect(KILL cr);
8625
8626 format %{ "shrq $dst, $shift" %}
8627 opcode(0xC1, 0x5); /* C1 /5 ib */
8628 ins_encode(REX_mem_wide(dst), OpcP,
8629 RM_opc_mem(secondary, dst), Con8or32(shift));
8630 ins_pipe(ialu_mem_imm);
8631 %}
8632
8633 // Logical Shift Right by variable
8634 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8635 %{
8636 match(Set dst (URShiftL dst shift));
8637 effect(KILL cr);
8638
8639 format %{ "shrq $dst, $shift" %}
8640 opcode(0xD3, 0x5); /* D3 /5 */
8641 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8642 ins_pipe(ialu_reg_reg);
8643 %}
8644
8645 // Logical Shift Right by variable
8646 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8647 %{
8648 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8649 effect(KILL cr);
8650
8651 format %{ "shrq $dst, $shift" %}
8652 opcode(0xD3, 0x5); /* D3 /5 */
8653 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8654 ins_pipe(ialu_mem_reg);
8655 %}
8656
8657 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8658 // This idiom is used by the compiler for the i2b bytecode.
8659 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8660 %{
8661 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8662
8663 format %{ "movsbl $dst, $src\t# i2b" %}
8664 opcode(0x0F, 0xBE);
8665 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8666 ins_pipe(ialu_reg_reg);
8667 %}
8668
8669 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8670 // This idiom is used by the compiler the i2s bytecode.
8671 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8672 %{
8673 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8674
8675 format %{ "movswl $dst, $src\t# i2s" %}
8676 opcode(0x0F, 0xBF);
8677 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8678 ins_pipe(ialu_reg_reg);
8679 %}
8680
8681 // ROL/ROR instructions
8682
8683 // ROL expand
8684 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8685 effect(KILL cr, USE_DEF dst);
8686
8687 format %{ "roll $dst" %}
8688 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8689 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8690 ins_pipe(ialu_reg);
8691 %}
8692
8693 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8694 effect(USE_DEF dst, USE shift, KILL cr);
8695
8696 format %{ "roll $dst, $shift" %}
8697 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8698 ins_encode( reg_opc_imm(dst, shift) );
8699 ins_pipe(ialu_reg);
8700 %}
8701
8702 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8703 %{
8704 effect(USE_DEF dst, USE shift, KILL cr);
8705
8706 format %{ "roll $dst, $shift" %}
8707 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8708 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8709 ins_pipe(ialu_reg_reg);
8710 %}
8711 // end of ROL expand
8712
8713 // Rotate Left by one
8714 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8715 %{
8716 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8717
8718 expand %{
8719 rolI_rReg_imm1(dst, cr);
8720 %}
8721 %}
8722
8723 // Rotate Left by 8-bit immediate
8724 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8725 %{
8726 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8727 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8728
8729 expand %{
8730 rolI_rReg_imm8(dst, lshift, cr);
8731 %}
8732 %}
8733
8734 // Rotate Left by variable
8735 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8736 %{
8737 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8738
8739 expand %{
8740 rolI_rReg_CL(dst, shift, cr);
8741 %}
8742 %}
8743
8744 // Rotate Left by variable
8745 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8746 %{
8747 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8748
8749 expand %{
8750 rolI_rReg_CL(dst, shift, cr);
8751 %}
8752 %}
8753
8754 // ROR expand
8755 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8756 %{
8757 effect(USE_DEF dst, KILL cr);
8758
8759 format %{ "rorl $dst" %}
8760 opcode(0xD1, 0x1); /* D1 /1 */
8761 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8762 ins_pipe(ialu_reg);
8763 %}
8764
8765 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8766 %{
8767 effect(USE_DEF dst, USE shift, KILL cr);
8768
8769 format %{ "rorl $dst, $shift" %}
8770 opcode(0xC1, 0x1); /* C1 /1 ib */
8771 ins_encode(reg_opc_imm(dst, shift));
8772 ins_pipe(ialu_reg);
8773 %}
8774
8775 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8776 %{
8777 effect(USE_DEF dst, USE shift, KILL cr);
8778
8779 format %{ "rorl $dst, $shift" %}
8780 opcode(0xD3, 0x1); /* D3 /1 */
8781 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8782 ins_pipe(ialu_reg_reg);
8783 %}
8784 // end of ROR expand
8785
8786 // Rotate Right by one
8787 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8788 %{
8789 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8790
8791 expand %{
8792 rorI_rReg_imm1(dst, cr);
8793 %}
8794 %}
8795
8796 // Rotate Right by 8-bit immediate
8797 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8798 %{
8799 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8800 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8801
8802 expand %{
8803 rorI_rReg_imm8(dst, rshift, cr);
8804 %}
8805 %}
8806
8807 // Rotate Right by variable
8808 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8809 %{
8810 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8811
8812 expand %{
8813 rorI_rReg_CL(dst, shift, cr);
8814 %}
8815 %}
8816
8817 // Rotate Right by variable
8818 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8819 %{
8820 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8821
8822 expand %{
8823 rorI_rReg_CL(dst, shift, cr);
8824 %}
8825 %}
8826
8827 // for long rotate
8828 // ROL expand
8829 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8830 effect(USE_DEF dst, KILL cr);
8831
8832 format %{ "rolq $dst" %}
8833 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8834 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8835 ins_pipe(ialu_reg);
8836 %}
8837
8838 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8839 effect(USE_DEF dst, USE shift, KILL cr);
8840
8841 format %{ "rolq $dst, $shift" %}
8842 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8843 ins_encode( reg_opc_imm_wide(dst, shift) );
8844 ins_pipe(ialu_reg);
8845 %}
8846
8847 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8848 %{
8849 effect(USE_DEF dst, USE shift, KILL cr);
8850
8851 format %{ "rolq $dst, $shift" %}
8852 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8853 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8854 ins_pipe(ialu_reg_reg);
8855 %}
8856 // end of ROL expand
8857
8858 // Rotate Left by one
8859 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8860 %{
8861 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8862
8863 expand %{
8864 rolL_rReg_imm1(dst, cr);
8865 %}
8866 %}
8867
8868 // Rotate Left by 8-bit immediate
8869 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8870 %{
8871 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8872 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8873
8874 expand %{
8875 rolL_rReg_imm8(dst, lshift, cr);
8876 %}
8877 %}
8878
8879 // Rotate Left by variable
8880 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8881 %{
8882 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8883
8884 expand %{
8885 rolL_rReg_CL(dst, shift, cr);
8886 %}
8887 %}
8888
8889 // Rotate Left by variable
8890 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8891 %{
8892 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8893
8894 expand %{
8895 rolL_rReg_CL(dst, shift, cr);
8896 %}
8897 %}
8898
8899 // ROR expand
8900 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8901 %{
8902 effect(USE_DEF dst, KILL cr);
8903
8904 format %{ "rorq $dst" %}
8905 opcode(0xD1, 0x1); /* D1 /1 */
8906 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8907 ins_pipe(ialu_reg);
8908 %}
8909
8910 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8911 %{
8912 effect(USE_DEF dst, USE shift, KILL cr);
8913
8914 format %{ "rorq $dst, $shift" %}
8915 opcode(0xC1, 0x1); /* C1 /1 ib */
8916 ins_encode(reg_opc_imm_wide(dst, shift));
8917 ins_pipe(ialu_reg);
8918 %}
8919
8920 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8921 %{
8922 effect(USE_DEF dst, USE shift, KILL cr);
8923
8924 format %{ "rorq $dst, $shift" %}
8925 opcode(0xD3, 0x1); /* D3 /1 */
8926 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8927 ins_pipe(ialu_reg_reg);
8928 %}
8929 // end of ROR expand
8930
8931 // Rotate Right by one
8932 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8933 %{
8934 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8935
8936 expand %{
8937 rorL_rReg_imm1(dst, cr);
8938 %}
8939 %}
8940
8941 // Rotate Right by 8-bit immediate
8942 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8943 %{
8944 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8945 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8946
8947 expand %{
8948 rorL_rReg_imm8(dst, rshift, cr);
8949 %}
8950 %}
8951
8952 // Rotate Right by variable
8953 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8954 %{
8955 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8956
8957 expand %{
8958 rorL_rReg_CL(dst, shift, cr);
8959 %}
8960 %}
8961
8962 // Rotate Right by variable
8963 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8964 %{
8965 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8966
8967 expand %{
8968 rorL_rReg_CL(dst, shift, cr);
8969 %}
8970 %}
8971
8972 // Logical Instructions
8973
8974 // Integer Logical Instructions
8975
8976 // And Instructions
8977 // And Register with Register
8978 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8979 %{
8980 match(Set dst (AndI dst src));
8981 effect(KILL cr);
8982
8983 format %{ "andl $dst, $src\t# int" %}
8984 opcode(0x23);
8985 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8986 ins_pipe(ialu_reg_reg);
8987 %}
8988
8989 // And Register with Immediate 255
8990 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8991 %{
8992 match(Set dst (AndI dst src));
8993
8994 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8995 opcode(0x0F, 0xB6);
8996 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8997 ins_pipe(ialu_reg);
8998 %}
8999
9000 // And Register with Immediate 255 and promote to long
9001 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9002 %{
9003 match(Set dst (ConvI2L (AndI src mask)));
9004
9005 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9006 opcode(0x0F, 0xB6);
9007 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9008 ins_pipe(ialu_reg);
9009 %}
9010
9011 // And Register with Immediate 65535
9012 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9013 %{
9014 match(Set dst (AndI dst src));
9015
9016 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9017 opcode(0x0F, 0xB7);
9018 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9019 ins_pipe(ialu_reg);
9020 %}
9021
9022 // And Register with Immediate 65535 and promote to long
9023 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9024 %{
9025 match(Set dst (ConvI2L (AndI src mask)));
9026
9027 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9028 opcode(0x0F, 0xB7);
9029 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9030 ins_pipe(ialu_reg);
9031 %}
9032
9033 // And Register with Immediate
9034 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9035 %{
9036 match(Set dst (AndI dst src));
9037 effect(KILL cr);
9038
9039 format %{ "andl $dst, $src\t# int" %}
9040 opcode(0x81, 0x04); /* Opcode 81 /4 */
9041 ins_encode(OpcSErm(dst, src), Con8or32(src));
9042 ins_pipe(ialu_reg);
9043 %}
9044
9045 // And Register with Memory
9046 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9047 %{
9048 match(Set dst (AndI dst (LoadI src)));
9049 effect(KILL cr);
9050
9051 ins_cost(125);
9052 format %{ "andl $dst, $src\t# int" %}
9053 opcode(0x23);
9054 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9055 ins_pipe(ialu_reg_mem);
9056 %}
9057
9058 // And Memory with Register
9059 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9060 %{
9061 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9062 effect(KILL cr);
9063
9064 ins_cost(150);
9065 format %{ "andl $dst, $src\t# int" %}
9066 opcode(0x21); /* Opcode 21 /r */
9067 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9068 ins_pipe(ialu_mem_reg);
9069 %}
9070
9071 // And Memory with Immediate
9072 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9073 %{
9074 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9075 effect(KILL cr);
9076
9077 ins_cost(125);
9078 format %{ "andl $dst, $src\t# int" %}
9079 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9080 ins_encode(REX_mem(dst), OpcSE(src),
9081 RM_opc_mem(secondary, dst), Con8or32(src));
9082 ins_pipe(ialu_mem_imm);
9083 %}
9084
9085 // BMI1 instructions
9086 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9087 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9088 predicate(UseBMI1Instructions);
9089 effect(KILL cr);
9090
9091 ins_cost(125);
9092 format %{ "andnl $dst, $src1, $src2" %}
9093
9094 ins_encode %{
9095 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9096 %}
9097 ins_pipe(ialu_reg_mem);
9098 %}
9099
9100 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9101 match(Set dst (AndI (XorI src1 minus_1) src2));
9102 predicate(UseBMI1Instructions);
9103 effect(KILL cr);
9104
9105 format %{ "andnl $dst, $src1, $src2" %}
9106
9107 ins_encode %{
9108 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9109 %}
9110 ins_pipe(ialu_reg);
9111 %}
9112
9113 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9114 match(Set dst (AndI (SubI imm_zero src) src));
9115 predicate(UseBMI1Instructions);
9116 effect(KILL cr);
9117
9118 format %{ "blsil $dst, $src" %}
9119
9120 ins_encode %{
9121 __ blsil($dst$$Register, $src$$Register);
9122 %}
9123 ins_pipe(ialu_reg);
9124 %}
9125
9126 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9127 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9128 predicate(UseBMI1Instructions);
9129 effect(KILL cr);
9130
9131 ins_cost(125);
9132 format %{ "blsil $dst, $src" %}
9133
9134 ins_encode %{
9135 __ blsil($dst$$Register, $src$$Address);
9136 %}
9137 ins_pipe(ialu_reg_mem);
9138 %}
9139
9140 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9141 %{
9142 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9143 predicate(UseBMI1Instructions);
9144 effect(KILL cr);
9145
9146 ins_cost(125);
9147 format %{ "blsmskl $dst, $src" %}
9148
9149 ins_encode %{
9150 __ blsmskl($dst$$Register, $src$$Address);
9151 %}
9152 ins_pipe(ialu_reg_mem);
9153 %}
9154
9155 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9156 %{
9157 match(Set dst (XorI (AddI src minus_1) src));
9158 predicate(UseBMI1Instructions);
9159 effect(KILL cr);
9160
9161 format %{ "blsmskl $dst, $src" %}
9162
9163 ins_encode %{
9164 __ blsmskl($dst$$Register, $src$$Register);
9165 %}
9166
9167 ins_pipe(ialu_reg);
9168 %}
9169
9170 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9171 %{
9172 match(Set dst (AndI (AddI src minus_1) src) );
9173 predicate(UseBMI1Instructions);
9174 effect(KILL cr);
9175
9176 format %{ "blsrl $dst, $src" %}
9177
9178 ins_encode %{
9179 __ blsrl($dst$$Register, $src$$Register);
9180 %}
9181
9182 ins_pipe(ialu_reg_mem);
9183 %}
9184
9185 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9186 %{
9187 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9188 predicate(UseBMI1Instructions);
9189 effect(KILL cr);
9190
9191 ins_cost(125);
9192 format %{ "blsrl $dst, $src" %}
9193
9194 ins_encode %{
9195 __ blsrl($dst$$Register, $src$$Address);
9196 %}
9197
9198 ins_pipe(ialu_reg);
9199 %}
9200
9201 // Or Instructions
9202 // Or Register with Register
9203 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9204 %{
9205 match(Set dst (OrI dst src));
9206 effect(KILL cr);
9207
9208 format %{ "orl $dst, $src\t# int" %}
9209 opcode(0x0B);
9210 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9211 ins_pipe(ialu_reg_reg);
9212 %}
9213
9214 // Or Register with Immediate
9215 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9216 %{
9217 match(Set dst (OrI dst src));
9218 effect(KILL cr);
9219
9220 format %{ "orl $dst, $src\t# int" %}
9221 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9222 ins_encode(OpcSErm(dst, src), Con8or32(src));
9223 ins_pipe(ialu_reg);
9224 %}
9225
9226 // Or Register with Memory
9227 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9228 %{
9229 match(Set dst (OrI dst (LoadI src)));
9230 effect(KILL cr);
9231
9232 ins_cost(125);
9233 format %{ "orl $dst, $src\t# int" %}
9234 opcode(0x0B);
9235 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9236 ins_pipe(ialu_reg_mem);
9237 %}
9238
9239 // Or Memory with Register
9240 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9241 %{
9242 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9243 effect(KILL cr);
9244
9245 ins_cost(150);
9246 format %{ "orl $dst, $src\t# int" %}
9247 opcode(0x09); /* Opcode 09 /r */
9248 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9249 ins_pipe(ialu_mem_reg);
9250 %}
9251
9252 // Or Memory with Immediate
9253 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9254 %{
9255 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9256 effect(KILL cr);
9257
9258 ins_cost(125);
9259 format %{ "orl $dst, $src\t# int" %}
9260 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9261 ins_encode(REX_mem(dst), OpcSE(src),
9262 RM_opc_mem(secondary, dst), Con8or32(src));
9263 ins_pipe(ialu_mem_imm);
9264 %}
9265
9266 // Xor Instructions
9267 // Xor Register with Register
9268 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9269 %{
9270 match(Set dst (XorI dst src));
9271 effect(KILL cr);
9272
9273 format %{ "xorl $dst, $src\t# int" %}
9274 opcode(0x33);
9275 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9276 ins_pipe(ialu_reg_reg);
9277 %}
9278
9279 // Xor Register with Immediate -1
9280 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9281 match(Set dst (XorI dst imm));
9282
9283 format %{ "not $dst" %}
9284 ins_encode %{
9285 __ notl($dst$$Register);
9286 %}
9287 ins_pipe(ialu_reg);
9288 %}
9289
9290 // Xor Register with Immediate
9291 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9292 %{
9293 match(Set dst (XorI dst src));
9294 effect(KILL cr);
9295
9296 format %{ "xorl $dst, $src\t# int" %}
9297 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9298 ins_encode(OpcSErm(dst, src), Con8or32(src));
9299 ins_pipe(ialu_reg);
9300 %}
9301
9302 // Xor Register with Memory
9303 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9304 %{
9305 match(Set dst (XorI dst (LoadI src)));
9306 effect(KILL cr);
9307
9308 ins_cost(125);
9309 format %{ "xorl $dst, $src\t# int" %}
9310 opcode(0x33);
9311 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9312 ins_pipe(ialu_reg_mem);
9313 %}
9314
9315 // Xor Memory with Register
9316 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9317 %{
9318 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9319 effect(KILL cr);
9320
9321 ins_cost(150);
9322 format %{ "xorl $dst, $src\t# int" %}
9323 opcode(0x31); /* Opcode 31 /r */
9324 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9325 ins_pipe(ialu_mem_reg);
9326 %}
9327
9328 // Xor Memory with Immediate
9329 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9330 %{
9331 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9332 effect(KILL cr);
9333
9334 ins_cost(125);
9335 format %{ "xorl $dst, $src\t# int" %}
9336 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9337 ins_encode(REX_mem(dst), OpcSE(src),
9338 RM_opc_mem(secondary, dst), Con8or32(src));
9339 ins_pipe(ialu_mem_imm);
9340 %}
9341
9342
9343 // Long Logical Instructions
9344
9345 // And Instructions
9346 // And Register with Register
9347 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9348 %{
9349 match(Set dst (AndL dst src));
9350 effect(KILL cr);
9351
9352 format %{ "andq $dst, $src\t# long" %}
9353 opcode(0x23);
9354 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9355 ins_pipe(ialu_reg_reg);
9356 %}
9357
9358 // And Register with Immediate 255
9359 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9360 %{
9361 match(Set dst (AndL dst src));
9362
9363 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9364 opcode(0x0F, 0xB6);
9365 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9366 ins_pipe(ialu_reg);
9367 %}
9368
9369 // And Register with Immediate 65535
9370 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9371 %{
9372 match(Set dst (AndL dst src));
9373
9374 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9375 opcode(0x0F, 0xB7);
9376 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9377 ins_pipe(ialu_reg);
9378 %}
9379
9380 // And Register with Immediate
9381 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9382 %{
9383 match(Set dst (AndL dst src));
9384 effect(KILL cr);
9385
9386 format %{ "andq $dst, $src\t# long" %}
9387 opcode(0x81, 0x04); /* Opcode 81 /4 */
9388 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9389 ins_pipe(ialu_reg);
9390 %}
9391
9392 // And Register with Memory
9393 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9394 %{
9395 match(Set dst (AndL dst (LoadL src)));
9396 effect(KILL cr);
9397
9398 ins_cost(125);
9399 format %{ "andq $dst, $src\t# long" %}
9400 opcode(0x23);
9401 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9402 ins_pipe(ialu_reg_mem);
9403 %}
9404
9405 // And Memory with Register
9406 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9407 %{
9408 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9409 effect(KILL cr);
9410
9411 ins_cost(150);
9412 format %{ "andq $dst, $src\t# long" %}
9413 opcode(0x21); /* Opcode 21 /r */
9414 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9415 ins_pipe(ialu_mem_reg);
9416 %}
9417
9418 // And Memory with Immediate
9419 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9420 %{
9421 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9422 effect(KILL cr);
9423
9424 ins_cost(125);
9425 format %{ "andq $dst, $src\t# long" %}
9426 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9427 ins_encode(REX_mem_wide(dst), OpcSE(src),
9428 RM_opc_mem(secondary, dst), Con8or32(src));
9429 ins_pipe(ialu_mem_imm);
9430 %}
9431
9432 // BMI1 instructions
9433 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9434 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9435 predicate(UseBMI1Instructions);
9436 effect(KILL cr);
9437
9438 ins_cost(125);
9439 format %{ "andnq $dst, $src1, $src2" %}
9440
9441 ins_encode %{
9442 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9443 %}
9444 ins_pipe(ialu_reg_mem);
9445 %}
9446
9447 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9448 match(Set dst (AndL (XorL src1 minus_1) src2));
9449 predicate(UseBMI1Instructions);
9450 effect(KILL cr);
9451
9452 format %{ "andnq $dst, $src1, $src2" %}
9453
9454 ins_encode %{
9455 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9456 %}
9457 ins_pipe(ialu_reg_mem);
9458 %}
9459
9460 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9461 match(Set dst (AndL (SubL imm_zero src) src));
9462 predicate(UseBMI1Instructions);
9463 effect(KILL cr);
9464
9465 format %{ "blsiq $dst, $src" %}
9466
9467 ins_encode %{
9468 __ blsiq($dst$$Register, $src$$Register);
9469 %}
9470 ins_pipe(ialu_reg);
9471 %}
9472
9473 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9474 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9475 predicate(UseBMI1Instructions);
9476 effect(KILL cr);
9477
9478 ins_cost(125);
9479 format %{ "blsiq $dst, $src" %}
9480
9481 ins_encode %{
9482 __ blsiq($dst$$Register, $src$$Address);
9483 %}
9484 ins_pipe(ialu_reg_mem);
9485 %}
9486
9487 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9488 %{
9489 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9490 predicate(UseBMI1Instructions);
9491 effect(KILL cr);
9492
9493 ins_cost(125);
9494 format %{ "blsmskq $dst, $src" %}
9495
9496 ins_encode %{
9497 __ blsmskq($dst$$Register, $src$$Address);
9498 %}
9499 ins_pipe(ialu_reg_mem);
9500 %}
9501
9502 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9503 %{
9504 match(Set dst (XorL (AddL src minus_1) src));
9505 predicate(UseBMI1Instructions);
9506 effect(KILL cr);
9507
9508 format %{ "blsmskq $dst, $src" %}
9509
9510 ins_encode %{
9511 __ blsmskq($dst$$Register, $src$$Register);
9512 %}
9513
9514 ins_pipe(ialu_reg);
9515 %}
9516
9517 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9518 %{
9519 match(Set dst (AndL (AddL src minus_1) src) );
9520 predicate(UseBMI1Instructions);
9521 effect(KILL cr);
9522
9523 format %{ "blsrq $dst, $src" %}
9524
9525 ins_encode %{
9526 __ blsrq($dst$$Register, $src$$Register);
9527 %}
9528
9529 ins_pipe(ialu_reg);
9530 %}
9531
9532 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9533 %{
9534 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9535 predicate(UseBMI1Instructions);
9536 effect(KILL cr);
9537
9538 ins_cost(125);
9539 format %{ "blsrq $dst, $src" %}
9540
9541 ins_encode %{
9542 __ blsrq($dst$$Register, $src$$Address);
9543 %}
9544
9545 ins_pipe(ialu_reg);
9546 %}
9547
9548 // Or Instructions
9549 // Or Register with Register
9550 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9551 %{
9552 match(Set dst (OrL dst src));
9553 effect(KILL cr);
9554
9555 format %{ "orq $dst, $src\t# long" %}
9556 opcode(0x0B);
9557 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9558 ins_pipe(ialu_reg_reg);
9559 %}
9560
9561 // Use any_RegP to match R15 (TLS register) without spilling.
9562 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9563 match(Set dst (OrL dst (CastP2X src)));
9564 effect(KILL cr);
9565
9566 format %{ "orq $dst, $src\t# long" %}
9567 opcode(0x0B);
9568 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9569 ins_pipe(ialu_reg_reg);
9570 %}
9571
9572
9573 // Or Register with Immediate
9574 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9575 %{
9576 match(Set dst (OrL dst src));
9577 effect(KILL cr);
9578
9579 format %{ "orq $dst, $src\t# long" %}
9580 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9581 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9582 ins_pipe(ialu_reg);
9583 %}
9584
9585 // Or Register with Memory
9586 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9587 %{
9588 match(Set dst (OrL dst (LoadL src)));
9589 effect(KILL cr);
9590
9591 ins_cost(125);
9592 format %{ "orq $dst, $src\t# long" %}
9593 opcode(0x0B);
9594 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9595 ins_pipe(ialu_reg_mem);
9596 %}
9597
9598 // Or Memory with Register
9599 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9600 %{
9601 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9602 effect(KILL cr);
9603
9604 ins_cost(150);
9605 format %{ "orq $dst, $src\t# long" %}
9606 opcode(0x09); /* Opcode 09 /r */
9607 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9608 ins_pipe(ialu_mem_reg);
9609 %}
9610
9611 // Or Memory with Immediate
9612 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9613 %{
9614 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9615 effect(KILL cr);
9616
9617 ins_cost(125);
9618 format %{ "orq $dst, $src\t# long" %}
9619 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9620 ins_encode(REX_mem_wide(dst), OpcSE(src),
9621 RM_opc_mem(secondary, dst), Con8or32(src));
9622 ins_pipe(ialu_mem_imm);
9623 %}
9624
9625 // Xor Instructions
9626 // Xor Register with Register
9627 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9628 %{
9629 match(Set dst (XorL dst src));
9630 effect(KILL cr);
9631
9632 format %{ "xorq $dst, $src\t# long" %}
9633 opcode(0x33);
9634 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9635 ins_pipe(ialu_reg_reg);
9636 %}
9637
9638 // Xor Register with Immediate -1
9639 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9640 match(Set dst (XorL dst imm));
9641
9642 format %{ "notq $dst" %}
9643 ins_encode %{
9644 __ notq($dst$$Register);
9645 %}
9646 ins_pipe(ialu_reg);
9647 %}
9648
9649 // Xor Register with Immediate
9650 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9651 %{
9652 match(Set dst (XorL dst src));
9653 effect(KILL cr);
9654
9655 format %{ "xorq $dst, $src\t# long" %}
9656 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9657 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9658 ins_pipe(ialu_reg);
9659 %}
9660
9661 // Xor Register with Memory
9662 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9663 %{
9664 match(Set dst (XorL dst (LoadL src)));
9665 effect(KILL cr);
9666
9667 ins_cost(125);
9668 format %{ "xorq $dst, $src\t# long" %}
9669 opcode(0x33);
9670 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9671 ins_pipe(ialu_reg_mem);
9672 %}
9673
9674 // Xor Memory with Register
9675 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9676 %{
9677 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9678 effect(KILL cr);
9679
9680 ins_cost(150);
9681 format %{ "xorq $dst, $src\t# long" %}
9682 opcode(0x31); /* Opcode 31 /r */
9683 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9684 ins_pipe(ialu_mem_reg);
9685 %}
9686
9687 // Xor Memory with Immediate
9688 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9689 %{
9690 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9691 effect(KILL cr);
9692
9693 ins_cost(125);
9694 format %{ "xorq $dst, $src\t# long" %}
9695 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9696 ins_encode(REX_mem_wide(dst), OpcSE(src),
9697 RM_opc_mem(secondary, dst), Con8or32(src));
9698 ins_pipe(ialu_mem_imm);
9699 %}
9700
9701 // Convert Int to Boolean
9702 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9703 %{
9704 match(Set dst (Conv2B src));
9705 effect(KILL cr);
9706
9707 format %{ "testl $src, $src\t# ci2b\n\t"
9708 "setnz $dst\n\t"
9709 "movzbl $dst, $dst" %}
9710 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9711 setNZ_reg(dst),
9712 REX_reg_breg(dst, dst), // movzbl
9713 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9714 ins_pipe(pipe_slow); // XXX
9715 %}
9716
9717 // Convert Pointer to Boolean
9718 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9719 %{
9720 match(Set dst (Conv2B src));
9721 effect(KILL cr);
9722
9723 format %{ "testq $src, $src\t# cp2b\n\t"
9724 "setnz $dst\n\t"
9725 "movzbl $dst, $dst" %}
9726 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9727 setNZ_reg(dst),
9728 REX_reg_breg(dst, dst), // movzbl
9729 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9730 ins_pipe(pipe_slow); // XXX
9731 %}
9732
9733 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9734 %{
9735 match(Set dst (CmpLTMask p q));
9736 effect(KILL cr);
9737
9738 ins_cost(400);
9739 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9740 "setlt $dst\n\t"
9741 "movzbl $dst, $dst\n\t"
9742 "negl $dst" %}
9743 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9744 setLT_reg(dst),
9745 REX_reg_breg(dst, dst), // movzbl
9746 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9747 neg_reg(dst));
9748 ins_pipe(pipe_slow);
9749 %}
9750
9751 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9752 %{
9753 match(Set dst (CmpLTMask dst zero));
9754 effect(KILL cr);
9755
9756 ins_cost(100);
9757 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9758 ins_encode %{
9759 __ sarl($dst$$Register, 31);
9760 %}
9761 ins_pipe(ialu_reg);
9762 %}
9763
9764 /* Better to save a register than avoid a branch */
9765 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9766 %{
9767 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9768 effect(KILL cr);
9769 ins_cost(300);
9770 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9771 "jge done\n\t"
9772 "addl $p,$y\n"
9773 "done: " %}
9774 ins_encode %{
9775 Register Rp = $p$$Register;
9776 Register Rq = $q$$Register;
9777 Register Ry = $y$$Register;
9778 Label done;
9779 __ subl(Rp, Rq);
9780 __ jccb(Assembler::greaterEqual, done);
9781 __ addl(Rp, Ry);
9782 __ bind(done);
9783 %}
9784 ins_pipe(pipe_cmplt);
9785 %}
9786
9787 /* Better to save a register than avoid a branch */
9788 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9789 %{
9790 match(Set y (AndI (CmpLTMask p q) y));
9791 effect(KILL cr);
9792
9793 ins_cost(300);
9794
9795 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9796 "jlt done\n\t"
9797 "xorl $y, $y\n"
9798 "done: " %}
9799 ins_encode %{
9800 Register Rp = $p$$Register;
9801 Register Rq = $q$$Register;
9802 Register Ry = $y$$Register;
9803 Label done;
9804 __ cmpl(Rp, Rq);
9805 __ jccb(Assembler::less, done);
9806 __ xorl(Ry, Ry);
9807 __ bind(done);
9808 %}
9809 ins_pipe(pipe_cmplt);
9810 %}
9811
9812
9813 //---------- FP Instructions------------------------------------------------
9814
9815 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9816 %{
9817 match(Set cr (CmpF src1 src2));
9818
9819 ins_cost(145);
9820 format %{ "ucomiss $src1, $src2\n\t"
9821 "jnp,s exit\n\t"
9822 "pushfq\t# saw NaN, set CF\n\t"
9823 "andq [rsp], #0xffffff2b\n\t"
9824 "popfq\n"
9825 "exit:" %}
9826 ins_encode %{
9827 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9828 emit_cmpfp_fixup(_masm);
9829 %}
9830 ins_pipe(pipe_slow);
9831 %}
9832
9833 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9834 match(Set cr (CmpF src1 src2));
9835
9836 ins_cost(100);
9837 format %{ "ucomiss $src1, $src2" %}
9838 ins_encode %{
9839 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9840 %}
9841 ins_pipe(pipe_slow);
9842 %}
9843
9844 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9845 %{
9846 match(Set cr (CmpF src1 (LoadF src2)));
9847
9848 ins_cost(145);
9849 format %{ "ucomiss $src1, $src2\n\t"
9850 "jnp,s exit\n\t"
9851 "pushfq\t# saw NaN, set CF\n\t"
9852 "andq [rsp], #0xffffff2b\n\t"
9853 "popfq\n"
9854 "exit:" %}
9855 ins_encode %{
9856 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9857 emit_cmpfp_fixup(_masm);
9858 %}
9859 ins_pipe(pipe_slow);
9860 %}
9861
9862 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9863 match(Set cr (CmpF src1 (LoadF src2)));
9864
9865 ins_cost(100);
9866 format %{ "ucomiss $src1, $src2" %}
9867 ins_encode %{
9868 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9869 %}
9870 ins_pipe(pipe_slow);
9871 %}
9872
9873 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9874 match(Set cr (CmpF src con));
9875
9876 ins_cost(145);
9877 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9878 "jnp,s exit\n\t"
9879 "pushfq\t# saw NaN, set CF\n\t"
9880 "andq [rsp], #0xffffff2b\n\t"
9881 "popfq\n"
9882 "exit:" %}
9883 ins_encode %{
9884 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9885 emit_cmpfp_fixup(_masm);
9886 %}
9887 ins_pipe(pipe_slow);
9888 %}
9889
9890 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9891 match(Set cr (CmpF src con));
9892 ins_cost(100);
9893 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9894 ins_encode %{
9895 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9896 %}
9897 ins_pipe(pipe_slow);
9898 %}
9899
9900 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9901 %{
9902 match(Set cr (CmpD src1 src2));
9903
9904 ins_cost(145);
9905 format %{ "ucomisd $src1, $src2\n\t"
9906 "jnp,s exit\n\t"
9907 "pushfq\t# saw NaN, set CF\n\t"
9908 "andq [rsp], #0xffffff2b\n\t"
9909 "popfq\n"
9910 "exit:" %}
9911 ins_encode %{
9912 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9913 emit_cmpfp_fixup(_masm);
9914 %}
9915 ins_pipe(pipe_slow);
9916 %}
9917
9918 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9919 match(Set cr (CmpD src1 src2));
9920
9921 ins_cost(100);
9922 format %{ "ucomisd $src1, $src2 test" %}
9923 ins_encode %{
9924 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9925 %}
9926 ins_pipe(pipe_slow);
9927 %}
9928
9929 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9930 %{
9931 match(Set cr (CmpD src1 (LoadD src2)));
9932
9933 ins_cost(145);
9934 format %{ "ucomisd $src1, $src2\n\t"
9935 "jnp,s exit\n\t"
9936 "pushfq\t# saw NaN, set CF\n\t"
9937 "andq [rsp], #0xffffff2b\n\t"
9938 "popfq\n"
9939 "exit:" %}
9940 ins_encode %{
9941 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9942 emit_cmpfp_fixup(_masm);
9943 %}
9944 ins_pipe(pipe_slow);
9945 %}
9946
9947 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9948 match(Set cr (CmpD src1 (LoadD src2)));
9949
9950 ins_cost(100);
9951 format %{ "ucomisd $src1, $src2" %}
9952 ins_encode %{
9953 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9954 %}
9955 ins_pipe(pipe_slow);
9956 %}
9957
9958 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9959 match(Set cr (CmpD src con));
9960
9961 ins_cost(145);
9962 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9963 "jnp,s exit\n\t"
9964 "pushfq\t# saw NaN, set CF\n\t"
9965 "andq [rsp], #0xffffff2b\n\t"
9966 "popfq\n"
9967 "exit:" %}
9968 ins_encode %{
9969 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9970 emit_cmpfp_fixup(_masm);
9971 %}
9972 ins_pipe(pipe_slow);
9973 %}
9974
9975 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9976 match(Set cr (CmpD src con));
9977 ins_cost(100);
9978 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9979 ins_encode %{
9980 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9981 %}
9982 ins_pipe(pipe_slow);
9983 %}
9984
9985 // Compare into -1,0,1
9986 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9987 %{
9988 match(Set dst (CmpF3 src1 src2));
9989 effect(KILL cr);
9990
9991 ins_cost(275);
9992 format %{ "ucomiss $src1, $src2\n\t"
9993 "movl $dst, #-1\n\t"
9994 "jp,s done\n\t"
9995 "jb,s done\n\t"
9996 "setne $dst\n\t"
9997 "movzbl $dst, $dst\n"
9998 "done:" %}
9999 ins_encode %{
10000 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10001 emit_cmpfp3(_masm, $dst$$Register);
10002 %}
10003 ins_pipe(pipe_slow);
10004 %}
10005
10006 // Compare into -1,0,1
10007 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10008 %{
10009 match(Set dst (CmpF3 src1 (LoadF src2)));
10010 effect(KILL cr);
10011
10012 ins_cost(275);
10013 format %{ "ucomiss $src1, $src2\n\t"
10014 "movl $dst, #-1\n\t"
10015 "jp,s done\n\t"
10016 "jb,s done\n\t"
10017 "setne $dst\n\t"
10018 "movzbl $dst, $dst\n"
10019 "done:" %}
10020 ins_encode %{
10021 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10022 emit_cmpfp3(_masm, $dst$$Register);
10023 %}
10024 ins_pipe(pipe_slow);
10025 %}
10026
10027 // Compare into -1,0,1
10028 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10029 match(Set dst (CmpF3 src con));
10030 effect(KILL cr);
10031
10032 ins_cost(275);
10033 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10034 "movl $dst, #-1\n\t"
10035 "jp,s done\n\t"
10036 "jb,s done\n\t"
10037 "setne $dst\n\t"
10038 "movzbl $dst, $dst\n"
10039 "done:" %}
10040 ins_encode %{
10041 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10042 emit_cmpfp3(_masm, $dst$$Register);
10043 %}
10044 ins_pipe(pipe_slow);
10045 %}
10046
10047 // Compare into -1,0,1
10048 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10049 %{
10050 match(Set dst (CmpD3 src1 src2));
10051 effect(KILL cr);
10052
10053 ins_cost(275);
10054 format %{ "ucomisd $src1, $src2\n\t"
10055 "movl $dst, #-1\n\t"
10056 "jp,s done\n\t"
10057 "jb,s done\n\t"
10058 "setne $dst\n\t"
10059 "movzbl $dst, $dst\n"
10060 "done:" %}
10061 ins_encode %{
10062 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10063 emit_cmpfp3(_masm, $dst$$Register);
10064 %}
10065 ins_pipe(pipe_slow);
10066 %}
10067
10068 // Compare into -1,0,1
10069 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10070 %{
10071 match(Set dst (CmpD3 src1 (LoadD src2)));
10072 effect(KILL cr);
10073
10074 ins_cost(275);
10075 format %{ "ucomisd $src1, $src2\n\t"
10076 "movl $dst, #-1\n\t"
10077 "jp,s done\n\t"
10078 "jb,s done\n\t"
10079 "setne $dst\n\t"
10080 "movzbl $dst, $dst\n"
10081 "done:" %}
10082 ins_encode %{
10083 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10084 emit_cmpfp3(_masm, $dst$$Register);
10085 %}
10086 ins_pipe(pipe_slow);
10087 %}
10088
10089 // Compare into -1,0,1
10090 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10091 match(Set dst (CmpD3 src con));
10092 effect(KILL cr);
10093
10094 ins_cost(275);
10095 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10096 "movl $dst, #-1\n\t"
10097 "jp,s done\n\t"
10098 "jb,s done\n\t"
10099 "setne $dst\n\t"
10100 "movzbl $dst, $dst\n"
10101 "done:" %}
10102 ins_encode %{
10103 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10104 emit_cmpfp3(_masm, $dst$$Register);
10105 %}
10106 ins_pipe(pipe_slow);
10107 %}
10108
10109 //----------Arithmetic Conversion Instructions---------------------------------
10110
10111 instruct roundFloat_nop(regF dst)
10112 %{
10113 match(Set dst (RoundFloat dst));
10114
10115 ins_cost(0);
10116 ins_encode();
10117 ins_pipe(empty);
10118 %}
10119
10120 instruct roundDouble_nop(regD dst)
10121 %{
10122 match(Set dst (RoundDouble dst));
10123
10124 ins_cost(0);
10125 ins_encode();
10126 ins_pipe(empty);
10127 %}
10128
10129 instruct convF2D_reg_reg(regD dst, regF src)
10130 %{
10131 match(Set dst (ConvF2D src));
10132
10133 format %{ "cvtss2sd $dst, $src" %}
10134 ins_encode %{
10135 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10136 %}
10137 ins_pipe(pipe_slow); // XXX
10138 %}
10139
10140 instruct convF2D_reg_mem(regD dst, memory src)
10141 %{
10142 match(Set dst (ConvF2D (LoadF src)));
10143
10144 format %{ "cvtss2sd $dst, $src" %}
10145 ins_encode %{
10146 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10147 %}
10148 ins_pipe(pipe_slow); // XXX
10149 %}
10150
10151 instruct convD2F_reg_reg(regF dst, regD src)
10152 %{
10153 match(Set dst (ConvD2F src));
10154
10155 format %{ "cvtsd2ss $dst, $src" %}
10156 ins_encode %{
10157 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10158 %}
10159 ins_pipe(pipe_slow); // XXX
10160 %}
10161
10162 instruct convD2F_reg_mem(regF dst, memory src)
10163 %{
10164 match(Set dst (ConvD2F (LoadD src)));
10165
10166 format %{ "cvtsd2ss $dst, $src" %}
10167 ins_encode %{
10168 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10169 %}
10170 ins_pipe(pipe_slow); // XXX
10171 %}
10172
10173 // XXX do mem variants
10174 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10175 %{
10176 match(Set dst (ConvF2I src));
10177 effect(KILL cr);
10178
10179 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10180 "cmpl $dst, #0x80000000\n\t"
10181 "jne,s done\n\t"
10182 "subq rsp, #8\n\t"
10183 "movss [rsp], $src\n\t"
10184 "call f2i_fixup\n\t"
10185 "popq $dst\n"
10186 "done: "%}
10187 ins_encode %{
10188 Label done;
10189 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10190 __ cmpl($dst$$Register, 0x80000000);
10191 __ jccb(Assembler::notEqual, done);
10192 __ subptr(rsp, 8);
10193 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10194 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10195 __ pop($dst$$Register);
10196 __ bind(done);
10197 %}
10198 ins_pipe(pipe_slow);
10199 %}
10200
10201 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10202 %{
10203 match(Set dst (ConvF2L src));
10204 effect(KILL cr);
10205
10206 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10207 "cmpq $dst, [0x8000000000000000]\n\t"
10208 "jne,s done\n\t"
10209 "subq rsp, #8\n\t"
10210 "movss [rsp], $src\n\t"
10211 "call f2l_fixup\n\t"
10212 "popq $dst\n"
10213 "done: "%}
10214 ins_encode %{
10215 Label done;
10216 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10217 __ cmp64($dst$$Register,
10218 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10219 __ jccb(Assembler::notEqual, done);
10220 __ subptr(rsp, 8);
10221 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10222 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10223 __ pop($dst$$Register);
10224 __ bind(done);
10225 %}
10226 ins_pipe(pipe_slow);
10227 %}
10228
10229 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10230 %{
10231 match(Set dst (ConvD2I src));
10232 effect(KILL cr);
10233
10234 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10235 "cmpl $dst, #0x80000000\n\t"
10236 "jne,s done\n\t"
10237 "subq rsp, #8\n\t"
10238 "movsd [rsp], $src\n\t"
10239 "call d2i_fixup\n\t"
10240 "popq $dst\n"
10241 "done: "%}
10242 ins_encode %{
10243 Label done;
10244 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10245 __ cmpl($dst$$Register, 0x80000000);
10246 __ jccb(Assembler::notEqual, done);
10247 __ subptr(rsp, 8);
10248 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10249 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10250 __ pop($dst$$Register);
10251 __ bind(done);
10252 %}
10253 ins_pipe(pipe_slow);
10254 %}
10255
10256 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10257 %{
10258 match(Set dst (ConvD2L src));
10259 effect(KILL cr);
10260
10261 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10262 "cmpq $dst, [0x8000000000000000]\n\t"
10263 "jne,s done\n\t"
10264 "subq rsp, #8\n\t"
10265 "movsd [rsp], $src\n\t"
10266 "call d2l_fixup\n\t"
10267 "popq $dst\n"
10268 "done: "%}
10269 ins_encode %{
10270 Label done;
10271 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10272 __ cmp64($dst$$Register,
10273 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10274 __ jccb(Assembler::notEqual, done);
10275 __ subptr(rsp, 8);
10276 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10277 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10278 __ pop($dst$$Register);
10279 __ bind(done);
10280 %}
10281 ins_pipe(pipe_slow);
10282 %}
10283
10284 instruct convI2F_reg_reg(regF dst, rRegI src)
10285 %{
10286 predicate(!UseXmmI2F);
10287 match(Set dst (ConvI2F src));
10288
10289 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10290 ins_encode %{
10291 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10292 %}
10293 ins_pipe(pipe_slow); // XXX
10294 %}
10295
10296 instruct convI2F_reg_mem(regF dst, memory src)
10297 %{
10298 match(Set dst (ConvI2F (LoadI src)));
10299
10300 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10301 ins_encode %{
10302 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10303 %}
10304 ins_pipe(pipe_slow); // XXX
10305 %}
10306
10307 instruct convI2D_reg_reg(regD dst, rRegI src)
10308 %{
10309 predicate(!UseXmmI2D);
10310 match(Set dst (ConvI2D src));
10311
10312 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10313 ins_encode %{
10314 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10315 %}
10316 ins_pipe(pipe_slow); // XXX
10317 %}
10318
10319 instruct convI2D_reg_mem(regD dst, memory src)
10320 %{
10321 match(Set dst (ConvI2D (LoadI src)));
10322
10323 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10324 ins_encode %{
10325 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10326 %}
10327 ins_pipe(pipe_slow); // XXX
10328 %}
10329
10330 instruct convXI2F_reg(regF dst, rRegI src)
10331 %{
10332 predicate(UseXmmI2F);
10333 match(Set dst (ConvI2F src));
10334
10335 format %{ "movdl $dst, $src\n\t"
10336 "cvtdq2psl $dst, $dst\t# i2f" %}
10337 ins_encode %{
10338 __ movdl($dst$$XMMRegister, $src$$Register);
10339 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10340 %}
10341 ins_pipe(pipe_slow); // XXX
10342 %}
10343
10344 instruct convXI2D_reg(regD dst, rRegI src)
10345 %{
10346 predicate(UseXmmI2D);
10347 match(Set dst (ConvI2D src));
10348
10349 format %{ "movdl $dst, $src\n\t"
10350 "cvtdq2pdl $dst, $dst\t# i2d" %}
10351 ins_encode %{
10352 __ movdl($dst$$XMMRegister, $src$$Register);
10353 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10354 %}
10355 ins_pipe(pipe_slow); // XXX
10356 %}
10357
10358 instruct convL2F_reg_reg(regF dst, rRegL src)
10359 %{
10360 match(Set dst (ConvL2F src));
10361
10362 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10363 ins_encode %{
10364 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10365 %}
10366 ins_pipe(pipe_slow); // XXX
10367 %}
10368
10369 instruct convL2F_reg_mem(regF dst, memory src)
10370 %{
10371 match(Set dst (ConvL2F (LoadL src)));
10372
10373 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10374 ins_encode %{
10375 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10376 %}
10377 ins_pipe(pipe_slow); // XXX
10378 %}
10379
10380 instruct convL2D_reg_reg(regD dst, rRegL src)
10381 %{
10382 match(Set dst (ConvL2D src));
10383
10384 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10385 ins_encode %{
10386 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10387 %}
10388 ins_pipe(pipe_slow); // XXX
10389 %}
10390
10391 instruct convL2D_reg_mem(regD dst, memory src)
10392 %{
10393 match(Set dst (ConvL2D (LoadL src)));
10394
10395 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10396 ins_encode %{
10397 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10398 %}
10399 ins_pipe(pipe_slow); // XXX
10400 %}
10401
10402 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10403 %{
10404 match(Set dst (ConvI2L src));
10405
10406 ins_cost(125);
10407 format %{ "movslq $dst, $src\t# i2l" %}
10408 ins_encode %{
10409 __ movslq($dst$$Register, $src$$Register);
10410 %}
10411 ins_pipe(ialu_reg_reg);
10412 %}
10413
10414 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10415 // %{
10416 // match(Set dst (ConvI2L src));
10417 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10418 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10419 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10420 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10421 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10422 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10423
10424 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10425 // ins_encode(enc_copy(dst, src));
10426 // // opcode(0x63); // needs REX.W
10427 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10428 // ins_pipe(ialu_reg_reg);
10429 // %}
10430
10431 // Zero-extend convert int to long
10432 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10433 %{
10434 match(Set dst (AndL (ConvI2L src) mask));
10435
10436 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10437 ins_encode %{
10438 if ($dst$$reg != $src$$reg) {
10439 __ movl($dst$$Register, $src$$Register);
10440 }
10441 %}
10442 ins_pipe(ialu_reg_reg);
10443 %}
10444
10445 // Zero-extend convert int to long
10446 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10447 %{
10448 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10449
10450 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10451 ins_encode %{
10452 __ movl($dst$$Register, $src$$Address);
10453 %}
10454 ins_pipe(ialu_reg_mem);
10455 %}
10456
10457 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10458 %{
10459 match(Set dst (AndL src mask));
10460
10461 format %{ "movl $dst, $src\t# zero-extend long" %}
10462 ins_encode %{
10463 __ movl($dst$$Register, $src$$Register);
10464 %}
10465 ins_pipe(ialu_reg_reg);
10466 %}
10467
10468 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10469 %{
10470 match(Set dst (ConvL2I src));
10471
10472 format %{ "movl $dst, $src\t# l2i" %}
10473 ins_encode %{
10474 __ movl($dst$$Register, $src$$Register);
10475 %}
10476 ins_pipe(ialu_reg_reg);
10477 %}
10478
10479
10480 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10481 match(Set dst (MoveF2I src));
10482 effect(DEF dst, USE src);
10483
10484 ins_cost(125);
10485 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10486 ins_encode %{
10487 __ movl($dst$$Register, Address(rsp, $src$$disp));
10488 %}
10489 ins_pipe(ialu_reg_mem);
10490 %}
10491
10492 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10493 match(Set dst (MoveI2F src));
10494 effect(DEF dst, USE src);
10495
10496 ins_cost(125);
10497 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10498 ins_encode %{
10499 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10500 %}
10501 ins_pipe(pipe_slow);
10502 %}
10503
10504 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10505 match(Set dst (MoveD2L src));
10506 effect(DEF dst, USE src);
10507
10508 ins_cost(125);
10509 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10510 ins_encode %{
10511 __ movq($dst$$Register, Address(rsp, $src$$disp));
10512 %}
10513 ins_pipe(ialu_reg_mem);
10514 %}
10515
10516 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10517 predicate(!UseXmmLoadAndClearUpper);
10518 match(Set dst (MoveL2D src));
10519 effect(DEF dst, USE src);
10520
10521 ins_cost(125);
10522 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10523 ins_encode %{
10524 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10525 %}
10526 ins_pipe(pipe_slow);
10527 %}
10528
10529 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10530 predicate(UseXmmLoadAndClearUpper);
10531 match(Set dst (MoveL2D src));
10532 effect(DEF dst, USE src);
10533
10534 ins_cost(125);
10535 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10536 ins_encode %{
10537 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10538 %}
10539 ins_pipe(pipe_slow);
10540 %}
10541
10542
10543 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10544 match(Set dst (MoveF2I src));
10545 effect(DEF dst, USE src);
10546
10547 ins_cost(95); // XXX
10548 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10549 ins_encode %{
10550 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10551 %}
10552 ins_pipe(pipe_slow);
10553 %}
10554
10555 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10556 match(Set dst (MoveI2F src));
10557 effect(DEF dst, USE src);
10558
10559 ins_cost(100);
10560 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10561 ins_encode %{
10562 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10563 %}
10564 ins_pipe( ialu_mem_reg );
10565 %}
10566
10567 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10568 match(Set dst (MoveD2L src));
10569 effect(DEF dst, USE src);
10570
10571 ins_cost(95); // XXX
10572 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10573 ins_encode %{
10574 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10575 %}
10576 ins_pipe(pipe_slow);
10577 %}
10578
10579 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10580 match(Set dst (MoveL2D src));
10581 effect(DEF dst, USE src);
10582
10583 ins_cost(100);
10584 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10585 ins_encode %{
10586 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10587 %}
10588 ins_pipe(ialu_mem_reg);
10589 %}
10590
10591 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10592 match(Set dst (MoveF2I src));
10593 effect(DEF dst, USE src);
10594 ins_cost(85);
10595 format %{ "movd $dst,$src\t# MoveF2I" %}
10596 ins_encode %{
10597 __ movdl($dst$$Register, $src$$XMMRegister);
10598 %}
10599 ins_pipe( pipe_slow );
10600 %}
10601
10602 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10603 match(Set dst (MoveD2L src));
10604 effect(DEF dst, USE src);
10605 ins_cost(85);
10606 format %{ "movd $dst,$src\t# MoveD2L" %}
10607 ins_encode %{
10608 __ movdq($dst$$Register, $src$$XMMRegister);
10609 %}
10610 ins_pipe( pipe_slow );
10611 %}
10612
10613 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10614 match(Set dst (MoveI2F src));
10615 effect(DEF dst, USE src);
10616 ins_cost(100);
10617 format %{ "movd $dst,$src\t# MoveI2F" %}
10618 ins_encode %{
10619 __ movdl($dst$$XMMRegister, $src$$Register);
10620 %}
10621 ins_pipe( pipe_slow );
10622 %}
10623
10624 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10625 match(Set dst (MoveL2D src));
10626 effect(DEF dst, USE src);
10627 ins_cost(100);
10628 format %{ "movd $dst,$src\t# MoveL2D" %}
10629 ins_encode %{
10630 __ movdq($dst$$XMMRegister, $src$$Register);
10631 %}
10632 ins_pipe( pipe_slow );
10633 %}
10634
10635
10636 // =======================================================================
10637 // fast clearing of an array
10638 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10639 rFlagsReg cr)
10640 %{
10641 predicate(!((ClearArrayNode*)n)->is_large());
10642 match(Set dummy (ClearArray cnt base));
10643 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10644
10645 format %{ $$template
10646 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10647 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10648 $$emit$$"jg LARGE\n\t"
10649 $$emit$$"dec rcx\n\t"
10650 $$emit$$"js DONE\t# Zero length\n\t"
10651 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10652 $$emit$$"dec rcx\n\t"
10653 $$emit$$"jge LOOP\n\t"
10654 $$emit$$"jmp DONE\n\t"
10655 $$emit$$"# LARGE:\n\t"
10656 if (UseFastStosb) {
10657 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10658 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10659 } else {
10660 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10661 }
10662 $$emit$$"# DONE"
10663 %}
10664 ins_encode %{
10665 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, false);
10666 %}
10667 ins_pipe(pipe_slow);
10668 %}
10669
10670 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10671 rFlagsReg cr)
10672 %{
10673 predicate(((ClearArrayNode*)n)->is_large());
10674 match(Set dummy (ClearArray cnt base));
10675 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10676
10677 format %{ $$template
10678 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10679 if (UseFastStosb) {
10680 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10681 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10682 } else {
10683 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10684 }
10685 %}
10686 ins_encode %{
10687 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, true);
10688 %}
10689 ins_pipe(pipe_slow);
10690 %}
10691
10692 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10693 rax_RegI result, regD tmp1, rFlagsReg cr)
10694 %{
10695 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10696 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10697 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10698
10699 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10700 ins_encode %{
10701 __ string_compare($str1$$Register, $str2$$Register,
10702 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10703 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
10704 %}
10705 ins_pipe( pipe_slow );
10706 %}
10707
10708 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10709 rax_RegI result, regD tmp1, rFlagsReg cr)
10710 %{
10711 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10712 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10713 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10714
10715 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10716 ins_encode %{
10717 __ string_compare($str1$$Register, $str2$$Register,
10718 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10719 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
10720 %}
10721 ins_pipe( pipe_slow );
10722 %}
10723
10724 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10725 rax_RegI result, regD tmp1, rFlagsReg cr)
10726 %{
10727 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10728 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10729 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10730
10731 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10732 ins_encode %{
10733 __ string_compare($str1$$Register, $str2$$Register,
10734 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10735 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
10736 %}
10737 ins_pipe( pipe_slow );
10738 %}
10739
10740 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
10741 rax_RegI result, regD tmp1, rFlagsReg cr)
10742 %{
10743 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10744 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10745 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10746
10747 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10748 ins_encode %{
10749 __ string_compare($str2$$Register, $str1$$Register,
10750 $cnt2$$Register, $cnt1$$Register, $result$$Register,
10751 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
10752 %}
10753 ins_pipe( pipe_slow );
10754 %}
10755
10756 // fast search of substring with known size.
10757 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10758 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10759 %{
10760 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10761 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10762 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10763
10764 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10765 ins_encode %{
10766 int icnt2 = (int)$int_cnt2$$constant;
10767 if (icnt2 >= 16) {
10768 // IndexOf for constant substrings with size >= 16 elements
10769 // which don't need to be loaded through stack.
10770 __ string_indexofC8($str1$$Register, $str2$$Register,
10771 $cnt1$$Register, $cnt2$$Register,
10772 icnt2, $result$$Register,
10773 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10774 } else {
10775 // Small strings are loaded through stack if they cross page boundary.
10776 __ string_indexof($str1$$Register, $str2$$Register,
10777 $cnt1$$Register, $cnt2$$Register,
10778 icnt2, $result$$Register,
10779 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10780 }
10781 %}
10782 ins_pipe( pipe_slow );
10783 %}
10784
10785 // fast search of substring with known size.
10786 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10787 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10788 %{
10789 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10790 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10791 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10792
10793 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10794 ins_encode %{
10795 int icnt2 = (int)$int_cnt2$$constant;
10796 if (icnt2 >= 8) {
10797 // IndexOf for constant substrings with size >= 8 elements
10798 // which don't need to be loaded through stack.
10799 __ string_indexofC8($str1$$Register, $str2$$Register,
10800 $cnt1$$Register, $cnt2$$Register,
10801 icnt2, $result$$Register,
10802 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10803 } else {
10804 // Small strings are loaded through stack if they cross page boundary.
10805 __ string_indexof($str1$$Register, $str2$$Register,
10806 $cnt1$$Register, $cnt2$$Register,
10807 icnt2, $result$$Register,
10808 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10809 }
10810 %}
10811 ins_pipe( pipe_slow );
10812 %}
10813
10814 // fast search of substring with known size.
10815 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10816 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10817 %{
10818 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10819 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10820 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10821
10822 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10823 ins_encode %{
10824 int icnt2 = (int)$int_cnt2$$constant;
10825 if (icnt2 >= 8) {
10826 // IndexOf for constant substrings with size >= 8 elements
10827 // which don't need to be loaded through stack.
10828 __ string_indexofC8($str1$$Register, $str2$$Register,
10829 $cnt1$$Register, $cnt2$$Register,
10830 icnt2, $result$$Register,
10831 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10832 } else {
10833 // Small strings are loaded through stack if they cross page boundary.
10834 __ string_indexof($str1$$Register, $str2$$Register,
10835 $cnt1$$Register, $cnt2$$Register,
10836 icnt2, $result$$Register,
10837 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10838 }
10839 %}
10840 ins_pipe( pipe_slow );
10841 %}
10842
10843 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10844 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10845 %{
10846 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10847 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10848 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10849
10850 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10851 ins_encode %{
10852 __ string_indexof($str1$$Register, $str2$$Register,
10853 $cnt1$$Register, $cnt2$$Register,
10854 (-1), $result$$Register,
10855 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10856 %}
10857 ins_pipe( pipe_slow );
10858 %}
10859
10860 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10861 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10862 %{
10863 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10864 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10865 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10866
10867 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10868 ins_encode %{
10869 __ string_indexof($str1$$Register, $str2$$Register,
10870 $cnt1$$Register, $cnt2$$Register,
10871 (-1), $result$$Register,
10872 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10873 %}
10874 ins_pipe( pipe_slow );
10875 %}
10876
10877 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10878 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10879 %{
10880 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10881 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10882 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10883
10884 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10885 ins_encode %{
10886 __ string_indexof($str1$$Register, $str2$$Register,
10887 $cnt1$$Register, $cnt2$$Register,
10888 (-1), $result$$Register,
10889 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10890 %}
10891 ins_pipe( pipe_slow );
10892 %}
10893
10894 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
10895 rbx_RegI result, regD vec1, regD vec2, regD vec3, rcx_RegI tmp, rFlagsReg cr)
10896 %{
10897 predicate(UseSSE42Intrinsics);
10898 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10899 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
10900 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
10901 ins_encode %{
10902 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
10903 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
10904 %}
10905 ins_pipe( pipe_slow );
10906 %}
10907
10908 // fast string equals
10909 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10910 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10911 %{
10912 match(Set result (StrEquals (Binary str1 str2) cnt));
10913 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10914
10915 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10916 ins_encode %{
10917 __ arrays_equals(false, $str1$$Register, $str2$$Register,
10918 $cnt$$Register, $result$$Register, $tmp3$$Register,
10919 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10920 %}
10921 ins_pipe( pipe_slow );
10922 %}
10923
10924 // fast array equals
10925 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10926 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10927 %{
10928 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10929 match(Set result (AryEq ary1 ary2));
10930 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10931
10932 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10933 ins_encode %{
10934 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10935 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10936 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10937 %}
10938 ins_pipe( pipe_slow );
10939 %}
10940
10941 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10942 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10943 %{
10944 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10945 match(Set result (AryEq ary1 ary2));
10946 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10947
10948 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10949 ins_encode %{
10950 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10951 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10952 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
10953 %}
10954 ins_pipe( pipe_slow );
10955 %}
10956
10957 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
10958 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10959 %{
10960 match(Set result (HasNegatives ary1 len));
10961 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
10962
10963 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10964 ins_encode %{
10965 __ has_negatives($ary1$$Register, $len$$Register,
10966 $result$$Register, $tmp3$$Register,
10967 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10968 %}
10969 ins_pipe( pipe_slow );
10970 %}
10971
10972 // fast char[] to byte[] compression
10973 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10974 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10975 match(Set result (StrCompressedCopy src (Binary dst len)));
10976 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10977
10978 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
10979 ins_encode %{
10980 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
10981 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10982 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10983 %}
10984 ins_pipe( pipe_slow );
10985 %}
10986
10987 // fast byte[] to char[] inflation
10988 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10989 regD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
10990 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10991 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
10992
10993 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
10994 ins_encode %{
10995 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
10996 $tmp1$$XMMRegister, $tmp2$$Register);
10997 %}
10998 ins_pipe( pipe_slow );
10999 %}
11000
11001 // encode char[] to byte[] in ISO_8859_1
11002 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11003 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11004 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11005 match(Set result (EncodeISOArray src (Binary dst len)));
11006 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11007
11008 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11009 ins_encode %{
11010 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11011 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11012 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11013 %}
11014 ins_pipe( pipe_slow );
11015 %}
11016
11017 instruct getFP(rRegL dst) %{
11018 match(Set dst (GetFP));
11019 effect(DEF dst);
11020 ins_cost(1);
11021
11022 ins_encode %{
11023 // Remove wordSize for return addr which is already pushed.
11024 int framesize = Compile::current()->frame_size_in_bytes() - wordSize;
11025 Address base(rsp, framesize);
11026 __ lea($dst$$Register, base);
11027 %}
11028 ins_pipe(ialu_reg_reg_long);
11029 %}
11030
11031 //----------Overflow Math Instructions-----------------------------------------
11032
11033 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11034 %{
11035 match(Set cr (OverflowAddI op1 op2));
11036 effect(DEF cr, USE_KILL op1, USE op2);
11037
11038 format %{ "addl $op1, $op2\t# overflow check int" %}
11039
11040 ins_encode %{
11041 __ addl($op1$$Register, $op2$$Register);
11042 %}
11043 ins_pipe(ialu_reg_reg);
11044 %}
11045
11046 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11047 %{
11048 match(Set cr (OverflowAddI op1 op2));
11049 effect(DEF cr, USE_KILL op1, USE op2);
11050
11051 format %{ "addl $op1, $op2\t# overflow check int" %}
11052
11053 ins_encode %{
11054 __ addl($op1$$Register, $op2$$constant);
11055 %}
11056 ins_pipe(ialu_reg_reg);
11057 %}
11058
11059 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11060 %{
11061 match(Set cr (OverflowAddL op1 op2));
11062 effect(DEF cr, USE_KILL op1, USE op2);
11063
11064 format %{ "addq $op1, $op2\t# overflow check long" %}
11065 ins_encode %{
11066 __ addq($op1$$Register, $op2$$Register);
11067 %}
11068 ins_pipe(ialu_reg_reg);
11069 %}
11070
11071 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11072 %{
11073 match(Set cr (OverflowAddL op1 op2));
11074 effect(DEF cr, USE_KILL op1, USE op2);
11075
11076 format %{ "addq $op1, $op2\t# overflow check long" %}
11077 ins_encode %{
11078 __ addq($op1$$Register, $op2$$constant);
11079 %}
11080 ins_pipe(ialu_reg_reg);
11081 %}
11082
11083 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11084 %{
11085 match(Set cr (OverflowSubI op1 op2));
11086
11087 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11088 ins_encode %{
11089 __ cmpl($op1$$Register, $op2$$Register);
11090 %}
11091 ins_pipe(ialu_reg_reg);
11092 %}
11093
11094 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11095 %{
11096 match(Set cr (OverflowSubI op1 op2));
11097
11098 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11099 ins_encode %{
11100 __ cmpl($op1$$Register, $op2$$constant);
11101 %}
11102 ins_pipe(ialu_reg_reg);
11103 %}
11104
11105 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11106 %{
11107 match(Set cr (OverflowSubL op1 op2));
11108
11109 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11110 ins_encode %{
11111 __ cmpq($op1$$Register, $op2$$Register);
11112 %}
11113 ins_pipe(ialu_reg_reg);
11114 %}
11115
11116 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11117 %{
11118 match(Set cr (OverflowSubL op1 op2));
11119
11120 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11121 ins_encode %{
11122 __ cmpq($op1$$Register, $op2$$constant);
11123 %}
11124 ins_pipe(ialu_reg_reg);
11125 %}
11126
11127 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11128 %{
11129 match(Set cr (OverflowSubI zero op2));
11130 effect(DEF cr, USE_KILL op2);
11131
11132 format %{ "negl $op2\t# overflow check int" %}
11133 ins_encode %{
11134 __ negl($op2$$Register);
11135 %}
11136 ins_pipe(ialu_reg_reg);
11137 %}
11138
11139 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11140 %{
11141 match(Set cr (OverflowSubL zero op2));
11142 effect(DEF cr, USE_KILL op2);
11143
11144 format %{ "negq $op2\t# overflow check long" %}
11145 ins_encode %{
11146 __ negq($op2$$Register);
11147 %}
11148 ins_pipe(ialu_reg_reg);
11149 %}
11150
11151 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11152 %{
11153 match(Set cr (OverflowMulI op1 op2));
11154 effect(DEF cr, USE_KILL op1, USE op2);
11155
11156 format %{ "imull $op1, $op2\t# overflow check int" %}
11157 ins_encode %{
11158 __ imull($op1$$Register, $op2$$Register);
11159 %}
11160 ins_pipe(ialu_reg_reg_alu0);
11161 %}
11162
11163 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11164 %{
11165 match(Set cr (OverflowMulI op1 op2));
11166 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11167
11168 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11169 ins_encode %{
11170 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11171 %}
11172 ins_pipe(ialu_reg_reg_alu0);
11173 %}
11174
11175 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11176 %{
11177 match(Set cr (OverflowMulL op1 op2));
11178 effect(DEF cr, USE_KILL op1, USE op2);
11179
11180 format %{ "imulq $op1, $op2\t# overflow check long" %}
11181 ins_encode %{
11182 __ imulq($op1$$Register, $op2$$Register);
11183 %}
11184 ins_pipe(ialu_reg_reg_alu0);
11185 %}
11186
11187 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11188 %{
11189 match(Set cr (OverflowMulL op1 op2));
11190 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11191
11192 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11193 ins_encode %{
11194 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11195 %}
11196 ins_pipe(ialu_reg_reg_alu0);
11197 %}
11198
11199
11200 //----------Control Flow Instructions------------------------------------------
11201 // Signed compare Instructions
11202
11203 // XXX more variants!!
11204 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11205 %{
11206 match(Set cr (CmpI op1 op2));
11207 effect(DEF cr, USE op1, USE op2);
11208
11209 format %{ "cmpl $op1, $op2" %}
11210 opcode(0x3B); /* Opcode 3B /r */
11211 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11212 ins_pipe(ialu_cr_reg_reg);
11213 %}
11214
11215 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11216 %{
11217 match(Set cr (CmpI op1 op2));
11218
11219 format %{ "cmpl $op1, $op2" %}
11220 opcode(0x81, 0x07); /* Opcode 81 /7 */
11221 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11222 ins_pipe(ialu_cr_reg_imm);
11223 %}
11224
11225 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11226 %{
11227 match(Set cr (CmpI op1 (LoadI op2)));
11228
11229 ins_cost(500); // XXX
11230 format %{ "cmpl $op1, $op2" %}
11231 opcode(0x3B); /* Opcode 3B /r */
11232 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11233 ins_pipe(ialu_cr_reg_mem);
11234 %}
11235
11236 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11237 %{
11238 match(Set cr (CmpI src zero));
11239
11240 format %{ "testl $src, $src" %}
11241 opcode(0x85);
11242 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11243 ins_pipe(ialu_cr_reg_imm);
11244 %}
11245
11246 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11247 %{
11248 match(Set cr (CmpI (AndI src con) zero));
11249
11250 format %{ "testl $src, $con" %}
11251 opcode(0xF7, 0x00);
11252 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11253 ins_pipe(ialu_cr_reg_imm);
11254 %}
11255
11256 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11257 %{
11258 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11259
11260 format %{ "testl $src, $mem" %}
11261 opcode(0x85);
11262 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11263 ins_pipe(ialu_cr_reg_mem);
11264 %}
11265
11266 // Unsigned compare Instructions; really, same as signed except they
11267 // produce an rFlagsRegU instead of rFlagsReg.
11268 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11269 %{
11270 match(Set cr (CmpU op1 op2));
11271
11272 format %{ "cmpl $op1, $op2\t# unsigned" %}
11273 opcode(0x3B); /* Opcode 3B /r */
11274 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11275 ins_pipe(ialu_cr_reg_reg);
11276 %}
11277
11278 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11279 %{
11280 match(Set cr (CmpU op1 op2));
11281
11282 format %{ "cmpl $op1, $op2\t# unsigned" %}
11283 opcode(0x81,0x07); /* Opcode 81 /7 */
11284 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11285 ins_pipe(ialu_cr_reg_imm);
11286 %}
11287
11288 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11289 %{
11290 match(Set cr (CmpU op1 (LoadI op2)));
11291
11292 ins_cost(500); // XXX
11293 format %{ "cmpl $op1, $op2\t# unsigned" %}
11294 opcode(0x3B); /* Opcode 3B /r */
11295 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11296 ins_pipe(ialu_cr_reg_mem);
11297 %}
11298
11299 // // // Cisc-spilled version of cmpU_rReg
11300 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11301 // //%{
11302 // // match(Set cr (CmpU (LoadI op1) op2));
11303 // //
11304 // // format %{ "CMPu $op1,$op2" %}
11305 // // ins_cost(500);
11306 // // opcode(0x39); /* Opcode 39 /r */
11307 // // ins_encode( OpcP, reg_mem( op1, op2) );
11308 // //%}
11309
11310 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11311 %{
11312 match(Set cr (CmpU src zero));
11313
11314 format %{ "testl $src, $src\t# unsigned" %}
11315 opcode(0x85);
11316 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11317 ins_pipe(ialu_cr_reg_imm);
11318 %}
11319
11320 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11321 %{
11322 match(Set cr (CmpP op1 op2));
11323
11324 format %{ "cmpq $op1, $op2\t# ptr" %}
11325 opcode(0x3B); /* Opcode 3B /r */
11326 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11327 ins_pipe(ialu_cr_reg_reg);
11328 %}
11329
11330 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11331 %{
11332 match(Set cr (CmpP op1 (LoadP op2)));
11333
11334 ins_cost(500); // XXX
11335 format %{ "cmpq $op1, $op2\t# ptr" %}
11336 opcode(0x3B); /* Opcode 3B /r */
11337 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11338 ins_pipe(ialu_cr_reg_mem);
11339 %}
11340
11341 // // // Cisc-spilled version of cmpP_rReg
11342 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11343 // //%{
11344 // // match(Set cr (CmpP (LoadP op1) op2));
11345 // //
11346 // // format %{ "CMPu $op1,$op2" %}
11347 // // ins_cost(500);
11348 // // opcode(0x39); /* Opcode 39 /r */
11349 // // ins_encode( OpcP, reg_mem( op1, op2) );
11350 // //%}
11351
11352 // XXX this is generalized by compP_rReg_mem???
11353 // Compare raw pointer (used in out-of-heap check).
11354 // Only works because non-oop pointers must be raw pointers
11355 // and raw pointers have no anti-dependencies.
11356 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11357 %{
11358 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11359 match(Set cr (CmpP op1 (LoadP op2)));
11360
11361 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11362 opcode(0x3B); /* Opcode 3B /r */
11363 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11364 ins_pipe(ialu_cr_reg_mem);
11365 %}
11366
11367 // This will generate a signed flags result. This should be OK since
11368 // any compare to a zero should be eq/neq.
11369 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11370 %{
11371 match(Set cr (CmpP src zero));
11372
11373 format %{ "testq $src, $src\t# ptr" %}
11374 opcode(0x85);
11375 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11376 ins_pipe(ialu_cr_reg_imm);
11377 %}
11378
11379 // This will generate a signed flags result. This should be OK since
11380 // any compare to a zero should be eq/neq.
11381 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11382 %{
11383 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11384 match(Set cr (CmpP (LoadP op) zero));
11385
11386 ins_cost(500); // XXX
11387 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11388 opcode(0xF7); /* Opcode F7 /0 */
11389 ins_encode(REX_mem_wide(op),
11390 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11391 ins_pipe(ialu_cr_reg_imm);
11392 %}
11393
11394 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11395 %{
11396 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11397 match(Set cr (CmpP (LoadP mem) zero));
11398
11399 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11400 ins_encode %{
11401 __ cmpq(r12, $mem$$Address);
11402 %}
11403 ins_pipe(ialu_cr_reg_mem);
11404 %}
11405
11406 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11407 %{
11408 match(Set cr (CmpN op1 op2));
11409
11410 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11411 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11412 ins_pipe(ialu_cr_reg_reg);
11413 %}
11414
11415 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11416 %{
11417 match(Set cr (CmpN src (LoadN mem)));
11418
11419 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11420 ins_encode %{
11421 __ cmpl($src$$Register, $mem$$Address);
11422 %}
11423 ins_pipe(ialu_cr_reg_mem);
11424 %}
11425
11426 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11427 match(Set cr (CmpN op1 op2));
11428
11429 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11430 ins_encode %{
11431 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11432 %}
11433 ins_pipe(ialu_cr_reg_imm);
11434 %}
11435
11436 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11437 %{
11438 match(Set cr (CmpN src (LoadN mem)));
11439
11440 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11441 ins_encode %{
11442 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11443 %}
11444 ins_pipe(ialu_cr_reg_mem);
11445 %}
11446
11447 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11448 match(Set cr (CmpN op1 op2));
11449
11450 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11451 ins_encode %{
11452 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11453 %}
11454 ins_pipe(ialu_cr_reg_imm);
11455 %}
11456
11457 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11458 %{
11459 match(Set cr (CmpN src (LoadNKlass mem)));
11460
11461 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11462 ins_encode %{
11463 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11464 %}
11465 ins_pipe(ialu_cr_reg_mem);
11466 %}
11467
11468 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11469 match(Set cr (CmpN src zero));
11470
11471 format %{ "testl $src, $src\t# compressed ptr" %}
11472 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11473 ins_pipe(ialu_cr_reg_imm);
11474 %}
11475
11476 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11477 %{
11478 predicate(Universe::narrow_oop_base() != NULL);
11479 match(Set cr (CmpN (LoadN mem) zero));
11480
11481 ins_cost(500); // XXX
11482 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11483 ins_encode %{
11484 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11485 %}
11486 ins_pipe(ialu_cr_reg_mem);
11487 %}
11488
11489 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11490 %{
11491 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11492 match(Set cr (CmpN (LoadN mem) zero));
11493
11494 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11495 ins_encode %{
11496 __ cmpl(r12, $mem$$Address);
11497 %}
11498 ins_pipe(ialu_cr_reg_mem);
11499 %}
11500
11501 // Yanked all unsigned pointer compare operations.
11502 // Pointer compares are done with CmpP which is already unsigned.
11503
11504 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11505 %{
11506 match(Set cr (CmpL op1 op2));
11507
11508 format %{ "cmpq $op1, $op2" %}
11509 opcode(0x3B); /* Opcode 3B /r */
11510 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11511 ins_pipe(ialu_cr_reg_reg);
11512 %}
11513
11514 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11515 %{
11516 match(Set cr (CmpL op1 op2));
11517
11518 format %{ "cmpq $op1, $op2" %}
11519 opcode(0x81, 0x07); /* Opcode 81 /7 */
11520 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11521 ins_pipe(ialu_cr_reg_imm);
11522 %}
11523
11524 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11525 %{
11526 match(Set cr (CmpL op1 (LoadL op2)));
11527
11528 format %{ "cmpq $op1, $op2" %}
11529 opcode(0x3B); /* Opcode 3B /r */
11530 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11531 ins_pipe(ialu_cr_reg_mem);
11532 %}
11533
11534 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11535 %{
11536 match(Set cr (CmpL src zero));
11537
11538 format %{ "testq $src, $src" %}
11539 opcode(0x85);
11540 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11541 ins_pipe(ialu_cr_reg_imm);
11542 %}
11543
11544 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11545 %{
11546 match(Set cr (CmpL (AndL src con) zero));
11547
11548 format %{ "testq $src, $con\t# long" %}
11549 opcode(0xF7, 0x00);
11550 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11551 ins_pipe(ialu_cr_reg_imm);
11552 %}
11553
11554 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11555 %{
11556 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11557
11558 format %{ "testq $src, $mem" %}
11559 opcode(0x85);
11560 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11561 ins_pipe(ialu_cr_reg_mem);
11562 %}
11563
11564 // Manifest a CmpL result in an integer register. Very painful.
11565 // This is the test to avoid.
11566 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11567 %{
11568 match(Set dst (CmpL3 src1 src2));
11569 effect(KILL flags);
11570
11571 ins_cost(275); // XXX
11572 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11573 "movl $dst, -1\n\t"
11574 "jl,s done\n\t"
11575 "setne $dst\n\t"
11576 "movzbl $dst, $dst\n\t"
11577 "done:" %}
11578 ins_encode(cmpl3_flag(src1, src2, dst));
11579 ins_pipe(pipe_slow);
11580 %}
11581
11582 // Unsigned long compare Instructions; really, same as signed long except they
11583 // produce an rFlagsRegU instead of rFlagsReg.
11584 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
11585 %{
11586 match(Set cr (CmpUL op1 op2));
11587
11588 format %{ "cmpq $op1, $op2\t# unsigned" %}
11589 opcode(0x3B); /* Opcode 3B /r */
11590 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11591 ins_pipe(ialu_cr_reg_reg);
11592 %}
11593
11594 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
11595 %{
11596 match(Set cr (CmpUL op1 op2));
11597
11598 format %{ "cmpq $op1, $op2\t# unsigned" %}
11599 opcode(0x81, 0x07); /* Opcode 81 /7 */
11600 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11601 ins_pipe(ialu_cr_reg_imm);
11602 %}
11603
11604 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
11605 %{
11606 match(Set cr (CmpUL op1 (LoadL op2)));
11607
11608 format %{ "cmpq $op1, $op2\t# unsigned" %}
11609 opcode(0x3B); /* Opcode 3B /r */
11610 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11611 ins_pipe(ialu_cr_reg_mem);
11612 %}
11613
11614 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
11615 %{
11616 match(Set cr (CmpUL src zero));
11617
11618 format %{ "testq $src, $src\t# unsigned" %}
11619 opcode(0x85);
11620 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11621 ins_pipe(ialu_cr_reg_imm);
11622 %}
11623
11624 instruct compUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm)
11625 %{
11626 match(Set cr (CmpI (LoadUB mem) imm));
11627
11628 ins_cost(125);
11629 format %{ "cmpb $mem, $imm" %}
11630 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
11631 ins_pipe(ialu_cr_reg_mem);
11632 %}
11633
11634 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
11635 %{
11636 match(Set cr (CmpI (LoadB mem) imm));
11637
11638 ins_cost(125);
11639 format %{ "cmpb $mem, $imm" %}
11640 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
11641 ins_pipe(ialu_cr_reg_mem);
11642 %}
11643
11644 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
11645 %{
11646 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
11647
11648 ins_cost(125);
11649 format %{ "testb $mem, $imm" %}
11650 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
11651 ins_pipe(ialu_cr_reg_mem);
11652 %}
11653
11654 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
11655 %{
11656 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
11657
11658 ins_cost(125);
11659 format %{ "testb $mem, $imm" %}
11660 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
11661 ins_pipe(ialu_cr_reg_mem);
11662 %}
11663
11664 //----------Max and Min--------------------------------------------------------
11665 // Min Instructions
11666
11667 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11668 %{
11669 effect(USE_DEF dst, USE src, USE cr);
11670
11671 format %{ "cmovlgt $dst, $src\t# min" %}
11672 opcode(0x0F, 0x4F);
11673 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11674 ins_pipe(pipe_cmov_reg);
11675 %}
11676
11677
11678 instruct minI_rReg(rRegI dst, rRegI src)
11679 %{
11680 match(Set dst (MinI dst src));
11681
11682 ins_cost(200);
11683 expand %{
11684 rFlagsReg cr;
11685 compI_rReg(cr, dst, src);
11686 cmovI_reg_g(dst, src, cr);
11687 %}
11688 %}
11689
11690 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11691 %{
11692 effect(USE_DEF dst, USE src, USE cr);
11693
11694 format %{ "cmovllt $dst, $src\t# max" %}
11695 opcode(0x0F, 0x4C);
11696 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11697 ins_pipe(pipe_cmov_reg);
11698 %}
11699
11700
11701 instruct maxI_rReg(rRegI dst, rRegI src)
11702 %{
11703 match(Set dst (MaxI dst src));
11704
11705 ins_cost(200);
11706 expand %{
11707 rFlagsReg cr;
11708 compI_rReg(cr, dst, src);
11709 cmovI_reg_l(dst, src, cr);
11710 %}
11711 %}
11712
11713 // ============================================================================
11714 // Branch Instructions
11715
11716 // Jump Direct - Label defines a relative address from JMP+1
11717 instruct jmpDir(label labl)
11718 %{
11719 match(Goto);
11720 effect(USE labl);
11721
11722 ins_cost(300);
11723 format %{ "jmp $labl" %}
11724 size(5);
11725 ins_encode %{
11726 Label* L = $labl$$label;
11727 __ jmp(*L, false); // Always long jump
11728 %}
11729 ins_pipe(pipe_jmp);
11730 %}
11731
11732 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11733 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11734 %{
11735 match(If cop cr);
11736 effect(USE labl);
11737
11738 ins_cost(300);
11739 format %{ "j$cop $labl" %}
11740 size(6);
11741 ins_encode %{
11742 Label* L = $labl$$label;
11743 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11744 %}
11745 ins_pipe(pipe_jcc);
11746 %}
11747
11748 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11749 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11750 %{
11751 predicate(!n->has_vector_mask_set());
11752 match(CountedLoopEnd cop cr);
11753 effect(USE labl);
11754
11755 ins_cost(300);
11756 format %{ "j$cop $labl\t# loop end" %}
11757 size(6);
11758 ins_encode %{
11759 Label* L = $labl$$label;
11760 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11761 %}
11762 ins_pipe(pipe_jcc);
11763 %}
11764
11765 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11766 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11767 predicate(!n->has_vector_mask_set());
11768 match(CountedLoopEnd cop cmp);
11769 effect(USE labl);
11770
11771 ins_cost(300);
11772 format %{ "j$cop,u $labl\t# loop end" %}
11773 size(6);
11774 ins_encode %{
11775 Label* L = $labl$$label;
11776 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11777 %}
11778 ins_pipe(pipe_jcc);
11779 %}
11780
11781 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11782 predicate(!n->has_vector_mask_set());
11783 match(CountedLoopEnd cop cmp);
11784 effect(USE labl);
11785
11786 ins_cost(200);
11787 format %{ "j$cop,u $labl\t# loop end" %}
11788 size(6);
11789 ins_encode %{
11790 Label* L = $labl$$label;
11791 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11792 %}
11793 ins_pipe(pipe_jcc);
11794 %}
11795
11796 // mask version
11797 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11798 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
11799 %{
11800 predicate(n->has_vector_mask_set());
11801 match(CountedLoopEnd cop cr);
11802 effect(USE labl);
11803
11804 ins_cost(400);
11805 format %{ "j$cop $labl\t# loop end\n\t"
11806 "restorevectmask \t# vector mask restore for loops" %}
11807 size(10);
11808 ins_encode %{
11809 Label* L = $labl$$label;
11810 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11811 __ restorevectmask();
11812 %}
11813 ins_pipe(pipe_jcc);
11814 %}
11815
11816 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11817 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11818 predicate(n->has_vector_mask_set());
11819 match(CountedLoopEnd cop cmp);
11820 effect(USE labl);
11821
11822 ins_cost(400);
11823 format %{ "j$cop,u $labl\t# loop end\n\t"
11824 "restorevectmask \t# vector mask restore for loops" %}
11825 size(10);
11826 ins_encode %{
11827 Label* L = $labl$$label;
11828 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11829 __ restorevectmask();
11830 %}
11831 ins_pipe(pipe_jcc);
11832 %}
11833
11834 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11835 predicate(n->has_vector_mask_set());
11836 match(CountedLoopEnd cop cmp);
11837 effect(USE labl);
11838
11839 ins_cost(300);
11840 format %{ "j$cop,u $labl\t# loop end\n\t"
11841 "restorevectmask \t# vector mask restore for loops" %}
11842 size(10);
11843 ins_encode %{
11844 Label* L = $labl$$label;
11845 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11846 __ restorevectmask();
11847 %}
11848 ins_pipe(pipe_jcc);
11849 %}
11850
11851 // Jump Direct Conditional - using unsigned comparison
11852 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11853 match(If cop cmp);
11854 effect(USE labl);
11855
11856 ins_cost(300);
11857 format %{ "j$cop,u $labl" %}
11858 size(6);
11859 ins_encode %{
11860 Label* L = $labl$$label;
11861 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11862 %}
11863 ins_pipe(pipe_jcc);
11864 %}
11865
11866 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11867 match(If cop cmp);
11868 effect(USE labl);
11869
11870 ins_cost(200);
11871 format %{ "j$cop,u $labl" %}
11872 size(6);
11873 ins_encode %{
11874 Label* L = $labl$$label;
11875 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11876 %}
11877 ins_pipe(pipe_jcc);
11878 %}
11879
11880 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11881 match(If cop cmp);
11882 effect(USE labl);
11883
11884 ins_cost(200);
11885 format %{ $$template
11886 if ($cop$$cmpcode == Assembler::notEqual) {
11887 $$emit$$"jp,u $labl\n\t"
11888 $$emit$$"j$cop,u $labl"
11889 } else {
11890 $$emit$$"jp,u done\n\t"
11891 $$emit$$"j$cop,u $labl\n\t"
11892 $$emit$$"done:"
11893 }
11894 %}
11895 ins_encode %{
11896 Label* l = $labl$$label;
11897 if ($cop$$cmpcode == Assembler::notEqual) {
11898 __ jcc(Assembler::parity, *l, false);
11899 __ jcc(Assembler::notEqual, *l, false);
11900 } else if ($cop$$cmpcode == Assembler::equal) {
11901 Label done;
11902 __ jccb(Assembler::parity, done);
11903 __ jcc(Assembler::equal, *l, false);
11904 __ bind(done);
11905 } else {
11906 ShouldNotReachHere();
11907 }
11908 %}
11909 ins_pipe(pipe_jcc);
11910 %}
11911
11912 // ============================================================================
11913 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11914 // superklass array for an instance of the superklass. Set a hidden
11915 // internal cache on a hit (cache is checked with exposed code in
11916 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11917 // encoding ALSO sets flags.
11918
11919 instruct partialSubtypeCheck(rdi_RegP result,
11920 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11921 rFlagsReg cr)
11922 %{
11923 match(Set result (PartialSubtypeCheck sub super));
11924 effect(KILL rcx, KILL cr);
11925
11926 ins_cost(1100); // slightly larger than the next version
11927 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11928 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11929 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11930 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11931 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11932 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11933 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11934 "miss:\t" %}
11935
11936 opcode(0x1); // Force a XOR of RDI
11937 ins_encode(enc_PartialSubtypeCheck());
11938 ins_pipe(pipe_slow);
11939 %}
11940
11941 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11942 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11943 immP0 zero,
11944 rdi_RegP result)
11945 %{
11946 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11947 effect(KILL rcx, KILL result);
11948
11949 ins_cost(1000);
11950 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11951 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11952 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11953 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11954 "jne,s miss\t\t# Missed: flags nz\n\t"
11955 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11956 "miss:\t" %}
11957
11958 opcode(0x0); // No need to XOR RDI
11959 ins_encode(enc_PartialSubtypeCheck());
11960 ins_pipe(pipe_slow);
11961 %}
11962
11963 // ============================================================================
11964 // Branch Instructions -- short offset versions
11965 //
11966 // These instructions are used to replace jumps of a long offset (the default
11967 // match) with jumps of a shorter offset. These instructions are all tagged
11968 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11969 // match rules in general matching. Instead, the ADLC generates a conversion
11970 // method in the MachNode which can be used to do in-place replacement of the
11971 // long variant with the shorter variant. The compiler will determine if a
11972 // branch can be taken by the is_short_branch_offset() predicate in the machine
11973 // specific code section of the file.
11974
11975 // Jump Direct - Label defines a relative address from JMP+1
11976 instruct jmpDir_short(label labl) %{
11977 match(Goto);
11978 effect(USE labl);
11979
11980 ins_cost(300);
11981 format %{ "jmp,s $labl" %}
11982 size(2);
11983 ins_encode %{
11984 Label* L = $labl$$label;
11985 __ jmpb(*L);
11986 %}
11987 ins_pipe(pipe_jmp);
11988 ins_short_branch(1);
11989 %}
11990
11991 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11992 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11993 match(If cop cr);
11994 effect(USE labl);
11995
11996 ins_cost(300);
11997 format %{ "j$cop,s $labl" %}
11998 size(2);
11999 ins_encode %{
12000 Label* L = $labl$$label;
12001 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12002 %}
12003 ins_pipe(pipe_jcc);
12004 ins_short_branch(1);
12005 %}
12006
12007 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12008 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12009 match(CountedLoopEnd cop cr);
12010 effect(USE labl);
12011
12012 ins_cost(300);
12013 format %{ "j$cop,s $labl\t# loop end" %}
12014 size(2);
12015 ins_encode %{
12016 Label* L = $labl$$label;
12017 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12018 %}
12019 ins_pipe(pipe_jcc);
12020 ins_short_branch(1);
12021 %}
12022
12023 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12024 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12025 match(CountedLoopEnd cop cmp);
12026 effect(USE labl);
12027
12028 ins_cost(300);
12029 format %{ "j$cop,us $labl\t# loop end" %}
12030 size(2);
12031 ins_encode %{
12032 Label* L = $labl$$label;
12033 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12034 %}
12035 ins_pipe(pipe_jcc);
12036 ins_short_branch(1);
12037 %}
12038
12039 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12040 match(CountedLoopEnd cop cmp);
12041 effect(USE labl);
12042
12043 ins_cost(300);
12044 format %{ "j$cop,us $labl\t# loop end" %}
12045 size(2);
12046 ins_encode %{
12047 Label* L = $labl$$label;
12048 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12049 %}
12050 ins_pipe(pipe_jcc);
12051 ins_short_branch(1);
12052 %}
12053
12054 // Jump Direct Conditional - using unsigned comparison
12055 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12056 match(If cop cmp);
12057 effect(USE labl);
12058
12059 ins_cost(300);
12060 format %{ "j$cop,us $labl" %}
12061 size(2);
12062 ins_encode %{
12063 Label* L = $labl$$label;
12064 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12065 %}
12066 ins_pipe(pipe_jcc);
12067 ins_short_branch(1);
12068 %}
12069
12070 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12071 match(If cop cmp);
12072 effect(USE labl);
12073
12074 ins_cost(300);
12075 format %{ "j$cop,us $labl" %}
12076 size(2);
12077 ins_encode %{
12078 Label* L = $labl$$label;
12079 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12080 %}
12081 ins_pipe(pipe_jcc);
12082 ins_short_branch(1);
12083 %}
12084
12085 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12086 match(If cop cmp);
12087 effect(USE labl);
12088
12089 ins_cost(300);
12090 format %{ $$template
12091 if ($cop$$cmpcode == Assembler::notEqual) {
12092 $$emit$$"jp,u,s $labl\n\t"
12093 $$emit$$"j$cop,u,s $labl"
12094 } else {
12095 $$emit$$"jp,u,s done\n\t"
12096 $$emit$$"j$cop,u,s $labl\n\t"
12097 $$emit$$"done:"
12098 }
12099 %}
12100 size(4);
12101 ins_encode %{
12102 Label* l = $labl$$label;
12103 if ($cop$$cmpcode == Assembler::notEqual) {
12104 __ jccb(Assembler::parity, *l);
12105 __ jccb(Assembler::notEqual, *l);
12106 } else if ($cop$$cmpcode == Assembler::equal) {
12107 Label done;
12108 __ jccb(Assembler::parity, done);
12109 __ jccb(Assembler::equal, *l);
12110 __ bind(done);
12111 } else {
12112 ShouldNotReachHere();
12113 }
12114 %}
12115 ins_pipe(pipe_jcc);
12116 ins_short_branch(1);
12117 %}
12118
12119 // ============================================================================
12120 // inlined locking and unlocking
12121
12122 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12123 predicate(Compile::current()->use_rtm());
12124 match(Set cr (FastLock object box));
12125 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12126 ins_cost(300);
12127 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12128 ins_encode %{
12129 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12130 $scr$$Register, $cx1$$Register, $cx2$$Register,
12131 _counters, _rtm_counters, _stack_rtm_counters,
12132 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12133 true, ra_->C->profile_rtm());
12134 %}
12135 ins_pipe(pipe_slow);
12136 %}
12137
12138 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12139 predicate(!Compile::current()->use_rtm());
12140 match(Set cr (FastLock object box));
12141 effect(TEMP tmp, TEMP scr, USE_KILL box);
12142 ins_cost(300);
12143 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12144 ins_encode %{
12145 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12146 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12147 %}
12148 ins_pipe(pipe_slow);
12149 %}
12150
12151 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12152 match(Set cr (FastUnlock object box));
12153 effect(TEMP tmp, USE_KILL box);
12154 ins_cost(300);
12155 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12156 ins_encode %{
12157 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12158 %}
12159 ins_pipe(pipe_slow);
12160 %}
12161
12162
12163 // ============================================================================
12164 // Safepoint Instructions
12165 instruct safePoint_poll(rFlagsReg cr)
12166 %{
12167 predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12168 match(SafePoint);
12169 effect(KILL cr);
12170
12171 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12172 "# Safepoint: poll for GC" %}
12173 ins_cost(125);
12174 ins_encode %{
12175 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12176 __ testl(rax, addr);
12177 %}
12178 ins_pipe(ialu_reg_mem);
12179 %}
12180
12181 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12182 %{
12183 predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12184 match(SafePoint poll);
12185 effect(KILL cr, USE poll);
12186
12187 format %{ "testl rax, [$poll]\t"
12188 "# Safepoint: poll for GC" %}
12189 ins_cost(125);
12190 ins_encode %{
12191 __ relocate(relocInfo::poll_type);
12192 __ testl(rax, Address($poll$$Register, 0));
12193 %}
12194 ins_pipe(ialu_reg_mem);
12195 %}
12196
12197 instruct safePoint_poll_tls(rFlagsReg cr, rex_RegP poll)
12198 %{
12199 predicate(SafepointMechanism::uses_thread_local_poll());
12200 match(SafePoint poll);
12201 effect(KILL cr, USE poll);
12202
12203 format %{ "testl rax, [$poll]\t"
12204 "# Safepoint: poll for GC" %}
12205 ins_cost(125);
12206 size(3); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12207 ins_encode %{
12208 __ relocate(relocInfo::poll_type);
12209 address pre_pc = __ pc();
12210 __ testl(rax, Address($poll$$Register, 0));
12211 address post_pc = __ pc();
12212 guarantee(pre_pc[0] == 0x41 && pre_pc[1] == 0x85, "must emit #rex test-ax [reg]");
12213 %}
12214 ins_pipe(ialu_reg_mem);
12215 %}
12216
12217 // ============================================================================
12218 // Procedure Call/Return Instructions
12219 // Call Java Static Instruction
12220 // Note: If this code changes, the corresponding ret_addr_offset() and
12221 // compute_padding() functions will have to be adjusted.
12222 instruct CallStaticJavaDirect(method meth) %{
12223 match(CallStaticJava);
12224 effect(USE meth);
12225
12226 ins_cost(300);
12227 format %{ "call,static " %}
12228 opcode(0xE8); /* E8 cd */
12229 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12230 ins_pipe(pipe_slow);
12231 ins_alignment(4);
12232 %}
12233
12234 // Call Java Dynamic Instruction
12235 // Note: If this code changes, the corresponding ret_addr_offset() and
12236 // compute_padding() functions will have to be adjusted.
12237 instruct CallDynamicJavaDirect(method meth)
12238 %{
12239 match(CallDynamicJava);
12240 effect(USE meth);
12241
12242 ins_cost(300);
12243 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12244 "call,dynamic " %}
12245 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12246 ins_pipe(pipe_slow);
12247 ins_alignment(4);
12248 %}
12249
12250 // Call Runtime Instruction
12251 instruct CallRuntimeDirect(method meth)
12252 %{
12253 match(CallRuntime);
12254 effect(USE meth);
12255
12256 ins_cost(300);
12257 format %{ "call,runtime " %}
12258 ins_encode(clear_avx, Java_To_Runtime(meth));
12259 ins_pipe(pipe_slow);
12260 %}
12261
12262 // Call runtime without safepoint
12263 instruct CallLeafDirect(method meth)
12264 %{
12265 match(CallLeaf);
12266 effect(USE meth);
12267
12268 ins_cost(300);
12269 format %{ "call_leaf,runtime " %}
12270 ins_encode(clear_avx, Java_To_Runtime(meth));
12271 ins_pipe(pipe_slow);
12272 %}
12273
12274 // Call runtime without safepoint
12275 instruct CallLeafNoFPDirect(method meth)
12276 %{
12277 match(CallLeafNoFP);
12278 effect(USE meth);
12279
12280 ins_cost(300);
12281 format %{ "call_leaf_nofp,runtime " %}
12282 ins_encode(clear_avx, Java_To_Runtime(meth));
12283 ins_pipe(pipe_slow);
12284 %}
12285
12286 // Return Instruction
12287 // Remove the return address & jump to it.
12288 // Notice: We always emit a nop after a ret to make sure there is room
12289 // for safepoint patching
12290 instruct Ret()
12291 %{
12292 match(Return);
12293
12294 format %{ "ret" %}
12295 opcode(0xC3);
12296 ins_encode(OpcP);
12297 ins_pipe(pipe_jmp);
12298 %}
12299
12300 // Tail Call; Jump from runtime stub to Java code.
12301 // Also known as an 'interprocedural jump'.
12302 // Target of jump will eventually return to caller.
12303 // TailJump below removes the return address.
12304 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12305 %{
12306 match(TailCall jump_target method_oop);
12307
12308 ins_cost(300);
12309 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12310 opcode(0xFF, 0x4); /* Opcode FF /4 */
12311 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12312 ins_pipe(pipe_jmp);
12313 %}
12314
12315 // Tail Jump; remove the return address; jump to target.
12316 // TailCall above leaves the return address around.
12317 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12318 %{
12319 match(TailJump jump_target ex_oop);
12320
12321 ins_cost(300);
12322 format %{ "popq rdx\t# pop return address\n\t"
12323 "jmp $jump_target" %}
12324 opcode(0xFF, 0x4); /* Opcode FF /4 */
12325 ins_encode(Opcode(0x5a), // popq rdx
12326 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12327 ins_pipe(pipe_jmp);
12328 %}
12329
12330 // Create exception oop: created by stack-crawling runtime code.
12331 // Created exception is now available to this handler, and is setup
12332 // just prior to jumping to this handler. No code emitted.
12333 instruct CreateException(rax_RegP ex_oop)
12334 %{
12335 match(Set ex_oop (CreateEx));
12336
12337 size(0);
12338 // use the following format syntax
12339 format %{ "# exception oop is in rax; no code emitted" %}
12340 ins_encode();
12341 ins_pipe(empty);
12342 %}
12343
12344 // Rethrow exception:
12345 // The exception oop will come in the first argument position.
12346 // Then JUMP (not call) to the rethrow stub code.
12347 instruct RethrowException()
12348 %{
12349 match(Rethrow);
12350
12351 // use the following format syntax
12352 format %{ "jmp rethrow_stub" %}
12353 ins_encode(enc_rethrow);
12354 ins_pipe(pipe_jmp);
12355 %}
12356
12357
12358 // ============================================================================
12359 // This name is KNOWN by the ADLC and cannot be changed.
12360 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12361 // for this guy.
12362 instruct tlsLoadP(r15_RegP dst) %{
12363 match(Set dst (ThreadLocal));
12364 effect(DEF dst);
12365
12366 size(0);
12367 format %{ "# TLS is in R15" %}
12368 ins_encode( /*empty encoding*/ );
12369 ins_pipe(ialu_reg_reg);
12370 %}
12371
12372
12373 //----------PEEPHOLE RULES-----------------------------------------------------
12374 // These must follow all instruction definitions as they use the names
12375 // defined in the instructions definitions.
12376 //
12377 // peepmatch ( root_instr_name [preceding_instruction]* );
12378 //
12379 // peepconstraint %{
12380 // (instruction_number.operand_name relational_op instruction_number.operand_name
12381 // [, ...] );
12382 // // instruction numbers are zero-based using left to right order in peepmatch
12383 //
12384 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12385 // // provide an instruction_number.operand_name for each operand that appears
12386 // // in the replacement instruction's match rule
12387 //
12388 // ---------VM FLAGS---------------------------------------------------------
12389 //
12390 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12391 //
12392 // Each peephole rule is given an identifying number starting with zero and
12393 // increasing by one in the order seen by the parser. An individual peephole
12394 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12395 // on the command-line.
12396 //
12397 // ---------CURRENT LIMITATIONS----------------------------------------------
12398 //
12399 // Only match adjacent instructions in same basic block
12400 // Only equality constraints
12401 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12402 // Only one replacement instruction
12403 //
12404 // ---------EXAMPLE----------------------------------------------------------
12405 //
12406 // // pertinent parts of existing instructions in architecture description
12407 // instruct movI(rRegI dst, rRegI src)
12408 // %{
12409 // match(Set dst (CopyI src));
12410 // %}
12411 //
12412 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12413 // %{
12414 // match(Set dst (AddI dst src));
12415 // effect(KILL cr);
12416 // %}
12417 //
12418 // // Change (inc mov) to lea
12419 // peephole %{
12420 // // increment preceeded by register-register move
12421 // peepmatch ( incI_rReg movI );
12422 // // require that the destination register of the increment
12423 // // match the destination register of the move
12424 // peepconstraint ( 0.dst == 1.dst );
12425 // // construct a replacement instruction that sets
12426 // // the destination to ( move's source register + one )
12427 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12428 // %}
12429 //
12430
12431 // Implementation no longer uses movX instructions since
12432 // machine-independent system no longer uses CopyX nodes.
12433 //
12434 // peephole
12435 // %{
12436 // peepmatch (incI_rReg movI);
12437 // peepconstraint (0.dst == 1.dst);
12438 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12439 // %}
12440
12441 // peephole
12442 // %{
12443 // peepmatch (decI_rReg movI);
12444 // peepconstraint (0.dst == 1.dst);
12445 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12446 // %}
12447
12448 // peephole
12449 // %{
12450 // peepmatch (addI_rReg_imm movI);
12451 // peepconstraint (0.dst == 1.dst);
12452 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12453 // %}
12454
12455 // peephole
12456 // %{
12457 // peepmatch (incL_rReg movL);
12458 // peepconstraint (0.dst == 1.dst);
12459 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12460 // %}
12461
12462 // peephole
12463 // %{
12464 // peepmatch (decL_rReg movL);
12465 // peepconstraint (0.dst == 1.dst);
12466 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12467 // %}
12468
12469 // peephole
12470 // %{
12471 // peepmatch (addL_rReg_imm movL);
12472 // peepconstraint (0.dst == 1.dst);
12473 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12474 // %}
12475
12476 // peephole
12477 // %{
12478 // peepmatch (addP_rReg_imm movP);
12479 // peepconstraint (0.dst == 1.dst);
12480 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12481 // %}
12482
12483 // // Change load of spilled value to only a spill
12484 // instruct storeI(memory mem, rRegI src)
12485 // %{
12486 // match(Set mem (StoreI mem src));
12487 // %}
12488 //
12489 // instruct loadI(rRegI dst, memory mem)
12490 // %{
12491 // match(Set dst (LoadI mem));
12492 // %}
12493 //
12494
12495 peephole
12496 %{
12497 peepmatch (loadI storeI);
12498 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12499 peepreplace (storeI(1.mem 1.mem 1.src));
12500 %}
12501
12502 peephole
12503 %{
12504 peepmatch (loadL storeL);
12505 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12506 peepreplace (storeL(1.mem 1.mem 1.src));
12507 %}
12508
12509 //----------SMARTSPILL RULES---------------------------------------------------
12510 // These must follow all instruction definitions as they use the names
12511 // defined in the instructions definitions.