< prev index next >

src/cpu/arm/vm/vm_version_arm_64.cpp

Print this page




 184 
 185   if (UseAESCTRIntrinsics) {
 186     warning("AES/CTR intrinsics are not available on this CPU");
 187     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 188   }
 189 
 190   _supports_cx8 = true;
 191   _supports_atomic_getset4 = true;
 192   _supports_atomic_getadd4 = true;
 193   _supports_atomic_getset8 = true;
 194   _supports_atomic_getadd8 = true;
 195 
 196   // TODO-AARCH64 revise C2 flags
 197 
 198   if (has_simd()) {
 199     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 200       FLAG_SET_DEFAULT(UsePopCountInstruction, true);
 201     }
 202   }
 203 

 204   AllocatePrefetchDistance = 128;

 205 
 206 #ifdef COMPILER2
 207   FLAG_SET_DEFAULT(UseFPUForSpilling, true);
 208 
 209   if (FLAG_IS_DEFAULT(MaxVectorSize)) {
 210     // FLAG_SET_DEFAULT(MaxVectorSize, has_simd() ? 16 : 8);
 211     // SIMD/NEON can use 16, but default is 8 because currently
 212     // larger than 8 will disable instruction scheduling
 213     FLAG_SET_DEFAULT(MaxVectorSize, 8);
 214   }
 215 
 216   if (MaxVectorSize > 16) {
 217     FLAG_SET_DEFAULT(MaxVectorSize, 8);
 218   }
 219 #endif
 220 
 221   if (FLAG_IS_DEFAULT(Tier4CompileThreshold)) {
 222     Tier4CompileThreshold = 10000;
 223   }
 224   if (FLAG_IS_DEFAULT(Tier3InvocationThreshold)) {




 184 
 185   if (UseAESCTRIntrinsics) {
 186     warning("AES/CTR intrinsics are not available on this CPU");
 187     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 188   }
 189 
 190   _supports_cx8 = true;
 191   _supports_atomic_getset4 = true;
 192   _supports_atomic_getadd4 = true;
 193   _supports_atomic_getset8 = true;
 194   _supports_atomic_getadd8 = true;
 195 
 196   // TODO-AARCH64 revise C2 flags
 197 
 198   if (has_simd()) {
 199     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 200       FLAG_SET_DEFAULT(UsePopCountInstruction, true);
 201     }
 202   }
 203 
 204   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
 205     AllocatePrefetchDistance = 128;
 206   }
 207 
 208 #ifdef COMPILER2
 209   FLAG_SET_DEFAULT(UseFPUForSpilling, true);
 210 
 211   if (FLAG_IS_DEFAULT(MaxVectorSize)) {
 212     // FLAG_SET_DEFAULT(MaxVectorSize, has_simd() ? 16 : 8);
 213     // SIMD/NEON can use 16, but default is 8 because currently
 214     // larger than 8 will disable instruction scheduling
 215     FLAG_SET_DEFAULT(MaxVectorSize, 8);
 216   }
 217 
 218   if (MaxVectorSize > 16) {
 219     FLAG_SET_DEFAULT(MaxVectorSize, 8);
 220   }
 221 #endif
 222 
 223   if (FLAG_IS_DEFAULT(Tier4CompileThreshold)) {
 224     Tier4CompileThreshold = 10000;
 225   }
 226   if (FLAG_IS_DEFAULT(Tier3InvocationThreshold)) {


< prev index next >