239 #ifdef COMPILER2
240 assert(_supports_cx8 && _supports_atomic_getset4 && _supports_atomic_getadd4
241 && _supports_atomic_getset8 && _supports_atomic_getadd8, "C2: atomic operations must be supported");
242 #endif
243 char buf[512];
244 jio_snprintf(buf, sizeof(buf), "(ARMv%d)%s%s%s",
245 _arm_arch,
246 (has_vfp() ? ", vfp" : ""),
247 (has_vfp3_32() ? ", vfp3-32" : ""),
248 (has_simd() ? ", simd" : ""));
249
250 // buf is started with ", " or is empty
251 _features_string = os::strdup(buf);
252
253 if (has_simd()) {
254 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
255 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
256 }
257 }
258
259 AllocatePrefetchDistance = 128;
260
261 #ifdef COMPILER2
262 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
263
264 if (FLAG_IS_DEFAULT(MaxVectorSize)) {
265 // FLAG_SET_DEFAULT(MaxVectorSize, has_simd() ? 16 : 8);
266 // SIMD/NEON can use 16, but default is 8 because currently
267 // larger than 8 will disable instruction scheduling
268 FLAG_SET_DEFAULT(MaxVectorSize, 8);
269 }
270
271 if (MaxVectorSize > 16) {
272 FLAG_SET_DEFAULT(MaxVectorSize, 8);
273 }
274 #endif
275
276 if (FLAG_IS_DEFAULT(Tier4CompileThreshold)) {
277 Tier4CompileThreshold = 10000;
278 }
279 if (FLAG_IS_DEFAULT(Tier3InvocationThreshold)) {
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239 #ifdef COMPILER2
240 assert(_supports_cx8 && _supports_atomic_getset4 && _supports_atomic_getadd4
241 && _supports_atomic_getset8 && _supports_atomic_getadd8, "C2: atomic operations must be supported");
242 #endif
243 char buf[512];
244 jio_snprintf(buf, sizeof(buf), "(ARMv%d)%s%s%s",
245 _arm_arch,
246 (has_vfp() ? ", vfp" : ""),
247 (has_vfp3_32() ? ", vfp3-32" : ""),
248 (has_simd() ? ", simd" : ""));
249
250 // buf is started with ", " or is empty
251 _features_string = os::strdup(buf);
252
253 if (has_simd()) {
254 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
255 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
256 }
257 }
258
259 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
260 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 128);
261 }
262
263 #ifdef COMPILER2
264 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
265
266 if (FLAG_IS_DEFAULT(MaxVectorSize)) {
267 // FLAG_SET_DEFAULT(MaxVectorSize, has_simd() ? 16 : 8);
268 // SIMD/NEON can use 16, but default is 8 because currently
269 // larger than 8 will disable instruction scheduling
270 FLAG_SET_DEFAULT(MaxVectorSize, 8);
271 }
272
273 if (MaxVectorSize > 16) {
274 FLAG_SET_DEFAULT(MaxVectorSize, 8);
275 }
276 #endif
277
278 if (FLAG_IS_DEFAULT(Tier4CompileThreshold)) {
279 Tier4CompileThreshold = 10000;
280 }
281 if (FLAG_IS_DEFAULT(Tier3InvocationThreshold)) {
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