803 intx count = AllocatePrefetchDistance;
804 if (count < 0) { // default ?
805 if (is_amd()) { // AMD
806 if (supports_sse2())
807 count = 256; // Opteron
808 else
809 count = 128; // Athlon
810 } else { // Intel
811 if (supports_sse2())
812 if (cpu_family() == 6) {
813 count = 256; // Pentium M, Core, Core2
814 } else {
815 count = 512; // Pentium 4
816 }
817 else
818 count = 128; // Pentium 3 (and all other old CPUs)
819 }
820 }
821 return count;
822 }
823 static intx allocate_prefetch_style() {
824 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
825 // Return 0 if AllocatePrefetchDistance was not defined.
826 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
827 }
828
829 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
830 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
831 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
832 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
833
834 // gc copy/scan is disabled if prefetchw isn't supported, because
835 // Prefetch::write emits an inlined prefetchw on Linux.
836 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
837 // The used prefetcht0 instruction works for both amd64 and em64t.
838 static intx prefetch_copy_interval_in_bytes() {
839 intx interval = PrefetchCopyIntervalInBytes;
840 return interval >= 0 ? interval : 576;
841 }
842 static intx prefetch_scan_interval_in_bytes() {
843 intx interval = PrefetchScanIntervalInBytes;
844 return interval >= 0 ? interval : 576;
845 }
846 static intx prefetch_fields_ahead() {
|
803 intx count = AllocatePrefetchDistance;
804 if (count < 0) { // default ?
805 if (is_amd()) { // AMD
806 if (supports_sse2())
807 count = 256; // Opteron
808 else
809 count = 128; // Athlon
810 } else { // Intel
811 if (supports_sse2())
812 if (cpu_family() == 6) {
813 count = 256; // Pentium M, Core, Core2
814 } else {
815 count = 512; // Pentium 4
816 }
817 else
818 count = 128; // Pentium 3 (and all other old CPUs)
819 }
820 }
821 return count;
822 }
823
824 static intx allocate_prefetch_style() {
825 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
826 // Return 0 if AllocatePrefetchDistance was not defined.
827 if (AllocatePrefetchDistance > 0) {
828 return AllocatePrefetchStyle;
829 } else {
830 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle) && (AllocatePrefetchStyle != 0)) {
831 warning("AllocatePrefetchDistance is not set. Ignoring AllocatePrefetchStyle flag.");
832 }
833 return 0;
834 }
835 }
836
837 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
838 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
839 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
840 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
841
842 // gc copy/scan is disabled if prefetchw isn't supported, because
843 // Prefetch::write emits an inlined prefetchw on Linux.
844 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
845 // The used prefetcht0 instruction works for both amd64 and em64t.
846 static intx prefetch_copy_interval_in_bytes() {
847 intx interval = PrefetchCopyIntervalInBytes;
848 return interval >= 0 ? interval : 576;
849 }
850 static intx prefetch_scan_interval_in_bytes() {
851 intx interval = PrefetchScanIntervalInBytes;
852 return interval >= 0 ? interval : 576;
853 }
854 static intx prefetch_fields_ahead() {
|