1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
41 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, prefetch_copy_interval_in_bytes());
42 }
43 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
44 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, prefetch_scan_interval_in_bytes());
45 }
46 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
47 FLAG_SET_DEFAULT(PrefetchFieldsAhead, prefetch_fields_ahead());
48 }
49
50 // Allocation prefetch settings
51 intx cache_line_size = prefetch_data_size();
52 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
53 (cache_line_size > AllocatePrefetchStepSize)) {
54 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
55 }
56
57 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
58 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 512);
59 }
60
61 if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
62 assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
63 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
64 warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
65 }
66 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
67 }
68
69 if ((AllocatePrefetchInstr == 1) && (!has_blk_init() || cache_line_size <= 0)) {
70 if (!FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
71 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
72 }
73 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
74 }
75
76 UseSSE = 0; // Only on x86 and x64
77
78 _supports_cx8 = has_v9();
79 _supports_atomic_getset4 = true; // swap instruction
80
81 if (is_niagara()) {
82 // Indirect branch is the same cost as direct
83 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
84 FLAG_SET_DEFAULT(UseInlineCaches, false);
85 }
86 // Align loops on a single instruction boundary.
87 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
88 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
89 }
90 // 32-bit oops don't make sense for the 64-bit VM on sparc
91 // since the 32-bit VM has the same registers and smaller objects.
92 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
93 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
94 #ifdef COMPILER2
95 // Indirect branch is the same cost as direct
96 if (FLAG_IS_DEFAULT(UseJumpTables)) {
97 FLAG_SET_DEFAULT(UseJumpTables, true);
98 }
99 // Single-issue, so entry and loop tops are
100 // aligned on a single instruction boundary
101 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
102 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
103 }
104 if (is_niagara_plus()) {
105 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
106 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
107 if (!has_sparc5_instr()) {
108 // Use BIS instruction for TLAB allocation prefetch
109 // on Niagara plus processors other than those based on CoreS4
110 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
111 } else {
112 // On CoreS4 processors use prefetch instruction
113 // to avoid partial RAW issue, also use prefetch style 3
114 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
115 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
116 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
117 }
118 }
119 }
120 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
121 if (AllocatePrefetchInstr == 0) {
122 // Use different prefetch distance without BIS
123 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
124 } else {
125 // Use smaller prefetch distance with BIS
126 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
127 }
128 }
129 if (is_T4()) {
130 // Double number of prefetched cache lines on T4
131 // since L2 cache line size is smaller (32 bytes).
132 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
133 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
134 }
135 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
136 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
137 }
138 }
139 }
140
141 if ((AllocatePrefetchInstr == 1) && (AllocatePrefetchStyle != 3)) {
142 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
143 warning("AllocatePrefetchStyle set to 3 because BIS instructions require aligned memory addresses");
144 }
145 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
146 }
147 #endif /* COMPILER2 */
148 }
149
150 // Use hardware population count instruction if available.
151 if (has_hardware_popc()) {
152 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
153 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
154 }
155 } else if (UsePopCountInstruction) {
156 warning("POPC instruction is not available on this CPU");
157 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
158 }
159
160 // T4 and newer Sparc cpus have new compare and branch instruction.
161 if (has_cbcond()) {
162 if (FLAG_IS_DEFAULT(UseCBCond)) {
163 FLAG_SET_DEFAULT(UseCBCond, true);
164 }
165 } else if (UseCBCond) {
166 warning("CBCOND instruction is not available on this CPU");
167 FLAG_SET_DEFAULT(UseCBCond, false);
168 }
169
170 assert(BlockZeroingLowLimit > 0, "invalid value");
171 if (has_block_zeroing() && cache_line_size > 0) {
172 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
173 FLAG_SET_DEFAULT(UseBlockZeroing, true);
174 }
175 } else if (UseBlockZeroing) {
176 warning("BIS zeroing instructions are not available on this CPU");
177 FLAG_SET_DEFAULT(UseBlockZeroing, false);
178 }
179
180 assert(BlockCopyLowLimit > 0, "invalid value");
181 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
182 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
183 FLAG_SET_DEFAULT(UseBlockCopy, true);
184 }
185 } else if (UseBlockCopy) {
186 warning("BIS instructions are not available or expensive on this CPU");
187 FLAG_SET_DEFAULT(UseBlockCopy, false);
188 }
189
190 #ifdef COMPILER2
191 // T4 and newer Sparc cpus have fast RDPC.
192 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
193 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
194 }
195
196 // Currently not supported anywhere.
197 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
198
199 MaxVectorSize = 8;
200
201 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
202 #endif
203
204 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
205 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
206
207 char buf[512];
208 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
209 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
210 (has_hardware_popc() ? ", popc" : ""),
211 (has_vis1() ? ", vis1" : ""),
212 (has_vis2() ? ", vis2" : ""),
213 (has_vis3() ? ", vis3" : ""),
214 (has_blk_init() ? ", blk_init" : ""),
215 (has_cbcond() ? ", cbcond" : ""),
216 (has_aes() ? ", aes" : ""),
217 (has_sha1() ? ", sha1" : ""),
218 (has_sha256() ? ", sha256" : ""),
219 (has_sha512() ? ", sha512" : ""),
220 (has_crc32c() ? ", crc32c" : ""),
221 (is_ultra3() ? ", ultra3" : ""),
222 (has_sparc5_instr() ? ", sparc5" : ""),
223 (is_sun4v() ? ", sun4v" : ""),
224 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
225 (is_sparc64() ? ", sparc64" : ""),
226 (!has_hardware_mul32() ? ", no-mul32" : ""),
227 (!has_hardware_div32() ? ", no-div32" : ""),
228 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
229
230 // buf is started with ", " or is empty
231 _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
232
233 // UseVIS is set to the smallest of what hardware supports and what
234 // the command line requires. I.e., you cannot set UseVIS to 3 on
235 // older UltraSparc which do not support it.
236 if (UseVIS > 3) UseVIS=3;
237 if (UseVIS < 0) UseVIS=0;
238 if (!has_vis3()) // Drop to 2 if no VIS3 support
239 UseVIS = MIN2((intx)2,UseVIS);
240 if (!has_vis2()) // Drop to 1 if no VIS2 support
241 UseVIS = MIN2((intx)1,UseVIS);
242 if (!has_vis1()) // Drop to 0 if no VIS1 support
243 UseVIS = 0;
244
245 // SPARC T4 and above should have support for AES instructions
246 if (has_aes()) {
247 if (FLAG_IS_DEFAULT(UseAES)) {
248 FLAG_SET_DEFAULT(UseAES, true);
249 }
250 if (!UseAES) {
251 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
252 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
253 }
254 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
255 } else {
256 // The AES intrinsic stubs require AES instruction support (of course)
257 // but also require VIS3 mode or higher for instructions it use.
258 if (UseVIS > 2) {
259 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
260 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
261 }
262 } else {
263 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
264 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
265 }
266 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
267 }
268 }
269 } else if (UseAES || UseAESIntrinsics) {
270 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
271 warning("AES instructions are not available on this CPU");
272 FLAG_SET_DEFAULT(UseAES, false);
273 }
274 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
275 warning("AES intrinsics are not available on this CPU");
276 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
277 }
278 }
279
280 if (UseAESCTRIntrinsics) {
281 warning("AES/CTR intrinsics are not available on this CPU");
282 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
283 }
284
285 // GHASH/GCM intrinsics
286 if (has_vis3() && (UseVIS > 2)) {
287 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
288 UseGHASHIntrinsics = true;
289 }
290 } else if (UseGHASHIntrinsics) {
291 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
292 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
293 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
294 }
295
296 if (UseFMA) {
297 warning("FMA instructions are not available on this CPU");
298 FLAG_SET_DEFAULT(UseFMA, false);
299 }
300
301 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
302 if (has_sha1() || has_sha256() || has_sha512()) {
303 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
304 if (FLAG_IS_DEFAULT(UseSHA)) {
305 FLAG_SET_DEFAULT(UseSHA, true);
306 }
307 } else {
308 if (UseSHA) {
309 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
310 FLAG_SET_DEFAULT(UseSHA, false);
311 }
312 }
313 } else if (UseSHA) {
314 warning("SHA instructions are not available on this CPU");
315 FLAG_SET_DEFAULT(UseSHA, false);
316 }
317
318 if (UseSHA && has_sha1()) {
319 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
320 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
321 }
322 } else if (UseSHA1Intrinsics) {
323 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
324 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
325 }
326
327 if (UseSHA && has_sha256()) {
328 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
329 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
330 }
331 } else if (UseSHA256Intrinsics) {
332 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
333 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
334 }
335
336 if (UseSHA && has_sha512()) {
337 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
338 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
339 }
340 } else if (UseSHA512Intrinsics) {
341 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
342 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
343 }
344
345 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
346 FLAG_SET_DEFAULT(UseSHA, false);
347 }
348
349 // SPARC T4 and above should have support for CRC32C instruction
350 if (has_crc32c()) {
351 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
352 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
353 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
354 }
355 } else {
356 if (UseCRC32CIntrinsics) {
357 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
358 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
359 }
360 }
361 } else if (UseCRC32CIntrinsics) {
362 warning("CRC32C instruction is not available on this CPU");
363 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
364 }
365
366 if (UseVIS > 2) {
367 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
368 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
369 }
370 } else if (UseAdler32Intrinsics) {
371 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
372 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
373 }
374
375 if (UseVIS > 2) {
376 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
377 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
378 }
379 } else if (UseCRC32Intrinsics) {
380 warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled");
381 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
382 }
383
384 if (UseVectorizedMismatchIntrinsic) {
385 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
386 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
387 }
388
389 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
390 (cache_line_size > ContendedPaddingWidth))
391 ContendedPaddingWidth = cache_line_size;
392
393 // This machine does not allow unaligned memory accesses
394 if (UseUnalignedAccesses) {
395 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
396 warning("Unaligned memory access is not available on this CPU");
397 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
398 }
399
400 if (log_is_enabled(Info, os, cpu)) {
401 ResourceMark rm;
402 outputStream* log = Log(os, cpu)::info_stream();
403 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
404 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
405 log->print("Allocation");
406 if (AllocatePrefetchStyle <= 0) {
407 log->print(": no prefetching");
408 } else {
409 log->print(" prefetching: ");
410 if (AllocatePrefetchInstr == 0) {
411 log->print("PREFETCH");
412 } else if (AllocatePrefetchInstr == 1) {
413 log->print("BIS");
414 }
415 if (AllocatePrefetchLines > 1) {
416 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
417 } else {
418 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
419 }
420 }
421 if (PrefetchCopyIntervalInBytes > 0) {
422 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
423 }
424 if (PrefetchScanIntervalInBytes > 0) {
425 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
426 }
427 if (PrefetchFieldsAhead > 0) {
428 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
429 }
430 if (ContendedPaddingWidth > 0) {
431 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
432 }
433 }
434 }
435
436 void VM_Version::print_features() {
437 tty->print_cr("Version:%s", _features);
438 }
439
440 int VM_Version::determine_features() {
441 if (UseV8InstrsOnly) {
442 log_info(os, cpu)("Version is Forced-V8");
443 return generic_v8_m;
444 }
445
446 int features = platform_features(unknown_m); // platform_features() is os_arch specific
447
448 if (features == unknown_m) {
449 features = generic_v9_m;
450 log_info(os)("Cannot recognize SPARC version. Default to V9");
451 }
452
453 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
454 if (UseNiagaraInstrs) { // Force code generation for Niagara
455 if (is_T_family(features)) {
456 // Happy to accomodate...
457 } else {
458 log_info(os, cpu)("Version is Forced-Niagara");
459 features |= T_family_m;
460 }
461 } else {
462 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
463 log_info(os, cpu)("Version is Forced-Not-Niagara");
464 features &= ~(T_family_m | T1_model_m);
465 } else {
466 // Happy to accomodate...
467 }
468 }
469
470 return features;
471 }
472
473 static uint64_t saved_features = 0;
474
475 void VM_Version::allow_all() {
476 saved_features = _features;
477 _features = all_features_m;
478 }
479
480 void VM_Version::revert() {
481 _features = saved_features;
482 }
483
484 unsigned int VM_Version::calc_parallel_worker_threads() {
485 unsigned int result;
486 if (is_M_series() || is_S_series()) {
487 // for now, use same gc thread calculation for M-series and S-series as for
488 // niagara-plus. In future, we may want to tweak parameters for
489 // nof_parallel_worker_thread
490 result = nof_parallel_worker_threads(5, 16, 8);
491 } else if (is_niagara_plus()) {
492 result = nof_parallel_worker_threads(5, 16, 8);
493 } else {
494 result = nof_parallel_worker_threads(5, 8, 8);
495 }
496 return result;
497 }
498
499
500 int VM_Version::parse_features(const char* implementation) {
501 int features = unknown_m;
502 // Convert to UPPER case before compare.
503 char* impl = os::strdup_check_oom(implementation);
504
505 for (int i = 0; impl[i] != 0; i++)
506 impl[i] = (char)toupper((uint)impl[i]);
507
508 if (strstr(impl, "SPARC64") != NULL) {
509 features |= sparc64_family_m;
510 } else if (strstr(impl, "SPARC-M") != NULL) {
511 // M-series SPARC is based on T-series.
512 features |= (M_family_m | T_family_m);
513 } else if (strstr(impl, "SPARC-S") != NULL) {
514 // S-series SPARC is based on T-series.
515 features |= (S_family_m | T_family_m);
516 } else if (strstr(impl, "SPARC-T") != NULL) {
517 features |= T_family_m;
518 if (strstr(impl, "SPARC-T1") != NULL) {
519 features |= T1_model_m;
520 }
521 } else if (strstr(impl, "SUN4V-CPU") != NULL) {
522 // Generic or migration class LDOM
523 features |= T_family_m;
524 } else {
525 log_info(os, cpu)("Failed to parse CPU implementation = '%s'", impl);
526 }
527 os::free((void*)impl);
528 return features;
529 }