20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
41 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
42 PrefetchFieldsAhead = prefetch_fields_ahead();
43
44 // Allocation prefetch settings
45 intx cache_line_size = prefetch_data_size();
46 if( cache_line_size > AllocatePrefetchStepSize )
47 AllocatePrefetchStepSize = cache_line_size;
48
49 AllocatePrefetchDistance = allocate_prefetch_distance();
50 AllocatePrefetchStyle = allocate_prefetch_style();
51
52 if (!has_blk_init() || cache_line_size <= 0) {
53 if (AllocatePrefetchInstr == 1) {
54 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
55 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
56 }
57 }
58
59 UseSSE = 0; // Only on x86 and x64
60
61 _supports_cx8 = has_v9();
62 _supports_atomic_getset4 = true; // swap instruction
63
64 if (is_niagara()) {
65 // Indirect branch is the same cost as direct
66 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
67 FLAG_SET_DEFAULT(UseInlineCaches, false);
68 }
69 // Align loops on a single instruction boundary.
70 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
71 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
72 }
73 // 32-bit oops don't make sense for the 64-bit VM on sparc
74 // since the 32-bit VM has the same registers and smaller objects.
75 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
76 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
104 if (AllocatePrefetchInstr == 0) {
105 // Use different prefetch distance without BIS
106 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
107 } else {
108 // Use smaller prefetch distance with BIS
109 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
110 }
111 }
112 if (is_T4()) {
113 // Double number of prefetched cache lines on T4
114 // since L2 cache line size is smaller (32 bytes).
115 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
116 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
117 }
118 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
119 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
120 }
121 }
122 }
123
124 if (AllocatePrefetchInstr == 1) {
125 // Use allocation prefetch style 3 because BIS instructions
126 // require aligned memory addresses.
127 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
128 }
129 #endif /* COMPILER2 */
130 }
131
132 // Use hardware population count instruction if available.
133 if (has_hardware_popc()) {
134 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
135 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
136 }
137 } else if (UsePopCountInstruction) {
138 warning("POPC instruction is not available on this CPU");
139 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
140 }
141
142 // T4 and newer Sparc cpus have new compare and branch instruction.
143 if (has_cbcond()) {
144 if (FLAG_IS_DEFAULT(UseCBCond)) {
145 FLAG_SET_DEFAULT(UseCBCond, true);
146 }
|
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
41 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, prefetch_copy_interval_in_bytes());
42 }
43 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
44 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, prefetch_scan_interval_in_bytes());
45 }
46 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
47 FLAG_SET_DEFAULT(PrefetchFieldsAhead, prefetch_fields_ahead());
48 }
49
50 // Allocation prefetch settings
51 intx cache_line_size = prefetch_data_size();
52 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
53 (cache_line_size > AllocatePrefetchStepSize)) {
54 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
55 }
56
57 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
58 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 512);
59 }
60
61 if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
62 assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
63 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
64 warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
65 }
66 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
67 }
68
69 if ((AllocatePrefetchInstr == 1) && (!has_blk_init() || cache_line_size <= 0)) {
70 if (!FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
71 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
72 }
73 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
74 }
75
76 UseSSE = 0; // Only on x86 and x64
77
78 _supports_cx8 = has_v9();
79 _supports_atomic_getset4 = true; // swap instruction
80
81 if (is_niagara()) {
82 // Indirect branch is the same cost as direct
83 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
84 FLAG_SET_DEFAULT(UseInlineCaches, false);
85 }
86 // Align loops on a single instruction boundary.
87 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
88 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
89 }
90 // 32-bit oops don't make sense for the 64-bit VM on sparc
91 // since the 32-bit VM has the same registers and smaller objects.
92 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
93 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
121 if (AllocatePrefetchInstr == 0) {
122 // Use different prefetch distance without BIS
123 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
124 } else {
125 // Use smaller prefetch distance with BIS
126 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
127 }
128 }
129 if (is_T4()) {
130 // Double number of prefetched cache lines on T4
131 // since L2 cache line size is smaller (32 bytes).
132 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
133 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
134 }
135 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
136 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
137 }
138 }
139 }
140
141 if ((AllocatePrefetchInstr == 1) && (AllocatePrefetchStyle != 3)) {
142 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
143 warning("AllocatePrefetchStyle set to 3 because BIS instructions require aligned memory addresses");
144 }
145 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
146 }
147 #endif /* COMPILER2 */
148 }
149
150 // Use hardware population count instruction if available.
151 if (has_hardware_popc()) {
152 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
153 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
154 }
155 } else if (UsePopCountInstruction) {
156 warning("POPC instruction is not available on this CPU");
157 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
158 }
159
160 // T4 and newer Sparc cpus have new compare and branch instruction.
161 if (has_cbcond()) {
162 if (FLAG_IS_DEFAULT(UseCBCond)) {
163 FLAG_SET_DEFAULT(UseCBCond, true);
164 }
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