1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "logging/log.hpp"
29 #include "logging/logStream.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "vm_version_sparc.hpp"
35
36 #include <sys/mman.h>
37
38 uint VM_Version::_L2_data_cache_line_size = 0;
39
40 void VM_Version::initialize() {
41 assert(_features != 0, "System pre-initialization is not complete.");
42 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
43
44 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
45 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
46 PrefetchFieldsAhead = prefetch_fields_ahead();
47
48 // Allocation prefetch settings
49
50 AllocatePrefetchDistance = allocate_prefetch_distance();
51 AllocatePrefetchStyle = allocate_prefetch_style();
52
53 intx cache_line_size = prefetch_data_size();
54
55 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) {
56 AllocatePrefetchStepSize = MAX2(AllocatePrefetchStepSize, cache_line_size);
57 }
58
59 if (AllocatePrefetchInstr == 1) {
60 if (!has_blk_init()) {
61 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
62 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
63 }
64 if (cache_line_size <= 0) {
65 warning("Cache-line size must be known for AllocatePrefetchInstr 1 to work");
66 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
67 }
68 }
69
70 _supports_cx8 = true; // All SPARC V9 implementations.
71 _supports_atomic_getset4 = true; // Using the 'swap' instruction.
72
73 if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseInlineCaches)) {
74 // Indirect and direct branches are cost equivalent.
75 FLAG_SET_DEFAULT(UseInlineCaches, false);
76 }
77 // Align loops on the proper instruction boundary to fill the instruction
78 // fetch buffer.
79 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
80 FLAG_SET_DEFAULT(OptoLoopAlignment, VM_Version::insn_fetch_alignment);
81 }
82
83 // 32-bit oops don't make sense for the 64-bit VM on SPARC since the 32-bit
84 // VM has the same registers and smaller objects.
85 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
86 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
87
88 #ifdef COMPILER2
89 if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseJumpTables)) {
90 // Indirect and direct branches are cost equivalent.
91 FLAG_SET_DEFAULT(UseJumpTables, true);
92 }
93 // Entry and loop tops are aligned to fill the instruction fetch buffer.
94 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
95 FLAG_SET_DEFAULT(InteriorEntryAlignment, VM_Version::insn_fetch_alignment);
96 }
97 if (UseTLAB && cache_line_size > 0 &&
98 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
99 if (has_fast_bis()) {
100 // Use BIS instruction for TLAB allocation prefetch.
101 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
102 }
103 else if (has_sparc5()) {
104 // Use prefetch instruction to avoid partial RAW issue on Core C4 processors,
105 // also use prefetch style 3.
106 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
107 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
108 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
109 }
110 }
111 }
112 if (AllocatePrefetchInstr == 1) {
113 // Use allocation prefetch style 3 because BIS instructions require
114 // aligned memory addresses.
115 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
116 }
117 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
118 if (AllocatePrefetchInstr == 0) {
119 // Use different prefetch distance without BIS
120 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
121 } else {
122 // Use smaller prefetch distance with BIS
123 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
124 }
125 }
126
127 // We increase the number of prefetched cache lines, to use just a bit more
128 // aggressive approach, when the L2-cache line size is small (32 bytes), or
129 // when running on newer processor implementations, such as the Core C4.
130 bool inc_prefetch = cache_line_size > 0 && (cache_line_size < 64 || has_sparc5());
131
132 if (inc_prefetch) {
133 // We use a factor two for small cache line sizes (as before) but a slightly
134 // more conservative increase when running on more recent hardware that will
135 // benefit from just a bit more aggressive prefetching.
136 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
137 const int ap_lns = AllocatePrefetchLines;
138 const int ap_inc = cache_line_size < 64 ? ap_lns : (ap_lns + 1) / 2;
139 FLAG_SET_ERGO(intx, AllocatePrefetchLines, ap_lns + ap_inc);
140 }
141 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
142 const int ip_lns = AllocateInstancePrefetchLines;
143 const int ip_inc = cache_line_size < 64 ? ip_lns : (ip_lns + 1) / 2;
144 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, ip_lns + ip_inc);
145 }
146 }
147 #endif /* COMPILER2 */
148
149 // Use hardware population count instruction if available.
150 if (has_popc()) {
151 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
152 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
153 }
154 } else if (UsePopCountInstruction) {
155 warning("POPC instruction is not available on this CPU");
156 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
157 }
158
159 // Use compare and branch instructions if available.
160 if (has_cbcond()) {
161 if (FLAG_IS_DEFAULT(UseCBCond)) {
162 FLAG_SET_DEFAULT(UseCBCond, true);
163 }
164 } else if (UseCBCond) {
165 warning("CBCOND instruction is not available on this CPU");
166 FLAG_SET_DEFAULT(UseCBCond, false);
167 }
168
169 // Use 'mpmul' instruction if available.
170 if (has_mpmul()) {
171 if (FLAG_IS_DEFAULT(UseMPMUL)) {
172 FLAG_SET_DEFAULT(UseMPMUL, true);
173 }
174 } else if (UseMPMUL) {
175 warning("MPMUL instruction is not available on this CPU");
176 FLAG_SET_DEFAULT(UseMPMUL, false);
177 }
178
179 assert(BlockZeroingLowLimit > 0, "invalid value");
180
181 if (has_blk_zeroing() && cache_line_size > 0) {
182 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
183 FLAG_SET_DEFAULT(UseBlockZeroing, true);
184 }
185 } else if (UseBlockZeroing) {
186 warning("BIS zeroing instructions are not available on this CPU");
187 FLAG_SET_DEFAULT(UseBlockZeroing, false);
188 }
189
190 assert(BlockCopyLowLimit > 0, "invalid value");
191
192 if (has_blk_zeroing() && cache_line_size > 0) {
193 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
194 FLAG_SET_DEFAULT(UseBlockCopy, true);
195 }
196 } else if (UseBlockCopy) {
197 warning("BIS instructions are not available or expensive on this CPU");
198 FLAG_SET_DEFAULT(UseBlockCopy, false);
199 }
200
201 #ifdef COMPILER2
202 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
203 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
204 }
205
206 // Currently not supported anywhere.
207 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
208
209 MaxVectorSize = 8;
210
211 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
212 #endif
213
214 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
215 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
216
217 char buf[512];
218 jio_snprintf(buf, sizeof(buf),
219 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
220 "%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s"
221 "%s%s%s%s%s%s%s",
222 (has_v9() ? "v9" : ""),
223 (has_popc() ? ", popc" : ""),
224 (has_vis1() ? ", vis1" : ""),
225 (has_vis2() ? ", vis2" : ""),
226 (has_blk_init() ? ", blk_init" : ""),
227 (has_fmaf() ? ", fmaf" : ""),
228 (has_hpc() ? ", hpc" : ""),
229 (has_ima() ? ", ima" : ""),
230 (has_aes() ? ", aes" : ""),
231 (has_des() ? ", des" : ""),
232 (has_kasumi() ? ", kas" : ""),
233 (has_camellia() ? ", cam" : ""),
234 (has_md5() ? ", md5" : ""),
235 (has_sha1() ? ", sha1" : ""),
236 (has_sha256() ? ", sha256" : ""),
237 (has_sha512() ? ", sha512" : ""),
238 (has_mpmul() ? ", mpmul" : ""),
239 (has_mont() ? ", mont" : ""),
240 (has_pause() ? ", pause" : ""),
241 (has_cbcond() ? ", cbcond" : ""),
242 (has_crc32c() ? ", crc32c" : ""),
243
244 (has_athena_plus() ? ", athena_plus" : ""),
245 (has_vis3b() ? ", vis3b" : ""),
246 (has_adi() ? ", adi" : ""),
247 (has_sparc5() ? ", sparc5" : ""),
248 (has_mwait() ? ", mwait" : ""),
249 (has_xmpmul() ? ", xmpmul" : ""),
250 (has_xmont() ? ", xmont" : ""),
251 (has_pause_nsec() ? ", pause_nsec" : ""),
252 (has_vamask() ? ", vamask" : ""),
253
254 (has_sparc6() ? ", sparc6" : ""),
255 (has_dictunp() ? ", dictunp" : ""),
256 (has_fpcmpshl() ? ", fpcmpshl" : ""),
257 (has_rle() ? ", rle" : ""),
258 (has_sha3() ? ", sha3" : ""),
259 (has_athena_plus2()? ", athena_plus2" : ""),
260 (has_vis3c() ? ", vis3c" : ""),
261 (has_sparc5b() ? ", sparc5b" : ""),
262 (has_mme() ? ", mme" : ""),
263
264 (has_fast_idiv() ? ", *idiv" : ""),
265 (has_fast_rdpc() ? ", *rdpc" : ""),
266 (has_fast_bis() ? ", *bis" : ""),
267 (has_fast_ld() ? ", *ld" : ""),
268 (has_fast_cmove() ? ", *cmove" : ""),
269 (has_fast_ind_br() ? ", *ind_br" : ""),
270 (has_blk_zeroing() ? ", *blk_zeroing" : ""));
271
272 assert(strlen(buf) >= 2, "must be");
273
274 _features_string = os::strdup(buf);
275
276 log_info(os, cpu)("SPARC features detected: %s", _features_string);
277
278 // UseVIS is set to the smallest of what hardware supports and what the command
279 // line requires, i.e. you cannot set UseVIS to 3 on older UltraSparc which do
280 // not support it.
281
282 if (UseVIS > 3) UseVIS = 3;
283 if (UseVIS < 0) UseVIS = 0;
284 if (!has_vis3()) // Drop to 2 if no VIS3 support
285 UseVIS = MIN2((intx)2, UseVIS);
286 if (!has_vis2()) // Drop to 1 if no VIS2 support
287 UseVIS = MIN2((intx)1, UseVIS);
288 if (!has_vis1()) // Drop to 0 if no VIS1 support
289 UseVIS = 0;
290
291 if (has_aes()) {
292 if (FLAG_IS_DEFAULT(UseAES)) {
293 FLAG_SET_DEFAULT(UseAES, true);
294 }
295 if (!UseAES) {
296 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
297 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
298 }
299 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
300 } else {
301 // The AES intrinsic stubs require AES instruction support (of course)
302 // but also require VIS3 mode or higher for instructions it use.
303 if (UseVIS > 2) {
304 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
305 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
306 }
307 } else {
308 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
309 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
310 }
311 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
312 }
313 }
314 } else if (UseAES || UseAESIntrinsics) {
315 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
316 warning("AES instructions are not available on this CPU");
317 FLAG_SET_DEFAULT(UseAES, false);
318 }
319 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
320 warning("AES intrinsics are not available on this CPU");
321 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
322 }
323 }
324
325 if (UseAESCTRIntrinsics) {
326 warning("AES/CTR intrinsics are not available on this CPU");
327 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
328 }
329
330 // GHASH/GCM intrinsics
331 if (has_vis3() && (UseVIS > 2)) {
332 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
333 UseGHASHIntrinsics = true;
334 }
335 } else if (UseGHASHIntrinsics) {
336 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
337 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
338 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
339 }
340
341 if (has_fmaf()) {
342 if (FLAG_IS_DEFAULT(UseFMA)) {
343 UseFMA = true;
344 }
345 } else if (UseFMA) {
346 warning("FMA instructions are not available on this CPU");
347 FLAG_SET_DEFAULT(UseFMA, false);
348 }
349
350 // SHA1, SHA256, and SHA512 instructions were added to SPARC at different times
351 if (has_sha1() || has_sha256() || has_sha512()) {
352 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
353 if (FLAG_IS_DEFAULT(UseSHA)) {
354 FLAG_SET_DEFAULT(UseSHA, true);
355 }
356 } else {
357 if (UseSHA) {
358 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
359 FLAG_SET_DEFAULT(UseSHA, false);
360 }
361 }
362 } else if (UseSHA) {
363 warning("SHA instructions are not available on this CPU");
364 FLAG_SET_DEFAULT(UseSHA, false);
365 }
366
367 if (UseSHA && has_sha1()) {
368 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
369 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
370 }
371 } else if (UseSHA1Intrinsics) {
372 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
373 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
374 }
375
376 if (UseSHA && has_sha256()) {
377 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
378 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
379 }
380 } else if (UseSHA256Intrinsics) {
381 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
382 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
383 }
384
385 if (UseSHA && has_sha512()) {
386 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
387 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
388 }
389 } else if (UseSHA512Intrinsics) {
390 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
391 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
392 }
393
394 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
395 FLAG_SET_DEFAULT(UseSHA, false);
396 }
397
398 if (has_crc32c()) {
399 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
400 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
401 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
402 }
403 } else {
404 if (UseCRC32CIntrinsics) {
405 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
406 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
407 }
408 }
409 } else if (UseCRC32CIntrinsics) {
410 warning("CRC32C instruction is not available on this CPU");
411 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
412 }
413
414 if (UseVIS > 2) {
415 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
416 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
417 }
418 } else if (UseAdler32Intrinsics) {
419 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
420 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
421 }
422
423 if (UseVIS > 2) {
424 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
425 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
426 }
427 } else if (UseCRC32Intrinsics) {
428 warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled");
429 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
430 }
431
432 if (UseVIS > 2) {
433 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
434 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, true);
435 }
436 } else if (UseMultiplyToLenIntrinsic) {
437 warning("SPARC multiplyToLen intrinsics require VIS3 instructions support. Intrinsics will be disabled");
438 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
439 }
440
441 if (UseVectorizedMismatchIntrinsic) {
442 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
443 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
444 }
445
446 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
447 (cache_line_size > ContendedPaddingWidth))
448 ContendedPaddingWidth = cache_line_size;
449
450 // This machine does not allow unaligned memory accesses
451 if (UseUnalignedAccesses) {
452 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
453 warning("Unaligned memory access is not available on this CPU");
454 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
455 }
456
457 if (log_is_enabled(Info, os, cpu)) {
458 ResourceMark rm;
459 LogStream ls(Log(os, cpu)::info());
460 outputStream* log = &ls;
461 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
462 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
463 log->print("Allocation");
464 if (AllocatePrefetchStyle <= 0) {
465 log->print(": no prefetching");
466 } else {
467 log->print(" prefetching: ");
468 if (AllocatePrefetchInstr == 0) {
469 log->print("PREFETCH");
470 } else if (AllocatePrefetchInstr == 1) {
471 log->print("BIS");
472 }
473 if (AllocatePrefetchLines > 1) {
474 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
475 } else {
476 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
477 }
478 }
479 if (PrefetchCopyIntervalInBytes > 0) {
480 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
481 }
482 if (PrefetchScanIntervalInBytes > 0) {
483 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
484 }
485 if (PrefetchFieldsAhead > 0) {
486 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
487 }
488 if (ContendedPaddingWidth > 0) {
489 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
490 }
491 }
492 }
493
494 void VM_Version::print_features() {
495 tty->print("ISA features [0x%0" PRIx64 "]:", _features);
496 if (_features_string != NULL) {
497 tty->print(" %s", _features_string);
498 }
499 tty->cr();
500 }
501
502 void VM_Version::determine_features() {
503 platform_features(); // platform_features() is os_arch specific.
504
505 assert(has_v9(), "must be");
506
507 if (UseNiagaraInstrs) { // Limit code generation to Niagara.
508 _features &= niagara1_msk;
509 }
510 }
511
512 static uint64_t saved_features = 0;
513
514 void VM_Version::allow_all() {
515 saved_features = _features;
516 _features = full_feature_msk;
517 }
518
519 void VM_Version::revert() {
520 _features = saved_features;
521 }
522
523 /* Determine a suitable number of threads on this particular machine.
524 *
525 * FIXME: Simply checking the processor family is insufficient.
526 */
527 unsigned int VM_Version::calc_parallel_worker_threads() {
528 const int num = 5;
529 const int den = is_post_niagara() ? 16 : 8;
530 const int threshold = 8;
531
532 return nof_parallel_worker_threads(num, den, threshold);
533 }