1 /*
2 * Copyright (c) 2005, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_CFGPrinter.hpp"
27 #include "c1/c1_CodeStubs.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_FrameMap.hpp"
30 #include "c1/c1_IR.hpp"
31 #include "c1/c1_LIRGenerator.hpp"
32 #include "c1/c1_LinearScan.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "code/vmreg.inline.hpp"
35 #include "runtime/timerTrace.hpp"
36 #include "utilities/bitMap.inline.hpp"
37
38 #ifndef PRODUCT
39
40 static LinearScanStatistic _stat_before_alloc;
41 static LinearScanStatistic _stat_after_asign;
42 static LinearScanStatistic _stat_final;
43
44 static LinearScanTimers _total_timer;
45
46 // helper macro for short definition of timer
47 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
48
49 // helper macro for short definition of trace-output inside code
50 #define TRACE_LINEAR_SCAN(level, code) \
51 if (TraceLinearScanLevel >= level) { \
52 code; \
53 }
54
55 #else
56
57 #define TIME_LINEAR_SCAN(timer_name)
58 #define TRACE_LINEAR_SCAN(level, code)
59
60 #endif
61
62 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
63 #ifdef _LP64
64 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2, 1, 2, 1, -1};
65 #else
66 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
67 #endif
68
69
70 // Implementation of LinearScan
71
72 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
73 : _compilation(ir->compilation())
74 , _ir(ir)
75 , _gen(gen)
76 , _frame_map(frame_map)
77 , _num_virtual_regs(gen->max_virtual_register_number())
78 , _has_fpu_registers(false)
79 , _num_calls(-1)
80 , _max_spills(0)
81 , _unused_spill_slot(-1)
82 , _intervals(0) // initialized later with correct length
83 , _new_intervals_from_allocation(new IntervalList())
84 , _sorted_intervals(NULL)
85 , _needs_full_resort(false)
86 , _lir_ops(0) // initialized later with correct length
87 , _block_of_op(0) // initialized later with correct length
88 , _has_info(0)
89 , _has_call(0)
90 , _scope_value_cache(0) // initialized later with correct length
91 , _interval_in_loop(0) // initialized later with correct length
92 , _cached_blocks(*ir->linear_scan_order())
93 #ifdef X86
94 , _fpu_stack_allocator(NULL)
95 #endif
96 {
97 assert(this->ir() != NULL, "check if valid");
98 assert(this->compilation() != NULL, "check if valid");
99 assert(this->gen() != NULL, "check if valid");
100 assert(this->frame_map() != NULL, "check if valid");
101 }
102
103
104 // ********** functions for converting LIR-Operands to register numbers
105 //
106 // Emulate a flat register file comprising physical integer registers,
107 // physical floating-point registers and virtual registers, in that order.
108 // Virtual registers already have appropriate numbers, since V0 is
109 // the number of physical registers.
110 // Returns -1 for hi word if opr is a single word operand.
111 //
112 // Note: the inverse operation (calculating an operand for register numbers)
113 // is done in calc_operand_for_interval()
114
115 int LinearScan::reg_num(LIR_Opr opr) {
116 assert(opr->is_register(), "should not call this otherwise");
117
118 if (opr->is_virtual_register()) {
119 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
120 return opr->vreg_number();
121 } else if (opr->is_single_cpu()) {
122 return opr->cpu_regnr();
123 } else if (opr->is_double_cpu()) {
124 return opr->cpu_regnrLo();
125 #ifdef X86
126 } else if (opr->is_single_xmm()) {
127 return opr->fpu_regnr() + pd_first_xmm_reg;
128 } else if (opr->is_double_xmm()) {
129 return opr->fpu_regnrLo() + pd_first_xmm_reg;
130 #endif
131 } else if (opr->is_single_fpu()) {
132 return opr->fpu_regnr() + pd_first_fpu_reg;
133 } else if (opr->is_double_fpu()) {
134 return opr->fpu_regnrLo() + pd_first_fpu_reg;
135 } else {
136 ShouldNotReachHere();
137 return -1;
138 }
139 }
140
141 int LinearScan::reg_numHi(LIR_Opr opr) {
142 assert(opr->is_register(), "should not call this otherwise");
143
144 if (opr->is_virtual_register()) {
145 return -1;
146 } else if (opr->is_single_cpu()) {
147 return -1;
148 } else if (opr->is_double_cpu()) {
149 return opr->cpu_regnrHi();
150 #ifdef X86
151 } else if (opr->is_single_xmm()) {
152 return -1;
153 } else if (opr->is_double_xmm()) {
154 return -1;
155 #endif
156 } else if (opr->is_single_fpu()) {
157 return -1;
158 } else if (opr->is_double_fpu()) {
159 return opr->fpu_regnrHi() + pd_first_fpu_reg;
160 } else {
161 ShouldNotReachHere();
162 return -1;
163 }
164 }
165
166
167 // ********** functions for classification of intervals
168
169 bool LinearScan::is_precolored_interval(const Interval* i) {
170 return i->reg_num() < LinearScan::nof_regs;
171 }
172
173 bool LinearScan::is_virtual_interval(const Interval* i) {
174 return i->reg_num() >= LIR_OprDesc::vreg_base;
175 }
176
177 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
178 return i->reg_num() < LinearScan::nof_cpu_regs;
179 }
180
181 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
182 #if defined(__SOFTFP__) || defined(E500V2)
183 return i->reg_num() >= LIR_OprDesc::vreg_base;
184 #else
185 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
186 #endif // __SOFTFP__ or E500V2
187 }
188
189 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
190 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
191 }
192
193 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
194 #if defined(__SOFTFP__) || defined(E500V2)
195 return false;
196 #else
197 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
198 #endif // __SOFTFP__ or E500V2
199 }
200
201 bool LinearScan::is_in_fpu_register(const Interval* i) {
202 // fixed intervals not needed for FPU stack allocation
203 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
204 }
205
206 bool LinearScan::is_oop_interval(const Interval* i) {
207 // fixed intervals never contain oops
208 return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
209 }
210
211
212 // ********** General helper functions
213
214 // compute next unused stack index that can be used for spilling
215 int LinearScan::allocate_spill_slot(bool double_word) {
216 int spill_slot;
217 if (double_word) {
218 if ((_max_spills & 1) == 1) {
219 // alignment of double-word values
220 // the hole because of the alignment is filled with the next single-word value
221 assert(_unused_spill_slot == -1, "wasting a spill slot");
222 _unused_spill_slot = _max_spills;
223 _max_spills++;
224 }
225 spill_slot = _max_spills;
226 _max_spills += 2;
227
228 } else if (_unused_spill_slot != -1) {
229 // re-use hole that was the result of a previous double-word alignment
230 spill_slot = _unused_spill_slot;
231 _unused_spill_slot = -1;
232
233 } else {
234 spill_slot = _max_spills;
235 _max_spills++;
236 }
237
238 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
239
240 // the class OopMapValue uses only 11 bits for storing the name of the
241 // oop location. So a stack slot bigger than 2^11 leads to an overflow
242 // that is not reported in product builds. Prevent this by checking the
243 // spill slot here (altough this value and the later used location name
244 // are slightly different)
245 if (result > 2000) {
246 bailout("too many stack slots used");
247 }
248
249 return result;
250 }
251
252 void LinearScan::assign_spill_slot(Interval* it) {
253 // assign the canonical spill slot of the parent (if a part of the interval
254 // is already spilled) or allocate a new spill slot
255 if (it->canonical_spill_slot() >= 0) {
256 it->assign_reg(it->canonical_spill_slot());
257 } else {
258 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
259 it->set_canonical_spill_slot(spill);
260 it->assign_reg(spill);
261 }
262 }
263
264 void LinearScan::propagate_spill_slots() {
265 if (!frame_map()->finalize_frame(max_spills())) {
266 bailout("frame too large");
267 }
268 }
269
270 // create a new interval with a predefined reg_num
271 // (only used for parent intervals that are created during the building phase)
272 Interval* LinearScan::create_interval(int reg_num) {
273 assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
274
275 Interval* interval = new Interval(reg_num);
276 _intervals.at_put(reg_num, interval);
277
278 // assign register number for precolored intervals
279 if (reg_num < LIR_OprDesc::vreg_base) {
280 interval->assign_reg(reg_num);
281 }
282 return interval;
283 }
284
285 // assign a new reg_num to the interval and append it to the list of intervals
286 // (only used for child intervals that are created during register allocation)
287 void LinearScan::append_interval(Interval* it) {
288 it->set_reg_num(_intervals.length());
289 _intervals.append(it);
290 _new_intervals_from_allocation->append(it);
291 }
292
293 // copy the vreg-flags if an interval is split
294 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
295 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
296 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
297 }
298 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
299 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
300 }
301
302 // Note: do not copy the must_start_in_memory flag because it is not necessary for child
303 // intervals (only the very beginning of the interval must be in memory)
304 }
305
306
307 // ********** spill move optimization
308 // eliminate moves from register to stack if stack slot is known to be correct
309
310 // called during building of intervals
311 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
312 assert(interval->is_split_parent(), "can only be called for split parents");
313
314 switch (interval->spill_state()) {
315 case noDefinitionFound:
316 assert(interval->spill_definition_pos() == -1, "must no be set before");
317 interval->set_spill_definition_pos(def_pos);
318 interval->set_spill_state(oneDefinitionFound);
319 break;
320
321 case oneDefinitionFound:
322 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
323 if (def_pos < interval->spill_definition_pos() - 2) {
324 // second definition found, so no spill optimization possible for this interval
325 interval->set_spill_state(noOptimization);
326 } else {
327 // two consecutive definitions (because of two-operand LIR form)
328 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
329 }
330 break;
331
332 case noOptimization:
333 // nothing to do
334 break;
335
336 default:
337 assert(false, "other states not allowed at this time");
338 }
339 }
340
341 // called during register allocation
342 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
343 switch (interval->spill_state()) {
344 case oneDefinitionFound: {
345 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
346 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
347
348 if (def_loop_depth < spill_loop_depth) {
349 // the loop depth of the spilling position is higher then the loop depth
350 // at the definition of the interval -> move write to memory out of loop
351 // by storing at definitin of the interval
352 interval->set_spill_state(storeAtDefinition);
353 } else {
354 // the interval is currently spilled only once, so for now there is no
355 // reason to store the interval at the definition
356 interval->set_spill_state(oneMoveInserted);
357 }
358 break;
359 }
360
361 case oneMoveInserted: {
362 // the interval is spilled more then once, so it is better to store it to
363 // memory at the definition
364 interval->set_spill_state(storeAtDefinition);
365 break;
366 }
367
368 case storeAtDefinition:
369 case startInMemory:
370 case noOptimization:
371 case noDefinitionFound:
372 // nothing to do
373 break;
374
375 default:
376 assert(false, "other states not allowed at this time");
377 }
378 }
379
380
381 bool LinearScan::must_store_at_definition(const Interval* i) {
382 return i->is_split_parent() && i->spill_state() == storeAtDefinition;
383 }
384
385 // called once before asignment of register numbers
386 void LinearScan::eliminate_spill_moves() {
387 TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
388 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
389
390 // collect all intervals that must be stored after their definion.
391 // the list is sorted by Interval::spill_definition_pos
392 Interval* interval;
393 Interval* temp_list;
394 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
395
396 #ifdef ASSERT
397 Interval* prev = NULL;
398 Interval* temp = interval;
399 while (temp != Interval::end()) {
400 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
401 if (prev != NULL) {
402 assert(temp->from() >= prev->from(), "intervals not sorted");
403 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
404 }
405
406 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
407 assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
408 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
409
410 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
411
412 temp = temp->next();
413 }
414 #endif
415
416 LIR_InsertionBuffer insertion_buffer;
417 int num_blocks = block_count();
418 for (int i = 0; i < num_blocks; i++) {
419 BlockBegin* block = block_at(i);
420 LIR_OpList* instructions = block->lir()->instructions_list();
421 int num_inst = instructions->length();
422 bool has_new = false;
423
424 // iterate all instructions of the block. skip the first because it is always a label
425 for (int j = 1; j < num_inst; j++) {
426 LIR_Op* op = instructions->at(j);
427 int op_id = op->id();
428
429 if (op_id == -1) {
430 // remove move from register to stack if the stack slot is guaranteed to be correct.
431 // only moves that have been inserted by LinearScan can be removed.
432 assert(op->code() == lir_move, "only moves can have a op_id of -1");
433 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
434 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
435
436 LIR_Op1* op1 = (LIR_Op1*)op;
437 Interval* interval = interval_at(op1->result_opr()->vreg_number());
438
439 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
440 // move target is a stack slot that is always correct, so eliminate instruction
441 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
442 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
443 }
444
445 } else {
446 // insert move from register to stack just after the beginning of the interval
447 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
448 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
449
450 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
451 if (!has_new) {
452 // prepare insertion buffer (appended when all instructions of the block are processed)
453 insertion_buffer.init(block->lir());
454 has_new = true;
455 }
456
457 LIR_Opr from_opr = operand_for_interval(interval);
458 LIR_Opr to_opr = canonical_spill_opr(interval);
459 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
460 assert(to_opr->is_stack(), "to operand must be a stack slot");
461
462 insertion_buffer.move(j, from_opr, to_opr);
463 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
464
465 interval = interval->next();
466 }
467 }
468 } // end of instruction iteration
469
470 if (has_new) {
471 block->lir()->append(&insertion_buffer);
472 }
473 } // end of block iteration
474
475 assert(interval == Interval::end(), "missed an interval");
476 }
477
478
479 // ********** Phase 1: number all instructions in all blocks
480 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
481
482 void LinearScan::number_instructions() {
483 {
484 // dummy-timer to measure the cost of the timer itself
485 // (this time is then subtracted from all other timers to get the real value)
486 TIME_LINEAR_SCAN(timer_do_nothing);
487 }
488 TIME_LINEAR_SCAN(timer_number_instructions);
489
490 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
491 int num_blocks = block_count();
492 int num_instructions = 0;
493 int i;
494 for (i = 0; i < num_blocks; i++) {
495 num_instructions += block_at(i)->lir()->instructions_list()->length();
496 }
497
498 // initialize with correct length
499 _lir_ops = LIR_OpArray(num_instructions, num_instructions, NULL);
500 _block_of_op = BlockBeginArray(num_instructions, num_instructions, NULL);
501
502 int op_id = 0;
503 int idx = 0;
504
505 for (i = 0; i < num_blocks; i++) {
506 BlockBegin* block = block_at(i);
507 block->set_first_lir_instruction_id(op_id);
508 LIR_OpList* instructions = block->lir()->instructions_list();
509
510 int num_inst = instructions->length();
511 for (int j = 0; j < num_inst; j++) {
512 LIR_Op* op = instructions->at(j);
513 op->set_id(op_id);
514
515 _lir_ops.at_put(idx, op);
516 _block_of_op.at_put(idx, block);
517 assert(lir_op_with_id(op_id) == op, "must match");
518
519 idx++;
520 op_id += 2; // numbering of lir_ops by two
521 }
522 block->set_last_lir_instruction_id(op_id - 2);
523 }
524 assert(idx == num_instructions, "must match");
525 assert(idx * 2 == op_id, "must match");
526
527 _has_call.initialize(num_instructions);
528 _has_info.initialize(num_instructions);
529 }
530
531
532 // ********** Phase 2: compute local live sets separately for each block
533 // (sets live_gen and live_kill for each block)
534
535 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
536 LIR_Opr opr = value->operand();
537 Constant* con = value->as_Constant();
538
539 // check some asumptions about debug information
540 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
541 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
542 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
543
544 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
545 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
546 int reg = opr->vreg_number();
547 if (!live_kill.at(reg)) {
548 live_gen.set_bit(reg);
549 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
550 }
551 }
552 }
553
554
555 void LinearScan::compute_local_live_sets() {
556 TIME_LINEAR_SCAN(timer_compute_local_live_sets);
557
558 int num_blocks = block_count();
559 int live_size = live_set_size();
560 bool local_has_fpu_registers = false;
561 int local_num_calls = 0;
562 LIR_OpVisitState visitor;
563
564 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
565
566 // iterate all blocks
567 for (int i = 0; i < num_blocks; i++) {
568 BlockBegin* block = block_at(i);
569
570 ResourceBitMap live_gen(live_size);
571 ResourceBitMap live_kill(live_size);
572
573 if (block->is_set(BlockBegin::exception_entry_flag)) {
574 // Phi functions at the begin of an exception handler are
575 // implicitly defined (= killed) at the beginning of the block.
576 for_each_phi_fun(block, phi,
577 live_kill.set_bit(phi->operand()->vreg_number())
578 );
579 }
580
581 LIR_OpList* instructions = block->lir()->instructions_list();
582 int num_inst = instructions->length();
583
584 // iterate all instructions of the block. skip the first because it is always a label
585 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
586 for (int j = 1; j < num_inst; j++) {
587 LIR_Op* op = instructions->at(j);
588
589 // visit operation to collect all operands
590 visitor.visit(op);
591
592 if (visitor.has_call()) {
593 _has_call.set_bit(op->id() >> 1);
594 local_num_calls++;
595 }
596 if (visitor.info_count() > 0) {
597 _has_info.set_bit(op->id() >> 1);
598 }
599
600 // iterate input operands of instruction
601 int k, n, reg;
602 n = visitor.opr_count(LIR_OpVisitState::inputMode);
603 for (k = 0; k < n; k++) {
604 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
605 assert(opr->is_register(), "visitor should only return register operands");
606
607 if (opr->is_virtual_register()) {
608 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
609 reg = opr->vreg_number();
610 if (!live_kill.at(reg)) {
611 live_gen.set_bit(reg);
612 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id()));
613 }
614 if (block->loop_index() >= 0) {
615 local_interval_in_loop.set_bit(reg, block->loop_index());
616 }
617 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
618 }
619
620 #ifdef ASSERT
621 // fixed intervals are never live at block boundaries, so
622 // they need not be processed in live sets.
623 // this is checked by these assertions to be sure about it.
624 // the entry block may have incoming values in registers, which is ok.
625 if (!opr->is_virtual_register() && block != ir()->start()) {
626 reg = reg_num(opr);
627 if (is_processed_reg_num(reg)) {
628 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
629 }
630 reg = reg_numHi(opr);
631 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
632 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
633 }
634 }
635 #endif
636 }
637
638 // Add uses of live locals from interpreter's point of view for proper debug information generation
639 n = visitor.info_count();
640 for (k = 0; k < n; k++) {
641 CodeEmitInfo* info = visitor.info_at(k);
642 ValueStack* stack = info->stack();
643 for_each_state_value(stack, value,
644 set_live_gen_kill(value, op, live_gen, live_kill)
645 );
646 }
647
648 // iterate temp operands of instruction
649 n = visitor.opr_count(LIR_OpVisitState::tempMode);
650 for (k = 0; k < n; k++) {
651 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
652 assert(opr->is_register(), "visitor should only return register operands");
653
654 if (opr->is_virtual_register()) {
655 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
656 reg = opr->vreg_number();
657 live_kill.set_bit(reg);
658 if (block->loop_index() >= 0) {
659 local_interval_in_loop.set_bit(reg, block->loop_index());
660 }
661 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
662 }
663
664 #ifdef ASSERT
665 // fixed intervals are never live at block boundaries, so
666 // they need not be processed in live sets
667 // process them only in debug mode so that this can be checked
668 if (!opr->is_virtual_register()) {
669 reg = reg_num(opr);
670 if (is_processed_reg_num(reg)) {
671 live_kill.set_bit(reg_num(opr));
672 }
673 reg = reg_numHi(opr);
674 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
675 live_kill.set_bit(reg);
676 }
677 }
678 #endif
679 }
680
681 // iterate output operands of instruction
682 n = visitor.opr_count(LIR_OpVisitState::outputMode);
683 for (k = 0; k < n; k++) {
684 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
685 assert(opr->is_register(), "visitor should only return register operands");
686
687 if (opr->is_virtual_register()) {
688 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
689 reg = opr->vreg_number();
690 live_kill.set_bit(reg);
691 if (block->loop_index() >= 0) {
692 local_interval_in_loop.set_bit(reg, block->loop_index());
693 }
694 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
695 }
696
697 #ifdef ASSERT
698 // fixed intervals are never live at block boundaries, so
699 // they need not be processed in live sets
700 // process them only in debug mode so that this can be checked
701 if (!opr->is_virtual_register()) {
702 reg = reg_num(opr);
703 if (is_processed_reg_num(reg)) {
704 live_kill.set_bit(reg_num(opr));
705 }
706 reg = reg_numHi(opr);
707 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
708 live_kill.set_bit(reg);
709 }
710 }
711 #endif
712 }
713 } // end of instruction iteration
714
715 block->set_live_gen (live_gen);
716 block->set_live_kill(live_kill);
717 block->set_live_in (ResourceBitMap(live_size));
718 block->set_live_out (ResourceBitMap(live_size));
719
720 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen()));
721 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
722 } // end of block iteration
723
724 // propagate local calculated information into LinearScan object
725 _has_fpu_registers = local_has_fpu_registers;
726 compilation()->set_has_fpu_code(local_has_fpu_registers);
727
728 _num_calls = local_num_calls;
729 _interval_in_loop = local_interval_in_loop;
730 }
731
732
733 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
734 // (sets live_in and live_out for each block)
735
736 void LinearScan::compute_global_live_sets() {
737 TIME_LINEAR_SCAN(timer_compute_global_live_sets);
738
739 int num_blocks = block_count();
740 bool change_occurred;
741 bool change_occurred_in_block;
742 int iteration_count = 0;
743 ResourceBitMap live_out(live_set_size()); // scratch set for calculations
744
745 // Perform a backward dataflow analysis to compute live_out and live_in for each block.
746 // The loop is executed until a fixpoint is reached (no changes in an iteration)
747 // Exception handlers must be processed because not all live values are
748 // present in the state array, e.g. because of global value numbering
749 do {
750 change_occurred = false;
751
752 // iterate all blocks in reverse order
753 for (int i = num_blocks - 1; i >= 0; i--) {
754 BlockBegin* block = block_at(i);
755
756 change_occurred_in_block = false;
757
758 // live_out(block) is the union of live_in(sux), for successors sux of block
759 int n = block->number_of_sux();
760 int e = block->number_of_exception_handlers();
761 if (n + e > 0) {
762 // block has successors
763 if (n > 0) {
764 live_out.set_from(block->sux_at(0)->live_in());
765 for (int j = 1; j < n; j++) {
766 live_out.set_union(block->sux_at(j)->live_in());
767 }
768 } else {
769 live_out.clear();
770 }
771 for (int j = 0; j < e; j++) {
772 live_out.set_union(block->exception_handler_at(j)->live_in());
773 }
774
775 if (!block->live_out().is_same(live_out)) {
776 // A change occurred. Swap the old and new live out sets to avoid copying.
777 ResourceBitMap temp = block->live_out();
778 block->set_live_out(live_out);
779 live_out = temp;
780
781 change_occurred = true;
782 change_occurred_in_block = true;
783 }
784 }
785
786 if (iteration_count == 0 || change_occurred_in_block) {
787 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
788 // note: live_in has to be computed only in first iteration or if live_out has changed!
789 ResourceBitMap live_in = block->live_in();
790 live_in.set_from(block->live_out());
791 live_in.set_difference(block->live_kill());
792 live_in.set_union(block->live_gen());
793 }
794
795 #ifndef PRODUCT
796 if (TraceLinearScanLevel >= 4) {
797 char c = ' ';
798 if (iteration_count == 0 || change_occurred_in_block) {
799 c = '*';
800 }
801 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
802 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
803 }
804 #endif
805 }
806 iteration_count++;
807
808 if (change_occurred && iteration_count > 50) {
809 BAILOUT("too many iterations in compute_global_live_sets");
810 }
811 } while (change_occurred);
812
813
814 #ifdef ASSERT
815 // check that fixed intervals are not live at block boundaries
816 // (live set must be empty at fixed intervals)
817 for (int i = 0; i < num_blocks; i++) {
818 BlockBegin* block = block_at(i);
819 for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
820 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty");
821 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
822 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
823 }
824 }
825 #endif
826
827 // check that the live_in set of the first block is empty
828 ResourceBitMap live_in_args(ir()->start()->live_in().size());
829 if (!ir()->start()->live_in().is_same(live_in_args)) {
830 #ifdef ASSERT
831 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
832 tty->print_cr("affected registers:");
833 print_bitmap(ir()->start()->live_in());
834
835 // print some additional information to simplify debugging
836 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
837 if (ir()->start()->live_in().at(i)) {
838 Instruction* instr = gen()->instruction_for_vreg(i);
839 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
840
841 for (int j = 0; j < num_blocks; j++) {
842 BlockBegin* block = block_at(j);
843 if (block->live_gen().at(i)) {
844 tty->print_cr(" used in block B%d", block->block_id());
845 }
846 if (block->live_kill().at(i)) {
847 tty->print_cr(" defined in block B%d", block->block_id());
848 }
849 }
850 }
851 }
852
853 #endif
854 // when this fails, virtual registers are used before they are defined.
855 assert(false, "live_in set of first block must be empty");
856 // bailout of if this occurs in product mode.
857 bailout("live_in set of first block not empty");
858 }
859 }
860
861
862 // ********** Phase 4: build intervals
863 // (fills the list _intervals)
864
865 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
866 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
867 LIR_Opr opr = value->operand();
868 Constant* con = value->as_Constant();
869
870 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
871 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
872 add_use(opr, from, to, use_kind);
873 }
874 }
875
876
877 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
878 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
879 assert(opr->is_register(), "should not be called otherwise");
880
881 if (opr->is_virtual_register()) {
882 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
883 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
884
885 } else {
886 int reg = reg_num(opr);
887 if (is_processed_reg_num(reg)) {
888 add_def(reg, def_pos, use_kind, opr->type_register());
889 }
890 reg = reg_numHi(opr);
891 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
892 add_def(reg, def_pos, use_kind, opr->type_register());
893 }
894 }
895 }
896
897 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
898 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
899 assert(opr->is_register(), "should not be called otherwise");
900
901 if (opr->is_virtual_register()) {
902 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
903 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
904
905 } else {
906 int reg = reg_num(opr);
907 if (is_processed_reg_num(reg)) {
908 add_use(reg, from, to, use_kind, opr->type_register());
909 }
910 reg = reg_numHi(opr);
911 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
912 add_use(reg, from, to, use_kind, opr->type_register());
913 }
914 }
915 }
916
917 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
918 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
919 assert(opr->is_register(), "should not be called otherwise");
920
921 if (opr->is_virtual_register()) {
922 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
923 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
924
925 } else {
926 int reg = reg_num(opr);
927 if (is_processed_reg_num(reg)) {
928 add_temp(reg, temp_pos, use_kind, opr->type_register());
929 }
930 reg = reg_numHi(opr);
931 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
932 add_temp(reg, temp_pos, use_kind, opr->type_register());
933 }
934 }
935 }
936
937
938 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
939 Interval* interval = interval_at(reg_num);
940 if (interval != NULL) {
941 assert(interval->reg_num() == reg_num, "wrong interval");
942
943 if (type != T_ILLEGAL) {
944 interval->set_type(type);
945 }
946
947 Range* r = interval->first();
948 if (r->from() <= def_pos) {
949 // Update the starting point (when a range is first created for a use, its
950 // start is the beginning of the current block until a def is encountered.)
951 r->set_from(def_pos);
952 interval->add_use_pos(def_pos, use_kind);
953
954 } else {
955 // Dead value - make vacuous interval
956 // also add use_kind for dead intervals
957 interval->add_range(def_pos, def_pos + 1);
958 interval->add_use_pos(def_pos, use_kind);
959 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
960 }
961
962 } else {
963 // Dead value - make vacuous interval
964 // also add use_kind for dead intervals
965 interval = create_interval(reg_num);
966 if (type != T_ILLEGAL) {
967 interval->set_type(type);
968 }
969
970 interval->add_range(def_pos, def_pos + 1);
971 interval->add_use_pos(def_pos, use_kind);
972 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
973 }
974
975 change_spill_definition_pos(interval, def_pos);
976 if (use_kind == noUse && interval->spill_state() <= startInMemory) {
977 // detection of method-parameters and roundfp-results
978 // TODO: move this directly to position where use-kind is computed
979 interval->set_spill_state(startInMemory);
980 }
981 }
982
983 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
984 Interval* interval = interval_at(reg_num);
985 if (interval == NULL) {
986 interval = create_interval(reg_num);
987 }
988 assert(interval->reg_num() == reg_num, "wrong interval");
989
990 if (type != T_ILLEGAL) {
991 interval->set_type(type);
992 }
993
994 interval->add_range(from, to);
995 interval->add_use_pos(to, use_kind);
996 }
997
998 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
999 Interval* interval = interval_at(reg_num);
1000 if (interval == NULL) {
1001 interval = create_interval(reg_num);
1002 }
1003 assert(interval->reg_num() == reg_num, "wrong interval");
1004
1005 if (type != T_ILLEGAL) {
1006 interval->set_type(type);
1007 }
1008
1009 interval->add_range(temp_pos, temp_pos + 1);
1010 interval->add_use_pos(temp_pos, use_kind);
1011 }
1012
1013
1014 // the results of this functions are used for optimizing spilling and reloading
1015 // if the functions return shouldHaveRegister and the interval is spilled,
1016 // it is not reloaded to a register.
1017 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1018 if (op->code() == lir_move) {
1019 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1020 LIR_Op1* move = (LIR_Op1*)op;
1021 LIR_Opr res = move->result_opr();
1022 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1023
1024 if (result_in_memory) {
1025 // Begin of an interval with must_start_in_memory set.
1026 // This interval will always get a stack slot first, so return noUse.
1027 return noUse;
1028
1029 } else if (move->in_opr()->is_stack()) {
1030 // method argument (condition must be equal to handle_method_arguments)
1031 return noUse;
1032
1033 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1034 // Move from register to register
1035 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1036 // special handling of phi-function moves inside osr-entry blocks
1037 // input operand must have a register instead of output operand (leads to better register allocation)
1038 return shouldHaveRegister;
1039 }
1040 }
1041 }
1042
1043 if (opr->is_virtual() &&
1044 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1045 // result is a stack-slot, so prevent immediate reloading
1046 return noUse;
1047 }
1048
1049 // all other operands require a register
1050 return mustHaveRegister;
1051 }
1052
1053 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1054 if (op->code() == lir_move) {
1055 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1056 LIR_Op1* move = (LIR_Op1*)op;
1057 LIR_Opr res = move->result_opr();
1058 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1059
1060 if (result_in_memory) {
1061 // Move to an interval with must_start_in_memory set.
1062 // To avoid moves from stack to stack (not allowed) force the input operand to a register
1063 return mustHaveRegister;
1064
1065 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1066 // Move from register to register
1067 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1068 // special handling of phi-function moves inside osr-entry blocks
1069 // input operand must have a register instead of output operand (leads to better register allocation)
1070 return mustHaveRegister;
1071 }
1072
1073 // The input operand is not forced to a register (moves from stack to register are allowed),
1074 // but it is faster if the input operand is in a register
1075 return shouldHaveRegister;
1076 }
1077 }
1078
1079
1080 #if defined(X86) || defined(S390)
1081 if (op->code() == lir_cmove) {
1082 // conditional moves can handle stack operands
1083 assert(op->result_opr()->is_register(), "result must always be in a register");
1084 return shouldHaveRegister;
1085 }
1086
1087 // optimizations for second input operand of arithmehtic operations on Intel
1088 // this operand is allowed to be on the stack in some cases
1089 BasicType opr_type = opr->type_register();
1090 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1091 #ifdef X86
1092 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) {
1093 #endif
1094 // SSE float instruction (T_DOUBLE only supported with SSE2)
1095 switch (op->code()) {
1096 case lir_cmp:
1097 case lir_add:
1098 case lir_sub:
1099 case lir_mul:
1100 case lir_div:
1101 {
1102 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1103 LIR_Op2* op2 = (LIR_Op2*)op;
1104 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1105 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1106 return shouldHaveRegister;
1107 }
1108 }
1109 default:
1110 break;
1111 }
1112 #ifdef X86
1113 } else {
1114 // FPU stack float instruction
1115 switch (op->code()) {
1116 case lir_add:
1117 case lir_sub:
1118 case lir_mul:
1119 case lir_div:
1120 {
1121 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1122 LIR_Op2* op2 = (LIR_Op2*)op;
1123 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1124 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1125 return shouldHaveRegister;
1126 }
1127 }
1128 default:
1129 break;
1130 }
1131 }
1132 #endif
1133 // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1134 // Since 64bit logical operations do not current support operands on stack, we have to make sure
1135 // T_OBJECT doesn't get spilled along with T_LONG.
1136 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1137 // integer instruction (note: long operands must always be in register)
1138 switch (op->code()) {
1139 case lir_cmp:
1140 case lir_add:
1141 case lir_sub:
1142 case lir_logic_and:
1143 case lir_logic_or:
1144 case lir_logic_xor:
1145 {
1146 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1147 LIR_Op2* op2 = (LIR_Op2*)op;
1148 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1149 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1150 return shouldHaveRegister;
1151 }
1152 }
1153 default:
1154 break;
1155 }
1156 }
1157 #endif // X86 S390
1158
1159 // all other operands require a register
1160 return mustHaveRegister;
1161 }
1162
1163
1164 void LinearScan::handle_method_arguments(LIR_Op* op) {
1165 // special handling for method arguments (moves from stack to virtual register):
1166 // the interval gets no register assigned, but the stack slot.
1167 // it is split before the first use by the register allocator.
1168
1169 if (op->code() == lir_move) {
1170 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1171 LIR_Op1* move = (LIR_Op1*)op;
1172
1173 if (move->in_opr()->is_stack()) {
1174 #ifdef ASSERT
1175 int arg_size = compilation()->method()->arg_size();
1176 LIR_Opr o = move->in_opr();
1177 if (o->is_single_stack()) {
1178 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1179 } else if (o->is_double_stack()) {
1180 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1181 } else {
1182 ShouldNotReachHere();
1183 }
1184
1185 assert(move->id() > 0, "invalid id");
1186 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1187 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1188
1189 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1190 #endif
1191
1192 Interval* interval = interval_at(reg_num(move->result_opr()));
1193
1194 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1195 interval->set_canonical_spill_slot(stack_slot);
1196 interval->assign_reg(stack_slot);
1197 }
1198 }
1199 }
1200
1201 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1202 // special handling for doubleword move from memory to register:
1203 // in this case the registers of the input address and the result
1204 // registers must not overlap -> add a temp range for the input registers
1205 if (op->code() == lir_move) {
1206 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1207 LIR_Op1* move = (LIR_Op1*)op;
1208
1209 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1210 LIR_Address* address = move->in_opr()->as_address_ptr();
1211 if (address != NULL) {
1212 if (address->base()->is_valid()) {
1213 add_temp(address->base(), op->id(), noUse);
1214 }
1215 if (address->index()->is_valid()) {
1216 add_temp(address->index(), op->id(), noUse);
1217 }
1218 }
1219 }
1220 }
1221 }
1222
1223 void LinearScan::add_register_hints(LIR_Op* op) {
1224 switch (op->code()) {
1225 case lir_move: // fall through
1226 case lir_convert: {
1227 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1228 LIR_Op1* move = (LIR_Op1*)op;
1229
1230 LIR_Opr move_from = move->in_opr();
1231 LIR_Opr move_to = move->result_opr();
1232
1233 if (move_to->is_register() && move_from->is_register()) {
1234 Interval* from = interval_at(reg_num(move_from));
1235 Interval* to = interval_at(reg_num(move_to));
1236 if (from != NULL && to != NULL) {
1237 to->set_register_hint(from);
1238 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1239 }
1240 }
1241 break;
1242 }
1243 case lir_cmove: {
1244 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1245 LIR_Op2* cmove = (LIR_Op2*)op;
1246
1247 LIR_Opr move_from = cmove->in_opr1();
1248 LIR_Opr move_to = cmove->result_opr();
1249
1250 if (move_to->is_register() && move_from->is_register()) {
1251 Interval* from = interval_at(reg_num(move_from));
1252 Interval* to = interval_at(reg_num(move_to));
1253 if (from != NULL && to != NULL) {
1254 to->set_register_hint(from);
1255 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1256 }
1257 }
1258 break;
1259 }
1260 default:
1261 break;
1262 }
1263 }
1264
1265
1266 void LinearScan::build_intervals() {
1267 TIME_LINEAR_SCAN(timer_build_intervals);
1268
1269 // initialize interval list with expected number of intervals
1270 // (32 is added to have some space for split children without having to resize the list)
1271 _intervals = IntervalList(num_virtual_regs() + 32);
1272 // initialize all slots that are used by build_intervals
1273 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1274
1275 // create a list with all caller-save registers (cpu, fpu, xmm)
1276 // when an instruction is a call, a temp range is created for all these registers
1277 int num_caller_save_registers = 0;
1278 int caller_save_registers[LinearScan::nof_regs];
1279
1280 int i;
1281 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1282 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1283 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1284 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1285 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1286 }
1287
1288 // temp ranges for fpu registers are only created when the method has
1289 // virtual fpu operands. Otherwise no allocation for fpu registers is
1290 // perfomed and so the temp ranges would be useless
1291 if (has_fpu_registers()) {
1292 #ifdef X86
1293 if (UseSSE < 2) {
1294 #endif
1295 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1296 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1297 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1298 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1299 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1300 }
1301 #ifdef X86
1302 }
1303 if (UseSSE > 0) {
1304 int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
1305 for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1306 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1307 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1308 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1309 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1310 }
1311 }
1312 #endif
1313 }
1314 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1315
1316
1317 LIR_OpVisitState visitor;
1318
1319 // iterate all blocks in reverse order
1320 for (i = block_count() - 1; i >= 0; i--) {
1321 BlockBegin* block = block_at(i);
1322 LIR_OpList* instructions = block->lir()->instructions_list();
1323 int block_from = block->first_lir_instruction_id();
1324 int block_to = block->last_lir_instruction_id();
1325
1326 assert(block_from == instructions->at(0)->id(), "must be");
1327 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be");
1328
1329 // Update intervals for registers live at the end of this block;
1330 ResourceBitMap live = block->live_out();
1331 int size = (int)live.size();
1332 for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1333 assert(live.at(number), "should not stop here otherwise");
1334 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1335 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1336
1337 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1338
1339 // add special use positions for loop-end blocks when the
1340 // interval is used anywhere inside this loop. It's possible
1341 // that the block was part of a non-natural loop, so it might
1342 // have an invalid loop index.
1343 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1344 block->loop_index() != -1 &&
1345 is_interval_in_loop(number, block->loop_index())) {
1346 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1347 }
1348 }
1349
1350 // iterate all instructions of the block in reverse order.
1351 // skip the first instruction because it is always a label
1352 // definitions of intervals are processed before uses
1353 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1354 for (int j = instructions->length() - 1; j >= 1; j--) {
1355 LIR_Op* op = instructions->at(j);
1356 int op_id = op->id();
1357
1358 // visit operation to collect all operands
1359 visitor.visit(op);
1360
1361 // add a temp range for each register if operation destroys caller-save registers
1362 if (visitor.has_call()) {
1363 for (int k = 0; k < num_caller_save_registers; k++) {
1364 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1365 }
1366 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1367 }
1368
1369 // Add any platform dependent temps
1370 pd_add_temps(op);
1371
1372 // visit definitions (output and temp operands)
1373 int k, n;
1374 n = visitor.opr_count(LIR_OpVisitState::outputMode);
1375 for (k = 0; k < n; k++) {
1376 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1377 assert(opr->is_register(), "visitor should only return register operands");
1378 add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1379 }
1380
1381 n = visitor.opr_count(LIR_OpVisitState::tempMode);
1382 for (k = 0; k < n; k++) {
1383 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1384 assert(opr->is_register(), "visitor should only return register operands");
1385 add_temp(opr, op_id, mustHaveRegister);
1386 }
1387
1388 // visit uses (input operands)
1389 n = visitor.opr_count(LIR_OpVisitState::inputMode);
1390 for (k = 0; k < n; k++) {
1391 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1392 assert(opr->is_register(), "visitor should only return register operands");
1393 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1394 }
1395
1396 // Add uses of live locals from interpreter's point of view for proper
1397 // debug information generation
1398 // Treat these operands as temp values (if the life range is extended
1399 // to a call site, the value would be in a register at the call otherwise)
1400 n = visitor.info_count();
1401 for (k = 0; k < n; k++) {
1402 CodeEmitInfo* info = visitor.info_at(k);
1403 ValueStack* stack = info->stack();
1404 for_each_state_value(stack, value,
1405 add_use(value, block_from, op_id + 1, noUse);
1406 );
1407 }
1408
1409 // special steps for some instructions (especially moves)
1410 handle_method_arguments(op);
1411 handle_doubleword_moves(op);
1412 add_register_hints(op);
1413
1414 } // end of instruction iteration
1415 } // end of block iteration
1416
1417
1418 // add the range [0, 1[ to all fixed intervals
1419 // -> the register allocator need not handle unhandled fixed intervals
1420 for (int n = 0; n < LinearScan::nof_regs; n++) {
1421 Interval* interval = interval_at(n);
1422 if (interval != NULL) {
1423 interval->add_range(0, 1);
1424 }
1425 }
1426 }
1427
1428
1429 // ********** Phase 5: actual register allocation
1430
1431 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1432 if (*a != NULL) {
1433 if (*b != NULL) {
1434 return (*a)->from() - (*b)->from();
1435 } else {
1436 return -1;
1437 }
1438 } else {
1439 if (*b != NULL) {
1440 return 1;
1441 } else {
1442 return 0;
1443 }
1444 }
1445 }
1446
1447 #ifndef PRODUCT
1448 int interval_cmp(Interval* const& l, Interval* const& r) {
1449 return l->from() - r->from();
1450 }
1451
1452 bool find_interval(Interval* interval, IntervalArray* intervals) {
1453 bool found;
1454 int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found);
1455
1456 if (!found) {
1457 return false;
1458 }
1459
1460 int from = interval->from();
1461
1462 // The index we've found using binary search is pointing to an interval
1463 // that is defined in the same place as the interval we were looking for.
1464 // So now we have to look around that index and find exact interval.
1465 for (int i = idx; i >= 0; i--) {
1466 if (intervals->at(i) == interval) {
1467 return true;
1468 }
1469 if (intervals->at(i)->from() != from) {
1470 break;
1471 }
1472 }
1473
1474 for (int i = idx + 1; i < intervals->length(); i++) {
1475 if (intervals->at(i) == interval) {
1476 return true;
1477 }
1478 if (intervals->at(i)->from() != from) {
1479 break;
1480 }
1481 }
1482
1483 return false;
1484 }
1485
1486 bool LinearScan::is_sorted(IntervalArray* intervals) {
1487 int from = -1;
1488 int null_count = 0;
1489
1490 for (int i = 0; i < intervals->length(); i++) {
1491 Interval* it = intervals->at(i);
1492 if (it != NULL) {
1493 assert(from <= it->from(), "Intervals are unordered");
1494 from = it->from();
1495 } else {
1496 null_count++;
1497 }
1498 }
1499
1500 assert(null_count == 0, "Sorted intervals should not contain nulls");
1501
1502 null_count = 0;
1503
1504 for (int i = 0; i < interval_count(); i++) {
1505 Interval* interval = interval_at(i);
1506 if (interval != NULL) {
1507 assert(find_interval(interval, intervals), "Lists do not contain same intervals");
1508 } else {
1509 null_count++;
1510 }
1511 }
1512
1513 assert(interval_count() - null_count == intervals->length(),
1514 "Sorted list should contain the same amount of non-NULL intervals as unsorted list");
1515
1516 return true;
1517 }
1518 #endif
1519
1520 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1521 if (*prev != NULL) {
1522 (*prev)->set_next(interval);
1523 } else {
1524 *first = interval;
1525 }
1526 *prev = interval;
1527 }
1528
1529 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1530 assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1531
1532 *list1 = *list2 = Interval::end();
1533
1534 Interval* list1_prev = NULL;
1535 Interval* list2_prev = NULL;
1536 Interval* v;
1537
1538 const int n = _sorted_intervals->length();
1539 for (int i = 0; i < n; i++) {
1540 v = _sorted_intervals->at(i);
1541 if (v == NULL) continue;
1542
1543 if (is_list1(v)) {
1544 add_to_list(list1, &list1_prev, v);
1545 } else if (is_list2 == NULL || is_list2(v)) {
1546 add_to_list(list2, &list2_prev, v);
1547 }
1548 }
1549
1550 if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1551 if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1552
1553 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1554 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1555 }
1556
1557
1558 void LinearScan::sort_intervals_before_allocation() {
1559 TIME_LINEAR_SCAN(timer_sort_intervals_before);
1560
1561 if (_needs_full_resort) {
1562 // There is no known reason why this should occur but just in case...
1563 assert(false, "should never occur");
1564 // Re-sort existing interval list because an Interval::from() has changed
1565 _sorted_intervals->sort(interval_cmp);
1566 _needs_full_resort = false;
1567 }
1568
1569 IntervalList* unsorted_list = &_intervals;
1570 int unsorted_len = unsorted_list->length();
1571 int sorted_len = 0;
1572 int unsorted_idx;
1573 int sorted_idx = 0;
1574 int sorted_from_max = -1;
1575
1576 // calc number of items for sorted list (sorted list must not contain NULL values)
1577 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1578 if (unsorted_list->at(unsorted_idx) != NULL) {
1579 sorted_len++;
1580 }
1581 }
1582 IntervalArray* sorted_list = new IntervalArray(sorted_len, sorted_len, NULL);
1583
1584 // special sorting algorithm: the original interval-list is almost sorted,
1585 // only some intervals are swapped. So this is much faster than a complete QuickSort
1586 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1587 Interval* cur_interval = unsorted_list->at(unsorted_idx);
1588
1589 if (cur_interval != NULL) {
1590 int cur_from = cur_interval->from();
1591
1592 if (sorted_from_max <= cur_from) {
1593 sorted_list->at_put(sorted_idx++, cur_interval);
1594 sorted_from_max = cur_interval->from();
1595 } else {
1596 // the asumption that the intervals are already sorted failed,
1597 // so this interval must be sorted in manually
1598 int j;
1599 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1600 sorted_list->at_put(j + 1, sorted_list->at(j));
1601 }
1602 sorted_list->at_put(j + 1, cur_interval);
1603 sorted_idx++;
1604 }
1605 }
1606 }
1607 _sorted_intervals = sorted_list;
1608 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1609 }
1610
1611 void LinearScan::sort_intervals_after_allocation() {
1612 TIME_LINEAR_SCAN(timer_sort_intervals_after);
1613
1614 if (_needs_full_resort) {
1615 // Re-sort existing interval list because an Interval::from() has changed
1616 _sorted_intervals->sort(interval_cmp);
1617 _needs_full_resort = false;
1618 }
1619
1620 IntervalArray* old_list = _sorted_intervals;
1621 IntervalList* new_list = _new_intervals_from_allocation;
1622 int old_len = old_list->length();
1623 int new_len = new_list->length();
1624
1625 if (new_len == 0) {
1626 // no intervals have been added during allocation, so sorted list is already up to date
1627 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1628 return;
1629 }
1630
1631 // conventional sort-algorithm for new intervals
1632 new_list->sort(interval_cmp);
1633
1634 // merge old and new list (both already sorted) into one combined list
1635 int combined_list_len = old_len + new_len;
1636 IntervalArray* combined_list = new IntervalArray(combined_list_len, combined_list_len, NULL);
1637 int old_idx = 0;
1638 int new_idx = 0;
1639
1640 while (old_idx + new_idx < old_len + new_len) {
1641 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1642 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1643 old_idx++;
1644 } else {
1645 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1646 new_idx++;
1647 }
1648 }
1649
1650 _sorted_intervals = combined_list;
1651 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1652 }
1653
1654
1655 void LinearScan::allocate_registers() {
1656 TIME_LINEAR_SCAN(timer_allocate_registers);
1657
1658 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1659 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1660
1661 // allocate cpu registers
1662 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals,
1663 is_precolored_cpu_interval, is_virtual_cpu_interval);
1664
1665 // allocate fpu registers
1666 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals,
1667 is_precolored_fpu_interval, is_virtual_fpu_interval);
1668
1669 // the fpu interval allocation cannot be moved down below with the fpu section as
1670 // the cpu_lsw.walk() changes interval positions.
1671
1672 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1673 cpu_lsw.walk();
1674 cpu_lsw.finish_allocation();
1675
1676 if (has_fpu_registers()) {
1677 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1678 fpu_lsw.walk();
1679 fpu_lsw.finish_allocation();
1680 }
1681 }
1682
1683
1684 // ********** Phase 6: resolve data flow
1685 // (insert moves at edges between blocks if intervals have been split)
1686
1687 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1688 // instead of returning NULL
1689 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1690 Interval* result = interval->split_child_at_op_id(op_id, mode);
1691 if (result != NULL) {
1692 return result;
1693 }
1694
1695 assert(false, "must find an interval, but do a clean bailout in product mode");
1696 result = new Interval(LIR_OprDesc::vreg_base);
1697 result->assign_reg(0);
1698 result->set_type(T_INT);
1699 BAILOUT_("LinearScan: interval is NULL", result);
1700 }
1701
1702
1703 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1704 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1705 assert(interval_at(reg_num) != NULL, "no interval found");
1706
1707 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1708 }
1709
1710 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1711 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1712 assert(interval_at(reg_num) != NULL, "no interval found");
1713
1714 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1715 }
1716
1717 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1718 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1719 assert(interval_at(reg_num) != NULL, "no interval found");
1720
1721 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1722 }
1723
1724
1725 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1726 DEBUG_ONLY(move_resolver.check_empty());
1727
1728 const int num_regs = num_virtual_regs();
1729 const int size = live_set_size();
1730 const ResourceBitMap live_at_edge = to_block->live_in();
1731
1732 // visit all registers where the live_at_edge bit is set
1733 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1734 assert(r < num_regs, "live information set for not exisiting interval");
1735 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1736
1737 Interval* from_interval = interval_at_block_end(from_block, r);
1738 Interval* to_interval = interval_at_block_begin(to_block, r);
1739
1740 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1741 // need to insert move instruction
1742 move_resolver.add_mapping(from_interval, to_interval);
1743 }
1744 }
1745 }
1746
1747
1748 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1749 if (from_block->number_of_sux() <= 1) {
1750 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1751
1752 LIR_OpList* instructions = from_block->lir()->instructions_list();
1753 LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1754 if (branch != NULL) {
1755 // insert moves before branch
1756 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1757 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1758 } else {
1759 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1760 }
1761
1762 } else {
1763 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1764 #ifdef ASSERT
1765 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1766
1767 // because the number of predecessor edges matches the number of
1768 // successor edges, blocks which are reached by switch statements
1769 // may have be more than one predecessor but it will be guaranteed
1770 // that all predecessors will be the same.
1771 for (int i = 0; i < to_block->number_of_preds(); i++) {
1772 assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1773 }
1774 #endif
1775
1776 move_resolver.set_insert_position(to_block->lir(), 0);
1777 }
1778 }
1779
1780
1781 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1782 void LinearScan::resolve_data_flow() {
1783 TIME_LINEAR_SCAN(timer_resolve_data_flow);
1784
1785 int num_blocks = block_count();
1786 MoveResolver move_resolver(this);
1787 ResourceBitMap block_completed(num_blocks);
1788 ResourceBitMap already_resolved(num_blocks);
1789
1790 int i;
1791 for (i = 0; i < num_blocks; i++) {
1792 BlockBegin* block = block_at(i);
1793
1794 // check if block has only one predecessor and only one successor
1795 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1796 LIR_OpList* instructions = block->lir()->instructions_list();
1797 assert(instructions->at(0)->code() == lir_label, "block must start with label");
1798 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1799 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1800
1801 // check if block is empty (only label and branch)
1802 if (instructions->length() == 2) {
1803 BlockBegin* pred = block->pred_at(0);
1804 BlockBegin* sux = block->sux_at(0);
1805
1806 // prevent optimization of two consecutive blocks
1807 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1808 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1809 block_completed.set_bit(block->linear_scan_number());
1810
1811 // directly resolve between pred and sux (without looking at the empty block between)
1812 resolve_collect_mappings(pred, sux, move_resolver);
1813 if (move_resolver.has_mappings()) {
1814 move_resolver.set_insert_position(block->lir(), 0);
1815 move_resolver.resolve_and_append_moves();
1816 }
1817 }
1818 }
1819 }
1820 }
1821
1822
1823 for (i = 0; i < num_blocks; i++) {
1824 if (!block_completed.at(i)) {
1825 BlockBegin* from_block = block_at(i);
1826 already_resolved.set_from(block_completed);
1827
1828 int num_sux = from_block->number_of_sux();
1829 for (int s = 0; s < num_sux; s++) {
1830 BlockBegin* to_block = from_block->sux_at(s);
1831
1832 // check for duplicate edges between the same blocks (can happen with switch blocks)
1833 if (!already_resolved.at(to_block->linear_scan_number())) {
1834 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1835 already_resolved.set_bit(to_block->linear_scan_number());
1836
1837 // collect all intervals that have been split between from_block and to_block
1838 resolve_collect_mappings(from_block, to_block, move_resolver);
1839 if (move_resolver.has_mappings()) {
1840 resolve_find_insert_pos(from_block, to_block, move_resolver);
1841 move_resolver.resolve_and_append_moves();
1842 }
1843 }
1844 }
1845 }
1846 }
1847 }
1848
1849
1850 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1851 if (interval_at(reg_num) == NULL) {
1852 // if a phi function is never used, no interval is created -> ignore this
1853 return;
1854 }
1855
1856 Interval* interval = interval_at_block_begin(block, reg_num);
1857 int reg = interval->assigned_reg();
1858 int regHi = interval->assigned_regHi();
1859
1860 if ((reg < nof_regs && interval->always_in_memory()) ||
1861 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1862 // the interval is split to get a short range that is located on the stack
1863 // in the following two cases:
1864 // * the interval started in memory (e.g. method parameter), but is currently in a register
1865 // this is an optimization for exception handling that reduces the number of moves that
1866 // are necessary for resolving the states when an exception uses this exception handler
1867 // * the interval would be on the fpu stack at the begin of the exception handler
1868 // this is not allowed because of the complicated fpu stack handling on Intel
1869
1870 // range that will be spilled to memory
1871 int from_op_id = block->first_lir_instruction_id();
1872 int to_op_id = from_op_id + 1; // short live range of length 1
1873 assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1874 "no split allowed between exception entry and first instruction");
1875
1876 if (interval->from() != from_op_id) {
1877 // the part before from_op_id is unchanged
1878 interval = interval->split(from_op_id);
1879 interval->assign_reg(reg, regHi);
1880 append_interval(interval);
1881 } else {
1882 _needs_full_resort = true;
1883 }
1884 assert(interval->from() == from_op_id, "must be true now");
1885
1886 Interval* spilled_part = interval;
1887 if (interval->to() != to_op_id) {
1888 // the part after to_op_id is unchanged
1889 spilled_part = interval->split_from_start(to_op_id);
1890 append_interval(spilled_part);
1891 move_resolver.add_mapping(spilled_part, interval);
1892 }
1893 assign_spill_slot(spilled_part);
1894
1895 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1896 }
1897 }
1898
1899 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1900 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1901 DEBUG_ONLY(move_resolver.check_empty());
1902
1903 // visit all registers where the live_in bit is set
1904 int size = live_set_size();
1905 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1906 resolve_exception_entry(block, r, move_resolver);
1907 }
1908
1909 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1910 for_each_phi_fun(block, phi,
1911 resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver)
1912 );
1913
1914 if (move_resolver.has_mappings()) {
1915 // insert moves after first instruction
1916 move_resolver.set_insert_position(block->lir(), 0);
1917 move_resolver.resolve_and_append_moves();
1918 }
1919 }
1920
1921
1922 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1923 if (interval_at(reg_num) == NULL) {
1924 // if a phi function is never used, no interval is created -> ignore this
1925 return;
1926 }
1927
1928 // the computation of to_interval is equal to resolve_collect_mappings,
1929 // but from_interval is more complicated because of phi functions
1930 BlockBegin* to_block = handler->entry_block();
1931 Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1932
1933 if (phi != NULL) {
1934 // phi function of the exception entry block
1935 // no moves are created for this phi function in the LIR_Generator, so the
1936 // interval at the throwing instruction must be searched using the operands
1937 // of the phi function
1938 Value from_value = phi->operand_at(handler->phi_operand());
1939
1940 // with phi functions it can happen that the same from_value is used in
1941 // multiple mappings, so notify move-resolver that this is allowed
1942 move_resolver.set_multiple_reads_allowed();
1943
1944 Constant* con = from_value->as_Constant();
1945 if (con != NULL && !con->is_pinned()) {
1946 // unpinned constants may have no register, so add mapping from constant to interval
1947 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1948 } else {
1949 // search split child at the throwing op_id
1950 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1951 move_resolver.add_mapping(from_interval, to_interval);
1952 }
1953
1954 } else {
1955 // no phi function, so use reg_num also for from_interval
1956 // search split child at the throwing op_id
1957 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1958 if (from_interval != to_interval) {
1959 // optimization to reduce number of moves: when to_interval is on stack and
1960 // the stack slot is known to be always correct, then no move is necessary
1961 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1962 move_resolver.add_mapping(from_interval, to_interval);
1963 }
1964 }
1965 }
1966 }
1967
1968 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1969 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1970
1971 DEBUG_ONLY(move_resolver.check_empty());
1972 assert(handler->lir_op_id() == -1, "already processed this xhandler");
1973 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1974 assert(handler->entry_code() == NULL, "code already present");
1975
1976 // visit all registers where the live_in bit is set
1977 BlockBegin* block = handler->entry_block();
1978 int size = live_set_size();
1979 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1980 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1981 }
1982
1983 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1984 for_each_phi_fun(block, phi,
1985 resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
1986 );
1987
1988 if (move_resolver.has_mappings()) {
1989 LIR_List* entry_code = new LIR_List(compilation());
1990 move_resolver.set_insert_position(entry_code, 0);
1991 move_resolver.resolve_and_append_moves();
1992
1993 entry_code->jump(handler->entry_block());
1994 handler->set_entry_code(entry_code);
1995 }
1996 }
1997
1998
1999 void LinearScan::resolve_exception_handlers() {
2000 MoveResolver move_resolver(this);
2001 LIR_OpVisitState visitor;
2002 int num_blocks = block_count();
2003
2004 int i;
2005 for (i = 0; i < num_blocks; i++) {
2006 BlockBegin* block = block_at(i);
2007 if (block->is_set(BlockBegin::exception_entry_flag)) {
2008 resolve_exception_entry(block, move_resolver);
2009 }
2010 }
2011
2012 for (i = 0; i < num_blocks; i++) {
2013 BlockBegin* block = block_at(i);
2014 LIR_List* ops = block->lir();
2015 int num_ops = ops->length();
2016
2017 // iterate all instructions of the block. skip the first because it is always a label
2018 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
2019 for (int j = 1; j < num_ops; j++) {
2020 LIR_Op* op = ops->at(j);
2021 int op_id = op->id();
2022
2023 if (op_id != -1 && has_info(op_id)) {
2024 // visit operation to collect all operands
2025 visitor.visit(op);
2026 assert(visitor.info_count() > 0, "should not visit otherwise");
2027
2028 XHandlers* xhandlers = visitor.all_xhandler();
2029 int n = xhandlers->length();
2030 for (int k = 0; k < n; k++) {
2031 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2032 }
2033
2034 #ifdef ASSERT
2035 } else {
2036 visitor.visit(op);
2037 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2038 #endif
2039 }
2040 }
2041 }
2042 }
2043
2044
2045 // ********** Phase 7: assign register numbers back to LIR
2046 // (includes computation of debug information and oop maps)
2047
2048 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2049 VMReg reg = interval->cached_vm_reg();
2050 if (!reg->is_valid() ) {
2051 reg = vm_reg_for_operand(operand_for_interval(interval));
2052 interval->set_cached_vm_reg(reg);
2053 }
2054 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2055 return reg;
2056 }
2057
2058 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2059 assert(opr->is_oop(), "currently only implemented for oop operands");
2060 return frame_map()->regname(opr);
2061 }
2062
2063
2064 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2065 LIR_Opr opr = interval->cached_opr();
2066 if (opr->is_illegal()) {
2067 opr = calc_operand_for_interval(interval);
2068 interval->set_cached_opr(opr);
2069 }
2070
2071 assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2072 return opr;
2073 }
2074
2075 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2076 int assigned_reg = interval->assigned_reg();
2077 BasicType type = interval->type();
2078
2079 if (assigned_reg >= nof_regs) {
2080 // stack slot
2081 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2082 return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2083
2084 } else {
2085 // register
2086 switch (type) {
2087 case T_OBJECT: {
2088 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2089 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2090 return LIR_OprFact::single_cpu_oop(assigned_reg);
2091 }
2092
2093 case T_ADDRESS: {
2094 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2095 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2096 return LIR_OprFact::single_cpu_address(assigned_reg);
2097 }
2098
2099 case T_METADATA: {
2100 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2101 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2102 return LIR_OprFact::single_cpu_metadata(assigned_reg);
2103 }
2104
2105 #ifdef __SOFTFP__
2106 case T_FLOAT: // fall through
2107 #endif // __SOFTFP__
2108 case T_INT: {
2109 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2110 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2111 return LIR_OprFact::single_cpu(assigned_reg);
2112 }
2113
2114 #ifdef __SOFTFP__
2115 case T_DOUBLE: // fall through
2116 #endif // __SOFTFP__
2117 case T_LONG: {
2118 int assigned_regHi = interval->assigned_regHi();
2119 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2120 assert(num_physical_regs(T_LONG) == 1 ||
2121 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2122
2123 assert(assigned_reg != assigned_regHi, "invalid allocation");
2124 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2125 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2126 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2127 if (requires_adjacent_regs(T_LONG)) {
2128 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2129 }
2130
2131 #ifdef _LP64
2132 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2133 #else
2134 #if defined(SPARC) || defined(PPC32)
2135 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2136 #else
2137 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2138 #endif // SPARC
2139 #endif // LP64
2140 }
2141
2142 #ifndef __SOFTFP__
2143 case T_FLOAT: {
2144 #ifdef X86
2145 if (UseSSE >= 1) {
2146 int last_xmm_reg = pd_last_xmm_reg;
2147 #ifdef _LP64
2148 if (UseAVX < 3) {
2149 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2150 }
2151 #endif
2152 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2153 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2154 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2155 }
2156 #endif
2157
2158 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2159 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2160 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2161 }
2162
2163 case T_DOUBLE: {
2164 #ifdef X86
2165 if (UseSSE >= 2) {
2166 int last_xmm_reg = pd_last_xmm_reg;
2167 #ifdef _LP64
2168 if (UseAVX < 3) {
2169 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2170 }
2171 #endif
2172 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2173 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2174 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2175 }
2176 #endif
2177
2178 #ifdef SPARC
2179 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2180 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2181 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2182 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2183 #elif defined(ARM32)
2184 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2185 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2186 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2187 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2188 #else
2189 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2190 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2191 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2192 #endif
2193 return result;
2194 }
2195 #endif // __SOFTFP__
2196
2197 default: {
2198 ShouldNotReachHere();
2199 return LIR_OprFact::illegalOpr;
2200 }
2201 }
2202 }
2203 }
2204
2205 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2206 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2207 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2208 }
2209
2210 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2211 assert(opr->is_virtual(), "should not call this otherwise");
2212
2213 Interval* interval = interval_at(opr->vreg_number());
2214 assert(interval != NULL, "interval must exist");
2215
2216 if (op_id != -1) {
2217 #ifdef ASSERT
2218 BlockBegin* block = block_of_op_with_id(op_id);
2219 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2220 // check if spill moves could have been appended at the end of this block, but
2221 // before the branch instruction. So the split child information for this branch would
2222 // be incorrect.
2223 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2224 if (branch != NULL) {
2225 if (block->live_out().at(opr->vreg_number())) {
2226 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2227 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2228 }
2229 }
2230 }
2231 #endif
2232
2233 // operands are not changed when an interval is split during allocation,
2234 // so search the right interval here
2235 interval = split_child_at_op_id(interval, op_id, mode);
2236 }
2237
2238 LIR_Opr res = operand_for_interval(interval);
2239
2240 #ifdef X86
2241 // new semantic for is_last_use: not only set on definite end of interval,
2242 // but also before hole
2243 // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2244 // last use information is completely correct
2245 // information is only needed for fpu stack allocation
2246 if (res->is_fpu_register()) {
2247 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2248 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2249 res = res->make_last_use();
2250 }
2251 }
2252 #endif
2253
2254 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2255
2256 return res;
2257 }
2258
2259
2260 #ifdef ASSERT
2261 // some methods used to check correctness of debug information
2262
2263 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2264 if (values == NULL) {
2265 return;
2266 }
2267
2268 for (int i = 0; i < values->length(); i++) {
2269 ScopeValue* value = values->at(i);
2270
2271 if (value->is_location()) {
2272 Location location = ((LocationValue*)value)->location();
2273 assert(location.where() == Location::on_stack, "value is in register");
2274 }
2275 }
2276 }
2277
2278 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2279 if (values == NULL) {
2280 return;
2281 }
2282
2283 for (int i = 0; i < values->length(); i++) {
2284 MonitorValue* value = values->at(i);
2285
2286 if (value->owner()->is_location()) {
2287 Location location = ((LocationValue*)value->owner())->location();
2288 assert(location.where() == Location::on_stack, "owner is in register");
2289 }
2290 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2291 }
2292 }
2293
2294 void assert_equal(Location l1, Location l2) {
2295 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2296 }
2297
2298 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2299 if (v1->is_location()) {
2300 assert(v2->is_location(), "");
2301 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2302 } else if (v1->is_constant_int()) {
2303 assert(v2->is_constant_int(), "");
2304 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2305 } else if (v1->is_constant_double()) {
2306 assert(v2->is_constant_double(), "");
2307 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2308 } else if (v1->is_constant_long()) {
2309 assert(v2->is_constant_long(), "");
2310 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2311 } else if (v1->is_constant_oop()) {
2312 assert(v2->is_constant_oop(), "");
2313 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2314 } else {
2315 ShouldNotReachHere();
2316 }
2317 }
2318
2319 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2320 assert_equal(m1->owner(), m2->owner());
2321 assert_equal(m1->basic_lock(), m2->basic_lock());
2322 }
2323
2324 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2325 assert(d1->scope() == d2->scope(), "not equal");
2326 assert(d1->bci() == d2->bci(), "not equal");
2327
2328 if (d1->locals() != NULL) {
2329 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2330 assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2331 for (int i = 0; i < d1->locals()->length(); i++) {
2332 assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2333 }
2334 } else {
2335 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2336 }
2337
2338 if (d1->expressions() != NULL) {
2339 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2340 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2341 for (int i = 0; i < d1->expressions()->length(); i++) {
2342 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2343 }
2344 } else {
2345 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2346 }
2347
2348 if (d1->monitors() != NULL) {
2349 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2350 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2351 for (int i = 0; i < d1->monitors()->length(); i++) {
2352 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2353 }
2354 } else {
2355 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2356 }
2357
2358 if (d1->caller() != NULL) {
2359 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2360 assert_equal(d1->caller(), d2->caller());
2361 } else {
2362 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2363 }
2364 }
2365
2366 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2367 if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2368 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2369 switch (code) {
2370 case Bytecodes::_ifnull : // fall through
2371 case Bytecodes::_ifnonnull : // fall through
2372 case Bytecodes::_ifeq : // fall through
2373 case Bytecodes::_ifne : // fall through
2374 case Bytecodes::_iflt : // fall through
2375 case Bytecodes::_ifge : // fall through
2376 case Bytecodes::_ifgt : // fall through
2377 case Bytecodes::_ifle : // fall through
2378 case Bytecodes::_if_icmpeq : // fall through
2379 case Bytecodes::_if_icmpne : // fall through
2380 case Bytecodes::_if_icmplt : // fall through
2381 case Bytecodes::_if_icmpge : // fall through
2382 case Bytecodes::_if_icmpgt : // fall through
2383 case Bytecodes::_if_icmple : // fall through
2384 case Bytecodes::_if_acmpeq : // fall through
2385 case Bytecodes::_if_acmpne :
2386 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2387 break;
2388 default:
2389 break;
2390 }
2391 }
2392 }
2393
2394 #endif // ASSERT
2395
2396
2397 IntervalWalker* LinearScan::init_compute_oop_maps() {
2398 // setup lists of potential oops for walking
2399 Interval* oop_intervals;
2400 Interval* non_oop_intervals;
2401
2402 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2403
2404 // intervals that have no oops inside need not to be processed
2405 // to ensure a walking until the last instruction id, add a dummy interval
2406 // with a high operation id
2407 non_oop_intervals = new Interval(any_reg);
2408 non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2409
2410 return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2411 }
2412
2413
2414 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2415 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2416
2417 // walk before the current operation -> intervals that start at
2418 // the operation (= output operands of the operation) are not
2419 // included in the oop map
2420 iw->walk_before(op->id());
2421
2422 int frame_size = frame_map()->framesize();
2423 int arg_count = frame_map()->oop_map_arg_count();
2424 OopMap* map = new OopMap(frame_size, arg_count);
2425
2426 // Iterate through active intervals
2427 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2428 int assigned_reg = interval->assigned_reg();
2429
2430 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2431 assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2432 assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2433
2434 // Check if this range covers the instruction. Intervals that
2435 // start or end at the current operation are not included in the
2436 // oop map, except in the case of patching moves. For patching
2437 // moves, any intervals which end at this instruction are included
2438 // in the oop map since we may safepoint while doing the patch
2439 // before we've consumed the inputs.
2440 if (op->is_patching() || op->id() < interval->current_to()) {
2441
2442 // caller-save registers must not be included into oop-maps at calls
2443 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2444
2445 VMReg name = vm_reg_for_interval(interval);
2446 set_oop(map, name);
2447
2448 // Spill optimization: when the stack value is guaranteed to be always correct,
2449 // then it must be added to the oop map even if the interval is currently in a register
2450 if (interval->always_in_memory() &&
2451 op->id() > interval->spill_definition_pos() &&
2452 interval->assigned_reg() != interval->canonical_spill_slot()) {
2453 assert(interval->spill_definition_pos() > 0, "position not set correctly");
2454 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2455 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2456
2457 set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2458 }
2459 }
2460 }
2461
2462 // add oops from lock stack
2463 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2464 int locks_count = info->stack()->total_locks_size();
2465 for (int i = 0; i < locks_count; i++) {
2466 set_oop(map, frame_map()->monitor_object_regname(i));
2467 }
2468
2469 return map;
2470 }
2471
2472
2473 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2474 assert(visitor.info_count() > 0, "no oop map needed");
2475
2476 // compute oop_map only for first CodeEmitInfo
2477 // because it is (in most cases) equal for all other infos of the same operation
2478 CodeEmitInfo* first_info = visitor.info_at(0);
2479 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2480
2481 for (int i = 0; i < visitor.info_count(); i++) {
2482 CodeEmitInfo* info = visitor.info_at(i);
2483 OopMap* oop_map = first_oop_map;
2484
2485 // compute worst case interpreter size in case of a deoptimization
2486 _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2487
2488 if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2489 // this info has a different number of locks then the precomputed oop map
2490 // (possible for lock and unlock instructions) -> compute oop map with
2491 // correct lock information
2492 oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2493 }
2494
2495 if (info->_oop_map == NULL) {
2496 info->_oop_map = oop_map;
2497 } else {
2498 // a CodeEmitInfo can not be shared between different LIR-instructions
2499 // because interval splitting can occur anywhere between two instructions
2500 // and so the oop maps must be different
2501 // -> check if the already set oop_map is exactly the one calculated for this operation
2502 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2503 }
2504 }
2505 }
2506
2507
2508 // frequently used constants
2509 // Allocate them with new so they are never destroyed (otherwise, a
2510 // forced exit could destroy these objects while they are still in
2511 // use).
2512 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2513 ConstantIntValue* LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2514 ConstantIntValue* LinearScan::_int_0_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue((jint)0);
2515 ConstantIntValue* LinearScan::_int_1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2516 ConstantIntValue* LinearScan::_int_2_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2517 LocationValue* _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2518
2519 void LinearScan::init_compute_debug_info() {
2520 // cache for frequently used scope values
2521 // (cpu registers and stack slots)
2522 int cache_size = (LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2;
2523 _scope_value_cache = ScopeValueArray(cache_size, cache_size, NULL);
2524 }
2525
2526 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2527 Location loc;
2528 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2529 bailout("too large frame");
2530 }
2531 ScopeValue* object_scope_value = new LocationValue(loc);
2532
2533 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2534 bailout("too large frame");
2535 }
2536 return new MonitorValue(object_scope_value, loc);
2537 }
2538
2539 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2540 Location loc;
2541 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2542 bailout("too large frame");
2543 }
2544 return new LocationValue(loc);
2545 }
2546
2547
2548 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2549 assert(opr->is_constant(), "should not be called otherwise");
2550
2551 LIR_Const* c = opr->as_constant_ptr();
2552 BasicType t = c->type();
2553 switch (t) {
2554 case T_OBJECT: {
2555 jobject value = c->as_jobject();
2556 if (value == NULL) {
2557 scope_values->append(_oop_null_scope_value);
2558 } else {
2559 scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2560 }
2561 return 1;
2562 }
2563
2564 case T_INT: // fall through
2565 case T_FLOAT: {
2566 int value = c->as_jint_bits();
2567 switch (value) {
2568 case -1: scope_values->append(_int_m1_scope_value); break;
2569 case 0: scope_values->append(_int_0_scope_value); break;
2570 case 1: scope_values->append(_int_1_scope_value); break;
2571 case 2: scope_values->append(_int_2_scope_value); break;
2572 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2573 }
2574 return 1;
2575 }
2576
2577 case T_LONG: // fall through
2578 case T_DOUBLE: {
2579 #ifdef _LP64
2580 scope_values->append(_int_0_scope_value);
2581 scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2582 #else
2583 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2584 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2585 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2586 } else {
2587 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2588 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2589 }
2590 #endif
2591 return 2;
2592 }
2593
2594 case T_ADDRESS: {
2595 #ifdef _LP64
2596 scope_values->append(new ConstantLongValue(c->as_jint()));
2597 #else
2598 scope_values->append(new ConstantIntValue(c->as_jint()));
2599 #endif
2600 return 1;
2601 }
2602
2603 default:
2604 ShouldNotReachHere();
2605 return -1;
2606 }
2607 }
2608
2609 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2610 if (opr->is_single_stack()) {
2611 int stack_idx = opr->single_stack_ix();
2612 bool is_oop = opr->is_oop_register();
2613 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2614
2615 ScopeValue* sv = _scope_value_cache.at(cache_idx);
2616 if (sv == NULL) {
2617 Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2618 sv = location_for_name(stack_idx, loc_type);
2619 _scope_value_cache.at_put(cache_idx, sv);
2620 }
2621
2622 // check if cached value is correct
2623 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2624
2625 scope_values->append(sv);
2626 return 1;
2627
2628 } else if (opr->is_single_cpu()) {
2629 bool is_oop = opr->is_oop_register();
2630 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2631 Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2632
2633 ScopeValue* sv = _scope_value_cache.at(cache_idx);
2634 if (sv == NULL) {
2635 Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2636 VMReg rname = frame_map()->regname(opr);
2637 sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2638 _scope_value_cache.at_put(cache_idx, sv);
2639 }
2640
2641 // check if cached value is correct
2642 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2643
2644 scope_values->append(sv);
2645 return 1;
2646
2647 #ifdef X86
2648 } else if (opr->is_single_xmm()) {
2649 VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2650 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2651
2652 scope_values->append(sv);
2653 return 1;
2654 #endif
2655
2656 } else if (opr->is_single_fpu()) {
2657 #ifdef X86
2658 // the exact location of fpu stack values is only known
2659 // during fpu stack allocation, so the stack allocator object
2660 // must be present
2661 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2662 assert(_fpu_stack_allocator != NULL, "must be present");
2663 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2664 #endif
2665
2666 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2667 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2668 #ifndef __SOFTFP__
2669 #ifndef VM_LITTLE_ENDIAN
2670 // On S390 a (single precision) float value occupies only the high
2671 // word of the full double register. So when the double register is
2672 // stored to memory (e.g. by the RegisterSaver), then the float value
2673 // is found at offset 0. I.e. the code below is not needed on S390.
2674 #ifndef S390
2675 if (! float_saved_as_double) {
2676 // On big endian system, we may have an issue if float registers use only
2677 // the low half of the (same) double registers.
2678 // Both the float and the double could have the same regnr but would correspond
2679 // to two different addresses once saved.
2680
2681 // get next safely (no assertion checks)
2682 VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2683 if (next->is_reg() &&
2684 (next->as_FloatRegister() == rname->as_FloatRegister())) {
2685 // the back-end does use the same numbering for the double and the float
2686 rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2687 }
2688 }
2689 #endif // !S390
2690 #endif
2691 #endif
2692 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2693
2694 scope_values->append(sv);
2695 return 1;
2696
2697 } else {
2698 // double-size operands
2699
2700 ScopeValue* first;
2701 ScopeValue* second;
2702
2703 if (opr->is_double_stack()) {
2704 #ifdef _LP64
2705 Location loc1;
2706 Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2707 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2708 bailout("too large frame");
2709 }
2710 // Does this reverse on x86 vs. sparc?
2711 first = new LocationValue(loc1);
2712 second = _int_0_scope_value;
2713 #else
2714 Location loc1, loc2;
2715 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2716 bailout("too large frame");
2717 }
2718 first = new LocationValue(loc1);
2719 second = new LocationValue(loc2);
2720 #endif // _LP64
2721
2722 } else if (opr->is_double_cpu()) {
2723 #ifdef _LP64
2724 VMReg rname_first = opr->as_register_lo()->as_VMReg();
2725 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2726 second = _int_0_scope_value;
2727 #else
2728 VMReg rname_first = opr->as_register_lo()->as_VMReg();
2729 VMReg rname_second = opr->as_register_hi()->as_VMReg();
2730
2731 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2732 // lo/hi and swapped relative to first and second, so swap them
2733 VMReg tmp = rname_first;
2734 rname_first = rname_second;
2735 rname_second = tmp;
2736 }
2737
2738 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2739 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2740 #endif //_LP64
2741
2742
2743 #ifdef X86
2744 } else if (opr->is_double_xmm()) {
2745 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2746 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg();
2747 # ifdef _LP64
2748 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2749 second = _int_0_scope_value;
2750 # else
2751 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2752 // %%% This is probably a waste but we'll keep things as they were for now
2753 if (true) {
2754 VMReg rname_second = rname_first->next();
2755 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2756 }
2757 # endif
2758 #endif
2759
2760 } else if (opr->is_double_fpu()) {
2761 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2762 // the double as float registers in the native ordering. On X86,
2763 // fpu_regnrLo is a FPU stack slot whose VMReg represents
2764 // the low-order word of the double and fpu_regnrLo + 1 is the
2765 // name for the other half. *first and *second must represent the
2766 // least and most significant words, respectively.
2767
2768 #ifdef X86
2769 // the exact location of fpu stack values is only known
2770 // during fpu stack allocation, so the stack allocator object
2771 // must be present
2772 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2773 assert(_fpu_stack_allocator != NULL, "must be present");
2774 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2775
2776 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2777 #endif
2778 #ifdef SPARC
2779 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2780 #endif
2781 #ifdef ARM32
2782 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2783 #endif
2784 #ifdef PPC32
2785 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2786 #endif
2787
2788 #ifdef VM_LITTLE_ENDIAN
2789 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2790 #else
2791 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2792 #endif
2793
2794 #ifdef _LP64
2795 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2796 second = _int_0_scope_value;
2797 #else
2798 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2799 // %%% This is probably a waste but we'll keep things as they were for now
2800 if (true) {
2801 VMReg rname_second = rname_first->next();
2802 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2803 }
2804 #endif
2805
2806 } else {
2807 ShouldNotReachHere();
2808 first = NULL;
2809 second = NULL;
2810 }
2811
2812 assert(first != NULL && second != NULL, "must be set");
2813 // The convention the interpreter uses is that the second local
2814 // holds the first raw word of the native double representation.
2815 // This is actually reasonable, since locals and stack arrays
2816 // grow downwards in all implementations.
2817 // (If, on some machine, the interpreter's Java locals or stack
2818 // were to grow upwards, the embedded doubles would be word-swapped.)
2819 scope_values->append(second);
2820 scope_values->append(first);
2821 return 2;
2822 }
2823 }
2824
2825
2826 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2827 if (value != NULL) {
2828 LIR_Opr opr = value->operand();
2829 Constant* con = value->as_Constant();
2830
2831 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2832 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2833
2834 if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2835 // Unpinned constants may have a virtual operand for a part of the lifetime
2836 // or may be illegal when it was optimized away,
2837 // so always use a constant operand
2838 opr = LIR_OprFact::value_type(con->type());
2839 }
2840 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2841
2842 if (opr->is_virtual()) {
2843 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2844
2845 BlockBegin* block = block_of_op_with_id(op_id);
2846 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2847 // generating debug information for the last instruction of a block.
2848 // if this instruction is a branch, spill moves are inserted before this branch
2849 // and so the wrong operand would be returned (spill moves at block boundaries are not
2850 // considered in the live ranges of intervals)
2851 // Solution: use the first op_id of the branch target block instead.
2852 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2853 if (block->live_out().at(opr->vreg_number())) {
2854 op_id = block->sux_at(0)->first_lir_instruction_id();
2855 mode = LIR_OpVisitState::outputMode;
2856 }
2857 }
2858 }
2859
2860 // Get current location of operand
2861 // The operand must be live because debug information is considered when building the intervals
2862 // if the interval is not live, color_lir_opr will cause an assertion failure
2863 opr = color_lir_opr(opr, op_id, mode);
2864 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2865
2866 // Append to ScopeValue array
2867 return append_scope_value_for_operand(opr, scope_values);
2868
2869 } else {
2870 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2871 assert(opr->is_constant(), "operand must be constant");
2872
2873 return append_scope_value_for_constant(opr, scope_values);
2874 }
2875 } else {
2876 // append a dummy value because real value not needed
2877 scope_values->append(_illegal_value);
2878 return 1;
2879 }
2880 }
2881
2882
2883 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2884 IRScopeDebugInfo* caller_debug_info = NULL;
2885
2886 ValueStack* caller_state = cur_state->caller_state();
2887 if (caller_state != NULL) {
2888 // process recursively to compute outermost scope first
2889 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2890 }
2891
2892 // initialize these to null.
2893 // If we don't need deopt info or there are no locals, expressions or monitors,
2894 // then these get recorded as no information and avoids the allocation of 0 length arrays.
2895 GrowableArray<ScopeValue*>* locals = NULL;
2896 GrowableArray<ScopeValue*>* expressions = NULL;
2897 GrowableArray<MonitorValue*>* monitors = NULL;
2898
2899 // describe local variable values
2900 int nof_locals = cur_state->locals_size();
2901 if (nof_locals > 0) {
2902 locals = new GrowableArray<ScopeValue*>(nof_locals);
2903
2904 int pos = 0;
2905 while (pos < nof_locals) {
2906 assert(pos < cur_state->locals_size(), "why not?");
2907
2908 Value local = cur_state->local_at(pos);
2909 pos += append_scope_value(op_id, local, locals);
2910
2911 assert(locals->length() == pos, "must match");
2912 }
2913 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2914 assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2915 } else if (cur_scope->method()->max_locals() > 0) {
2916 assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2917 nof_locals = cur_scope->method()->max_locals();
2918 locals = new GrowableArray<ScopeValue*>(nof_locals);
2919 for(int i = 0; i < nof_locals; i++) {
2920 locals->append(_illegal_value);
2921 }
2922 }
2923
2924 // describe expression stack
2925 int nof_stack = cur_state->stack_size();
2926 if (nof_stack > 0) {
2927 expressions = new GrowableArray<ScopeValue*>(nof_stack);
2928
2929 int pos = 0;
2930 while (pos < nof_stack) {
2931 Value expression = cur_state->stack_at_inc(pos);
2932 append_scope_value(op_id, expression, expressions);
2933
2934 assert(expressions->length() == pos, "must match");
2935 }
2936 assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2937 }
2938
2939 // describe monitors
2940 int nof_locks = cur_state->locks_size();
2941 if (nof_locks > 0) {
2942 int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2943 monitors = new GrowableArray<MonitorValue*>(nof_locks);
2944 for (int i = 0; i < nof_locks; i++) {
2945 monitors->append(location_for_monitor_index(lock_offset + i));
2946 }
2947 }
2948
2949 return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2950 }
2951
2952
2953 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2954 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2955
2956 IRScope* innermost_scope = info->scope();
2957 ValueStack* innermost_state = info->stack();
2958
2959 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2960
2961 DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2962
2963 if (info->_scope_debug_info == NULL) {
2964 // compute debug information
2965 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2966 } else {
2967 // debug information already set. Check that it is correct from the current point of view
2968 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2969 }
2970 }
2971
2972
2973 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2974 LIR_OpVisitState visitor;
2975 int num_inst = instructions->length();
2976 bool has_dead = false;
2977
2978 for (int j = 0; j < num_inst; j++) {
2979 LIR_Op* op = instructions->at(j);
2980 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves
2981 has_dead = true;
2982 continue;
2983 }
2984 int op_id = op->id();
2985
2986 // visit instruction to get list of operands
2987 visitor.visit(op);
2988
2989 // iterate all modes of the visitor and process all virtual operands
2990 for_each_visitor_mode(mode) {
2991 int n = visitor.opr_count(mode);
2992 for (int k = 0; k < n; k++) {
2993 LIR_Opr opr = visitor.opr_at(mode, k);
2994 if (opr->is_virtual_register()) {
2995 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
2996 }
2997 }
2998 }
2999
3000 if (visitor.info_count() > 0) {
3001 // exception handling
3002 if (compilation()->has_exception_handlers()) {
3003 XHandlers* xhandlers = visitor.all_xhandler();
3004 int n = xhandlers->length();
3005 for (int k = 0; k < n; k++) {
3006 XHandler* handler = xhandlers->handler_at(k);
3007 if (handler->entry_code() != NULL) {
3008 assign_reg_num(handler->entry_code()->instructions_list(), NULL);
3009 }
3010 }
3011 } else {
3012 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
3013 }
3014
3015 // compute oop map
3016 assert(iw != NULL, "needed for compute_oop_map");
3017 compute_oop_map(iw, visitor, op);
3018
3019 // compute debug information
3020 if (!use_fpu_stack_allocation()) {
3021 // compute debug information if fpu stack allocation is not needed.
3022 // when fpu stack allocation is needed, the debug information can not
3023 // be computed here because the exact location of fpu operands is not known
3024 // -> debug information is created inside the fpu stack allocator
3025 int n = visitor.info_count();
3026 for (int k = 0; k < n; k++) {
3027 compute_debug_info(visitor.info_at(k), op_id);
3028 }
3029 }
3030 }
3031
3032 #ifdef ASSERT
3033 // make sure we haven't made the op invalid.
3034 op->verify();
3035 #endif
3036
3037 // remove useless moves
3038 if (op->code() == lir_move) {
3039 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3040 LIR_Op1* move = (LIR_Op1*)op;
3041 LIR_Opr src = move->in_opr();
3042 LIR_Opr dst = move->result_opr();
3043 if (dst == src ||
3044 (!dst->is_pointer() && !src->is_pointer() &&
3045 src->is_same_register(dst))) {
3046 instructions->at_put(j, NULL);
3047 has_dead = true;
3048 }
3049 }
3050 }
3051
3052 if (has_dead) {
3053 // iterate all instructions of the block and remove all null-values.
3054 int insert_point = 0;
3055 for (int j = 0; j < num_inst; j++) {
3056 LIR_Op* op = instructions->at(j);
3057 if (op != NULL) {
3058 if (insert_point != j) {
3059 instructions->at_put(insert_point, op);
3060 }
3061 insert_point++;
3062 }
3063 }
3064 instructions->trunc_to(insert_point);
3065 }
3066 }
3067
3068 void LinearScan::assign_reg_num() {
3069 TIME_LINEAR_SCAN(timer_assign_reg_num);
3070
3071 init_compute_debug_info();
3072 IntervalWalker* iw = init_compute_oop_maps();
3073
3074 int num_blocks = block_count();
3075 for (int i = 0; i < num_blocks; i++) {
3076 BlockBegin* block = block_at(i);
3077 assign_reg_num(block->lir()->instructions_list(), iw);
3078 }
3079 }
3080
3081
3082 void LinearScan::do_linear_scan() {
3083 NOT_PRODUCT(_total_timer.begin_method());
3084
3085 number_instructions();
3086
3087 NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3088
3089 compute_local_live_sets();
3090 compute_global_live_sets();
3091 CHECK_BAILOUT();
3092
3093 build_intervals();
3094 CHECK_BAILOUT();
3095 sort_intervals_before_allocation();
3096
3097 NOT_PRODUCT(print_intervals("Before Register Allocation"));
3098 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3099
3100 allocate_registers();
3101 CHECK_BAILOUT();
3102
3103 resolve_data_flow();
3104 if (compilation()->has_exception_handlers()) {
3105 resolve_exception_handlers();
3106 }
3107 // fill in number of spill slots into frame_map
3108 propagate_spill_slots();
3109 CHECK_BAILOUT();
3110
3111 NOT_PRODUCT(print_intervals("After Register Allocation"));
3112 NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3113
3114 sort_intervals_after_allocation();
3115
3116 DEBUG_ONLY(verify());
3117
3118 eliminate_spill_moves();
3119 assign_reg_num();
3120 CHECK_BAILOUT();
3121
3122 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3123 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3124
3125 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3126
3127 if (use_fpu_stack_allocation()) {
3128 allocate_fpu_stack(); // Only has effect on Intel
3129 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3130 }
3131 }
3132
3133 { TIME_LINEAR_SCAN(timer_optimize_lir);
3134
3135 EdgeMoveOptimizer::optimize(ir()->code());
3136 ControlFlowOptimizer::optimize(ir()->code());
3137 // check that cfg is still correct after optimizations
3138 ir()->verify();
3139 }
3140
3141 NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3142 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3143 NOT_PRODUCT(_total_timer.end_method(this));
3144 }
3145
3146
3147 // ********** Printing functions
3148
3149 #ifndef PRODUCT
3150
3151 void LinearScan::print_timers(double total) {
3152 _total_timer.print(total);
3153 }
3154
3155 void LinearScan::print_statistics() {
3156 _stat_before_alloc.print("before allocation");
3157 _stat_after_asign.print("after assignment of register");
3158 _stat_final.print("after optimization");
3159 }
3160
3161 void LinearScan::print_bitmap(BitMap& b) {
3162 for (unsigned int i = 0; i < b.size(); i++) {
3163 if (b.at(i)) tty->print("%d ", i);
3164 }
3165 tty->cr();
3166 }
3167
3168 void LinearScan::print_intervals(const char* label) {
3169 if (TraceLinearScanLevel >= 1) {
3170 int i;
3171 tty->cr();
3172 tty->print_cr("%s", label);
3173
3174 for (i = 0; i < interval_count(); i++) {
3175 Interval* interval = interval_at(i);
3176 if (interval != NULL) {
3177 interval->print();
3178 }
3179 }
3180
3181 tty->cr();
3182 tty->print_cr("--- Basic Blocks ---");
3183 for (i = 0; i < block_count(); i++) {
3184 BlockBegin* block = block_at(i);
3185 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3186 }
3187 tty->cr();
3188 tty->cr();
3189 }
3190
3191 if (PrintCFGToFile) {
3192 CFGPrinter::print_intervals(&_intervals, label);
3193 }
3194 }
3195
3196 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3197 if (TraceLinearScanLevel >= level) {
3198 tty->cr();
3199 tty->print_cr("%s", label);
3200 print_LIR(ir()->linear_scan_order());
3201 tty->cr();
3202 }
3203
3204 if (level == 1 && PrintCFGToFile) {
3205 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3206 }
3207 }
3208
3209 #endif //PRODUCT
3210
3211
3212 // ********** verification functions for allocation
3213 // (check that all intervals have a correct register and that no registers are overwritten)
3214 #ifdef ASSERT
3215
3216 void LinearScan::verify() {
3217 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3218 verify_intervals();
3219
3220 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3221 verify_no_oops_in_fixed_intervals();
3222
3223 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3224 verify_constants();
3225
3226 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3227 verify_registers();
3228
3229 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3230 }
3231
3232 void LinearScan::verify_intervals() {
3233 int len = interval_count();
3234 bool has_error = false;
3235
3236 for (int i = 0; i < len; i++) {
3237 Interval* i1 = interval_at(i);
3238 if (i1 == NULL) continue;
3239
3240 i1->check_split_children();
3241
3242 if (i1->reg_num() != i) {
3243 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3244 has_error = true;
3245 }
3246
3247 if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3248 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3249 has_error = true;
3250 }
3251
3252 if (i1->assigned_reg() == any_reg) {
3253 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3254 has_error = true;
3255 }
3256
3257 if (i1->assigned_reg() == i1->assigned_regHi()) {
3258 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3259 has_error = true;
3260 }
3261
3262 if (!is_processed_reg_num(i1->assigned_reg())) {
3263 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3264 has_error = true;
3265 }
3266
3267 // special intervals that are created in MoveResolver
3268 // -> ignore them because the range information has no meaning there
3269 if (i1->from() == 1 && i1->to() == 2) continue;
3270
3271 if (i1->first() == Range::end()) {
3272 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3273 has_error = true;
3274 }
3275
3276 for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3277 if (r->from() >= r->to()) {
3278 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3279 has_error = true;
3280 }
3281 }
3282
3283 for (int j = i + 1; j < len; j++) {
3284 Interval* i2 = interval_at(j);
3285 if (i2 == NULL || (i2->from() == 1 && i2->to() == 2)) continue;
3286
3287 int r1 = i1->assigned_reg();
3288 int r1Hi = i1->assigned_regHi();
3289 int r2 = i2->assigned_reg();
3290 int r2Hi = i2->assigned_regHi();
3291 if ((r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi))) && i1->intersects(i2)) {
3292 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3293 i1->print(); tty->cr();
3294 i2->print(); tty->cr();
3295 has_error = true;
3296 }
3297 }
3298 }
3299
3300 assert(has_error == false, "register allocation invalid");
3301 }
3302
3303
3304 void LinearScan::verify_no_oops_in_fixed_intervals() {
3305 Interval* fixed_intervals;
3306 Interval* other_intervals;
3307 create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3308
3309 // to ensure a walking until the last instruction id, add a dummy interval
3310 // with a high operation id
3311 other_intervals = new Interval(any_reg);
3312 other_intervals->add_range(max_jint - 2, max_jint - 1);
3313 IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3314
3315 LIR_OpVisitState visitor;
3316 for (int i = 0; i < block_count(); i++) {
3317 BlockBegin* block = block_at(i);
3318
3319 LIR_OpList* instructions = block->lir()->instructions_list();
3320
3321 for (int j = 0; j < instructions->length(); j++) {
3322 LIR_Op* op = instructions->at(j);
3323 int op_id = op->id();
3324
3325 visitor.visit(op);
3326
3327 if (visitor.info_count() > 0) {
3328 iw->walk_before(op->id());
3329 bool check_live = true;
3330 if (op->code() == lir_move) {
3331 LIR_Op1* move = (LIR_Op1*)op;
3332 check_live = (move->patch_code() == lir_patch_none);
3333 }
3334 LIR_OpBranch* branch = op->as_OpBranch();
3335 if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3336 // Don't bother checking the stub in this case since the
3337 // exception stub will never return to normal control flow.
3338 check_live = false;
3339 }
3340
3341 // Make sure none of the fixed registers is live across an
3342 // oopmap since we can't handle that correctly.
3343 if (check_live) {
3344 for (Interval* interval = iw->active_first(fixedKind);
3345 interval != Interval::end();
3346 interval = interval->next()) {
3347 if (interval->current_to() > op->id() + 1) {
3348 // This interval is live out of this op so make sure
3349 // that this interval represents some value that's
3350 // referenced by this op either as an input or output.
3351 bool ok = false;
3352 for_each_visitor_mode(mode) {
3353 int n = visitor.opr_count(mode);
3354 for (int k = 0; k < n; k++) {
3355 LIR_Opr opr = visitor.opr_at(mode, k);
3356 if (opr->is_fixed_cpu()) {
3357 if (interval_at(reg_num(opr)) == interval) {
3358 ok = true;
3359 break;
3360 }
3361 int hi = reg_numHi(opr);
3362 if (hi != -1 && interval_at(hi) == interval) {
3363 ok = true;
3364 break;
3365 }
3366 }
3367 }
3368 }
3369 assert(ok, "fixed intervals should never be live across an oopmap point");
3370 }
3371 }
3372 }
3373 }
3374
3375 // oop-maps at calls do not contain registers, so check is not needed
3376 if (!visitor.has_call()) {
3377
3378 for_each_visitor_mode(mode) {
3379 int n = visitor.opr_count(mode);
3380 for (int k = 0; k < n; k++) {
3381 LIR_Opr opr = visitor.opr_at(mode, k);
3382
3383 if (opr->is_fixed_cpu() && opr->is_oop()) {
3384 // operand is a non-virtual cpu register and contains an oop
3385 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3386
3387 Interval* interval = interval_at(reg_num(opr));
3388 assert(interval != NULL, "no interval");
3389
3390 if (mode == LIR_OpVisitState::inputMode) {
3391 if (interval->to() >= op_id + 1) {
3392 assert(interval->to() < op_id + 2 ||
3393 interval->has_hole_between(op_id, op_id + 2),
3394 "oop input operand live after instruction");
3395 }
3396 } else if (mode == LIR_OpVisitState::outputMode) {
3397 if (interval->from() <= op_id - 1) {
3398 assert(interval->has_hole_between(op_id - 1, op_id),
3399 "oop input operand live after instruction");
3400 }
3401 }
3402 }
3403 }
3404 }
3405 }
3406 }
3407 }
3408 }
3409
3410
3411 void LinearScan::verify_constants() {
3412 int num_regs = num_virtual_regs();
3413 int size = live_set_size();
3414 int num_blocks = block_count();
3415
3416 for (int i = 0; i < num_blocks; i++) {
3417 BlockBegin* block = block_at(i);
3418 ResourceBitMap live_at_edge = block->live_in();
3419
3420 // visit all registers where the live_at_edge bit is set
3421 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3422 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3423
3424 Value value = gen()->instruction_for_vreg(r);
3425
3426 assert(value != NULL, "all intervals live across block boundaries must have Value");
3427 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3428 assert(value->operand()->vreg_number() == r, "register number must match");
3429 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3430 }
3431 }
3432 }
3433
3434
3435 class RegisterVerifier: public StackObj {
3436 private:
3437 LinearScan* _allocator;
3438 BlockList _work_list; // all blocks that must be processed
3439 IntervalsList _saved_states; // saved information of previous check
3440
3441 // simplified access to methods of LinearScan
3442 Compilation* compilation() const { return _allocator->compilation(); }
3443 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); }
3444 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); }
3445
3446 // currently, only registers are processed
3447 int state_size() { return LinearScan::nof_regs; }
3448
3449 // accessors
3450 IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3451 void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3452 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3453
3454 // helper functions
3455 IntervalList* copy(IntervalList* input_state);
3456 void state_put(IntervalList* input_state, int reg, Interval* interval);
3457 bool check_state(IntervalList* input_state, int reg, Interval* interval);
3458
3459 void process_block(BlockBegin* block);
3460 void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3461 void process_successor(BlockBegin* block, IntervalList* input_state);
3462 void process_operations(LIR_List* ops, IntervalList* input_state);
3463
3464 public:
3465 RegisterVerifier(LinearScan* allocator)
3466 : _allocator(allocator)
3467 , _work_list(16)
3468 , _saved_states(BlockBegin::number_of_blocks(), BlockBegin::number_of_blocks(), NULL)
3469 { }
3470
3471 void verify(BlockBegin* start);
3472 };
3473
3474
3475 // entry function from LinearScan that starts the verification
3476 void LinearScan::verify_registers() {
3477 RegisterVerifier verifier(this);
3478 verifier.verify(block_at(0));
3479 }
3480
3481
3482 void RegisterVerifier::verify(BlockBegin* start) {
3483 // setup input registers (method arguments) for first block
3484 int input_state_len = state_size();
3485 IntervalList* input_state = new IntervalList(input_state_len, input_state_len, NULL);
3486 CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3487 for (int n = 0; n < args->length(); n++) {
3488 LIR_Opr opr = args->at(n);
3489 if (opr->is_register()) {
3490 Interval* interval = interval_at(reg_num(opr));
3491
3492 if (interval->assigned_reg() < state_size()) {
3493 input_state->at_put(interval->assigned_reg(), interval);
3494 }
3495 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3496 input_state->at_put(interval->assigned_regHi(), interval);
3497 }
3498 }
3499 }
3500
3501 set_state_for_block(start, input_state);
3502 add_to_work_list(start);
3503
3504 // main loop for verification
3505 do {
3506 BlockBegin* block = _work_list.at(0);
3507 _work_list.remove_at(0);
3508
3509 process_block(block);
3510 } while (!_work_list.is_empty());
3511 }
3512
3513 void RegisterVerifier::process_block(BlockBegin* block) {
3514 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3515
3516 // must copy state because it is modified
3517 IntervalList* input_state = copy(state_for_block(block));
3518
3519 if (TraceLinearScanLevel >= 4) {
3520 tty->print_cr("Input-State of intervals:");
3521 tty->print(" ");
3522 for (int i = 0; i < state_size(); i++) {
3523 if (input_state->at(i) != NULL) {
3524 tty->print(" %4d", input_state->at(i)->reg_num());
3525 } else {
3526 tty->print(" __");
3527 }
3528 }
3529 tty->cr();
3530 tty->cr();
3531 }
3532
3533 // process all operations of the block
3534 process_operations(block->lir(), input_state);
3535
3536 // iterate all successors
3537 for (int i = 0; i < block->number_of_sux(); i++) {
3538 process_successor(block->sux_at(i), input_state);
3539 }
3540 }
3541
3542 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3543 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3544
3545 // must copy state because it is modified
3546 input_state = copy(input_state);
3547
3548 if (xhandler->entry_code() != NULL) {
3549 process_operations(xhandler->entry_code(), input_state);
3550 }
3551 process_successor(xhandler->entry_block(), input_state);
3552 }
3553
3554 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3555 IntervalList* saved_state = state_for_block(block);
3556
3557 if (saved_state != NULL) {
3558 // this block was already processed before.
3559 // check if new input_state is consistent with saved_state
3560
3561 bool saved_state_correct = true;
3562 for (int i = 0; i < state_size(); i++) {
3563 if (input_state->at(i) != saved_state->at(i)) {
3564 // current input_state and previous saved_state assume a different
3565 // interval in this register -> assume that this register is invalid
3566 if (saved_state->at(i) != NULL) {
3567 // invalidate old calculation only if it assumed that
3568 // register was valid. when the register was already invalid,
3569 // then the old calculation was correct.
3570 saved_state_correct = false;
3571 saved_state->at_put(i, NULL);
3572
3573 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3574 }
3575 }
3576 }
3577
3578 if (saved_state_correct) {
3579 // already processed block with correct input_state
3580 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3581 } else {
3582 // must re-visit this block
3583 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3584 add_to_work_list(block);
3585 }
3586
3587 } else {
3588 // block was not processed before, so set initial input_state
3589 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3590
3591 set_state_for_block(block, copy(input_state));
3592 add_to_work_list(block);
3593 }
3594 }
3595
3596
3597 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3598 IntervalList* copy_state = new IntervalList(input_state->length());
3599 copy_state->appendAll(input_state);
3600 return copy_state;
3601 }
3602
3603 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3604 if (reg != LinearScan::any_reg && reg < state_size()) {
3605 if (interval != NULL) {
3606 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num()));
3607 } else if (input_state->at(reg) != NULL) {
3608 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg));
3609 }
3610
3611 input_state->at_put(reg, interval);
3612 }
3613 }
3614
3615 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3616 if (reg != LinearScan::any_reg && reg < state_size()) {
3617 if (input_state->at(reg) != interval) {
3618 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3619 return true;
3620 }
3621 }
3622 return false;
3623 }
3624
3625 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3626 // visit all instructions of the block
3627 LIR_OpVisitState visitor;
3628 bool has_error = false;
3629
3630 for (int i = 0; i < ops->length(); i++) {
3631 LIR_Op* op = ops->at(i);
3632 visitor.visit(op);
3633
3634 TRACE_LINEAR_SCAN(4, op->print_on(tty));
3635
3636 // check if input operands are correct
3637 int j;
3638 int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3639 for (j = 0; j < n; j++) {
3640 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3641 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3642 Interval* interval = interval_at(reg_num(opr));
3643 if (op->id() != -1) {
3644 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3645 }
3646
3647 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent());
3648 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3649
3650 // When an operand is marked with is_last_use, then the fpu stack allocator
3651 // removes the register from the fpu stack -> the register contains no value
3652 if (opr->is_last_use()) {
3653 state_put(input_state, interval->assigned_reg(), NULL);
3654 state_put(input_state, interval->assigned_regHi(), NULL);
3655 }
3656 }
3657 }
3658
3659 // invalidate all caller save registers at calls
3660 if (visitor.has_call()) {
3661 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3662 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3663 }
3664 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3665 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3666 }
3667
3668 #ifdef X86
3669 int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
3670 for (j = 0; j < num_caller_save_xmm_regs; j++) {
3671 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3672 }
3673 #endif
3674 }
3675
3676 // process xhandler before output and temp operands
3677 XHandlers* xhandlers = visitor.all_xhandler();
3678 n = xhandlers->length();
3679 for (int k = 0; k < n; k++) {
3680 process_xhandler(xhandlers->handler_at(k), input_state);
3681 }
3682
3683 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3684 n = visitor.opr_count(LIR_OpVisitState::tempMode);
3685 for (j = 0; j < n; j++) {
3686 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3687 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3688 Interval* interval = interval_at(reg_num(opr));
3689 if (op->id() != -1) {
3690 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3691 }
3692
3693 state_put(input_state, interval->assigned_reg(), interval->split_parent());
3694 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3695 }
3696 }
3697
3698 // set output operands
3699 n = visitor.opr_count(LIR_OpVisitState::outputMode);
3700 for (j = 0; j < n; j++) {
3701 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3702 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3703 Interval* interval = interval_at(reg_num(opr));
3704 if (op->id() != -1) {
3705 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3706 }
3707
3708 state_put(input_state, interval->assigned_reg(), interval->split_parent());
3709 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3710 }
3711 }
3712 }
3713 assert(has_error == false, "Error in register allocation");
3714 }
3715
3716 #endif // ASSERT
3717
3718
3719
3720 // **** Implementation of MoveResolver ******************************
3721
3722 MoveResolver::MoveResolver(LinearScan* allocator) :
3723 _allocator(allocator),
3724 _multiple_reads_allowed(false),
3725 _mapping_from(8),
3726 _mapping_from_opr(8),
3727 _mapping_to(8),
3728 _insert_list(NULL),
3729 _insert_idx(-1),
3730 _insertion_buffer()
3731 {
3732 for (int i = 0; i < LinearScan::nof_regs; i++) {
3733 _register_blocked[i] = 0;
3734 }
3735 DEBUG_ONLY(check_empty());
3736 }
3737
3738
3739 #ifdef ASSERT
3740
3741 void MoveResolver::check_empty() {
3742 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3743 for (int i = 0; i < LinearScan::nof_regs; i++) {
3744 assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3745 }
3746 assert(_multiple_reads_allowed == false, "must have default value");
3747 }
3748
3749 void MoveResolver::verify_before_resolve() {
3750 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3751 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3752 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3753
3754 int i, j;
3755 if (!_multiple_reads_allowed) {
3756 for (i = 0; i < _mapping_from.length(); i++) {
3757 for (j = i + 1; j < _mapping_from.length(); j++) {
3758 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3759 }
3760 }
3761 }
3762
3763 for (i = 0; i < _mapping_to.length(); i++) {
3764 for (j = i + 1; j < _mapping_to.length(); j++) {
3765 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3766 }
3767 }
3768
3769
3770 ResourceBitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3771 if (!_multiple_reads_allowed) {
3772 for (i = 0; i < _mapping_from.length(); i++) {
3773 Interval* it = _mapping_from.at(i);
3774 if (it != NULL) {
3775 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3776 used_regs.set_bit(it->assigned_reg());
3777
3778 if (it->assigned_regHi() != LinearScan::any_reg) {
3779 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3780 used_regs.set_bit(it->assigned_regHi());
3781 }
3782 }
3783 }
3784 }
3785
3786 used_regs.clear();
3787 for (i = 0; i < _mapping_to.length(); i++) {
3788 Interval* it = _mapping_to.at(i);
3789 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3790 used_regs.set_bit(it->assigned_reg());
3791
3792 if (it->assigned_regHi() != LinearScan::any_reg) {
3793 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3794 used_regs.set_bit(it->assigned_regHi());
3795 }
3796 }
3797
3798 used_regs.clear();
3799 for (i = 0; i < _mapping_from.length(); i++) {
3800 Interval* it = _mapping_from.at(i);
3801 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3802 used_regs.set_bit(it->assigned_reg());
3803 }
3804 }
3805 for (i = 0; i < _mapping_to.length(); i++) {
3806 Interval* it = _mapping_to.at(i);
3807 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3808 }
3809 }
3810
3811 #endif // ASSERT
3812
3813
3814 // mark assigned_reg and assigned_regHi of the interval as blocked
3815 void MoveResolver::block_registers(Interval* it) {
3816 int reg = it->assigned_reg();
3817 if (reg < LinearScan::nof_regs) {
3818 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3819 set_register_blocked(reg, 1);
3820 }
3821 reg = it->assigned_regHi();
3822 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3823 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3824 set_register_blocked(reg, 1);
3825 }
3826 }
3827
3828 // mark assigned_reg and assigned_regHi of the interval as unblocked
3829 void MoveResolver::unblock_registers(Interval* it) {
3830 int reg = it->assigned_reg();
3831 if (reg < LinearScan::nof_regs) {
3832 assert(register_blocked(reg) > 0, "register already marked as unused");
3833 set_register_blocked(reg, -1);
3834 }
3835 reg = it->assigned_regHi();
3836 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3837 assert(register_blocked(reg) > 0, "register already marked as unused");
3838 set_register_blocked(reg, -1);
3839 }
3840 }
3841
3842 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3843 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3844 int from_reg = -1;
3845 int from_regHi = -1;
3846 if (from != NULL) {
3847 from_reg = from->assigned_reg();
3848 from_regHi = from->assigned_regHi();
3849 }
3850
3851 int reg = to->assigned_reg();
3852 if (reg < LinearScan::nof_regs) {
3853 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3854 return false;
3855 }
3856 }
3857 reg = to->assigned_regHi();
3858 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3859 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3860 return false;
3861 }
3862 }
3863
3864 return true;
3865 }
3866
3867
3868 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3869 assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3870 _insertion_buffer.init(list);
3871 }
3872
3873 void MoveResolver::append_insertion_buffer() {
3874 if (_insertion_buffer.initialized()) {
3875 _insertion_buffer.lir_list()->append(&_insertion_buffer);
3876 }
3877 assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3878
3879 _insert_list = NULL;
3880 _insert_idx = -1;
3881 }
3882
3883 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3884 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3885 assert(from_interval->type() == to_interval->type(), "move between different types");
3886 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3887 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3888
3889 LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
3890 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3891
3892 if (!_multiple_reads_allowed) {
3893 // the last_use flag is an optimization for FPU stack allocation. When the same
3894 // input interval is used in more than one move, then it is too difficult to determine
3895 // if this move is really the last use.
3896 from_opr = from_opr->make_last_use();
3897 }
3898 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3899
3900 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3901 }
3902
3903 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3904 assert(from_opr->type() == to_interval->type(), "move between different types");
3905 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3906 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3907
3908 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3909 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3910
3911 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3912 }
3913
3914
3915 void MoveResolver::resolve_mappings() {
3916 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3917 DEBUG_ONLY(verify_before_resolve());
3918
3919 // Block all registers that are used as input operands of a move.
3920 // When a register is blocked, no move to this register is emitted.
3921 // This is necessary for detecting cycles in moves.
3922 int i;
3923 for (i = _mapping_from.length() - 1; i >= 0; i--) {
3924 Interval* from_interval = _mapping_from.at(i);
3925 if (from_interval != NULL) {
3926 block_registers(from_interval);
3927 }
3928 }
3929
3930 int spill_candidate = -1;
3931 while (_mapping_from.length() > 0) {
3932 bool processed_interval = false;
3933
3934 for (i = _mapping_from.length() - 1; i >= 0; i--) {
3935 Interval* from_interval = _mapping_from.at(i);
3936 Interval* to_interval = _mapping_to.at(i);
3937
3938 if (save_to_process_move(from_interval, to_interval)) {
3939 // this inverval can be processed because target is free
3940 if (from_interval != NULL) {
3941 insert_move(from_interval, to_interval);
3942 unblock_registers(from_interval);
3943 } else {
3944 insert_move(_mapping_from_opr.at(i), to_interval);
3945 }
3946 _mapping_from.remove_at(i);
3947 _mapping_from_opr.remove_at(i);
3948 _mapping_to.remove_at(i);
3949
3950 processed_interval = true;
3951 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
3952 // this interval cannot be processed now because target is not free
3953 // it starts in a register, so it is a possible candidate for spilling
3954 spill_candidate = i;
3955 }
3956 }
3957
3958 if (!processed_interval) {
3959 // no move could be processed because there is a cycle in the move list
3960 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
3961 assert(spill_candidate != -1, "no interval in register for spilling found");
3962
3963 // create a new spill interval and assign a stack slot to it
3964 Interval* from_interval = _mapping_from.at(spill_candidate);
3965 Interval* spill_interval = new Interval(-1);
3966 spill_interval->set_type(from_interval->type());
3967
3968 // add a dummy range because real position is difficult to calculate
3969 // Note: this range is a special case when the integrity of the allocation is checked
3970 spill_interval->add_range(1, 2);
3971
3972 // do not allocate a new spill slot for temporary interval, but
3973 // use spill slot assigned to from_interval. Otherwise moves from
3974 // one stack slot to another can happen (not allowed by LIR_Assembler
3975 int spill_slot = from_interval->canonical_spill_slot();
3976 if (spill_slot < 0) {
3977 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
3978 from_interval->set_canonical_spill_slot(spill_slot);
3979 }
3980 spill_interval->assign_reg(spill_slot);
3981 allocator()->append_interval(spill_interval);
3982
3983 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
3984
3985 // insert a move from register to stack and update the mapping
3986 insert_move(from_interval, spill_interval);
3987 _mapping_from.at_put(spill_candidate, spill_interval);
3988 unblock_registers(from_interval);
3989 }
3990 }
3991
3992 // reset to default value
3993 _multiple_reads_allowed = false;
3994
3995 // check that all intervals have been processed
3996 DEBUG_ONLY(check_empty());
3997 }
3998
3999
4000 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
4001 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4002 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
4003
4004 create_insertion_buffer(insert_list);
4005 _insert_list = insert_list;
4006 _insert_idx = insert_idx;
4007 }
4008
4009 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
4010 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4011
4012 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
4013 // insert position changed -> resolve current mappings
4014 resolve_mappings();
4015 }
4016
4017 if (insert_list != _insert_list) {
4018 // block changed -> append insertion_buffer because it is
4019 // bound to a specific block and create a new insertion_buffer
4020 append_insertion_buffer();
4021 create_insertion_buffer(insert_list);
4022 }
4023
4024 _insert_list = insert_list;
4025 _insert_idx = insert_idx;
4026 }
4027
4028 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
4029 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4030
4031 _mapping_from.append(from_interval);
4032 _mapping_from_opr.append(LIR_OprFact::illegalOpr);
4033 _mapping_to.append(to_interval);
4034 }
4035
4036
4037 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
4038 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4039 assert(from_opr->is_constant(), "only for constants");
4040
4041 _mapping_from.append(NULL);
4042 _mapping_from_opr.append(from_opr);
4043 _mapping_to.append(to_interval);
4044 }
4045
4046 void MoveResolver::resolve_and_append_moves() {
4047 if (has_mappings()) {
4048 resolve_mappings();
4049 }
4050 append_insertion_buffer();
4051 }
4052
4053
4054
4055 // **** Implementation of Range *************************************
4056
4057 Range::Range(int from, int to, Range* next) :
4058 _from(from),
4059 _to(to),
4060 _next(next)
4061 {
4062 }
4063
4064 // initialize sentinel
4065 Range* Range::_end = NULL;
4066 void Range::initialize(Arena* arena) {
4067 _end = new (arena) Range(max_jint, max_jint, NULL);
4068 }
4069
4070 int Range::intersects_at(Range* r2) const {
4071 const Range* r1 = this;
4072
4073 assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4074 assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4075
4076 do {
4077 if (r1->from() < r2->from()) {
4078 if (r1->to() <= r2->from()) {
4079 r1 = r1->next(); if (r1 == _end) return -1;
4080 } else {
4081 return r2->from();
4082 }
4083 } else if (r2->from() < r1->from()) {
4084 if (r2->to() <= r1->from()) {
4085 r2 = r2->next(); if (r2 == _end) return -1;
4086 } else {
4087 return r1->from();
4088 }
4089 } else { // r1->from() == r2->from()
4090 if (r1->from() == r1->to()) {
4091 r1 = r1->next(); if (r1 == _end) return -1;
4092 } else if (r2->from() == r2->to()) {
4093 r2 = r2->next(); if (r2 == _end) return -1;
4094 } else {
4095 return r1->from();
4096 }
4097 }
4098 } while (true);
4099 }
4100
4101 #ifndef PRODUCT
4102 void Range::print(outputStream* out) const {
4103 out->print("[%d, %d[ ", _from, _to);
4104 }
4105 #endif
4106
4107
4108
4109 // **** Implementation of Interval **********************************
4110
4111 // initialize sentinel
4112 Interval* Interval::_end = NULL;
4113 void Interval::initialize(Arena* arena) {
4114 Range::initialize(arena);
4115 _end = new (arena) Interval(-1);
4116 }
4117
4118 Interval::Interval(int reg_num) :
4119 _reg_num(reg_num),
4120 _type(T_ILLEGAL),
4121 _first(Range::end()),
4122 _use_pos_and_kinds(12),
4123 _current(Range::end()),
4124 _next(_end),
4125 _state(invalidState),
4126 _assigned_reg(LinearScan::any_reg),
4127 _assigned_regHi(LinearScan::any_reg),
4128 _cached_to(-1),
4129 _cached_opr(LIR_OprFact::illegalOpr),
4130 _cached_vm_reg(VMRegImpl::Bad()),
4131 _split_children(0),
4132 _canonical_spill_slot(-1),
4133 _insert_move_when_activated(false),
4134 _register_hint(NULL),
4135 _spill_state(noDefinitionFound),
4136 _spill_definition_pos(-1)
4137 {
4138 _split_parent = this;
4139 _current_split_child = this;
4140 }
4141
4142 int Interval::calc_to() {
4143 assert(_first != Range::end(), "interval has no range");
4144
4145 Range* r = _first;
4146 while (r->next() != Range::end()) {
4147 r = r->next();
4148 }
4149 return r->to();
4150 }
4151
4152
4153 #ifdef ASSERT
4154 // consistency check of split-children
4155 void Interval::check_split_children() {
4156 if (_split_children.length() > 0) {
4157 assert(is_split_parent(), "only split parents can have children");
4158
4159 for (int i = 0; i < _split_children.length(); i++) {
4160 Interval* i1 = _split_children.at(i);
4161
4162 assert(i1->split_parent() == this, "not a split child of this interval");
4163 assert(i1->type() == type(), "must be equal for all split children");
4164 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4165
4166 for (int j = i + 1; j < _split_children.length(); j++) {
4167 Interval* i2 = _split_children.at(j);
4168
4169 assert(i1->reg_num() != i2->reg_num(), "same register number");
4170
4171 if (i1->from() < i2->from()) {
4172 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4173 } else {
4174 assert(i2->from() < i1->from(), "intervals start at same op_id");
4175 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4176 }
4177 }
4178 }
4179 }
4180 }
4181 #endif // ASSERT
4182
4183 Interval* Interval::register_hint(bool search_split_child) const {
4184 if (!search_split_child) {
4185 return _register_hint;
4186 }
4187
4188 if (_register_hint != NULL) {
4189 assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4190
4191 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4192 return _register_hint;
4193
4194 } else if (_register_hint->_split_children.length() > 0) {
4195 // search the first split child that has a register assigned
4196 int len = _register_hint->_split_children.length();
4197 for (int i = 0; i < len; i++) {
4198 Interval* cur = _register_hint->_split_children.at(i);
4199
4200 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4201 return cur;
4202 }
4203 }
4204 }
4205 }
4206
4207 // no hint interval found that has a register assigned
4208 return NULL;
4209 }
4210
4211
4212 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4213 assert(is_split_parent(), "can only be called for split parents");
4214 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4215
4216 Interval* result;
4217 if (_split_children.length() == 0) {
4218 result = this;
4219 } else {
4220 result = NULL;
4221 int len = _split_children.length();
4222
4223 // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4224 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4225
4226 int i;
4227 for (i = 0; i < len; i++) {
4228 Interval* cur = _split_children.at(i);
4229 if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4230 if (i > 0) {
4231 // exchange current split child to start of list (faster access for next call)
4232 _split_children.at_put(i, _split_children.at(0));
4233 _split_children.at_put(0, cur);
4234 }
4235
4236 // interval found
4237 result = cur;
4238 break;
4239 }
4240 }
4241
4242 #ifdef ASSERT
4243 for (i = 0; i < len; i++) {
4244 Interval* tmp = _split_children.at(i);
4245 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4246 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4247 result->print();
4248 tmp->print();
4249 assert(false, "two valid result intervals found");
4250 }
4251 }
4252 #endif
4253 }
4254
4255 assert(result != NULL, "no matching interval found");
4256 assert(result->covers(op_id, mode), "op_id not covered by interval");
4257
4258 return result;
4259 }
4260
4261
4262 // returns the last split child that ends before the given op_id
4263 Interval* Interval::split_child_before_op_id(int op_id) {
4264 assert(op_id >= 0, "invalid op_id");
4265
4266 Interval* parent = split_parent();
4267 Interval* result = NULL;
4268
4269 int len = parent->_split_children.length();
4270 assert(len > 0, "no split children available");
4271
4272 for (int i = len - 1; i >= 0; i--) {
4273 Interval* cur = parent->_split_children.at(i);
4274 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4275 result = cur;
4276 }
4277 }
4278
4279 assert(result != NULL, "no split child found");
4280 return result;
4281 }
4282
4283
4284 // checks if op_id is covered by any split child
4285 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) {
4286 assert(is_split_parent(), "can only be called for split parents");
4287 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4288
4289 if (_split_children.length() == 0) {
4290 // simple case if interval was not split
4291 return covers(op_id, mode);
4292
4293 } else {
4294 // extended case: check all split children
4295 int len = _split_children.length();
4296 for (int i = 0; i < len; i++) {
4297 Interval* cur = _split_children.at(i);
4298 if (cur->covers(op_id, mode)) {
4299 return true;
4300 }
4301 }
4302 return false;
4303 }
4304 }
4305
4306
4307 // Note: use positions are sorted descending -> first use has highest index
4308 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4309 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4310
4311 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4312 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4313 return _use_pos_and_kinds.at(i);
4314 }
4315 }
4316 return max_jint;
4317 }
4318
4319 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4320 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4321
4322 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4323 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4324 return _use_pos_and_kinds.at(i);
4325 }
4326 }
4327 return max_jint;
4328 }
4329
4330 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4331 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4332
4333 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4334 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4335 return _use_pos_and_kinds.at(i);
4336 }
4337 }
4338 return max_jint;
4339 }
4340
4341 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4342 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4343
4344 int prev = 0;
4345 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4346 if (_use_pos_and_kinds.at(i) > from) {
4347 return prev;
4348 }
4349 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4350 prev = _use_pos_and_kinds.at(i);
4351 }
4352 }
4353 return prev;
4354 }
4355
4356 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4357 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4358
4359 // do not add use positions for precolored intervals because
4360 // they are never used
4361 if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4362 #ifdef ASSERT
4363 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4364 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4365 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4366 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4367 if (i > 0) {
4368 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4369 }
4370 }
4371 #endif
4372
4373 // Note: add_use is called in descending order, so list gets sorted
4374 // automatically by just appending new use positions
4375 int len = _use_pos_and_kinds.length();
4376 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4377 _use_pos_and_kinds.append(pos);
4378 _use_pos_and_kinds.append(use_kind);
4379 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4380 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4381 _use_pos_and_kinds.at_put(len - 1, use_kind);
4382 }
4383 }
4384 }
4385
4386 void Interval::add_range(int from, int to) {
4387 assert(from < to, "invalid range");
4388 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4389 assert(from <= first()->to(), "not inserting at begin of interval");
4390
4391 if (first()->from() <= to) {
4392 // join intersecting ranges
4393 first()->set_from(MIN2(from, first()->from()));
4394 first()->set_to (MAX2(to, first()->to()));
4395 } else {
4396 // insert new range
4397 _first = new Range(from, to, first());
4398 }
4399 }
4400
4401 Interval* Interval::new_split_child() {
4402 // allocate new interval
4403 Interval* result = new Interval(-1);
4404 result->set_type(type());
4405
4406 Interval* parent = split_parent();
4407 result->_split_parent = parent;
4408 result->set_register_hint(parent);
4409
4410 // insert new interval in children-list of parent
4411 if (parent->_split_children.length() == 0) {
4412 assert(is_split_parent(), "list must be initialized at first split");
4413
4414 parent->_split_children = IntervalList(4);
4415 parent->_split_children.append(this);
4416 }
4417 parent->_split_children.append(result);
4418
4419 return result;
4420 }
4421
4422 // split this interval at the specified position and return
4423 // the remainder as a new interval.
4424 //
4425 // when an interval is split, a bi-directional link is established between the original interval
4426 // (the split parent) and the intervals that are split off this interval (the split children)
4427 // When a split child is split again, the new created interval is also a direct child
4428 // of the original parent (there is no tree of split children stored, but a flat list)
4429 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4430 //
4431 // Note: The new interval has no valid reg_num
4432 Interval* Interval::split(int split_pos) {
4433 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4434
4435 // allocate new interval
4436 Interval* result = new_split_child();
4437
4438 // split the ranges
4439 Range* prev = NULL;
4440 Range* cur = _first;
4441 while (cur != Range::end() && cur->to() <= split_pos) {
4442 prev = cur;
4443 cur = cur->next();
4444 }
4445 assert(cur != Range::end(), "split interval after end of last range");
4446
4447 if (cur->from() < split_pos) {
4448 result->_first = new Range(split_pos, cur->to(), cur->next());
4449 cur->set_to(split_pos);
4450 cur->set_next(Range::end());
4451
4452 } else {
4453 assert(prev != NULL, "split before start of first range");
4454 result->_first = cur;
4455 prev->set_next(Range::end());
4456 }
4457 result->_current = result->_first;
4458 _cached_to = -1; // clear cached value
4459
4460 // split list of use positions
4461 int total_len = _use_pos_and_kinds.length();
4462 int start_idx = total_len - 2;
4463 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4464 start_idx -= 2;
4465 }
4466
4467 intStack new_use_pos_and_kinds(total_len - start_idx);
4468 int i;
4469 for (i = start_idx + 2; i < total_len; i++) {
4470 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4471 }
4472
4473 _use_pos_and_kinds.trunc_to(start_idx + 2);
4474 result->_use_pos_and_kinds = _use_pos_and_kinds;
4475 _use_pos_and_kinds = new_use_pos_and_kinds;
4476
4477 #ifdef ASSERT
4478 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4479 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4480 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4481
4482 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4483 assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4484 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4485 }
4486 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4487 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4488 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4489 }
4490 #endif
4491
4492 return result;
4493 }
4494
4495 // split this interval at the specified position and return
4496 // the head as a new interval (the original interval is the tail)
4497 //
4498 // Currently, only the first range can be split, and the new interval
4499 // must not have split positions
4500 Interval* Interval::split_from_start(int split_pos) {
4501 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4502 assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4503 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4504 assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4505
4506 // allocate new interval
4507 Interval* result = new_split_child();
4508
4509 // the new created interval has only one range (checked by assertion above),
4510 // so the splitting of the ranges is very simple
4511 result->add_range(_first->from(), split_pos);
4512
4513 if (split_pos == _first->to()) {
4514 assert(_first->next() != Range::end(), "must not be at end");
4515 _first = _first->next();
4516 } else {
4517 _first->set_from(split_pos);
4518 }
4519
4520 return result;
4521 }
4522
4523
4524 // returns true if the op_id is inside the interval
4525 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4526 Range* cur = _first;
4527
4528 while (cur != Range::end() && cur->to() < op_id) {
4529 cur = cur->next();
4530 }
4531 if (cur != Range::end()) {
4532 assert(cur->to() != cur->next()->from(), "ranges not separated");
4533
4534 if (mode == LIR_OpVisitState::outputMode) {
4535 return cur->from() <= op_id && op_id < cur->to();
4536 } else {
4537 return cur->from() <= op_id && op_id <= cur->to();
4538 }
4539 }
4540 return false;
4541 }
4542
4543 // returns true if the interval has any hole between hole_from and hole_to
4544 // (even if the hole has only the length 1)
4545 bool Interval::has_hole_between(int hole_from, int hole_to) {
4546 assert(hole_from < hole_to, "check");
4547 assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4548
4549 Range* cur = _first;
4550 while (cur != Range::end()) {
4551 assert(cur->to() < cur->next()->from(), "no space between ranges");
4552
4553 // hole-range starts before this range -> hole
4554 if (hole_from < cur->from()) {
4555 return true;
4556
4557 // hole-range completely inside this range -> no hole
4558 } else if (hole_to <= cur->to()) {
4559 return false;
4560
4561 // overlapping of hole-range with this range -> hole
4562 } else if (hole_from <= cur->to()) {
4563 return true;
4564 }
4565
4566 cur = cur->next();
4567 }
4568
4569 return false;
4570 }
4571
4572
4573 #ifndef PRODUCT
4574 void Interval::print(outputStream* out) const {
4575 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4576 const char* UseKind2Name[] = { "N", "L", "S", "M" };
4577
4578 const char* type_name;
4579 LIR_Opr opr = LIR_OprFact::illegal();
4580 if (reg_num() < LIR_OprDesc::vreg_base) {
4581 type_name = "fixed";
4582 // need a temporary operand for fixed intervals because type() cannot be called
4583 #ifdef X86
4584 int last_xmm_reg = pd_last_xmm_reg;
4585 #ifdef _LP64
4586 if (UseAVX < 3) {
4587 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
4588 }
4589 #endif
4590 #endif
4591 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4592 opr = LIR_OprFact::single_cpu(assigned_reg());
4593 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4594 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4595 #ifdef X86
4596 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= last_xmm_reg) {
4597 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4598 #endif
4599 } else {
4600 ShouldNotReachHere();
4601 }
4602 } else {
4603 type_name = type2name(type());
4604 if (assigned_reg() != -1 &&
4605 (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4606 opr = LinearScan::calc_operand_for_interval(this);
4607 }
4608 }
4609
4610 out->print("%d %s ", reg_num(), type_name);
4611 if (opr->is_valid()) {
4612 out->print("\"");
4613 opr->print(out);
4614 out->print("\" ");
4615 }
4616 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4617
4618 // print ranges
4619 Range* cur = _first;
4620 while (cur != Range::end()) {
4621 cur->print(out);
4622 cur = cur->next();
4623 assert(cur != NULL, "range list not closed with range sentinel");
4624 }
4625
4626 // print use positions
4627 int prev = 0;
4628 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4629 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4630 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4631 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4632
4633 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4634 prev = _use_pos_and_kinds.at(i);
4635 }
4636
4637 out->print(" \"%s\"", SpillState2Name[spill_state()]);
4638 out->cr();
4639 }
4640 #endif
4641
4642
4643
4644 // **** Implementation of IntervalWalker ****************************
4645
4646 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4647 : _compilation(allocator->compilation())
4648 , _allocator(allocator)
4649 {
4650 _unhandled_first[fixedKind] = unhandled_fixed_first;
4651 _unhandled_first[anyKind] = unhandled_any_first;
4652 _active_first[fixedKind] = Interval::end();
4653 _inactive_first[fixedKind] = Interval::end();
4654 _active_first[anyKind] = Interval::end();
4655 _inactive_first[anyKind] = Interval::end();
4656 _current_position = -1;
4657 _current = NULL;
4658 next_interval();
4659 }
4660
4661
4662 // append interval at top of list
4663 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) {
4664 interval->set_next(*list); *list = interval;
4665 }
4666
4667
4668 // append interval in order of current range from()
4669 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4670 Interval* prev = NULL;
4671 Interval* cur = *list;
4672 while (cur->current_from() < interval->current_from()) {
4673 prev = cur; cur = cur->next();
4674 }
4675 if (prev == NULL) {
4676 *list = interval;
4677 } else {
4678 prev->set_next(interval);
4679 }
4680 interval->set_next(cur);
4681 }
4682
4683 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4684 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4685
4686 Interval* prev = NULL;
4687 Interval* cur = *list;
4688 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4689 prev = cur; cur = cur->next();
4690 }
4691 if (prev == NULL) {
4692 *list = interval;
4693 } else {
4694 prev->set_next(interval);
4695 }
4696 interval->set_next(cur);
4697 }
4698
4699
4700 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4701 while (*list != Interval::end() && *list != i) {
4702 list = (*list)->next_addr();
4703 }
4704 if (*list != Interval::end()) {
4705 assert(*list == i, "check");
4706 *list = (*list)->next();
4707 return true;
4708 } else {
4709 return false;
4710 }
4711 }
4712
4713 void IntervalWalker::remove_from_list(Interval* i) {
4714 bool deleted;
4715
4716 if (i->state() == activeState) {
4717 deleted = remove_from_list(active_first_addr(anyKind), i);
4718 } else {
4719 assert(i->state() == inactiveState, "invalid state");
4720 deleted = remove_from_list(inactive_first_addr(anyKind), i);
4721 }
4722
4723 assert(deleted, "interval has not been found in list");
4724 }
4725
4726
4727 void IntervalWalker::walk_to(IntervalState state, int from) {
4728 assert (state == activeState || state == inactiveState, "wrong state");
4729 for_each_interval_kind(kind) {
4730 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4731 Interval* next = *prev;
4732 while (next->current_from() <= from) {
4733 Interval* cur = next;
4734 next = cur->next();
4735
4736 bool range_has_changed = false;
4737 while (cur->current_to() <= from) {
4738 cur->next_range();
4739 range_has_changed = true;
4740 }
4741
4742 // also handle move from inactive list to active list
4743 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4744
4745 if (range_has_changed) {
4746 // remove cur from list
4747 *prev = next;
4748 if (cur->current_at_end()) {
4749 // move to handled state (not maintained as a list)
4750 cur->set_state(handledState);
4751 interval_moved(cur, kind, state, handledState);
4752 } else if (cur->current_from() <= from){
4753 // sort into active list
4754 append_sorted(active_first_addr(kind), cur);
4755 cur->set_state(activeState);
4756 if (*prev == cur) {
4757 assert(state == activeState, "check");
4758 prev = cur->next_addr();
4759 }
4760 interval_moved(cur, kind, state, activeState);
4761 } else {
4762 // sort into inactive list
4763 append_sorted(inactive_first_addr(kind), cur);
4764 cur->set_state(inactiveState);
4765 if (*prev == cur) {
4766 assert(state == inactiveState, "check");
4767 prev = cur->next_addr();
4768 }
4769 interval_moved(cur, kind, state, inactiveState);
4770 }
4771 } else {
4772 prev = cur->next_addr();
4773 continue;
4774 }
4775 }
4776 }
4777 }
4778
4779
4780 void IntervalWalker::next_interval() {
4781 IntervalKind kind;
4782 Interval* any = _unhandled_first[anyKind];
4783 Interval* fixed = _unhandled_first[fixedKind];
4784
4785 if (any != Interval::end()) {
4786 // intervals may start at same position -> prefer fixed interval
4787 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4788
4789 assert (kind == fixedKind && fixed->from() <= any->from() ||
4790 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!");
4791 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4792
4793 } else if (fixed != Interval::end()) {
4794 kind = fixedKind;
4795 } else {
4796 _current = NULL; return;
4797 }
4798 _current_kind = kind;
4799 _current = _unhandled_first[kind];
4800 _unhandled_first[kind] = _current->next();
4801 _current->set_next(Interval::end());
4802 _current->rewind_range();
4803 }
4804
4805
4806 void IntervalWalker::walk_to(int lir_op_id) {
4807 assert(_current_position <= lir_op_id, "can not walk backwards");
4808 while (current() != NULL) {
4809 bool is_active = current()->from() <= lir_op_id;
4810 int id = is_active ? current()->from() : lir_op_id;
4811
4812 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4813
4814 // set _current_position prior to call of walk_to
4815 _current_position = id;
4816
4817 // call walk_to even if _current_position == id
4818 walk_to(activeState, id);
4819 walk_to(inactiveState, id);
4820
4821 if (is_active) {
4822 current()->set_state(activeState);
4823 if (activate_current()) {
4824 append_sorted(active_first_addr(current_kind()), current());
4825 interval_moved(current(), current_kind(), unhandledState, activeState);
4826 }
4827
4828 next_interval();
4829 } else {
4830 return;
4831 }
4832 }
4833 }
4834
4835 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4836 #ifndef PRODUCT
4837 if (TraceLinearScanLevel >= 4) {
4838 #define print_state(state) \
4839 switch(state) {\
4840 case unhandledState: tty->print("unhandled"); break;\
4841 case activeState: tty->print("active"); break;\
4842 case inactiveState: tty->print("inactive"); break;\
4843 case handledState: tty->print("handled"); break;\
4844 default: ShouldNotReachHere(); \
4845 }
4846
4847 print_state(from); tty->print(" to "); print_state(to);
4848 tty->fill_to(23);
4849 interval->print();
4850
4851 #undef print_state
4852 }
4853 #endif
4854 }
4855
4856
4857
4858 // **** Implementation of LinearScanWalker **************************
4859
4860 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4861 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4862 , _move_resolver(allocator)
4863 {
4864 for (int i = 0; i < LinearScan::nof_regs; i++) {
4865 _spill_intervals[i] = new IntervalList(2);
4866 }
4867 }
4868
4869
4870 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4871 for (int i = _first_reg; i <= _last_reg; i++) {
4872 _use_pos[i] = max_jint;
4873
4874 if (!only_process_use_pos) {
4875 _block_pos[i] = max_jint;
4876 _spill_intervals[i]->clear();
4877 }
4878 }
4879 }
4880
4881 inline void LinearScanWalker::exclude_from_use(int reg) {
4882 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4883 if (reg >= _first_reg && reg <= _last_reg) {
4884 _use_pos[reg] = 0;
4885 }
4886 }
4887 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4888 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4889
4890 exclude_from_use(i->assigned_reg());
4891 exclude_from_use(i->assigned_regHi());
4892 }
4893
4894 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4895 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4896
4897 if (reg >= _first_reg && reg <= _last_reg) {
4898 if (_use_pos[reg] > use_pos) {
4899 _use_pos[reg] = use_pos;
4900 }
4901 if (!only_process_use_pos) {
4902 _spill_intervals[reg]->append(i);
4903 }
4904 }
4905 }
4906 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4907 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4908 if (use_pos != -1) {
4909 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4910 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4911 }
4912 }
4913
4914 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4915 if (reg >= _first_reg && reg <= _last_reg) {
4916 if (_block_pos[reg] > block_pos) {
4917 _block_pos[reg] = block_pos;
4918 }
4919 if (_use_pos[reg] > block_pos) {
4920 _use_pos[reg] = block_pos;
4921 }
4922 }
4923 }
4924 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4925 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4926 if (block_pos != -1) {
4927 set_block_pos(i->assigned_reg(), i, block_pos);
4928 set_block_pos(i->assigned_regHi(), i, block_pos);
4929 }
4930 }
4931
4932
4933 void LinearScanWalker::free_exclude_active_fixed() {
4934 Interval* list = active_first(fixedKind);
4935 while (list != Interval::end()) {
4936 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4937 exclude_from_use(list);
4938 list = list->next();
4939 }
4940 }
4941
4942 void LinearScanWalker::free_exclude_active_any() {
4943 Interval* list = active_first(anyKind);
4944 while (list != Interval::end()) {
4945 exclude_from_use(list);
4946 list = list->next();
4947 }
4948 }
4949
4950 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
4951 Interval* list = inactive_first(fixedKind);
4952 while (list != Interval::end()) {
4953 if (cur->to() <= list->current_from()) {
4954 assert(list->current_intersects_at(cur) == -1, "must not intersect");
4955 set_use_pos(list, list->current_from(), true);
4956 } else {
4957 set_use_pos(list, list->current_intersects_at(cur), true);
4958 }
4959 list = list->next();
4960 }
4961 }
4962
4963 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
4964 Interval* list = inactive_first(anyKind);
4965 while (list != Interval::end()) {
4966 set_use_pos(list, list->current_intersects_at(cur), true);
4967 list = list->next();
4968 }
4969 }
4970
4971 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) {
4972 Interval* list = unhandled_first(kind);
4973 while (list != Interval::end()) {
4974 set_use_pos(list, list->intersects_at(cur), true);
4975 if (kind == fixedKind && cur->to() <= list->from()) {
4976 set_use_pos(list, list->from(), true);
4977 }
4978 list = list->next();
4979 }
4980 }
4981
4982 void LinearScanWalker::spill_exclude_active_fixed() {
4983 Interval* list = active_first(fixedKind);
4984 while (list != Interval::end()) {
4985 exclude_from_use(list);
4986 list = list->next();
4987 }
4988 }
4989
4990 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) {
4991 Interval* list = unhandled_first(fixedKind);
4992 while (list != Interval::end()) {
4993 set_block_pos(list, list->intersects_at(cur));
4994 list = list->next();
4995 }
4996 }
4997
4998 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
4999 Interval* list = inactive_first(fixedKind);
5000 while (list != Interval::end()) {
5001 if (cur->to() > list->current_from()) {
5002 set_block_pos(list, list->current_intersects_at(cur));
5003 } else {
5004 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
5005 }
5006
5007 list = list->next();
5008 }
5009 }
5010
5011 void LinearScanWalker::spill_collect_active_any() {
5012 Interval* list = active_first(anyKind);
5013 while (list != Interval::end()) {
5014 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5015 list = list->next();
5016 }
5017 }
5018
5019 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
5020 Interval* list = inactive_first(anyKind);
5021 while (list != Interval::end()) {
5022 if (list->current_intersects(cur)) {
5023 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5024 }
5025 list = list->next();
5026 }
5027 }
5028
5029
5030 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
5031 // output all moves here. When source and target are equal, the move is
5032 // optimized away later in assign_reg_nums
5033
5034 op_id = (op_id + 1) & ~1;
5035 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
5036 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
5037
5038 // calculate index of instruction inside instruction list of current block
5039 // the minimal index (for a block with no spill moves) can be calculated because the
5040 // numbering of instructions is known.
5041 // When the block already contains spill moves, the index must be increased until the
5042 // correct index is reached.
5043 LIR_OpList* list = op_block->lir()->instructions_list();
5044 int index = (op_id - list->at(0)->id()) / 2;
5045 assert(list->at(index)->id() <= op_id, "error in calculation");
5046
5047 while (list->at(index)->id() != op_id) {
5048 index++;
5049 assert(0 <= index && index < list->length(), "index out of bounds");
5050 }
5051 assert(1 <= index && index < list->length(), "index out of bounds");
5052 assert(list->at(index)->id() == op_id, "error in calculation");
5053
5054 // insert new instruction before instruction at position index
5055 _move_resolver.move_insert_position(op_block->lir(), index - 1);
5056 _move_resolver.add_mapping(src_it, dst_it);
5057 }
5058
5059
5060 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5061 int from_block_nr = min_block->linear_scan_number();
5062 int to_block_nr = max_block->linear_scan_number();
5063
5064 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5065 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5066 assert(from_block_nr < to_block_nr, "must cross block boundary");
5067
5068 // Try to split at end of max_block. If this would be after
5069 // max_split_pos, then use the begin of max_block
5070 int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5071 if (optimal_split_pos > max_split_pos) {
5072 optimal_split_pos = max_block->first_lir_instruction_id();
5073 }
5074
5075 int min_loop_depth = max_block->loop_depth();
5076 for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5077 BlockBegin* cur = block_at(i);
5078
5079 if (cur->loop_depth() < min_loop_depth) {
5080 // block with lower loop-depth found -> split at the end of this block
5081 min_loop_depth = cur->loop_depth();
5082 optimal_split_pos = cur->last_lir_instruction_id() + 2;
5083 }
5084 }
5085 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5086
5087 return optimal_split_pos;
5088 }
5089
5090
5091 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5092 int optimal_split_pos = -1;
5093 if (min_split_pos == max_split_pos) {
5094 // trivial case, no optimization of split position possible
5095 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible"));
5096 optimal_split_pos = min_split_pos;
5097
5098 } else {
5099 assert(min_split_pos < max_split_pos, "must be true then");
5100 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5101
5102 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5103 // beginning of a block, then min_split_pos is also a possible split position.
5104 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5105 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5106
5107 // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5108 // when an interval ends at the end of the last block of the method
5109 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5110 // block at this op_id)
5111 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5112
5113 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5114 if (min_block == max_block) {
5115 // split position cannot be moved to block boundary, so split as late as possible
5116 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5117 optimal_split_pos = max_split_pos;
5118
5119 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5120 // Do not move split position if the interval has a hole before max_split_pos.
5121 // Intervals resulting from Phi-Functions have more than one definition (marked
5122 // as mustHaveRegister) with a hole before each definition. When the register is needed
5123 // for the second definition, an earlier reloading is unnecessary.
5124 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos"));
5125 optimal_split_pos = max_split_pos;
5126
5127 } else {
5128 // seach optimal block boundary between min_split_pos and max_split_pos
5129 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5130
5131 if (do_loop_optimization) {
5132 // Loop optimization: if a loop-end marker is found between min- and max-position,
5133 // then split before this loop
5134 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5135 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos));
5136
5137 assert(loop_end_pos > min_split_pos, "invalid order");
5138 if (loop_end_pos < max_split_pos) {
5139 // loop-end marker found between min- and max-position
5140 // if it is not the end marker for the same loop as the min-position, then move
5141 // the max-position to this loop block.
5142 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5143 // of the interval (normally, only mustHaveRegister causes a reloading)
5144 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5145
5146 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5147 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5148
5149 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5150 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5151 optimal_split_pos = -1;
5152 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary"));
5153 } else {
5154 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful"));
5155 }
5156 }
5157 }
5158
5159 if (optimal_split_pos == -1) {
5160 // not calculated by loop optimization
5161 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5162 }
5163 }
5164 }
5165 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos));
5166
5167 return optimal_split_pos;
5168 }
5169
5170
5171 /*
5172 split an interval at the optimal position between min_split_pos and
5173 max_split_pos in two parts:
5174 1) the left part has already a location assigned
5175 2) the right part is sorted into to the unhandled-list
5176 */
5177 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5178 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print());
5179 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
5180
5181 assert(it->from() < min_split_pos, "cannot split at start of interval");
5182 assert(current_position() < min_split_pos, "cannot split before current position");
5183 assert(min_split_pos <= max_split_pos, "invalid order");
5184 assert(max_split_pos <= it->to(), "cannot split after end of interval");
5185
5186 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5187
5188 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5189 assert(optimal_split_pos <= it->to(), "cannot split after end of interval");
5190 assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5191
5192 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5193 // the split position would be just before the end of the interval
5194 // -> no split at all necessary
5195 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval"));
5196 return;
5197 }
5198
5199 // must calculate this before the actual split is performed and before split position is moved to odd op_id
5200 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5201
5202 if (!allocator()->is_block_begin(optimal_split_pos)) {
5203 // move position before actual instruction (odd op_id)
5204 optimal_split_pos = (optimal_split_pos - 1) | 1;
5205 }
5206
5207 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
5208 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5209 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5210
5211 Interval* split_part = it->split(optimal_split_pos);
5212
5213 allocator()->append_interval(split_part);
5214 allocator()->copy_register_flags(it, split_part);
5215 split_part->set_insert_move_when_activated(move_necessary);
5216 append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5217
5218 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5219 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
5220 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print());
5221 }
5222
5223 /*
5224 split an interval at the optimal position between min_split_pos and
5225 max_split_pos in two parts:
5226 1) the left part has already a location assigned
5227 2) the right part is always on the stack and therefore ignored in further processing
5228 */
5229 void LinearScanWalker::split_for_spilling(Interval* it) {
5230 // calculate allowed range of splitting position
5231 int max_split_pos = current_position();
5232 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5233
5234 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print());
5235 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
5236
5237 assert(it->state() == activeState, "why spill interval that is not active?");
5238 assert(it->from() <= min_split_pos, "cannot split before start of interval");
5239 assert(min_split_pos <= max_split_pos, "invalid order");
5240 assert(max_split_pos < it->to(), "cannot split at end end of interval");
5241 assert(current_position() < it->to(), "interval must not end before current position");
5242
5243 if (min_split_pos == it->from()) {
5244 // the whole interval is never used, so spill it entirely to memory
5245 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval"));
5246 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5247
5248 allocator()->assign_spill_slot(it);
5249 allocator()->change_spill_state(it, min_split_pos);
5250
5251 // Also kick parent intervals out of register to memory when they have no use
5252 // position. This avoids short interval in register surrounded by intervals in
5253 // memory -> avoid useless moves from memory to register and back
5254 Interval* parent = it;
5255 while (parent != NULL && parent->is_split_child()) {
5256 parent = parent->split_child_before_op_id(parent->from());
5257
5258 if (parent->assigned_reg() < LinearScan::nof_regs) {
5259 if (parent->first_usage(shouldHaveRegister) == max_jint) {
5260 // parent is never used, so kick it out of its assigned register
5261 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num()));
5262 allocator()->assign_spill_slot(parent);
5263 } else {
5264 // do not go further back because the register is actually used by the interval
5265 parent = NULL;
5266 }
5267 }
5268 }
5269
5270 } else {
5271 // search optimal split pos, split interval and spill only the right hand part
5272 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5273
5274 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5275 assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5276 assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5277
5278 if (!allocator()->is_block_begin(optimal_split_pos)) {
5279 // move position before actual instruction (odd op_id)
5280 optimal_split_pos = (optimal_split_pos - 1) | 1;
5281 }
5282
5283 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
5284 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5285 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5286
5287 Interval* spilled_part = it->split(optimal_split_pos);
5288 allocator()->append_interval(spilled_part);
5289 allocator()->assign_spill_slot(spilled_part);
5290 allocator()->change_spill_state(spilled_part, optimal_split_pos);
5291
5292 if (!allocator()->is_block_begin(optimal_split_pos)) {
5293 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5294 insert_move(optimal_split_pos, it, spilled_part);
5295 }
5296
5297 // the current_split_child is needed later when moves are inserted for reloading
5298 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5299 spilled_part->make_current_split_child();
5300
5301 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts"));
5302 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
5303 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print());
5304 }
5305 }
5306
5307
5308 void LinearScanWalker::split_stack_interval(Interval* it) {
5309 int min_split_pos = current_position() + 1;
5310 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5311
5312 split_before_usage(it, min_split_pos, max_split_pos);
5313 }
5314
5315 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5316 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5317 int max_split_pos = register_available_until;
5318
5319 split_before_usage(it, min_split_pos, max_split_pos);
5320 }
5321
5322 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5323 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5324
5325 int current_pos = current_position();
5326 if (it->state() == inactiveState) {
5327 // the interval is currently inactive, so no spill slot is needed for now.
5328 // when the split part is activated, the interval has a new chance to get a register,
5329 // so in the best case no stack slot is necessary
5330 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5331 split_before_usage(it, current_pos + 1, current_pos + 1);
5332
5333 } else {
5334 // search the position where the interval must have a register and split
5335 // at the optimal position before.
5336 // The new created part is added to the unhandled list and will get a register
5337 // when it is activated
5338 int min_split_pos = current_pos + 1;
5339 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5340
5341 split_before_usage(it, min_split_pos, max_split_pos);
5342
5343 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5344 split_for_spilling(it);
5345 }
5346 }
5347
5348
5349 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5350 int min_full_reg = any_reg;
5351 int max_partial_reg = any_reg;
5352
5353 for (int i = _first_reg; i <= _last_reg; i++) {
5354 if (i == ignore_reg) {
5355 // this register must be ignored
5356
5357 } else if (_use_pos[i] >= interval_to) {
5358 // this register is free for the full interval
5359 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5360 min_full_reg = i;
5361 }
5362 } else if (_use_pos[i] > reg_needed_until) {
5363 // this register is at least free until reg_needed_until
5364 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5365 max_partial_reg = i;
5366 }
5367 }
5368 }
5369
5370 if (min_full_reg != any_reg) {
5371 return min_full_reg;
5372 } else if (max_partial_reg != any_reg) {
5373 *need_split = true;
5374 return max_partial_reg;
5375 } else {
5376 return any_reg;
5377 }
5378 }
5379
5380 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5381 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5382
5383 int min_full_reg = any_reg;
5384 int max_partial_reg = any_reg;
5385
5386 for (int i = _first_reg; i < _last_reg; i+=2) {
5387 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5388 // this register is free for the full interval
5389 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5390 min_full_reg = i;
5391 }
5392 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5393 // this register is at least free until reg_needed_until
5394 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5395 max_partial_reg = i;
5396 }
5397 }
5398 }
5399
5400 if (min_full_reg != any_reg) {
5401 return min_full_reg;
5402 } else if (max_partial_reg != any_reg) {
5403 *need_split = true;
5404 return max_partial_reg;
5405 } else {
5406 return any_reg;
5407 }
5408 }
5409
5410
5411 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5412 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5413
5414 init_use_lists(true);
5415 free_exclude_active_fixed();
5416 free_exclude_active_any();
5417 free_collect_inactive_fixed(cur);
5418 free_collect_inactive_any(cur);
5419 // free_collect_unhandled(fixedKind, cur);
5420 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5421
5422 // _use_pos contains the start of the next interval that has this register assigned
5423 // (either as a fixed register or a normal allocated register in the past)
5424 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5425 TRACE_LINEAR_SCAN(4, tty->print_cr(" state of registers:"));
5426 TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i]));
5427
5428 int hint_reg, hint_regHi;
5429 Interval* register_hint = cur->register_hint();
5430 if (register_hint != NULL) {
5431 hint_reg = register_hint->assigned_reg();
5432 hint_regHi = register_hint->assigned_regHi();
5433
5434 if (allocator()->is_precolored_cpu_interval(register_hint)) {
5435 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5436 hint_regHi = hint_reg + 1; // connect e.g. eax-edx
5437 }
5438 TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
5439
5440 } else {
5441 hint_reg = any_reg;
5442 hint_regHi = any_reg;
5443 }
5444 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5445 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5446
5447 // the register must be free at least until this position
5448 int reg_needed_until = cur->from() + 1;
5449 int interval_to = cur->to();
5450
5451 bool need_split = false;
5452 int split_pos = -1;
5453 int reg = any_reg;
5454 int regHi = any_reg;
5455
5456 if (_adjacent_regs) {
5457 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5458 regHi = reg + 1;
5459 if (reg == any_reg) {
5460 return false;
5461 }
5462 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5463
5464 } else {
5465 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5466 if (reg == any_reg) {
5467 return false;
5468 }
5469 split_pos = _use_pos[reg];
5470
5471 if (_num_phys_regs == 2) {
5472 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5473
5474 if (_use_pos[reg] < interval_to && regHi == any_reg) {
5475 // do not split interval if only one register can be assigned until the split pos
5476 // (when one register is found for the whole interval, split&spill is only
5477 // performed for the hi register)
5478 return false;
5479
5480 } else if (regHi != any_reg) {
5481 split_pos = MIN2(split_pos, _use_pos[regHi]);
5482
5483 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5484 if (reg > regHi) {
5485 int temp = reg;
5486 reg = regHi;
5487 regHi = temp;
5488 }
5489 }
5490 }
5491 }
5492
5493 cur->assign_reg(reg, regHi);
5494 TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi));
5495
5496 assert(split_pos > 0, "invalid split_pos");
5497 if (need_split) {
5498 // register not available for full interval, so split it
5499 split_when_partial_register_available(cur, split_pos);
5500 }
5501
5502 // only return true if interval is completely assigned
5503 return _num_phys_regs == 1 || regHi != any_reg;
5504 }
5505
5506
5507 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5508 int max_reg = any_reg;
5509
5510 for (int i = _first_reg; i <= _last_reg; i++) {
5511 if (i == ignore_reg) {
5512 // this register must be ignored
5513
5514 } else if (_use_pos[i] > reg_needed_until) {
5515 if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
5516 max_reg = i;
5517 }
5518 }
5519 }
5520
5521 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5522 *need_split = true;
5523 }
5524
5525 return max_reg;
5526 }
5527
5528 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5529 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5530
5531 int max_reg = any_reg;
5532
5533 for (int i = _first_reg; i < _last_reg; i+=2) {
5534 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5535 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5536 max_reg = i;
5537 }
5538 }
5539 }
5540
5541 if (max_reg != any_reg &&
5542 (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to)) {
5543 *need_split = true;
5544 }
5545
5546 return max_reg;
5547 }
5548
5549 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5550 assert(reg != any_reg, "no register assigned");
5551
5552 for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5553 Interval* it = _spill_intervals[reg]->at(i);
5554 remove_from_list(it);
5555 split_and_spill_interval(it);
5556 }
5557
5558 if (regHi != any_reg) {
5559 IntervalList* processed = _spill_intervals[reg];
5560 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5561 Interval* it = _spill_intervals[regHi]->at(i);
5562 if (processed->find(it) == -1) {
5563 remove_from_list(it);
5564 split_and_spill_interval(it);
5565 }
5566 }
5567 }
5568 }
5569
5570
5571 // Split an Interval and spill it to memory so that cur can be placed in a register
5572 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5573 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5574
5575 // collect current usage of registers
5576 init_use_lists(false);
5577 spill_exclude_active_fixed();
5578 // spill_block_unhandled_fixed(cur);
5579 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5580 spill_block_inactive_fixed(cur);
5581 spill_collect_active_any();
5582 spill_collect_inactive_any(cur);
5583
5584 #ifndef PRODUCT
5585 if (TraceLinearScanLevel >= 4) {
5586 tty->print_cr(" state of registers:");
5587 for (int i = _first_reg; i <= _last_reg; i++) {
5588 tty->print(" reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]);
5589 for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5590 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5591 }
5592 tty->cr();
5593 }
5594 }
5595 #endif
5596
5597 // the register must be free at least until this position
5598 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5599 int interval_to = cur->to();
5600 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5601
5602 int split_pos = 0;
5603 int use_pos = 0;
5604 bool need_split = false;
5605 int reg, regHi;
5606
5607 if (_adjacent_regs) {
5608 reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split);
5609 regHi = reg + 1;
5610
5611 if (reg != any_reg) {
5612 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5613 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5614 }
5615 } else {
5616 reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split);
5617 regHi = any_reg;
5618
5619 if (reg != any_reg) {
5620 use_pos = _use_pos[reg];
5621 split_pos = _block_pos[reg];
5622
5623 if (_num_phys_regs == 2) {
5624 if (cur->assigned_reg() != any_reg) {
5625 regHi = reg;
5626 reg = cur->assigned_reg();
5627 } else {
5628 regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split);
5629 if (regHi != any_reg) {
5630 use_pos = MIN2(use_pos, _use_pos[regHi]);
5631 split_pos = MIN2(split_pos, _block_pos[regHi]);
5632 }
5633 }
5634
5635 if (regHi != any_reg && reg > regHi) {
5636 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5637 int temp = reg;
5638 reg = regHi;
5639 regHi = temp;
5640 }
5641 }
5642 }
5643 }
5644
5645 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5646 // the first use of cur is later than the spilling position -> spill cur
5647 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5648
5649 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5650 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5651 // assign a reasonable register and do a bailout in product mode to avoid errors
5652 allocator()->assign_spill_slot(cur);
5653 BAILOUT("LinearScan: no register found");
5654 }
5655
5656 split_and_spill_interval(cur);
5657 } else {
5658 TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi));
5659 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5660 assert(split_pos > 0, "invalid split_pos");
5661 assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5662
5663 cur->assign_reg(reg, regHi);
5664 if (need_split) {
5665 // register not available for full interval, so split it
5666 split_when_partial_register_available(cur, split_pos);
5667 }
5668
5669 // perform splitting and spilling for all affected intervalls
5670 split_and_spill_intersecting_intervals(reg, regHi);
5671 }
5672 }
5673
5674 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5675 #ifdef X86
5676 // fast calculation of intervals that can never get a register because the
5677 // the next instruction is a call that blocks all registers
5678 // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5679
5680 // check if this interval is the result of a split operation
5681 // (an interval got a register until this position)
5682 int pos = cur->from();
5683 if ((pos & 1) == 1) {
5684 // the current instruction is a call that blocks all registers
5685 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5686 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call"));
5687
5688 // safety check that there is really no register available
5689 assert(alloc_free_reg(cur) == false, "found a register for this interval");
5690 return true;
5691 }
5692
5693 }
5694 #endif
5695 return false;
5696 }
5697
5698 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5699 BasicType type = cur->type();
5700 _num_phys_regs = LinearScan::num_physical_regs(type);
5701 _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5702
5703 if (pd_init_regs_for_alloc(cur)) {
5704 // the appropriate register range was selected.
5705 } else if (type == T_FLOAT || type == T_DOUBLE) {
5706 _first_reg = pd_first_fpu_reg;
5707 _last_reg = pd_last_fpu_reg;
5708 } else {
5709 _first_reg = pd_first_cpu_reg;
5710 _last_reg = FrameMap::last_cpu_reg();
5711 }
5712
5713 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5714 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5715 }
5716
5717
5718 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5719 if (op->code() != lir_move) {
5720 return false;
5721 }
5722 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5723
5724 LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5725 LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5726 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5727 }
5728
5729 // optimization (especially for phi functions of nested loops):
5730 // assign same spill slot to non-intersecting intervals
5731 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5732 if (cur->is_split_child()) {
5733 // optimization is only suitable for split parents
5734 return;
5735 }
5736
5737 Interval* register_hint = cur->register_hint(false);
5738 if (register_hint == NULL) {
5739 // cur is not the target of a move, otherwise register_hint would be set
5740 return;
5741 }
5742 assert(register_hint->is_split_parent(), "register hint must be split parent");
5743
5744 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5745 // combining the stack slots for intervals where spill move optimization is applied
5746 // is not benefitial and would cause problems
5747 return;
5748 }
5749
5750 int begin_pos = cur->from();
5751 int end_pos = cur->to();
5752 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5753 // safety check that lir_op_with_id is allowed
5754 return;
5755 }
5756
5757 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5758 // cur and register_hint are not connected with two moves
5759 return;
5760 }
5761
5762 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5763 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5764 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5765 // register_hint must be split, otherwise the re-writing of use positions does not work
5766 return;
5767 }
5768
5769 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5770 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5771 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5772 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5773
5774 if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5775 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5776 return;
5777 }
5778 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5779
5780 // modify intervals such that cur gets the same stack slot as register_hint
5781 // delete use positions to prevent the intervals to get a register at beginning
5782 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5783 cur->remove_first_use_pos();
5784 end_hint->remove_first_use_pos();
5785 }
5786
5787
5788 // allocate a physical register or memory location to an interval
5789 bool LinearScanWalker::activate_current() {
5790 Interval* cur = current();
5791 bool result = true;
5792
5793 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print());
5794 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5795
5796 if (cur->assigned_reg() >= LinearScan::nof_regs) {
5797 // activating an interval that has a stack slot assigned -> split it at first use position
5798 // used for method parameters
5799 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use"));
5800
5801 split_stack_interval(cur);
5802 result = false;
5803
5804 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5805 // activating an interval that must start in a stack slot, but may get a register later
5806 // used for lir_roundfp: rounding is done by store to stack and reload later
5807 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use"));
5808 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5809
5810 allocator()->assign_spill_slot(cur);
5811 split_stack_interval(cur);
5812 result = false;
5813
5814 } else if (cur->assigned_reg() == any_reg) {
5815 // interval has not assigned register -> normal allocation
5816 // (this is the normal case for most intervals)
5817 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register"));
5818
5819 // assign same spill slot to non-intersecting intervals
5820 combine_spilled_intervals(cur);
5821
5822 init_vars_for_alloc(cur);
5823 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5824 // no empty register available.
5825 // split and spill another interval so that this interval gets a register
5826 alloc_locked_reg(cur);
5827 }
5828
5829 // spilled intervals need not be move to active-list
5830 if (cur->assigned_reg() >= LinearScan::nof_regs) {
5831 result = false;
5832 }
5833 }
5834
5835 // load spilled values that become active from stack slot to register
5836 if (cur->insert_move_when_activated()) {
5837 assert(cur->is_split_child(), "must be");
5838 assert(cur->current_split_child() != NULL, "must be");
5839 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5840 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5841
5842 insert_move(cur->from(), cur->current_split_child(), cur);
5843 }
5844 cur->make_current_split_child();
5845
5846 return result; // true = interval is moved to active list
5847 }
5848
5849
5850 // Implementation of EdgeMoveOptimizer
5851
5852 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5853 _edge_instructions(4),
5854 _edge_instructions_idx(4)
5855 {
5856 }
5857
5858 void EdgeMoveOptimizer::optimize(BlockList* code) {
5859 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5860
5861 // ignore the first block in the list (index 0 is not processed)
5862 for (int i = code->length() - 1; i >= 1; i--) {
5863 BlockBegin* block = code->at(i);
5864
5865 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5866 optimizer.optimize_moves_at_block_end(block);
5867 }
5868 if (block->number_of_sux() == 2) {
5869 optimizer.optimize_moves_at_block_begin(block);
5870 }
5871 }
5872 }
5873
5874
5875 // clear all internal data structures
5876 void EdgeMoveOptimizer::init_instructions() {
5877 _edge_instructions.clear();
5878 _edge_instructions_idx.clear();
5879 }
5880
5881 // append a lir-instruction-list and the index of the current operation in to the list
5882 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5883 _edge_instructions.append(instructions);
5884 _edge_instructions_idx.append(instructions_idx);
5885 }
5886
5887 // return the current operation of the given edge (predecessor or successor)
5888 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5889 LIR_OpList* instructions = _edge_instructions.at(edge);
5890 int idx = _edge_instructions_idx.at(edge);
5891
5892 if (idx < instructions->length()) {
5893 return instructions->at(idx);
5894 } else {
5895 return NULL;
5896 }
5897 }
5898
5899 // removes the current operation of the given edge (predecessor or successor)
5900 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5901 LIR_OpList* instructions = _edge_instructions.at(edge);
5902 int idx = _edge_instructions_idx.at(edge);
5903 instructions->remove_at(idx);
5904
5905 if (decrement_index) {
5906 _edge_instructions_idx.at_put(edge, idx - 1);
5907 }
5908 }
5909
5910
5911 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5912 if (op1 == NULL || op2 == NULL) {
5913 // at least one block is already empty -> no optimization possible
5914 return true;
5915 }
5916
5917 if (op1->code() == lir_move && op2->code() == lir_move) {
5918 assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5919 assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5920 LIR_Op1* move1 = (LIR_Op1*)op1;
5921 LIR_Op1* move2 = (LIR_Op1*)op2;
5922 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5923 // these moves are exactly equal and can be optimized
5924 return false;
5925 }
5926
5927 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
5928 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
5929 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
5930 LIR_Op1* fxch1 = (LIR_Op1*)op1;
5931 LIR_Op1* fxch2 = (LIR_Op1*)op2;
5932 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
5933 // equal FPU stack operations can be optimized
5934 return false;
5935 }
5936
5937 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
5938 // equal FPU stack operations can be optimized
5939 return false;
5940 }
5941
5942 // no optimization possible
5943 return true;
5944 }
5945
5946 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
5947 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
5948
5949 if (block->is_predecessor(block)) {
5950 // currently we can't handle this correctly.
5951 return;
5952 }
5953
5954 init_instructions();
5955 int num_preds = block->number_of_preds();
5956 assert(num_preds > 1, "do not call otherwise");
5957 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5958
5959 // setup a list with the lir-instructions of all predecessors
5960 int i;
5961 for (i = 0; i < num_preds; i++) {
5962 BlockBegin* pred = block->pred_at(i);
5963 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
5964
5965 if (pred->number_of_sux() != 1) {
5966 // this can happen with switch-statements where multiple edges are between
5967 // the same blocks.
5968 return;
5969 }
5970
5971 assert(pred->number_of_sux() == 1, "can handle only one successor");
5972 assert(pred->sux_at(0) == block, "invalid control flow");
5973 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5974 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5975 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5976
5977 if (pred_instructions->last()->info() != NULL) {
5978 // can not optimize instructions when debug info is needed
5979 return;
5980 }
5981
5982 // ignore the unconditional branch at the end of the block
5983 append_instructions(pred_instructions, pred_instructions->length() - 2);
5984 }
5985
5986
5987 // process lir-instructions while all predecessors end with the same instruction
5988 while (true) {
5989 LIR_Op* op = instruction_at(0);
5990 for (i = 1; i < num_preds; i++) {
5991 if (operations_different(op, instruction_at(i))) {
5992 // these instructions are different and cannot be optimized ->
5993 // no further optimization possible
5994 return;
5995 }
5996 }
5997
5998 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
5999
6000 // insert the instruction at the beginning of the current block
6001 block->lir()->insert_before(1, op);
6002
6003 // delete the instruction at the end of all predecessors
6004 for (i = 0; i < num_preds; i++) {
6005 remove_cur_instruction(i, true);
6006 }
6007 }
6008 }
6009
6010
6011 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
6012 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
6013
6014 init_instructions();
6015 int num_sux = block->number_of_sux();
6016
6017 LIR_OpList* cur_instructions = block->lir()->instructions_list();
6018
6019 assert(num_sux == 2, "method should not be called otherwise");
6020 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6021 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6022 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6023
6024 if (cur_instructions->last()->info() != NULL) {
6025 // can no optimize instructions when debug info is needed
6026 return;
6027 }
6028
6029 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
6030 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
6031 // not a valid case for optimization
6032 // currently, only blocks that end with two branches (conditional branch followed
6033 // by unconditional branch) are optimized
6034 return;
6035 }
6036
6037 // now it is guaranteed that the block ends with two branch instructions.
6038 // the instructions are inserted at the end of the block before these two branches
6039 int insert_idx = cur_instructions->length() - 2;
6040
6041 int i;
6042 #ifdef ASSERT
6043 for (i = insert_idx - 1; i >= 0; i--) {
6044 LIR_Op* op = cur_instructions->at(i);
6045 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
6046 assert(false, "block with two successors can have only two branch instructions");
6047 }
6048 }
6049 #endif
6050
6051 // setup a list with the lir-instructions of all successors
6052 for (i = 0; i < num_sux; i++) {
6053 BlockBegin* sux = block->sux_at(i);
6054 LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6055
6056 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6057
6058 if (sux->number_of_preds() != 1) {
6059 // this can happen with switch-statements where multiple edges are between
6060 // the same blocks.
6061 return;
6062 }
6063 assert(sux->pred_at(0) == block, "invalid control flow");
6064 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6065
6066 // ignore the label at the beginning of the block
6067 append_instructions(sux_instructions, 1);
6068 }
6069
6070 // process lir-instructions while all successors begin with the same instruction
6071 while (true) {
6072 LIR_Op* op = instruction_at(0);
6073 for (i = 1; i < num_sux; i++) {
6074 if (operations_different(op, instruction_at(i))) {
6075 // these instructions are different and cannot be optimized ->
6076 // no further optimization possible
6077 return;
6078 }
6079 }
6080
6081 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6082
6083 // insert instruction at end of current block
6084 block->lir()->insert_before(insert_idx, op);
6085 insert_idx++;
6086
6087 // delete the instructions at the beginning of all successors
6088 for (i = 0; i < num_sux; i++) {
6089 remove_cur_instruction(i, false);
6090 }
6091 }
6092 }
6093
6094
6095 // Implementation of ControlFlowOptimizer
6096
6097 ControlFlowOptimizer::ControlFlowOptimizer() :
6098 _original_preds(4)
6099 {
6100 }
6101
6102 void ControlFlowOptimizer::optimize(BlockList* code) {
6103 ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6104
6105 // push the OSR entry block to the end so that we're not jumping over it.
6106 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6107 if (osr_entry) {
6108 int index = osr_entry->linear_scan_number();
6109 assert(code->at(index) == osr_entry, "wrong index");
6110 code->remove_at(index);
6111 code->append(osr_entry);
6112 }
6113
6114 optimizer.reorder_short_loops(code);
6115 optimizer.delete_empty_blocks(code);
6116 optimizer.delete_unnecessary_jumps(code);
6117 optimizer.delete_jumps_to_return(code);
6118 }
6119
6120 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6121 int i = header_idx + 1;
6122 int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6123 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6124 i++;
6125 }
6126
6127 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6128 int end_idx = i - 1;
6129 BlockBegin* end_block = code->at(end_idx);
6130
6131 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6132 // short loop from header_idx to end_idx found -> reorder blocks such that
6133 // the header_block is the last block instead of the first block of the loop
6134 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6135 end_idx - header_idx + 1,
6136 header_block->block_id(), end_block->block_id()));
6137
6138 for (int j = header_idx; j < end_idx; j++) {
6139 code->at_put(j, code->at(j + 1));
6140 }
6141 code->at_put(end_idx, header_block);
6142
6143 // correct the flags so that any loop alignment occurs in the right place.
6144 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6145 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6146 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6147 }
6148 }
6149 }
6150
6151 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6152 for (int i = code->length() - 1; i >= 0; i--) {
6153 BlockBegin* block = code->at(i);
6154
6155 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6156 reorder_short_loop(code, block, i);
6157 }
6158 }
6159
6160 DEBUG_ONLY(verify(code));
6161 }
6162
6163 // only blocks with exactly one successor can be deleted. Such blocks
6164 // must always end with an unconditional branch to this successor
6165 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6166 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6167 return false;
6168 }
6169
6170 LIR_OpList* instructions = block->lir()->instructions_list();
6171
6172 assert(instructions->length() >= 2, "block must have label and branch");
6173 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6174 assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6175 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6176 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6177
6178 // block must have exactly one successor
6179
6180 if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6181 return true;
6182 }
6183 return false;
6184 }
6185
6186 // substitute branch targets in all branch-instructions of this blocks
6187 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6188 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6189
6190 LIR_OpList* instructions = block->lir()->instructions_list();
6191
6192 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6193 for (int i = instructions->length() - 1; i >= 1; i--) {
6194 LIR_Op* op = instructions->at(i);
6195
6196 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6197 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6198 LIR_OpBranch* branch = (LIR_OpBranch*)op;
6199
6200 if (branch->block() == target_from) {
6201 branch->change_block(target_to);
6202 }
6203 if (branch->ublock() == target_from) {
6204 branch->change_ublock(target_to);
6205 }
6206 }
6207 }
6208 }
6209
6210 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6211 int old_pos = 0;
6212 int new_pos = 0;
6213 int num_blocks = code->length();
6214
6215 while (old_pos < num_blocks) {
6216 BlockBegin* block = code->at(old_pos);
6217
6218 if (can_delete_block(block)) {
6219 BlockBegin* new_target = block->sux_at(0);
6220
6221 // propagate backward branch target flag for correct code alignment
6222 if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6223 new_target->set(BlockBegin::backward_branch_target_flag);
6224 }
6225
6226 // collect a list with all predecessors that contains each predecessor only once
6227 // the predecessors of cur are changed during the substitution, so a copy of the
6228 // predecessor list is necessary
6229 int j;
6230 _original_preds.clear();
6231 for (j = block->number_of_preds() - 1; j >= 0; j--) {
6232 BlockBegin* pred = block->pred_at(j);
6233 if (_original_preds.find(pred) == -1) {
6234 _original_preds.append(pred);
6235 }
6236 }
6237
6238 for (j = _original_preds.length() - 1; j >= 0; j--) {
6239 BlockBegin* pred = _original_preds.at(j);
6240 substitute_branch_target(pred, block, new_target);
6241 pred->substitute_sux(block, new_target);
6242 }
6243 } else {
6244 // adjust position of this block in the block list if blocks before
6245 // have been deleted
6246 if (new_pos != old_pos) {
6247 code->at_put(new_pos, code->at(old_pos));
6248 }
6249 new_pos++;
6250 }
6251 old_pos++;
6252 }
6253 code->trunc_to(new_pos);
6254
6255 DEBUG_ONLY(verify(code));
6256 }
6257
6258 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6259 // skip the last block because there a branch is always necessary
6260 for (int i = code->length() - 2; i >= 0; i--) {
6261 BlockBegin* block = code->at(i);
6262 LIR_OpList* instructions = block->lir()->instructions_list();
6263
6264 LIR_Op* last_op = instructions->last();
6265 if (last_op->code() == lir_branch) {
6266 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6267 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6268
6269 assert(last_branch->block() != NULL, "last branch must always have a block as target");
6270 assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6271
6272 if (last_branch->info() == NULL) {
6273 if (last_branch->block() == code->at(i + 1)) {
6274
6275 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6276
6277 // delete last branch instruction
6278 instructions->trunc_to(instructions->length() - 1);
6279
6280 } else {
6281 LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6282 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6283 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6284 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6285
6286 if (prev_branch->stub() == NULL) {
6287
6288 LIR_Op2* prev_cmp = NULL;
6289 // There might be a cmove inserted for profiling which depends on the same
6290 // compare. If we change the condition of the respective compare, we have
6291 // to take care of this cmove as well.
6292 LIR_Op2* prev_cmove = NULL;
6293
6294 for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6295 prev_op = instructions->at(j);
6296 // check for the cmove
6297 if (prev_op->code() == lir_cmove) {
6298 assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2");
6299 prev_cmove = (LIR_Op2*)prev_op;
6300 assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
6301 }
6302 if (prev_op->code() == lir_cmp) {
6303 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6304 prev_cmp = (LIR_Op2*)prev_op;
6305 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6306 }
6307 }
6308 assert(prev_cmp != NULL, "should have found comp instruction for branch");
6309 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6310
6311 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6312
6313 // eliminate a conditional branch to the immediate successor
6314 prev_branch->change_block(last_branch->block());
6315 prev_branch->negate_cond();
6316 prev_cmp->set_condition(prev_branch->cond());
6317 instructions->trunc_to(instructions->length() - 1);
6318 // if we do change the condition, we have to change the cmove as well
6319 if (prev_cmove != NULL) {
6320 prev_cmove->set_condition(prev_branch->cond());
6321 LIR_Opr t = prev_cmove->in_opr1();
6322 prev_cmove->set_in_opr1(prev_cmove->in_opr2());
6323 prev_cmove->set_in_opr2(t);
6324 }
6325 }
6326 }
6327 }
6328 }
6329 }
6330 }
6331 }
6332
6333 DEBUG_ONLY(verify(code));
6334 }
6335
6336 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6337 #ifdef ASSERT
6338 ResourceBitMap return_converted(BlockBegin::number_of_blocks());
6339 #endif
6340
6341 for (int i = code->length() - 1; i >= 0; i--) {
6342 BlockBegin* block = code->at(i);
6343 LIR_OpList* cur_instructions = block->lir()->instructions_list();
6344 LIR_Op* cur_last_op = cur_instructions->last();
6345
6346 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6347 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6348 // the block contains only a label and a return
6349 // if a predecessor ends with an unconditional jump to this block, then the jump
6350 // can be replaced with a return instruction
6351 //
6352 // Note: the original block with only a return statement cannot be deleted completely
6353 // because the predecessors might have other (conditional) jumps to this block
6354 // -> this may lead to unnecesary return instructions in the final code
6355
6356 assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6357 assert(block->number_of_sux() == 0 ||
6358 (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6359 "blocks that end with return must not have successors");
6360
6361 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6362 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6363
6364 for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6365 BlockBegin* pred = block->pred_at(j);
6366 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6367 LIR_Op* pred_last_op = pred_instructions->last();
6368
6369 if (pred_last_op->code() == lir_branch) {
6370 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6371 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6372
6373 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6374 // replace the jump to a return with a direct return
6375 // Note: currently the edge between the blocks is not deleted
6376 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
6377 #ifdef ASSERT
6378 return_converted.set_bit(pred->block_id());
6379 #endif
6380 }
6381 }
6382 }
6383 }
6384 }
6385 }
6386
6387
6388 #ifdef ASSERT
6389 void ControlFlowOptimizer::verify(BlockList* code) {
6390 for (int i = 0; i < code->length(); i++) {
6391 BlockBegin* block = code->at(i);
6392 LIR_OpList* instructions = block->lir()->instructions_list();
6393
6394 int j;
6395 for (j = 0; j < instructions->length(); j++) {
6396 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6397
6398 if (op_branch != NULL) {
6399 assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid");
6400 assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid");
6401 }
6402 }
6403
6404 for (j = 0; j < block->number_of_sux() - 1; j++) {
6405 BlockBegin* sux = block->sux_at(j);
6406 assert(code->find(sux) != -1, "successor not valid");
6407 }
6408
6409 for (j = 0; j < block->number_of_preds() - 1; j++) {
6410 BlockBegin* pred = block->pred_at(j);
6411 assert(code->find(pred) != -1, "successor not valid");
6412 }
6413 }
6414 }
6415 #endif
6416
6417
6418 #ifndef PRODUCT
6419
6420 // Implementation of LinearStatistic
6421
6422 const char* LinearScanStatistic::counter_name(int counter_idx) {
6423 switch (counter_idx) {
6424 case counter_method: return "compiled methods";
6425 case counter_fpu_method: return "methods using fpu";
6426 case counter_loop_method: return "methods with loops";
6427 case counter_exception_method:return "methods with xhandler";
6428
6429 case counter_loop: return "loops";
6430 case counter_block: return "blocks";
6431 case counter_loop_block: return "blocks inside loop";
6432 case counter_exception_block: return "exception handler entries";
6433 case counter_interval: return "intervals";
6434 case counter_fixed_interval: return "fixed intervals";
6435 case counter_range: return "ranges";
6436 case counter_fixed_range: return "fixed ranges";
6437 case counter_use_pos: return "use positions";
6438 case counter_fixed_use_pos: return "fixed use positions";
6439 case counter_spill_slots: return "spill slots";
6440
6441 // counter for classes of lir instructions
6442 case counter_instruction: return "total instructions";
6443 case counter_label: return "labels";
6444 case counter_entry: return "method entries";
6445 case counter_return: return "method returns";
6446 case counter_call: return "method calls";
6447 case counter_move: return "moves";
6448 case counter_cmp: return "compare";
6449 case counter_cond_branch: return "conditional branches";
6450 case counter_uncond_branch: return "unconditional branches";
6451 case counter_stub_branch: return "branches to stub";
6452 case counter_alu: return "artithmetic + logic";
6453 case counter_alloc: return "allocations";
6454 case counter_sync: return "synchronisation";
6455 case counter_throw: return "throw";
6456 case counter_unwind: return "unwind";
6457 case counter_typecheck: return "type+null-checks";
6458 case counter_fpu_stack: return "fpu-stack";
6459 case counter_misc_inst: return "other instructions";
6460 case counter_other_inst: return "misc. instructions";
6461
6462 // counter for different types of moves
6463 case counter_move_total: return "total moves";
6464 case counter_move_reg_reg: return "register->register";
6465 case counter_move_reg_stack: return "register->stack";
6466 case counter_move_stack_reg: return "stack->register";
6467 case counter_move_stack_stack:return "stack->stack";
6468 case counter_move_reg_mem: return "register->memory";
6469 case counter_move_mem_reg: return "memory->register";
6470 case counter_move_const_any: return "constant->any";
6471
6472 case blank_line_1: return "";
6473 case blank_line_2: return "";
6474
6475 default: ShouldNotReachHere(); return "";
6476 }
6477 }
6478
6479 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6480 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6481 return counter_method;
6482 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6483 return counter_block;
6484 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6485 return counter_instruction;
6486 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6487 return counter_move_total;
6488 }
6489 return invalid_counter;
6490 }
6491
6492 LinearScanStatistic::LinearScanStatistic() {
6493 for (int i = 0; i < number_of_counters; i++) {
6494 _counters_sum[i] = 0;
6495 _counters_max[i] = -1;
6496 }
6497
6498 }
6499
6500 // add the method-local numbers to the total sum
6501 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6502 for (int i = 0; i < number_of_counters; i++) {
6503 _counters_sum[i] += method_statistic._counters_sum[i];
6504 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6505 }
6506 }
6507
6508 void LinearScanStatistic::print(const char* title) {
6509 if (CountLinearScan || TraceLinearScanLevel > 0) {
6510 tty->cr();
6511 tty->print_cr("***** LinearScan statistic - %s *****", title);
6512
6513 for (int i = 0; i < number_of_counters; i++) {
6514 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6515 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6516
6517 LinearScanStatistic::Counter cntr = base_counter(i);
6518 if (cntr != invalid_counter) {
6519 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[cntr]);
6520 } else {
6521 tty->print(" ");
6522 }
6523
6524 if (_counters_max[i] >= 0) {
6525 tty->print("%8d", _counters_max[i]);
6526 }
6527 }
6528 tty->cr();
6529 }
6530 }
6531 }
6532
6533 void LinearScanStatistic::collect(LinearScan* allocator) {
6534 inc_counter(counter_method);
6535 if (allocator->has_fpu_registers()) {
6536 inc_counter(counter_fpu_method);
6537 }
6538 if (allocator->num_loops() > 0) {
6539 inc_counter(counter_loop_method);
6540 }
6541 inc_counter(counter_loop, allocator->num_loops());
6542 inc_counter(counter_spill_slots, allocator->max_spills());
6543
6544 int i;
6545 for (i = 0; i < allocator->interval_count(); i++) {
6546 Interval* cur = allocator->interval_at(i);
6547
6548 if (cur != NULL) {
6549 inc_counter(counter_interval);
6550 inc_counter(counter_use_pos, cur->num_use_positions());
6551 if (LinearScan::is_precolored_interval(cur)) {
6552 inc_counter(counter_fixed_interval);
6553 inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6554 }
6555
6556 Range* range = cur->first();
6557 while (range != Range::end()) {
6558 inc_counter(counter_range);
6559 if (LinearScan::is_precolored_interval(cur)) {
6560 inc_counter(counter_fixed_range);
6561 }
6562 range = range->next();
6563 }
6564 }
6565 }
6566
6567 bool has_xhandlers = false;
6568 // Note: only count blocks that are in code-emit order
6569 for (i = 0; i < allocator->ir()->code()->length(); i++) {
6570 BlockBegin* cur = allocator->ir()->code()->at(i);
6571
6572 inc_counter(counter_block);
6573 if (cur->loop_depth() > 0) {
6574 inc_counter(counter_loop_block);
6575 }
6576 if (cur->is_set(BlockBegin::exception_entry_flag)) {
6577 inc_counter(counter_exception_block);
6578 has_xhandlers = true;
6579 }
6580
6581 LIR_OpList* instructions = cur->lir()->instructions_list();
6582 for (int j = 0; j < instructions->length(); j++) {
6583 LIR_Op* op = instructions->at(j);
6584
6585 inc_counter(counter_instruction);
6586
6587 switch (op->code()) {
6588 case lir_label: inc_counter(counter_label); break;
6589 case lir_std_entry:
6590 case lir_osr_entry: inc_counter(counter_entry); break;
6591 case lir_return: inc_counter(counter_return); break;
6592
6593 case lir_rtcall:
6594 case lir_static_call:
6595 case lir_optvirtual_call:
6596 case lir_virtual_call: inc_counter(counter_call); break;
6597
6598 case lir_move: {
6599 inc_counter(counter_move);
6600 inc_counter(counter_move_total);
6601
6602 LIR_Opr in = op->as_Op1()->in_opr();
6603 LIR_Opr res = op->as_Op1()->result_opr();
6604 if (in->is_register()) {
6605 if (res->is_register()) {
6606 inc_counter(counter_move_reg_reg);
6607 } else if (res->is_stack()) {
6608 inc_counter(counter_move_reg_stack);
6609 } else if (res->is_address()) {
6610 inc_counter(counter_move_reg_mem);
6611 } else {
6612 ShouldNotReachHere();
6613 }
6614 } else if (in->is_stack()) {
6615 if (res->is_register()) {
6616 inc_counter(counter_move_stack_reg);
6617 } else {
6618 inc_counter(counter_move_stack_stack);
6619 }
6620 } else if (in->is_address()) {
6621 assert(res->is_register(), "must be");
6622 inc_counter(counter_move_mem_reg);
6623 } else if (in->is_constant()) {
6624 inc_counter(counter_move_const_any);
6625 } else {
6626 ShouldNotReachHere();
6627 }
6628 break;
6629 }
6630
6631 case lir_cmp: inc_counter(counter_cmp); break;
6632
6633 case lir_branch:
6634 case lir_cond_float_branch: {
6635 LIR_OpBranch* branch = op->as_OpBranch();
6636 if (branch->block() == NULL) {
6637 inc_counter(counter_stub_branch);
6638 } else if (branch->cond() == lir_cond_always) {
6639 inc_counter(counter_uncond_branch);
6640 } else {
6641 inc_counter(counter_cond_branch);
6642 }
6643 break;
6644 }
6645
6646 case lir_neg:
6647 case lir_add:
6648 case lir_sub:
6649 case lir_mul:
6650 case lir_mul_strictfp:
6651 case lir_div:
6652 case lir_div_strictfp:
6653 case lir_rem:
6654 case lir_sqrt:
6655 case lir_abs:
6656 case lir_log10:
6657 case lir_logic_and:
6658 case lir_logic_or:
6659 case lir_logic_xor:
6660 case lir_shl:
6661 case lir_shr:
6662 case lir_ushr: inc_counter(counter_alu); break;
6663
6664 case lir_alloc_object:
6665 case lir_alloc_array: inc_counter(counter_alloc); break;
6666
6667 case lir_monaddr:
6668 case lir_lock:
6669 case lir_unlock: inc_counter(counter_sync); break;
6670
6671 case lir_throw: inc_counter(counter_throw); break;
6672
6673 case lir_unwind: inc_counter(counter_unwind); break;
6674
6675 case lir_null_check:
6676 case lir_leal:
6677 case lir_instanceof:
6678 case lir_checkcast:
6679 case lir_store_check: inc_counter(counter_typecheck); break;
6680
6681 case lir_fpop_raw:
6682 case lir_fxch:
6683 case lir_fld: inc_counter(counter_fpu_stack); break;
6684
6685 case lir_nop:
6686 case lir_push:
6687 case lir_pop:
6688 case lir_convert:
6689 case lir_roundfp:
6690 case lir_cmove: inc_counter(counter_misc_inst); break;
6691
6692 default: inc_counter(counter_other_inst); break;
6693 }
6694 }
6695 }
6696
6697 if (has_xhandlers) {
6698 inc_counter(counter_exception_method);
6699 }
6700 }
6701
6702 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6703 if (CountLinearScan || TraceLinearScanLevel > 0) {
6704
6705 LinearScanStatistic local_statistic = LinearScanStatistic();
6706
6707 local_statistic.collect(allocator);
6708 global_statistic.sum_up(local_statistic);
6709
6710 if (TraceLinearScanLevel > 2) {
6711 local_statistic.print("current local statistic");
6712 }
6713 }
6714 }
6715
6716
6717 // Implementation of LinearTimers
6718
6719 LinearScanTimers::LinearScanTimers() {
6720 for (int i = 0; i < number_of_timers; i++) {
6721 timer(i)->reset();
6722 }
6723 }
6724
6725 const char* LinearScanTimers::timer_name(int idx) {
6726 switch (idx) {
6727 case timer_do_nothing: return "Nothing (Time Check)";
6728 case timer_number_instructions: return "Number Instructions";
6729 case timer_compute_local_live_sets: return "Local Live Sets";
6730 case timer_compute_global_live_sets: return "Global Live Sets";
6731 case timer_build_intervals: return "Build Intervals";
6732 case timer_sort_intervals_before: return "Sort Intervals Before";
6733 case timer_allocate_registers: return "Allocate Registers";
6734 case timer_resolve_data_flow: return "Resolve Data Flow";
6735 case timer_sort_intervals_after: return "Sort Intervals After";
6736 case timer_eliminate_spill_moves: return "Spill optimization";
6737 case timer_assign_reg_num: return "Assign Reg Num";
6738 case timer_allocate_fpu_stack: return "Allocate FPU Stack";
6739 case timer_optimize_lir: return "Optimize LIR";
6740 default: ShouldNotReachHere(); return "";
6741 }
6742 }
6743
6744 void LinearScanTimers::begin_method() {
6745 if (TimeEachLinearScan) {
6746 // reset all timers to measure only current method
6747 for (int i = 0; i < number_of_timers; i++) {
6748 timer(i)->reset();
6749 }
6750 }
6751 }
6752
6753 void LinearScanTimers::end_method(LinearScan* allocator) {
6754 if (TimeEachLinearScan) {
6755
6756 double c = timer(timer_do_nothing)->seconds();
6757 double total = 0;
6758 for (int i = 1; i < number_of_timers; i++) {
6759 total += timer(i)->seconds() - c;
6760 }
6761
6762 if (total >= 0.0005) {
6763 // print all information in one line for automatic processing
6764 tty->print("@"); allocator->compilation()->method()->print_name();
6765
6766 tty->print("@ %d ", allocator->compilation()->method()->code_size());
6767 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6768 tty->print("@ %d ", allocator->block_count());
6769 tty->print("@ %d ", allocator->num_virtual_regs());
6770 tty->print("@ %d ", allocator->interval_count());
6771 tty->print("@ %d ", allocator->_num_calls);
6772 tty->print("@ %d ", allocator->num_loops());
6773
6774 tty->print("@ %6.6f ", total);
6775 for (int i = 1; i < number_of_timers; i++) {
6776 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6777 }
6778 tty->cr();
6779 }
6780 }
6781 }
6782
6783 void LinearScanTimers::print(double total_time) {
6784 if (TimeLinearScan) {
6785 // correction value: sum of dummy-timer that only measures the time that
6786 // is necesary to start and stop itself
6787 double c = timer(timer_do_nothing)->seconds();
6788
6789 for (int i = 0; i < number_of_timers; i++) {
6790 double t = timer(i)->seconds();
6791 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6792 }
6793 }
6794 }
6795
6796 #endif // #ifndef PRODUCT