1071 }
1072
1073 // The input operand is not forced to a register (moves from stack to register are allowed),
1074 // but it is faster if the input operand is in a register
1075 return shouldHaveRegister;
1076 }
1077 }
1078
1079
1080 #if defined(X86) || defined(S390)
1081 if (op->code() == lir_cmove) {
1082 // conditional moves can handle stack operands
1083 assert(op->result_opr()->is_register(), "result must always be in a register");
1084 return shouldHaveRegister;
1085 }
1086
1087 // optimizations for second input operand of arithmehtic operations on Intel
1088 // this operand is allowed to be on the stack in some cases
1089 BasicType opr_type = opr->type_register();
1090 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1091 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 S390_ONLY(|| true)) {
1092 // SSE float instruction (T_DOUBLE only supported with SSE2)
1093 switch (op->code()) {
1094 case lir_cmp:
1095 case lir_add:
1096 case lir_sub:
1097 case lir_mul:
1098 case lir_div:
1099 {
1100 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1101 LIR_Op2* op2 = (LIR_Op2*)op;
1102 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1103 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1104 return shouldHaveRegister;
1105 }
1106 }
1107 default:
1108 break;
1109 }
1110 } else {
1111 // FPU stack float instruction
1112 switch (op->code()) {
1113 case lir_add:
1114 case lir_sub:
1115 case lir_mul:
1116 case lir_div:
1117 {
1118 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1119 LIR_Op2* op2 = (LIR_Op2*)op;
1120 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1121 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1122 return shouldHaveRegister;
1123 }
1124 }
1125 default:
1126 break;
1127 }
1128 }
1129 // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1130 // Since 64bit logical operations do not current support operands on stack, we have to make sure
1131 // T_OBJECT doesn't get spilled along with T_LONG.
1132 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1133 // integer instruction (note: long operands must always be in register)
1134 switch (op->code()) {
1135 case lir_cmp:
1136 case lir_add:
1137 case lir_sub:
1138 case lir_logic_and:
1139 case lir_logic_or:
1140 case lir_logic_xor:
1141 {
1142 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1143 LIR_Op2* op2 = (LIR_Op2*)op;
1144 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1145 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1146 return shouldHaveRegister;
1147 }
1148 }
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1071 }
1072
1073 // The input operand is not forced to a register (moves from stack to register are allowed),
1074 // but it is faster if the input operand is in a register
1075 return shouldHaveRegister;
1076 }
1077 }
1078
1079
1080 #if defined(X86) || defined(S390)
1081 if (op->code() == lir_cmove) {
1082 // conditional moves can handle stack operands
1083 assert(op->result_opr()->is_register(), "result must always be in a register");
1084 return shouldHaveRegister;
1085 }
1086
1087 // optimizations for second input operand of arithmehtic operations on Intel
1088 // this operand is allowed to be on the stack in some cases
1089 BasicType opr_type = opr->type_register();
1090 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1091 #ifdef X86
1092 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) {
1093 #endif
1094 // SSE float instruction (T_DOUBLE only supported with SSE2)
1095 switch (op->code()) {
1096 case lir_cmp:
1097 case lir_add:
1098 case lir_sub:
1099 case lir_mul:
1100 case lir_div:
1101 {
1102 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1103 LIR_Op2* op2 = (LIR_Op2*)op;
1104 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1105 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1106 return shouldHaveRegister;
1107 }
1108 }
1109 default:
1110 break;
1111 }
1112 #ifdef X86
1113 } else {
1114 // FPU stack float instruction
1115 switch (op->code()) {
1116 case lir_add:
1117 case lir_sub:
1118 case lir_mul:
1119 case lir_div:
1120 {
1121 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1122 LIR_Op2* op2 = (LIR_Op2*)op;
1123 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1124 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1125 return shouldHaveRegister;
1126 }
1127 }
1128 default:
1129 break;
1130 }
1131 }
1132 #endif
1133 // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1134 // Since 64bit logical operations do not current support operands on stack, we have to make sure
1135 // T_OBJECT doesn't get spilled along with T_LONG.
1136 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1137 // integer instruction (note: long operands must always be in register)
1138 switch (op->code()) {
1139 case lir_cmp:
1140 case lir_add:
1141 case lir_sub:
1142 case lir_logic_and:
1143 case lir_logic_or:
1144 case lir_logic_xor:
1145 {
1146 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1147 LIR_Op2* op2 = (LIR_Op2*)op;
1148 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1149 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1150 return shouldHaveRegister;
1151 }
1152 }
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