--- old/src/cpu/x86/vm/assembler_x86.hpp	2014-07-22 11:44:00.439076308 +0400
+++ new/src/cpu/x86/vm/assembler_x86.hpp	2014-07-22 11:44:00.347073623 +0400
@@ -1283,14 +1283,21 @@
       if (order_constraint & StoreLoad) {
         // All usable chips support "locked" instructions which suffice
         // as barriers, and are much faster than the alternative of
-        // using cpuid instruction. We use here a locked add [esp],0.
+        // using cpuid instruction. We use here a locked add [esp+C],0.
         // This is conveniently otherwise a no-op except for blowing
-        // flags.
+        // flags, and introducing a false dependency on target memory
+        // location. We can't do anything with flags, but we can avoid
+        // memory dependencies in the current method by locked-adding
+        // somewhere else on the stack. [esp+C] is convenient since it
+        // is almost always in data cache, for any small C. Positive C
+        // will collide with something on stack in current method, hence
+        // we shoot for a small negative C.
+        //
         // Any change to this code may need to revisit other places in
         // the code where this idiom is used, in particular the
         // orderAccess code.
         lock();
-        addl(Address(rsp, 0), 0);// Assert the lock# signal here
+        addl(Address(rsp, -8), 0);// Assert the lock# signal here
       }
     }
   }