1 /* 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP 26 #define CPU_X86_VM_ASSEMBLER_X86_HPP 27 28 #include "asm/register.hpp" 29 #include "vm_version_x86.hpp" 30 31 class BiasedLockingCounters; 32 33 // Contains all the definitions needed for x86 assembly code generation. 34 35 // Calling convention 36 class Argument VALUE_OBJ_CLASS_SPEC { 37 public: 38 enum { 39 #ifdef _LP64 40 #ifdef _WIN64 41 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) 42 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) 43 #else 44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) 45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) 46 #endif // _WIN64 47 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... 48 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... 49 #else 50 n_register_parameters = 0 // 0 registers used to pass arguments 51 #endif // _LP64 52 }; 53 }; 54 55 56 #ifdef _LP64 57 // Symbolically name the register arguments used by the c calling convention. 58 // Windows is different from linux/solaris. So much for standards... 59 60 #ifdef _WIN64 61 62 REGISTER_DECLARATION(Register, c_rarg0, rcx); 63 REGISTER_DECLARATION(Register, c_rarg1, rdx); 64 REGISTER_DECLARATION(Register, c_rarg2, r8); 65 REGISTER_DECLARATION(Register, c_rarg3, r9); 66 67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 71 72 #else 73 74 REGISTER_DECLARATION(Register, c_rarg0, rdi); 75 REGISTER_DECLARATION(Register, c_rarg1, rsi); 76 REGISTER_DECLARATION(Register, c_rarg2, rdx); 77 REGISTER_DECLARATION(Register, c_rarg3, rcx); 78 REGISTER_DECLARATION(Register, c_rarg4, r8); 79 REGISTER_DECLARATION(Register, c_rarg5, r9); 80 81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); 86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); 87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); 88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); 89 90 #endif // _WIN64 91 92 // Symbolically name the register arguments used by the Java calling convention. 93 // We have control over the convention for java so we can do what we please. 94 // What pleases us is to offset the java calling convention so that when 95 // we call a suitable jni method the arguments are lined up and we don't 96 // have to do little shuffling. A suitable jni method is non-static and a 97 // small number of arguments (two fewer args on windows) 98 // 99 // |-------------------------------------------------------| 100 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | 101 // |-------------------------------------------------------| 102 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) 103 // | rdi rsi rdx rcx r8 r9 | solaris/linux 104 // |-------------------------------------------------------| 105 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | 106 // |-------------------------------------------------------| 107 108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 111 // Windows runs out of register args here 112 #ifdef _WIN64 113 REGISTER_DECLARATION(Register, j_rarg3, rdi); 114 REGISTER_DECLARATION(Register, j_rarg4, rsi); 115 #else 116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 118 #endif /* _WIN64 */ 119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); 120 121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); 122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); 123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); 124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); 125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); 126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); 127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); 128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); 129 130 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile 131 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile 132 133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved 134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved 135 136 #else 137 // rscratch1 will apear in 32bit code that is dead but of course must compile 138 // Using noreg ensures if the dead code is incorrectly live and executed it 139 // will cause an assertion failure 140 #define rscratch1 noreg 141 #define rscratch2 noreg 142 143 #endif // _LP64 144 145 // JSR 292 fixed register usages: 146 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); 147 148 // Address is an abstraction used to represent a memory location 149 // using any of the amd64 addressing modes with one object. 150 // 151 // Note: A register location is represented via a Register, not 152 // via an address for efficiency & simplicity reasons. 153 154 class ArrayAddress; 155 156 class Address VALUE_OBJ_CLASS_SPEC { 157 public: 158 enum ScaleFactor { 159 no_scale = -1, 160 times_1 = 0, 161 times_2 = 1, 162 times_4 = 2, 163 times_8 = 3, 164 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) 165 }; 166 static ScaleFactor times(int size) { 167 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); 168 if (size == 8) return times_8; 169 if (size == 4) return times_4; 170 if (size == 2) return times_2; 171 return times_1; 172 } 173 static int scale_size(ScaleFactor scale) { 174 assert(scale != no_scale, ""); 175 assert(((1 << (int)times_1) == 1 && 176 (1 << (int)times_2) == 2 && 177 (1 << (int)times_4) == 4 && 178 (1 << (int)times_8) == 8), ""); 179 return (1 << (int)scale); 180 } 181 182 private: 183 Register _base; 184 Register _index; 185 ScaleFactor _scale; 186 int _disp; 187 RelocationHolder _rspec; 188 189 // Easily misused constructors make them private 190 // %%% can we make these go away? 191 NOT_LP64(Address(address loc, RelocationHolder spec);) 192 Address(int disp, address loc, relocInfo::relocType rtype); 193 Address(int disp, address loc, RelocationHolder spec); 194 195 public: 196 197 int disp() { return _disp; } 198 // creation 199 Address() 200 : _base(noreg), 201 _index(noreg), 202 _scale(no_scale), 203 _disp(0) { 204 } 205 206 // No default displacement otherwise Register can be implicitly 207 // converted to 0(Register) which is quite a different animal. 208 209 Address(Register base, int disp) 210 : _base(base), 211 _index(noreg), 212 _scale(no_scale), 213 _disp(disp) { 214 } 215 216 Address(Register base, Register index, ScaleFactor scale, int disp = 0) 217 : _base (base), 218 _index(index), 219 _scale(scale), 220 _disp (disp) { 221 assert(!index->is_valid() == (scale == Address::no_scale), 222 "inconsistent address"); 223 } 224 225 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) 226 : _base (base), 227 _index(index.register_or_noreg()), 228 _scale(scale), 229 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { 230 if (!index.is_register()) scale = Address::no_scale; 231 assert(!_index->is_valid() == (scale == Address::no_scale), 232 "inconsistent address"); 233 } 234 235 Address plus_disp(int disp) const { 236 Address a = (*this); 237 a._disp += disp; 238 return a; 239 } 240 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { 241 Address a = (*this); 242 a._disp += disp.constant_or_zero() * scale_size(scale); 243 if (disp.is_register()) { 244 assert(!a.index()->is_valid(), "competing indexes"); 245 a._index = disp.as_register(); 246 a._scale = scale; 247 } 248 return a; 249 } 250 bool is_same_address(Address a) const { 251 // disregard _rspec 252 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; 253 } 254 255 // The following two overloads are used in connection with the 256 // ByteSize type (see sizes.hpp). They simplify the use of 257 // ByteSize'd arguments in assembly code. Note that their equivalent 258 // for the optimized build are the member functions with int disp 259 // argument since ByteSize is mapped to an int type in that case. 260 // 261 // Note: DO NOT introduce similar overloaded functions for WordSize 262 // arguments as in the optimized mode, both ByteSize and WordSize 263 // are mapped to the same type and thus the compiler cannot make a 264 // distinction anymore (=> compiler errors). 265 266 #ifdef ASSERT 267 Address(Register base, ByteSize disp) 268 : _base(base), 269 _index(noreg), 270 _scale(no_scale), 271 _disp(in_bytes(disp)) { 272 } 273 274 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) 275 : _base(base), 276 _index(index), 277 _scale(scale), 278 _disp(in_bytes(disp)) { 279 assert(!index->is_valid() == (scale == Address::no_scale), 280 "inconsistent address"); 281 } 282 283 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) 284 : _base (base), 285 _index(index.register_or_noreg()), 286 _scale(scale), 287 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { 288 if (!index.is_register()) scale = Address::no_scale; 289 assert(!_index->is_valid() == (scale == Address::no_scale), 290 "inconsistent address"); 291 } 292 293 #endif // ASSERT 294 295 // accessors 296 bool uses(Register reg) const { return _base == reg || _index == reg; } 297 Register base() const { return _base; } 298 Register index() const { return _index; } 299 ScaleFactor scale() const { return _scale; } 300 int disp() const { return _disp; } 301 302 // Convert the raw encoding form into the form expected by the constructor for 303 // Address. An index of 4 (rsp) corresponds to having no index, so convert 304 // that to noreg for the Address constructor. 305 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); 306 307 static Address make_array(ArrayAddress); 308 309 private: 310 bool base_needs_rex() const { 311 return _base != noreg && _base->encoding() >= 8; 312 } 313 314 bool index_needs_rex() const { 315 return _index != noreg &&_index->encoding() >= 8; 316 } 317 318 relocInfo::relocType reloc() const { return _rspec.type(); } 319 320 friend class Assembler; 321 friend class MacroAssembler; 322 friend class LIR_Assembler; // base/index/scale/disp 323 }; 324 325 // 326 // AddressLiteral has been split out from Address because operands of this type 327 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out 328 // the few instructions that need to deal with address literals are unique and the 329 // MacroAssembler does not have to implement every instruction in the Assembler 330 // in order to search for address literals that may need special handling depending 331 // on the instruction and the platform. As small step on the way to merging i486/amd64 332 // directories. 333 // 334 class AddressLiteral VALUE_OBJ_CLASS_SPEC { 335 friend class ArrayAddress; 336 RelocationHolder _rspec; 337 // Typically we use AddressLiterals we want to use their rval 338 // However in some situations we want the lval (effect address) of the item. 339 // We provide a special factory for making those lvals. 340 bool _is_lval; 341 342 // If the target is far we'll need to load the ea of this to 343 // a register to reach it. Otherwise if near we can do rip 344 // relative addressing. 345 346 address _target; 347 348 protected: 349 // creation 350 AddressLiteral() 351 : _is_lval(false), 352 _target(NULL) 353 {} 354 355 public: 356 357 358 AddressLiteral(address target, relocInfo::relocType rtype); 359 360 AddressLiteral(address target, RelocationHolder const& rspec) 361 : _rspec(rspec), 362 _is_lval(false), 363 _target(target) 364 {} 365 366 AddressLiteral addr() { 367 AddressLiteral ret = *this; 368 ret._is_lval = true; 369 return ret; 370 } 371 372 373 private: 374 375 address target() { return _target; } 376 bool is_lval() { return _is_lval; } 377 378 relocInfo::relocType reloc() const { return _rspec.type(); } 379 const RelocationHolder& rspec() const { return _rspec; } 380 381 friend class Assembler; 382 friend class MacroAssembler; 383 friend class Address; 384 friend class LIR_Assembler; 385 }; 386 387 // Convience classes 388 class RuntimeAddress: public AddressLiteral { 389 390 public: 391 392 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} 393 394 }; 395 396 class ExternalAddress: public AddressLiteral { 397 private: 398 static relocInfo::relocType reloc_for_target(address target) { 399 // Sometimes ExternalAddress is used for values which aren't 400 // exactly addresses, like the card table base. 401 // external_word_type can't be used for values in the first page 402 // so just skip the reloc in that case. 403 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 404 } 405 406 public: 407 408 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} 409 410 }; 411 412 class InternalAddress: public AddressLiteral { 413 414 public: 415 416 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} 417 418 }; 419 420 // x86 can do array addressing as a single operation since disp can be an absolute 421 // address amd64 can't. We create a class that expresses the concept but does extra 422 // magic on amd64 to get the final result 423 424 class ArrayAddress VALUE_OBJ_CLASS_SPEC { 425 private: 426 427 AddressLiteral _base; 428 Address _index; 429 430 public: 431 432 ArrayAddress() {}; 433 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; 434 AddressLiteral base() { return _base; } 435 Address index() { return _index; } 436 437 }; 438 439 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); 440 441 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction 442 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write 443 // is what you get. The Assembler is generating code into a CodeBuffer. 444 445 class Assembler : public AbstractAssembler { 446 friend class AbstractAssembler; // for the non-virtual hack 447 friend class LIR_Assembler; // as_Address() 448 friend class StubGenerator; 449 450 public: 451 enum Condition { // The x86 condition codes used for conditional jumps/moves. 452 zero = 0x4, 453 notZero = 0x5, 454 equal = 0x4, 455 notEqual = 0x5, 456 less = 0xc, 457 lessEqual = 0xe, 458 greater = 0xf, 459 greaterEqual = 0xd, 460 below = 0x2, 461 belowEqual = 0x6, 462 above = 0x7, 463 aboveEqual = 0x3, 464 overflow = 0x0, 465 noOverflow = 0x1, 466 carrySet = 0x2, 467 carryClear = 0x3, 468 negative = 0x8, 469 positive = 0x9, 470 parity = 0xa, 471 noParity = 0xb 472 }; 473 474 enum Prefix { 475 // segment overrides 476 CS_segment = 0x2e, 477 SS_segment = 0x36, 478 DS_segment = 0x3e, 479 ES_segment = 0x26, 480 FS_segment = 0x64, 481 GS_segment = 0x65, 482 483 REX = 0x40, 484 485 REX_B = 0x41, 486 REX_X = 0x42, 487 REX_XB = 0x43, 488 REX_R = 0x44, 489 REX_RB = 0x45, 490 REX_RX = 0x46, 491 REX_RXB = 0x47, 492 493 REX_W = 0x48, 494 495 REX_WB = 0x49, 496 REX_WX = 0x4A, 497 REX_WXB = 0x4B, 498 REX_WR = 0x4C, 499 REX_WRB = 0x4D, 500 REX_WRX = 0x4E, 501 REX_WRXB = 0x4F, 502 503 VEX_3bytes = 0xC4, 504 VEX_2bytes = 0xC5 505 }; 506 507 enum VexPrefix { 508 VEX_B = 0x20, 509 VEX_X = 0x40, 510 VEX_R = 0x80, 511 VEX_W = 0x80 512 }; 513 514 enum VexSimdPrefix { 515 VEX_SIMD_NONE = 0x0, 516 VEX_SIMD_66 = 0x1, 517 VEX_SIMD_F3 = 0x2, 518 VEX_SIMD_F2 = 0x3 519 }; 520 521 enum VexOpcode { 522 VEX_OPCODE_NONE = 0x0, 523 VEX_OPCODE_0F = 0x1, 524 VEX_OPCODE_0F_38 = 0x2, 525 VEX_OPCODE_0F_3A = 0x3 526 }; 527 528 enum WhichOperand { 529 // input to locate_operand, and format code for relocations 530 imm_operand = 0, // embedded 32-bit|64-bit immediate operand 531 disp32_operand = 1, // embedded 32-bit displacement or address 532 call32_operand = 2, // embedded 32-bit self-relative displacement 533 #ifndef _LP64 534 _WhichOperand_limit = 3 535 #else 536 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop 537 _WhichOperand_limit = 4 538 #endif 539 }; 540 541 542 543 // NOTE: The general philopsophy of the declarations here is that 64bit versions 544 // of instructions are freely declared without the need for wrapping them an ifdef. 545 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) 546 // In the .cpp file the implementations are wrapped so that they are dropped out 547 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL 548 // to the size it was prior to merging up the 32bit and 64bit assemblers. 549 // 550 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction 551 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. 552 553 private: 554 555 556 // 64bit prefixes 557 int prefix_and_encode(int reg_enc, bool byteinst = false); 558 int prefixq_and_encode(int reg_enc); 559 560 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); 561 int prefixq_and_encode(int dst_enc, int src_enc); 562 563 void prefix(Register reg); 564 void prefix(Address adr); 565 void prefixq(Address adr); 566 567 void prefix(Address adr, Register reg, bool byteinst = false); 568 void prefix(Address adr, XMMRegister reg); 569 void prefixq(Address adr, Register reg); 570 void prefixq(Address adr, XMMRegister reg); 571 572 void prefetch_prefix(Address src); 573 574 void rex_prefix(Address adr, XMMRegister xreg, 575 VexSimdPrefix pre, VexOpcode opc, bool rex_w); 576 int rex_prefix_and_encode(int dst_enc, int src_enc, 577 VexSimdPrefix pre, VexOpcode opc, bool rex_w); 578 579 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, 580 int nds_enc, VexSimdPrefix pre, VexOpcode opc, 581 bool vector256); 582 583 void vex_prefix(Address adr, int nds_enc, int xreg_enc, 584 VexSimdPrefix pre, VexOpcode opc, 585 bool vex_w, bool vector256); 586 587 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, 588 VexSimdPrefix pre, bool vector256 = false) { 589 int dst_enc = dst->encoding(); 590 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 591 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); 592 } 593 594 void vex_prefix_0F38(Register dst, Register nds, Address src) { 595 bool vex_w = false; 596 bool vector256 = false; 597 vex_prefix(src, nds->encoding(), dst->encoding(), 598 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); 599 } 600 601 void vex_prefix_0F38_q(Register dst, Register nds, Address src) { 602 bool vex_w = true; 603 bool vector256 = false; 604 vex_prefix(src, nds->encoding(), dst->encoding(), 605 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); 606 } 607 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, 608 VexSimdPrefix pre, VexOpcode opc, 609 bool vex_w, bool vector256); 610 611 int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src) { 612 bool vex_w = false; 613 bool vector256 = false; 614 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), 615 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); 616 } 617 int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src) { 618 bool vex_w = true; 619 bool vector256 = false; 620 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), 621 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); 622 } 623 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, 624 VexSimdPrefix pre, bool vector256 = false, 625 VexOpcode opc = VEX_OPCODE_0F) { 626 int src_enc = src->encoding(); 627 int dst_enc = dst->encoding(); 628 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 629 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256); 630 } 631 632 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, 633 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, 634 bool rex_w = false, bool vector256 = false); 635 636 void simd_prefix(XMMRegister dst, Address src, 637 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 638 simd_prefix(dst, xnoreg, src, pre, opc); 639 } 640 641 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { 642 simd_prefix(src, dst, pre); 643 } 644 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, 645 VexSimdPrefix pre) { 646 bool rex_w = true; 647 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); 648 } 649 650 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, 651 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, 652 bool rex_w = false, bool vector256 = false); 653 654 // Move/convert 32-bit integer value. 655 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, 656 VexSimdPrefix pre) { 657 // It is OK to cast from Register to XMMRegister to pass argument here 658 // since only encoding is used in simd_prefix_and_encode() and number of 659 // Gen and Xmm registers are the same. 660 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); 661 } 662 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { 663 return simd_prefix_and_encode(dst, xnoreg, src, pre); 664 } 665 int simd_prefix_and_encode(Register dst, XMMRegister src, 666 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 667 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); 668 } 669 670 // Move/convert 64-bit integer value. 671 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, 672 VexSimdPrefix pre) { 673 bool rex_w = true; 674 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); 675 } 676 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { 677 return simd_prefix_and_encode_q(dst, xnoreg, src, pre); 678 } 679 int simd_prefix_and_encode_q(Register dst, XMMRegister src, 680 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 681 bool rex_w = true; 682 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); 683 } 684 685 // Helper functions for groups of instructions 686 void emit_arith_b(int op1, int op2, Register dst, int imm8); 687 688 void emit_arith(int op1, int op2, Register dst, int32_t imm32); 689 // Force generation of a 4 byte immediate value even if it fits into 8bit 690 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); 691 void emit_arith(int op1, int op2, Register dst, Register src); 692 693 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); 694 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); 695 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); 696 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); 697 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, 698 Address src, VexSimdPrefix pre, bool vector256); 699 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, 700 XMMRegister src, VexSimdPrefix pre, bool vector256); 701 702 void emit_operand(Register reg, 703 Register base, Register index, Address::ScaleFactor scale, 704 int disp, 705 RelocationHolder const& rspec, 706 int rip_relative_correction = 0); 707 708 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); 709 710 // operands that only take the original 32bit registers 711 void emit_operand32(Register reg, Address adr); 712 713 void emit_operand(XMMRegister reg, 714 Register base, Register index, Address::ScaleFactor scale, 715 int disp, 716 RelocationHolder const& rspec); 717 718 void emit_operand(XMMRegister reg, Address adr); 719 720 void emit_operand(MMXRegister reg, Address adr); 721 722 // workaround gcc (3.2.1-7) bug 723 void emit_operand(Address adr, MMXRegister reg); 724 725 726 // Immediate-to-memory forms 727 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); 728 729 void emit_farith(int b1, int b2, int i); 730 731 732 protected: 733 #ifdef ASSERT 734 void check_relocation(RelocationHolder const& rspec, int format); 735 #endif 736 737 void emit_data(jint data, relocInfo::relocType rtype, int format); 738 void emit_data(jint data, RelocationHolder const& rspec, int format); 739 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 740 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 741 742 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); 743 744 // These are all easily abused and hence protected 745 746 // 32BIT ONLY SECTION 747 #ifndef _LP64 748 // Make these disappear in 64bit mode since they would never be correct 749 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 750 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 751 752 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 753 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 754 755 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 756 #else 757 // 64BIT ONLY SECTION 758 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY 759 760 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); 761 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); 762 763 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); 764 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); 765 #endif // _LP64 766 767 // These are unique in that we are ensured by the caller that the 32bit 768 // relative in these instructions will always be able to reach the potentially 769 // 64bit address described by entry. Since they can take a 64bit address they 770 // don't have the 32 suffix like the other instructions in this class. 771 772 void call_literal(address entry, RelocationHolder const& rspec); 773 void jmp_literal(address entry, RelocationHolder const& rspec); 774 775 // Avoid using directly section 776 // Instructions in this section are actually usable by anyone without danger 777 // of failure but have performance issues that are addressed my enhanced 778 // instructions which will do the proper thing base on the particular cpu. 779 // We protect them because we don't trust you... 780 781 // Don't use next inc() and dec() methods directly. INC & DEC instructions 782 // could cause a partial flag stall since they don't set CF flag. 783 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods 784 // which call inc() & dec() or add() & sub() in accordance with 785 // the product flag UseIncDec value. 786 787 void decl(Register dst); 788 void decl(Address dst); 789 void decq(Register dst); 790 void decq(Address dst); 791 792 void incl(Register dst); 793 void incl(Address dst); 794 void incq(Register dst); 795 void incq(Address dst); 796 797 // New cpus require use of movsd and movss to avoid partial register stall 798 // when loading from memory. But for old Opteron use movlpd instead of movsd. 799 // The selection is done in MacroAssembler::movdbl() and movflt(). 800 801 // Move Scalar Single-Precision Floating-Point Values 802 void movss(XMMRegister dst, Address src); 803 void movss(XMMRegister dst, XMMRegister src); 804 void movss(Address dst, XMMRegister src); 805 806 // Move Scalar Double-Precision Floating-Point Values 807 void movsd(XMMRegister dst, Address src); 808 void movsd(XMMRegister dst, XMMRegister src); 809 void movsd(Address dst, XMMRegister src); 810 void movlpd(XMMRegister dst, Address src); 811 812 // New cpus require use of movaps and movapd to avoid partial register stall 813 // when moving between registers. 814 void movaps(XMMRegister dst, XMMRegister src); 815 void movapd(XMMRegister dst, XMMRegister src); 816 817 // End avoid using directly 818 819 820 // Instruction prefixes 821 void prefix(Prefix p); 822 823 public: 824 825 // Creation 826 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} 827 828 // Decoding 829 static address locate_operand(address inst, WhichOperand which); 830 static address locate_next_instruction(address inst); 831 832 // Utilities 833 static bool is_polling_page_far() NOT_LP64({ return false;}); 834 835 // Generic instructions 836 // Does 32bit or 64bit as needed for the platform. In some sense these 837 // belong in macro assembler but there is no need for both varieties to exist 838 839 void lea(Register dst, Address src); 840 841 void mov(Register dst, Register src); 842 843 void pusha(); 844 void popa(); 845 846 void pushf(); 847 void popf(); 848 849 void push(int32_t imm32); 850 851 void push(Register src); 852 853 void pop(Register dst); 854 855 // These are dummies to prevent surprise implicit conversions to Register 856 void push(void* v); 857 void pop(void* v); 858 859 // These do register sized moves/scans 860 void rep_mov(); 861 void rep_stos(); 862 void rep_stosb(); 863 void repne_scan(); 864 #ifdef _LP64 865 void repne_scanl(); 866 #endif 867 868 // Vanilla instructions in lexical order 869 870 void adcl(Address dst, int32_t imm32); 871 void adcl(Address dst, Register src); 872 void adcl(Register dst, int32_t imm32); 873 void adcl(Register dst, Address src); 874 void adcl(Register dst, Register src); 875 876 void adcq(Register dst, int32_t imm32); 877 void adcq(Register dst, Address src); 878 void adcq(Register dst, Register src); 879 880 void addl(Address dst, int32_t imm32); 881 void addl(Address dst, Register src); 882 void addl(Register dst, int32_t imm32); 883 void addl(Register dst, Address src); 884 void addl(Register dst, Register src); 885 886 void addq(Address dst, int32_t imm32); 887 void addq(Address dst, Register src); 888 void addq(Register dst, int32_t imm32); 889 void addq(Register dst, Address src); 890 void addq(Register dst, Register src); 891 892 void addr_nop_4(); 893 void addr_nop_5(); 894 void addr_nop_7(); 895 void addr_nop_8(); 896 897 // Add Scalar Double-Precision Floating-Point Values 898 void addsd(XMMRegister dst, Address src); 899 void addsd(XMMRegister dst, XMMRegister src); 900 901 // Add Scalar Single-Precision Floating-Point Values 902 void addss(XMMRegister dst, Address src); 903 void addss(XMMRegister dst, XMMRegister src); 904 905 // AES instructions 906 void aesdec(XMMRegister dst, Address src); 907 void aesdec(XMMRegister dst, XMMRegister src); 908 void aesdeclast(XMMRegister dst, Address src); 909 void aesdeclast(XMMRegister dst, XMMRegister src); 910 void aesenc(XMMRegister dst, Address src); 911 void aesenc(XMMRegister dst, XMMRegister src); 912 void aesenclast(XMMRegister dst, Address src); 913 void aesenclast(XMMRegister dst, XMMRegister src); 914 915 916 void andl(Address dst, int32_t imm32); 917 void andl(Register dst, int32_t imm32); 918 void andl(Register dst, Address src); 919 void andl(Register dst, Register src); 920 921 void andq(Address dst, int32_t imm32); 922 void andq(Register dst, int32_t imm32); 923 void andq(Register dst, Address src); 924 void andq(Register dst, Register src); 925 926 // BMI instructions 927 void andnl(Register dst, Register src1, Register src2); 928 void andnl(Register dst, Register src1, Address src2); 929 void andnq(Register dst, Register src1, Register src2); 930 void andnq(Register dst, Register src1, Address src2); 931 932 void blsil(Register dst, Register src); 933 void blsil(Register dst, Address src); 934 void blsiq(Register dst, Register src); 935 void blsiq(Register dst, Address src); 936 937 void blsmskl(Register dst, Register src); 938 void blsmskl(Register dst, Address src); 939 void blsmskq(Register dst, Register src); 940 void blsmskq(Register dst, Address src); 941 942 void blsrl(Register dst, Register src); 943 void blsrl(Register dst, Address src); 944 void blsrq(Register dst, Register src); 945 void blsrq(Register dst, Address src); 946 947 void bsfl(Register dst, Register src); 948 void bsrl(Register dst, Register src); 949 950 #ifdef _LP64 951 void bsfq(Register dst, Register src); 952 void bsrq(Register dst, Register src); 953 #endif 954 955 void bswapl(Register reg); 956 957 void bswapq(Register reg); 958 959 void call(Label& L, relocInfo::relocType rtype); 960 void call(Register reg); // push pc; pc <- reg 961 void call(Address adr); // push pc; pc <- adr 962 963 void cdql(); 964 965 void cdqq(); 966 967 void cld(); 968 969 void clflush(Address adr); 970 971 void cmovl(Condition cc, Register dst, Register src); 972 void cmovl(Condition cc, Register dst, Address src); 973 974 void cmovq(Condition cc, Register dst, Register src); 975 void cmovq(Condition cc, Register dst, Address src); 976 977 978 void cmpb(Address dst, int imm8); 979 980 void cmpl(Address dst, int32_t imm32); 981 982 void cmpl(Register dst, int32_t imm32); 983 void cmpl(Register dst, Register src); 984 void cmpl(Register dst, Address src); 985 986 void cmpq(Address dst, int32_t imm32); 987 void cmpq(Address dst, Register src); 988 989 void cmpq(Register dst, int32_t imm32); 990 void cmpq(Register dst, Register src); 991 void cmpq(Register dst, Address src); 992 993 // these are dummies used to catch attempting to convert NULL to Register 994 void cmpl(Register dst, void* junk); // dummy 995 void cmpq(Register dst, void* junk); // dummy 996 997 void cmpw(Address dst, int imm16); 998 999 void cmpxchg8 (Address adr); 1000 1001 void cmpxchgl(Register reg, Address adr); 1002 1003 void cmpxchgq(Register reg, Address adr); 1004 1005 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 1006 void comisd(XMMRegister dst, Address src); 1007 void comisd(XMMRegister dst, XMMRegister src); 1008 1009 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 1010 void comiss(XMMRegister dst, Address src); 1011 void comiss(XMMRegister dst, XMMRegister src); 1012 1013 // Identify processor type and features 1014 void cpuid(); 1015 1016 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value 1017 void cvtsd2ss(XMMRegister dst, XMMRegister src); 1018 void cvtsd2ss(XMMRegister dst, Address src); 1019 1020 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value 1021 void cvtsi2sdl(XMMRegister dst, Register src); 1022 void cvtsi2sdl(XMMRegister dst, Address src); 1023 void cvtsi2sdq(XMMRegister dst, Register src); 1024 void cvtsi2sdq(XMMRegister dst, Address src); 1025 1026 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value 1027 void cvtsi2ssl(XMMRegister dst, Register src); 1028 void cvtsi2ssl(XMMRegister dst, Address src); 1029 void cvtsi2ssq(XMMRegister dst, Register src); 1030 void cvtsi2ssq(XMMRegister dst, Address src); 1031 1032 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value 1033 void cvtdq2pd(XMMRegister dst, XMMRegister src); 1034 1035 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value 1036 void cvtdq2ps(XMMRegister dst, XMMRegister src); 1037 1038 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value 1039 void cvtss2sd(XMMRegister dst, XMMRegister src); 1040 void cvtss2sd(XMMRegister dst, Address src); 1041 1042 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer 1043 void cvttsd2sil(Register dst, Address src); 1044 void cvttsd2sil(Register dst, XMMRegister src); 1045 void cvttsd2siq(Register dst, XMMRegister src); 1046 1047 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer 1048 void cvttss2sil(Register dst, XMMRegister src); 1049 void cvttss2siq(Register dst, XMMRegister src); 1050 1051 // Divide Scalar Double-Precision Floating-Point Values 1052 void divsd(XMMRegister dst, Address src); 1053 void divsd(XMMRegister dst, XMMRegister src); 1054 1055 // Divide Scalar Single-Precision Floating-Point Values 1056 void divss(XMMRegister dst, Address src); 1057 void divss(XMMRegister dst, XMMRegister src); 1058 1059 void emms(); 1060 1061 void fabs(); 1062 1063 void fadd(int i); 1064 1065 void fadd_d(Address src); 1066 void fadd_s(Address src); 1067 1068 // "Alternate" versions of x87 instructions place result down in FPU 1069 // stack instead of on TOS 1070 1071 void fadda(int i); // "alternate" fadd 1072 void faddp(int i = 1); 1073 1074 void fchs(); 1075 1076 void fcom(int i); 1077 1078 void fcomp(int i = 1); 1079 void fcomp_d(Address src); 1080 void fcomp_s(Address src); 1081 1082 void fcompp(); 1083 1084 void fcos(); 1085 1086 void fdecstp(); 1087 1088 void fdiv(int i); 1089 void fdiv_d(Address src); 1090 void fdivr_s(Address src); 1091 void fdiva(int i); // "alternate" fdiv 1092 void fdivp(int i = 1); 1093 1094 void fdivr(int i); 1095 void fdivr_d(Address src); 1096 void fdiv_s(Address src); 1097 1098 void fdivra(int i); // "alternate" reversed fdiv 1099 1100 void fdivrp(int i = 1); 1101 1102 void ffree(int i = 0); 1103 1104 void fild_d(Address adr); 1105 void fild_s(Address adr); 1106 1107 void fincstp(); 1108 1109 void finit(); 1110 1111 void fist_s (Address adr); 1112 void fistp_d(Address adr); 1113 void fistp_s(Address adr); 1114 1115 void fld1(); 1116 1117 void fld_d(Address adr); 1118 void fld_s(Address adr); 1119 void fld_s(int index); 1120 void fld_x(Address adr); // extended-precision (80-bit) format 1121 1122 void fldcw(Address src); 1123 1124 void fldenv(Address src); 1125 1126 void fldlg2(); 1127 1128 void fldln2(); 1129 1130 void fldz(); 1131 1132 void flog(); 1133 void flog10(); 1134 1135 void fmul(int i); 1136 1137 void fmul_d(Address src); 1138 void fmul_s(Address src); 1139 1140 void fmula(int i); // "alternate" fmul 1141 1142 void fmulp(int i = 1); 1143 1144 void fnsave(Address dst); 1145 1146 void fnstcw(Address src); 1147 1148 void fnstsw_ax(); 1149 1150 void fprem(); 1151 void fprem1(); 1152 1153 void frstor(Address src); 1154 1155 void fsin(); 1156 1157 void fsqrt(); 1158 1159 void fst_d(Address adr); 1160 void fst_s(Address adr); 1161 1162 void fstp_d(Address adr); 1163 void fstp_d(int index); 1164 void fstp_s(Address adr); 1165 void fstp_x(Address adr); // extended-precision (80-bit) format 1166 1167 void fsub(int i); 1168 void fsub_d(Address src); 1169 void fsub_s(Address src); 1170 1171 void fsuba(int i); // "alternate" fsub 1172 1173 void fsubp(int i = 1); 1174 1175 void fsubr(int i); 1176 void fsubr_d(Address src); 1177 void fsubr_s(Address src); 1178 1179 void fsubra(int i); // "alternate" reversed fsub 1180 1181 void fsubrp(int i = 1); 1182 1183 void ftan(); 1184 1185 void ftst(); 1186 1187 void fucomi(int i = 1); 1188 void fucomip(int i = 1); 1189 1190 void fwait(); 1191 1192 void fxch(int i = 1); 1193 1194 void fxrstor(Address src); 1195 1196 void fxsave(Address dst); 1197 1198 void fyl2x(); 1199 void frndint(); 1200 void f2xm1(); 1201 void fldl2e(); 1202 1203 void hlt(); 1204 1205 void idivl(Register src); 1206 void divl(Register src); // Unsigned division 1207 1208 void idivq(Register src); 1209 1210 void imull(Register dst, Register src); 1211 void imull(Register dst, Register src, int value); 1212 void imull(Register dst, Address src); 1213 1214 void imulq(Register dst, Register src); 1215 void imulq(Register dst, Register src, int value); 1216 #ifdef _LP64 1217 void imulq(Register dst, Address src); 1218 #endif 1219 1220 1221 // jcc is the generic conditional branch generator to run- 1222 // time routines, jcc is used for branches to labels. jcc 1223 // takes a branch opcode (cc) and a label (L) and generates 1224 // either a backward branch or a forward branch and links it 1225 // to the label fixup chain. Usage: 1226 // 1227 // Label L; // unbound label 1228 // jcc(cc, L); // forward branch to unbound label 1229 // bind(L); // bind label to the current pc 1230 // jcc(cc, L); // backward branch to bound label 1231 // bind(L); // illegal: a label may be bound only once 1232 // 1233 // Note: The same Label can be used for forward and backward branches 1234 // but it may be bound only once. 1235 1236 void jcc(Condition cc, Label& L, bool maybe_short = true); 1237 1238 // Conditional jump to a 8-bit offset to L. 1239 // WARNING: be very careful using this for forward jumps. If the label is 1240 // not bound within an 8-bit offset of this instruction, a run-time error 1241 // will occur. 1242 void jccb(Condition cc, Label& L); 1243 1244 void jmp(Address entry); // pc <- entry 1245 1246 // Label operations & relative jumps (PPUM Appendix D) 1247 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L 1248 1249 void jmp(Register entry); // pc <- entry 1250 1251 // Unconditional 8-bit offset jump to L. 1252 // WARNING: be very careful using this for forward jumps. If the label is 1253 // not bound within an 8-bit offset of this instruction, a run-time error 1254 // will occur. 1255 void jmpb(Label& L); 1256 1257 void ldmxcsr( Address src ); 1258 1259 void leal(Register dst, Address src); 1260 1261 void leaq(Register dst, Address src); 1262 1263 void lfence(); 1264 1265 void lock(); 1266 1267 void lzcntl(Register dst, Register src); 1268 1269 #ifdef _LP64 1270 void lzcntq(Register dst, Register src); 1271 #endif 1272 1273 enum Membar_mask_bits { 1274 StoreStore = 1 << 3, 1275 LoadStore = 1 << 2, 1276 StoreLoad = 1 << 1, 1277 LoadLoad = 1 << 0 1278 }; 1279 1280 // Serializes memory and blows flags 1281 void membar(Membar_mask_bits order_constraint) { 1282 if (os::is_MP()) { 1283 // We only have to handle StoreLoad 1284 if (order_constraint & StoreLoad) { 1285 // All usable chips support "locked" instructions which suffice 1286 // as barriers, and are much faster than the alternative of 1287 // using cpuid instruction. We use here a locked add [esp-C],0. 1288 // This is conveniently otherwise a no-op except for blowing 1289 // flags, and introducing a false dependency on target memory 1290 // location. We can't do anything with flags, but we can avoid 1291 // memory dependencies in the current method by locked-adding 1292 // somewhere else on the stack. Doing [esp+C] will collide with 1293 // something on stack in current method, hence we go for [esp-C]. 1294 // It is convenient since it is almost always in data cache, for 1295 // any small C. We need to step back from SP to avoid data 1296 // dependencies with other things on below SP (callee-saves, for 1297 // example). Without a clear way to figure out the minimal safe 1298 // distance from SP, it makes sense to step back the complete 1299 // cache line, as this will also avoid possible second-order effects 1300 // with locked ops against the cache line. Our choice of offset 1301 // is bounded by x86 operand encoding, which should stay within 1302 // [-128; +127] to have the 8-byte displacement encoding. 1303 // 1304 // Any change to this code may need to revisit other places in 1305 // the code where this idiom is used, in particular the 1306 // orderAccess code. 1307 1308 int offset = -VM_Version::L1_line_size(); 1309 if (offset < -128) { 1310 offset = -128; 1311 } 1312 1313 lock(); 1314 addl(Address(rsp, offset), 0);// Assert the lock# signal here 1315 } 1316 } 1317 } 1318 1319 void mfence(); 1320 1321 // Moves 1322 1323 void mov64(Register dst, int64_t imm64); 1324 1325 void movb(Address dst, Register src); 1326 void movb(Address dst, int imm8); 1327 void movb(Register dst, Address src); 1328 1329 void movdl(XMMRegister dst, Register src); 1330 void movdl(Register dst, XMMRegister src); 1331 void movdl(XMMRegister dst, Address src); 1332 void movdl(Address dst, XMMRegister src); 1333 1334 // Move Double Quadword 1335 void movdq(XMMRegister dst, Register src); 1336 void movdq(Register dst, XMMRegister src); 1337 1338 // Move Aligned Double Quadword 1339 void movdqa(XMMRegister dst, XMMRegister src); 1340 void movdqa(XMMRegister dst, Address src); 1341 1342 // Move Unaligned Double Quadword 1343 void movdqu(Address dst, XMMRegister src); 1344 void movdqu(XMMRegister dst, Address src); 1345 void movdqu(XMMRegister dst, XMMRegister src); 1346 1347 // Move Unaligned 256bit Vector 1348 void vmovdqu(Address dst, XMMRegister src); 1349 void vmovdqu(XMMRegister dst, Address src); 1350 void vmovdqu(XMMRegister dst, XMMRegister src); 1351 1352 // Move lower 64bit to high 64bit in 128bit register 1353 void movlhps(XMMRegister dst, XMMRegister src); 1354 1355 void movl(Register dst, int32_t imm32); 1356 void movl(Address dst, int32_t imm32); 1357 void movl(Register dst, Register src); 1358 void movl(Register dst, Address src); 1359 void movl(Address dst, Register src); 1360 1361 // These dummies prevent using movl from converting a zero (like NULL) into Register 1362 // by giving the compiler two choices it can't resolve 1363 1364 void movl(Address dst, void* junk); 1365 void movl(Register dst, void* junk); 1366 1367 #ifdef _LP64 1368 void movq(Register dst, Register src); 1369 void movq(Register dst, Address src); 1370 void movq(Address dst, Register src); 1371 #endif 1372 1373 void movq(Address dst, MMXRegister src ); 1374 void movq(MMXRegister dst, Address src ); 1375 1376 #ifdef _LP64 1377 // These dummies prevent using movq from converting a zero (like NULL) into Register 1378 // by giving the compiler two choices it can't resolve 1379 1380 void movq(Address dst, void* dummy); 1381 void movq(Register dst, void* dummy); 1382 #endif 1383 1384 // Move Quadword 1385 void movq(Address dst, XMMRegister src); 1386 void movq(XMMRegister dst, Address src); 1387 1388 void movsbl(Register dst, Address src); 1389 void movsbl(Register dst, Register src); 1390 1391 #ifdef _LP64 1392 void movsbq(Register dst, Address src); 1393 void movsbq(Register dst, Register src); 1394 1395 // Move signed 32bit immediate to 64bit extending sign 1396 void movslq(Address dst, int32_t imm64); 1397 void movslq(Register dst, int32_t imm64); 1398 1399 void movslq(Register dst, Address src); 1400 void movslq(Register dst, Register src); 1401 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous 1402 #endif 1403 1404 void movswl(Register dst, Address src); 1405 void movswl(Register dst, Register src); 1406 1407 #ifdef _LP64 1408 void movswq(Register dst, Address src); 1409 void movswq(Register dst, Register src); 1410 #endif 1411 1412 void movw(Address dst, int imm16); 1413 void movw(Register dst, Address src); 1414 void movw(Address dst, Register src); 1415 1416 void movzbl(Register dst, Address src); 1417 void movzbl(Register dst, Register src); 1418 1419 #ifdef _LP64 1420 void movzbq(Register dst, Address src); 1421 void movzbq(Register dst, Register src); 1422 #endif 1423 1424 void movzwl(Register dst, Address src); 1425 void movzwl(Register dst, Register src); 1426 1427 #ifdef _LP64 1428 void movzwq(Register dst, Address src); 1429 void movzwq(Register dst, Register src); 1430 #endif 1431 1432 void mull(Address src); 1433 void mull(Register src); 1434 1435 // Multiply Scalar Double-Precision Floating-Point Values 1436 void mulsd(XMMRegister dst, Address src); 1437 void mulsd(XMMRegister dst, XMMRegister src); 1438 1439 // Multiply Scalar Single-Precision Floating-Point Values 1440 void mulss(XMMRegister dst, Address src); 1441 void mulss(XMMRegister dst, XMMRegister src); 1442 1443 void negl(Register dst); 1444 1445 #ifdef _LP64 1446 void negq(Register dst); 1447 #endif 1448 1449 void nop(int i = 1); 1450 1451 void notl(Register dst); 1452 1453 #ifdef _LP64 1454 void notq(Register dst); 1455 #endif 1456 1457 void orl(Address dst, int32_t imm32); 1458 void orl(Register dst, int32_t imm32); 1459 void orl(Register dst, Address src); 1460 void orl(Register dst, Register src); 1461 1462 void orq(Address dst, int32_t imm32); 1463 void orq(Register dst, int32_t imm32); 1464 void orq(Register dst, Address src); 1465 void orq(Register dst, Register src); 1466 1467 // Pack with unsigned saturation 1468 void packuswb(XMMRegister dst, XMMRegister src); 1469 void packuswb(XMMRegister dst, Address src); 1470 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1471 1472 // Pemutation of 64bit words 1473 void vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256); 1474 1475 void pause(); 1476 1477 // SSE4.2 string instructions 1478 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); 1479 void pcmpestri(XMMRegister xmm1, Address src, int imm8); 1480 1481 // SSE 4.1 extract 1482 void pextrd(Register dst, XMMRegister src, int imm8); 1483 void pextrq(Register dst, XMMRegister src, int imm8); 1484 1485 // SSE 4.1 insert 1486 void pinsrd(XMMRegister dst, Register src, int imm8); 1487 void pinsrq(XMMRegister dst, Register src, int imm8); 1488 1489 // SSE4.1 packed move 1490 void pmovzxbw(XMMRegister dst, XMMRegister src); 1491 void pmovzxbw(XMMRegister dst, Address src); 1492 1493 #ifndef _LP64 // no 32bit push/pop on amd64 1494 void popl(Address dst); 1495 #endif 1496 1497 #ifdef _LP64 1498 void popq(Address dst); 1499 #endif 1500 1501 void popcntl(Register dst, Address src); 1502 void popcntl(Register dst, Register src); 1503 1504 #ifdef _LP64 1505 void popcntq(Register dst, Address src); 1506 void popcntq(Register dst, Register src); 1507 #endif 1508 1509 // Prefetches (SSE, SSE2, 3DNOW only) 1510 1511 void prefetchnta(Address src); 1512 void prefetchr(Address src); 1513 void prefetcht0(Address src); 1514 void prefetcht1(Address src); 1515 void prefetcht2(Address src); 1516 void prefetchw(Address src); 1517 1518 // Shuffle Bytes 1519 void pshufb(XMMRegister dst, XMMRegister src); 1520 void pshufb(XMMRegister dst, Address src); 1521 1522 // Shuffle Packed Doublewords 1523 void pshufd(XMMRegister dst, XMMRegister src, int mode); 1524 void pshufd(XMMRegister dst, Address src, int mode); 1525 1526 // Shuffle Packed Low Words 1527 void pshuflw(XMMRegister dst, XMMRegister src, int mode); 1528 void pshuflw(XMMRegister dst, Address src, int mode); 1529 1530 // Shift Right by bytes Logical DoubleQuadword Immediate 1531 void psrldq(XMMRegister dst, int shift); 1532 1533 // Logical Compare 128bit 1534 void ptest(XMMRegister dst, XMMRegister src); 1535 void ptest(XMMRegister dst, Address src); 1536 // Logical Compare 256bit 1537 void vptest(XMMRegister dst, XMMRegister src); 1538 void vptest(XMMRegister dst, Address src); 1539 1540 // Interleave Low Bytes 1541 void punpcklbw(XMMRegister dst, XMMRegister src); 1542 void punpcklbw(XMMRegister dst, Address src); 1543 1544 // Interleave Low Doublewords 1545 void punpckldq(XMMRegister dst, XMMRegister src); 1546 void punpckldq(XMMRegister dst, Address src); 1547 1548 // Interleave Low Quadwords 1549 void punpcklqdq(XMMRegister dst, XMMRegister src); 1550 1551 #ifndef _LP64 // no 32bit push/pop on amd64 1552 void pushl(Address src); 1553 #endif 1554 1555 void pushq(Address src); 1556 1557 void rcll(Register dst, int imm8); 1558 1559 void rclq(Register dst, int imm8); 1560 1561 void rdtsc(); 1562 1563 void ret(int imm16); 1564 1565 void sahf(); 1566 1567 void sarl(Register dst, int imm8); 1568 void sarl(Register dst); 1569 1570 void sarq(Register dst, int imm8); 1571 void sarq(Register dst); 1572 1573 void sbbl(Address dst, int32_t imm32); 1574 void sbbl(Register dst, int32_t imm32); 1575 void sbbl(Register dst, Address src); 1576 void sbbl(Register dst, Register src); 1577 1578 void sbbq(Address dst, int32_t imm32); 1579 void sbbq(Register dst, int32_t imm32); 1580 void sbbq(Register dst, Address src); 1581 void sbbq(Register dst, Register src); 1582 1583 void setb(Condition cc, Register dst); 1584 1585 void shldl(Register dst, Register src); 1586 1587 void shll(Register dst, int imm8); 1588 void shll(Register dst); 1589 1590 void shlq(Register dst, int imm8); 1591 void shlq(Register dst); 1592 1593 void shrdl(Register dst, Register src); 1594 1595 void shrl(Register dst, int imm8); 1596 void shrl(Register dst); 1597 1598 void shrq(Register dst, int imm8); 1599 void shrq(Register dst); 1600 1601 void smovl(); // QQQ generic? 1602 1603 // Compute Square Root of Scalar Double-Precision Floating-Point Value 1604 void sqrtsd(XMMRegister dst, Address src); 1605 void sqrtsd(XMMRegister dst, XMMRegister src); 1606 1607 // Compute Square Root of Scalar Single-Precision Floating-Point Value 1608 void sqrtss(XMMRegister dst, Address src); 1609 void sqrtss(XMMRegister dst, XMMRegister src); 1610 1611 void std(); 1612 1613 void stmxcsr( Address dst ); 1614 1615 void subl(Address dst, int32_t imm32); 1616 void subl(Address dst, Register src); 1617 void subl(Register dst, int32_t imm32); 1618 void subl(Register dst, Address src); 1619 void subl(Register dst, Register src); 1620 1621 void subq(Address dst, int32_t imm32); 1622 void subq(Address dst, Register src); 1623 void subq(Register dst, int32_t imm32); 1624 void subq(Register dst, Address src); 1625 void subq(Register dst, Register src); 1626 1627 // Force generation of a 4 byte immediate value even if it fits into 8bit 1628 void subl_imm32(Register dst, int32_t imm32); 1629 void subq_imm32(Register dst, int32_t imm32); 1630 1631 // Subtract Scalar Double-Precision Floating-Point Values 1632 void subsd(XMMRegister dst, Address src); 1633 void subsd(XMMRegister dst, XMMRegister src); 1634 1635 // Subtract Scalar Single-Precision Floating-Point Values 1636 void subss(XMMRegister dst, Address src); 1637 void subss(XMMRegister dst, XMMRegister src); 1638 1639 void testb(Register dst, int imm8); 1640 1641 void testl(Register dst, int32_t imm32); 1642 void testl(Register dst, Register src); 1643 void testl(Register dst, Address src); 1644 1645 void testq(Register dst, int32_t imm32); 1646 void testq(Register dst, Register src); 1647 1648 // BMI - count trailing zeros 1649 void tzcntl(Register dst, Register src); 1650 void tzcntq(Register dst, Register src); 1651 1652 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 1653 void ucomisd(XMMRegister dst, Address src); 1654 void ucomisd(XMMRegister dst, XMMRegister src); 1655 1656 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 1657 void ucomiss(XMMRegister dst, Address src); 1658 void ucomiss(XMMRegister dst, XMMRegister src); 1659 1660 void xabort(int8_t imm8); 1661 1662 void xaddl(Address dst, Register src); 1663 1664 void xaddq(Address dst, Register src); 1665 1666 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none); 1667 1668 void xchgl(Register reg, Address adr); 1669 void xchgl(Register dst, Register src); 1670 1671 void xchgq(Register reg, Address adr); 1672 void xchgq(Register dst, Register src); 1673 1674 void xend(); 1675 1676 // Get Value of Extended Control Register 1677 void xgetbv(); 1678 1679 void xorl(Register dst, int32_t imm32); 1680 void xorl(Register dst, Address src); 1681 void xorl(Register dst, Register src); 1682 1683 void xorq(Register dst, Address src); 1684 void xorq(Register dst, Register src); 1685 1686 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 1687 1688 // AVX 3-operands scalar instructions (encoded with VEX prefix) 1689 1690 void vaddsd(XMMRegister dst, XMMRegister nds, Address src); 1691 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1692 void vaddss(XMMRegister dst, XMMRegister nds, Address src); 1693 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1694 void vdivsd(XMMRegister dst, XMMRegister nds, Address src); 1695 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1696 void vdivss(XMMRegister dst, XMMRegister nds, Address src); 1697 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1698 void vmulsd(XMMRegister dst, XMMRegister nds, Address src); 1699 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1700 void vmulss(XMMRegister dst, XMMRegister nds, Address src); 1701 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1702 void vsubsd(XMMRegister dst, XMMRegister nds, Address src); 1703 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1704 void vsubss(XMMRegister dst, XMMRegister nds, Address src); 1705 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1706 1707 1708 //====================VECTOR ARITHMETIC===================================== 1709 1710 // Add Packed Floating-Point Values 1711 void addpd(XMMRegister dst, XMMRegister src); 1712 void addps(XMMRegister dst, XMMRegister src); 1713 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1714 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1715 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1716 void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1717 1718 // Subtract Packed Floating-Point Values 1719 void subpd(XMMRegister dst, XMMRegister src); 1720 void subps(XMMRegister dst, XMMRegister src); 1721 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1722 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1723 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1724 void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1725 1726 // Multiply Packed Floating-Point Values 1727 void mulpd(XMMRegister dst, XMMRegister src); 1728 void mulps(XMMRegister dst, XMMRegister src); 1729 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1730 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1731 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1732 void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1733 1734 // Divide Packed Floating-Point Values 1735 void divpd(XMMRegister dst, XMMRegister src); 1736 void divps(XMMRegister dst, XMMRegister src); 1737 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1738 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1739 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1740 void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1741 1742 // Bitwise Logical AND of Packed Floating-Point Values 1743 void andpd(XMMRegister dst, XMMRegister src); 1744 void andps(XMMRegister dst, XMMRegister src); 1745 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1746 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1747 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1748 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1749 1750 // Bitwise Logical XOR of Packed Floating-Point Values 1751 void xorpd(XMMRegister dst, XMMRegister src); 1752 void xorps(XMMRegister dst, XMMRegister src); 1753 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1754 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1755 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1756 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1757 1758 // Add packed integers 1759 void paddb(XMMRegister dst, XMMRegister src); 1760 void paddw(XMMRegister dst, XMMRegister src); 1761 void paddd(XMMRegister dst, XMMRegister src); 1762 void paddq(XMMRegister dst, XMMRegister src); 1763 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1764 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1765 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1766 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1767 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1768 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1769 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1770 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1771 1772 // Sub packed integers 1773 void psubb(XMMRegister dst, XMMRegister src); 1774 void psubw(XMMRegister dst, XMMRegister src); 1775 void psubd(XMMRegister dst, XMMRegister src); 1776 void psubq(XMMRegister dst, XMMRegister src); 1777 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1778 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1779 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1780 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1781 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1782 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1783 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1784 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1785 1786 // Multiply packed integers (only shorts and ints) 1787 void pmullw(XMMRegister dst, XMMRegister src); 1788 void pmulld(XMMRegister dst, XMMRegister src); 1789 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1790 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1791 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1792 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1793 1794 // Shift left packed integers 1795 void psllw(XMMRegister dst, int shift); 1796 void pslld(XMMRegister dst, int shift); 1797 void psllq(XMMRegister dst, int shift); 1798 void psllw(XMMRegister dst, XMMRegister shift); 1799 void pslld(XMMRegister dst, XMMRegister shift); 1800 void psllq(XMMRegister dst, XMMRegister shift); 1801 void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1802 void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1803 void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1804 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1805 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1806 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1807 1808 // Logical shift right packed integers 1809 void psrlw(XMMRegister dst, int shift); 1810 void psrld(XMMRegister dst, int shift); 1811 void psrlq(XMMRegister dst, int shift); 1812 void psrlw(XMMRegister dst, XMMRegister shift); 1813 void psrld(XMMRegister dst, XMMRegister shift); 1814 void psrlq(XMMRegister dst, XMMRegister shift); 1815 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1816 void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1817 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1818 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1819 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1820 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1821 1822 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) 1823 void psraw(XMMRegister dst, int shift); 1824 void psrad(XMMRegister dst, int shift); 1825 void psraw(XMMRegister dst, XMMRegister shift); 1826 void psrad(XMMRegister dst, XMMRegister shift); 1827 void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1828 void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256); 1829 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1830 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); 1831 1832 // And packed integers 1833 void pand(XMMRegister dst, XMMRegister src); 1834 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1835 void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1836 1837 // Or packed integers 1838 void por(XMMRegister dst, XMMRegister src); 1839 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1840 void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1841 1842 // Xor packed integers 1843 void pxor(XMMRegister dst, XMMRegister src); 1844 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1845 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); 1846 1847 // Copy low 128bit into high 128bit of YMM registers. 1848 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src); 1849 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src); 1850 1851 // Load/store high 128bit of YMM registers which does not destroy other half. 1852 void vinsertf128h(XMMRegister dst, Address src); 1853 void vinserti128h(XMMRegister dst, Address src); 1854 void vextractf128h(Address dst, XMMRegister src); 1855 void vextracti128h(Address dst, XMMRegister src); 1856 1857 // duplicate 4-bytes integer data from src into 8 locations in dest 1858 void vpbroadcastd(XMMRegister dst, XMMRegister src); 1859 1860 // Carry-Less Multiplication Quadword 1861 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask); 1862 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask); 1863 1864 // AVX instruction which is used to clear upper 128 bits of YMM registers and 1865 // to avoid transaction penalty between AVX and SSE states. There is no 1866 // penalty if legacy SSE instructions are encoded using VEX prefix because 1867 // they always clear upper 128 bits. It should be used before calling 1868 // runtime code and native libraries. 1869 void vzeroupper(); 1870 1871 protected: 1872 // Next instructions require address alignment 16 bytes SSE mode. 1873 // They should be called only from corresponding MacroAssembler instructions. 1874 void andpd(XMMRegister dst, Address src); 1875 void andps(XMMRegister dst, Address src); 1876 void xorpd(XMMRegister dst, Address src); 1877 void xorps(XMMRegister dst, Address src); 1878 1879 }; 1880 1881 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP