289 LRG& lrg = lrgs(lid);
290 const RegMask& rm = lrg.mask();
291 IndexSetIterator elements(liveout);
292 uint interfering_lid = elements.next();
293 while (interfering_lid != 0) {
294 LRG& interfering_lrg = lrgs(interfering_lid);
295 if (rm.overlap(interfering_lrg.mask())) {
296 _ifg->add_edge(lid, interfering_lid);
297 }
298 interfering_lid = elements.next();
299 }
300 }
301
302 // Actually build the interference graph. Uses virtual registers only, no
303 // physical register masks. This allows me to be very aggressive when
304 // coalescing copies. Some of this aggressiveness will have to be undone
305 // later, but I'd rather get all the copies I can now (since unremoved copies
306 // at this point can end up in bad places). Copies I re-insert later I have
307 // more opportunity to insert them in low-frequency locations.
308 void PhaseChaitin::build_ifg_virtual( ) {
309
310 // For all blocks (in any order) do...
311 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
312 Block* block = _cfg.get_block(i);
313 IndexSet* liveout = _live->live(block);
314
315 // The IFG is built by a single reverse pass over each basic block.
316 // Starting with the known live-out set, we remove things that get
317 // defined and add things that become live (essentially executing one
318 // pass of a standard LIVE analysis). Just before a Node defines a value
319 // (and removes it from the live-ness set) that value is certainly live.
320 // The defined value interferes with everything currently live. The
321 // value is then removed from the live-ness set and it's inputs are
322 // added to the live-ness set.
323 for (uint j = block->end_idx() + 1; j > 1; j--) {
324 Node* n = block->get_node(j - 1);
325
326 // Get value being defined
327 uint r = _lrg_map.live_range_id(n);
328
722 }
723 }
724 block_hrp_index = i;
725 }
726
727 /* Build an interference graph:
728 * That is, if 2 live ranges are simultaneously alive but in their acceptable
729 * register sets do not overlap, then they do not interfere. The IFG is built
730 * by a single reverse pass over each basic block. Starting with the known
731 * live-out set, we remove things that get defined and add things that become
732 * live (essentially executing one pass of a standard LIVE analysis). Just
733 * before a Node defines a value (and removes it from the live-ness set) that
734 * value is certainly live. The defined value interferes with everything
735 * currently live. The value is then removed from the live-ness set and it's
736 * inputs are added to the live-ness set.
737 * Compute register pressure for each block:
738 * We store the biggest register pressure for each block and also the first
739 * low to high register pressure transition within the block (if any).
740 */
741 uint PhaseChaitin::build_ifg_physical( ResourceArea *a ) {
742 NOT_PRODUCT(Compile::TracePhase t3("buildIFG", &_t_buildIFGphysical, TimeCompiler);)
743
744 uint must_spill = 0;
745 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
746 Block* block = _cfg.get_block(i);
747
748 // Clone (rather than smash in place) the liveout info, so it is alive
749 // for the "collect_gc_info" phase later.
750 IndexSet liveout(_live->live(block));
751
752 uint first_inst = first_nonphi_index(block);
753 uint last_inst = block->end_idx();
754
755 move_exception_node_up(block, first_inst, last_inst);
756
757 Pressure int_pressure(last_inst + 1, INTPRESSURE);
758 Pressure float_pressure(last_inst + 1, FLOATPRESSURE);
759 block->_reg_pressure = 0;
760 block->_freg_pressure = 0;
761
762 int inst_count = last_inst - first_inst;
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289 LRG& lrg = lrgs(lid);
290 const RegMask& rm = lrg.mask();
291 IndexSetIterator elements(liveout);
292 uint interfering_lid = elements.next();
293 while (interfering_lid != 0) {
294 LRG& interfering_lrg = lrgs(interfering_lid);
295 if (rm.overlap(interfering_lrg.mask())) {
296 _ifg->add_edge(lid, interfering_lid);
297 }
298 interfering_lid = elements.next();
299 }
300 }
301
302 // Actually build the interference graph. Uses virtual registers only, no
303 // physical register masks. This allows me to be very aggressive when
304 // coalescing copies. Some of this aggressiveness will have to be undone
305 // later, but I'd rather get all the copies I can now (since unremoved copies
306 // at this point can end up in bad places). Copies I re-insert later I have
307 // more opportunity to insert them in low-frequency locations.
308 void PhaseChaitin::build_ifg_virtual( ) {
309 Compile::TracePhase t3("buildIFG_virt", &timers[_t_buildIFGvirtual]);
310
311 // For all blocks (in any order) do...
312 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
313 Block* block = _cfg.get_block(i);
314 IndexSet* liveout = _live->live(block);
315
316 // The IFG is built by a single reverse pass over each basic block.
317 // Starting with the known live-out set, we remove things that get
318 // defined and add things that become live (essentially executing one
319 // pass of a standard LIVE analysis). Just before a Node defines a value
320 // (and removes it from the live-ness set) that value is certainly live.
321 // The defined value interferes with everything currently live. The
322 // value is then removed from the live-ness set and it's inputs are
323 // added to the live-ness set.
324 for (uint j = block->end_idx() + 1; j > 1; j--) {
325 Node* n = block->get_node(j - 1);
326
327 // Get value being defined
328 uint r = _lrg_map.live_range_id(n);
329
723 }
724 }
725 block_hrp_index = i;
726 }
727
728 /* Build an interference graph:
729 * That is, if 2 live ranges are simultaneously alive but in their acceptable
730 * register sets do not overlap, then they do not interfere. The IFG is built
731 * by a single reverse pass over each basic block. Starting with the known
732 * live-out set, we remove things that get defined and add things that become
733 * live (essentially executing one pass of a standard LIVE analysis). Just
734 * before a Node defines a value (and removes it from the live-ness set) that
735 * value is certainly live. The defined value interferes with everything
736 * currently live. The value is then removed from the live-ness set and it's
737 * inputs are added to the live-ness set.
738 * Compute register pressure for each block:
739 * We store the biggest register pressure for each block and also the first
740 * low to high register pressure transition within the block (if any).
741 */
742 uint PhaseChaitin::build_ifg_physical( ResourceArea *a ) {
743 Compile::TracePhase t3("buildIFG", &timers[_t_buildIFGphysical]);
744
745 uint must_spill = 0;
746 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
747 Block* block = _cfg.get_block(i);
748
749 // Clone (rather than smash in place) the liveout info, so it is alive
750 // for the "collect_gc_info" phase later.
751 IndexSet liveout(_live->live(block));
752
753 uint first_inst = first_nonphi_index(block);
754 uint last_inst = block->end_idx();
755
756 move_exception_node_up(block, first_inst, last_inst);
757
758 Pressure int_pressure(last_inst + 1, INTPRESSURE);
759 Pressure float_pressure(last_inst + 1, FLOATPRESSURE);
760 block->_reg_pressure = 0;
761 block->_freg_pressure = 0;
762
763 int inst_count = last_inst - first_inst;
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