1 /*
2 * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "compiler/compileLog.hpp"
27 #include "compiler/oopMap.hpp"
28 #include "memory/allocation.inline.hpp"
29 #include "opto/addnode.hpp"
30 #include "opto/block.hpp"
31 #include "opto/callnode.hpp"
32 #include "opto/cfgnode.hpp"
33 #include "opto/chaitin.hpp"
34 #include "opto/coalesce.hpp"
35 #include "opto/connode.hpp"
36 #include "opto/idealGraphPrinter.hpp"
37 #include "opto/indexSet.hpp"
38 #include "opto/machnode.hpp"
39 #include "opto/memnode.hpp"
40 #include "opto/movenode.hpp"
41 #include "opto/opcodes.hpp"
42 #include "opto/rootnode.hpp"
43
44 #ifndef PRODUCT
45 void LRG::dump() const {
46 ttyLocker ttyl;
47 tty->print("%d ",num_regs());
48 _mask.dump();
49 if( _msize_valid ) {
50 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
51 else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());
52 } else {
53 tty->print(", #?(%d) ",_mask.Size());
54 }
55
56 tty->print("EffDeg: ");
57 if( _degree_valid ) tty->print( "%d ", _eff_degree );
58 else tty->print("? ");
59
60 if( is_multidef() ) {
61 tty->print("MultiDef ");
62 if (_defs != NULL) {
63 tty->print("(");
64 for (int i = 0; i < _defs->length(); i++) {
65 tty->print("N%d ", _defs->at(i)->_idx);
66 }
67 tty->print(") ");
68 }
69 }
70 else if( _def == 0 ) tty->print("Dead ");
71 else tty->print("Def: N%d ",_def->_idx);
72
73 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
74 // Flags
75 if( _is_oop ) tty->print("Oop ");
76 if( _is_float ) tty->print("Float ");
77 if( _is_vector ) tty->print("Vector ");
78 if( _was_spilled1 ) tty->print("Spilled ");
79 if( _was_spilled2 ) tty->print("Spilled2 ");
80 if( _direct_conflict ) tty->print("Direct_conflict ");
81 if( _fat_proj ) tty->print("Fat ");
82 if( _was_lo ) tty->print("Lo ");
83 if( _has_copy ) tty->print("Copy ");
84 if( _at_risk ) tty->print("Risk ");
85
86 if( _must_spill ) tty->print("Must_spill ");
87 if( _is_bound ) tty->print("Bound ");
88 if( _msize_valid ) {
89 if( _degree_valid && lo_degree() ) tty->print("Trivial ");
90 }
91
92 tty->cr();
93 }
94 #endif
95
96 // Compute score from cost and area. Low score is best to spill.
97 static double raw_score( double cost, double area ) {
98 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
99 }
100
101 double LRG::score() const {
102 // Scale _area by RegisterCostAreaRatio/64K then subtract from cost.
103 // Bigger area lowers score, encourages spilling this live range.
104 // Bigger cost raise score, prevents spilling this live range.
105 // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer
106 // to turn a divide by a constant into a multiply by the reciprical).
107 double score = raw_score( _cost, _area);
108
109 // Account for area. Basically, LRGs covering large areas are better
110 // to spill because more other LRGs get freed up.
111 if( _area == 0.0 ) // No area? Then no progress to spill
112 return 1e35;
113
114 if( _was_spilled2 ) // If spilled once before, we are unlikely
115 return score + 1e30; // to make progress again.
116
117 if( _cost >= _area*3.0 ) // Tiny area relative to cost
118 return score + 1e17; // Probably no progress to spill
119
120 if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost
121 return score + 1e10; // Likely no progress to spill
122
123 return score;
124 }
125
126 #define NUMBUCKS 3
127
128 // Straight out of Tarjan's union-find algorithm
129 uint LiveRangeMap::find_compress(uint lrg) {
130 uint cur = lrg;
131 uint next = _uf_map.at(cur);
132 while (next != cur) { // Scan chain of equivalences
133 assert( next < cur, "always union smaller");
134 cur = next; // until find a fixed-point
135 next = _uf_map.at(cur);
136 }
137
138 // Core of union-find algorithm: update chain of
139 // equivalences to be equal to the root.
140 while (lrg != next) {
141 uint tmp = _uf_map.at(lrg);
142 _uf_map.at_put(lrg, next);
143 lrg = tmp;
144 }
145 return lrg;
146 }
147
148 // Reset the Union-Find map to identity
149 void LiveRangeMap::reset_uf_map(uint max_lrg_id) {
150 _max_lrg_id= max_lrg_id;
151 // Force the Union-Find mapping to be at least this large
152 _uf_map.at_put_grow(_max_lrg_id, 0);
153 // Initialize it to be the ID mapping.
154 for (uint i = 0; i < _max_lrg_id; ++i) {
155 _uf_map.at_put(i, i);
156 }
157 }
158
159 // Make all Nodes map directly to their final live range; no need for
160 // the Union-Find mapping after this call.
161 void LiveRangeMap::compress_uf_map_for_nodes() {
162 // For all Nodes, compress mapping
163 uint unique = _names.length();
164 for (uint i = 0; i < unique; ++i) {
165 uint lrg = _names.at(i);
166 uint compressed_lrg = find(lrg);
167 if (lrg != compressed_lrg) {
168 _names.at_put(i, compressed_lrg);
169 }
170 }
171 }
172
173 // Like Find above, but no path compress, so bad asymptotic behavior
174 uint LiveRangeMap::find_const(uint lrg) const {
175 if (!lrg) {
176 return lrg; // Ignore the zero LRG
177 }
178
179 // Off the end? This happens during debugging dumps when you got
180 // brand new live ranges but have not told the allocator yet.
181 if (lrg >= _max_lrg_id) {
182 return lrg;
183 }
184
185 uint next = _uf_map.at(lrg);
186 while (next != lrg) { // Scan chain of equivalences
187 assert(next < lrg, "always union smaller");
188 lrg = next; // until find a fixed-point
189 next = _uf_map.at(lrg);
190 }
191 return next;
192 }
193
194 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher)
195 : PhaseRegAlloc(unique, cfg, matcher,
196 #ifndef PRODUCT
197 print_chaitin_statistics
198 #else
199 NULL
200 #endif
201 )
202 , _lrg_map(Thread::current()->resource_area(), unique)
203 , _live(0)
204 , _spilled_once(Thread::current()->resource_area())
205 , _spilled_twice(Thread::current()->resource_area())
206 , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0)
207 , _oldphi(unique)
208 #ifndef PRODUCT
209 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling"))
210 #endif
211 {
212 Compile::TracePhase tp("ctorChaitin", &timers[_t_ctorChaitin]);
213
214 _high_frequency_lrg = MIN2(double(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency());
215
216 // Build a list of basic blocks, sorted by frequency
217 _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
218 // Experiment with sorting strategies to speed compilation
219 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
220 Block **buckets[NUMBUCKS]; // Array of buckets
221 uint buckcnt[NUMBUCKS]; // Array of bucket counters
222 double buckval[NUMBUCKS]; // Array of bucket value cutoffs
223 for (uint i = 0; i < NUMBUCKS; i++) {
224 buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
225 buckcnt[i] = 0;
226 // Bump by three orders of magnitude each time
227 cutoff *= 0.001;
228 buckval[i] = cutoff;
229 for (uint j = 0; j < _cfg.number_of_blocks(); j++) {
230 buckets[i][j] = NULL;
231 }
232 }
233 // Sort blocks into buckets
234 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
235 for (uint j = 0; j < NUMBUCKS; j++) {
236 if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) {
237 // Assign block to end of list for appropriate bucket
238 buckets[j][buckcnt[j]++] = _cfg.get_block(i);
239 break; // kick out of inner loop
240 }
241 }
242 }
243 // Dump buckets into final block array
244 uint blkcnt = 0;
245 for (uint i = 0; i < NUMBUCKS; i++) {
246 for (uint j = 0; j < buckcnt[i]; j++) {
247 _blks[blkcnt++] = buckets[i][j];
248 }
249 }
250
251 assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled");
252 }
253
254 // union 2 sets together.
255 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) {
256 uint src = _lrg_map.find(src_n);
257 uint dst = _lrg_map.find(dst_n);
258 assert(src, "");
259 assert(dst, "");
260 assert(src < _lrg_map.max_lrg_id(), "oob");
261 assert(dst < _lrg_map.max_lrg_id(), "oob");
262 assert(src < dst, "always union smaller");
263 _lrg_map.uf_map(dst, src);
264 }
265
266 void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
267 // Make the Node->LRG mapping
268 _lrg_map.extend(x->_idx,lrg);
269 // Make the Union-Find mapping an identity function
270 _lrg_map.uf_extend(lrg, lrg);
271 }
272
273
274 int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) {
275 assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections");
276 DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); )
277 int found_projs = 0;
278 uint cnt = orig->outcnt();
279 for (uint i = 0; i < cnt; i++) {
280 Node* proj = orig->raw_out(i);
281 if (proj->is_MachProj()) {
282 assert(proj->outcnt() == 0, "only kill projections are expected here");
283 assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections");
284 found_projs++;
285 // Copy kill projections after the cloned node
286 Node* kills = proj->clone();
287 kills->set_req(0, copy);
288 b->insert_node(kills, idx++);
289 _cfg.map_node_to_block(kills, b);
290 new_lrg(kills, max_lrg_id++);
291 }
292 }
293 return found_projs;
294 }
295
296 // Renumber the live ranges to compact them. Makes the IFG smaller.
297 void PhaseChaitin::compact() {
298 Compile::TracePhase tp("chaitinCompact", &timers[_t_chaitinCompact]);
299
300 // Current the _uf_map contains a series of short chains which are headed
301 // by a self-cycle. All the chains run from big numbers to little numbers.
302 // The Find() call chases the chains & shortens them for the next Find call.
303 // We are going to change this structure slightly. Numbers above a moving
304 // wave 'i' are unchanged. Numbers below 'j' point directly to their
305 // compacted live range with no further chaining. There are no chains or
306 // cycles below 'i', so the Find call no longer works.
307 uint j=1;
308 uint i;
309 for (i = 1; i < _lrg_map.max_lrg_id(); i++) {
310 uint lr = _lrg_map.uf_live_range_id(i);
311 // Ignore unallocated live ranges
312 if (!lr) {
313 continue;
314 }
315 assert(lr <= i, "");
316 _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr));
317 }
318 // Now change the Node->LR mapping to reflect the compacted names
319 uint unique = _lrg_map.size();
320 for (i = 0; i < unique; i++) {
321 uint lrg_id = _lrg_map.live_range_id(i);
322 _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id));
323 }
324
325 // Reset the Union-Find mapping
326 _lrg_map.reset_uf_map(j);
327 }
328
329 void PhaseChaitin::Register_Allocate() {
330
331 // Above the OLD FP (and in registers) are the incoming arguments. Stack
332 // slots in this area are called "arg_slots". Above the NEW FP (and in
333 // registers) is the outgoing argument area; above that is the spill/temp
334 // area. These are all "frame_slots". Arg_slots start at the zero
335 // stack_slots and count up to the known arg_size. Frame_slots start at
336 // the stack_slot #arg_size and go up. After allocation I map stack
337 // slots to actual offsets. Stack-slots in the arg_slot area are biased
338 // by the frame_size; stack-slots in the frame_slot area are biased by 0.
339
340 _trip_cnt = 0;
341 _alternate = 0;
342 _matcher._allocation_started = true;
343
344 ResourceArea split_arena; // Arena for Split local resources
345 ResourceArea live_arena; // Arena for liveness & IFG info
346 ResourceMark rm(&live_arena);
347
348 // Need live-ness for the IFG; need the IFG for coalescing. If the
349 // liveness is JUST for coalescing, then I can get some mileage by renaming
350 // all copy-related live ranges low and then using the max copy-related
351 // live range as a cut-off for LIVE and the IFG. In other words, I can
352 // build a subset of LIVE and IFG just for copies.
353 PhaseLive live(_cfg, _lrg_map.names(), &live_arena);
354
355 // Need IFG for coalescing and coloring
356 PhaseIFG ifg(&live_arena);
357 _ifg = &ifg;
358
359 // Come out of SSA world to the Named world. Assign (virtual) registers to
360 // Nodes. Use the same register for all inputs and the output of PhiNodes
361 // - effectively ending SSA form. This requires either coalescing live
362 // ranges or inserting copies. For the moment, we insert "virtual copies"
363 // - we pretend there is a copy prior to each Phi in predecessor blocks.
364 // We will attempt to coalesce such "virtual copies" before we manifest
365 // them for real.
366 de_ssa();
367
368 #ifdef ASSERT
369 // Veify the graph before RA.
370 verify(&live_arena);
371 #endif
372
373 {
374 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
375 _live = NULL; // Mark live as being not available
376 rm.reset_to_mark(); // Reclaim working storage
377 ifg.init(_lrg_map.max_lrg_id()); // Empty IFG
378 gather_lrg_masks( false ); // Collect LRG masks
379 live.compute(_lrg_map.max_lrg_id()); // Compute liveness
380 _live = &live; // Mark LIVE as being available
381 }
382
383 // Base pointers are currently "used" by instructions which define new
384 // derived pointers. This makes base pointers live up to the where the
385 // derived pointer is made, but not beyond. Really, they need to be live
386 // across any GC point where the derived value is live. So this code looks
387 // at all the GC points, and "stretches" the live range of any base pointer
388 // to the GC point.
389 if (stretch_base_pointer_live_ranges(&live_arena)) {
390 Compile::TracePhase tp("computeLive (sbplr)", &timers[_t_computeLive]);
391 // Since some live range stretched, I need to recompute live
392 _live = NULL;
393 rm.reset_to_mark(); // Reclaim working storage
394 ifg.init(_lrg_map.max_lrg_id());
395 gather_lrg_masks(false);
396 live.compute(_lrg_map.max_lrg_id());
397 _live = &live;
398 }
399 // Create the interference graph using virtual copies
400 build_ifg_virtual(); // Include stack slots this time
401
402 // The IFG is/was triangular. I am 'squaring it up' so Union can run
403 // faster. Union requires a 'for all' operation which is slow on the
404 // triangular adjacency matrix (quick reminder: the IFG is 'sparse' -
405 // meaning I can visit all the Nodes neighbors less than a Node in time
406 // O(# of neighbors), but I have to visit all the Nodes greater than a
407 // given Node and search them for an instance, i.e., time O(#MaxLRG)).
408 _ifg->SquareUp();
409
410 // Aggressive (but pessimistic) copy coalescing.
411 // This pass works on virtual copies. Any virtual copies which are not
412 // coalesced get manifested as actual copies
413 {
414 Compile::TracePhase tp("chaitinCoalesce1", &timers[_t_chaitinCoalesce1]);
415
416 PhaseAggressiveCoalesce coalesce(*this);
417 coalesce.coalesce_driver();
418 // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do
419 // not match the Phi itself, insert a copy.
420 coalesce.insert_copies(_matcher);
421 if (C->failing()) {
422 return;
423 }
424 }
425
426 // After aggressive coalesce, attempt a first cut at coloring.
427 // To color, we need the IFG and for that we need LIVE.
428 {
429 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
430 _live = NULL;
431 rm.reset_to_mark(); // Reclaim working storage
432 ifg.init(_lrg_map.max_lrg_id());
433 gather_lrg_masks( true );
434 live.compute(_lrg_map.max_lrg_id());
435 _live = &live;
436 }
437
438 // Build physical interference graph
439 uint must_spill = 0;
440 must_spill = build_ifg_physical(&live_arena);
441 // If we have a guaranteed spill, might as well spill now
442 if (must_spill) {
443 if(!_lrg_map.max_lrg_id()) {
444 return;
445 }
446 // Bail out if unique gets too large (ie - unique > MaxNodeLimit)
447 C->check_node_count(10*must_spill, "out of nodes before split");
448 if (C->failing()) {
449 return;
450 }
451
452 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere
453 _lrg_map.set_max_lrg_id(new_max_lrg_id);
454 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
455 // or we failed to split
456 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");
457 if (C->failing()) {
458 return;
459 }
460
461 NOT_PRODUCT(C->verify_graph_edges();)
462
463 compact(); // Compact LRGs; return new lower max lrg
464
465 {
466 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
467 _live = NULL;
468 rm.reset_to_mark(); // Reclaim working storage
469 ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph
470 gather_lrg_masks( true ); // Collect intersect mask
471 live.compute(_lrg_map.max_lrg_id()); // Compute LIVE
472 _live = &live;
473 }
474 build_ifg_physical(&live_arena);
475 _ifg->SquareUp();
476 _ifg->Compute_Effective_Degree();
477 // Only do conservative coalescing if requested
478 if (OptoCoalesce) {
479 Compile::TracePhase tp("chaitinCoalesce2", &timers[_t_chaitinCoalesce2]);
480 // Conservative (and pessimistic) copy coalescing of those spills
481 PhaseConservativeCoalesce coalesce(*this);
482 // If max live ranges greater than cutoff, don't color the stack.
483 // This cutoff can be larger than below since it is only done once.
484 coalesce.coalesce_driver();
485 }
486 _lrg_map.compress_uf_map_for_nodes();
487
488 #ifdef ASSERT
489 verify(&live_arena, true);
490 #endif
491 } else {
492 ifg.SquareUp();
493 ifg.Compute_Effective_Degree();
494 #ifdef ASSERT
495 set_was_low();
496 #endif
497 }
498
499 // Prepare for Simplify & Select
500 cache_lrg_info(); // Count degree of LRGs
501
502 // Simplify the InterFerence Graph by removing LRGs of low degree.
503 // LRGs of low degree are trivially colorable.
504 Simplify();
505
506 // Select colors by re-inserting LRGs back into the IFG in reverse order.
507 // Return whether or not something spills.
508 uint spills = Select( );
509
510 // If we spill, split and recycle the entire thing
511 while( spills ) {
512 if( _trip_cnt++ > 24 ) {
513 DEBUG_ONLY( dump_for_spill_split_recycle(); )
514 if( _trip_cnt > 27 ) {
515 C->record_method_not_compilable("failed spill-split-recycle sanity check");
516 return;
517 }
518 }
519
520 if (!_lrg_map.max_lrg_id()) {
521 return;
522 }
523 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere
524 _lrg_map.set_max_lrg_id(new_max_lrg_id);
525 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
526 C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split");
527 if (C->failing()) {
528 return;
529 }
530
531 compact(); // Compact LRGs; return new lower max lrg
532
533 // Nuke the live-ness and interference graph and LiveRanGe info
534 {
535 Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
536 _live = NULL;
537 rm.reset_to_mark(); // Reclaim working storage
538 ifg.init(_lrg_map.max_lrg_id());
539
540 // Create LiveRanGe array.
541 // Intersect register masks for all USEs and DEFs
542 gather_lrg_masks(true);
543 live.compute(_lrg_map.max_lrg_id());
544 _live = &live;
545 }
546 must_spill = build_ifg_physical(&live_arena);
547 _ifg->SquareUp();
548 _ifg->Compute_Effective_Degree();
549
550 // Only do conservative coalescing if requested
551 if (OptoCoalesce) {
552 Compile::TracePhase tp("chaitinCoalesce3", &timers[_t_chaitinCoalesce3]);
553 // Conservative (and pessimistic) copy coalescing
554 PhaseConservativeCoalesce coalesce(*this);
555 // Check for few live ranges determines how aggressive coalesce is.
556 coalesce.coalesce_driver();
557 }
558 _lrg_map.compress_uf_map_for_nodes();
559 #ifdef ASSERT
560 verify(&live_arena, true);
561 #endif
562 cache_lrg_info(); // Count degree of LRGs
563
564 // Simplify the InterFerence Graph by removing LRGs of low degree.
565 // LRGs of low degree are trivially colorable.
566 Simplify();
567
568 // Select colors by re-inserting LRGs back into the IFG in reverse order.
569 // Return whether or not something spills.
570 spills = Select();
571 }
572
573 // Count number of Simplify-Select trips per coloring success.
574 _allocator_attempts += _trip_cnt + 1;
575 _allocator_successes += 1;
576
577 // Peephole remove copies
578 post_allocate_copy_removal();
579
580 #ifdef ASSERT
581 // Veify the graph after RA.
582 verify(&live_arena);
583 #endif
584
585 // max_reg is past the largest *register* used.
586 // Convert that to a frame_slot number.
587 if (_max_reg <= _matcher._new_SP) {
588 _framesize = C->out_preserve_stack_slots();
589 }
590 else {
591 _framesize = _max_reg -_matcher._new_SP;
592 }
593 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
594
595 // This frame must preserve the required fp alignment
596 _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots());
597 assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" );
598 #ifndef PRODUCT
599 _total_framesize += _framesize;
600 if ((int)_framesize > _max_framesize) {
601 _max_framesize = _framesize;
602 }
603 #endif
604
605 // Convert CISC spills
606 fixup_spills();
607
608 // Log regalloc results
609 CompileLog* log = Compile::current()->log();
610 if (log != NULL) {
611 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
612 }
613
614 if (C->failing()) {
615 return;
616 }
617
618 NOT_PRODUCT(C->verify_graph_edges();)
619
620 // Move important info out of the live_arena to longer lasting storage.
621 alloc_node_regs(_lrg_map.size());
622 for (uint i=0; i < _lrg_map.size(); i++) {
623 if (_lrg_map.live_range_id(i)) { // Live range associated with Node?
624 LRG &lrg = lrgs(_lrg_map.live_range_id(i));
625 if (!lrg.alive()) {
626 set_bad(i);
627 } else if (lrg.num_regs() == 1) {
628 set1(i, lrg.reg());
629 } else { // Must be a register-set
630 if (!lrg._fat_proj) { // Must be aligned adjacent register set
631 // Live ranges record the highest register in their mask.
632 // We want the low register for the AD file writer's convenience.
633 OptoReg::Name hi = lrg.reg(); // Get hi register
634 OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo
635 // We have to use pair [lo,lo+1] even for wide vectors because
636 // the rest of code generation works only with pairs. It is safe
637 // since for registers encoding only 'lo' is used.
638 // Second reg from pair is used in ScheduleAndBundle on SPARC where
639 // vector max size is 8 which corresponds to registers pair.
640 // It is also used in BuildOopMaps but oop operations are not
641 // vectorized.
642 set2(i, lo);
643 } else { // Misaligned; extract 2 bits
644 OptoReg::Name hi = lrg.reg(); // Get hi register
645 lrg.Remove(hi); // Yank from mask
646 int lo = lrg.mask().find_first_elem(); // Find lo
647 set_pair(i, hi, lo);
648 }
649 }
650 if( lrg._is_oop ) _node_oops.set(i);
651 } else {
652 set_bad(i);
653 }
654 }
655
656 // Done!
657 _live = NULL;
658 _ifg = NULL;
659 }
660
661 void PhaseChaitin::de_ssa() {
662 // Set initial Names for all Nodes. Most Nodes get the virtual register
663 // number. A few get the ZERO live range number. These do not
664 // get allocated, but instead rely on correct scheduling to ensure that
665 // only one instance is simultaneously live at a time.
666 uint lr_counter = 1;
667 for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
668 Block* block = _cfg.get_block(i);
669 uint cnt = block->number_of_nodes();
670
671 // Handle all the normal Nodes in the block
672 for( uint j = 0; j < cnt; j++ ) {
673 Node *n = block->get_node(j);
674 // Pre-color to the zero live range, or pick virtual register
675 const RegMask &rm = n->out_RegMask();
676 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0);
677 }
678 }
679
680 // Reset the Union-Find mapping to be identity
681 _lrg_map.reset_uf_map(lr_counter);
682 }
683
684
685 // Gather LiveRanGe information, including register masks. Modification of
686 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
687 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
688
689 // Nail down the frame pointer live range
690 uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr));
691 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite
692
693 // For all blocks
694 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
695 Block* block = _cfg.get_block(i);
696
697 // For all instructions
698 for (uint j = 1; j < block->number_of_nodes(); j++) {
699 Node* n = block->get_node(j);
700 uint input_edge_start =1; // Skip control most nodes
701 if (n->is_Mach()) {
702 input_edge_start = n->as_Mach()->oper_input_base();
703 }
704 uint idx = n->is_Copy();
705
706 // Get virtual register number, same as LiveRanGe index
707 uint vreg = _lrg_map.live_range_id(n);
708 LRG& lrg = lrgs(vreg);
709 if (vreg) { // No vreg means un-allocable (e.g. memory)
710
711 // Collect has-copy bit
712 if (idx) {
713 lrg._has_copy = 1;
714 uint clidx = _lrg_map.live_range_id(n->in(idx));
715 LRG& copy_src = lrgs(clidx);
716 copy_src._has_copy = 1;
717 }
718
719 // Check for float-vs-int live range (used in register-pressure
720 // calculations)
721 const Type *n_type = n->bottom_type();
722 if (n_type->is_floatingpoint()) {
723 lrg._is_float = 1;
724 }
725
726 // Check for twice prior spilling. Once prior spilling might have
727 // spilled 'soft', 2nd prior spill should have spilled 'hard' and
728 // further spilling is unlikely to make progress.
729 if (_spilled_once.test(n->_idx)) {
730 lrg._was_spilled1 = 1;
731 if (_spilled_twice.test(n->_idx)) {
732 lrg._was_spilled2 = 1;
733 }
734 }
735
736 #ifndef PRODUCT
737 if (trace_spilling() && lrg._def != NULL) {
738 // collect defs for MultiDef printing
739 if (lrg._defs == NULL) {
740 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
741 lrg._defs->append(lrg._def);
742 }
743 lrg._defs->append(n);
744 }
745 #endif
746
747 // Check for a single def LRG; these can spill nicely
748 // via rematerialization. Flag as NULL for no def found
749 // yet, or 'n' for single def or -1 for many defs.
750 lrg._def = lrg._def ? NodeSentinel : n;
751
752 // Limit result register mask to acceptable registers
753 const RegMask &rm = n->out_RegMask();
754 lrg.AND( rm );
755
756 int ireg = n->ideal_reg();
757 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
758 "oops must be in Op_RegP's" );
759
760 // Check for vector live range (only if vector register is used).
761 // On SPARC vector uses RegD which could be misaligned so it is not
762 // processes as vector in RA.
763 if (RegMask::is_vector(ireg))
764 lrg._is_vector = 1;
765 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL,
766 "vector must be in vector registers");
767
768 // Check for bound register masks
769 const RegMask &lrgmask = lrg.mask();
770 if (lrgmask.is_bound(ireg)) {
771 lrg._is_bound = 1;
772 }
773
774 // Check for maximum frequency value
775 if (lrg._maxfreq < block->_freq) {
776 lrg._maxfreq = block->_freq;
777 }
778
779 // Check for oop-iness, or long/double
780 // Check for multi-kill projection
781 switch (ireg) {
782 case MachProjNode::fat_proj:
783 // Fat projections have size equal to number of registers killed
784 lrg.set_num_regs(rm.Size());
785 lrg.set_reg_pressure(lrg.num_regs());
786 lrg._fat_proj = 1;
787 lrg._is_bound = 1;
788 break;
789 case Op_RegP:
790 #ifdef _LP64
791 lrg.set_num_regs(2); // Size is 2 stack words
792 #else
793 lrg.set_num_regs(1); // Size is 1 stack word
794 #endif
795 // Register pressure is tracked relative to the maximum values
796 // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
797 // and relative to other types which compete for the same regs.
798 //
799 // The following table contains suggested values based on the
800 // architectures as defined in each .ad file.
801 // INTPRESSURE and FLOATPRESSURE may be tuned differently for
802 // compile-speed or performance.
803 // Note1:
804 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
805 // since .ad registers are defined as high and low halves.
806 // These reg_pressure values remain compatible with the code
807 // in is_high_pressure() which relates get_invalid_mask_size(),
808 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
809 // Note2:
810 // SPARC -d32 has 24 registers available for integral values,
811 // but only 10 of these are safe for 64-bit longs.
812 // Using set_reg_pressure(2) for both int and long means
813 // the allocator will believe it can fit 26 longs into
814 // registers. Using 2 for longs and 1 for ints means the
815 // allocator will attempt to put 52 integers into registers.
816 // The settings below limit this problem to methods with
817 // many long values which are being run on 32-bit SPARC.
818 //
819 // ------------------- reg_pressure --------------------
820 // Each entry is reg_pressure_per_value,number_of_regs
821 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
822 // IA32 2 1 1 1 1 6 6
823 // IA64 1 1 1 1 1 50 41
824 // SPARC 2 2 2 2 2 48 (24) 52 (26)
825 // SPARCV9 2 2 2 2 2 48 (24) 52 (26)
826 // AMD64 1 1 1 1 1 14 15
827 // -----------------------------------------------------
828 #if defined(SPARC)
829 lrg.set_reg_pressure(2); // use for v9 as well
830 #else
831 lrg.set_reg_pressure(1); // normally one value per register
832 #endif
833 if( n_type->isa_oop_ptr() ) {
834 lrg._is_oop = 1;
835 }
836 break;
837 case Op_RegL: // Check for long or double
838 case Op_RegD:
839 lrg.set_num_regs(2);
840 // Define platform specific register pressure
841 #if defined(SPARC) || defined(ARM)
842 lrg.set_reg_pressure(2);
843 #elif defined(IA32)
844 if( ireg == Op_RegL ) {
845 lrg.set_reg_pressure(2);
846 } else {
847 lrg.set_reg_pressure(1);
848 }
849 #else
850 lrg.set_reg_pressure(1); // normally one value per register
851 #endif
852 // If this def of a double forces a mis-aligned double,
853 // flag as '_fat_proj' - really flag as allowing misalignment
854 // AND changes how we count interferences. A mis-aligned
855 // double can interfere with TWO aligned pairs, or effectively
856 // FOUR registers!
857 if (rm.is_misaligned_pair()) {
858 lrg._fat_proj = 1;
859 lrg._is_bound = 1;
860 }
861 break;
862 case Op_RegF:
863 case Op_RegI:
864 case Op_RegN:
865 case Op_RegFlags:
866 case 0: // not an ideal register
867 lrg.set_num_regs(1);
868 #ifdef SPARC
869 lrg.set_reg_pressure(2);
870 #else
871 lrg.set_reg_pressure(1);
872 #endif
873 break;
874 case Op_VecS:
875 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
876 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
877 lrg.set_num_regs(RegMask::SlotsPerVecS);
878 lrg.set_reg_pressure(1);
879 break;
880 case Op_VecD:
881 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
882 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
883 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
884 lrg.set_num_regs(RegMask::SlotsPerVecD);
885 lrg.set_reg_pressure(1);
886 break;
887 case Op_VecX:
888 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
889 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
890 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
891 lrg.set_num_regs(RegMask::SlotsPerVecX);
892 lrg.set_reg_pressure(1);
893 break;
894 case Op_VecY:
895 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
896 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
897 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
898 lrg.set_num_regs(RegMask::SlotsPerVecY);
899 lrg.set_reg_pressure(1);
900 break;
901 default:
902 ShouldNotReachHere();
903 }
904 }
905
906 // Now do the same for inputs
907 uint cnt = n->req();
908 // Setup for CISC SPILLING
909 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
910 if( UseCISCSpill && after_aggressive ) {
911 inp = n->cisc_operand();
912 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
913 // Convert operand number to edge index number
914 inp = n->as_Mach()->operand_index(inp);
915 }
916 // Prepare register mask for each input
917 for( uint k = input_edge_start; k < cnt; k++ ) {
918 uint vreg = _lrg_map.live_range_id(n->in(k));
919 if (!vreg) {
920 continue;
921 }
922
923 // If this instruction is CISC Spillable, add the flags
924 // bit to its appropriate input
925 if( UseCISCSpill && after_aggressive && inp == k ) {
926 #ifndef PRODUCT
927 if( TraceCISCSpill ) {
928 tty->print(" use_cisc_RegMask: ");
929 n->dump();
930 }
931 #endif
932 n->as_Mach()->use_cisc_RegMask();
933 }
934
935 LRG &lrg = lrgs(vreg);
936 // // Testing for floating point code shape
937 // Node *test = n->in(k);
938 // if( test->is_Mach() ) {
939 // MachNode *m = test->as_Mach();
940 // int op = m->ideal_Opcode();
941 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
942 // int zzz = 1;
943 // }
944 // }
945
946 // Limit result register mask to acceptable registers.
947 // Do not limit registers from uncommon uses before
948 // AggressiveCoalesce. This effectively pre-virtual-splits
949 // around uncommon uses of common defs.
950 const RegMask &rm = n->in_RegMask(k);
951 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) {
952 // Since we are BEFORE aggressive coalesce, leave the register
953 // mask untrimmed by the call. This encourages more coalescing.
954 // Later, AFTER aggressive, this live range will have to spill
955 // but the spiller handles slow-path calls very nicely.
956 } else {
957 lrg.AND( rm );
958 }
959
960 // Check for bound register masks
961 const RegMask &lrgmask = lrg.mask();
962 int kreg = n->in(k)->ideal_reg();
963 bool is_vect = RegMask::is_vector(kreg);
964 assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
965 is_vect || kreg == Op_RegD || kreg == Op_RegL,
966 "vector must be in vector registers");
967 if (lrgmask.is_bound(kreg))
968 lrg._is_bound = 1;
969
970 // If this use of a double forces a mis-aligned double,
971 // flag as '_fat_proj' - really flag as allowing misalignment
972 // AND changes how we count interferences. A mis-aligned
973 // double can interfere with TWO aligned pairs, or effectively
974 // FOUR registers!
975 #ifdef ASSERT
976 if (is_vect) {
977 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
978 assert(!lrg._fat_proj, "sanity");
979 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
980 }
981 #endif
982 if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) {
983 lrg._fat_proj = 1;
984 lrg._is_bound = 1;
985 }
986 // if the LRG is an unaligned pair, we will have to spill
987 // so clear the LRG's register mask if it is not already spilled
988 if (!is_vect && !n->is_SpillCopy() &&
989 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
990 lrgmask.is_misaligned_pair()) {
991 lrg.Clear();
992 }
993
994 // Check for maximum frequency value
995 if (lrg._maxfreq < block->_freq) {
996 lrg._maxfreq = block->_freq;
997 }
998
999 } // End for all allocated inputs
1000 } // end for all instructions
1001 } // end for all blocks
1002
1003 // Final per-liverange setup
1004 for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) {
1005 LRG &lrg = lrgs(i2);
1006 assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
1007 if (lrg.num_regs() > 1 && !lrg._fat_proj) {
1008 lrg.clear_to_sets();
1009 }
1010 lrg.compute_set_mask_size();
1011 if (lrg.not_free()) { // Handle case where we lose from the start
1012 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
1013 lrg._direct_conflict = 1;
1014 }
1015 lrg.set_degree(0); // no neighbors in IFG yet
1016 }
1017 }
1018
1019 // Set the was-lo-degree bit. Conservative coalescing should not change the
1020 // colorability of the graph. If any live range was of low-degree before
1021 // coalescing, it should Simplify. This call sets the was-lo-degree bit.
1022 // The bit is checked in Simplify.
1023 void PhaseChaitin::set_was_low() {
1024 #ifdef ASSERT
1025 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1026 int size = lrgs(i).num_regs();
1027 uint old_was_lo = lrgs(i)._was_lo;
1028 lrgs(i)._was_lo = 0;
1029 if( lrgs(i).lo_degree() ) {
1030 lrgs(i)._was_lo = 1; // Trivially of low degree
1031 } else { // Else check the Brigg's assertion
1032 // Brigg's observation is that the lo-degree neighbors of a
1033 // hi-degree live range will not interfere with the color choices
1034 // of said hi-degree live range. The Simplify reverse-stack-coloring
1035 // order takes care of the details. Hence you do not have to count
1036 // low-degree neighbors when determining if this guy colors.
1037 int briggs_degree = 0;
1038 IndexSet *s = _ifg->neighbors(i);
1039 IndexSetIterator elements(s);
1040 uint lidx;
1041 while((lidx = elements.next()) != 0) {
1042 if( !lrgs(lidx).lo_degree() )
1043 briggs_degree += MAX2(size,lrgs(lidx).num_regs());
1044 }
1045 if( briggs_degree < lrgs(i).degrees_of_freedom() )
1046 lrgs(i)._was_lo = 1; // Low degree via the briggs assertion
1047 }
1048 assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease");
1049 }
1050 #endif
1051 }
1052
1053 #define REGISTER_CONSTRAINED 16
1054
1055 // Compute cost/area ratio, in case we spill. Build the lo-degree list.
1056 void PhaseChaitin::cache_lrg_info( ) {
1057 Compile::TracePhase tp("chaitinCacheLRG", &timers[_t_chaitinCacheLRG]);
1058
1059 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1060 LRG &lrg = lrgs(i);
1061
1062 // Check for being of low degree: means we can be trivially colored.
1063 // Low degree, dead or must-spill guys just get to simplify right away
1064 if( lrg.lo_degree() ||
1065 !lrg.alive() ||
1066 lrg._must_spill ) {
1067 // Split low degree list into those guys that must get a
1068 // register and those that can go to register or stack.
1069 // The idea is LRGs that can go register or stack color first when
1070 // they have a good chance of getting a register. The register-only
1071 // lo-degree live ranges always get a register.
1072 OptoReg::Name hi_reg = lrg.mask().find_last_elem();
1073 if( OptoReg::is_stack(hi_reg)) { // Can go to stack?
1074 lrg._next = _lo_stk_degree;
1075 _lo_stk_degree = i;
1076 } else {
1077 lrg._next = _lo_degree;
1078 _lo_degree = i;
1079 }
1080 } else { // Else high degree
1081 lrgs(_hi_degree)._prev = i;
1082 lrg._next = _hi_degree;
1083 lrg._prev = 0;
1084 _hi_degree = i;
1085 }
1086 }
1087 }
1088
1089 // Simplify the IFG by removing LRGs of low degree that have NO copies
1090 void PhaseChaitin::Pre_Simplify( ) {
1091
1092 // Warm up the lo-degree no-copy list
1093 int lo_no_copy = 0;
1094 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1095 if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
1096 !lrgs(i).alive() ||
1097 lrgs(i)._must_spill) {
1098 lrgs(i)._next = lo_no_copy;
1099 lo_no_copy = i;
1100 }
1101 }
1102
1103 while( lo_no_copy ) {
1104 uint lo = lo_no_copy;
1105 lo_no_copy = lrgs(lo)._next;
1106 int size = lrgs(lo).num_regs();
1107
1108 // Put the simplified guy on the simplified list.
1109 lrgs(lo)._next = _simplified;
1110 _simplified = lo;
1111
1112 // Yank this guy from the IFG.
1113 IndexSet *adj = _ifg->remove_node( lo );
1114
1115 // If any neighbors' degrees fall below their number of
1116 // allowed registers, then put that neighbor on the low degree
1117 // list. Note that 'degree' can only fall and 'numregs' is
1118 // unchanged by this action. Thus the two are equal at most once,
1119 // so LRGs hit the lo-degree worklists at most once.
1120 IndexSetIterator elements(adj);
1121 uint neighbor;
1122 while ((neighbor = elements.next()) != 0) {
1123 LRG *n = &lrgs(neighbor);
1124 assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1125
1126 // Check for just becoming of-low-degree
1127 if( n->just_lo_degree() && !n->_has_copy ) {
1128 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1129 // Put on lo-degree list
1130 n->_next = lo_no_copy;
1131 lo_no_copy = neighbor;
1132 }
1133 }
1134 } // End of while lo-degree no_copy worklist not empty
1135
1136 // No more lo-degree no-copy live ranges to simplify
1137 }
1138
1139 // Simplify the IFG by removing LRGs of low degree.
1140 void PhaseChaitin::Simplify( ) {
1141 Compile::TracePhase tp("chaitinSimplify", &timers[_t_chaitinSimplify]);
1142
1143 while( 1 ) { // Repeat till simplified it all
1144 // May want to explore simplifying lo_degree before _lo_stk_degree.
1145 // This might result in more spills coloring into registers during
1146 // Select().
1147 while( _lo_degree || _lo_stk_degree ) {
1148 // If possible, pull from lo_stk first
1149 uint lo;
1150 if( _lo_degree ) {
1151 lo = _lo_degree;
1152 _lo_degree = lrgs(lo)._next;
1153 } else {
1154 lo = _lo_stk_degree;
1155 _lo_stk_degree = lrgs(lo)._next;
1156 }
1157
1158 // Put the simplified guy on the simplified list.
1159 lrgs(lo)._next = _simplified;
1160 _simplified = lo;
1161 // If this guy is "at risk" then mark his current neighbors
1162 if( lrgs(lo)._at_risk ) {
1163 IndexSetIterator elements(_ifg->neighbors(lo));
1164 uint datum;
1165 while ((datum = elements.next()) != 0) {
1166 lrgs(datum)._risk_bias = lo;
1167 }
1168 }
1169
1170 // Yank this guy from the IFG.
1171 IndexSet *adj = _ifg->remove_node( lo );
1172
1173 // If any neighbors' degrees fall below their number of
1174 // allowed registers, then put that neighbor on the low degree
1175 // list. Note that 'degree' can only fall and 'numregs' is
1176 // unchanged by this action. Thus the two are equal at most once,
1177 // so LRGs hit the lo-degree worklist at most once.
1178 IndexSetIterator elements(adj);
1179 uint neighbor;
1180 while ((neighbor = elements.next()) != 0) {
1181 LRG *n = &lrgs(neighbor);
1182 #ifdef ASSERT
1183 if( VerifyOpto || VerifyRegisterAllocator ) {
1184 assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1185 }
1186 #endif
1187
1188 // Check for just becoming of-low-degree just counting registers.
1189 // _must_spill live ranges are already on the low degree list.
1190 if( n->just_lo_degree() && !n->_must_spill ) {
1191 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1192 // Pull from hi-degree list
1193 uint prev = n->_prev;
1194 uint next = n->_next;
1195 if( prev ) lrgs(prev)._next = next;
1196 else _hi_degree = next;
1197 lrgs(next)._prev = prev;
1198 n->_next = _lo_degree;
1199 _lo_degree = neighbor;
1200 }
1201 }
1202 } // End of while lo-degree/lo_stk_degree worklist not empty
1203
1204 // Check for got everything: is hi-degree list empty?
1205 if( !_hi_degree ) break;
1206
1207 // Time to pick a potential spill guy
1208 uint lo_score = _hi_degree;
1209 double score = lrgs(lo_score).score();
1210 double area = lrgs(lo_score)._area;
1211 double cost = lrgs(lo_score)._cost;
1212 bool bound = lrgs(lo_score)._is_bound;
1213
1214 // Find cheapest guy
1215 debug_only( int lo_no_simplify=0; );
1216 for( uint i = _hi_degree; i; i = lrgs(i)._next ) {
1217 assert( !(*_ifg->_yanked)[i], "" );
1218 // It's just vaguely possible to move hi-degree to lo-degree without
1219 // going through a just-lo-degree stage: If you remove a double from
1220 // a float live range it's degree will drop by 2 and you can skip the
1221 // just-lo-degree stage. It's very rare (shows up after 5000+ methods
1222 // in -Xcomp of Java2Demo). So just choose this guy to simplify next.
1223 if( lrgs(i).lo_degree() ) {
1224 lo_score = i;
1225 break;
1226 }
1227 debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; );
1228 double iscore = lrgs(i).score();
1229 double iarea = lrgs(i)._area;
1230 double icost = lrgs(i)._cost;
1231 bool ibound = lrgs(i)._is_bound;
1232
1233 // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area
1234 // wins. Ties happen because all live ranges in question have spilled
1235 // a few times before and the spill-score adds a huge number which
1236 // washes out the low order bits. We are choosing the lesser of 2
1237 // evils; in this case pick largest area to spill.
1238 // Ties also happen when live ranges are defined and used only inside
1239 // one block. In which case their area is 0 and score set to max.
1240 // In such case choose bound live range over unbound to free registers
1241 // or with smaller cost to spill.
1242 if( iscore < score ||
1243 (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ||
1244 (iscore == score && iarea == area &&
1245 ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) {
1246 lo_score = i;
1247 score = iscore;
1248 area = iarea;
1249 cost = icost;
1250 bound = ibound;
1251 }
1252 }
1253 LRG *lo_lrg = &lrgs(lo_score);
1254 // The live range we choose for spilling is either hi-degree, or very
1255 // rarely it can be low-degree. If we choose a hi-degree live range
1256 // there better not be any lo-degree choices.
1257 assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" );
1258
1259 // Pull from hi-degree list
1260 uint prev = lo_lrg->_prev;
1261 uint next = lo_lrg->_next;
1262 if( prev ) lrgs(prev)._next = next;
1263 else _hi_degree = next;
1264 lrgs(next)._prev = prev;
1265 // Jam him on the lo-degree list, despite his high degree.
1266 // Maybe he'll get a color, and maybe he'll spill.
1267 // Only Select() will know.
1268 lrgs(lo_score)._at_risk = true;
1269 _lo_degree = lo_score;
1270 lo_lrg->_next = 0;
1271
1272 } // End of while not simplified everything
1273
1274 }
1275
1276 // Is 'reg' register legal for 'lrg'?
1277 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) {
1278 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) &&
1279 lrg.mask().Member(OptoReg::add(reg,-chunk))) {
1280 // RA uses OptoReg which represent the highest element of a registers set.
1281 // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set
1282 // in which XMMd is used by RA to represent such vectors. A double value
1283 // uses [XMM,XMMb] pairs and XMMb is used by RA for it.
1284 // The register mask uses largest bits set of overlapping register sets.
1285 // On x86 with AVX it uses 8 bits for each XMM registers set.
1286 //
1287 // The 'lrg' already has cleared-to-set register mask (done in Select()
1288 // before calling choose_color()). Passing mask.Member(reg) check above
1289 // indicates that the size (num_regs) of 'reg' set is less or equal to
1290 // 'lrg' set size.
1291 // For set size 1 any register which is member of 'lrg' mask is legal.
1292 if (lrg.num_regs()==1)
1293 return true;
1294 // For larger sets only an aligned register with the same set size is legal.
1295 int mask = lrg.num_regs()-1;
1296 if ((reg&mask) == mask)
1297 return true;
1298 }
1299 return false;
1300 }
1301
1302 // Choose a color using the biasing heuristic
1303 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1304
1305 // Check for "at_risk" LRG's
1306 uint risk_lrg = _lrg_map.find(lrg._risk_bias);
1307 if( risk_lrg != 0 ) {
1308 // Walk the colored neighbors of the "at_risk" candidate
1309 // Choose a color which is both legal and already taken by a neighbor
1310 // of the "at_risk" candidate in order to improve the chances of the
1311 // "at_risk" candidate of coloring
1312 IndexSetIterator elements(_ifg->neighbors(risk_lrg));
1313 uint datum;
1314 while ((datum = elements.next()) != 0) {
1315 OptoReg::Name reg = lrgs(datum).reg();
1316 // If this LRG's register is legal for us, choose it
1317 if (is_legal_reg(lrg, reg, chunk))
1318 return reg;
1319 }
1320 }
1321
1322 uint copy_lrg = _lrg_map.find(lrg._copy_bias);
1323 if( copy_lrg != 0 ) {
1324 // If he has a color,
1325 if( !(*(_ifg->_yanked))[copy_lrg] ) {
1326 OptoReg::Name reg = lrgs(copy_lrg).reg();
1327 // And it is legal for you,
1328 if (is_legal_reg(lrg, reg, chunk))
1329 return reg;
1330 } else if( chunk == 0 ) {
1331 // Choose a color which is legal for him
1332 RegMask tempmask = lrg.mask();
1333 tempmask.AND(lrgs(copy_lrg).mask());
1334 tempmask.clear_to_sets(lrg.num_regs());
1335 OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs());
1336 if (OptoReg::is_valid(reg))
1337 return reg;
1338 }
1339 }
1340
1341 // If no bias info exists, just go with the register selection ordering
1342 if (lrg._is_vector || lrg.num_regs() == 2) {
1343 // Find an aligned set
1344 return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk);
1345 }
1346
1347 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate
1348 // copy removal to remove many more copies, by preventing a just-assigned
1349 // register from being repeatedly assigned.
1350 OptoReg::Name reg = lrg.mask().find_first_elem();
1351 if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
1352 // This 'Remove; find; Insert' idiom is an expensive way to find the
1353 // SECOND element in the mask.
1354 lrg.Remove(reg);
1355 OptoReg::Name reg2 = lrg.mask().find_first_elem();
1356 lrg.Insert(reg);
1357 if( OptoReg::is_reg(reg2))
1358 reg = reg2;
1359 }
1360 return OptoReg::add( reg, chunk );
1361 }
1362
1363 // Choose a color in the current chunk
1364 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
1365 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
1366 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
1367
1368 if( lrg.num_regs() == 1 || // Common Case
1369 !lrg._fat_proj ) // Aligned+adjacent pairs ok
1370 // Use a heuristic to "bias" the color choice
1371 return bias_color(lrg, chunk);
1372
1373 assert(!lrg._is_vector, "should be not vector here" );
1374 assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
1375
1376 // Fat-proj case or misaligned double argument.
1377 assert(lrg.compute_mask_size() == lrg.num_regs() ||
1378 lrg.num_regs() == 2,"fat projs exactly color" );
1379 assert( !chunk, "always color in 1st chunk" );
1380 // Return the highest element in the set.
1381 return lrg.mask().find_last_elem();
1382 }
1383
1384 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted
1385 // in reverse order of removal. As long as nothing of hi-degree was yanked,
1386 // everything going back is guaranteed a color. Select that color. If some
1387 // hi-degree LRG cannot get a color then we record that we must spill.
1388 uint PhaseChaitin::Select( ) {
1389 Compile::TracePhase tp("chaitinSelect", &timers[_t_chaitinSelect]);
1390
1391 uint spill_reg = LRG::SPILL_REG;
1392 _max_reg = OptoReg::Name(0); // Past max register used
1393 while( _simplified ) {
1394 // Pull next LRG from the simplified list - in reverse order of removal
1395 uint lidx = _simplified;
1396 LRG *lrg = &lrgs(lidx);
1397 _simplified = lrg->_next;
1398
1399
1400 #ifndef PRODUCT
1401 if (trace_spilling()) {
1402 ttyLocker ttyl;
1403 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
1404 lrg->degrees_of_freedom());
1405 lrg->dump();
1406 }
1407 #endif
1408
1409 // Re-insert into the IFG
1410 _ifg->re_insert(lidx);
1411 if( !lrg->alive() ) continue;
1412 // capture allstackedness flag before mask is hacked
1413 const int is_allstack = lrg->mask().is_AllStack();
1414
1415 // Yeah, yeah, yeah, I know, I know. I can refactor this
1416 // to avoid the GOTO, although the refactored code will not
1417 // be much clearer. We arrive here IFF we have a stack-based
1418 // live range that cannot color in the current chunk, and it
1419 // has to move into the next free stack chunk.
1420 int chunk = 0; // Current chunk is first chunk
1421 retry_next_chunk:
1422
1423 // Remove neighbor colors
1424 IndexSet *s = _ifg->neighbors(lidx);
1425
1426 debug_only(RegMask orig_mask = lrg->mask();)
1427 IndexSetIterator elements(s);
1428 uint neighbor;
1429 while ((neighbor = elements.next()) != 0) {
1430 // Note that neighbor might be a spill_reg. In this case, exclusion
1431 // of its color will be a no-op, since the spill_reg chunk is in outer
1432 // space. Also, if neighbor is in a different chunk, this exclusion
1433 // will be a no-op. (Later on, if lrg runs out of possible colors in
1434 // its chunk, a new chunk of color may be tried, in which case
1435 // examination of neighbors is started again, at retry_next_chunk.)
1436 LRG &nlrg = lrgs(neighbor);
1437 OptoReg::Name nreg = nlrg.reg();
1438 // Only subtract masks in the same chunk
1439 if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) {
1440 #ifndef PRODUCT
1441 uint size = lrg->mask().Size();
1442 RegMask rm = lrg->mask();
1443 #endif
1444 lrg->SUBTRACT(nlrg.mask());
1445 #ifndef PRODUCT
1446 if (trace_spilling() && lrg->mask().Size() != size) {
1447 ttyLocker ttyl;
1448 tty->print("L%d ", lidx);
1449 rm.dump();
1450 tty->print(" intersected L%d ", neighbor);
1451 nlrg.mask().dump();
1452 tty->print(" removed ");
1453 rm.SUBTRACT(lrg->mask());
1454 rm.dump();
1455 tty->print(" leaving ");
1456 lrg->mask().dump();
1457 tty->cr();
1458 }
1459 #endif
1460 }
1461 }
1462 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1463 // Aligned pairs need aligned masks
1464 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1465 if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
1466 lrg->clear_to_sets();
1467 }
1468
1469 // Check if a color is available and if so pick the color
1470 OptoReg::Name reg = choose_color( *lrg, chunk );
1471 #ifdef SPARC
1472 debug_only(lrg->compute_set_mask_size());
1473 assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1474 #endif
1475
1476 //---------------
1477 // If we fail to color and the AllStack flag is set, trigger
1478 // a chunk-rollover event
1479 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
1480 // Bump register mask up to next stack chunk
1481 chunk += RegMask::CHUNK_SIZE;
1482 lrg->Set_All();
1483
1484 goto retry_next_chunk;
1485 }
1486
1487 //---------------
1488 // Did we get a color?
1489 else if( OptoReg::is_valid(reg)) {
1490 #ifndef PRODUCT
1491 RegMask avail_rm = lrg->mask();
1492 #endif
1493
1494 // Record selected register
1495 lrg->set_reg(reg);
1496
1497 if( reg >= _max_reg ) // Compute max register limit
1498 _max_reg = OptoReg::add(reg,1);
1499 // Fold reg back into normal space
1500 reg = OptoReg::add(reg,-chunk);
1501
1502 // If the live range is not bound, then we actually had some choices
1503 // to make. In this case, the mask has more bits in it than the colors
1504 // chosen. Restrict the mask to just what was picked.
1505 int n_regs = lrg->num_regs();
1506 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1507 if (n_regs == 1 || !lrg->_fat_proj) {
1508 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity");
1509 lrg->Clear(); // Clear the mask
1510 lrg->Insert(reg); // Set regmask to match selected reg
1511 // For vectors and pairs, also insert the low bit of the pair
1512 for (int i = 1; i < n_regs; i++)
1513 lrg->Insert(OptoReg::add(reg,-i));
1514 lrg->set_mask_size(n_regs);
1515 } else { // Else fatproj
1516 // mask must be equal to fatproj bits, by definition
1517 }
1518 #ifndef PRODUCT
1519 if (trace_spilling()) {
1520 ttyLocker ttyl;
1521 tty->print("L%d selected ", lidx);
1522 lrg->mask().dump();
1523 tty->print(" from ");
1524 avail_rm.dump();
1525 tty->cr();
1526 }
1527 #endif
1528 // Note that reg is the highest-numbered register in the newly-bound mask.
1529 } // end color available case
1530
1531 //---------------
1532 // Live range is live and no colors available
1533 else {
1534 assert( lrg->alive(), "" );
1535 assert( !lrg->_fat_proj || lrg->is_multidef() ||
1536 lrg->_def->outcnt() > 0, "fat_proj cannot spill");
1537 assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
1538
1539 // Assign the special spillreg register
1540 lrg->set_reg(OptoReg::Name(spill_reg++));
1541 // Do not empty the regmask; leave mask_size lying around
1542 // for use during Spilling
1543 #ifndef PRODUCT
1544 if( trace_spilling() ) {
1545 ttyLocker ttyl;
1546 tty->print("L%d spilling with neighbors: ", lidx);
1547 s->dump();
1548 debug_only(tty->print(" original mask: "));
1549 debug_only(orig_mask.dump());
1550 dump_lrg(lidx);
1551 }
1552 #endif
1553 } // end spill case
1554
1555 }
1556
1557 return spill_reg-LRG::SPILL_REG; // Return number of spills
1558 }
1559
1560 // Copy 'was_spilled'-edness from the source Node to the dst Node.
1561 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
1562 if( _spilled_once.test(src->_idx) ) {
1563 _spilled_once.set(dst->_idx);
1564 lrgs(_lrg_map.find(dst))._was_spilled1 = 1;
1565 if( _spilled_twice.test(src->_idx) ) {
1566 _spilled_twice.set(dst->_idx);
1567 lrgs(_lrg_map.find(dst))._was_spilled2 = 1;
1568 }
1569 }
1570 }
1571
1572 // Set the 'spilled_once' or 'spilled_twice' flag on a node.
1573 void PhaseChaitin::set_was_spilled( Node *n ) {
1574 if( _spilled_once.test_set(n->_idx) )
1575 _spilled_twice.set(n->_idx);
1576 }
1577
1578 // Convert Ideal spill instructions into proper FramePtr + offset Loads and
1579 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are.
1580 void PhaseChaitin::fixup_spills() {
1581 // This function does only cisc spill work.
1582 if( !UseCISCSpill ) return;
1583
1584 Compile::TracePhase tp("fixupSpills", &timers[_t_fixupSpills]);
1585
1586 // Grab the Frame Pointer
1587 Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr);
1588
1589 // For all blocks
1590 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1591 Block* block = _cfg.get_block(i);
1592
1593 // For all instructions in block
1594 uint last_inst = block->end_idx();
1595 for (uint j = 1; j <= last_inst; j++) {
1596 Node* n = block->get_node(j);
1597
1598 // Dead instruction???
1599 assert( n->outcnt() != 0 ||// Nothing dead after post alloc
1600 C->top() == n || // Or the random TOP node
1601 n->is_Proj(), // Or a fat-proj kill node
1602 "No dead instructions after post-alloc" );
1603
1604 int inp = n->cisc_operand();
1605 if( inp != AdlcVMDeps::Not_cisc_spillable ) {
1606 // Convert operand number to edge index number
1607 MachNode *mach = n->as_Mach();
1608 inp = mach->operand_index(inp);
1609 Node *src = n->in(inp); // Value to load or store
1610 LRG &lrg_cisc = lrgs(_lrg_map.find_const(src));
1611 OptoReg::Name src_reg = lrg_cisc.reg();
1612 // Doubles record the HIGH register of an adjacent pair.
1613 src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs());
1614 if( OptoReg::is_stack(src_reg) ) { // If input is on stack
1615 // This is a CISC Spill, get stack offset and construct new node
1616 #ifndef PRODUCT
1617 if( TraceCISCSpill ) {
1618 tty->print(" reg-instr: ");
1619 n->dump();
1620 }
1621 #endif
1622 int stk_offset = reg2offset(src_reg);
1623 // Bailout if we might exceed node limit when spilling this instruction
1624 C->check_node_count(0, "out of nodes fixing spills");
1625 if (C->failing()) return;
1626 // Transform node
1627 MachNode *cisc = mach->cisc_version(stk_offset)->as_Mach();
1628 cisc->set_req(inp,fp); // Base register is frame pointer
1629 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
1630 assert( cisc->oper_input_base() == 2, "Only adding one edge");
1631 cisc->ins_req(1,src); // Requires a memory edge
1632 }
1633 block->map_node(cisc, j); // Insert into basic block
1634 n->subsume_by(cisc, C); // Correct graph
1635 //
1636 ++_used_cisc_instructions;
1637 #ifndef PRODUCT
1638 if( TraceCISCSpill ) {
1639 tty->print(" cisc-instr: ");
1640 cisc->dump();
1641 }
1642 #endif
1643 } else {
1644 #ifndef PRODUCT
1645 if( TraceCISCSpill ) {
1646 tty->print(" using reg-instr: ");
1647 n->dump();
1648 }
1649 #endif
1650 ++_unused_cisc_instructions; // input can be on stack
1651 }
1652 }
1653
1654 } // End of for all instructions
1655
1656 } // End of for all blocks
1657 }
1658
1659 // Helper to stretch above; recursively discover the base Node for a
1660 // given derived Node. Easy for AddP-related machine nodes, but needs
1661 // to be recursive for derived Phis.
1662 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
1663 // See if already computed; if so return it
1664 if( derived_base_map[derived->_idx] )
1665 return derived_base_map[derived->_idx];
1666
1667 // See if this happens to be a base.
1668 // NOTE: we use TypePtr instead of TypeOopPtr because we can have
1669 // pointers derived from NULL! These are always along paths that
1670 // can't happen at run-time but the optimizer cannot deduce it so
1671 // we have to handle it gracefully.
1672 assert(!derived->bottom_type()->isa_narrowoop() ||
1673 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1674 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1675 // If its an OOP with a non-zero offset, then it is derived.
1676 if( tj == NULL || tj->_offset == 0 ) {
1677 derived_base_map[derived->_idx] = derived;
1678 return derived;
1679 }
1680 // Derived is NULL+offset? Base is NULL!
1681 if( derived->is_Con() ) {
1682 Node *base = _matcher.mach_null();
1683 assert(base != NULL, "sanity");
1684 if (base->in(0) == NULL) {
1685 // Initialize it once and make it shared:
1686 // set control to _root and place it into Start block
1687 // (where top() node is placed).
1688 base->init_req(0, _cfg.get_root_node());
1689 Block *startb = _cfg.get_block_for_node(C->top());
1690 uint node_pos = startb->find_node(C->top());
1691 startb->insert_node(base, node_pos);
1692 _cfg.map_node_to_block(base, startb);
1693 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
1694
1695 // The loadConP0 might have projection nodes depending on architecture
1696 // Add the projection nodes to the CFG
1697 for (DUIterator_Fast imax, i = base->fast_outs(imax); i < imax; i++) {
1698 Node* use = base->fast_out(i);
1699 if (use->is_MachProj()) {
1700 startb->insert_node(use, ++node_pos);
1701 _cfg.map_node_to_block(use, startb);
1702 new_lrg(use, maxlrg++);
1703 }
1704 }
1705 }
1706 if (_lrg_map.live_range_id(base) == 0) {
1707 new_lrg(base, maxlrg++);
1708 }
1709 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1710 derived_base_map[derived->_idx] = base;
1711 return base;
1712 }
1713
1714 // Check for AddP-related opcodes
1715 if (!derived->is_Phi()) {
1716 assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name()));
1717 Node *base = derived->in(AddPNode::Base);
1718 derived_base_map[derived->_idx] = base;
1719 return base;
1720 }
1721
1722 // Recursively find bases for Phis.
1723 // First check to see if we can avoid a base Phi here.
1724 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1725 uint i;
1726 for( i = 2; i < derived->req(); i++ )
1727 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1728 break;
1729 // Went to the end without finding any different bases?
1730 if( i == derived->req() ) { // No need for a base Phi here
1731 derived_base_map[derived->_idx] = base;
1732 return base;
1733 }
1734
1735 // Now we see we need a base-Phi here to merge the bases
1736 const Type *t = base->bottom_type();
1737 base = new PhiNode( derived->in(0), t );
1738 for( i = 1; i < derived->req(); i++ ) {
1739 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
1740 t = t->meet(base->in(i)->bottom_type());
1741 }
1742 base->as_Phi()->set_type(t);
1743
1744 // Search the current block for an existing base-Phi
1745 Block *b = _cfg.get_block_for_node(derived);
1746 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
1747 Node *phi = b->get_node(i);
1748 if( !phi->is_Phi() ) { // Found end of Phis with no match?
1749 b->insert_node(base, i); // Must insert created Phi here as base
1750 _cfg.map_node_to_block(base, b);
1751 new_lrg(base,maxlrg++);
1752 break;
1753 }
1754 // See if Phi matches.
1755 uint j;
1756 for( j = 1; j < base->req(); j++ )
1757 if( phi->in(j) != base->in(j) &&
1758 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
1759 break;
1760 if( j == base->req() ) { // All inputs match?
1761 base = phi; // Then use existing 'phi' and drop 'base'
1762 break;
1763 }
1764 }
1765
1766
1767 // Cache info for later passes
1768 derived_base_map[derived->_idx] = base;
1769 return base;
1770 }
1771
1772 // At each Safepoint, insert extra debug edges for each pair of derived value/
1773 // base pointer that is live across the Safepoint for oopmap building. The
1774 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
1775 // required edge set.
1776 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) {
1777 int must_recompute_live = false;
1778 uint maxlrg = _lrg_map.max_lrg_id();
1779 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
1780 memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
1781
1782 // For all blocks in RPO do...
1783 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1784 Block* block = _cfg.get_block(i);
1785 // Note use of deep-copy constructor. I cannot hammer the original
1786 // liveout bits, because they are needed by the following coalesce pass.
1787 IndexSet liveout(_live->live(block));
1788
1789 for (uint j = block->end_idx() + 1; j > 1; j--) {
1790 Node* n = block->get_node(j - 1);
1791
1792 // Pre-split compares of loop-phis. Loop-phis form a cycle we would
1793 // like to see in the same register. Compare uses the loop-phi and so
1794 // extends its live range BUT cannot be part of the cycle. If this
1795 // extended live range overlaps with the update of the loop-phi value
1796 // we need both alive at the same time -- which requires at least 1
1797 // copy. But because Intel has only 2-address registers we end up with
1798 // at least 2 copies, one before the loop-phi update instruction and
1799 // one after. Instead we split the input to the compare just after the
1800 // phi.
1801 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1802 Node *phi = n->in(1);
1803 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1804 Block *phi_block = _cfg.get_block_for_node(phi);
1805 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
1806 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1807 Node *spill = new MachSpillCopyNode(MachSpillCopyNode::LoopPhiInput, phi, *mask, *mask);
1808 insert_proj( phi_block, 1, spill, maxlrg++ );
1809 n->set_req(1,spill);
1810 must_recompute_live = true;
1811 }
1812 }
1813 }
1814
1815 // Get value being defined
1816 uint lidx = _lrg_map.live_range_id(n);
1817 // Ignore the occasional brand-new live range
1818 if (lidx && lidx < _lrg_map.max_lrg_id()) {
1819 // Remove from live-out set
1820 liveout.remove(lidx);
1821
1822 // Copies do not define a new value and so do not interfere.
1823 // Remove the copies source from the liveout set before interfering.
1824 uint idx = n->is_Copy();
1825 if (idx) {
1826 liveout.remove(_lrg_map.live_range_id(n->in(idx)));
1827 }
1828 }
1829
1830 // Found a safepoint?
1831 JVMState *jvms = n->jvms();
1832 if( jvms ) {
1833 // Now scan for a live derived pointer
1834 IndexSetIterator elements(&liveout);
1835 uint neighbor;
1836 while ((neighbor = elements.next()) != 0) {
1837 // Find reaching DEF for base and derived values
1838 // This works because we are still in SSA during this call.
1839 Node *derived = lrgs(neighbor)._def;
1840 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1841 assert(!derived->bottom_type()->isa_narrowoop() ||
1842 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1843 // If its an OOP with a non-zero offset, then it is derived.
1844 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
1845 Node *base = find_base_for_derived(derived_base_map, derived, maxlrg);
1846 assert(base->_idx < _lrg_map.size(), "");
1847 // Add reaching DEFs of derived pointer and base pointer as a
1848 // pair of inputs
1849 n->add_req(derived);
1850 n->add_req(base);
1851
1852 // See if the base pointer is already live to this point.
1853 // Since I'm working on the SSA form, live-ness amounts to
1854 // reaching def's. So if I find the base's live range then
1855 // I know the base's def reaches here.
1856 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
1857 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
1858 (_lrg_map.live_range_id(base) > 0) && // not a constant
1859 _cfg.get_block_for_node(base) != block) { // base not def'd in blk)
1860 // Base pointer is not currently live. Since I stretched
1861 // the base pointer to here and it crosses basic-block
1862 // boundaries, the global live info is now incorrect.
1863 // Recompute live.
1864 must_recompute_live = true;
1865 } // End of if base pointer is not live to debug info
1866 }
1867 } // End of scan all live data for derived ptrs crossing GC point
1868 } // End of if found a GC point
1869
1870 // Make all inputs live
1871 if (!n->is_Phi()) { // Phi function uses come from prior block
1872 for (uint k = 1; k < n->req(); k++) {
1873 uint lidx = _lrg_map.live_range_id(n->in(k));
1874 if (lidx < _lrg_map.max_lrg_id()) {
1875 liveout.insert(lidx);
1876 }
1877 }
1878 }
1879
1880 } // End of forall instructions in block
1881 liveout.clear(); // Free the memory used by liveout.
1882
1883 } // End of forall blocks
1884 _lrg_map.set_max_lrg_id(maxlrg);
1885
1886 // If I created a new live range I need to recompute live
1887 if (maxlrg != _ifg->_maxlrg) {
1888 must_recompute_live = true;
1889 }
1890
1891 return must_recompute_live != 0;
1892 }
1893
1894 // Extend the node to LRG mapping
1895
1896 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
1897 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
1898 }
1899
1900 #ifndef PRODUCT
1901 void PhaseChaitin::dump(const Node *n) const {
1902 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
1903 tty->print("L%d",r);
1904 if (r && n->Opcode() != Op_Phi) {
1905 if( _node_regs ) { // Got a post-allocation copy of allocation?
1906 tty->print("[");
1907 OptoReg::Name second = get_reg_second(n);
1908 if( OptoReg::is_valid(second) ) {
1909 if( OptoReg::is_reg(second) )
1910 tty->print("%s:",Matcher::regName[second]);
1911 else
1912 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
1913 }
1914 OptoReg::Name first = get_reg_first(n);
1915 if( OptoReg::is_reg(first) )
1916 tty->print("%s]",Matcher::regName[first]);
1917 else
1918 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
1919 } else
1920 n->out_RegMask().dump();
1921 }
1922 tty->print("/N%d\t",n->_idx);
1923 tty->print("%s === ", n->Name());
1924 uint k;
1925 for (k = 0; k < n->req(); k++) {
1926 Node *m = n->in(k);
1927 if (!m) {
1928 tty->print("_ ");
1929 }
1930 else {
1931 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1932 tty->print("L%d",r);
1933 // Data MultiNode's can have projections with no real registers.
1934 // Don't die while dumping them.
1935 int op = n->Opcode();
1936 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
1937 if( _node_regs ) {
1938 tty->print("[");
1939 OptoReg::Name second = get_reg_second(n->in(k));
1940 if( OptoReg::is_valid(second) ) {
1941 if( OptoReg::is_reg(second) )
1942 tty->print("%s:",Matcher::regName[second]);
1943 else
1944 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
1945 reg2offset_unchecked(second));
1946 }
1947 OptoReg::Name first = get_reg_first(n->in(k));
1948 if( OptoReg::is_reg(first) )
1949 tty->print("%s]",Matcher::regName[first]);
1950 else
1951 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
1952 reg2offset_unchecked(first));
1953 } else
1954 n->in_RegMask(k).dump();
1955 }
1956 tty->print("/N%d ",m->_idx);
1957 }
1958 }
1959 if( k < n->len() && n->in(k) ) tty->print("| ");
1960 for( ; k < n->len(); k++ ) {
1961 Node *m = n->in(k);
1962 if(!m) {
1963 break;
1964 }
1965 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1966 tty->print("L%d",r);
1967 tty->print("/N%d ",m->_idx);
1968 }
1969 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
1970 else n->dump_spec(tty);
1971 if( _spilled_once.test(n->_idx ) ) {
1972 tty->print(" Spill_1");
1973 if( _spilled_twice.test(n->_idx ) )
1974 tty->print(" Spill_2");
1975 }
1976 tty->print("\n");
1977 }
1978
1979 void PhaseChaitin::dump(const Block *b) const {
1980 b->dump_head(&_cfg);
1981
1982 // For all instructions
1983 for( uint j = 0; j < b->number_of_nodes(); j++ )
1984 dump(b->get_node(j));
1985 // Print live-out info at end of block
1986 if( _live ) {
1987 tty->print("Liveout: ");
1988 IndexSet *live = _live->live(b);
1989 IndexSetIterator elements(live);
1990 tty->print("{");
1991 uint i;
1992 while ((i = elements.next()) != 0) {
1993 tty->print("L%d ", _lrg_map.find_const(i));
1994 }
1995 tty->print_cr("}");
1996 }
1997 tty->print("\n");
1998 }
1999
2000 void PhaseChaitin::dump() const {
2001 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n",
2002 _matcher._new_SP, _framesize );
2003
2004 // For all blocks
2005 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2006 dump(_cfg.get_block(i));
2007 }
2008 // End of per-block dump
2009 tty->print("\n");
2010
2011 if (!_ifg) {
2012 tty->print("(No IFG.)\n");
2013 return;
2014 }
2015
2016 // Dump LRG array
2017 tty->print("--- Live RanGe Array ---\n");
2018 for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) {
2019 tty->print("L%d: ",i2);
2020 if (i2 < _ifg->_maxlrg) {
2021 lrgs(i2).dump();
2022 }
2023 else {
2024 tty->print_cr("new LRG");
2025 }
2026 }
2027 tty->cr();
2028
2029 // Dump lo-degree list
2030 tty->print("Lo degree: ");
2031 for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next )
2032 tty->print("L%d ",i3);
2033 tty->cr();
2034
2035 // Dump lo-stk-degree list
2036 tty->print("Lo stk degree: ");
2037 for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next )
2038 tty->print("L%d ",i4);
2039 tty->cr();
2040
2041 // Dump lo-degree list
2042 tty->print("Hi degree: ");
2043 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
2044 tty->print("L%d ",i5);
2045 tty->cr();
2046 }
2047
2048 void PhaseChaitin::dump_degree_lists() const {
2049 // Dump lo-degree list
2050 tty->print("Lo degree: ");
2051 for( uint i = _lo_degree; i; i = lrgs(i)._next )
2052 tty->print("L%d ",i);
2053 tty->cr();
2054
2055 // Dump lo-stk-degree list
2056 tty->print("Lo stk degree: ");
2057 for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next )
2058 tty->print("L%d ",i2);
2059 tty->cr();
2060
2061 // Dump lo-degree list
2062 tty->print("Hi degree: ");
2063 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
2064 tty->print("L%d ",i3);
2065 tty->cr();
2066 }
2067
2068 void PhaseChaitin::dump_simplified() const {
2069 tty->print("Simplified: ");
2070 for( uint i = _simplified; i; i = lrgs(i)._next )
2071 tty->print("L%d ",i);
2072 tty->cr();
2073 }
2074
2075 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) {
2076 if ((int)reg < 0)
2077 sprintf(buf, "<OptoReg::%d>", (int)reg);
2078 else if (OptoReg::is_reg(reg))
2079 strcpy(buf, Matcher::regName[reg]);
2080 else
2081 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
2082 pc->reg2offset(reg));
2083 return buf+strlen(buf);
2084 }
2085
2086 // Dump a register name into a buffer. Be intelligent if we get called
2087 // before allocation is complete.
2088 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const {
2089 if( !this ) { // Not got anything?
2090 sprintf(buf,"N%d",n->_idx); // Then use Node index
2091 } else if( _node_regs ) {
2092 // Post allocation, use direct mappings, no LRG info available
2093 print_reg( get_reg_first(n), this, buf );
2094 } else {
2095 uint lidx = _lrg_map.find_const(n); // Grab LRG number
2096 if( !_ifg ) {
2097 sprintf(buf,"L%d",lidx); // No register binding yet
2098 } else if( !lidx ) { // Special, not allocated value
2099 strcpy(buf,"Special");
2100 } else {
2101 if (lrgs(lidx)._is_vector) {
2102 if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs()))
2103 print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register
2104 else
2105 sprintf(buf,"L%d",lidx); // No register binding yet
2106 } else if( (lrgs(lidx).num_regs() == 1)
2107 ? lrgs(lidx).mask().is_bound1()
2108 : lrgs(lidx).mask().is_bound_pair() ) {
2109 // Hah! We have a bound machine register
2110 print_reg( lrgs(lidx).reg(), this, buf );
2111 } else {
2112 sprintf(buf,"L%d",lidx); // No register binding yet
2113 }
2114 }
2115 }
2116 return buf+strlen(buf);
2117 }
2118
2119 void PhaseChaitin::dump_for_spill_split_recycle() const {
2120 if( WizardMode && (PrintCompilation || PrintOpto) ) {
2121 // Display which live ranges need to be split and the allocator's state
2122 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
2123 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) {
2124 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
2125 tty->print("L%d: ", bidx);
2126 lrgs(bidx).dump();
2127 }
2128 }
2129 tty->cr();
2130 dump();
2131 }
2132 }
2133
2134 void PhaseChaitin::dump_frame() const {
2135 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
2136 const TypeTuple *domain = C->tf()->domain();
2137 const int argcnt = domain->cnt() - TypeFunc::Parms;
2138
2139 // Incoming arguments in registers dump
2140 for( int k = 0; k < argcnt; k++ ) {
2141 OptoReg::Name parmreg = _matcher._parm_regs[k].first();
2142 if( OptoReg::is_reg(parmreg)) {
2143 const char *reg_name = OptoReg::regname(parmreg);
2144 tty->print("#r%3.3d %s", parmreg, reg_name);
2145 parmreg = _matcher._parm_regs[k].second();
2146 if( OptoReg::is_reg(parmreg)) {
2147 tty->print(":%s", OptoReg::regname(parmreg));
2148 }
2149 tty->print(" : parm %d: ", k);
2150 domain->field_at(k + TypeFunc::Parms)->dump();
2151 tty->cr();
2152 }
2153 }
2154
2155 // Check for un-owned padding above incoming args
2156 OptoReg::Name reg = _matcher._new_SP;
2157 if( reg > _matcher._in_arg_limit ) {
2158 reg = OptoReg::add(reg, -1);
2159 tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg));
2160 }
2161
2162 // Incoming argument area dump
2163 OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots());
2164 while( reg > begin_in_arg ) {
2165 reg = OptoReg::add(reg, -1);
2166 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2167 int j;
2168 for( j = 0; j < argcnt; j++) {
2169 if( _matcher._parm_regs[j].first() == reg ||
2170 _matcher._parm_regs[j].second() == reg ) {
2171 tty->print("parm %d: ",j);
2172 domain->field_at(j + TypeFunc::Parms)->dump();
2173 tty->cr();
2174 break;
2175 }
2176 }
2177 if( j >= argcnt )
2178 tty->print_cr("HOLE, owned by SELF");
2179 }
2180
2181 // Old outgoing preserve area
2182 while( reg > _matcher._old_SP ) {
2183 reg = OptoReg::add(reg, -1);
2184 tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg));
2185 }
2186
2187 // Old SP
2188 tty->print_cr("# -- Old %s -- Framesize: %d --",fp,
2189 reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
2190
2191 // Preserve area dump
2192 int fixed_slots = C->fixed_slots();
2193 OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots());
2194 OptoReg::Name return_addr = _matcher.return_addr();
2195
2196 reg = OptoReg::add(reg, -1);
2197 while (OptoReg::is_stack(reg)) {
2198 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2199 if (return_addr == reg) {
2200 tty->print_cr("return address");
2201 } else if (reg >= begin_in_preserve) {
2202 // Preserved slots are present on x86
2203 if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word))
2204 tty->print_cr("saved fp register");
2205 else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) &&
2206 VerifyStackAtCalls)
2207 tty->print_cr("0xBADB100D +VerifyStackAtCalls");
2208 else
2209 tty->print_cr("in_preserve");
2210 } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) {
2211 tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
2212 } else {
2213 tty->print_cr("pad2, stack alignment");
2214 }
2215 reg = OptoReg::add(reg, -1);
2216 }
2217
2218 // Spill area dump
2219 reg = OptoReg::add(_matcher._new_SP, _framesize );
2220 while( reg > _matcher._out_arg_limit ) {
2221 reg = OptoReg::add(reg, -1);
2222 tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg));
2223 }
2224
2225 // Outgoing argument area dump
2226 while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) {
2227 reg = OptoReg::add(reg, -1);
2228 tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg));
2229 }
2230
2231 // Outgoing new preserve area
2232 while( reg > _matcher._new_SP ) {
2233 reg = OptoReg::add(reg, -1);
2234 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
2235 }
2236 tty->print_cr("#");
2237 }
2238
2239 void PhaseChaitin::dump_bb( uint pre_order ) const {
2240 tty->print_cr("---dump of B%d---",pre_order);
2241 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2242 Block* block = _cfg.get_block(i);
2243 if (block->_pre_order == pre_order) {
2244 dump(block);
2245 }
2246 }
2247 }
2248
2249 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const {
2250 tty->print_cr("---dump of L%d---",lidx);
2251
2252 if (_ifg) {
2253 if (lidx >= _lrg_map.max_lrg_id()) {
2254 tty->print("Attempt to print live range index beyond max live range.\n");
2255 return;
2256 }
2257 tty->print("L%d: ",lidx);
2258 if (lidx < _ifg->_maxlrg) {
2259 lrgs(lidx).dump();
2260 } else {
2261 tty->print_cr("new LRG");
2262 }
2263 }
2264 if( _ifg && lidx < _ifg->_maxlrg) {
2265 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
2266 _ifg->neighbors(lidx)->dump();
2267 tty->cr();
2268 }
2269 // For all blocks
2270 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2271 Block* block = _cfg.get_block(i);
2272 int dump_once = 0;
2273
2274 // For all instructions
2275 for( uint j = 0; j < block->number_of_nodes(); j++ ) {
2276 Node *n = block->get_node(j);
2277 if (_lrg_map.find_const(n) == lidx) {
2278 if (!dump_once++) {
2279 tty->cr();
2280 block->dump_head(&_cfg);
2281 }
2282 dump(n);
2283 continue;
2284 }
2285 if (!defs_only) {
2286 uint cnt = n->req();
2287 for( uint k = 1; k < cnt; k++ ) {
2288 Node *m = n->in(k);
2289 if (!m) {
2290 continue; // be robust in the dumper
2291 }
2292 if (_lrg_map.find_const(m) == lidx) {
2293 if (!dump_once++) {
2294 tty->cr();
2295 block->dump_head(&_cfg);
2296 }
2297 dump(n);
2298 }
2299 }
2300 }
2301 }
2302 } // End of per-block dump
2303 tty->cr();
2304 }
2305 #endif // not PRODUCT
2306
2307 int PhaseChaitin::_final_loads = 0;
2308 int PhaseChaitin::_final_stores = 0;
2309 int PhaseChaitin::_final_memoves= 0;
2310 int PhaseChaitin::_final_copies = 0;
2311 double PhaseChaitin::_final_load_cost = 0;
2312 double PhaseChaitin::_final_store_cost = 0;
2313 double PhaseChaitin::_final_memove_cost= 0;
2314 double PhaseChaitin::_final_copy_cost = 0;
2315 int PhaseChaitin::_conserv_coalesce = 0;
2316 int PhaseChaitin::_conserv_coalesce_pair = 0;
2317 int PhaseChaitin::_conserv_coalesce_trie = 0;
2318 int PhaseChaitin::_conserv_coalesce_quad = 0;
2319 int PhaseChaitin::_post_alloc = 0;
2320 int PhaseChaitin::_lost_opp_pp_coalesce = 0;
2321 int PhaseChaitin::_lost_opp_cflow_coalesce = 0;
2322 int PhaseChaitin::_used_cisc_instructions = 0;
2323 int PhaseChaitin::_unused_cisc_instructions = 0;
2324 int PhaseChaitin::_allocator_attempts = 0;
2325 int PhaseChaitin::_allocator_successes = 0;
2326
2327 #ifndef PRODUCT
2328 uint PhaseChaitin::_high_pressure = 0;
2329 uint PhaseChaitin::_low_pressure = 0;
2330
2331 void PhaseChaitin::print_chaitin_statistics() {
2332 tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies);
2333 tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost);
2334 tty->print_cr("Adjusted spill cost = %7.0f.",
2335 _final_load_cost*4.0 + _final_store_cost * 2.0 +
2336 _final_copy_cost*1.0 + _final_memove_cost*12.0);
2337 tty->print("Conservatively coalesced %d copies, %d pairs",
2338 _conserv_coalesce, _conserv_coalesce_pair);
2339 if( _conserv_coalesce_trie || _conserv_coalesce_quad )
2340 tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad);
2341 tty->print_cr(", %d post alloc.", _post_alloc);
2342 if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce )
2343 tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.",
2344 _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce );
2345 if( _used_cisc_instructions || _unused_cisc_instructions )
2346 tty->print_cr("Used cisc instruction %d, remained in register %d",
2347 _used_cisc_instructions, _unused_cisc_instructions);
2348 if( _allocator_successes != 0 )
2349 tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes);
2350 tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure);
2351 }
2352 #endif // not PRODUCT